drm/amdgpu: set vm size and block size by individual gmc by default (v3)

By default, the value is set by individual gmc.
if a specific value is input, it overrides the global value for all

v2: create helper funcs
v3: update gmc9 APU's num_level athough it may be updated in the future.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8 files changed, 66 insertions, 40 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 831c2bfd2072..483660742f75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1040,35 +1040,31 @@ static bool amdgpu_check_pot_argument(int arg)
         return (arg & (arg - 1)) == 0;
 }
 
-static void amdgpu_get_block_size(struct amdgpu_device *adev)
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
 {
         /* defines number of bits in page table versus page directory,
          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
          * page table and the remaining bits are in the page directory */
-        if (amdgpu_vm_block_size == -1) {
-
-                /* Total bits covered by PD + PTs */
-                unsigned bits = ilog2(amdgpu_vm_size) + 18;
-
-                /* Make sure the PD is 4K in size up to 8GB address space.
-                   Above that split equal between PD and PTs */
-                if (amdgpu_vm_size <= 8)
-                        amdgpu_vm_block_size = bits - 9;
-                else
-                        amdgpu_vm_block_size = (bits + 3) / 2;
+        if (amdgpu_vm_block_size == -1)
+                return;
 
-        } else if (amdgpu_vm_block_size < 9) {
+        if (amdgpu_vm_block_size < 9) {
                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
                          amdgpu_vm_block_size);
-                amdgpu_vm_block_size = 9;
+                goto def_value;
         }
 
         if (amdgpu_vm_block_size > 24 ||
             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
                          amdgpu_vm_block_size);
-                amdgpu_vm_block_size = 9;
+                goto def_value;
         }
+
+        return;
+
+def_value:
+        amdgpu_vm_block_size = -1;
 }
 
 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
@@ -1097,8 +1093,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev)
         return;
 
 def_value:
-        amdgpu_vm_size = 8;
-        dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
+        amdgpu_vm_size = -1;
 }
 
 /**
@@ -1132,7 +1127,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
 
         amdgpu_check_vm_size(adev);
 
-        amdgpu_get_block_size(adev);
+        amdgpu_check_block_size(adev);
 
         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
             !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 400917fd7486..4e0f7d2d87f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -86,7 +86,7 @@ int amdgpu_runtime_pm = -1;
 unsigned amdgpu_ip_block_mask = 0xffffffff;
 int amdgpu_bapm = -1;
 int amdgpu_deep_color = 0;
-int amdgpu_vm_size = 64;
+int amdgpu_vm_size = -1;
 int amdgpu_vm_block_size = -1;
 int amdgpu_vm_fault_stop = 0;
 int amdgpu_vm_debug = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 2895d9d86f29..7ed5302b511a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2064,6 +2064,44 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
         }
 }
 
+static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
+{
+        /* Total bits covered by PD + PTs */
+        unsigned bits = ilog2(vm_size) + 18;
+
+        /* Make sure the PD is 4K in size up to 8GB address space.
+           Above that split equal between PD and PTs */
+        if (vm_size <= 8)
+                return (bits - 9);
+        else
+                return ((bits + 3) / 2);
+}
+
+/**
+ * amdgpu_vm_adjust_size - adjust vm size and block size
+ *
+ * @adev: amdgpu_device pointer
+ * @vm_size: the default vm size if it's set auto
+ */
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size)
+{
+        /* adjust vm size firstly */
+        if (amdgpu_vm_size == -1)
+                adev->vm_manager.vm_size = vm_size;
+        else
+                adev->vm_manager.vm_size = amdgpu_vm_size;
+
+        /* block size depends on vm size */
+        if (amdgpu_vm_block_size == -1)
+                adev->vm_manager.block_size =
+                        amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
+        else
+                adev->vm_manager.block_size = amdgpu_vm_block_size;
+
+        DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
+                adev->vm_manager.vm_size, adev->vm_manager.block_size);
+}
+
 /**
  * amdgpu_vm_init - initialize a vm instance
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 02b0dd3b135f..d9e57290dc71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -234,5 +234,6 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
                                 uint64_t saddr, uint64_t size);
 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
                       struct amdgpu_bo_va *bo_va);
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 8f18d14f8eda..631aef38126d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -849,13 +849,9 @@ static int gmc_v6_0_sw_init(void *handle)
         if (r)
                 return r;
 
-        adev->vm_manager.vm_size = amdgpu_vm_size;
-        adev->vm_manager.block_size = amdgpu_vm_block_size;
+        amdgpu_vm_adjust_size(adev, 64);
         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
-        DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
-                adev->vm_manager.vm_size, adev->vm_manager.block_size);
-
         adev->mc.mc_mask = 0xffffffffffULL;
 
         adev->need_dma32 = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index b86b454197f8..92abe12d92bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1003,13 +1003,9 @@ static int gmc_v7_0_sw_init(void *handle)
          * Currently set to 4GB ((1 << 20) 4k pages).
          * Max GPUVM size for cayman and SI is 40 bits.
          */
-        adev->vm_manager.vm_size = amdgpu_vm_size;
-        adev->vm_manager.block_size = amdgpu_vm_block_size;
+        amdgpu_vm_adjust_size(adev, 64);
         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
-        DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
-                adev->vm_manager.vm_size, adev->vm_manager.block_size);
-
         /* Set the internal MC address mask
          * This is the max address of the GPU's
          * internal address space.
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 108a20e832cf..f2ccefc66fd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1087,13 +1087,9 @@ static int gmc_v8_0_sw_init(void *handle)
          * Currently set to 4GB ((1 << 20) 4k pages).
          * Max GPUVM size for cayman and SI is 40 bits.
          */
-        adev->vm_manager.vm_size = amdgpu_vm_size;
-        adev->vm_manager.block_size = amdgpu_vm_block_size;
+        amdgpu_vm_adjust_size(adev, 64);
         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
-        DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
-                adev->vm_manager.vm_size, adev->vm_manager.block_size);
-
         /* Set the internal MC address mask
          * This is the max address of the GPU's
          * internal address space.
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6329be81f260..3b045e0b114e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -520,7 +520,12 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
          * amdkfd will use VMIDs 8-15
          */
         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
-        adev->vm_manager.num_level = 3;
+
+        /* TODO: fix num_level for APU when updating vm size and block size */
+        if (adev->flags & AMD_IS_APU)
+                adev->vm_manager.num_level = 1;
+        else
+                adev->vm_manager.num_level = 3;
         amdgpu_vm_manager_init(adev);
 
         /* base offset of vram pages */
@@ -552,8 +557,7 @@ static int gmc_v9_0_sw_init(void *handle)
 
         if (adev->flags & AMD_IS_APU) {
                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
-                adev->vm_manager.vm_size = amdgpu_vm_size;
-                adev->vm_manager.block_size = amdgpu_vm_block_size;
+                amdgpu_vm_adjust_size(adev, 64);
         } else {
                 /* XXX Don't know how to get VRAM type yet. */
                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
@@ -564,11 +568,11 @@ static int gmc_v9_0_sw_init(void *handle)
                  */
                 adev->vm_manager.vm_size = 1U << 18;
                 adev->vm_manager.block_size = 9;
+                DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
+                                adev->vm_manager.vm_size,
+                                adev->vm_manager.block_size);
         }
 
-        DRM_INFO("vm size is %llu GB, block size is %d-bit\n",
-                adev->vm_manager.vm_size, adev->vm_manager.block_size);
-
         /* This interrupt is VMC page fault.*/
         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
                                 &adev->mc.vm_fault);