aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorRafał Miłecki <zajec5@gmail.com>2016-04-22 07:23:13 -0400
committerBoris Brezillon <boris.brezillon@free-electrons.com>2016-05-05 17:55:14 -0400
commitba4f46b28f87396d3270d05d8d0e08467471b7fb (patch)
tree09a1a2c22d26e24367bb35cea61bb014a7137047
parente4225ae8234cf5548c38dc887b233ad1d45b4d53 (diff)
mtd: nand: add support for "nand-ecc-algo" DT property
So far it was only possible to specify ECC algorithm using "soft" and "soft_bch" values of nand-ecc-mode prop. There wasn't a way to specify it for a hardware ECC mode. Now that we have independent field in NAND subsystem for storing info about ECC algorithm we may also add support for this new DT property. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-rw-r--r--Documentation/devicetree/bindings/mtd/nand.txt2
-rw-r--r--drivers/mtd/nand/nand_base.c20
2 files changed, 15 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
index a17662b1dfcb..5ac4ab75ea0c 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -22,6 +22,8 @@ Optional NAND chip properties:
22- nand-ecc-mode : String, operation mode of the NAND ecc mode. 22- nand-ecc-mode : String, operation mode of the NAND ecc mode.
23 Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", 23 Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
24 "soft_bch". 24 "soft_bch".
25- nand-ecc-algo: string, algorithm of NAND ECC.
26 Supported values are: "hamming", "bch".
25- nand-bus-width : 8 or 16 bus width if not present 8 27- nand-bus-width : 8 or 16 bus width if not present 8
26- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false 28- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
27 29
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index c9d6230eab08..c26f1852787b 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4003,17 +4003,23 @@ static int of_get_nand_ecc_mode(struct device_node *np)
4003 return -ENODEV; 4003 return -ENODEV;
4004} 4004}
4005 4005
4006static const char * const nand_ecc_algos[] = {
4007 [NAND_ECC_HAMMING] = "hamming",
4008 [NAND_ECC_BCH] = "bch",
4009};
4010
4006static int of_get_nand_ecc_algo(struct device_node *np) 4011static int of_get_nand_ecc_algo(struct device_node *np)
4007{ 4012{
4008 const char *pm; 4013 const char *pm;
4009 int err; 4014 int err, i;
4010 4015
4011 /* 4016 err = of_property_read_string(np, "nand-ecc-algo", &pm);
4012 * TODO: Read ECC algo OF property and map it to enum nand_ecc_algo. 4017 if (!err) {
4013 * It's not implemented yet as currently NAND subsystem ignores 4018 for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
4014 * algorithm explicitly set this way. Once it's handled we should 4019 if (!strcasecmp(pm, nand_ecc_algos[i]))
4015 * document & support new property. 4020 return i;
4016 */ 4021 return -ENODEV;
4022 }
4017 4023
4018 /* 4024 /*
4019 * For backward compatibility we also read "nand-ecc-mode" checking 4025 * For backward compatibility we also read "nand-ecc-mode" checking