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authorBai Ping <ping.bai@nxp.com>2018-01-06 09:25:53 -0500
committerLinus Walleij <linus.walleij@linaro.org>2018-01-09 08:59:17 -0500
commitba33f4f42e968854d8367fc4e55b07f835c55832 (patch)
tree64e444c16a52b55d283c3772f8bf342d1596e8aa
parentce8dc0943357a5d10b05dcf0556b537c1d7b8b1f (diff)
pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers are available in a separate IOMUXC_SNVS module. Add support for the IOMUXC_SNVS module to the i.MX 6UL pinctrl driver. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt3
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6ul.c52
2 files changed, 50 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
index a81bbf37ed66..7ca4f6118d9a 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
@@ -4,7 +4,8 @@ Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage. 4and usage.
5 5
6Required properties: 6Required properties:
7- compatible: "fsl,imx6ul-iomuxc" 7- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
8 "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
8- fsl,pins: each entry consists of 6 integers and represents the mux and config 9- fsl,pins: each entry consists of 6 integers and represents the mux and config
9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
10 input_val> are specified using a PIN_FUNC_ID macro, which can be found in 11 input_val> are specified using a PIN_FUNC_ID macro, which can be found in
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
index 1aeb840aae1d..4580717ade19 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
@@ -150,6 +150,21 @@ enum imx6ul_pads {
150 MX6UL_PAD_CSI_DATA07 = 128, 150 MX6UL_PAD_CSI_DATA07 = 128,
151}; 151};
152 152
153enum imx6ull_lpsr_pads {
154 MX6ULL_PAD_BOOT_MODE0 = 0,
155 MX6ULL_PAD_BOOT_MODE1 = 1,
156 MX6ULL_PAD_SNVS_TAMPER0 = 2,
157 MX6ULL_PAD_SNVS_TAMPER1 = 3,
158 MX6ULL_PAD_SNVS_TAMPER2 = 4,
159 MX6ULL_PAD_SNVS_TAMPER3 = 5,
160 MX6ULL_PAD_SNVS_TAMPER4 = 6,
161 MX6ULL_PAD_SNVS_TAMPER5 = 7,
162 MX6ULL_PAD_SNVS_TAMPER6 = 8,
163 MX6ULL_PAD_SNVS_TAMPER7 = 9,
164 MX6ULL_PAD_SNVS_TAMPER8 = 10,
165 MX6ULL_PAD_SNVS_TAMPER9 = 11,
166};
167
153/* Pad names for the pinmux subsystem */ 168/* Pad names for the pinmux subsystem */
154static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = { 169static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
155 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0), 170 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
@@ -283,20 +298,49 @@ static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
283 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07), 298 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
284}; 299};
285 300
286static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = { 301/* pad for i.MX6ULL lpsr pinmux */
302static const struct pinctrl_pin_desc imx6ull_snvs_pinctrl_pads[] = {
303 IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE0),
304 IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE1),
305 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER0),
306 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER1),
307 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER2),
308 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER3),
309 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER4),
310 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER5),
311 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER6),
312 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER7),
313 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER8),
314 IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER9),
315};
316
317static const struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
287 .pins = imx6ul_pinctrl_pads, 318 .pins = imx6ul_pinctrl_pads,
288 .npins = ARRAY_SIZE(imx6ul_pinctrl_pads), 319 .npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
289 .gpr_compatible = "fsl,imx6ul-iomuxc-gpr", 320 .gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
290}; 321};
291 322
292static struct of_device_id imx6ul_pinctrl_of_match[] = { 323static const struct imx_pinctrl_soc_info imx6ull_snvs_pinctrl_info = {
293 { .compatible = "fsl,imx6ul-iomuxc", }, 324 .pins = imx6ull_snvs_pinctrl_pads,
325 .npins = ARRAY_SIZE(imx6ull_snvs_pinctrl_pads),
326 .flags = ZERO_OFFSET_VALID,
327};
328
329static const struct of_device_id imx6ul_pinctrl_of_match[] = {
330 { .compatible = "fsl,imx6ul-iomuxc", .data = &imx6ul_pinctrl_info, },
331 { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, },
294 { /* sentinel */ } 332 { /* sentinel */ }
295}; 333};
296 334
297static int imx6ul_pinctrl_probe(struct platform_device *pdev) 335static int imx6ul_pinctrl_probe(struct platform_device *pdev)
298{ 336{
299 return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info); 337 const struct imx_pinctrl_soc_info *pinctrl_info;
338
339 pinctrl_info = of_device_get_match_data(&pdev->dev);
340 if (!pinctrl_info)
341 return -ENODEV;
342
343 return imx_pinctrl_probe(pdev, pinctrl_info);
300} 344}
301 345
302static struct platform_driver imx6ul_pinctrl_driver = { 346static struct platform_driver imx6ul_pinctrl_driver = {