aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorHeiko Stübner <heiko@sntech.de>2014-07-02 20:02:37 -0400
committerMike Turquette <mturquette@linaro.org>2014-07-13 15:17:10 -0400
commitb9e4ba541607e6ee9c6c8493f51198fe3af03aec (patch)
tree886b115b0e14b3224dc196ebb5755946a40ee0d3
parent5775b82e74d1b307b7dab670993b6b838c92f786 (diff)
clk: rockchip: add clock controller for rk3288
Add the clock tree definition for the new rk3288 SoC. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c717
-rw-r--r--drivers/clk/rockchip/clk.h9
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h278
4 files changed, 1005 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 3eebf72fe91f..ee6b077381e1 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -8,3 +8,4 @@ obj-y += clk-pll.o
8obj-$(CONFIG_RESET_CONTROLLER) += softrst.o 8obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
9 9
10obj-y += clk-rk3188.o 10obj-y += clk-rk3188.o
11obj-y += clk-rk3288.o
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
new file mode 100644
index 000000000000..0d8c6c59a75e
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -0,0 +1,717 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <dt-bindings/clock/rk3288-cru.h>
20#include "clk.h"
21
22#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
23#define RK3288_GRF_SOC_STATUS 0x280
24
25enum rk3288_plls {
26 apll, dpll, cpll, gpll, npll,
27};
28
29struct rockchip_pll_rate_table rk3288_pll_rates[] = {
30 RK3066_PLL_RATE(2208000000, 1, 92, 1),
31 RK3066_PLL_RATE(2184000000, 1, 91, 1),
32 RK3066_PLL_RATE(2160000000, 1, 90, 1),
33 RK3066_PLL_RATE(2136000000, 1, 89, 1),
34 RK3066_PLL_RATE(2112000000, 1, 88, 1),
35 RK3066_PLL_RATE(2088000000, 1, 87, 1),
36 RK3066_PLL_RATE(2064000000, 1, 86, 1),
37 RK3066_PLL_RATE(2040000000, 1, 85, 1),
38 RK3066_PLL_RATE(2016000000, 1, 84, 1),
39 RK3066_PLL_RATE(1992000000, 1, 83, 1),
40 RK3066_PLL_RATE(1968000000, 1, 82, 1),
41 RK3066_PLL_RATE(1944000000, 1, 81, 1),
42 RK3066_PLL_RATE(1920000000, 1, 80, 1),
43 RK3066_PLL_RATE(1896000000, 1, 79, 1),
44 RK3066_PLL_RATE(1872000000, 1, 78, 1),
45 RK3066_PLL_RATE(1848000000, 1, 77, 1),
46 RK3066_PLL_RATE(1824000000, 1, 76, 1),
47 RK3066_PLL_RATE(1800000000, 1, 75, 1),
48 RK3066_PLL_RATE(1776000000, 1, 74, 1),
49 RK3066_PLL_RATE(1752000000, 1, 73, 1),
50 RK3066_PLL_RATE(1728000000, 1, 72, 1),
51 RK3066_PLL_RATE(1704000000, 1, 71, 1),
52 RK3066_PLL_RATE(1680000000, 1, 70, 1),
53 RK3066_PLL_RATE(1656000000, 1, 69, 1),
54 RK3066_PLL_RATE(1632000000, 1, 68, 1),
55 RK3066_PLL_RATE(1608000000, 1, 67, 1),
56 RK3066_PLL_RATE(1560000000, 1, 65, 1),
57 RK3066_PLL_RATE(1512000000, 1, 63, 1),
58 RK3066_PLL_RATE(1488000000, 1, 62, 1),
59 RK3066_PLL_RATE(1464000000, 1, 61, 1),
60 RK3066_PLL_RATE(1440000000, 1, 60, 1),
61 RK3066_PLL_RATE(1416000000, 1, 59, 1),
62 RK3066_PLL_RATE(1392000000, 1, 58, 1),
63 RK3066_PLL_RATE(1368000000, 1, 57, 1),
64 RK3066_PLL_RATE(1344000000, 1, 56, 1),
65 RK3066_PLL_RATE(1320000000, 1, 55, 1),
66 RK3066_PLL_RATE(1296000000, 1, 54, 1),
67 RK3066_PLL_RATE(1272000000, 1, 53, 1),
68 RK3066_PLL_RATE(1248000000, 1, 52, 1),
69 RK3066_PLL_RATE(1224000000, 1, 51, 1),
70 RK3066_PLL_RATE(1200000000, 1, 50, 1),
71 RK3066_PLL_RATE(1188000000, 2, 99, 1),
72 RK3066_PLL_RATE(1176000000, 1, 49, 1),
73 RK3066_PLL_RATE(1128000000, 1, 47, 1),
74 RK3066_PLL_RATE(1104000000, 1, 46, 1),
75 RK3066_PLL_RATE(1008000000, 1, 84, 2),
76 RK3066_PLL_RATE( 912000000, 1, 76, 2),
77 RK3066_PLL_RATE( 891000000, 8, 594, 2),
78 RK3066_PLL_RATE( 888000000, 1, 74, 2),
79 RK3066_PLL_RATE( 816000000, 1, 68, 2),
80 RK3066_PLL_RATE( 798000000, 2, 133, 2),
81 RK3066_PLL_RATE( 792000000, 1, 66, 2),
82 RK3066_PLL_RATE( 768000000, 1, 64, 2),
83 RK3066_PLL_RATE( 742500000, 8, 495, 2),
84 RK3066_PLL_RATE( 696000000, 1, 58, 2),
85 RK3066_PLL_RATE( 600000000, 1, 50, 2),
86 RK3066_PLL_RATE( 594000000, 2, 198, 4),
87 RK3066_PLL_RATE( 552000000, 1, 46, 2),
88 RK3066_PLL_RATE( 504000000, 1, 84, 4),
89 RK3066_PLL_RATE( 456000000, 1, 76, 4),
90 RK3066_PLL_RATE( 408000000, 1, 68, 4),
91 RK3066_PLL_RATE( 384000000, 2, 128, 4),
92 RK3066_PLL_RATE( 360000000, 1, 60, 4),
93 RK3066_PLL_RATE( 312000000, 1, 52, 4),
94 RK3066_PLL_RATE( 300000000, 1, 50, 4),
95 RK3066_PLL_RATE( 297000000, 2, 198, 8),
96 RK3066_PLL_RATE( 252000000, 1, 84, 8),
97 RK3066_PLL_RATE( 216000000, 1, 72, 8),
98 RK3066_PLL_RATE( 148500000, 2, 99, 8),
99 RK3066_PLL_RATE( 126000000, 1, 84, 16),
100 RK3066_PLL_RATE( 48000000, 1, 64, 32),
101 { /* sentinel */ },
102};
103
104PNAME(mux_pll_p) = { "xin24m", "xin32k" };
105PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
106PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
107PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
108
109PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
110PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
111PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
112PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
113
114PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
115PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
116PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
117PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
118PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
119PNAME(mux_uart0_pll_p) = { "cpll", "gpll", "usbphy_480m_src", "npll" };
120PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
121PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
122PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
123PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
124PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
125PNAME(mux_cif_out_p) = { "cif_src", "xin24m" };
126PNAME(mux_macref_p) = { "mac_src", "ext_gmac" };
127PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
128PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
129PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
130
131PNAME(mux_usbphy480m_p) = { "sclk_otgphy0", "sclk_otgphy1",
132 "sclk_otgphy2" };
133PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
134PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
135
136static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
137 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
138 RK3288_MODE_CON, 0, 6, rk3288_pll_rates),
139 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
140 RK3288_MODE_CON, 4, 5, NULL),
141 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
142 RK3288_MODE_CON, 8, 7, rk3288_pll_rates),
143 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
144 RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
145 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
146 RK3288_MODE_CON, 14, 9, NULL),
147};
148
149static struct clk_div_table div_hclk_cpu_t[] = {
150 { .val = 0, .div = 1 },
151 { .val = 1, .div = 2 },
152 { .val = 3, .div = 4 },
153 { /* sentinel */},
154};
155
156#define MFLAGS CLK_MUX_HIWORD_MASK
157#define DFLAGS CLK_DIVIDER_HIWORD_MASK
158#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
159
160static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
161 /*
162 * Clock-Architecture Diagram 1
163 */
164
165 GATE(0, "apll_core", "apll", 0,
166 RK3288_CLKGATE_CON(0), 1, GFLAGS),
167 GATE(0, "gpll_core", "gpll", 0,
168 RK3288_CLKGATE_CON(0), 2, GFLAGS),
169 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
170 RK3288_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
171
172 COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
173 RK3288_CLKSEL_CON(36), 0, 3, DFLAGS,
174 RK3288_CLKGATE_CON(12), 0, GFLAGS),
175 COMPOSITE_NOMUX(0, "armcore1", "armclk", 0,
176 RK3288_CLKSEL_CON(36), 4, 3, DFLAGS,
177 RK3288_CLKGATE_CON(12), 1, GFLAGS),
178 COMPOSITE_NOMUX(0, "armcore2", "armclk", 0,
179 RK3288_CLKSEL_CON(36), 8, 3, DFLAGS,
180 RK3288_CLKGATE_CON(12), 2, GFLAGS),
181 COMPOSITE_NOMUX(0, "armcore3", "armclk", 0,
182 RK3288_CLKSEL_CON(36), 12, 3, DFLAGS,
183 RK3288_CLKGATE_CON(12), 3, GFLAGS),
184 COMPOSITE_NOMUX(0, "l2ram", "armclk", 0,
185 RK3288_CLKSEL_CON(37), 0, 3, DFLAGS,
186 RK3288_CLKGATE_CON(12), 4, GFLAGS),
187 COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", 0,
188 RK3288_CLKSEL_CON(0), 0, 4, DFLAGS,
189 RK3288_CLKGATE_CON(12), 5, GFLAGS),
190 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", 0,
191 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS,
192 RK3288_CLKGATE_CON(12), 6, GFLAGS),
193 COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
194 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS,
195 RK3288_CLKGATE_CON(12), 7, GFLAGS),
196 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", 0,
197 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS,
198 RK3288_CLKGATE_CON(12), 8, GFLAGS),
199 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
200 RK3288_CLKGATE_CON(12), 9, GFLAGS),
201 GATE(0, "cs_dbg", "pclk_dbg_pre", 0,
202 RK3288_CLKGATE_CON(12), 10, GFLAGS),
203 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
204 RK3288_CLKGATE_CON(12), 11, GFLAGS),
205
206 GATE(0, "dpll_ddr", "dpll", 0,
207 RK3288_CLKGATE_CON(0), 8, GFLAGS),
208 GATE(0, "gpll_ddr", "gpll", 0,
209 RK3288_CLKGATE_CON(0), 9, GFLAGS),
210 COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, 0,
211 RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
212 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
213
214 GATE(0, "gpll_aclk_cpu", "gpll", 0,
215 RK3288_CLKGATE_CON(0), 10, GFLAGS),
216 GATE(0, "cpll_aclk_cpu", "cpll", 0,
217 RK3288_CLKGATE_CON(0), 11, GFLAGS),
218 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
219 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
220 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
221 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
222 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
223 RK3288_CLKGATE_CON(0), 3, GFLAGS),
224 COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0,
225 RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
226 RK3288_CLKGATE_CON(0), 5, GFLAGS),
227 COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0,
228 RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
229 RK3288_CLKGATE_CON(0), 4, GFLAGS),
230 GATE(0, "c2c_host", "aclk_cpu_src", 0,
231 RK3288_CLKGATE_CON(13), 8, GFLAGS),
232 COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
233 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
234 RK3288_CLKGATE_CON(5), 4, GFLAGS),
235 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0,
236 RK3288_CLKGATE_CON(0), 7, GFLAGS),
237
238 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
239 RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
240 RK3288_CLKGATE_CON(4), 1, GFLAGS),
241 COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
242 RK3288_CLKSEL_CON(8), 0,
243 RK3288_CLKGATE_CON(4), 2, GFLAGS),
244 MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
245 RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
246 COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
247 RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
248 RK3288_CLKGATE_CON(4), 0, GFLAGS),
249 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
250 RK3288_CLKGATE_CON(4), 3, GFLAGS),
251
252 MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
253 RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
254 COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0,
255 RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
256 RK3288_CLKGATE_CON(4), 4, GFLAGS),
257 COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0,
258 RK3288_CLKSEL_CON(9), 0,
259 RK3288_CLKGATE_CON(4), 5, GFLAGS),
260 COMPOSITE_NODIV(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
261 RK3288_CLKSEL_CON(5), 8, 2, MFLAGS,
262 RK3288_CLKGATE_CON(4), 6, GFLAGS),
263 COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
264 RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
265 RK3288_CLKGATE_CON(4), 7, GFLAGS),
266 COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", 0,
267 RK3288_CLKSEL_CON(41), 0,
268 RK3288_CLKGATE_CON(4), 8, GFLAGS),
269 COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
270 RK3288_CLKSEL_CON(40), 8, 2, MFLAGS,
271 RK3288_CLKGATE_CON(4), 9, GFLAGS),
272
273 GATE(0, "sclk_acc_efuse", "xin24m", 0,
274 RK3288_CLKGATE_CON(0), 12, GFLAGS),
275
276 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
277 RK3288_CLKGATE_CON(1), 0, GFLAGS),
278 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
279 RK3288_CLKGATE_CON(1), 1, GFLAGS),
280 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
281 RK3288_CLKGATE_CON(1), 2, GFLAGS),
282 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
283 RK3288_CLKGATE_CON(1), 3, GFLAGS),
284 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
285 RK3288_CLKGATE_CON(1), 4, GFLAGS),
286 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
287 RK3288_CLKGATE_CON(1), 5, GFLAGS),
288
289 /*
290 * Clock-Architecture Diagram 2
291 */
292
293 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
294 RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
295 RK3288_CLKGATE_CON(3), 9, GFLAGS),
296 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
297 RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
298 RK3288_CLKGATE_CON(3), 11, GFLAGS),
299
300 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
301 RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
302 RK3288_CLKGATE_CON(3), 0, GFLAGS),
303 DIV(0, "hclk_vio", "aclk_vio0", 0,
304 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
305 COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 0,
306 RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
307 RK3288_CLKGATE_CON(3), 2, GFLAGS),
308
309 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
310 RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
311 RK3288_CLKGATE_CON(3), 5, GFLAGS),
312 COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
313 RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
314 RK3288_CLKGATE_CON(3), 4, GFLAGS),
315
316 COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
317 RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
318 RK3288_CLKGATE_CON(3), 1, GFLAGS),
319 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
320 RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
321 RK3288_CLKGATE_CON(3), 3, GFLAGS),
322
323 COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0,
324 RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
325 RK3288_CLKGATE_CON(3), 12, GFLAGS),
326 COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
327 RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
328 RK3288_CLKGATE_CON(3), 13, GFLAGS),
329
330 COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
331 RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
332 RK3288_CLKGATE_CON(3), 14, GFLAGS),
333 COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
334 RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
335 RK3288_CLKGATE_CON(3), 15, GFLAGS),
336
337 GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
338 RK3288_CLKGATE_CON(5), 12, GFLAGS),
339 GATE(0, "sclk_hdmi_cec", "xin32k", 0,
340 RK3288_CLKGATE_CON(5), 11, GFLAGS),
341
342 COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
343 RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
344 RK3288_CLKGATE_CON(13), 13, GFLAGS),
345 DIV(0, "hclk_hevc", "aclk_hevc", 0,
346 RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
347
348 COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
349 RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
350 RK3288_CLKGATE_CON(13), 14, GFLAGS),
351 COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
352 RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
353 RK3288_CLKGATE_CON(13), 15, GFLAGS),
354
355 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
356 RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
357 RK3288_CLKGATE_CON(3), 7, GFLAGS),
358 COMPOSITE_NOGATE(0, "sclk_vip_out", mux_cif_out_p, 0,
359 RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
360
361 DIV(0, "pclk_pd_alive", "gpll", 0,
362 RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
363 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 0,
364 RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
365 RK3288_CLKGATE_CON(5), 8, GFLAGS),
366
367 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
368 RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
369 RK3288_CLKGATE_CON(5), 7, GFLAGS),
370
371 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
372 RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
373 RK3288_CLKGATE_CON(2), 0, GFLAGS),
374 COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0,
375 RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
376 RK3288_CLKGATE_CON(2), 3, GFLAGS),
377 COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0,
378 RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
379 RK3288_CLKGATE_CON(2), 2, GFLAGS),
380 GATE(0, "aclk_peri", "aclk_peri_src", 0,
381 RK3288_CLKGATE_CON(2), 1, GFLAGS),
382
383 /*
384 * Clock-Architecture Diagram 3
385 */
386
387 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
388 RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
389 RK3288_CLKGATE_CON(2), 9, GFLAGS),
390 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
391 RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
392 RK3288_CLKGATE_CON(2), 10, GFLAGS),
393 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
394 RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
395 RK3288_CLKGATE_CON(2), 11, GFLAGS),
396
397 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
398 RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
399 RK3288_CLKGATE_CON(13), 0, GFLAGS),
400 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
401 RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
402 RK3288_CLKGATE_CON(13), 1, GFLAGS),
403 COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
404 RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
405 RK3288_CLKGATE_CON(13), 2, GFLAGS),
406 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
407 RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
408 RK3288_CLKGATE_CON(13), 3, GFLAGS),
409
410 COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
411 RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
412 RK3288_CLKGATE_CON(4), 11, GFLAGS),
413 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
414 RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
415 RK3288_CLKGATE_CON(4), 10, GFLAGS),
416
417 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
418 RK3288_CLKGATE_CON(13), 4, GFLAGS),
419 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
420 RK3288_CLKGATE_CON(13), 5, GFLAGS),
421 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", 0,
422 RK3288_CLKGATE_CON(13), 6, GFLAGS),
423 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 0,
424 RK3288_CLKGATE_CON(13), 7, GFLAGS),
425
426 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
427 RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
428 RK3288_CLKGATE_CON(2), 7, GFLAGS),
429
430 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
431 RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
432 RK3288_CLKGATE_CON(2), 8, GFLAGS),
433
434 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
435 RK3288_CLKGATE_CON(5), 13, GFLAGS),
436
437 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
438 RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
439 RK3288_CLKGATE_CON(5), 5, GFLAGS),
440 COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
441 RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
442 RK3288_CLKGATE_CON(5), 6, GFLAGS),
443
444 COMPOSITE(0, "uart0_src", mux_uart0_pll_p, 0,
445 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
446 RK3288_CLKGATE_CON(1), 8, GFLAGS),
447 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0,
448 RK3288_CLKSEL_CON(17), 0,
449 RK3288_CLKGATE_CON(1), 9, GFLAGS),
450 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, 0,
451 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS),
452 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
453 RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
454 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
455 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
456 RK3288_CLKGATE_CON(1), 10, GFLAGS),
457 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", 0,
458 RK3288_CLKSEL_CON(18), 0,
459 RK3288_CLKGATE_CON(1), 11, GFLAGS),
460 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, 0,
461 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS),
462 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
463 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
464 RK3288_CLKGATE_CON(1), 12, GFLAGS),
465 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", 0,
466 RK3288_CLKSEL_CON(19), 0,
467 RK3288_CLKGATE_CON(1), 13, GFLAGS),
468 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, 0,
469 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS),
470 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
471 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
472 RK3288_CLKGATE_CON(1), 14, GFLAGS),
473 COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", 0,
474 RK3288_CLKSEL_CON(20), 0,
475 RK3288_CLKGATE_CON(1), 15, GFLAGS),
476 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, 0,
477 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS),
478 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
479 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
480 RK3288_CLKGATE_CON(2), 12, GFLAGS),
481 COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", 0,
482 RK3288_CLKSEL_CON(7), 0,
483 RK3288_CLKGATE_CON(2), 13, GFLAGS),
484 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, 0,
485 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),
486
487 COMPOSITE(0, "mac_src", mux_pll_src_npll_cpll_gpll_p, 0,
488 RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
489 RK3288_CLKGATE_CON(2), 5, GFLAGS),
490 MUX(0, "macref", mux_macref_p, 0,
491 RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
492 GATE(0, "sclk_macref_out", "macref", 0,
493 RK3288_CLKGATE_CON(5), 3, GFLAGS),
494 GATE(SCLK_MACREF, "sclk_macref", "macref", 0,
495 RK3288_CLKGATE_CON(5), 2, GFLAGS),
496 GATE(SCLK_MAC_RX, "sclk_mac_rx", "macref", 0,
497 RK3288_CLKGATE_CON(5), 0, GFLAGS),
498 GATE(SCLK_MAC_TX, "sclk_mac_tx", "macref", 0,
499 RK3288_CLKGATE_CON(5), 1, GFLAGS),
500
501 COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
502 RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
503 RK3288_CLKGATE_CON(2), 6, GFLAGS),
504 MUX(SCLK_HSADC, "sclk_hsadc_out", mux_hsadcout_p, 0,
505 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
506
507 GATE(0, "jtag", "ext_jtag", 0,
508 RK3288_CLKGATE_CON(4), 14, GFLAGS),
509
510 COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
511 RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
512 RK3288_CLKGATE_CON(5), 15, GFLAGS),
513 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
514 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
515 RK3288_CLKGATE_CON(3), 6, GFLAGS),
516 GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
517 RK3288_CLKGATE_CON(13), 9, GFLAGS),
518 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
519 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
520 MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
521 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
522
523 /*
524 * Clock-Architecture Diagram 4
525 */
526
527 /* aclk_cpu gates */
528 GATE(0, "sclk_intmem0", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 5, GFLAGS),
529 GATE(0, "sclk_intmem1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 6, GFLAGS),
530 GATE(0, "sclk_intmem2", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 7, GFLAGS),
531 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
532 GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 13, GFLAGS),
533 GATE(0, "aclk_intmem", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 4, GFLAGS),
534 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
535 GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
536
537 /* hclk_cpu gates */
538 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
539 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
540 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 9, GFLAGS),
541 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
542 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
543
544 /* pclk_cpu gates */
545 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
546 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
547 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
548 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
549 GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
550 GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
551 GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
552 GATE(0, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
553 GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
554 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
555 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
556 GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
557 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
558
559 /* ddrctrl [DDR Controller PHY clock] gates */
560 GATE(0, "nclk_ddrupctl0", "ddrphy", 0, RK3288_CLKGATE_CON(11), 4, GFLAGS),
561 GATE(0, "nclk_ddrupctl1", "ddrphy", 0, RK3288_CLKGATE_CON(11), 5, GFLAGS),
562
563 /* ddrphy gates */
564 GATE(0, "sclk_ddrphy0", "ddrphy", 0, RK3288_CLKGATE_CON(4), 12, GFLAGS),
565 GATE(0, "sclk_ddrphy1", "ddrphy", 0, RK3288_CLKGATE_CON(4), 13, GFLAGS),
566
567 /* aclk_peri gates */
568 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 2, GFLAGS),
569 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
570 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
571 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 12, GFLAGS),
572 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
573 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
574
575 /* hclk_peri gates */
576 GATE(0, "hclk_peri_matrix", "hclk_peri", 0, RK3288_CLKGATE_CON(6), 0, GFLAGS),
577 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 4, GFLAGS),
578 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
579 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 7, GFLAGS),
580 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
581 GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 9, GFLAGS),
582 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 10, GFLAGS),
583 GATE(0, "hclk_emem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 12, GFLAGS),
584 GATE(0, "hclk_mem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 13, GFLAGS),
585 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
586 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
587 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
588 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
589 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
590 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
591 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
592 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
593 GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
594
595 /* pclk_peri gates */
596 GATE(0, "pclk_peri_matrix", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 1, GFLAGS),
597 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
598 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
599 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
600 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
601 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
602 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
603 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
604 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
605 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
606 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
607 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
608 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
609 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
610 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
611 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
612 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
613
614 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
615 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
616 GATE(0, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
617 GATE(0, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
618 GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
619
620 /* sclk_gpu gates */
621 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
622
623 /* pclk_pd_alive gates */
624 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
625 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
626 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
627 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
628 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
629 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
630 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
631 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
632 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 11, GFLAGS),
633 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
634
635 /* pclk_pd_pmu gates */
636 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 0, GFLAGS),
637 GATE(0, "pclk_intmem1", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 1, GFLAGS),
638 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
639 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 3, GFLAGS),
640 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
641
642 /* hclk_vio gates */
643 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
644 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
645 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
646 GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
647 GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
648 GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
649 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
650 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
651 GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
652 GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
653 GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
654 GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
655 GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
656 GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
657 GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
658 GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
659
660 /* aclk_vio0 gates */
661 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
662 GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
663 GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
664 GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
665
666 /* aclk_vio1 gates */
667 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
668 GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
669 GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
670
671 /* aclk_rga_pre gates */
672 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
673 GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
674
675 /*
676 * Other ungrouped clocks.
677 */
678
679 GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
680 GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
681};
682
683static void __init rk3288_clk_init(struct device_node *np)
684{
685 void __iomem *reg_base;
686 struct clk *clk;
687
688 reg_base = of_iomap(np, 0);
689 if (!reg_base) {
690 pr_err("%s: could not map cru region\n", __func__);
691 return;
692 }
693
694 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
695
696 /* xin12m is created by an cru-internal divider */
697 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
698 if (IS_ERR(clk))
699 pr_warn("%s: could not register clock xin12m: %ld\n",
700 __func__, PTR_ERR(clk));
701
702
703 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
704 if (IS_ERR(clk))
705 pr_warn("%s: could not register clock usb480m: %ld\n",
706 __func__, PTR_ERR(clk));
707
708 rockchip_clk_register_plls(rk3288_pll_clks,
709 ARRAY_SIZE(rk3288_pll_clks),
710 RK3288_GRF_SOC_STATUS);
711 rockchip_clk_register_branches(rk3288_clk_branches,
712 ARRAY_SIZE(rk3288_clk_branches));
713
714 rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
715 ROCKCHIP_SOFTRST_HIWORD_MASK);
716}
717CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 32c334d7fc87..887cbdeca2aa 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -40,6 +40,15 @@
40#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110) 40#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110)
41#define RK2928_MISC_CON 0x134 41#define RK2928_MISC_CON 0x134
42 42
43#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
44#define RK3288_MODE_CON 0x50
45#define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60)
46#define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160)
47#define RK3288_GLB_SRST_FST 0x1b0
48#define RK3288_GLB_SRST_SND 0x1b4
49#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8)
50#define RK3288_MISC_CON 0x1e8
51
43enum rockchip_pll_type { 52enum rockchip_pll_type {
44 pll_rk3066, 53 pll_rk3066,
45}; 54};
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
new file mode 100644
index 000000000000..ebcb460ea4ad
--- /dev/null
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -0,0 +1,278 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/* core clocks */
17#define PLL_APLL 1
18#define PLL_DPLL 2
19#define PLL_CPLL 3
20#define PLL_GPLL 4
21#define PLL_NPLL 5
22
23/* sclk gates (special clocks) */
24#define SCLK_GPU 64
25#define SCLK_SPI0 65
26#define SCLK_SPI1 66
27#define SCLK_SPI2 67
28#define SCLK_SDMMC 68
29#define SCLK_SDIO0 69
30#define SCLK_SDIO1 70
31#define SCLK_EMMC 71
32#define SCLK_TSADC 72
33#define SCLK_SARADC 73
34#define SCLK_PS2C 74
35#define SCLK_NANDC0 75
36#define SCLK_NANDC1 76
37#define SCLK_UART0 77
38#define SCLK_UART1 78
39#define SCLK_UART2 79
40#define SCLK_UART3 80
41#define SCLK_UART4 81
42#define SCLK_I2S0 82
43#define SCLK_SPDIF 83
44#define SCLK_SPDIF8CH 84
45#define SCLK_TIMER0 85
46#define SCLK_TIMER1 86
47#define SCLK_TIMER2 87
48#define SCLK_TIMER3 88
49#define SCLK_TIMER4 89
50#define SCLK_TIMER5 90
51#define SCLK_TIMER6 91
52#define SCLK_HSADC 92
53#define SCLK_OTGPHY0 93
54#define SCLK_OTGPHY1 94
55#define SCLK_OTGPHY2 95
56#define SCLK_OTG_ADP 96
57#define SCLK_HSICPHY480M 97
58#define SCLK_HSICPHY12M 98
59#define SCLK_MACREF 99
60#define SCLK_LCDC_PWM0 100
61#define SCLK_LCDC_PWM1 101
62#define SCLK_MAC_RX 102
63#define SCLK_MAC_TX 103
64
65#define DCLK_VOP0 190
66#define DCLK_VOP1 191
67
68/* aclk gates */
69#define ACLK_GPU 192
70#define ACLK_DMAC1 193
71#define ACLK_DMAC2 194
72#define ACLK_MMU 195
73#define ACLK_GMAC 196
74#define ACLK_VOP0 197
75#define ACLK_VOP1 198
76#define ACLK_CRYPTO 199
77#define ACLK_RGA 200
78
79/* pclk gates */
80#define PCLK_GPIO0 320
81#define PCLK_GPIO1 321
82#define PCLK_GPIO2 322
83#define PCLK_GPIO3 323
84#define PCLK_GPIO4 324
85#define PCLK_GPIO5 325
86#define PCLK_GPIO6 326
87#define PCLK_GPIO7 327
88#define PCLK_GPIO8 328
89#define PCLK_GRF 329
90#define PCLK_SGRF 330
91#define PCLK_PMU 331
92#define PCLK_I2C0 332
93#define PCLK_I2C1 333
94#define PCLK_I2C2 334
95#define PCLK_I2C3 335
96#define PCLK_I2C4 336
97#define PCLK_I2C5 337
98#define PCLK_SPI0 338
99#define PCLK_SPI1 339
100#define PCLK_SPI2 340
101#define PCLK_UART0 341
102#define PCLK_UART1 342
103#define PCLK_UART2 343
104#define PCLK_UART3 344
105#define PCLK_UART4 345
106#define PCLK_TSADC 346
107#define PCLK_SARADC 347
108#define PCLK_SIM 348
109#define PCLK_GMAC 349
110#define PCLK_PWM 350
111#define PCLK_RKPWM 351
112#define PCLK_PS2C 352
113#define PCLK_TIMER 353
114#define PCLK_TZPC 354
115
116/* hclk gates */
117#define HCLK_GPS 448
118#define HCLK_OTG0 449
119#define HCLK_USBHOST0 450
120#define HCLK_USBHOST1 451
121#define HCLK_HSIC 452
122#define HCLK_NANDC0 453
123#define HCLK_NANDC1 454
124#define HCLK_TSP 455
125#define HCLK_SDMMC 456
126#define HCLK_SDIO0 457
127#define HCLK_SDIO1 458
128#define HCLK_EMMC 459
129#define HCLK_HSADC 460
130#define HCLK_CRYPTO 461
131#define HCLK_I2S0 462
132#define HCLK_SPDIF 463
133#define HCLK_SPDIF8CH 464
134#define HCLK_VOP0 465
135#define HCLK_VOP1 466
136#define HCLK_ROM 467
137#define HCLK_IEP 468
138#define HCLK_ISP 469
139#define HCLK_RGA 470
140
141#define CLK_NR_CLKS (HCLK_RGA + 1)
142
143/* soft-reset indices */
144#define SRST_CORE0 0
145#define SRST_CORE1 1
146#define SRST_CORE2 2
147#define SRST_CORE3 3
148#define SRST_CORE0_PO 4
149#define SRST_CORE1_PO 5
150#define SRST_CORE2_PO 6
151#define SRST_CORE3_PO 7
152#define SRST_PDCORE_STRSYS 8
153#define SRST_PDBUS_STRSYS 9
154#define SRST_L2C 10
155#define SRST_TOPDBG 11
156#define SRST_CORE0_DBG 12
157#define SRST_CORE1_DBG 13
158#define SRST_CORE2_DBG 14
159#define SRST_CORE3_DBG 15
160
161#define SRST_PDBUG_AHB_ARBITOR 16
162#define SRST_EFUSE256 17
163#define SRST_DMAC1 18
164#define SRST_INTMEM 19
165#define SRST_ROM 20
166#define SRST_SPDIF8CH 21
167#define SRST_TIMER 22
168#define SRST_I2S0 23
169#define SRST_SPDIF 24
170#define SRST_TIMER0 25
171#define SRST_TIMER1 26
172#define SRST_TIMER2 27
173#define SRST_TIMER3 28
174#define SRST_TIMER4 29
175#define SRST_TIMER5 30
176#define SRST_EFUSE 31
177
178#define SRST_GPIO0 32
179#define SRST_GPIO1 33
180#define SRST_GPIO2 34
181#define SRST_GPIO3 35
182#define SRST_GPIO4 36
183#define SRST_GPIO5 37
184#define SRST_GPIO6 38
185#define SRST_GPIO7 39
186#define SRST_GPIO8 40
187#define SRST_I2C0 42
188#define SRST_I2C1 43
189#define SRST_I2C2 44
190#define SRST_I2C3 45
191#define SRST_I2C4 46
192#define SRST_I2C5 47
193
194#define SRST_DWPWM 48
195#define SRST_MMC_PERI 49
196#define SRST_PERIPH_MMU 50
197#define SRST_DAP 51
198#define SRST_DAP_SYS 52
199#define SRST_TPIU 53
200#define SRST_PMU_APB 54
201#define SRST_GRF 55
202#define SRST_PMU 56
203#define SRST_PERIPH_AXI 57
204#define SRST_PERIPH_AHB 58
205#define SRST_PERIPH_APB 59
206#define SRST_PERIPH_NIU 60
207#define SRST_PDPERI_AHB_ARBI 61
208#define SRST_EMEM 62
209#define SRST_USB_PERI 63
210
211#define SRST_DMAC2 64
212#define SRST_MAC 66
213#define SRST_GPS 67
214#define SRST_RKPWM 69
215#define SRST_CCP 71
216#define SRST_USBHOST0 72
217#define SRST_HSIC 73
218#define SRST_HSIC_AUX 74
219#define SRST_HSIC_PHY 75
220#define SRST_HSADC 76
221#define SRST_NANDC0 77
222#define SRST_NANDC1 78
223
224#define SRST_TZPC 80
225#define SRST_SPI0 83
226#define SRST_SPI1 84
227#define SRST_SPI2 85
228#define SRST_SARADC 87
229#define SRST_PDALIVE_NIU 88
230#define SRST_PDPMU_INTMEM 89
231#define SRST_PDPMU_NIU 90
232#define SRST_SGRF 91
233
234#define SRST_VIO_ARBI 96
235#define SRST_RGA_NIU 97
236#define SRST_VIO0_NIU_AXI 98
237#define SRST_VIO_NIU_AHB 99
238#define SRST_LCDC0_AXI 100
239#define SRST_LCDC0_AHB 101
240#define SRST_LCDC0_DCLK 102
241#define SRST_VIO1_NIU_AXI 103
242#define SRST_VIP 104
243#define SRST_RGA_CORE 105
244#define SRST_IEP_AXI 106
245#define SRST_IEP_AHB 107
246#define SRST_RGA_AXI 108
247#define SRST_RGA_AHB 109
248#define SRST_ISP 110
249#define SRST_EDP 111
250
251#define SRST_VCODEC_AXI 112
252#define SRST_VCODEC_AHB 113
253#define SRST_VIO_H2P 114
254#define SRST_MIPIDSI0 115
255#define SRST_MIPIDSI1 116
256#define SRST_MIPICSI 117
257#define SRST_LVDS_PHY 118
258#define SRST_LVDS_CON 119
259#define SRST_GPU 120
260#define SRST_HDMI 121
261#define SRST_CORE_PVTM 124
262#define SRST_GPU_PVTM 125
263
264#define SRST_MMC0 128
265#define SRST_SDIO0 129
266#define SRST_SDIO1 130
267#define SRST_EMMC 131
268#define SRST_USBOTG_AHB 132
269#define SRST_USBOTG_PHY 133
270#define SRST_USBOTG_CON 134
271#define SRST_USBHOST0_AHB 135
272#define SRST_USBHOST0_PHY 136
273#define SRST_USBHOST0_CON 137
274#define SRST_USBHOST1_AHB 138
275#define SRST_USBHOST1_PHY 139
276#define SRST_USBHOST1_CON 140
277#define SRST_USB_ADP 141
278#define SRST_ACC_EFUSE 142
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-26 22:52:25 -0400