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authorMichael Turquette <mturquette@baylibre.com>2015-12-22 13:34:10 -0500
committerMichael Turquette <mturquette@baylibre.com>2015-12-22 14:57:35 -0500
commitb8f15e711904712e71d2aac3241f9669d0b62917 (patch)
treee44d2f1b0fdf7068df8d52318c1e74f7e3020468
parent4ef7675344d687a0ef5b0d7c0cee12da005870c0 (diff)
parentfcd5ac1a4137aea367f6a41399a15e7cef1c0841 (diff)
Merge commit 'fe5fa8fbd4d47f40a45fa29ee1abdb10cb061ec2' into clk-next
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt5
-rw-r--r--Documentation/devicetree/bindings/clock/cs2000-cp.txt22
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,mmcc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt56
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt58
-rw-r--r--Documentation/devicetree/bindings/clock/tango4-clock.txt23
-rw-r--r--arch/arm/mach-omap2/clock.c4
-rw-r--r--drivers/clk/Kconfig6
-rw-r--r--drivers/clk/Makefile3
-rw-r--r--drivers/clk/at91/clk-slow.c29
-rw-r--r--drivers/clk/bcm/Kconfig10
-rw-r--r--drivers/clk/bcm/Makefile1
-rw-r--r--drivers/clk/bcm/clk-bcm63xx.c22
-rw-r--r--drivers/clk/clk-cs2000-cp.c510
-rw-r--r--drivers/clk/clk-divider.c9
-rw-r--r--drivers/clk/clk-mux.c5
-rw-r--r--drivers/clk/clk-si5351.c7
-rw-r--r--drivers/clk/clk-tango4.c61
-rw-r--r--drivers/clk/clk-xgene.c3
-rw-r--r--drivers/clk/clk.c17
-rw-r--r--drivers/clk/imx/clk-imx25.c18
-rw-r--r--drivers/clk/imx/clk-imx51-imx53.c8
-rw-r--r--drivers/clk/imx/clk-imx6q.c3
-rw-r--r--drivers/clk/imx/clk-imx6ul.c4
-rw-r--r--drivers/clk/imx/clk-imx7d.c11
-rw-r--r--drivers/clk/imx/clk-pllv3.c14
-rw-r--r--drivers/clk/qcom/Kconfig17
-rw-r--r--drivers/clk/qcom/Makefile3
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.c355
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.h57
-rw-r--r--drivers/clk/qcom/clk-rcg.h1
-rw-r--r--drivers/clk/qcom/clk-rcg2.c87
-rw-r--r--drivers/clk/qcom/common.c87
-rw-r--r--drivers/clk/qcom/common.h4
-rw-r--r--drivers/clk/qcom/gcc-apq8084.c17
-rw-r--r--drivers/clk/qcom/gcc-ipq806x.c15
-rw-r--r--drivers/clk/qcom/gcc-msm8660.c16
-rw-r--r--drivers/clk/qcom/gcc-msm8916.c17
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c16
-rw-r--r--drivers/clk/qcom/gcc-msm8974.c18
-rw-r--r--drivers/clk/qcom/gcc-msm8996.c3422
-rw-r--r--drivers/clk/qcom/lcc-ipq806x.c1
-rw-r--r--drivers/clk/qcom/lcc-msm8960.c1
-rw-r--r--drivers/clk/qcom/mmcc-apq8084.c1
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c2
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c1
-rw-r--r--drivers/clk/qcom/mmcc-msm8996.c3217
-rw-r--r--drivers/clk/rockchip/Makefile2
-rw-r--r--drivers/clk/rockchip/clk-cpu.c4
-rw-r--r--drivers/clk/rockchip/clk-pll.c258
-rw-r--r--drivers/clk/rockchip/clk-rk3036.c478
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c2
-rw-r--r--drivers/clk/rockchip/clk-rk3228.c678
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c42
-rw-r--r--drivers/clk/rockchip/clk-rk3368.c13
-rw-r--r--drivers/clk/rockchip/clk.c7
-rw-r--r--drivers/clk/rockchip/clk.h43
-rw-r--r--drivers/clk/shmobile/Makefile24
-rw-r--r--drivers/clk/shmobile/clk-div6.c137
-rw-r--r--drivers/clk/shmobile/clk-div6.h7
-rw-r--r--drivers/clk/shmobile/clk-rcar-gen2.c4
-rw-r--r--drivers/clk/shmobile/r8a7795-cpg-mssr.c382
-rw-r--r--drivers/clk/shmobile/renesas-cpg-mssr.c596
-rw-r--r--drivers/clk/shmobile/renesas-cpg-mssr.h132
-rw-r--r--drivers/clk/st/clkgen-fsyn.c17
-rw-r--r--drivers/clk/ti/apll.c2
-rw-r--r--drivers/clk/ti/dpll3xxx.c25
-rw-r--r--drivers/clk/versatile/clk-sp810.c5
-rw-r--r--include/dt-bindings/clock/imx7d-clock.h3
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8996.h339
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-msm8996.h285
-rw-r--r--include/dt-bindings/clock/rk3036-cru.h193
-rw-r--r--include/dt-bindings/clock/rk3228-cru.h220
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h4
-rw-r--r--include/linux/clk-provider.h8
-rw-r--r--include/linux/clk/ti.h1
78 files changed, 11938 insertions, 243 deletions
diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
index ede65a55e21b..0b35e71b39e8 100644
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -208,3 +208,8 @@ These clock IDs are defined in:
208 ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED 208 ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
209 ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED 209 ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
210 ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED 210 ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
211
212BCM63138
213--------
214PLL and leaf clock compatible strings for BCM63138 are:
215 "brcm,bcm63138-armpll"
diff --git a/Documentation/devicetree/bindings/clock/cs2000-cp.txt b/Documentation/devicetree/bindings/clock/cs2000-cp.txt
new file mode 100644
index 000000000000..54e6df0bee8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/cs2000-cp.txt
@@ -0,0 +1,22 @@
1CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
2
3Required properties:
4
5- compatible: "cirrus,cs2000-cp"
6- reg: The chip select number on the I2C bus
7- clocks: common clock binding for CLK_IN, XTI/REF_CLK
8- clock-names: CLK_IN : clk_in, XTI/REF_CLK : ref_clk
9- #clock-cells: must be <0>
10
11Example:
12
13&i2c2 {
14 ...
15 cs2000: clk_multiplier@4f {
16 #clock-cells = <0>;
17 compatible = "cirrus,cs2000-cp";
18 reg = <0x4f>;
19 clocks = <&rcar_sound 0>, <&x12_clk>;
20 clock-names = "clk_in", "ref_clk";
21 };
22};
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 152dfaab2575..72f82f444091 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -13,6 +13,7 @@ Required properties :
13 "qcom,gcc-msm8974" 13 "qcom,gcc-msm8974"
14 "qcom,gcc-msm8974pro" 14 "qcom,gcc-msm8974pro"
15 "qcom,gcc-msm8974pro-ac" 15 "qcom,gcc-msm8974pro-ac"
16 "qcom,gcc-msm8996"
16 17
17- reg : shall contain base register location and length 18- reg : shall contain base register location and length
18- #clock-cells : shall contain 1 19- #clock-cells : shall contain 1
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index 34e7614d5074..8b0f7841af8d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -9,6 +9,7 @@ Required properties :
9 "qcom,mmcc-msm8660" 9 "qcom,mmcc-msm8660"
10 "qcom,mmcc-msm8960" 10 "qcom,mmcc-msm8960"
11 "qcom,mmcc-msm8974" 11 "qcom,mmcc-msm8974"
12 "qcom,mmcc-msm8996"
12 13
13- reg : shall contain base register location and length 14- reg : shall contain base register location and length
14- #clock-cells : shall contain 1 15- #clock-cells : shall contain 1
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 38dcf0370143..ae36ab842919 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -20,6 +20,10 @@ Required Properties:
20 clocks must be specified. For clocks with multiple parents, invalid 20 clocks must be specified. For clocks with multiple parents, invalid
21 settings must be specified as "<0>". 21 settings must be specified as "<0>".
22 - #clock-cells: Must be 0 22 - #clock-cells: Must be 0
23
24
25Optional Properties:
26
23 - clock-output-names: The name of the clock as a free-form string 27 - clock-output-names: The name of the clock as a free-form string
24 28
25 29
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000000000000..ace05992a262
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
1* Rockchip RK3036 Clock and Reset Unit
2
3The RK3036 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: should be "rockchip,rk3036-cru"
10- reg: physical base address of the controller and length of memory mapped
11 region.
12- #clock-cells: should be 1.
13- #reset-cells: should be 1.
14
15Optional Properties:
16
17- rockchip,grf: phandle to the syscon managing the "general register files"
18 If missing pll rates are not changeable, due to the missing pll lock status.
19
20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in
24these files.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_i2s" - external I2S clock - optional,
33 - "ext_gmac" - external GMAC clock - optional
34
35Example: Clock controller node:
36
37 cru: cru@20000000 {
38 compatible = "rockchip,rk3036-cru";
39 reg = <0x20000000 0x1000>;
40 rockchip,grf = <&grf>;
41
42 #clock-cells = <1>;
43 #reset-cells = <1>;
44 };
45
46Example: UART controller node that consumes the clock generated by the clock
47 controller:
48
49 uart0: serial@20060000 {
50 compatible = "snps,dw-apb-uart";
51 reg = <0x20060000 0x100>;
52 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
53 reg-shift = <2>;
54 reg-io-width = <4>;
55 clocks = <&cru SCLK_UART0>;
56 };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
new file mode 100644
index 000000000000..f323048127eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
@@ -0,0 +1,58 @@
1* Rockchip RK3228 Clock and Reset Unit
2
3The RK3228 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: should be "rockchip,rk3228-cru"
10- reg: physical base address of the controller and length of memory mapped
11 region.
12- #clock-cells: should be 1.
13- #reset-cells: should be 1.
14
15Optional Properties:
16
17- rockchip,grf: phandle to the syscon managing the "general register files"
18 If missing pll rates are not changeable, due to the missing pll lock status.
19
20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in
24these files.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_i2s" - external I2S clock - optional,
33 - "ext_gmac" - external GMAC clock - optional
34 - "ext_hsadc" - external HSADC clock - optional
35 - "phy_50m_out" - output clock of the pll in the mac phy
36
37Example: Clock controller node:
38
39 cru: cru@20000000 {
40 compatible = "rockchip,rk3228-cru";
41 reg = <0x20000000 0x1000>;
42 rockchip,grf = <&grf>;
43
44 #clock-cells = <1>;
45 #reset-cells = <1>;
46 };
47
48Example: UART controller node that consumes the clock generated by the clock
49 controller:
50
51 uart0: serial@10110000 {
52 compatible = "snps,dw-apb-uart";
53 reg = <0x10110000 0x100>;
54 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
55 reg-shift = <2>;
56 reg-io-width = <4>;
57 clocks = <&cru SCLK_UART0>;
58 };
diff --git a/Documentation/devicetree/bindings/clock/tango4-clock.txt b/Documentation/devicetree/bindings/clock/tango4-clock.txt
new file mode 100644
index 000000000000..19c580a7bda2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/tango4-clock.txt
@@ -0,0 +1,23 @@
1* Sigma Designs Tango4 Clock Generator
2
3The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
4for RAM and various peripheral devices). The clock binding described here
5is applicable to all Tango4 SoCs.
6
7Required Properties:
8
9- compatible: should be "sigma,tango4-clkgen".
10- reg: physical base address of the device and length of memory mapped region.
11- clocks: phandle of the input clock (crystal oscillator).
12- clock-output-names: should be "cpuclk" and "sysclk".
13- #clock-cells: should be set to 1.
14
15Example:
16
17 clkgen: clkgen@10000 {
18 compatible = "sigma,tango4-clkgen";
19 reg = <0x10000 0x40>;
20 clocks = <&xtal>;
21 clock-output-names = "cpuclk", "sysclk";
22 #clock-cells = <1>;
23 };
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index acb60ed17273..d058125876d8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -225,5 +225,9 @@ void __init ti_clk_init_features(void)
225 if (omap_rev() == OMAP3430_REV_ES1_0) 225 if (omap_rev() == OMAP3430_REV_ES1_0)
226 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; 226 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
227 227
228 /* Errata I810 for omap5 / dra7 */
229 if (soc_is_omap54xx() || soc_is_dra7xx())
230 features.flags |= TI_CLK_ERRATA_I810;
231
228 ti_clk_setup_features(&features); 232 ti_clk_setup_features(&features);
229} 233}
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index c3e3a02f7f1f..d2d3871e64c9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -116,6 +116,12 @@ config COMMON_CLK_CDCE925
116 Given a target output frequency, the driver will set the PLL and 116 Given a target output frequency, the driver will set the PLL and
117 divider to best approximate the desired output. 117 divider to best approximate the desired output.
118 118
119config COMMON_CLK_CS2000_CP
120 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
121 depends on I2C
122 help
123 If you say yes here you get support for the CS2000 clock multiplier.
124
119config COMMON_CLK_S2MPS11 125config COMMON_CLK_S2MPS11
120 tristate "Clock driver for S2MPS1X/S5M8767 MFD" 126 tristate "Clock driver for S2MPS1X/S5M8767 MFD"
121 depends on MFD_SEC_CORE 127 depends on MFD_SEC_CORE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 820714c72d36..0e0fdac2a599 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
21obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o 21obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
22obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o 22obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
23obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o 23obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
24obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
24obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o 25obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
25obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 26obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
26obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 27obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
@@ -42,6 +43,7 @@ obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
42obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o 43obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
43obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o 44obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
44obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o 45obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o
46obj-$(CONFIG_ARCH_TANGOX) += clk-tango4.o
45obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o 47obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
46obj-$(CONFIG_ARCH_U300) += clk-u300.o 48obj-$(CONFIG_ARCH_U300) += clk-u300.o
47obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 49obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
@@ -69,6 +71,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
69obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ 71obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
70obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ 72obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
71obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/ 73obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
74obj-$(CONFIG_ARCH_RENESAS) += shmobile/
72obj-$(CONFIG_ARCH_SIRF) += sirf/ 75obj-$(CONFIG_ARCH_SIRF) += sirf/
73obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ 76obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
74obj-$(CONFIG_PLAT_SPEAR) += spear/ 77obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
index d0d5076a9b94..6f99a530ead6 100644
--- a/drivers/clk/at91/clk-slow.c
+++ b/drivers/clk/at91/clk-slow.c
@@ -10,7 +10,6 @@
10 * 10 *
11 */ 11 */
12 12
13#include <linux/clk.h>
14#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
15#include <linux/clkdev.h> 14#include <linux/clkdev.h>
16#include <linux/slab.h> 15#include <linux/slab.h>
@@ -72,8 +71,6 @@ struct clk_sam9x5_slow {
72 71
73#define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw) 72#define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
74 73
75static struct clk *slow_clk;
76
77static int clk_slow_osc_prepare(struct clk_hw *hw) 74static int clk_slow_osc_prepare(struct clk_hw *hw)
78{ 75{
79 struct clk_slow_osc *osc = to_clk_slow_osc(hw); 76 struct clk_slow_osc *osc = to_clk_slow_osc(hw);
@@ -360,8 +357,6 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
360 clk = clk_register(NULL, &slowck->hw); 357 clk = clk_register(NULL, &slowck->hw);
361 if (IS_ERR(clk)) 358 if (IS_ERR(clk))
362 kfree(slowck); 359 kfree(slowck);
363 else
364 slow_clk = clk;
365 360
366 return clk; 361 return clk;
367} 362}
@@ -433,8 +428,6 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc,
433 clk = clk_register(NULL, &slowck->hw); 428 clk = clk_register(NULL, &slowck->hw);
434 if (IS_ERR(clk)) 429 if (IS_ERR(clk))
435 kfree(slowck); 430 kfree(slowck);
436 else
437 slow_clk = clk;
438 431
439 return clk; 432 return clk;
440} 433}
@@ -462,25 +455,3 @@ void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
462 455
463 of_clk_add_provider(np, of_clk_src_simple_get, clk); 456 of_clk_add_provider(np, of_clk_src_simple_get, clk);
464} 457}
465
466/*
467 * FIXME: All slow clk users are not properly claiming it (get + prepare +
468 * enable) before using it.
469 * If all users properly claiming this clock decide that they don't need it
470 * anymore (or are removed), it is disabled while faulty users are still
471 * requiring it, and the system hangs.
472 * Prevent this clock from being disabled until all users are properly
473 * requesting it.
474 * Once this is done we should remove this function and the slow_clk variable.
475 */
476static int __init of_at91_clk_slow_retain(void)
477{
478 if (!slow_clk)
479 return 0;
480
481 __clk_get(slow_clk);
482 clk_prepare_enable(slow_clk);
483
484 return 0;
485}
486arch_initcall(of_at91_clk_slow_retain);
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 85260fb96b36..f2878459199a 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -1,3 +1,13 @@
1config CLK_BCM_63XX
2 bool "Broadcom BCM63xx clock support"
3 depends on ARCH_BCM_63XX || COMPILE_TEST
4 depends on COMMON_CLK
5 select COMMON_CLK_IPROC
6 default ARCH_BCM_63XX
7 help
8 Enable common clock framework support for Broadcom BCM63xx DSL SoCs
9 based on the ARM architecture
10
1config CLK_BCM_KONA 11config CLK_BCM_KONA
2 bool "Broadcom Kona CCU clock support" 12 bool "Broadcom Kona CCU clock support"
3 depends on ARCH_BCM_MOBILE || COMPILE_TEST 13 depends on ARCH_BCM_MOBILE || COMPILE_TEST
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 3fc95060d875..247c26750d8b 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
1obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o 2obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
2obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o 3obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
3obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o 4obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c
new file mode 100644
index 000000000000..fbc17ae5ff2b
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm63xx.c
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#include <linux/init.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include "clk-iproc.h"
17
18static void __init bcm63138_armpll_init(struct device_node *node)
19{
20 iproc_armpll_setup(node);
21}
22CLK_OF_DECLARE(bcm63138_armpll, "brcm,bcm63138-armpll", bcm63138_armpll_init);
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
new file mode 100644
index 000000000000..7379de8dc894
--- /dev/null
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -0,0 +1,510 @@
1/*
2 * CS2000 -- CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/clk-provider.h>
12#include <linux/delay.h>
13#include <linux/clk.h>
14#include <linux/i2c.h>
15#include <linux/of_device.h>
16#include <linux/module.h>
17
18#define CH_MAX 4
19#define RATIO_REG_SIZE 4
20
21#define DEVICE_ID 0x1
22#define DEVICE_CTRL 0x2
23#define DEVICE_CFG1 0x3
24#define DEVICE_CFG2 0x4
25#define GLOBAL_CFG 0x5
26#define Ratio_Add(x, nth) (6 + (x * 4) + (nth))
27#define Ratio_Val(x, nth) ((x >> (24 - (8 * nth))) & 0xFF)
28#define Val_Ratio(x, nth) ((x & 0xFF) << (24 - (8 * nth)))
29#define FUNC_CFG1 0x16
30#define FUNC_CFG2 0x17
31
32/* DEVICE_ID */
33#define REVISION_MASK (0x7)
34#define REVISION_B2_B3 (0x4)
35#define REVISION_C1 (0x6)
36
37/* DEVICE_CTRL */
38#define PLL_UNLOCK (1 << 7)
39
40/* DEVICE_CFG1 */
41#define RSEL(x) (((x) & 0x3) << 3)
42#define RSEL_MASK RSEL(0x3)
43#define ENDEV1 (0x1)
44
45/* GLOBAL_CFG */
46#define ENDEV2 (0x1)
47
48#define CH_SIZE_ERR(ch) ((ch < 0) || (ch >= CH_MAX))
49#define hw_to_priv(_hw) container_of(_hw, struct cs2000_priv, hw)
50#define priv_to_client(priv) (priv->client)
51#define priv_to_dev(priv) (&(priv_to_client(priv)->dev))
52
53#define CLK_IN 0
54#define REF_CLK 1
55#define CLK_MAX 2
56
57struct cs2000_priv {
58 struct clk_hw hw;
59 struct i2c_client *client;
60 struct clk *clk_in;
61 struct clk *ref_clk;
62 struct clk *clk_out;
63};
64
65static const struct of_device_id cs2000_of_match[] = {
66 { .compatible = "cirrus,cs2000-cp", },
67 {},
68};
69MODULE_DEVICE_TABLE(of, cs2000_of_match);
70
71static const struct i2c_device_id cs2000_id[] = {
72 { "cs2000-cp", },
73 {}
74};
75MODULE_DEVICE_TABLE(i2c, cs2000_id);
76
77#define cs2000_read(priv, addr) \
78 i2c_smbus_read_byte_data(priv_to_client(priv), addr)
79#define cs2000_write(priv, addr, val) \
80 i2c_smbus_write_byte_data(priv_to_client(priv), addr, val)
81
82static int cs2000_bset(struct cs2000_priv *priv, u8 addr, u8 mask, u8 val)
83{
84 s32 data;
85
86 data = cs2000_read(priv, addr);
87 if (data < 0)
88 return data;
89
90 data &= ~mask;
91 data |= (val & mask);
92
93 return cs2000_write(priv, addr, data);
94}
95
96static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable)
97{
98 int ret;
99
100 ret = cs2000_bset(priv, DEVICE_CFG1, ENDEV1,
101 enable ? ENDEV1 : 0);
102 if (ret < 0)
103 return ret;
104
105 ret = cs2000_bset(priv, GLOBAL_CFG, ENDEV2,
106 enable ? ENDEV2 : 0);
107 if (ret < 0)
108 return ret;
109
110 return 0;
111}
112
113static int cs2000_clk_in_bound_rate(struct cs2000_priv *priv,
114 u32 rate_in)
115{
116 u32 val;
117
118 if (rate_in >= 32000000 && rate_in < 56000000)
119 val = 0x0;
120 else if (rate_in >= 16000000 && rate_in < 28000000)
121 val = 0x1;
122 else if (rate_in >= 8000000 && rate_in < 14000000)
123 val = 0x2;
124 else
125 return -EINVAL;
126
127 return cs2000_bset(priv, FUNC_CFG1, 0x3 << 3, val << 3);
128}
129
130static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
131{
132 struct device *dev = priv_to_dev(priv);
133 s32 val;
134 unsigned int i;
135
136 for (i = 0; i < 256; i++) {
137 val = cs2000_read(priv, DEVICE_CTRL);
138 if (val < 0)
139 return val;
140 if (!(val & PLL_UNLOCK))
141 return 0;
142 udelay(1);
143 }
144
145 dev_err(dev, "pll lock failed\n");
146
147 return -ETIMEDOUT;
148}
149
150static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable)
151{
152 /* enable both AUX_OUT, CLK_OUT */
153 return cs2000_write(priv, DEVICE_CTRL, enable ? 0 : 0x3);
154}
155
156static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out)
157{
158 u64 ratio;
159
160 /*
161 * ratio = rate_out / rate_in * 2^20
162 *
163 * To avoid over flow, rate_out is u64.
164 * The result should be u32.
165 */
166 ratio = (u64)rate_out << 20;
167 do_div(ratio, rate_in);
168
169 return ratio;
170}
171
172static unsigned long cs2000_ratio_to_rate(u32 ratio, u32 rate_in)
173{
174 u64 rate_out;
175
176 /*
177 * ratio = rate_out / rate_in * 2^20
178 *
179 * To avoid over flow, rate_out is u64.
180 * The result should be u32 or unsigned long.
181 */
182
183 rate_out = (u64)ratio * rate_in;
184 return rate_out >> 20;
185}
186
187static int cs2000_ratio_set(struct cs2000_priv *priv,
188 int ch, u32 rate_in, u32 rate_out)
189{
190 u32 val;
191 unsigned int i;
192 int ret;
193
194 if (CH_SIZE_ERR(ch))
195 return -EINVAL;
196
197 val = cs2000_rate_to_ratio(rate_in, rate_out);
198 for (i = 0; i < RATIO_REG_SIZE; i++) {
199 ret = cs2000_write(priv,
200 Ratio_Add(ch, i),
201 Ratio_Val(val, i));
202 if (ret < 0)
203 return ret;
204 }
205
206 return 0;
207}
208
209static u32 cs2000_ratio_get(struct cs2000_priv *priv, int ch)
210{
211 s32 tmp;
212 u32 val;
213 unsigned int i;
214
215 val = 0;
216 for (i = 0; i < RATIO_REG_SIZE; i++) {
217 tmp = cs2000_read(priv, Ratio_Add(ch, i));
218 if (tmp < 0)
219 return 0;
220
221 val |= Val_Ratio(tmp, i);
222 }
223
224 return val;
225}
226
227static int cs2000_ratio_select(struct cs2000_priv *priv, int ch)
228{
229 int ret;
230
231 if (CH_SIZE_ERR(ch))
232 return -EINVAL;
233
234 /*
235 * FIXME
236 *
237 * this driver supports static ratio mode only at this point.
238 */
239 ret = cs2000_bset(priv, DEVICE_CFG1, RSEL_MASK, RSEL(ch));
240 if (ret < 0)
241 return ret;
242
243 ret = cs2000_write(priv, DEVICE_CFG2, 0x0);
244 if (ret < 0)
245 return ret;
246
247 return 0;
248}
249
250static unsigned long cs2000_recalc_rate(struct clk_hw *hw,
251 unsigned long parent_rate)
252{
253 struct cs2000_priv *priv = hw_to_priv(hw);
254 int ch = 0; /* it uses ch0 only at this point */
255 u32 ratio;
256
257 ratio = cs2000_ratio_get(priv, ch);
258
259 return cs2000_ratio_to_rate(ratio, parent_rate);
260}
261
262static long cs2000_round_rate(struct clk_hw *hw, unsigned long rate,
263 unsigned long *parent_rate)
264{
265 u32 ratio;
266
267 ratio = cs2000_rate_to_ratio(*parent_rate, rate);
268
269 return cs2000_ratio_to_rate(ratio, *parent_rate);
270}
271
272static int __cs2000_set_rate(struct cs2000_priv *priv, int ch,
273 unsigned long rate, unsigned long parent_rate)
274
275{
276 int ret;
277
278 ret = cs2000_clk_in_bound_rate(priv, parent_rate);
279 if (ret < 0)
280 return ret;
281
282 ret = cs2000_ratio_set(priv, ch, parent_rate, rate);
283 if (ret < 0)
284 return ret;
285
286 ret = cs2000_ratio_select(priv, ch);
287 if (ret < 0)
288 return ret;
289
290 return 0;
291}
292
293static int cs2000_set_rate(struct clk_hw *hw,
294 unsigned long rate, unsigned long parent_rate)
295{
296 struct cs2000_priv *priv = hw_to_priv(hw);
297 int ch = 0; /* it uses ch0 only at this point */
298
299 return __cs2000_set_rate(priv, ch, rate, parent_rate);
300}
301
302static int cs2000_enable(struct clk_hw *hw)
303{
304 struct cs2000_priv *priv = hw_to_priv(hw);
305 int ret;
306
307 ret = cs2000_enable_dev_config(priv, true);
308 if (ret < 0)
309 return ret;
310
311 ret = cs2000_clk_out_enable(priv, true);
312 if (ret < 0)
313 return ret;
314
315 ret = cs2000_wait_pll_lock(priv);
316 if (ret < 0)
317 return ret;
318
319 return ret;
320}
321
322static void cs2000_disable(struct clk_hw *hw)
323{
324 struct cs2000_priv *priv = hw_to_priv(hw);
325
326 cs2000_enable_dev_config(priv, false);
327
328 cs2000_clk_out_enable(priv, false);
329}
330
331static u8 cs2000_get_parent(struct clk_hw *hw)
332{
333 /* always return REF_CLK */
334 return REF_CLK;
335}
336
337static const struct clk_ops cs2000_ops = {
338 .get_parent = cs2000_get_parent,
339 .recalc_rate = cs2000_recalc_rate,
340 .round_rate = cs2000_round_rate,
341 .set_rate = cs2000_set_rate,
342 .prepare = cs2000_enable,
343 .unprepare = cs2000_disable,
344};
345
346static int cs2000_clk_get(struct cs2000_priv *priv)
347{
348 struct i2c_client *client = priv_to_client(priv);
349 struct device *dev = &client->dev;
350 struct clk *clk_in, *ref_clk;
351
352 clk_in = devm_clk_get(dev, "clk_in");
353 /* not yet provided */
354 if (IS_ERR(clk_in))
355 return -EPROBE_DEFER;
356
357 ref_clk = devm_clk_get(dev, "ref_clk");
358 /* not yet provided */
359 if (IS_ERR(ref_clk))
360 return -EPROBE_DEFER;
361
362 priv->clk_in = clk_in;
363 priv->ref_clk = ref_clk;
364
365 return 0;
366}
367
368static int cs2000_clk_register(struct cs2000_priv *priv)
369{
370 struct device *dev = priv_to_dev(priv);
371 struct device_node *np = dev->of_node;
372 struct clk_init_data init;
373 const char *name = np->name;
374 struct clk *clk;
375 static const char *parent_names[CLK_MAX];
376 int ch = 0; /* it uses ch0 only at this point */
377 int rate;
378 int ret;
379
380 of_property_read_string(np, "clock-output-names", &name);
381
382 /*
383 * set default rate as 1/1.
384 * otherwise .set_rate which setup ratio
385 * is never called if user requests 1/1 rate
386 */
387 rate = clk_get_rate(priv->ref_clk);
388 ret = __cs2000_set_rate(priv, ch, rate, rate);
389 if (ret < 0)
390 return ret;
391
392 parent_names[CLK_IN] = __clk_get_name(priv->clk_in);
393 parent_names[REF_CLK] = __clk_get_name(priv->ref_clk);
394
395 init.name = name;
396 init.ops = &cs2000_ops;
397 init.flags = CLK_SET_RATE_GATE;
398 init.parent_names = parent_names;
399 init.num_parents = ARRAY_SIZE(parent_names);
400
401 priv->hw.init = &init;
402
403 clk = clk_register(dev, &priv->hw);
404 if (IS_ERR(clk))
405 return PTR_ERR(clk);
406
407 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
408 if (ret < 0) {
409 clk_unregister(clk);
410 return ret;
411 }
412
413 priv->clk_out = clk;
414
415 return 0;
416}
417
418static int cs2000_version_print(struct cs2000_priv *priv)
419{
420 struct i2c_client *client = priv_to_client(priv);
421 struct device *dev = &client->dev;
422 s32 val;
423 const char *revision;
424
425 val = cs2000_read(priv, DEVICE_ID);
426 if (val < 0)
427 return val;
428
429 /* CS2000 should be 0x0 */
430 if (val >> 3)
431 return -EIO;
432
433 switch (val & REVISION_MASK) {
434 case REVISION_B2_B3:
435 revision = "B2 / B3";
436 break;
437 case REVISION_C1:
438 revision = "C1";
439 break;
440 default:
441 return -EIO;
442 }
443
444 dev_info(dev, "revision - %s\n", revision);
445
446 return 0;
447}
448
449static int cs2000_remove(struct i2c_client *client)
450{
451 struct cs2000_priv *priv = i2c_get_clientdata(client);
452 struct device *dev = &client->dev;
453 struct device_node *np = dev->of_node;
454
455 of_clk_del_provider(np);
456
457 clk_unregister(priv->clk_out);
458
459 return 0;
460}
461
462static int cs2000_probe(struct i2c_client *client,
463 const struct i2c_device_id *id)
464{
465 struct cs2000_priv *priv;
466 struct device *dev = &client->dev;
467 int ret;
468
469 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
470 if (!priv)
471 return -ENOMEM;
472
473 priv->client = client;
474 i2c_set_clientdata(client, priv);
475
476 ret = cs2000_clk_get(priv);
477 if (ret < 0)
478 return ret;
479
480 ret = cs2000_clk_register(priv);
481 if (ret < 0)
482 return ret;
483
484 ret = cs2000_version_print(priv);
485 if (ret < 0)
486 goto probe_err;
487
488 return 0;
489
490probe_err:
491 cs2000_remove(client);
492
493 return ret;
494}
495
496static struct i2c_driver cs2000_driver = {
497 .driver = {
498 .name = "cs2000-cp",
499 .of_match_table = cs2000_of_match,
500 },
501 .probe = cs2000_probe,
502 .remove = cs2000_remove,
503 .id_table = cs2000_id,
504};
505
506module_i2c_driver(cs2000_driver);
507
508MODULE_DESCRIPTION("CS2000-CP driver");
509MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
510MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3ace102a2a0a..ded3ff4b91b9 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -32,13 +32,14 @@
32 32
33#define div_mask(width) ((1 << (width)) - 1) 33#define div_mask(width) ((1 << (width)) - 1)
34 34
35static unsigned int _get_table_maxdiv(const struct clk_div_table *table) 35static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
36 u8 width)
36{ 37{
37 unsigned int maxdiv = 0; 38 unsigned int maxdiv = 0, mask = div_mask(width);
38 const struct clk_div_table *clkt; 39 const struct clk_div_table *clkt;
39 40
40 for (clkt = table; clkt->div; clkt++) 41 for (clkt = table; clkt->div; clkt++)
41 if (clkt->div > maxdiv) 42 if (clkt->div > maxdiv && clkt->val <= mask)
42 maxdiv = clkt->div; 43 maxdiv = clkt->div;
43 return maxdiv; 44 return maxdiv;
44} 45}
@@ -62,7 +63,7 @@ static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
62 if (flags & CLK_DIVIDER_POWER_OF_TWO) 63 if (flags & CLK_DIVIDER_POWER_OF_TWO)
63 return 1 << div_mask(width); 64 return 1 << div_mask(width);
64 if (table) 65 if (table)
65 return _get_table_maxdiv(table); 66 return _get_table_maxdiv(table, width);
66 return div_mask(width) + 1; 67 return div_mask(width) + 1;
67} 68}
68 69
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 7129c86a79db..5ed03c8a8df9 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -71,10 +71,9 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
71 u32 val; 71 u32 val;
72 unsigned long flags = 0; 72 unsigned long flags = 0;
73 73
74 if (mux->table) 74 if (mux->table) {
75 index = mux->table[index]; 75 index = mux->table[index];
76 76 } else {
77 else {
78 if (mux->flags & CLK_MUX_INDEX_BIT) 77 if (mux->flags & CLK_MUX_INDEX_BIT)
79 index = 1 << index; 78 index = 1 << index;
80 79
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index e346b223199d..850316ac8831 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1091,6 +1091,13 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1091 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, 1091 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
1092 SI5351_CLK_POWERDOWN, 0); 1092 SI5351_CLK_POWERDOWN, 0);
1093 1093
1094 /*
1095 * Do a pll soft reset on both plls, needed in some cases to get
1096 * all outputs running.
1097 */
1098 si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
1099 SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
1100
1094 dev_dbg(&hwdata->drvdata->client->dev, 1101 dev_dbg(&hwdata->drvdata->client->dev,
1095 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", 1102 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1096 __func__, clk_hw_get_name(hw), (1 << rdiv), 1103 __func__, clk_hw_get_name(hw), (1 << rdiv),
diff --git a/drivers/clk/clk-tango4.c b/drivers/clk/clk-tango4.c
new file mode 100644
index 000000000000..004ab7dfcfe3
--- /dev/null
+++ b/drivers/clk/clk-tango4.c
@@ -0,0 +1,61 @@
1#include <linux/kernel.h>
2#include <linux/clk-provider.h>
3#include <linux/of_address.h>
4#include <linux/init.h>
5#include <linux/io.h>
6
7static struct clk *out[2];
8static struct clk_onecell_data clk_data = { out, 2 };
9
10#define SYSCLK_CTRL 0x20
11#define CPUCLK_CTRL 0x24
12#define LEGACY_DIV 0x3c
13
14#define PLL_N(val) (((val) >> 0) & 0x7f)
15#define PLL_K(val) (((val) >> 13) & 0x7)
16#define PLL_M(val) (((val) >> 16) & 0x7)
17#define DIV_INDEX(val) (((val) >> 8) & 0xf)
18
19static void __init make_pll(int idx, const char *parent, void __iomem *base)
20{
21 char name[8];
22 u32 val, mul, div;
23
24 sprintf(name, "pll%d", idx);
25 val = readl_relaxed(base + idx*8);
26 mul = PLL_N(val) + 1;
27 div = (PLL_M(val) + 1) << PLL_K(val);
28 clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
29}
30
31static int __init get_div(void __iomem *base)
32{
33 u8 sysclk_tab[16] = { 2, 4, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4 };
34 int idx = DIV_INDEX(readl_relaxed(base + LEGACY_DIV));
35
36 return sysclk_tab[idx];
37}
38
39static void __init tango4_clkgen_setup(struct device_node *np)
40{
41 int div, ret;
42 void __iomem *base = of_iomap(np, 0);
43 const char *parent = of_clk_get_parent_name(np, 0);
44
45 if (!base)
46 panic("%s: invalid address\n", np->full_name);
47
48 make_pll(0, parent, base);
49 make_pll(1, parent, base);
50
51 out[0] = clk_register_divider(NULL, "cpuclk", "pll0", 0,
52 base + CPUCLK_CTRL, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
53
54 div = readl_relaxed(base + SYSCLK_CTRL) & BIT(23) ? get_div(base) : 4;
55 out[1] = clk_register_fixed_factor(NULL, "sysclk", "pll1", 0, 1, div);
56
57 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
58 if (IS_ERR(out[0]) || IS_ERR(out[1]) || ret < 0)
59 panic("%s: clk registration failed\n", np->full_name);
60}
61CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 27c0da29eca3..10224b01b97c 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
351 /* Set new divider */ 351 /* Set new divider */
352 data = xgene_clk_read(pclk->param.divider_reg + 352 data = xgene_clk_read(pclk->param.divider_reg +
353 pclk->param.reg_divider_offset); 353 pclk->param.reg_divider_offset);
354 data &= ~((1 << pclk->param.reg_divider_width) - 1); 354 data &= ~((1 << pclk->param.reg_divider_width) - 1)
355 << pclk->param.reg_divider_shift;
355 data |= divider; 356 data |= divider;
356 xgene_clk_write(data, pclk->param.divider_reg + 357 xgene_clk_write(data, pclk->param.divider_reg +
357 pclk->param.reg_divider_offset); 358 pclk->param.reg_divider_offset);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index f13c3f4228d4..9352a13395c8 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1944,7 +1944,7 @@ bool clk_is_match(const struct clk *p, const struct clk *q)
1944 if (p == q) 1944 if (p == q)
1945 return true; 1945 return true;
1946 1946
1947 /* true if clk->core pointers match. Avoid derefing garbage */ 1947 /* true if clk->core pointers match. Avoid dereferencing garbage */
1948 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q)) 1948 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
1949 if (p->core == q->core) 1949 if (p->core == q->core)
1950 return true; 1950 return true;
@@ -2482,7 +2482,7 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2482 struct clk *clk; 2482 struct clk *clk;
2483 2483
2484 /* This is to allow this function to be chained to others */ 2484 /* This is to allow this function to be chained to others */
2485 if (!hw || IS_ERR(hw)) 2485 if (IS_ERR_OR_NULL(hw))
2486 return (struct clk *) hw; 2486 return (struct clk *) hw;
2487 2487
2488 clk = kzalloc(sizeof(*clk), GFP_KERNEL); 2488 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
@@ -2806,10 +2806,9 @@ void __clk_put(struct clk *clk)
2806 * re-enter into the clk framework by calling any top-level clk APIs; 2806 * re-enter into the clk framework by calling any top-level clk APIs;
2807 * this will cause a nested prepare_lock mutex. 2807 * this will cause a nested prepare_lock mutex.
2808 * 2808 *
2809 * In all notification cases cases (pre, post and abort rate change) the 2809 * In all notification cases (pre, post and abort rate change) the original
2810 * original clock rate is passed to the callback via struct 2810 * clock rate is passed to the callback via struct clk_notifier_data.old_rate
2811 * clk_notifier_data.old_rate and the new frequency is passed via struct 2811 * and the new frequency is passed via struct clk_notifier_data.new_rate.
2812 * clk_notifier_data.new_rate.
2813 * 2812 *
2814 * clk_notifier_register() must be called from non-atomic context. 2813 * clk_notifier_register() must be called from non-atomic context.
2815 * Returns -EINVAL if called with null arguments, -ENOMEM upon 2814 * Returns -EINVAL if called with null arguments, -ENOMEM upon
@@ -3062,9 +3061,6 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)
3062 int count; 3061 int count;
3063 struct clk *clk; 3062 struct clk *clk;
3064 3063
3065 if (index < 0)
3066 return NULL;
3067
3068 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index, 3064 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3069 &clkspec); 3065 &clkspec);
3070 if (rc) 3066 if (rc)
@@ -3083,6 +3079,9 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)
3083 } 3079 }
3084 count++; 3080 count++;
3085 } 3081 }
3082 /* We went off the end of 'clock-indices' without finding it */
3083 if (prop && !vp)
3084 return NULL;
3086 3085
3087 if (of_property_read_string_index(clkspec.np, "clock-output-names", 3086 if (of_property_read_string_index(clkspec.np, "clock-output-names",
3088 index, 3087 index,
diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c
index c4c141cab444..23686f756b5e 100644
--- a/drivers/clk/imx/clk-imx25.c
+++ b/drivers/clk/imx/clk-imx25.c
@@ -96,13 +96,11 @@ static struct clk ** const uart_clks[] __initconst = {
96 NULL 96 NULL
97}; 97};
98 98
99static int __init __mx25_clocks_init(unsigned long osc_rate, 99static int __init __mx25_clocks_init(void __iomem *ccm_base)
100 void __iomem *ccm_base)
101{ 100{
102 BUG_ON(!ccm_base); 101 BUG_ON(!ccm_base);
103 102
104 clk[dummy] = imx_clk_fixed("dummy", 0); 103 clk[dummy] = imx_clk_fixed("dummy", 0);
105 clk[osc] = imx_clk_fixed("osc", osc_rate);
106 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); 104 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL));
107 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); 105 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL));
108 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); 106 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
@@ -250,22 +248,10 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
250 248
251static void __init mx25_clocks_init_dt(struct device_node *np) 249static void __init mx25_clocks_init_dt(struct device_node *np)
252{ 250{
253 struct device_node *refnp;
254 unsigned long osc_rate = 24000000;
255 void __iomem *ccm; 251 void __iomem *ccm;
256 252
257 /* retrieve the freqency of fixed clocks from device tree */
258 for_each_compatible_node(refnp, NULL, "fixed-clock") {
259 u32 rate;
260 if (of_property_read_u32(refnp, "clock-frequency", &rate))
261 continue;
262
263 if (of_device_is_compatible(refnp, "fsl,imx-osc"))
264 osc_rate = rate;
265 }
266
267 ccm = of_iomap(np, 0); 253 ccm = of_iomap(np, 0);
268 __mx25_clocks_init(osc_rate, ccm); 254 __mx25_clocks_init(ccm);
269 255
270 clk_data.clks = clk; 256 clk_data.clks = clk;
271 clk_data.clk_num = ARRAY_SIZE(clk); 257 clk_data.clk_num = ARRAY_SIZE(clk);
diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c
index c6770348d2ab..29d4c44ef356 100644
--- a/drivers/clk/imx/clk-imx51-imx53.c
+++ b/drivers/clk/imx/clk-imx51-imx53.c
@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_node *np)
519 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); 519 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
520 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); 520 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
521 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); 521 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
522 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, 522 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
523 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); 523 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);
524 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, 524 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
525 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); 525 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);
526 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, 526 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
527 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); 527 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
528 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); 528 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index c1935081d34a..f0efc6feeec2 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -70,7 +70,8 @@ static const char *cko_sels[] = { "cko1", "cko2", };
70static const char *lvds_sels[] = { 70static const char *lvds_sels[] = {
71 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", 71 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
72 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", 72 "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
73 "pcie_ref_125m", "sata_ref_100m", 73 "pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2",
74 "dummy", "dummy", "dummy", "dummy", "osc",
74}; 75};
75static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; 76static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
76static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; 77static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 01718d05e952..08692d74b884 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -399,9 +399,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
399 /* mask handshake of mmdc */ 399 /* mask handshake of mmdc */
400 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); 400 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
401 401
402 for (i = 0; i < ARRAY_SIZE(clks); i++) 402 imx_check_clocks(clks, ARRAY_SIZE(clks));
403 if (IS_ERR(clks[i]))
404 pr_err("i.MX6UL clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
405 403
406 clk_data.clks = clks; 404 clk_data.clks = clks;
407 clk_data.clk_num = ARRAY_SIZE(clks); 405 clk_data.clk_num = ARRAY_SIZE(clks);
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 448ef321948b..fbb6a8c8653d 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -833,10 +833,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
833 833
834 clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); 834 clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
835 835
836 for (i = 0; i < ARRAY_SIZE(clks); i++) 836 clks[IMX7D_CLK_ARM] = imx_clk_cpu("arm", "arm_a7_root_clk",
837 if (IS_ERR(clks[i])) 837 clks[IMX7D_ARM_A7_ROOT_CLK],
838 pr_err("i.MX7D clk %d: register failed with %ld\n", 838 clks[IMX7D_ARM_A7_ROOT_SRC],
839 i, PTR_ERR(clks[i])); 839 clks[IMX7D_PLL_ARM_MAIN_CLK],
840 clks[IMX7D_PLL_SYS_MAIN_CLK]);
841
842 imx_check_clocks(clks, ARRAY_SIZE(clks));
840 843
841 clk_data.clks = clks; 844 clk_data.clks = clks;
842 clk_data.clk_num = ARRAY_SIZE(clks); 845 clk_data.clk_num = ARRAY_SIZE(clks);
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 6addf8f58b97..c05c43d56a94 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -97,6 +97,16 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
97 writel_relaxed(val, pll->base); 97 writel_relaxed(val, pll->base);
98} 98}
99 99
100static int clk_pllv3_is_prepared(struct clk_hw *hw)
101{
102 struct clk_pllv3 *pll = to_clk_pllv3(hw);
103
104 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
105 return 1;
106
107 return 0;
108}
109
100static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 110static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
101 unsigned long parent_rate) 111 unsigned long parent_rate)
102{ 112{
@@ -139,6 +149,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
139static const struct clk_ops clk_pllv3_ops = { 149static const struct clk_ops clk_pllv3_ops = {
140 .prepare = clk_pllv3_prepare, 150 .prepare = clk_pllv3_prepare,
141 .unprepare = clk_pllv3_unprepare, 151 .unprepare = clk_pllv3_unprepare,
152 .is_prepared = clk_pllv3_is_prepared,
142 .recalc_rate = clk_pllv3_recalc_rate, 153 .recalc_rate = clk_pllv3_recalc_rate,
143 .round_rate = clk_pllv3_round_rate, 154 .round_rate = clk_pllv3_round_rate,
144 .set_rate = clk_pllv3_set_rate, 155 .set_rate = clk_pllv3_set_rate,
@@ -193,6 +204,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
193static const struct clk_ops clk_pllv3_sys_ops = { 204static const struct clk_ops clk_pllv3_sys_ops = {
194 .prepare = clk_pllv3_prepare, 205 .prepare = clk_pllv3_prepare,
195 .unprepare = clk_pllv3_unprepare, 206 .unprepare = clk_pllv3_unprepare,
207 .is_prepared = clk_pllv3_is_prepared,
196 .recalc_rate = clk_pllv3_sys_recalc_rate, 208 .recalc_rate = clk_pllv3_sys_recalc_rate,
197 .round_rate = clk_pllv3_sys_round_rate, 209 .round_rate = clk_pllv3_sys_round_rate,
198 .set_rate = clk_pllv3_sys_set_rate, 210 .set_rate = clk_pllv3_sys_set_rate,
@@ -265,6 +277,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
265static const struct clk_ops clk_pllv3_av_ops = { 277static const struct clk_ops clk_pllv3_av_ops = {
266 .prepare = clk_pllv3_prepare, 278 .prepare = clk_pllv3_prepare,
267 .unprepare = clk_pllv3_unprepare, 279 .unprepare = clk_pllv3_unprepare,
280 .is_prepared = clk_pllv3_is_prepared,
268 .recalc_rate = clk_pllv3_av_recalc_rate, 281 .recalc_rate = clk_pllv3_av_recalc_rate,
269 .round_rate = clk_pllv3_av_round_rate, 282 .round_rate = clk_pllv3_av_round_rate,
270 .set_rate = clk_pllv3_av_set_rate, 283 .set_rate = clk_pllv3_av_set_rate,
@@ -279,6 +292,7 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
279static const struct clk_ops clk_pllv3_enet_ops = { 292static const struct clk_ops clk_pllv3_enet_ops = {
280 .prepare = clk_pllv3_prepare, 293 .prepare = clk_pllv3_prepare,
281 .unprepare = clk_pllv3_unprepare, 294 .unprepare = clk_pllv3_unprepare,
295 .is_prepared = clk_pllv3_is_prepared,
282 .recalc_rate = clk_pllv3_enet_recalc_rate, 296 .recalc_rate = clk_pllv3_enet_recalc_rate,
283}; 297};
284 298
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee4c83aab4f4..b552eceec2be 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -106,3 +106,20 @@ config MSM_MMCC_8974
106 Support for the multimedia clock controller on msm8974 devices. 106 Support for the multimedia clock controller on msm8974 devices.
107 Say Y if you want to support multimedia devices such as display, 107 Say Y if you want to support multimedia devices such as display,
108 graphics, video encode/decode, camera, etc. 108 graphics, video encode/decode, camera, etc.
109
110config MSM_GCC_8996
111 tristate "MSM8996 Global Clock Controller"
112 depends on COMMON_CLK_QCOM
113 help
114 Support for the global clock controller on msm8996 devices.
115 Say Y if you want to use peripheral devices such as UART, SPI,
116 i2c, USB, UFS, SD/eMMC, PCIe, etc.
117
118config MSM_MMCC_8996
119 tristate "MSM8996 Multimedia Clock Controller"
120 select MSM_GCC_8996
121 depends on COMMON_CLK_QCOM
122 help
123 Support for the multimedia clock controller on msm8996 devices.
124 Say Y if you want to support multimedia devices such as display,
125 graphics, video encode/decode, camera, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index fe6252349e55..dc4280b85db1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
2 2
3clk-qcom-y += common.o 3clk-qcom-y += common.o
4clk-qcom-y += clk-regmap.o 4clk-qcom-y += clk-regmap.o
5clk-qcom-y += clk-alpha-pll.o
5clk-qcom-y += clk-pll.o 6clk-qcom-y += clk-pll.o
6clk-qcom-y += clk-rcg.o 7clk-qcom-y += clk-rcg.o
7clk-qcom-y += clk-rcg2.o 8clk-qcom-y += clk-rcg2.o
@@ -20,5 +21,7 @@ obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
20obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 21obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
21obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o 22obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
22obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 23obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
24obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
23obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o 25obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
24obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o 26obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
27obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
new file mode 100644
index 000000000000..e6a03eaf7a93
--- /dev/null
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -0,0 +1,355 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/export.h>
16#include <linux/clk-provider.h>
17#include <linux/regmap.h>
18#include <linux/delay.h>
19
20#include "clk-alpha-pll.h"
21
22#define PLL_MODE 0x00
23# define PLL_OUTCTRL BIT(0)
24# define PLL_BYPASSNL BIT(1)
25# define PLL_RESET_N BIT(2)
26# define PLL_LOCK_COUNT_SHIFT 8
27# define PLL_LOCK_COUNT_MASK 0x3f
28# define PLL_BIAS_COUNT_SHIFT 14
29# define PLL_BIAS_COUNT_MASK 0x3f
30# define PLL_VOTE_FSM_ENA BIT(20)
31# define PLL_VOTE_FSM_RESET BIT(21)
32# define PLL_ACTIVE_FLAG BIT(30)
33# define PLL_LOCK_DET BIT(31)
34
35#define PLL_L_VAL 0x04
36#define PLL_ALPHA_VAL 0x08
37#define PLL_ALPHA_VAL_U 0x0c
38
39#define PLL_USER_CTL 0x10
40# define PLL_POST_DIV_SHIFT 8
41# define PLL_POST_DIV_MASK 0xf
42# define PLL_ALPHA_EN BIT(24)
43# define PLL_VCO_SHIFT 20
44# define PLL_VCO_MASK 0x3
45
46#define PLL_USER_CTL_U 0x14
47
48#define PLL_CONFIG_CTL 0x18
49#define PLL_TEST_CTL 0x1c
50#define PLL_TEST_CTL_U 0x20
51#define PLL_STATUS 0x24
52
53/*
54 * Even though 40 bits are present, use only 32 for ease of calculation.
55 */
56#define ALPHA_REG_BITWIDTH 40
57#define ALPHA_BITWIDTH 32
58
59#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
60 struct clk_alpha_pll, clkr)
61
62#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
63 struct clk_alpha_pll_postdiv, clkr)
64
65static int wait_for_pll(struct clk_alpha_pll *pll)
66{
67 u32 val, mask, off;
68 int count;
69 int ret;
70 const char *name = clk_hw_get_name(&pll->clkr.hw);
71
72 off = pll->offset;
73 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
74 if (ret)
75 return ret;
76
77 if (val & PLL_VOTE_FSM_ENA)
78 mask = PLL_ACTIVE_FLAG;
79 else
80 mask = PLL_LOCK_DET;
81
82 /* Wait for pll to enable. */
83 for (count = 100; count > 0; count--) {
84 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
85 if (ret)
86 return ret;
87 if ((val & mask) == mask)
88 return 0;
89
90 udelay(1);
91 }
92
93 WARN(1, "%s didn't enable after voting for it!\n", name);
94 return -ETIMEDOUT;
95}
96
97static int clk_alpha_pll_enable(struct clk_hw *hw)
98{
99 int ret;
100 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
101 u32 val, mask, off;
102
103 off = pll->offset;
104
105 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
106 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
107 if (ret)
108 return ret;
109
110 /* If in FSM mode, just vote for it */
111 if (val & PLL_VOTE_FSM_ENA) {
112 ret = clk_enable_regmap(hw);
113 if (ret)
114 return ret;
115 return wait_for_pll(pll);
116 }
117
118 /* Skip if already enabled */
119 if ((val & mask) == mask)
120 return 0;
121
122 ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
123 PLL_BYPASSNL, PLL_BYPASSNL);
124 if (ret)
125 return ret;
126
127 /*
128 * H/W requires a 5us delay between disabling the bypass and
129 * de-asserting the reset.
130 */
131 mb();
132 udelay(5);
133
134 ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
135 PLL_RESET_N, PLL_RESET_N);
136 if (ret)
137 return ret;
138
139 ret = wait_for_pll(pll);
140 if (ret)
141 return ret;
142
143 ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
144 PLL_OUTCTRL, PLL_OUTCTRL);
145
146 /* Ensure that the write above goes through before returning. */
147 mb();
148 return ret;
149}
150
151static void clk_alpha_pll_disable(struct clk_hw *hw)
152{
153 int ret;
154 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
155 u32 val, mask, off;
156
157 off = pll->offset;
158
159 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
160 if (ret)
161 return;
162
163 /* If in FSM mode, just unvote it */
164 if (val & PLL_VOTE_FSM_ENA) {
165 clk_disable_regmap(hw);
166 return;
167 }
168
169 mask = PLL_OUTCTRL;
170 regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
171
172 /* Delay of 2 output clock ticks required until output is disabled */
173 mb();
174 udelay(1);
175
176 mask = PLL_RESET_N | PLL_BYPASSNL;
177 regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
178}
179
180static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
181{
182 return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH);
183}
184
185static unsigned long
186alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
187{
188 u64 remainder;
189 u64 quotient;
190
191 quotient = rate;
192 remainder = do_div(quotient, prate);
193 *l = quotient;
194
195 if (!remainder) {
196 *a = 0;
197 return rate;
198 }
199
200 /* Upper ALPHA_BITWIDTH bits of Alpha */
201 quotient = remainder << ALPHA_BITWIDTH;
202 remainder = do_div(quotient, prate);
203
204 if (remainder)
205 quotient++;
206
207 *a = quotient;
208 return alpha_pll_calc_rate(prate, *l, *a);
209}
210
211static const struct pll_vco *
212alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
213{
214 const struct pll_vco *v = pll->vco_table;
215 const struct pll_vco *end = v + pll->num_vco;
216
217 for (; v < end; v++)
218 if (rate >= v->min_freq && rate <= v->max_freq)
219 return v;
220
221 return NULL;
222}
223
224static unsigned long
225clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
226{
227 u32 l, low, high, ctl;
228 u64 a = 0, prate = parent_rate;
229 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
230 u32 off = pll->offset;
231
232 regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);
233
234 regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
235 if (ctl & PLL_ALPHA_EN) {
236 regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
237 regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, &high);
238 a = (u64)high << 32 | low;
239 a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
240 }
241
242 return alpha_pll_calc_rate(prate, l, a);
243}
244
245static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
246 unsigned long prate)
247{
248 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
249 const struct pll_vco *vco;
250 u32 l, off = pll->offset;
251 u64 a;
252
253 rate = alpha_pll_round_rate(rate, prate, &l, &a);
254 vco = alpha_pll_find_vco(pll, rate);
255 if (!vco) {
256 pr_err("alpha pll not in a valid vco range\n");
257 return -EINVAL;
258 }
259
260 a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
261
262 regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
263 regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, a);
264 regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
265
266 regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
267 PLL_VCO_MASK << PLL_VCO_SHIFT,
268 vco->val << PLL_VCO_SHIFT);
269
270 regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
271 PLL_ALPHA_EN);
272
273 return 0;
274}
275
276static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
277 unsigned long *prate)
278{
279 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
280 u32 l;
281 u64 a;
282 unsigned long min_freq, max_freq;
283
284 rate = alpha_pll_round_rate(rate, *prate, &l, &a);
285 if (alpha_pll_find_vco(pll, rate))
286 return rate;
287
288 min_freq = pll->vco_table[0].min_freq;
289 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
290
291 return clamp(rate, min_freq, max_freq);
292}
293
294const struct clk_ops clk_alpha_pll_ops = {
295 .enable = clk_alpha_pll_enable,
296 .disable = clk_alpha_pll_disable,
297 .recalc_rate = clk_alpha_pll_recalc_rate,
298 .round_rate = clk_alpha_pll_round_rate,
299 .set_rate = clk_alpha_pll_set_rate,
300};
301EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
302
303static unsigned long
304clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
305{
306 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
307 u32 ctl;
308
309 regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl);
310
311 ctl >>= PLL_POST_DIV_SHIFT;
312 ctl &= PLL_POST_DIV_MASK;
313
314 return parent_rate >> fls(ctl);
315}
316
317static const struct clk_div_table clk_alpha_div_table[] = {
318 { 0x0, 1 },
319 { 0x1, 2 },
320 { 0x3, 4 },
321 { 0x7, 8 },
322 { 0xf, 16 },
323 { }
324};
325
326static long
327clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
328 unsigned long *prate)
329{
330 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
331
332 return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
333 pll->width, CLK_DIVIDER_POWER_OF_TWO);
334}
335
336static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
337 unsigned long parent_rate)
338{
339 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
340 int div;
341
342 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
343 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
344
345 return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,
346 PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
347 div << PLL_POST_DIV_SHIFT);
348}
349
350const struct clk_ops clk_alpha_pll_postdiv_ops = {
351 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
352 .round_rate = clk_alpha_pll_postdiv_round_rate,
353 .set_rate = clk_alpha_pll_postdiv_set_rate,
354};
355EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
new file mode 100644
index 000000000000..90ce2016e1a0
--- /dev/null
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_ALPHA_PLL_H__
15#define __QCOM_CLK_ALPHA_PLL_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20struct pll_vco {
21 unsigned long min_freq;
22 unsigned long max_freq;
23 u32 val;
24};
25
26/**
27 * struct clk_alpha_pll - phase locked loop (PLL)
28 * @offset: base address of registers
29 * @vco_table: array of VCO settings
30 * @clkr: regmap clock handle
31 */
32struct clk_alpha_pll {
33 u32 offset;
34
35 const struct pll_vco *vco_table;
36 size_t num_vco;
37
38 struct clk_regmap clkr;
39};
40
41/**
42 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
43 * @offset: base address of registers
44 * @width: width of post-divider
45 * @clkr: regmap clock handle
46 */
47struct clk_alpha_pll_postdiv {
48 u32 offset;
49 u8 width;
50
51 struct clk_regmap clkr;
52};
53
54extern const struct clk_ops clk_alpha_pll_ops;
55extern const struct clk_ops clk_alpha_pll_postdiv_ops;
56
57#endif
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 4b1e94bdf29e..b904c335cda4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -178,5 +178,6 @@ extern const struct clk_ops clk_edp_pixel_ops;
178extern const struct clk_ops clk_byte_ops; 178extern const struct clk_ops clk_byte_ops;
179extern const struct clk_ops clk_byte2_ops; 179extern const struct clk_ops clk_byte2_ops;
180extern const struct clk_ops clk_pixel_ops; 180extern const struct clk_ops clk_pixel_ops;
181extern const struct clk_ops clk_gfx3d_ops;
181 182
182#endif 183#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index b544bb302f79..a071bba8018c 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -723,3 +723,90 @@ const struct clk_ops clk_pixel_ops = {
723 .determine_rate = clk_pixel_determine_rate, 723 .determine_rate = clk_pixel_determine_rate,
724}; 724};
725EXPORT_SYMBOL_GPL(clk_pixel_ops); 725EXPORT_SYMBOL_GPL(clk_pixel_ops);
726
727static int clk_gfx3d_determine_rate(struct clk_hw *hw,
728 struct clk_rate_request *req)
729{
730 struct clk_rate_request parent_req = { };
731 struct clk_hw *p2, *p8, *p9, *xo;
732 unsigned long p9_rate;
733 int ret;
734
735 xo = clk_hw_get_parent_by_index(hw, 0);
736 if (req->rate == clk_hw_get_rate(xo)) {
737 req->best_parent_hw = xo;
738 return 0;
739 }
740
741 p9 = clk_hw_get_parent_by_index(hw, 2);
742 p2 = clk_hw_get_parent_by_index(hw, 3);
743 p8 = clk_hw_get_parent_by_index(hw, 4);
744
745 /* PLL9 is a fixed rate PLL */
746 p9_rate = clk_hw_get_rate(p9);
747
748 parent_req.rate = req->rate = min(req->rate, p9_rate);
749 if (req->rate == p9_rate) {
750 req->rate = req->best_parent_rate = p9_rate;
751 req->best_parent_hw = p9;
752 return 0;
753 }
754
755 if (req->best_parent_hw == p9) {
756 /* Are we going back to a previously used rate? */
757 if (clk_hw_get_rate(p8) == req->rate)
758 req->best_parent_hw = p8;
759 else
760 req->best_parent_hw = p2;
761 } else if (req->best_parent_hw == p8) {
762 req->best_parent_hw = p2;
763 } else {
764 req->best_parent_hw = p8;
765 }
766
767 ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
768 if (ret)
769 return ret;
770
771 req->rate = req->best_parent_rate = parent_req.rate;
772
773 return 0;
774}
775
776static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
777 unsigned long parent_rate, u8 index)
778{
779 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
780 u32 cfg;
781 int ret;
782
783 /* Just mux it, we don't use the division or m/n hardware */
784 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
785 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
786 if (ret)
787 return ret;
788
789 return update_config(rcg);
790}
791
792static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
793 unsigned long parent_rate)
794{
795 /*
796 * We should never get here; clk_gfx3d_determine_rate() should always
797 * make us use a different parent than what we're currently using, so
798 * clk_gfx3d_set_rate_and_parent() should always be called.
799 */
800 return 0;
801}
802
803const struct clk_ops clk_gfx3d_ops = {
804 .is_enabled = clk_rcg2_is_enabled,
805 .get_parent = clk_rcg2_get_parent,
806 .set_parent = clk_rcg2_set_parent,
807 .recalc_rate = clk_rcg2_recalc_rate,
808 .set_rate = clk_gfx3d_set_rate,
809 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
810 .determine_rate = clk_gfx3d_determine_rate,
811};
812EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 8fa477293ae0..c112ebaba70d 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -17,6 +17,7 @@
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/clk-provider.h> 18#include <linux/clk-provider.h>
19#include <linux/reset-controller.h> 19#include <linux/reset-controller.h>
20#include <linux/of.h>
20 21
21#include "common.h" 22#include "common.h"
22#include "clk-rcg.h" 23#include "clk-rcg.h"
@@ -88,6 +89,92 @@ static void qcom_cc_gdsc_unregister(void *data)
88 gdsc_unregister(data); 89 gdsc_unregister(data);
89} 90}
90 91
92/*
93 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
94 * clock to translate 'path' clk into 'name' clk and regsiter the 'path'
95 * clk as a fixed rate clock if it isn't present.
96 */
97static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
98 const char *name, unsigned long rate,
99 bool add_factor)
100{
101 struct device_node *node = NULL;
102 struct device_node *clocks_node;
103 struct clk_fixed_factor *factor;
104 struct clk_fixed_rate *fixed;
105 struct clk *clk;
106 struct clk_init_data init_data = { };
107
108 clocks_node = of_find_node_by_path("/clocks");
109 if (clocks_node)
110 node = of_find_node_by_name(clocks_node, path);
111 of_node_put(clocks_node);
112
113 if (!node) {
114 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
115 if (!fixed)
116 return -EINVAL;
117
118 fixed->fixed_rate = rate;
119 fixed->hw.init = &init_data;
120
121 init_data.name = path;
122 init_data.flags = CLK_IS_ROOT;
123 init_data.ops = &clk_fixed_rate_ops;
124
125 clk = devm_clk_register(dev, &fixed->hw);
126 if (IS_ERR(clk))
127 return PTR_ERR(clk);
128 }
129 of_node_put(node);
130
131 if (add_factor) {
132 factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
133 if (!factor)
134 return -EINVAL;
135
136 factor->mult = factor->div = 1;
137 factor->hw.init = &init_data;
138
139 init_data.name = name;
140 init_data.parent_names = &path;
141 init_data.num_parents = 1;
142 init_data.flags = 0;
143 init_data.ops = &clk_fixed_factor_ops;
144
145 clk = devm_clk_register(dev, &factor->hw);
146 if (IS_ERR(clk))
147 return PTR_ERR(clk);
148 }
149
150 return 0;
151}
152
153int qcom_cc_register_board_clk(struct device *dev, const char *path,
154 const char *name, unsigned long rate)
155{
156 bool add_factor = true;
157 struct device_node *node;
158
159 /* The RPM clock driver will add the factor clock if present */
160 if (IS_ENABLED(CONFIG_QCOM_RPMCC)) {
161 node = of_find_compatible_node(NULL, NULL, "qcom,rpmcc");
162 if (of_device_is_available(node))
163 add_factor = false;
164 of_node_put(node);
165 }
166
167 return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
168}
169EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
170
171int qcom_cc_register_sleep_clk(struct device *dev)
172{
173 return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
174 32768, true);
175}
176EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
177
91int qcom_cc_really_probe(struct platform_device *pdev, 178int qcom_cc_really_probe(struct platform_device *pdev,
92 const struct qcom_cc_desc *desc, struct regmap *regmap) 179 const struct qcom_cc_desc *desc, struct regmap *regmap)
93{ 180{
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 7c1fba3ebc03..ae9bdeb21f29 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -37,6 +37,10 @@ extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
37extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, 37extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
38 u8 src); 38 u8 src);
39 39
40extern int qcom_cc_register_board_clk(struct device *dev, const char *path,
41 const char *name, unsigned long rate);
42extern int qcom_cc_register_sleep_clk(struct device *dev);
43
40extern struct regmap *qcom_cc_map(struct platform_device *pdev, 44extern struct regmap *qcom_cc_map(struct platform_device *pdev,
41 const struct qcom_cc_desc *desc); 45 const struct qcom_cc_desc *desc);
42extern int qcom_cc_really_probe(struct platform_device *pdev, 46extern int qcom_cc_really_probe(struct platform_device *pdev,
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index 1567c3a79534..cf73e539e9f6 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -3587,6 +3587,7 @@ static const struct regmap_config gcc_apq8084_regmap_config = {
3587 .val_bits = 32, 3587 .val_bits = 32,
3588 .max_register = 0x1fc0, 3588 .max_register = 0x1fc0,
3589 .fast_io = true, 3589 .fast_io = true,
3590 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3590}; 3591};
3591 3592
3592static const struct qcom_cc_desc gcc_apq8084_desc = { 3593static const struct qcom_cc_desc gcc_apq8084_desc = {
@@ -3607,18 +3608,16 @@ MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
3607 3608
3608static int gcc_apq8084_probe(struct platform_device *pdev) 3609static int gcc_apq8084_probe(struct platform_device *pdev)
3609{ 3610{
3610 struct clk *clk; 3611 int ret;
3611 struct device *dev = &pdev->dev; 3612 struct device *dev = &pdev->dev;
3612 3613
3613 /* Temporary until RPM clocks supported */ 3614 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3614 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000); 3615 if (ret)
3615 if (IS_ERR(clk)) 3616 return ret;
3616 return PTR_ERR(clk);
3617 3617
3618 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL, 3618 ret = qcom_cc_register_sleep_clk(dev);
3619 CLK_IS_ROOT, 32768); 3619 if (ret)
3620 if (IS_ERR(clk)) 3620 return ret;
3621 return PTR_ERR(clk);
3622 3621
3623 return qcom_cc_probe(pdev, &gcc_apq8084_desc); 3622 return qcom_cc_probe(pdev, &gcc_apq8084_desc);
3624} 3623}
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 16fc64c082a5..b692ae881d6a 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -3005,6 +3005,7 @@ static const struct regmap_config gcc_ipq806x_regmap_config = {
3005 .val_bits = 32, 3005 .val_bits = 32,
3006 .max_register = 0x3e40, 3006 .max_register = 0x3e40,
3007 .fast_io = true, 3007 .fast_io = true,
3008 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3008}; 3009};
3009 3010
3010static const struct qcom_cc_desc gcc_ipq806x_desc = { 3011static const struct qcom_cc_desc gcc_ipq806x_desc = {
@@ -3023,19 +3024,17 @@ MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
3023 3024
3024static int gcc_ipq806x_probe(struct platform_device *pdev) 3025static int gcc_ipq806x_probe(struct platform_device *pdev)
3025{ 3026{
3026 struct clk *clk;
3027 struct device *dev = &pdev->dev; 3027 struct device *dev = &pdev->dev;
3028 struct regmap *regmap; 3028 struct regmap *regmap;
3029 int ret; 3029 int ret;
3030 3030
3031 /* Temporary until RPM clocks supported */ 3031 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3032 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); 3032 if (ret)
3033 if (IS_ERR(clk)) 3033 return ret;
3034 return PTR_ERR(clk);
3035 3034
3036 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000); 3035 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3037 if (IS_ERR(clk)) 3036 if (ret)
3038 return PTR_ERR(clk); 3037 return ret;
3039 3038
3040 ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); 3039 ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
3041 if (ret) 3040 if (ret)
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index f110bb5a1df3..f6a2b14dfec4 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -2702,6 +2702,7 @@ static const struct regmap_config gcc_msm8660_regmap_config = {
2702 .val_bits = 32, 2702 .val_bits = 32,
2703 .max_register = 0x363c, 2703 .max_register = 0x363c,
2704 .fast_io = true, 2704 .fast_io = true,
2705 .val_format_endian = REGMAP_ENDIAN_LITTLE,
2705}; 2706};
2706 2707
2707static const struct qcom_cc_desc gcc_msm8660_desc = { 2708static const struct qcom_cc_desc gcc_msm8660_desc = {
@@ -2720,17 +2721,16 @@ MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2720 2721
2721static int gcc_msm8660_probe(struct platform_device *pdev) 2722static int gcc_msm8660_probe(struct platform_device *pdev)
2722{ 2723{
2723 struct clk *clk; 2724 int ret;
2724 struct device *dev = &pdev->dev; 2725 struct device *dev = &pdev->dev;
2725 2726
2726 /* Temporary until RPM clocks supported */ 2727 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
2727 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000); 2728 if (ret)
2728 if (IS_ERR(clk)) 2729 return ret;
2729 return PTR_ERR(clk);
2730 2730
2731 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000); 2731 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
2732 if (IS_ERR(clk)) 2732 if (ret)
2733 return PTR_ERR(clk); 2733 return ret;
2734 2734
2735 return qcom_cc_probe(pdev, &gcc_msm8660_desc); 2735 return qcom_cc_probe(pdev, &gcc_msm8660_desc);
2736} 2736}
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index d0a0313d6bef..e3bf09d7d0ef 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -3336,6 +3336,7 @@ static const struct regmap_config gcc_msm8916_regmap_config = {
3336 .val_bits = 32, 3336 .val_bits = 32,
3337 .max_register = 0x80000, 3337 .max_register = 0x80000,
3338 .fast_io = true, 3338 .fast_io = true,
3339 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3339}; 3340};
3340 3341
3341static const struct qcom_cc_desc gcc_msm8916_desc = { 3342static const struct qcom_cc_desc gcc_msm8916_desc = {
@@ -3356,18 +3357,16 @@ MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
3356 3357
3357static int gcc_msm8916_probe(struct platform_device *pdev) 3358static int gcc_msm8916_probe(struct platform_device *pdev)
3358{ 3359{
3359 struct clk *clk; 3360 int ret;
3360 struct device *dev = &pdev->dev; 3361 struct device *dev = &pdev->dev;
3361 3362
3362 /* Temporary until RPM clocks supported */ 3363 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3363 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000); 3364 if (ret)
3364 if (IS_ERR(clk)) 3365 return ret;
3365 return PTR_ERR(clk);
3366 3366
3367 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL, 3367 ret = qcom_cc_register_sleep_clk(dev);
3368 CLK_IS_ROOT, 32768); 3368 if (ret)
3369 if (IS_ERR(clk)) 3369 return ret;
3370 return PTR_ERR(clk);
3371 3370
3372 return qcom_cc_probe(pdev, &gcc_msm8916_desc); 3371 return qcom_cc_probe(pdev, &gcc_msm8916_desc);
3373} 3372}
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 66c18bc97857..f31111e32d44 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -3468,6 +3468,7 @@ static const struct regmap_config gcc_msm8960_regmap_config = {
3468 .val_bits = 32, 3468 .val_bits = 32,
3469 .max_register = 0x3660, 3469 .max_register = 0x3660,
3470 .fast_io = true, 3470 .fast_io = true,
3471 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3471}; 3472};
3472 3473
3473static const struct regmap_config gcc_apq8064_regmap_config = { 3474static const struct regmap_config gcc_apq8064_regmap_config = {
@@ -3476,6 +3477,7 @@ static const struct regmap_config gcc_apq8064_regmap_config = {
3476 .val_bits = 32, 3477 .val_bits = 32,
3477 .max_register = 0x3880, 3478 .max_register = 0x3880,
3478 .fast_io = true, 3479 .fast_io = true,
3480 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3479}; 3481};
3480 3482
3481static const struct qcom_cc_desc gcc_msm8960_desc = { 3483static const struct qcom_cc_desc gcc_msm8960_desc = {
@@ -3503,7 +3505,6 @@ MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3503 3505
3504static int gcc_msm8960_probe(struct platform_device *pdev) 3506static int gcc_msm8960_probe(struct platform_device *pdev)
3505{ 3507{
3506 struct clk *clk;
3507 struct device *dev = &pdev->dev; 3508 struct device *dev = &pdev->dev;
3508 const struct of_device_id *match; 3509 const struct of_device_id *match;
3509 struct platform_device *tsens; 3510 struct platform_device *tsens;
@@ -3513,14 +3514,13 @@ static int gcc_msm8960_probe(struct platform_device *pdev)
3513 if (!match) 3514 if (!match)
3514 return -EINVAL; 3515 return -EINVAL;
3515 3516
3516 /* Temporary until RPM clocks supported */ 3517 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3517 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000); 3518 if (ret)
3518 if (IS_ERR(clk)) 3519 return ret;
3519 return PTR_ERR(clk);
3520 3520
3521 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000); 3521 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3522 if (IS_ERR(clk)) 3522 if (ret)
3523 return PTR_ERR(clk); 3523 return ret;
3524 3524
3525 ret = qcom_cc_probe(pdev, match->data); 3525 ret = qcom_cc_probe(pdev, match->data);
3526 if (ret) 3526 if (ret)
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 28abb8f8f293..df164d618e34 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -2680,6 +2680,7 @@ static const struct regmap_config gcc_msm8974_regmap_config = {
2680 .val_bits = 32, 2680 .val_bits = 32,
2681 .max_register = 0x1fc0, 2681 .max_register = 0x1fc0,
2682 .fast_io = true, 2682 .fast_io = true,
2683 .val_format_endian = REGMAP_ENDIAN_LITTLE,
2683}; 2684};
2684 2685
2685static const struct qcom_cc_desc gcc_msm8974_desc = { 2686static const struct qcom_cc_desc gcc_msm8974_desc = {
@@ -2717,7 +2718,7 @@ static void msm8974_pro_clock_override(void)
2717 2718
2718static int gcc_msm8974_probe(struct platform_device *pdev) 2719static int gcc_msm8974_probe(struct platform_device *pdev)
2719{ 2720{
2720 struct clk *clk; 2721 int ret;
2721 struct device *dev = &pdev->dev; 2722 struct device *dev = &pdev->dev;
2722 bool pro; 2723 bool pro;
2723 const struct of_device_id *id; 2724 const struct of_device_id *id;
@@ -2730,16 +2731,13 @@ static int gcc_msm8974_probe(struct platform_device *pdev)
2730 if (pro) 2731 if (pro)
2731 msm8974_pro_clock_override(); 2732 msm8974_pro_clock_override();
2732 2733
2733 /* Temporary until RPM clocks supported */ 2734 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
2734 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000); 2735 if (ret)
2735 if (IS_ERR(clk)) 2736 return ret;
2736 return PTR_ERR(clk);
2737 2737
2738 /* Should move to DT node? */ 2738 ret = qcom_cc_register_sleep_clk(dev);
2739 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL, 2739 if (ret)
2740 CLK_IS_ROOT, 32768); 2740 return ret;
2741 if (IS_ERR(clk))
2742 return PTR_ERR(clk);
2743 2741
2744 return qcom_cc_probe(pdev, &gcc_msm8974_desc); 2742 return qcom_cc_probe(pdev, &gcc_msm8974_desc);
2745} 2743}
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
new file mode 100644
index 000000000000..16d7c323db49
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -0,0 +1,3422 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8996.h>
26
27#include "common.h"
28#include "clk-regmap.h"
29#include "clk-alpha-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
35
36enum {
37 P_XO,
38 P_GPLL0,
39 P_GPLL2,
40 P_GPLL3,
41 P_GPLL1,
42 P_GPLL2_EARLY,
43 P_GPLL0_EARLY_DIV,
44 P_SLEEP_CLK,
45 P_GPLL4,
46 P_AUD_REF_CLK,
47 P_GPLL1_EARLY_DIV
48};
49
50static const struct parent_map gcc_sleep_clk_map[] = {
51 { P_SLEEP_CLK, 5 }
52};
53
54static const char * const gcc_sleep_clk[] = {
55 "sleep_clk"
56};
57
58static const struct parent_map gcc_xo_gpll0_map[] = {
59 { P_XO, 0 },
60 { P_GPLL0, 1 }
61};
62
63static const char * const gcc_xo_gpll0[] = {
64 "xo",
65 "gpll0"
66};
67
68static const struct parent_map gcc_xo_sleep_clk_map[] = {
69 { P_XO, 0 },
70 { P_SLEEP_CLK, 5 }
71};
72
73static const char * const gcc_xo_sleep_clk[] = {
74 "xo",
75 "sleep_clk"
76};
77
78static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
79 { P_XO, 0 },
80 { P_GPLL0, 1 },
81 { P_GPLL0_EARLY_DIV, 6 }
82};
83
84static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
85 "xo",
86 "gpll0",
87 "gpll0_early_div"
88};
89
90static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
91 { P_XO, 0 },
92 { P_GPLL0, 1 },
93 { P_GPLL4, 5 }
94};
95
96static const char * const gcc_xo_gpll0_gpll4[] = {
97 "xo",
98 "gpll0",
99 "gpll4"
100};
101
102static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
103 { P_XO, 0 },
104 { P_GPLL0, 1 },
105 { P_AUD_REF_CLK, 2 }
106};
107
108static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
109 "xo",
110 "gpll0",
111 "aud_ref_clk"
112};
113
114static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
115 { P_XO, 0 },
116 { P_GPLL0, 1 },
117 { P_SLEEP_CLK, 5 },
118 { P_GPLL0_EARLY_DIV, 6 }
119};
120
121static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
122 "xo",
123 "gpll0",
124 "sleep_clk",
125 "gpll0_early_div"
126};
127
128static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
129 { P_XO, 0 },
130 { P_GPLL0, 1 },
131 { P_GPLL4, 5 },
132 { P_GPLL0_EARLY_DIV, 6 }
133};
134
135static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
136 "xo",
137 "gpll0",
138 "gpll4",
139 "gpll0_early_div"
140};
141
142static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = {
143 { P_XO, 0 },
144 { P_GPLL0, 1 },
145 { P_GPLL2, 2 },
146 { P_GPLL3, 3 },
147 { P_GPLL0_EARLY_DIV, 6 }
148};
149
150static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = {
151 "xo",
152 "gpll0",
153 "gpll2",
154 "gpll3",
155 "gpll0_early_div"
156};
157
158static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
159 { P_XO, 0 },
160 { P_GPLL0, 1 },
161 { P_GPLL1_EARLY_DIV, 3 },
162 { P_GPLL1, 4 },
163 { P_GPLL4, 5 },
164 { P_GPLL0_EARLY_DIV, 6 }
165};
166
167static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
168 "xo",
169 "gpll0",
170 "gpll1_early_div",
171 "gpll1",
172 "gpll4",
173 "gpll0_early_div"
174};
175
176static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
177 { P_XO, 0 },
178 { P_GPLL0, 1 },
179 { P_GPLL2, 2 },
180 { P_GPLL3, 3 },
181 { P_GPLL1, 4 },
182 { P_GPLL2_EARLY, 5 },
183 { P_GPLL0_EARLY_DIV, 6 }
184};
185
186static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
187 "xo",
188 "gpll0",
189 "gpll2",
190 "gpll3",
191 "gpll1",
192 "gpll2_early",
193 "gpll0_early_div"
194};
195
196static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = {
197 { P_XO, 0 },
198 { P_GPLL0, 1 },
199 { P_GPLL2, 2 },
200 { P_GPLL3, 3 },
201 { P_GPLL1, 4 },
202 { P_GPLL4, 5 },
203 { P_GPLL0_EARLY_DIV, 6 }
204};
205
206static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
207 "xo",
208 "gpll0",
209 "gpll2",
210 "gpll3",
211 "gpll1",
212 "gpll4",
213 "gpll0_early_div"
214};
215
216static struct clk_fixed_factor xo = {
217 .mult = 1,
218 .div = 1,
219 .hw.init = &(struct clk_init_data){
220 .name = "xo",
221 .parent_names = (const char *[]){ "xo_board" },
222 .num_parents = 1,
223 .ops = &clk_fixed_factor_ops,
224 },
225};
226
227static struct clk_alpha_pll gpll0_early = {
228 .offset = 0x00000,
229 .clkr = {
230 .enable_reg = 0x52000,
231 .enable_mask = BIT(0),
232 .hw.init = &(struct clk_init_data){
233 .name = "gpll0_early",
234 .parent_names = (const char *[]){ "xo" },
235 .num_parents = 1,
236 .ops = &clk_alpha_pll_ops,
237 },
238 },
239};
240
241static struct clk_fixed_factor gpll0_early_div = {
242 .mult = 1,
243 .div = 2,
244 .hw.init = &(struct clk_init_data){
245 .name = "gpll0_early_div",
246 .parent_names = (const char *[]){ "gpll0_early" },
247 .num_parents = 1,
248 .ops = &clk_fixed_factor_ops,
249 },
250};
251
252static struct clk_alpha_pll_postdiv gpll0 = {
253 .offset = 0x00000,
254 .clkr.hw.init = &(struct clk_init_data){
255 .name = "gpll0",
256 .parent_names = (const char *[]){ "gpll0_early" },
257 .num_parents = 1,
258 .ops = &clk_alpha_pll_postdiv_ops,
259 },
260};
261
262static struct clk_alpha_pll gpll4_early = {
263 .offset = 0x77000,
264 .clkr = {
265 .enable_reg = 0x52000,
266 .enable_mask = BIT(4),
267 .hw.init = &(struct clk_init_data){
268 .name = "gpll4_early",
269 .parent_names = (const char *[]){ "xo" },
270 .num_parents = 1,
271 .ops = &clk_alpha_pll_ops,
272 },
273 },
274};
275
276static struct clk_alpha_pll_postdiv gpll4 = {
277 .offset = 0x77000,
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "gpll4",
280 .parent_names = (const char *[]){ "gpll4_early" },
281 .num_parents = 1,
282 .ops = &clk_alpha_pll_postdiv_ops,
283 },
284};
285
286static const struct freq_tbl ftbl_system_noc_clk_src[] = {
287 F(19200000, P_XO, 1, 0, 0),
288 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
289 F(100000000, P_GPLL0, 6, 0, 0),
290 F(150000000, P_GPLL0, 4, 0, 0),
291 F(200000000, P_GPLL0, 3, 0, 0),
292 F(240000000, P_GPLL0, 2.5, 0, 0),
293 { }
294};
295
296static struct clk_rcg2 system_noc_clk_src = {
297 .cmd_rcgr = 0x0401c,
298 .hid_width = 5,
299 .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
300 .freq_tbl = ftbl_system_noc_clk_src,
301 .clkr.hw.init = &(struct clk_init_data){
302 .name = "system_noc_clk_src",
303 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
304 .num_parents = 7,
305 .ops = &clk_rcg2_ops,
306 },
307};
308
309static const struct freq_tbl ftbl_config_noc_clk_src[] = {
310 F(19200000, P_XO, 1, 0, 0),
311 F(37500000, P_GPLL0, 16, 0, 0),
312 F(75000000, P_GPLL0, 8, 0, 0),
313 { }
314};
315
316static struct clk_rcg2 config_noc_clk_src = {
317 .cmd_rcgr = 0x0500c,
318 .hid_width = 5,
319 .parent_map = gcc_xo_gpll0_map,
320 .freq_tbl = ftbl_config_noc_clk_src,
321 .clkr.hw.init = &(struct clk_init_data){
322 .name = "config_noc_clk_src",
323 .parent_names = gcc_xo_gpll0,
324 .num_parents = 2,
325 .ops = &clk_rcg2_ops,
326 },
327};
328
329static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
330 F(19200000, P_XO, 1, 0, 0),
331 F(37500000, P_GPLL0, 16, 0, 0),
332 F(50000000, P_GPLL0, 12, 0, 0),
333 F(75000000, P_GPLL0, 8, 0, 0),
334 F(100000000, P_GPLL0, 6, 0, 0),
335 { }
336};
337
338static struct clk_rcg2 periph_noc_clk_src = {
339 .cmd_rcgr = 0x06014,
340 .hid_width = 5,
341 .parent_map = gcc_xo_gpll0_map,
342 .freq_tbl = ftbl_periph_noc_clk_src,
343 .clkr.hw.init = &(struct clk_init_data){
344 .name = "periph_noc_clk_src",
345 .parent_names = gcc_xo_gpll0,
346 .num_parents = 2,
347 .ops = &clk_rcg2_ops,
348 },
349};
350
351static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
352 F(19200000, P_XO, 1, 0, 0),
353 F(120000000, P_GPLL0, 5, 0, 0),
354 F(150000000, P_GPLL0, 4, 0, 0),
355 { }
356};
357
358static struct clk_rcg2 usb30_master_clk_src = {
359 .cmd_rcgr = 0x0f014,
360 .mnd_width = 8,
361 .hid_width = 5,
362 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
363 .freq_tbl = ftbl_usb30_master_clk_src,
364 .clkr.hw.init = &(struct clk_init_data){
365 .name = "usb30_master_clk_src",
366 .parent_names = gcc_xo_gpll0_gpll0_early_div,
367 .num_parents = 3,
368 .ops = &clk_rcg2_ops,
369 },
370};
371
372static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
373 F(19200000, P_XO, 1, 0, 0),
374 { }
375};
376
377static struct clk_rcg2 usb30_mock_utmi_clk_src = {
378 .cmd_rcgr = 0x0f028,
379 .hid_width = 5,
380 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
381 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
382 .clkr.hw.init = &(struct clk_init_data){
383 .name = "usb30_mock_utmi_clk_src",
384 .parent_names = gcc_xo_gpll0_gpll0_early_div,
385 .num_parents = 3,
386 .ops = &clk_rcg2_ops,
387 },
388};
389
390static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
391 F(1200000, P_XO, 16, 0, 0),
392 { }
393};
394
395static struct clk_rcg2 usb3_phy_aux_clk_src = {
396 .cmd_rcgr = 0x5000c,
397 .hid_width = 5,
398 .parent_map = gcc_xo_sleep_clk_map,
399 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
400 .clkr.hw.init = &(struct clk_init_data){
401 .name = "usb3_phy_aux_clk_src",
402 .parent_names = gcc_xo_sleep_clk,
403 .num_parents = 2,
404 .ops = &clk_rcg2_ops,
405 },
406};
407
408static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
409 F(120000000, P_GPLL0, 5, 0, 0),
410 { }
411};
412
413static struct clk_rcg2 usb20_master_clk_src = {
414 .cmd_rcgr = 0x12010,
415 .mnd_width = 8,
416 .hid_width = 5,
417 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
418 .freq_tbl = ftbl_usb20_master_clk_src,
419 .clkr.hw.init = &(struct clk_init_data){
420 .name = "usb20_master_clk_src",
421 .parent_names = gcc_xo_gpll0_gpll0_early_div,
422 .num_parents = 3,
423 .ops = &clk_rcg2_ops,
424 },
425};
426
427static struct clk_rcg2 usb20_mock_utmi_clk_src = {
428 .cmd_rcgr = 0x12024,
429 .hid_width = 5,
430 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
431 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
432 .clkr.hw.init = &(struct clk_init_data){
433 .name = "usb20_mock_utmi_clk_src",
434 .parent_names = gcc_xo_gpll0_gpll0_early_div,
435 .num_parents = 3,
436 .ops = &clk_rcg2_ops,
437 },
438};
439
440static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
441 F(144000, P_XO, 16, 3, 25),
442 F(400000, P_XO, 12, 1, 4),
443 F(20000000, P_GPLL0, 15, 1, 2),
444 F(25000000, P_GPLL0, 12, 1, 2),
445 F(50000000, P_GPLL0, 12, 0, 0),
446 F(96000000, P_GPLL4, 4, 0, 0),
447 F(192000000, P_GPLL4, 2, 0, 0),
448 F(384000000, P_GPLL4, 1, 0, 0),
449 { }
450};
451
452static struct clk_rcg2 sdcc1_apps_clk_src = {
453 .cmd_rcgr = 0x13010,
454 .mnd_width = 8,
455 .hid_width = 5,
456 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
457 .freq_tbl = ftbl_sdcc1_apps_clk_src,
458 .clkr.hw.init = &(struct clk_init_data){
459 .name = "sdcc1_apps_clk_src",
460 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
461 .num_parents = 4,
462 .ops = &clk_rcg2_ops,
463 },
464};
465
466static struct clk_rcg2 sdcc1_ice_core_clk_src = {
467 .cmd_rcgr = 0x13024,
468 .hid_width = 5,
469 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
470 .clkr.hw.init = &(struct clk_init_data){
471 .name = "sdcc1_ice_core_clk_src",
472 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
473 .num_parents = 4,
474 .ops = &clk_rcg2_ops,
475 },
476};
477
478static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
479 F(144000, P_XO, 16, 3, 25),
480 F(400000, P_XO, 12, 1, 4),
481 F(20000000, P_GPLL0, 15, 1, 2),
482 F(25000000, P_GPLL0, 12, 1, 2),
483 F(50000000, P_GPLL0, 12, 0, 0),
484 F(100000000, P_GPLL0, 6, 0, 0),
485 F(200000000, P_GPLL0, 3, 0, 0),
486 { }
487};
488
489static struct clk_rcg2 sdcc2_apps_clk_src = {
490 .cmd_rcgr = 0x14010,
491 .mnd_width = 8,
492 .hid_width = 5,
493 .parent_map = gcc_xo_gpll0_gpll4_map,
494 .freq_tbl = ftbl_sdcc2_apps_clk_src,
495 .clkr.hw.init = &(struct clk_init_data){
496 .name = "sdcc2_apps_clk_src",
497 .parent_names = gcc_xo_gpll0_gpll4,
498 .num_parents = 3,
499 .ops = &clk_rcg2_ops,
500 },
501};
502
503static struct clk_rcg2 sdcc3_apps_clk_src = {
504 .cmd_rcgr = 0x15010,
505 .mnd_width = 8,
506 .hid_width = 5,
507 .parent_map = gcc_xo_gpll0_gpll4_map,
508 .freq_tbl = ftbl_sdcc2_apps_clk_src,
509 .clkr.hw.init = &(struct clk_init_data){
510 .name = "sdcc3_apps_clk_src",
511 .parent_names = gcc_xo_gpll0_gpll4,
512 .num_parents = 3,
513 .ops = &clk_rcg2_ops,
514 },
515};
516
517static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
518 F(144000, P_XO, 16, 3, 25),
519 F(400000, P_XO, 12, 1, 4),
520 F(20000000, P_GPLL0, 15, 1, 2),
521 F(25000000, P_GPLL0, 12, 1, 2),
522 F(50000000, P_GPLL0, 12, 0, 0),
523 F(100000000, P_GPLL0, 6, 0, 0),
524 { }
525};
526
527static struct clk_rcg2 sdcc4_apps_clk_src = {
528 .cmd_rcgr = 0x16010,
529 .mnd_width = 8,
530 .hid_width = 5,
531 .parent_map = gcc_xo_gpll0_map,
532 .freq_tbl = ftbl_sdcc4_apps_clk_src,
533 .clkr.hw.init = &(struct clk_init_data){
534 .name = "sdcc4_apps_clk_src",
535 .parent_names = gcc_xo_gpll0,
536 .num_parents = 2,
537 .ops = &clk_rcg2_ops,
538 },
539};
540
541static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
542 F(960000, P_XO, 10, 1, 2),
543 F(4800000, P_XO, 4, 0, 0),
544 F(9600000, P_XO, 2, 0, 0),
545 F(15000000, P_GPLL0, 10, 1, 4),
546 F(19200000, P_XO, 1, 0, 0),
547 F(25000000, P_GPLL0, 12, 1, 2),
548 F(50000000, P_GPLL0, 12, 0, 0),
549 { }
550};
551
552static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
553 .cmd_rcgr = 0x1900c,
554 .mnd_width = 8,
555 .hid_width = 5,
556 .parent_map = gcc_xo_gpll0_map,
557 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
558 .clkr.hw.init = &(struct clk_init_data){
559 .name = "blsp1_qup1_spi_apps_clk_src",
560 .parent_names = gcc_xo_gpll0,
561 .num_parents = 2,
562 .ops = &clk_rcg2_ops,
563 },
564};
565
566static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
567 F(19200000, P_XO, 1, 0, 0),
568 F(50000000, P_GPLL0, 12, 0, 0),
569 { }
570};
571
572static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
573 .cmd_rcgr = 0x19020,
574 .hid_width = 5,
575 .parent_map = gcc_xo_gpll0_map,
576 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
577 .clkr.hw.init = &(struct clk_init_data){
578 .name = "blsp1_qup1_i2c_apps_clk_src",
579 .parent_names = gcc_xo_gpll0,
580 .num_parents = 2,
581 .ops = &clk_rcg2_ops,
582 },
583};
584
585static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
586 F(3686400, P_GPLL0, 1, 96, 15625),
587 F(7372800, P_GPLL0, 1, 192, 15625),
588 F(14745600, P_GPLL0, 1, 384, 15625),
589 F(16000000, P_GPLL0, 5, 2, 15),
590 F(19200000, P_XO, 1, 0, 0),
591 F(24000000, P_GPLL0, 5, 1, 5),
592 F(32000000, P_GPLL0, 1, 4, 75),
593 F(40000000, P_GPLL0, 15, 0, 0),
594 F(46400000, P_GPLL0, 1, 29, 375),
595 F(48000000, P_GPLL0, 12.5, 0, 0),
596 F(51200000, P_GPLL0, 1, 32, 375),
597 F(56000000, P_GPLL0, 1, 7, 75),
598 F(58982400, P_GPLL0, 1, 1536, 15625),
599 F(60000000, P_GPLL0, 10, 0, 0),
600 F(63157895, P_GPLL0, 9.5, 0, 0),
601 { }
602};
603
604static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
605 .cmd_rcgr = 0x1a00c,
606 .mnd_width = 16,
607 .hid_width = 5,
608 .parent_map = gcc_xo_gpll0_map,
609 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "blsp1_uart1_apps_clk_src",
612 .parent_names = gcc_xo_gpll0,
613 .num_parents = 2,
614 .ops = &clk_rcg2_ops,
615 },
616};
617
618static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
619 .cmd_rcgr = 0x1b00c,
620 .mnd_width = 8,
621 .hid_width = 5,
622 .parent_map = gcc_xo_gpll0_map,
623 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
624 .clkr.hw.init = &(struct clk_init_data){
625 .name = "blsp1_qup2_spi_apps_clk_src",
626 .parent_names = gcc_xo_gpll0,
627 .num_parents = 2,
628 .ops = &clk_rcg2_ops,
629 },
630};
631
632static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
633 .cmd_rcgr = 0x1b020,
634 .hid_width = 5,
635 .parent_map = gcc_xo_gpll0_map,
636 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
637 .clkr.hw.init = &(struct clk_init_data){
638 .name = "blsp1_qup2_i2c_apps_clk_src",
639 .parent_names = gcc_xo_gpll0,
640 .num_parents = 2,
641 .ops = &clk_rcg2_ops,
642 },
643};
644
645static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
646 .cmd_rcgr = 0x1c00c,
647 .mnd_width = 16,
648 .hid_width = 5,
649 .parent_map = gcc_xo_gpll0_map,
650 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
651 .clkr.hw.init = &(struct clk_init_data){
652 .name = "blsp1_uart2_apps_clk_src",
653 .parent_names = gcc_xo_gpll0,
654 .num_parents = 2,
655 .ops = &clk_rcg2_ops,
656 },
657};
658
659static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
660 .cmd_rcgr = 0x1d00c,
661 .mnd_width = 8,
662 .hid_width = 5,
663 .parent_map = gcc_xo_gpll0_map,
664 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "blsp1_qup3_spi_apps_clk_src",
667 .parent_names = gcc_xo_gpll0,
668 .num_parents = 2,
669 .ops = &clk_rcg2_ops,
670 },
671};
672
673static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
674 .cmd_rcgr = 0x1d020,
675 .hid_width = 5,
676 .parent_map = gcc_xo_gpll0_map,
677 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
678 .clkr.hw.init = &(struct clk_init_data){
679 .name = "blsp1_qup3_i2c_apps_clk_src",
680 .parent_names = gcc_xo_gpll0,
681 .num_parents = 2,
682 .ops = &clk_rcg2_ops,
683 },
684};
685
686static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
687 .cmd_rcgr = 0x1e00c,
688 .mnd_width = 16,
689 .hid_width = 5,
690 .parent_map = gcc_xo_gpll0_map,
691 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "blsp1_uart3_apps_clk_src",
694 .parent_names = gcc_xo_gpll0,
695 .num_parents = 2,
696 .ops = &clk_rcg2_ops,
697 },
698};
699
700static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
701 .cmd_rcgr = 0x1f00c,
702 .mnd_width = 8,
703 .hid_width = 5,
704 .parent_map = gcc_xo_gpll0_map,
705 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
706 .clkr.hw.init = &(struct clk_init_data){
707 .name = "blsp1_qup4_spi_apps_clk_src",
708 .parent_names = gcc_xo_gpll0,
709 .num_parents = 2,
710 .ops = &clk_rcg2_ops,
711 },
712};
713
714static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
715 .cmd_rcgr = 0x1f020,
716 .hid_width = 5,
717 .parent_map = gcc_xo_gpll0_map,
718 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
719 .clkr.hw.init = &(struct clk_init_data){
720 .name = "blsp1_qup4_i2c_apps_clk_src",
721 .parent_names = gcc_xo_gpll0,
722 .num_parents = 2,
723 .ops = &clk_rcg2_ops,
724 },
725};
726
727static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
728 .cmd_rcgr = 0x2000c,
729 .mnd_width = 16,
730 .hid_width = 5,
731 .parent_map = gcc_xo_gpll0_map,
732 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "blsp1_uart4_apps_clk_src",
735 .parent_names = gcc_xo_gpll0,
736 .num_parents = 2,
737 .ops = &clk_rcg2_ops,
738 },
739};
740
741static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
742 .cmd_rcgr = 0x2100c,
743 .mnd_width = 8,
744 .hid_width = 5,
745 .parent_map = gcc_xo_gpll0_map,
746 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "blsp1_qup5_spi_apps_clk_src",
749 .parent_names = gcc_xo_gpll0,
750 .num_parents = 2,
751 .ops = &clk_rcg2_ops,
752 },
753};
754
755static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
756 .cmd_rcgr = 0x21020,
757 .hid_width = 5,
758 .parent_map = gcc_xo_gpll0_map,
759 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "blsp1_qup5_i2c_apps_clk_src",
762 .parent_names = gcc_xo_gpll0,
763 .num_parents = 2,
764 .ops = &clk_rcg2_ops,
765 },
766};
767
768static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
769 .cmd_rcgr = 0x2200c,
770 .mnd_width = 16,
771 .hid_width = 5,
772 .parent_map = gcc_xo_gpll0_map,
773 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "blsp1_uart5_apps_clk_src",
776 .parent_names = gcc_xo_gpll0,
777 .num_parents = 2,
778 .ops = &clk_rcg2_ops,
779 },
780};
781
782static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
783 .cmd_rcgr = 0x2300c,
784 .mnd_width = 8,
785 .hid_width = 5,
786 .parent_map = gcc_xo_gpll0_map,
787 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "blsp1_qup6_spi_apps_clk_src",
790 .parent_names = gcc_xo_gpll0,
791 .num_parents = 2,
792 .ops = &clk_rcg2_ops,
793 },
794};
795
796static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
797 .cmd_rcgr = 0x23020,
798 .hid_width = 5,
799 .parent_map = gcc_xo_gpll0_map,
800 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "blsp1_qup6_i2c_apps_clk_src",
803 .parent_names = gcc_xo_gpll0,
804 .num_parents = 2,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
810 .cmd_rcgr = 0x2400c,
811 .mnd_width = 16,
812 .hid_width = 5,
813 .parent_map = gcc_xo_gpll0_map,
814 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
815 .clkr.hw.init = &(struct clk_init_data){
816 .name = "blsp1_uart6_apps_clk_src",
817 .parent_names = gcc_xo_gpll0,
818 .num_parents = 2,
819 .ops = &clk_rcg2_ops,
820 },
821};
822
823static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
824 .cmd_rcgr = 0x2600c,
825 .mnd_width = 8,
826 .hid_width = 5,
827 .parent_map = gcc_xo_gpll0_map,
828 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
829 .clkr.hw.init = &(struct clk_init_data){
830 .name = "blsp2_qup1_spi_apps_clk_src",
831 .parent_names = gcc_xo_gpll0,
832 .num_parents = 2,
833 .ops = &clk_rcg2_ops,
834 },
835};
836
837static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
838 .cmd_rcgr = 0x26020,
839 .hid_width = 5,
840 .parent_map = gcc_xo_gpll0_map,
841 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
842 .clkr.hw.init = &(struct clk_init_data){
843 .name = "blsp2_qup1_i2c_apps_clk_src",
844 .parent_names = gcc_xo_gpll0,
845 .num_parents = 2,
846 .ops = &clk_rcg2_ops,
847 },
848};
849
850static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
851 .cmd_rcgr = 0x2700c,
852 .mnd_width = 16,
853 .hid_width = 5,
854 .parent_map = gcc_xo_gpll0_map,
855 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
856 .clkr.hw.init = &(struct clk_init_data){
857 .name = "blsp2_uart1_apps_clk_src",
858 .parent_names = gcc_xo_gpll0,
859 .num_parents = 2,
860 .ops = &clk_rcg2_ops,
861 },
862};
863
864static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
865 .cmd_rcgr = 0x2800c,
866 .mnd_width = 8,
867 .hid_width = 5,
868 .parent_map = gcc_xo_gpll0_map,
869 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
870 .clkr.hw.init = &(struct clk_init_data){
871 .name = "blsp2_qup2_spi_apps_clk_src",
872 .parent_names = gcc_xo_gpll0,
873 .num_parents = 2,
874 .ops = &clk_rcg2_ops,
875 },
876};
877
878static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
879 .cmd_rcgr = 0x28020,
880 .hid_width = 5,
881 .parent_map = gcc_xo_gpll0_map,
882 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
883 .clkr.hw.init = &(struct clk_init_data){
884 .name = "blsp2_qup2_i2c_apps_clk_src",
885 .parent_names = gcc_xo_gpll0,
886 .num_parents = 2,
887 .ops = &clk_rcg2_ops,
888 },
889};
890
891static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
892 .cmd_rcgr = 0x2900c,
893 .mnd_width = 16,
894 .hid_width = 5,
895 .parent_map = gcc_xo_gpll0_map,
896 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
897 .clkr.hw.init = &(struct clk_init_data){
898 .name = "blsp2_uart2_apps_clk_src",
899 .parent_names = gcc_xo_gpll0,
900 .num_parents = 2,
901 .ops = &clk_rcg2_ops,
902 },
903};
904
905static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
906 .cmd_rcgr = 0x2a00c,
907 .mnd_width = 8,
908 .hid_width = 5,
909 .parent_map = gcc_xo_gpll0_map,
910 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
911 .clkr.hw.init = &(struct clk_init_data){
912 .name = "blsp2_qup3_spi_apps_clk_src",
913 .parent_names = gcc_xo_gpll0,
914 .num_parents = 2,
915 .ops = &clk_rcg2_ops,
916 },
917};
918
919static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
920 .cmd_rcgr = 0x2a020,
921 .hid_width = 5,
922 .parent_map = gcc_xo_gpll0_map,
923 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "blsp2_qup3_i2c_apps_clk_src",
926 .parent_names = gcc_xo_gpll0,
927 .num_parents = 2,
928 .ops = &clk_rcg2_ops,
929 },
930};
931
932static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
933 .cmd_rcgr = 0x2b00c,
934 .mnd_width = 16,
935 .hid_width = 5,
936 .parent_map = gcc_xo_gpll0_map,
937 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "blsp2_uart3_apps_clk_src",
940 .parent_names = gcc_xo_gpll0,
941 .num_parents = 2,
942 .ops = &clk_rcg2_ops,
943 },
944};
945
946static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
947 .cmd_rcgr = 0x2c00c,
948 .mnd_width = 8,
949 .hid_width = 5,
950 .parent_map = gcc_xo_gpll0_map,
951 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
952 .clkr.hw.init = &(struct clk_init_data){
953 .name = "blsp2_qup4_spi_apps_clk_src",
954 .parent_names = gcc_xo_gpll0,
955 .num_parents = 2,
956 .ops = &clk_rcg2_ops,
957 },
958};
959
960static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
961 .cmd_rcgr = 0x2c020,
962 .hid_width = 5,
963 .parent_map = gcc_xo_gpll0_map,
964 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
965 .clkr.hw.init = &(struct clk_init_data){
966 .name = "blsp2_qup4_i2c_apps_clk_src",
967 .parent_names = gcc_xo_gpll0,
968 .num_parents = 2,
969 .ops = &clk_rcg2_ops,
970 },
971};
972
973static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
974 .cmd_rcgr = 0x2d00c,
975 .mnd_width = 16,
976 .hid_width = 5,
977 .parent_map = gcc_xo_gpll0_map,
978 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
979 .clkr.hw.init = &(struct clk_init_data){
980 .name = "blsp2_uart4_apps_clk_src",
981 .parent_names = gcc_xo_gpll0,
982 .num_parents = 2,
983 .ops = &clk_rcg2_ops,
984 },
985};
986
987static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
988 .cmd_rcgr = 0x2e00c,
989 .mnd_width = 8,
990 .hid_width = 5,
991 .parent_map = gcc_xo_gpll0_map,
992 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
993 .clkr.hw.init = &(struct clk_init_data){
994 .name = "blsp2_qup5_spi_apps_clk_src",
995 .parent_names = gcc_xo_gpll0,
996 .num_parents = 2,
997 .ops = &clk_rcg2_ops,
998 },
999};
1000
1001static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
1002 .cmd_rcgr = 0x2e020,
1003 .hid_width = 5,
1004 .parent_map = gcc_xo_gpll0_map,
1005 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1006 .clkr.hw.init = &(struct clk_init_data){
1007 .name = "blsp2_qup5_i2c_apps_clk_src",
1008 .parent_names = gcc_xo_gpll0,
1009 .num_parents = 2,
1010 .ops = &clk_rcg2_ops,
1011 },
1012};
1013
1014static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
1015 .cmd_rcgr = 0x2f00c,
1016 .mnd_width = 16,
1017 .hid_width = 5,
1018 .parent_map = gcc_xo_gpll0_map,
1019 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1020 .clkr.hw.init = &(struct clk_init_data){
1021 .name = "blsp2_uart5_apps_clk_src",
1022 .parent_names = gcc_xo_gpll0,
1023 .num_parents = 2,
1024 .ops = &clk_rcg2_ops,
1025 },
1026};
1027
1028static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1029 .cmd_rcgr = 0x3000c,
1030 .mnd_width = 8,
1031 .hid_width = 5,
1032 .parent_map = gcc_xo_gpll0_map,
1033 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1034 .clkr.hw.init = &(struct clk_init_data){
1035 .name = "blsp2_qup6_spi_apps_clk_src",
1036 .parent_names = gcc_xo_gpll0,
1037 .num_parents = 2,
1038 .ops = &clk_rcg2_ops,
1039 },
1040};
1041
1042static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1043 .cmd_rcgr = 0x30020,
1044 .hid_width = 5,
1045 .parent_map = gcc_xo_gpll0_map,
1046 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1047 .clkr.hw.init = &(struct clk_init_data){
1048 .name = "blsp2_qup6_i2c_apps_clk_src",
1049 .parent_names = gcc_xo_gpll0,
1050 .num_parents = 2,
1051 .ops = &clk_rcg2_ops,
1052 },
1053};
1054
1055static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1056 .cmd_rcgr = 0x3100c,
1057 .mnd_width = 16,
1058 .hid_width = 5,
1059 .parent_map = gcc_xo_gpll0_map,
1060 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1061 .clkr.hw.init = &(struct clk_init_data){
1062 .name = "blsp2_uart6_apps_clk_src",
1063 .parent_names = gcc_xo_gpll0,
1064 .num_parents = 2,
1065 .ops = &clk_rcg2_ops,
1066 },
1067};
1068
1069static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1070 F(60000000, P_GPLL0, 10, 0, 0),
1071 { }
1072};
1073
1074static struct clk_rcg2 pdm2_clk_src = {
1075 .cmd_rcgr = 0x33010,
1076 .hid_width = 5,
1077 .parent_map = gcc_xo_gpll0_map,
1078 .freq_tbl = ftbl_pdm2_clk_src,
1079 .clkr.hw.init = &(struct clk_init_data){
1080 .name = "pdm2_clk_src",
1081 .parent_names = gcc_xo_gpll0,
1082 .num_parents = 2,
1083 .ops = &clk_rcg2_ops,
1084 },
1085};
1086
1087static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1088 F(105495, P_XO, 1, 1, 182),
1089 { }
1090};
1091
1092static struct clk_rcg2 tsif_ref_clk_src = {
1093 .cmd_rcgr = 0x36010,
1094 .mnd_width = 8,
1095 .hid_width = 5,
1096 .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1097 .freq_tbl = ftbl_tsif_ref_clk_src,
1098 .clkr.hw.init = &(struct clk_init_data){
1099 .name = "tsif_ref_clk_src",
1100 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1101 .num_parents = 3,
1102 .ops = &clk_rcg2_ops,
1103 },
1104};
1105
1106static struct clk_rcg2 gcc_sleep_clk_src = {
1107 .cmd_rcgr = 0x43014,
1108 .hid_width = 5,
1109 .parent_map = gcc_sleep_clk_map,
1110 .clkr.hw.init = &(struct clk_init_data){
1111 .name = "gcc_sleep_clk_src",
1112 .parent_names = gcc_sleep_clk,
1113 .num_parents = 1,
1114 .ops = &clk_rcg2_ops,
1115 },
1116};
1117
1118static struct clk_rcg2 hmss_rbcpr_clk_src = {
1119 .cmd_rcgr = 0x48040,
1120 .hid_width = 5,
1121 .parent_map = gcc_xo_gpll0_map,
1122 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1123 .clkr.hw.init = &(struct clk_init_data){
1124 .name = "hmss_rbcpr_clk_src",
1125 .parent_names = gcc_xo_gpll0,
1126 .num_parents = 2,
1127 .ops = &clk_rcg2_ops,
1128 },
1129};
1130
1131static struct clk_rcg2 hmss_gpll0_clk_src = {
1132 .cmd_rcgr = 0x48058,
1133 .hid_width = 5,
1134 .parent_map = gcc_xo_gpll0_map,
1135 .clkr.hw.init = &(struct clk_init_data){
1136 .name = "hmss_gpll0_clk_src",
1137 .parent_names = gcc_xo_gpll0,
1138 .num_parents = 2,
1139 .ops = &clk_rcg2_ops,
1140 },
1141};
1142
1143static const struct freq_tbl ftbl_gp1_clk_src[] = {
1144 F(19200000, P_XO, 1, 0, 0),
1145 F(100000000, P_GPLL0, 6, 0, 0),
1146 F(200000000, P_GPLL0, 3, 0, 0),
1147 { }
1148};
1149
1150static struct clk_rcg2 gp1_clk_src = {
1151 .cmd_rcgr = 0x64004,
1152 .mnd_width = 8,
1153 .hid_width = 5,
1154 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1155 .freq_tbl = ftbl_gp1_clk_src,
1156 .clkr.hw.init = &(struct clk_init_data){
1157 .name = "gp1_clk_src",
1158 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1159 .num_parents = 4,
1160 .ops = &clk_rcg2_ops,
1161 },
1162};
1163
1164static struct clk_rcg2 gp2_clk_src = {
1165 .cmd_rcgr = 0x65004,
1166 .mnd_width = 8,
1167 .hid_width = 5,
1168 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1169 .freq_tbl = ftbl_gp1_clk_src,
1170 .clkr.hw.init = &(struct clk_init_data){
1171 .name = "gp2_clk_src",
1172 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1173 .num_parents = 4,
1174 .ops = &clk_rcg2_ops,
1175 },
1176};
1177
1178static struct clk_rcg2 gp3_clk_src = {
1179 .cmd_rcgr = 0x66004,
1180 .mnd_width = 8,
1181 .hid_width = 5,
1182 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1183 .freq_tbl = ftbl_gp1_clk_src,
1184 .clkr.hw.init = &(struct clk_init_data){
1185 .name = "gp3_clk_src",
1186 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1187 .num_parents = 4,
1188 .ops = &clk_rcg2_ops,
1189 },
1190};
1191
1192static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1193 F(1010526, P_XO, 1, 1, 19),
1194 { }
1195};
1196
1197static struct clk_rcg2 pcie_aux_clk_src = {
1198 .cmd_rcgr = 0x6c000,
1199 .mnd_width = 16,
1200 .hid_width = 5,
1201 .parent_map = gcc_xo_sleep_clk_map,
1202 .freq_tbl = ftbl_pcie_aux_clk_src,
1203 .clkr.hw.init = &(struct clk_init_data){
1204 .name = "pcie_aux_clk_src",
1205 .parent_names = gcc_xo_sleep_clk,
1206 .num_parents = 2,
1207 .ops = &clk_rcg2_ops,
1208 },
1209};
1210
1211static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1212 F(100000000, P_GPLL0, 6, 0, 0),
1213 F(200000000, P_GPLL0, 3, 0, 0),
1214 F(240000000, P_GPLL0, 2.5, 0, 0),
1215 { }
1216};
1217
1218static struct clk_rcg2 ufs_axi_clk_src = {
1219 .cmd_rcgr = 0x75024,
1220 .mnd_width = 8,
1221 .hid_width = 5,
1222 .parent_map = gcc_xo_gpll0_map,
1223 .freq_tbl = ftbl_ufs_axi_clk_src,
1224 .clkr.hw.init = &(struct clk_init_data){
1225 .name = "ufs_axi_clk_src",
1226 .parent_names = gcc_xo_gpll0,
1227 .num_parents = 2,
1228 .ops = &clk_rcg2_ops,
1229 },
1230};
1231
1232static struct clk_rcg2 ufs_ice_core_clk_src = {
1233 .cmd_rcgr = 0x76014,
1234 .hid_width = 5,
1235 .parent_map = gcc_xo_gpll0_map,
1236 .clkr.hw.init = &(struct clk_init_data){
1237 .name = "ufs_ice_core_clk_src",
1238 .parent_names = gcc_xo_gpll0,
1239 .num_parents = 2,
1240 .ops = &clk_rcg2_ops,
1241 },
1242};
1243
1244static struct clk_rcg2 qspi_ser_clk_src = {
1245 .cmd_rcgr = 0x8b00c,
1246 .hid_width = 5,
1247 .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1248 .clkr.hw.init = &(struct clk_init_data){
1249 .name = "qspi_ser_clk_src",
1250 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1251 .num_parents = 6,
1252 .ops = &clk_rcg2_ops,
1253 },
1254};
1255
1256static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1257 .halt_reg = 0x0f03c,
1258 .clkr = {
1259 .enable_reg = 0x0f03c,
1260 .enable_mask = BIT(0),
1261 .hw.init = &(struct clk_init_data){
1262 .name = "gcc_sys_noc_usb3_axi_clk",
1263 .parent_names = (const char *[]){ "usb30_master_clk_src" },
1264 .num_parents = 1,
1265 .flags = CLK_SET_RATE_PARENT,
1266 .ops = &clk_branch2_ops,
1267 },
1268 },
1269};
1270
1271static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1272 .halt_reg = 0x75038,
1273 .clkr = {
1274 .enable_reg = 0x75038,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gcc_sys_noc_ufs_axi_clk",
1278 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1279 .num_parents = 1,
1280 .flags = CLK_SET_RATE_PARENT,
1281 .ops = &clk_branch2_ops,
1282 },
1283 },
1284};
1285
1286static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1287 .halt_reg = 0x6010,
1288 .clkr = {
1289 .enable_reg = 0x6010,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "gcc_periph_noc_usb20_ahb_clk",
1293 .parent_names = (const char *[]){ "usb20_master_clk_src" },
1294 .num_parents = 1,
1295 .flags = CLK_SET_RATE_PARENT,
1296 .ops = &clk_branch2_ops,
1297 },
1298 },
1299};
1300
1301static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1302 .halt_reg = 0x9008,
1303 .clkr = {
1304 .enable_reg = 0x9008,
1305 .enable_mask = BIT(0),
1306 .hw.init = &(struct clk_init_data){
1307 .name = "gcc_mmss_noc_cfg_ahb_clk",
1308 .parent_names = (const char *[]){ "config_noc_clk_src" },
1309 .num_parents = 1,
1310 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1311 .ops = &clk_branch2_ops,
1312 },
1313 },
1314};
1315
1316static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1317 .halt_reg = 0x9010,
1318 .clkr = {
1319 .enable_reg = 0x9010,
1320 .enable_mask = BIT(0),
1321 .hw.init = &(struct clk_init_data){
1322 .name = "gcc_mmss_bimc_gfx_clk",
1323 .flags = CLK_SET_RATE_PARENT | CLK_IS_ROOT,
1324 .ops = &clk_branch2_ops,
1325 },
1326 },
1327};
1328
1329static struct clk_branch gcc_usb30_master_clk = {
1330 .halt_reg = 0x0f008,
1331 .clkr = {
1332 .enable_reg = 0x0f008,
1333 .enable_mask = BIT(0),
1334 .hw.init = &(struct clk_init_data){
1335 .name = "gcc_usb30_master_clk",
1336 .parent_names = (const char *[]){ "usb30_master_clk_src" },
1337 .num_parents = 1,
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342};
1343
1344static struct clk_branch gcc_usb30_sleep_clk = {
1345 .halt_reg = 0x0f00c,
1346 .clkr = {
1347 .enable_reg = 0x0f00c,
1348 .enable_mask = BIT(0),
1349 .hw.init = &(struct clk_init_data){
1350 .name = "gcc_usb30_sleep_clk",
1351 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1352 .num_parents = 1,
1353 .flags = CLK_SET_RATE_PARENT,
1354 .ops = &clk_branch2_ops,
1355 },
1356 },
1357};
1358
1359static struct clk_branch gcc_usb30_mock_utmi_clk = {
1360 .halt_reg = 0x0f010,
1361 .clkr = {
1362 .enable_reg = 0x0f010,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gcc_usb30_mock_utmi_clk",
1366 .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1367 .num_parents = 1,
1368 .flags = CLK_SET_RATE_PARENT,
1369 .ops = &clk_branch2_ops,
1370 },
1371 },
1372};
1373
1374static struct clk_branch gcc_usb3_phy_aux_clk = {
1375 .halt_reg = 0x50000,
1376 .clkr = {
1377 .enable_reg = 0x50000,
1378 .enable_mask = BIT(0),
1379 .hw.init = &(struct clk_init_data){
1380 .name = "gcc_usb3_phy_aux_clk",
1381 .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1382 .num_parents = 1,
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1385 },
1386 },
1387};
1388
1389static struct clk_branch gcc_usb3_phy_pipe_clk = {
1390 .halt_reg = 0x50004,
1391 .clkr = {
1392 .enable_reg = 0x50004,
1393 .enable_mask = BIT(0),
1394 .hw.init = &(struct clk_init_data){
1395 .name = "gcc_usb3_phy_pipe_clk",
1396 .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1397 .num_parents = 1,
1398 .flags = CLK_SET_RATE_PARENT,
1399 .ops = &clk_branch2_ops,
1400 },
1401 },
1402};
1403
1404static struct clk_branch gcc_usb20_master_clk = {
1405 .halt_reg = 0x12004,
1406 .clkr = {
1407 .enable_reg = 0x12004,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gcc_usb20_master_clk",
1411 .parent_names = (const char *[]){ "usb20_master_clk_src" },
1412 .num_parents = 1,
1413 .flags = CLK_SET_RATE_PARENT,
1414 .ops = &clk_branch2_ops,
1415 },
1416 },
1417};
1418
1419static struct clk_branch gcc_usb20_sleep_clk = {
1420 .halt_reg = 0x12008,
1421 .clkr = {
1422 .enable_reg = 0x12008,
1423 .enable_mask = BIT(0),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "gcc_usb20_sleep_clk",
1426 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1427 .num_parents = 1,
1428 .flags = CLK_SET_RATE_PARENT,
1429 .ops = &clk_branch2_ops,
1430 },
1431 },
1432};
1433
1434static struct clk_branch gcc_usb20_mock_utmi_clk = {
1435 .halt_reg = 0x1200c,
1436 .clkr = {
1437 .enable_reg = 0x1200c,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "gcc_usb20_mock_utmi_clk",
1441 .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1442 .num_parents = 1,
1443 .flags = CLK_SET_RATE_PARENT,
1444 .ops = &clk_branch2_ops,
1445 },
1446 },
1447};
1448
1449static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1450 .halt_reg = 0x6a004,
1451 .clkr = {
1452 .enable_reg = 0x6a004,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1456 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1457 .num_parents = 1,
1458 .flags = CLK_SET_RATE_PARENT,
1459 .ops = &clk_branch2_ops,
1460 },
1461 },
1462};
1463
1464static struct clk_branch gcc_sdcc1_apps_clk = {
1465 .halt_reg = 0x13004,
1466 .clkr = {
1467 .enable_reg = 0x13004,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "gcc_sdcc1_apps_clk",
1471 .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1472 .num_parents = 1,
1473 .flags = CLK_SET_RATE_PARENT,
1474 .ops = &clk_branch2_ops,
1475 },
1476 },
1477};
1478
1479static struct clk_branch gcc_sdcc1_ahb_clk = {
1480 .halt_reg = 0x13008,
1481 .clkr = {
1482 .enable_reg = 0x13008,
1483 .enable_mask = BIT(0),
1484 .hw.init = &(struct clk_init_data){
1485 .name = "gcc_sdcc1_ahb_clk",
1486 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1487 .num_parents = 1,
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1490 },
1491 },
1492};
1493
1494static struct clk_branch gcc_sdcc1_ice_core_clk = {
1495 .halt_reg = 0x13038,
1496 .clkr = {
1497 .enable_reg = 0x13038,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "gcc_sdcc1_ice_core_clk",
1501 .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1502 .num_parents = 1,
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1505 },
1506 },
1507};
1508
1509static struct clk_branch gcc_sdcc2_apps_clk = {
1510 .halt_reg = 0x14004,
1511 .clkr = {
1512 .enable_reg = 0x14004,
1513 .enable_mask = BIT(0),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "gcc_sdcc2_apps_clk",
1516 .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1517 .num_parents = 1,
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522};
1523
1524static struct clk_branch gcc_sdcc2_ahb_clk = {
1525 .halt_reg = 0x14008,
1526 .clkr = {
1527 .enable_reg = 0x14008,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "gcc_sdcc2_ahb_clk",
1531 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1532 .num_parents = 1,
1533 .flags = CLK_SET_RATE_PARENT,
1534 .ops = &clk_branch2_ops,
1535 },
1536 },
1537};
1538
1539static struct clk_branch gcc_sdcc3_apps_clk = {
1540 .halt_reg = 0x15004,
1541 .clkr = {
1542 .enable_reg = 0x15004,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_sdcc3_apps_clk",
1546 .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1547 .num_parents = 1,
1548 .flags = CLK_SET_RATE_PARENT,
1549 .ops = &clk_branch2_ops,
1550 },
1551 },
1552};
1553
1554static struct clk_branch gcc_sdcc3_ahb_clk = {
1555 .halt_reg = 0x15008,
1556 .clkr = {
1557 .enable_reg = 0x15008,
1558 .enable_mask = BIT(0),
1559 .hw.init = &(struct clk_init_data){
1560 .name = "gcc_sdcc3_ahb_clk",
1561 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1562 .num_parents = 1,
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1565 },
1566 },
1567};
1568
1569static struct clk_branch gcc_sdcc4_apps_clk = {
1570 .halt_reg = 0x16004,
1571 .clkr = {
1572 .enable_reg = 0x16004,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_sdcc4_apps_clk",
1576 .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1577 .num_parents = 1,
1578 .flags = CLK_SET_RATE_PARENT,
1579 .ops = &clk_branch2_ops,
1580 },
1581 },
1582};
1583
1584static struct clk_branch gcc_sdcc4_ahb_clk = {
1585 .halt_reg = 0x16008,
1586 .clkr = {
1587 .enable_reg = 0x16008,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "gcc_sdcc4_ahb_clk",
1591 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1592 .num_parents = 1,
1593 .flags = CLK_SET_RATE_PARENT,
1594 .ops = &clk_branch2_ops,
1595 },
1596 },
1597};
1598
1599static struct clk_branch gcc_blsp1_ahb_clk = {
1600 .halt_reg = 0x17004,
1601 .halt_check = BRANCH_HALT_VOTED,
1602 .clkr = {
1603 .enable_reg = 0x52004,
1604 .enable_mask = BIT(17),
1605 .hw.init = &(struct clk_init_data){
1606 .name = "gcc_blsp1_ahb_clk",
1607 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1608 .num_parents = 1,
1609 .flags = CLK_SET_RATE_PARENT,
1610 .ops = &clk_branch2_ops,
1611 },
1612 },
1613};
1614
1615static struct clk_branch gcc_blsp1_sleep_clk = {
1616 .halt_reg = 0x17008,
1617 .halt_check = BRANCH_HALT_VOTED,
1618 .clkr = {
1619 .enable_reg = 0x52004,
1620 .enable_mask = BIT(16),
1621 .hw.init = &(struct clk_init_data){
1622 .name = "gcc_blsp1_sleep_clk",
1623 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629};
1630
1631static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1632 .halt_reg = 0x19004,
1633 .clkr = {
1634 .enable_reg = 0x19004,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "gcc_blsp1_qup1_spi_apps_clk",
1638 .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1639 .num_parents = 1,
1640 .flags = CLK_SET_RATE_PARENT,
1641 .ops = &clk_branch2_ops,
1642 },
1643 },
1644};
1645
1646static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1647 .halt_reg = 0x19008,
1648 .clkr = {
1649 .enable_reg = 0x19008,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1653 .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1654 .num_parents = 1,
1655 .flags = CLK_SET_RATE_PARENT,
1656 .ops = &clk_branch2_ops,
1657 },
1658 },
1659};
1660
1661static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1662 .halt_reg = 0x1a004,
1663 .clkr = {
1664 .enable_reg = 0x1a004,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "gcc_blsp1_uart1_apps_clk",
1668 .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1669 .num_parents = 1,
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1672 },
1673 },
1674};
1675
1676static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1677 .halt_reg = 0x1b004,
1678 .clkr = {
1679 .enable_reg = 0x1b004,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gcc_blsp1_qup2_spi_apps_clk",
1683 .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1684 .num_parents = 1,
1685 .flags = CLK_SET_RATE_PARENT,
1686 .ops = &clk_branch2_ops,
1687 },
1688 },
1689};
1690
1691static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1692 .halt_reg = 0x1b008,
1693 .clkr = {
1694 .enable_reg = 0x1b008,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1698 .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1699 .num_parents = 1,
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1702 },
1703 },
1704};
1705
1706static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1707 .halt_reg = 0x1c004,
1708 .clkr = {
1709 .enable_reg = 0x1c004,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "gcc_blsp1_uart2_apps_clk",
1713 .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1714 .num_parents = 1,
1715 .flags = CLK_SET_RATE_PARENT,
1716 .ops = &clk_branch2_ops,
1717 },
1718 },
1719};
1720
1721static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1722 .halt_reg = 0x1d004,
1723 .clkr = {
1724 .enable_reg = 0x1d004,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "gcc_blsp1_qup3_spi_apps_clk",
1728 .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1729 .num_parents = 1,
1730 .flags = CLK_SET_RATE_PARENT,
1731 .ops = &clk_branch2_ops,
1732 },
1733 },
1734};
1735
1736static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1737 .halt_reg = 0x1d008,
1738 .clkr = {
1739 .enable_reg = 0x1d008,
1740 .enable_mask = BIT(0),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1743 .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1744 .num_parents = 1,
1745 .flags = CLK_SET_RATE_PARENT,
1746 .ops = &clk_branch2_ops,
1747 },
1748 },
1749};
1750
1751static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1752 .halt_reg = 0x1e004,
1753 .clkr = {
1754 .enable_reg = 0x1e004,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "gcc_blsp1_uart3_apps_clk",
1758 .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1759 .num_parents = 1,
1760 .flags = CLK_SET_RATE_PARENT,
1761 .ops = &clk_branch2_ops,
1762 },
1763 },
1764};
1765
1766static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1767 .halt_reg = 0x1f004,
1768 .clkr = {
1769 .enable_reg = 0x1f004,
1770 .enable_mask = BIT(0),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "gcc_blsp1_qup4_spi_apps_clk",
1773 .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1774 .num_parents = 1,
1775 .flags = CLK_SET_RATE_PARENT,
1776 .ops = &clk_branch2_ops,
1777 },
1778 },
1779};
1780
1781static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1782 .halt_reg = 0x1f008,
1783 .clkr = {
1784 .enable_reg = 0x1f008,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1788 .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1789 .num_parents = 1,
1790 .flags = CLK_SET_RATE_PARENT,
1791 .ops = &clk_branch2_ops,
1792 },
1793 },
1794};
1795
1796static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1797 .halt_reg = 0x20004,
1798 .clkr = {
1799 .enable_reg = 0x20004,
1800 .enable_mask = BIT(0),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "gcc_blsp1_uart4_apps_clk",
1803 .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1804 .num_parents = 1,
1805 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops,
1807 },
1808 },
1809};
1810
1811static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1812 .halt_reg = 0x21004,
1813 .clkr = {
1814 .enable_reg = 0x21004,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "gcc_blsp1_qup5_spi_apps_clk",
1818 .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1819 .num_parents = 1,
1820 .flags = CLK_SET_RATE_PARENT,
1821 .ops = &clk_branch2_ops,
1822 },
1823 },
1824};
1825
1826static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1827 .halt_reg = 0x21008,
1828 .clkr = {
1829 .enable_reg = 0x21008,
1830 .enable_mask = BIT(0),
1831 .hw.init = &(struct clk_init_data){
1832 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1833 .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1834 .num_parents = 1,
1835 .flags = CLK_SET_RATE_PARENT,
1836 .ops = &clk_branch2_ops,
1837 },
1838 },
1839};
1840
1841static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1842 .halt_reg = 0x22004,
1843 .clkr = {
1844 .enable_reg = 0x22004,
1845 .enable_mask = BIT(0),
1846 .hw.init = &(struct clk_init_data){
1847 .name = "gcc_blsp1_uart5_apps_clk",
1848 .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1849 .num_parents = 1,
1850 .flags = CLK_SET_RATE_PARENT,
1851 .ops = &clk_branch2_ops,
1852 },
1853 },
1854};
1855
1856static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1857 .halt_reg = 0x23004,
1858 .clkr = {
1859 .enable_reg = 0x23004,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_blsp1_qup6_spi_apps_clk",
1863 .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1864 .num_parents = 1,
1865 .flags = CLK_SET_RATE_PARENT,
1866 .ops = &clk_branch2_ops,
1867 },
1868 },
1869};
1870
1871static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1872 .halt_reg = 0x23008,
1873 .clkr = {
1874 .enable_reg = 0x23008,
1875 .enable_mask = BIT(0),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1878 .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1879 .num_parents = 1,
1880 .flags = CLK_SET_RATE_PARENT,
1881 .ops = &clk_branch2_ops,
1882 },
1883 },
1884};
1885
1886static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1887 .halt_reg = 0x24004,
1888 .clkr = {
1889 .enable_reg = 0x24004,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "gcc_blsp1_uart6_apps_clk",
1893 .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1894 .num_parents = 1,
1895 .flags = CLK_SET_RATE_PARENT,
1896 .ops = &clk_branch2_ops,
1897 },
1898 },
1899};
1900
1901static struct clk_branch gcc_blsp2_ahb_clk = {
1902 .halt_reg = 0x25004,
1903 .halt_check = BRANCH_HALT_VOTED,
1904 .clkr = {
1905 .enable_reg = 0x52004,
1906 .enable_mask = BIT(15),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "gcc_blsp2_ahb_clk",
1909 .parent_names = (const char *[]){ "periph_noc_clk_src" },
1910 .num_parents = 1,
1911 .flags = CLK_SET_RATE_PARENT,
1912 .ops = &clk_branch2_ops,
1913 },
1914 },
1915};
1916
1917static struct clk_branch gcc_blsp2_sleep_clk = {
1918 .halt_reg = 0x25008,
1919 .halt_check = BRANCH_HALT_VOTED,
1920 .clkr = {
1921 .enable_reg = 0x52004,
1922 .enable_mask = BIT(14),
1923 .hw.init = &(struct clk_init_data){
1924 .name = "gcc_blsp2_sleep_clk",
1925 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1926 .num_parents = 1,
1927 .flags = CLK_SET_RATE_PARENT,
1928 .ops = &clk_branch2_ops,
1929 },
1930 },
1931};
1932
1933static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1934 .halt_reg = 0x26004,
1935 .clkr = {
1936 .enable_reg = 0x26004,
1937 .enable_mask = BIT(0),
1938 .hw.init = &(struct clk_init_data){
1939 .name = "gcc_blsp2_qup1_spi_apps_clk",
1940 .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1941 .num_parents = 1,
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1944 },
1945 },
1946};
1947
1948static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1949 .halt_reg = 0x26008,
1950 .clkr = {
1951 .enable_reg = 0x26008,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1955 .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1956 .num_parents = 1,
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1959 },
1960 },
1961};
1962
1963static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1964 .halt_reg = 0x27004,
1965 .clkr = {
1966 .enable_reg = 0x27004,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "gcc_blsp2_uart1_apps_clk",
1970 .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
1971 .num_parents = 1,
1972 .flags = CLK_SET_RATE_PARENT,
1973 .ops = &clk_branch2_ops,
1974 },
1975 },
1976};
1977
1978static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1979 .halt_reg = 0x28004,
1980 .clkr = {
1981 .enable_reg = 0x28004,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "gcc_blsp2_qup2_spi_apps_clk",
1985 .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
1986 .num_parents = 1,
1987 .flags = CLK_SET_RATE_PARENT,
1988 .ops = &clk_branch2_ops,
1989 },
1990 },
1991};
1992
1993static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1994 .halt_reg = 0x28008,
1995 .clkr = {
1996 .enable_reg = 0x28008,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "gcc_blsp2_qup2_i2c_apps_clk",
2000 .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
2001 .num_parents = 1,
2002 .flags = CLK_SET_RATE_PARENT,
2003 .ops = &clk_branch2_ops,
2004 },
2005 },
2006};
2007
2008static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2009 .halt_reg = 0x29004,
2010 .clkr = {
2011 .enable_reg = 0x29004,
2012 .enable_mask = BIT(0),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "gcc_blsp2_uart2_apps_clk",
2015 .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2016 .num_parents = 1,
2017 .flags = CLK_SET_RATE_PARENT,
2018 .ops = &clk_branch2_ops,
2019 },
2020 },
2021};
2022
2023static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2024 .halt_reg = 0x2a004,
2025 .clkr = {
2026 .enable_reg = 0x2a004,
2027 .enable_mask = BIT(0),
2028 .hw.init = &(struct clk_init_data){
2029 .name = "gcc_blsp2_qup3_spi_apps_clk",
2030 .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2031 .num_parents = 1,
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2039 .halt_reg = 0x2a008,
2040 .clkr = {
2041 .enable_reg = 0x2a008,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "gcc_blsp2_qup3_i2c_apps_clk",
2045 .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2046 .num_parents = 1,
2047 .flags = CLK_SET_RATE_PARENT,
2048 .ops = &clk_branch2_ops,
2049 },
2050 },
2051};
2052
2053static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2054 .halt_reg = 0x2b004,
2055 .clkr = {
2056 .enable_reg = 0x2b004,
2057 .enable_mask = BIT(0),
2058 .hw.init = &(struct clk_init_data){
2059 .name = "gcc_blsp2_uart3_apps_clk",
2060 .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2061 .num_parents = 1,
2062 .flags = CLK_SET_RATE_PARENT,
2063 .ops = &clk_branch2_ops,
2064 },
2065 },
2066};
2067
2068static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2069 .halt_reg = 0x2c004,
2070 .clkr = {
2071 .enable_reg = 0x2c004,
2072 .enable_mask = BIT(0),
2073 .hw.init = &(struct clk_init_data){
2074 .name = "gcc_blsp2_qup4_spi_apps_clk",
2075 .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2076 .num_parents = 1,
2077 .flags = CLK_SET_RATE_PARENT,
2078 .ops = &clk_branch2_ops,
2079 },
2080 },
2081};
2082
2083static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2084 .halt_reg = 0x2c008,
2085 .clkr = {
2086 .enable_reg = 0x2c008,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "gcc_blsp2_qup4_i2c_apps_clk",
2090 .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2091 .num_parents = 1,
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096};
2097
2098static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2099 .halt_reg = 0x2d004,
2100 .clkr = {
2101 .enable_reg = 0x2d004,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "gcc_blsp2_uart4_apps_clk",
2105 .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2106 .num_parents = 1,
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2109 },
2110 },
2111};
2112
2113static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2114 .halt_reg = 0x2e004,
2115 .clkr = {
2116 .enable_reg = 0x2e004,
2117 .enable_mask = BIT(0),
2118 .hw.init = &(struct clk_init_data){
2119 .name = "gcc_blsp2_qup5_spi_apps_clk",
2120 .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2121 .num_parents = 1,
2122 .flags = CLK_SET_RATE_PARENT,
2123 .ops = &clk_branch2_ops,
2124 },
2125 },
2126};
2127
2128static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2129 .halt_reg = 0x2e008,
2130 .clkr = {
2131 .enable_reg = 0x2e008,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "gcc_blsp2_qup5_i2c_apps_clk",
2135 .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2136 .num_parents = 1,
2137 .flags = CLK_SET_RATE_PARENT,
2138 .ops = &clk_branch2_ops,
2139 },
2140 },
2141};
2142
2143static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2144 .halt_reg = 0x2f004,
2145 .clkr = {
2146 .enable_reg = 0x2f004,
2147 .enable_mask = BIT(0),
2148 .hw.init = &(struct clk_init_data){
2149 .name = "gcc_blsp2_uart5_apps_clk",
2150 .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2151 .num_parents = 1,
2152 .flags = CLK_SET_RATE_PARENT,
2153 .ops = &clk_branch2_ops,
2154 },
2155 },
2156};
2157
2158static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2159 .halt_reg = 0x30004,
2160 .clkr = {
2161 .enable_reg = 0x30004,
2162 .enable_mask = BIT(0),
2163 .hw.init = &(struct clk_init_data){
2164 .name = "gcc_blsp2_qup6_spi_apps_clk",
2165 .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2166 .num_parents = 1,
2167 .flags = CLK_SET_RATE_PARENT,
2168 .ops = &clk_branch2_ops,
2169 },
2170 },
2171};
2172
2173static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2174 .halt_reg = 0x30008,
2175 .clkr = {
2176 .enable_reg = 0x30008,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gcc_blsp2_qup6_i2c_apps_clk",
2180 .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2181 .num_parents = 1,
2182 .flags = CLK_SET_RATE_PARENT,
2183 .ops = &clk_branch2_ops,
2184 },
2185 },
2186};
2187
2188static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2189 .halt_reg = 0x31004,
2190 .clkr = {
2191 .enable_reg = 0x31004,
2192 .enable_mask = BIT(0),
2193 .hw.init = &(struct clk_init_data){
2194 .name = "gcc_blsp2_uart6_apps_clk",
2195 .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2196 .num_parents = 1,
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2199 },
2200 },
2201};
2202
2203static struct clk_branch gcc_pdm_ahb_clk = {
2204 .halt_reg = 0x33004,
2205 .clkr = {
2206 .enable_reg = 0x33004,
2207 .enable_mask = BIT(0),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "gcc_pdm_ahb_clk",
2210 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2211 .num_parents = 1,
2212 .flags = CLK_SET_RATE_PARENT,
2213 .ops = &clk_branch2_ops,
2214 },
2215 },
2216};
2217
2218static struct clk_branch gcc_pdm2_clk = {
2219 .halt_reg = 0x3300c,
2220 .clkr = {
2221 .enable_reg = 0x3300c,
2222 .enable_mask = BIT(0),
2223 .hw.init = &(struct clk_init_data){
2224 .name = "gcc_pdm2_clk",
2225 .parent_names = (const char *[]){ "pdm2_clk_src" },
2226 .num_parents = 1,
2227 .flags = CLK_SET_RATE_PARENT,
2228 .ops = &clk_branch2_ops,
2229 },
2230 },
2231};
2232
2233static struct clk_branch gcc_prng_ahb_clk = {
2234 .halt_reg = 0x34004,
2235 .halt_check = BRANCH_HALT_VOTED,
2236 .clkr = {
2237 .enable_reg = 0x52004,
2238 .enable_mask = BIT(13),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "gcc_prng_ahb_clk",
2241 .parent_names = (const char *[]){ "config_noc_clk_src" },
2242 .num_parents = 1,
2243 .flags = CLK_SET_RATE_PARENT,
2244 .ops = &clk_branch2_ops,
2245 },
2246 },
2247};
2248
2249static struct clk_branch gcc_tsif_ahb_clk = {
2250 .halt_reg = 0x36004,
2251 .clkr = {
2252 .enable_reg = 0x36004,
2253 .enable_mask = BIT(0),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "gcc_tsif_ahb_clk",
2256 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2257 .num_parents = 1,
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262};
2263
2264static struct clk_branch gcc_tsif_ref_clk = {
2265 .halt_reg = 0x36008,
2266 .clkr = {
2267 .enable_reg = 0x36008,
2268 .enable_mask = BIT(0),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "gcc_tsif_ref_clk",
2271 .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2272 .num_parents = 1,
2273 .flags = CLK_SET_RATE_PARENT,
2274 .ops = &clk_branch2_ops,
2275 },
2276 },
2277};
2278
2279static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2280 .halt_reg = 0x3600c,
2281 .clkr = {
2282 .enable_reg = 0x3600c,
2283 .enable_mask = BIT(0),
2284 .hw.init = &(struct clk_init_data){
2285 .name = "gcc_tsif_inactivity_timers_clk",
2286 .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2287 .num_parents = 1,
2288 .flags = CLK_SET_RATE_PARENT,
2289 .ops = &clk_branch2_ops,
2290 },
2291 },
2292};
2293
2294static struct clk_branch gcc_boot_rom_ahb_clk = {
2295 .halt_reg = 0x38004,
2296 .halt_check = BRANCH_HALT_VOTED,
2297 .clkr = {
2298 .enable_reg = 0x52004,
2299 .enable_mask = BIT(10),
2300 .hw.init = &(struct clk_init_data){
2301 .name = "gcc_boot_rom_ahb_clk",
2302 .parent_names = (const char *[]){ "config_noc_clk_src" },
2303 .num_parents = 1,
2304 .flags = CLK_SET_RATE_PARENT,
2305 .ops = &clk_branch2_ops,
2306 },
2307 },
2308};
2309
2310static struct clk_branch gcc_bimc_gfx_clk = {
2311 .halt_reg = 0x46018,
2312 .clkr = {
2313 .enable_reg = 0x46018,
2314 .enable_mask = BIT(0),
2315 .hw.init = &(struct clk_init_data){
2316 .name = "gcc_bimc_gfx_clk",
2317 .flags = CLK_SET_RATE_PARENT | CLK_IS_ROOT,
2318 .ops = &clk_branch2_ops,
2319 },
2320 },
2321};
2322
2323static struct clk_branch gcc_hmss_rbcpr_clk = {
2324 .halt_reg = 0x4800c,
2325 .clkr = {
2326 .enable_reg = 0x4800c,
2327 .enable_mask = BIT(0),
2328 .hw.init = &(struct clk_init_data){
2329 .name = "gcc_hmss_rbcpr_clk",
2330 .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2331 .num_parents = 1,
2332 .flags = CLK_SET_RATE_PARENT,
2333 .ops = &clk_branch2_ops,
2334 },
2335 },
2336};
2337
2338static struct clk_branch gcc_gp1_clk = {
2339 .halt_reg = 0x64000,
2340 .clkr = {
2341 .enable_reg = 0x64000,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gcc_gp1_clk",
2345 .parent_names = (const char *[]){ "gp1_clk_src" },
2346 .num_parents = 1,
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2349 },
2350 },
2351};
2352
2353static struct clk_branch gcc_gp2_clk = {
2354 .halt_reg = 0x65000,
2355 .clkr = {
2356 .enable_reg = 0x65000,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "gcc_gp2_clk",
2360 .parent_names = (const char *[]){ "gp2_clk_src" },
2361 .num_parents = 1,
2362 .flags = CLK_SET_RATE_PARENT,
2363 .ops = &clk_branch2_ops,
2364 },
2365 },
2366};
2367
2368static struct clk_branch gcc_gp3_clk = {
2369 .halt_reg = 0x66000,
2370 .clkr = {
2371 .enable_reg = 0x66000,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "gcc_gp3_clk",
2375 .parent_names = (const char *[]){ "gp3_clk_src" },
2376 .num_parents = 1,
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2379 },
2380 },
2381};
2382
2383static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2384 .halt_reg = 0x6b008,
2385 .clkr = {
2386 .enable_reg = 0x6b008,
2387 .enable_mask = BIT(0),
2388 .hw.init = &(struct clk_init_data){
2389 .name = "gcc_pcie_0_slv_axi_clk",
2390 .parent_names = (const char *[]){ "system_noc_clk_src" },
2391 .num_parents = 1,
2392 .flags = CLK_SET_RATE_PARENT,
2393 .ops = &clk_branch2_ops,
2394 },
2395 },
2396};
2397
2398static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2399 .halt_reg = 0x6b00c,
2400 .clkr = {
2401 .enable_reg = 0x6b00c,
2402 .enable_mask = BIT(0),
2403 .hw.init = &(struct clk_init_data){
2404 .name = "gcc_pcie_0_mstr_axi_clk",
2405 .parent_names = (const char *[]){ "system_noc_clk_src" },
2406 .num_parents = 1,
2407 .flags = CLK_SET_RATE_PARENT,
2408 .ops = &clk_branch2_ops,
2409 },
2410 },
2411};
2412
2413static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2414 .halt_reg = 0x6b010,
2415 .clkr = {
2416 .enable_reg = 0x6b010,
2417 .enable_mask = BIT(0),
2418 .hw.init = &(struct clk_init_data){
2419 .name = "gcc_pcie_0_cfg_ahb_clk",
2420 .parent_names = (const char *[]){ "config_noc_clk_src" },
2421 .num_parents = 1,
2422 .flags = CLK_SET_RATE_PARENT,
2423 .ops = &clk_branch2_ops,
2424 },
2425 },
2426};
2427
2428static struct clk_branch gcc_pcie_0_aux_clk = {
2429 .halt_reg = 0x6b014,
2430 .clkr = {
2431 .enable_reg = 0x6b014,
2432 .enable_mask = BIT(0),
2433 .hw.init = &(struct clk_init_data){
2434 .name = "gcc_pcie_0_aux_clk",
2435 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2436 .num_parents = 1,
2437 .flags = CLK_SET_RATE_PARENT,
2438 .ops = &clk_branch2_ops,
2439 },
2440 },
2441};
2442
2443static struct clk_branch gcc_pcie_0_pipe_clk = {
2444 .halt_reg = 0x6b018,
2445 .clkr = {
2446 .enable_reg = 0x6b018,
2447 .enable_mask = BIT(0),
2448 .hw.init = &(struct clk_init_data){
2449 .name = "gcc_pcie_0_pipe_clk",
2450 .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2451 .num_parents = 1,
2452 .flags = CLK_SET_RATE_PARENT,
2453 .ops = &clk_branch2_ops,
2454 },
2455 },
2456};
2457
2458static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2459 .halt_reg = 0x6d008,
2460 .clkr = {
2461 .enable_reg = 0x6d008,
2462 .enable_mask = BIT(0),
2463 .hw.init = &(struct clk_init_data){
2464 .name = "gcc_pcie_1_slv_axi_clk",
2465 .parent_names = (const char *[]){ "system_noc_clk_src" },
2466 .num_parents = 1,
2467 .flags = CLK_SET_RATE_PARENT,
2468 .ops = &clk_branch2_ops,
2469 },
2470 },
2471};
2472
2473static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2474 .halt_reg = 0x6d00c,
2475 .clkr = {
2476 .enable_reg = 0x6d00c,
2477 .enable_mask = BIT(0),
2478 .hw.init = &(struct clk_init_data){
2479 .name = "gcc_pcie_1_mstr_axi_clk",
2480 .parent_names = (const char *[]){ "system_noc_clk_src" },
2481 .num_parents = 1,
2482 .flags = CLK_SET_RATE_PARENT,
2483 .ops = &clk_branch2_ops,
2484 },
2485 },
2486};
2487
2488static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2489 .halt_reg = 0x6d010,
2490 .clkr = {
2491 .enable_reg = 0x6d010,
2492 .enable_mask = BIT(0),
2493 .hw.init = &(struct clk_init_data){
2494 .name = "gcc_pcie_1_cfg_ahb_clk",
2495 .parent_names = (const char *[]){ "config_noc_clk_src" },
2496 .num_parents = 1,
2497 .flags = CLK_SET_RATE_PARENT,
2498 .ops = &clk_branch2_ops,
2499 },
2500 },
2501};
2502
2503static struct clk_branch gcc_pcie_1_aux_clk = {
2504 .halt_reg = 0x6d014,
2505 .clkr = {
2506 .enable_reg = 0x6d014,
2507 .enable_mask = BIT(0),
2508 .hw.init = &(struct clk_init_data){
2509 .name = "gcc_pcie_1_aux_clk",
2510 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2511 .num_parents = 1,
2512 .flags = CLK_SET_RATE_PARENT,
2513 .ops = &clk_branch2_ops,
2514 },
2515 },
2516};
2517
2518static struct clk_branch gcc_pcie_1_pipe_clk = {
2519 .halt_reg = 0x6d018,
2520 .clkr = {
2521 .enable_reg = 0x6d018,
2522 .enable_mask = BIT(0),
2523 .hw.init = &(struct clk_init_data){
2524 .name = "gcc_pcie_1_pipe_clk",
2525 .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2526 .num_parents = 1,
2527 .flags = CLK_SET_RATE_PARENT,
2528 .ops = &clk_branch2_ops,
2529 },
2530 },
2531};
2532
2533static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2534 .halt_reg = 0x6e008,
2535 .clkr = {
2536 .enable_reg = 0x6e008,
2537 .enable_mask = BIT(0),
2538 .hw.init = &(struct clk_init_data){
2539 .name = "gcc_pcie_2_slv_axi_clk",
2540 .parent_names = (const char *[]){ "system_noc_clk_src" },
2541 .num_parents = 1,
2542 .flags = CLK_SET_RATE_PARENT,
2543 .ops = &clk_branch2_ops,
2544 },
2545 },
2546};
2547
2548static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2549 .halt_reg = 0x6e00c,
2550 .clkr = {
2551 .enable_reg = 0x6e00c,
2552 .enable_mask = BIT(0),
2553 .hw.init = &(struct clk_init_data){
2554 .name = "gcc_pcie_2_mstr_axi_clk",
2555 .parent_names = (const char *[]){ "system_noc_clk_src" },
2556 .num_parents = 1,
2557 .flags = CLK_SET_RATE_PARENT,
2558 .ops = &clk_branch2_ops,
2559 },
2560 },
2561};
2562
2563static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2564 .halt_reg = 0x6e010,
2565 .clkr = {
2566 .enable_reg = 0x6e010,
2567 .enable_mask = BIT(0),
2568 .hw.init = &(struct clk_init_data){
2569 .name = "gcc_pcie_2_cfg_ahb_clk",
2570 .parent_names = (const char *[]){ "config_noc_clk_src" },
2571 .num_parents = 1,
2572 .flags = CLK_SET_RATE_PARENT,
2573 .ops = &clk_branch2_ops,
2574 },
2575 },
2576};
2577
2578static struct clk_branch gcc_pcie_2_aux_clk = {
2579 .halt_reg = 0x6e014,
2580 .clkr = {
2581 .enable_reg = 0x6e014,
2582 .enable_mask = BIT(0),
2583 .hw.init = &(struct clk_init_data){
2584 .name = "gcc_pcie_2_aux_clk",
2585 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2586 .num_parents = 1,
2587 .flags = CLK_SET_RATE_PARENT,
2588 .ops = &clk_branch2_ops,
2589 },
2590 },
2591};
2592
2593static struct clk_branch gcc_pcie_2_pipe_clk = {
2594 .halt_reg = 0x6e108,
2595 .clkr = {
2596 .enable_reg = 0x6e108,
2597 .enable_mask = BIT(0),
2598 .hw.init = &(struct clk_init_data){
2599 .name = "gcc_pcie_2_pipe_clk",
2600 .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2601 .num_parents = 1,
2602 .flags = CLK_SET_RATE_PARENT,
2603 .ops = &clk_branch2_ops,
2604 },
2605 },
2606};
2607
2608static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2609 .halt_reg = 0x6f004,
2610 .clkr = {
2611 .enable_reg = 0x6f004,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "gcc_pcie_phy_cfg_ahb_clk",
2615 .parent_names = (const char *[]){ "config_noc_clk_src" },
2616 .num_parents = 1,
2617 .flags = CLK_SET_RATE_PARENT,
2618 .ops = &clk_branch2_ops,
2619 },
2620 },
2621};
2622
2623static struct clk_branch gcc_pcie_phy_aux_clk = {
2624 .halt_reg = 0x6f008,
2625 .clkr = {
2626 .enable_reg = 0x6f008,
2627 .enable_mask = BIT(0),
2628 .hw.init = &(struct clk_init_data){
2629 .name = "gcc_pcie_phy_aux_clk",
2630 .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2631 .num_parents = 1,
2632 .flags = CLK_SET_RATE_PARENT,
2633 .ops = &clk_branch2_ops,
2634 },
2635 },
2636};
2637
2638static struct clk_branch gcc_ufs_axi_clk = {
2639 .halt_reg = 0x75008,
2640 .clkr = {
2641 .enable_reg = 0x75008,
2642 .enable_mask = BIT(0),
2643 .hw.init = &(struct clk_init_data){
2644 .name = "gcc_ufs_axi_clk",
2645 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2646 .num_parents = 1,
2647 .flags = CLK_SET_RATE_PARENT,
2648 .ops = &clk_branch2_ops,
2649 },
2650 },
2651};
2652
2653static struct clk_branch gcc_ufs_ahb_clk = {
2654 .halt_reg = 0x7500c,
2655 .clkr = {
2656 .enable_reg = 0x7500c,
2657 .enable_mask = BIT(0),
2658 .hw.init = &(struct clk_init_data){
2659 .name = "gcc_ufs_ahb_clk",
2660 .parent_names = (const char *[]){ "config_noc_clk_src" },
2661 .num_parents = 1,
2662 .flags = CLK_SET_RATE_PARENT,
2663 .ops = &clk_branch2_ops,
2664 },
2665 },
2666};
2667
2668static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2669 .mult = 1,
2670 .div = 16,
2671 .hw.init = &(struct clk_init_data){
2672 .name = "ufs_tx_cfg_clk_src",
2673 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2674 .num_parents = 1,
2675 .flags = CLK_SET_RATE_PARENT,
2676 .ops = &clk_fixed_factor_ops,
2677 },
2678};
2679
2680static struct clk_branch gcc_ufs_tx_cfg_clk = {
2681 .halt_reg = 0x75010,
2682 .clkr = {
2683 .enable_reg = 0x75010,
2684 .enable_mask = BIT(0),
2685 .hw.init = &(struct clk_init_data){
2686 .name = "gcc_ufs_tx_cfg_clk",
2687 .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2688 .num_parents = 1,
2689 .flags = CLK_SET_RATE_PARENT,
2690 .ops = &clk_branch2_ops,
2691 },
2692 },
2693};
2694
2695static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2696 .mult = 1,
2697 .div = 16,
2698 .hw.init = &(struct clk_init_data){
2699 .name = "ufs_rx_cfg_clk_src",
2700 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2701 .num_parents = 1,
2702 .flags = CLK_SET_RATE_PARENT,
2703 .ops = &clk_fixed_factor_ops,
2704 },
2705};
2706
2707static struct clk_branch gcc_ufs_rx_cfg_clk = {
2708 .halt_reg = 0x75014,
2709 .clkr = {
2710 .enable_reg = 0x75014,
2711 .enable_mask = BIT(0),
2712 .hw.init = &(struct clk_init_data){
2713 .name = "gcc_ufs_rx_cfg_clk",
2714 .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2715 .num_parents = 1,
2716 .flags = CLK_SET_RATE_PARENT,
2717 .ops = &clk_branch2_ops,
2718 },
2719 },
2720};
2721
2722static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2723 .halt_reg = 0x75018,
2724 .clkr = {
2725 .enable_reg = 0x75018,
2726 .enable_mask = BIT(0),
2727 .hw.init = &(struct clk_init_data){
2728 .name = "gcc_ufs_tx_symbol_0_clk",
2729 .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2730 .num_parents = 1,
2731 .flags = CLK_SET_RATE_PARENT,
2732 .ops = &clk_branch2_ops,
2733 },
2734 },
2735};
2736
2737static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2738 .halt_reg = 0x7501c,
2739 .clkr = {
2740 .enable_reg = 0x7501c,
2741 .enable_mask = BIT(0),
2742 .hw.init = &(struct clk_init_data){
2743 .name = "gcc_ufs_rx_symbol_0_clk",
2744 .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2745 .num_parents = 1,
2746 .flags = CLK_SET_RATE_PARENT,
2747 .ops = &clk_branch2_ops,
2748 },
2749 },
2750};
2751
2752static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2753 .halt_reg = 0x75020,
2754 .clkr = {
2755 .enable_reg = 0x75020,
2756 .enable_mask = BIT(0),
2757 .hw.init = &(struct clk_init_data){
2758 .name = "gcc_ufs_rx_symbol_1_clk",
2759 .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2760 .num_parents = 1,
2761 .flags = CLK_SET_RATE_PARENT,
2762 .ops = &clk_branch2_ops,
2763 },
2764 },
2765};
2766
2767static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2768 .mult = 1,
2769 .div = 2,
2770 .hw.init = &(struct clk_init_data){
2771 .name = "ufs_ice_core_postdiv_clk_src",
2772 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2773 .num_parents = 1,
2774 .flags = CLK_SET_RATE_PARENT,
2775 .ops = &clk_fixed_factor_ops,
2776 },
2777};
2778
2779static struct clk_branch gcc_ufs_unipro_core_clk = {
2780 .halt_reg = 0x7600c,
2781 .clkr = {
2782 .enable_reg = 0x7600c,
2783 .enable_mask = BIT(0),
2784 .hw.init = &(struct clk_init_data){
2785 .name = "gcc_ufs_unipro_core_clk",
2786 .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2787 .num_parents = 1,
2788 .flags = CLK_SET_RATE_PARENT,
2789 .ops = &clk_branch2_ops,
2790 },
2791 },
2792};
2793
2794static struct clk_branch gcc_ufs_ice_core_clk = {
2795 .halt_reg = 0x76010,
2796 .clkr = {
2797 .enable_reg = 0x76010,
2798 .enable_mask = BIT(0),
2799 .hw.init = &(struct clk_init_data){
2800 .name = "gcc_ufs_ice_core_clk",
2801 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2802 .num_parents = 1,
2803 .flags = CLK_SET_RATE_PARENT,
2804 .ops = &clk_branch2_ops,
2805 },
2806 },
2807};
2808
2809static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2810 .halt_check = BRANCH_HALT_DELAY,
2811 .clkr = {
2812 .enable_reg = 0x76030,
2813 .enable_mask = BIT(0),
2814 .hw.init = &(struct clk_init_data){
2815 .name = "gcc_ufs_sys_clk_core_clk",
2816 .ops = &clk_branch2_ops,
2817 .flags = CLK_IS_ROOT,
2818 },
2819 },
2820};
2821
2822static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2823 .halt_check = BRANCH_HALT_DELAY,
2824 .clkr = {
2825 .enable_reg = 0x76034,
2826 .enable_mask = BIT(0),
2827 .hw.init = &(struct clk_init_data){
2828 .name = "gcc_ufs_tx_symbol_clk_core_clk",
2829 .ops = &clk_branch2_ops,
2830 .flags = CLK_IS_ROOT,
2831 },
2832 },
2833};
2834
2835static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2836 .halt_reg = 0x81008,
2837 .clkr = {
2838 .enable_reg = 0x81008,
2839 .enable_mask = BIT(0),
2840 .hw.init = &(struct clk_init_data){
2841 .name = "gcc_aggre0_snoc_axi_clk",
2842 .parent_names = (const char *[]){ "system_noc_clk_src" },
2843 .num_parents = 1,
2844 .flags = CLK_SET_RATE_PARENT,
2845 .ops = &clk_branch2_ops,
2846 },
2847 },
2848};
2849
2850static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2851 .halt_reg = 0x8100c,
2852 .clkr = {
2853 .enable_reg = 0x8100c,
2854 .enable_mask = BIT(0),
2855 .hw.init = &(struct clk_init_data){
2856 .name = "gcc_aggre0_cnoc_ahb_clk",
2857 .parent_names = (const char *[]){ "config_noc_clk_src" },
2858 .num_parents = 1,
2859 .flags = CLK_SET_RATE_PARENT,
2860 .ops = &clk_branch2_ops,
2861 },
2862 },
2863};
2864
2865static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2866 .halt_reg = 0x81014,
2867 .clkr = {
2868 .enable_reg = 0x81014,
2869 .enable_mask = BIT(0),
2870 .hw.init = &(struct clk_init_data){
2871 .name = "gcc_smmu_aggre0_axi_clk",
2872 .parent_names = (const char *[]){ "system_noc_clk_src" },
2873 .num_parents = 1,
2874 .flags = CLK_SET_RATE_PARENT,
2875 .ops = &clk_branch2_ops,
2876 },
2877 },
2878};
2879
2880static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2881 .halt_reg = 0x81018,
2882 .clkr = {
2883 .enable_reg = 0x81018,
2884 .enable_mask = BIT(0),
2885 .hw.init = &(struct clk_init_data){
2886 .name = "gcc_smmu_aggre0_ahb_clk",
2887 .parent_names = (const char *[]){ "config_noc_clk_src" },
2888 .num_parents = 1,
2889 .flags = CLK_SET_RATE_PARENT,
2890 .ops = &clk_branch2_ops,
2891 },
2892 },
2893};
2894
2895static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
2896 .halt_reg = 0x82014,
2897 .clkr = {
2898 .enable_reg = 0x82014,
2899 .enable_mask = BIT(0),
2900 .hw.init = &(struct clk_init_data){
2901 .name = "gcc_aggre1_pnoc_ahb_clk",
2902 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2903 .num_parents = 1,
2904 .flags = CLK_SET_RATE_PARENT,
2905 .ops = &clk_branch2_ops,
2906 },
2907 },
2908};
2909
2910static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2911 .halt_reg = 0x83014,
2912 .clkr = {
2913 .enable_reg = 0x83014,
2914 .enable_mask = BIT(0),
2915 .hw.init = &(struct clk_init_data){
2916 .name = "gcc_aggre2_ufs_axi_clk",
2917 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2918 .num_parents = 1,
2919 .flags = CLK_SET_RATE_PARENT,
2920 .ops = &clk_branch2_ops,
2921 },
2922 },
2923};
2924
2925static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2926 .halt_reg = 0x83018,
2927 .clkr = {
2928 .enable_reg = 0x83018,
2929 .enable_mask = BIT(0),
2930 .hw.init = &(struct clk_init_data){
2931 .name = "gcc_aggre2_usb3_axi_clk",
2932 .parent_names = (const char *[]){ "usb30_master_clk_src" },
2933 .num_parents = 1,
2934 .flags = CLK_SET_RATE_PARENT,
2935 .ops = &clk_branch2_ops,
2936 },
2937 },
2938};
2939
2940static struct clk_branch gcc_qspi_ahb_clk = {
2941 .halt_reg = 0x8b004,
2942 .clkr = {
2943 .enable_reg = 0x8b004,
2944 .enable_mask = BIT(0),
2945 .hw.init = &(struct clk_init_data){
2946 .name = "gcc_qspi_ahb_clk",
2947 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2948 .num_parents = 1,
2949 .flags = CLK_SET_RATE_PARENT,
2950 .ops = &clk_branch2_ops,
2951 },
2952 },
2953};
2954
2955static struct clk_branch gcc_qspi_ser_clk = {
2956 .halt_reg = 0x8b008,
2957 .clkr = {
2958 .enable_reg = 0x8b008,
2959 .enable_mask = BIT(0),
2960 .hw.init = &(struct clk_init_data){
2961 .name = "gcc_qspi_ser_clk",
2962 .parent_names = (const char *[]){ "qspi_ser_clk_src" },
2963 .num_parents = 1,
2964 .flags = CLK_SET_RATE_PARENT,
2965 .ops = &clk_branch2_ops,
2966 },
2967 },
2968};
2969
2970static struct clk_branch gcc_usb3_clkref_clk = {
2971 .halt_reg = 0x8800C,
2972 .clkr = {
2973 .enable_reg = 0x8800C,
2974 .enable_mask = BIT(0),
2975 .hw.init = &(struct clk_init_data){
2976 .name = "gcc_usb3_clkref_clk",
2977 .parent_names = (const char *[]){ "xo" },
2978 .num_parents = 1,
2979 .ops = &clk_branch2_ops,
2980 },
2981 },
2982};
2983
2984static struct clk_branch gcc_hdmi_clkref_clk = {
2985 .halt_reg = 0x88000,
2986 .clkr = {
2987 .enable_reg = 0x88000,
2988 .enable_mask = BIT(0),
2989 .hw.init = &(struct clk_init_data){
2990 .name = "gcc_hdmi_clkref_clk",
2991 .parent_names = (const char *[]){ "xo" },
2992 .num_parents = 1,
2993 .ops = &clk_branch2_ops,
2994 },
2995 },
2996};
2997
2998static struct clk_branch gcc_ufs_clkref_clk = {
2999 .halt_reg = 0x88008,
3000 .clkr = {
3001 .enable_reg = 0x88008,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "gcc_ufs_clkref_clk",
3005 .parent_names = (const char *[]){ "xo" },
3006 .num_parents = 1,
3007 .ops = &clk_branch2_ops,
3008 },
3009 },
3010};
3011
3012static struct clk_branch gcc_pcie_clkref_clk = {
3013 .halt_reg = 0x88010,
3014 .clkr = {
3015 .enable_reg = 0x88010,
3016 .enable_mask = BIT(0),
3017 .hw.init = &(struct clk_init_data){
3018 .name = "gcc_pcie_clkref_clk",
3019 .parent_names = (const char *[]){ "xo" },
3020 .num_parents = 1,
3021 .ops = &clk_branch2_ops,
3022 },
3023 },
3024};
3025
3026static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3027 .halt_reg = 0x88014,
3028 .clkr = {
3029 .enable_reg = 0x88014,
3030 .enable_mask = BIT(0),
3031 .hw.init = &(struct clk_init_data){
3032 .name = "gcc_rx2_usb2_clkref_clk",
3033 .parent_names = (const char *[]){ "xo" },
3034 .num_parents = 1,
3035 .ops = &clk_branch2_ops,
3036 },
3037 },
3038};
3039
3040static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3041 .halt_reg = 0x88018,
3042 .clkr = {
3043 .enable_reg = 0x88018,
3044 .enable_mask = BIT(0),
3045 .hw.init = &(struct clk_init_data){
3046 .name = "gcc_rx1_usb2_clkref_clk",
3047 .parent_names = (const char *[]){ "xo" },
3048 .num_parents = 1,
3049 .ops = &clk_branch2_ops,
3050 },
3051 },
3052};
3053
3054static struct clk_hw *gcc_msm8996_hws[] = {
3055 &xo.hw,
3056 &gpll0_early_div.hw,
3057 &ufs_tx_cfg_clk_src.hw,
3058 &ufs_rx_cfg_clk_src.hw,
3059 &ufs_ice_core_postdiv_clk_src.hw,
3060};
3061
3062static struct clk_regmap *gcc_msm8996_clocks[] = {
3063 [GPLL0_EARLY] = &gpll0_early.clkr,
3064 [GPLL0] = &gpll0.clkr,
3065 [GPLL4_EARLY] = &gpll4_early.clkr,
3066 [GPLL4] = &gpll4.clkr,
3067 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3068 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3069 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3070 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3071 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3072 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3073 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3074 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3075 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3076 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3077 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3078 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3079 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3080 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3081 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3082 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3083 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3084 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3085 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3086 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3087 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3088 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3089 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3090 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3091 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3092 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3093 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3094 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3095 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3096 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3097 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3098 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3099 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3100 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3101 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3102 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3103 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3104 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3105 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3106 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3107 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3108 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3109 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3110 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3111 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3112 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3113 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3114 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3115 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3116 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3117 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3118 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3119 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3120 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3121 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3122 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3123 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3124 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3125 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3126 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3127 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3128 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3129 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3130 [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3131 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3132 [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3133 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3134 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3135 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3136 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3137 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3138 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3139 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3140 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3141 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3142 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3143 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3144 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3145 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3146 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3147 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3148 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3149 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3150 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3151 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3152 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3153 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3154 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3155 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3156 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3157 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3158 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3159 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3160 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3161 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3162 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3163 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3164 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3165 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3166 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3167 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3168 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3169 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3170 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3171 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3172 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3173 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3174 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3175 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3176 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3177 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3178 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3179 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3180 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3181 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3182 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3183 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3184 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3185 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3186 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3187 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3188 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3189 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3190 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3191 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3192 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3193 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3194 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3195 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3196 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3197 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3198 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3199 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3200 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3201 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3202 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3203 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3204 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3205 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3206 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3207 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3208 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3209 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3210 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3211 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3212 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3213 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3214 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3215 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3216 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3217 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3218 [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3219 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3220 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3221 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3222 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3223 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3224 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3225 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3226 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3227 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3228 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3229 [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3230 [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3231 [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3232 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3233 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3234 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3235 [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
3236 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3237 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3238 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3239 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3240 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3241 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3242 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3243 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3244 [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3245 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3246};
3247
3248static const struct qcom_reset_map gcc_msm8996_resets[] = {
3249 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3250 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3251 [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3252 [GCC_IMEM_BCR] = { 0x8000 },
3253 [GCC_MMSS_BCR] = { 0x9000 },
3254 [GCC_PIMEM_BCR] = { 0x0a000 },
3255 [GCC_QDSS_BCR] = { 0x0c000 },
3256 [GCC_USB_30_BCR] = { 0x0f000 },
3257 [GCC_USB_20_BCR] = { 0x12000 },
3258 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3259 [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3260 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3261 [GCC_SDCC1_BCR] = { 0x13000 },
3262 [GCC_SDCC2_BCR] = { 0x14000 },
3263 [GCC_SDCC3_BCR] = { 0x15000 },
3264 [GCC_SDCC4_BCR] = { 0x16000 },
3265 [GCC_BLSP1_BCR] = { 0x17000 },
3266 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3267 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3268 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3269 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3270 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3271 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3272 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3273 [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3274 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3275 [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3276 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3277 [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3278 [GCC_BLSP2_BCR] = { 0x25000 },
3279 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3280 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3281 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3282 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3283 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3284 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3285 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3286 [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3287 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3288 [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3289 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3290 [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3291 [GCC_PDM_BCR] = { 0x33000 },
3292 [GCC_PRNG_BCR] = { 0x34000 },
3293 [GCC_TSIF_BCR] = { 0x36000 },
3294 [GCC_TCSR_BCR] = { 0x37000 },
3295 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3296 [GCC_MSG_RAM_BCR] = { 0x39000 },
3297 [GCC_TLMM_BCR] = { 0x3a000 },
3298 [GCC_MPM_BCR] = { 0x3b000 },
3299 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3300 [GCC_SPMI_BCR] = { 0x3f000 },
3301 [GCC_SPDM_BCR] = { 0x40000 },
3302 [GCC_CE1_BCR] = { 0x41000 },
3303 [GCC_BIMC_BCR] = { 0x44000 },
3304 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3305 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3306 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3307 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3308 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3309 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3310 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3311 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3312 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3313 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3314 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3315 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3316 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3317 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3318 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3319 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3320 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3321 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3322 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3323 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3324 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3325 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3326 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3327 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3328 [GCC_PCIE_0_BCR] = { 0x6b000 },
3329 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3330 [GCC_PCIE_1_BCR] = { 0x6d000 },
3331 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3332 [GCC_PCIE_2_BCR] = { 0x6e000 },
3333 [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3334 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3335 [GCC_DCD_BCR] = { 0x70000 },
3336 [GCC_OBT_ODT_BCR] = { 0x73000 },
3337 [GCC_UFS_BCR] = { 0x75000 },
3338 [GCC_SSC_BCR] = { 0x63000 },
3339 [GCC_VS_BCR] = { 0x7a000 },
3340 [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3341 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3342 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3343 [GCC_DCC_BCR] = { 0x84000 },
3344 [GCC_IPA_BCR] = { 0x89000 },
3345 [GCC_QSPI_BCR] = { 0x8b000 },
3346 [GCC_SKL_BCR] = { 0x8c000 },
3347 [GCC_MSMPU_BCR] = { 0x8d000 },
3348 [GCC_MSS_Q6_BCR] = { 0x8e000 },
3349 [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3350};
3351
3352static const struct regmap_config gcc_msm8996_regmap_config = {
3353 .reg_bits = 32,
3354 .reg_stride = 4,
3355 .val_bits = 32,
3356 .max_register = 0x8f010,
3357 .fast_io = true,
3358};
3359
3360static const struct qcom_cc_desc gcc_msm8996_desc = {
3361 .config = &gcc_msm8996_regmap_config,
3362 .clks = gcc_msm8996_clocks,
3363 .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3364 .resets = gcc_msm8996_resets,
3365 .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3366};
3367
3368static const struct of_device_id gcc_msm8996_match_table[] = {
3369 { .compatible = "qcom,gcc-msm8996" },
3370 { }
3371};
3372MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3373
3374static int gcc_msm8996_probe(struct platform_device *pdev)
3375{
3376 struct clk *clk;
3377 struct device *dev = &pdev->dev;
3378 int i;
3379 struct regmap *regmap;
3380
3381 regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3382 if (IS_ERR(regmap))
3383 return PTR_ERR(regmap);
3384
3385 /*
3386 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3387 * turned off by hardware during certain apps low power modes.
3388 */
3389 regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3390
3391 for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3392 clk = devm_clk_register(dev, gcc_msm8996_hws[i]);
3393 if (IS_ERR(clk))
3394 return PTR_ERR(clk);
3395 }
3396
3397 return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3398}
3399
3400static struct platform_driver gcc_msm8996_driver = {
3401 .probe = gcc_msm8996_probe,
3402 .driver = {
3403 .name = "gcc-msm8996",
3404 .of_match_table = gcc_msm8996_match_table,
3405 },
3406};
3407
3408static int __init gcc_msm8996_init(void)
3409{
3410 return platform_driver_register(&gcc_msm8996_driver);
3411}
3412core_initcall(gcc_msm8996_init);
3413
3414static void __exit gcc_msm8996_exit(void)
3415{
3416 platform_driver_unregister(&gcc_msm8996_driver);
3417}
3418module_exit(gcc_msm8996_exit);
3419
3420MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3421MODULE_LICENSE("GPL v2");
3422MODULE_ALIAS("platform:gcc-msm8996");
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index db3998e5e2d8..62e79fadd5f7 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -419,6 +419,7 @@ static const struct regmap_config lcc_ipq806x_regmap_config = {
419 .val_bits = 32, 419 .val_bits = 32,
420 .max_register = 0xfc, 420 .max_register = 0xfc,
421 .fast_io = true, 421 .fast_io = true,
422 .val_format_endian = REGMAP_ENDIAN_LITTLE,
422}; 423};
423 424
424static const struct qcom_cc_desc lcc_ipq806x_desc = { 425static const struct qcom_cc_desc lcc_ipq806x_desc = {
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index 4fcf9d1d233c..bf95bb0ea1b8 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -524,6 +524,7 @@ static const struct regmap_config lcc_msm8960_regmap_config = {
524 .val_bits = 32, 524 .val_bits = 32,
525 .max_register = 0xfc, 525 .max_register = 0xfc,
526 .fast_io = true, 526 .fast_io = true,
527 .val_format_endian = REGMAP_ENDIAN_LITTLE,
527}; 528};
528 529
529static const struct qcom_cc_desc lcc_msm8960_desc = { 530static const struct qcom_cc_desc lcc_msm8960_desc = {
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 30777f9f1a43..1e703fda8a0f 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -3368,6 +3368,7 @@ static const struct regmap_config mmcc_apq8084_regmap_config = {
3368 .val_bits = 32, 3368 .val_bits = 32,
3369 .max_register = 0x5104, 3369 .max_register = 0x5104,
3370 .fast_io = true, 3370 .fast_io = true,
3371 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3371}; 3372};
3372 3373
3373static const struct qcom_cc_desc mmcc_apq8084_desc = { 3374static const struct qcom_cc_desc mmcc_apq8084_desc = {
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 00e36192a1de..d73a048d3b9d 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -3029,6 +3029,7 @@ static const struct regmap_config mmcc_msm8960_regmap_config = {
3029 .val_bits = 32, 3029 .val_bits = 32,
3030 .max_register = 0x334, 3030 .max_register = 0x334,
3031 .fast_io = true, 3031 .fast_io = true,
3032 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3032}; 3033};
3033 3034
3034static const struct regmap_config mmcc_apq8064_regmap_config = { 3035static const struct regmap_config mmcc_apq8064_regmap_config = {
@@ -3037,6 +3038,7 @@ static const struct regmap_config mmcc_apq8064_regmap_config = {
3037 .val_bits = 32, 3038 .val_bits = 32,
3038 .max_register = 0x350, 3039 .max_register = 0x350,
3039 .fast_io = true, 3040 .fast_io = true,
3041 .val_format_endian = REGMAP_ENDIAN_LITTLE,
3040}; 3042};
3041 3043
3042static const struct qcom_cc_desc mmcc_msm8960_desc = { 3044static const struct qcom_cc_desc mmcc_msm8960_desc = {
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 9d790bcadf25..bbe28ed93669 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2594,6 +2594,7 @@ static const struct regmap_config mmcc_msm8974_regmap_config = {
2594 .val_bits = 32, 2594 .val_bits = 32,
2595 .max_register = 0x5104, 2595 .max_register = 0x5104,
2596 .fast_io = true, 2596 .fast_io = true,
2597 .val_format_endian = REGMAP_ENDIAN_LITTLE,
2597}; 2598};
2598 2599
2599static const struct qcom_cc_desc mmcc_msm8974_desc = { 2600static const struct qcom_cc_desc mmcc_msm8974_desc = {
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
new file mode 100644
index 000000000000..064f3eaa39d0
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -0,0 +1,3217 @@
1/*x
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24#include <linux/clk.h>
25
26#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
27
28#include "common.h"
29#include "clk-regmap.h"
30#include "clk-regmap-divider.h"
31#include "clk-alpha-pll.h"
32#include "clk-rcg.h"
33#include "clk-branch.h"
34#include "reset.h"
35
36#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
37
38enum {
39 P_XO,
40 P_MMPLL0,
41 P_GPLL0,
42 P_GPLL0_DIV,
43 P_MMPLL1,
44 P_MMPLL9,
45 P_MMPLL2,
46 P_MMPLL8,
47 P_MMPLL3,
48 P_DSI0PLL,
49 P_DSI1PLL,
50 P_MMPLL5,
51 P_HDMIPLL,
52 P_DSI0PLL_BYTE,
53 P_DSI1PLL_BYTE,
54 P_MMPLL4,
55};
56
57static const struct parent_map mmss_xo_hdmi_map[] = {
58 { P_XO, 0 },
59 { P_HDMIPLL, 1 }
60};
61
62static const char * const mmss_xo_hdmi[] = {
63 "xo",
64 "hdmipll"
65};
66
67static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
68 { P_XO, 0 },
69 { P_DSI0PLL, 1 },
70 { P_DSI1PLL, 2 }
71};
72
73static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
74 "xo",
75 "dsi0pll",
76 "dsi1pll"
77};
78
79static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
80 { P_XO, 0 },
81 { P_GPLL0, 5 },
82 { P_GPLL0_DIV, 6 }
83};
84
85static const char * const mmss_xo_gpll0_gpll0_div[] = {
86 "xo",
87 "gpll0",
88 "gpll0_div"
89};
90
91static const struct parent_map mmss_xo_dsibyte_map[] = {
92 { P_XO, 0 },
93 { P_DSI0PLL_BYTE, 1 },
94 { P_DSI1PLL_BYTE, 2 }
95};
96
97static const char * const mmss_xo_dsibyte[] = {
98 "xo",
99 "dsi0pllbyte",
100 "dsi1pllbyte"
101};
102
103static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
104 { P_XO, 0 },
105 { P_MMPLL0, 1 },
106 { P_GPLL0, 5 },
107 { P_GPLL0_DIV, 6 }
108};
109
110static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = {
111 "xo",
112 "mmpll0",
113 "gpll0",
114 "gpll0_div"
115};
116
117static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
118 { P_XO, 0 },
119 { P_MMPLL0, 1 },
120 { P_MMPLL1, 2 },
121 { P_GPLL0, 5 },
122 { P_GPLL0_DIV, 6 }
123};
124
125static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
126 "xo",
127 "mmpll0",
128 "mmpll1",
129 "gpll0",
130 "gpll0_div"
131};
132
133static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
134 { P_XO, 0 },
135 { P_MMPLL0, 1 },
136 { P_MMPLL3, 3 },
137 { P_GPLL0, 5 },
138 { P_GPLL0_DIV, 6 }
139};
140
141static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
142 "xo",
143 "mmpll0",
144 "mmpll3",
145 "gpll0",
146 "gpll0_div"
147};
148
149static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
150 { P_XO, 0 },
151 { P_MMPLL0, 1 },
152 { P_MMPLL5, 2 },
153 { P_GPLL0, 5 },
154 { P_GPLL0_DIV, 6 }
155};
156
157static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
158 "xo",
159 "mmpll0",
160 "mmpll5",
161 "gpll0",
162 "gpll0_div"
163};
164
165static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
166 { P_XO, 0 },
167 { P_MMPLL0, 1 },
168 { P_MMPLL4, 3 },
169 { P_GPLL0, 5 },
170 { P_GPLL0_DIV, 6 }
171};
172
173static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
174 "xo",
175 "mmpll0",
176 "mmpll4",
177 "gpll0",
178 "gpll0_div"
179};
180
181static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
182 { P_XO, 0 },
183 { P_MMPLL0, 1 },
184 { P_MMPLL9, 2 },
185 { P_MMPLL2, 3 },
186 { P_MMPLL8, 4 },
187 { P_GPLL0, 5 }
188};
189
190static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
191 "xo",
192 "mmpll0",
193 "mmpll9",
194 "mmpll2",
195 "mmpll8",
196 "gpll0"
197};
198
199static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
200 { P_XO, 0 },
201 { P_MMPLL0, 1 },
202 { P_MMPLL9, 2 },
203 { P_MMPLL2, 3 },
204 { P_MMPLL8, 4 },
205 { P_GPLL0, 5 },
206 { P_GPLL0_DIV, 6 }
207};
208
209static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
210 "xo",
211 "mmpll0",
212 "mmpll9",
213 "mmpll2",
214 "mmpll8",
215 "gpll0",
216 "gpll0_div"
217};
218
219static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
220 { P_XO, 0 },
221 { P_MMPLL0, 1 },
222 { P_MMPLL1, 2 },
223 { P_MMPLL4, 3 },
224 { P_MMPLL3, 4 },
225 { P_GPLL0, 5 },
226 { P_GPLL0_DIV, 6 }
227};
228
229static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
230 "xo",
231 "mmpll0",
232 "mmpll1",
233 "mmpll4",
234 "mmpll3",
235 "gpll0",
236 "gpll0_div"
237};
238
239static struct clk_fixed_factor gpll0_div = {
240 .mult = 1,
241 .div = 2,
242 .hw.init = &(struct clk_init_data){
243 .name = "gpll0_div",
244 .parent_names = (const char *[]){ "gpll0" },
245 .num_parents = 1,
246 .ops = &clk_fixed_factor_ops,
247 },
248};
249
250static struct pll_vco mmpll_p_vco[] = {
251 { 250000000, 500000000, 3 },
252 { 500000000, 1000000000, 2 },
253 { 1000000000, 1500000000, 1 },
254 { 1500000000, 2000000000, 0 },
255};
256
257static struct pll_vco mmpll_gfx_vco[] = {
258 { 400000000, 1000000000, 2 },
259 { 1000000000, 1500000000, 1 },
260 { 1500000000, 2000000000, 0 },
261};
262
263static struct pll_vco mmpll_t_vco[] = {
264 { 500000000, 1500000000, 0 },
265};
266
267static struct clk_alpha_pll mmpll0_early = {
268 .offset = 0x0,
269 .vco_table = mmpll_p_vco,
270 .num_vco = ARRAY_SIZE(mmpll_p_vco),
271 .clkr = {
272 .enable_reg = 0x100,
273 .enable_mask = BIT(0),
274 .hw.init = &(struct clk_init_data){
275 .name = "mmpll0_early",
276 .parent_names = (const char *[]){ "xo" },
277 .num_parents = 1,
278 .ops = &clk_alpha_pll_ops,
279 },
280 },
281};
282
283static struct clk_alpha_pll_postdiv mmpll0 = {
284 .offset = 0x0,
285 .width = 4,
286 .clkr.hw.init = &(struct clk_init_data){
287 .name = "mmpll0",
288 .parent_names = (const char *[]){ "mmpll0_early" },
289 .num_parents = 1,
290 .ops = &clk_alpha_pll_postdiv_ops,
291 .flags = CLK_SET_RATE_PARENT,
292 },
293};
294
295static struct clk_alpha_pll mmpll1_early = {
296 .offset = 0x30,
297 .vco_table = mmpll_p_vco,
298 .num_vco = ARRAY_SIZE(mmpll_p_vco),
299 .clkr = {
300 .enable_reg = 0x100,
301 .enable_mask = BIT(1),
302 .hw.init = &(struct clk_init_data){
303 .name = "mmpll1_early",
304 .parent_names = (const char *[]){ "xo" },
305 .num_parents = 1,
306 .ops = &clk_alpha_pll_ops,
307 }
308 },
309};
310
311static struct clk_alpha_pll_postdiv mmpll1 = {
312 .offset = 0x30,
313 .width = 4,
314 .clkr.hw.init = &(struct clk_init_data){
315 .name = "mmpll1",
316 .parent_names = (const char *[]){ "mmpll1_early" },
317 .num_parents = 1,
318 .ops = &clk_alpha_pll_postdiv_ops,
319 .flags = CLK_SET_RATE_PARENT,
320 },
321};
322
323static struct clk_alpha_pll mmpll2_early = {
324 .offset = 0x4100,
325 .vco_table = mmpll_gfx_vco,
326 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
327 .clkr.hw.init = &(struct clk_init_data){
328 .name = "mmpll2_early",
329 .parent_names = (const char *[]){ "xo" },
330 .num_parents = 1,
331 .ops = &clk_alpha_pll_ops,
332 },
333};
334
335static struct clk_alpha_pll_postdiv mmpll2 = {
336 .offset = 0x4100,
337 .width = 4,
338 .clkr.hw.init = &(struct clk_init_data){
339 .name = "mmpll2",
340 .parent_names = (const char *[]){ "mmpll2_early" },
341 .num_parents = 1,
342 .ops = &clk_alpha_pll_postdiv_ops,
343 .flags = CLK_SET_RATE_PARENT,
344 },
345};
346
347static struct clk_alpha_pll mmpll3_early = {
348 .offset = 0x60,
349 .vco_table = mmpll_p_vco,
350 .num_vco = ARRAY_SIZE(mmpll_p_vco),
351 .clkr.hw.init = &(struct clk_init_data){
352 .name = "mmpll3_early",
353 .parent_names = (const char *[]){ "xo" },
354 .num_parents = 1,
355 .ops = &clk_alpha_pll_ops,
356 },
357};
358
359static struct clk_alpha_pll_postdiv mmpll3 = {
360 .offset = 0x60,
361 .width = 4,
362 .clkr.hw.init = &(struct clk_init_data){
363 .name = "mmpll3",
364 .parent_names = (const char *[]){ "mmpll3_early" },
365 .num_parents = 1,
366 .ops = &clk_alpha_pll_postdiv_ops,
367 .flags = CLK_SET_RATE_PARENT,
368 },
369};
370
371static struct clk_alpha_pll mmpll4_early = {
372 .offset = 0x90,
373 .vco_table = mmpll_t_vco,
374 .num_vco = ARRAY_SIZE(mmpll_t_vco),
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "mmpll4_early",
377 .parent_names = (const char *[]){ "xo" },
378 .num_parents = 1,
379 .ops = &clk_alpha_pll_ops,
380 },
381};
382
383static struct clk_alpha_pll_postdiv mmpll4 = {
384 .offset = 0x90,
385 .width = 2,
386 .clkr.hw.init = &(struct clk_init_data){
387 .name = "mmpll4",
388 .parent_names = (const char *[]){ "mmpll4_early" },
389 .num_parents = 1,
390 .ops = &clk_alpha_pll_postdiv_ops,
391 .flags = CLK_SET_RATE_PARENT,
392 },
393};
394
395static struct clk_alpha_pll mmpll5_early = {
396 .offset = 0xc0,
397 .vco_table = mmpll_p_vco,
398 .num_vco = ARRAY_SIZE(mmpll_p_vco),
399 .clkr.hw.init = &(struct clk_init_data){
400 .name = "mmpll5_early",
401 .parent_names = (const char *[]){ "xo" },
402 .num_parents = 1,
403 .ops = &clk_alpha_pll_ops,
404 },
405};
406
407static struct clk_alpha_pll_postdiv mmpll5 = {
408 .offset = 0xc0,
409 .width = 4,
410 .clkr.hw.init = &(struct clk_init_data){
411 .name = "mmpll5",
412 .parent_names = (const char *[]){ "mmpll5_early" },
413 .num_parents = 1,
414 .ops = &clk_alpha_pll_postdiv_ops,
415 .flags = CLK_SET_RATE_PARENT,
416 },
417};
418
419static struct clk_alpha_pll mmpll8_early = {
420 .offset = 0x4130,
421 .vco_table = mmpll_gfx_vco,
422 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
423 .clkr.hw.init = &(struct clk_init_data){
424 .name = "mmpll8_early",
425 .parent_names = (const char *[]){ "xo" },
426 .num_parents = 1,
427 .ops = &clk_alpha_pll_ops,
428 },
429};
430
431static struct clk_alpha_pll_postdiv mmpll8 = {
432 .offset = 0x4130,
433 .width = 4,
434 .clkr.hw.init = &(struct clk_init_data){
435 .name = "mmpll8",
436 .parent_names = (const char *[]){ "mmpll8_early" },
437 .num_parents = 1,
438 .ops = &clk_alpha_pll_postdiv_ops,
439 .flags = CLK_SET_RATE_PARENT,
440 },
441};
442
443static struct clk_alpha_pll mmpll9_early = {
444 .offset = 0x4200,
445 .vco_table = mmpll_t_vco,
446 .num_vco = ARRAY_SIZE(mmpll_t_vco),
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "mmpll9_early",
449 .parent_names = (const char *[]){ "xo" },
450 .num_parents = 1,
451 .ops = &clk_alpha_pll_ops,
452 },
453};
454
455static struct clk_alpha_pll_postdiv mmpll9 = {
456 .offset = 0x4200,
457 .width = 2,
458 .clkr.hw.init = &(struct clk_init_data){
459 .name = "mmpll9",
460 .parent_names = (const char *[]){ "mmpll9_early" },
461 .num_parents = 1,
462 .ops = &clk_alpha_pll_postdiv_ops,
463 .flags = CLK_SET_RATE_PARENT,
464 },
465};
466
467static const struct freq_tbl ftbl_ahb_clk_src[] = {
468 F(19200000, P_XO, 1, 0, 0),
469 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
470 F(80000000, P_MMPLL0, 10, 0, 0),
471 { }
472};
473
474static struct clk_rcg2 ahb_clk_src = {
475 .cmd_rcgr = 0x5000,
476 .hid_width = 5,
477 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
478 .freq_tbl = ftbl_ahb_clk_src,
479 .clkr.hw.init = &(struct clk_init_data){
480 .name = "ahb_clk_src",
481 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
482 .num_parents = 4,
483 .ops = &clk_rcg2_ops,
484 },
485};
486
487static const struct freq_tbl ftbl_axi_clk_src[] = {
488 F(19200000, P_XO, 1, 0, 0),
489 F(75000000, P_GPLL0_DIV, 4, 0, 0),
490 F(100000000, P_GPLL0, 6, 0, 0),
491 F(171430000, P_GPLL0, 3.5, 0, 0),
492 F(200000000, P_GPLL0, 3, 0, 0),
493 F(320000000, P_MMPLL0, 2.5, 0, 0),
494 F(400000000, P_MMPLL0, 2, 0, 0),
495 { }
496};
497
498static struct clk_rcg2 axi_clk_src = {
499 .cmd_rcgr = 0x5040,
500 .hid_width = 5,
501 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
502 .freq_tbl = ftbl_axi_clk_src,
503 .clkr.hw.init = &(struct clk_init_data){
504 .name = "axi_clk_src",
505 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
506 .num_parents = 5,
507 .ops = &clk_rcg2_ops,
508 },
509};
510
511static struct clk_rcg2 maxi_clk_src = {
512 .cmd_rcgr = 0x5090,
513 .hid_width = 5,
514 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
515 .freq_tbl = ftbl_axi_clk_src,
516 .clkr.hw.init = &(struct clk_init_data){
517 .name = "maxi_clk_src",
518 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
519 .num_parents = 5,
520 .ops = &clk_rcg2_ops,
521 },
522};
523
524static struct clk_rcg2 gfx3d_clk_src = {
525 .cmd_rcgr = 0x4000,
526 .hid_width = 5,
527 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
528 .clkr.hw.init = &(struct clk_init_data){
529 .name = "gfx3d_clk_src",
530 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
531 .num_parents = 6,
532 .ops = &clk_gfx3d_ops,
533 .flags = CLK_SET_RATE_PARENT,
534 },
535};
536
537static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
538 F(19200000, P_XO, 1, 0, 0),
539 { }
540};
541
542static struct clk_rcg2 rbbmtimer_clk_src = {
543 .cmd_rcgr = 0x4090,
544 .hid_width = 5,
545 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
546 .freq_tbl = ftbl_rbbmtimer_clk_src,
547 .clkr.hw.init = &(struct clk_init_data){
548 .name = "rbbmtimer_clk_src",
549 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
550 .num_parents = 4,
551 .ops = &clk_rcg2_ops,
552 },
553};
554
555static struct clk_rcg2 isense_clk_src = {
556 .cmd_rcgr = 0x4010,
557 .hid_width = 5,
558 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "isense_clk_src",
561 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
562 .num_parents = 7,
563 .ops = &clk_rcg2_ops,
564 },
565};
566
567static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
568 F(19200000, P_XO, 1, 0, 0),
569 F(50000000, P_GPLL0, 12, 0, 0),
570 { }
571};
572
573static struct clk_rcg2 rbcpr_clk_src = {
574 .cmd_rcgr = 0x4060,
575 .hid_width = 5,
576 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
577 .freq_tbl = ftbl_rbcpr_clk_src,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "rbcpr_clk_src",
580 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
581 .num_parents = 4,
582 .ops = &clk_rcg2_ops,
583 },
584};
585
586static const struct freq_tbl ftbl_video_core_clk_src[] = {
587 F(75000000, P_GPLL0_DIV, 4, 0, 0),
588 F(150000000, P_GPLL0, 4, 0, 0),
589 F(346666667, P_MMPLL3, 3, 0, 0),
590 F(520000000, P_MMPLL3, 2, 0, 0),
591 { }
592};
593
594static struct clk_rcg2 video_core_clk_src = {
595 .cmd_rcgr = 0x1000,
596 .mnd_width = 8,
597 .hid_width = 5,
598 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
599 .freq_tbl = ftbl_video_core_clk_src,
600 .clkr.hw.init = &(struct clk_init_data){
601 .name = "video_core_clk_src",
602 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
603 .num_parents = 5,
604 .ops = &clk_rcg2_ops,
605 },
606};
607
608static struct clk_rcg2 video_subcore0_clk_src = {
609 .cmd_rcgr = 0x1060,
610 .mnd_width = 8,
611 .hid_width = 5,
612 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
613 .freq_tbl = ftbl_video_core_clk_src,
614 .clkr.hw.init = &(struct clk_init_data){
615 .name = "video_subcore0_clk_src",
616 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
617 .num_parents = 5,
618 .ops = &clk_rcg2_ops,
619 },
620};
621
622static struct clk_rcg2 video_subcore1_clk_src = {
623 .cmd_rcgr = 0x1080,
624 .mnd_width = 8,
625 .hid_width = 5,
626 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
627 .freq_tbl = ftbl_video_core_clk_src,
628 .clkr.hw.init = &(struct clk_init_data){
629 .name = "video_subcore1_clk_src",
630 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
631 .num_parents = 5,
632 .ops = &clk_rcg2_ops,
633 },
634};
635
636static struct clk_rcg2 pclk0_clk_src = {
637 .cmd_rcgr = 0x2000,
638 .mnd_width = 8,
639 .hid_width = 5,
640 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "pclk0_clk_src",
643 .parent_names = mmss_xo_dsi0pll_dsi1pll,
644 .num_parents = 3,
645 .ops = &clk_pixel_ops,
646 .flags = CLK_SET_RATE_PARENT,
647 },
648};
649
650static struct clk_rcg2 pclk1_clk_src = {
651 .cmd_rcgr = 0x2020,
652 .mnd_width = 8,
653 .hid_width = 5,
654 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "pclk1_clk_src",
657 .parent_names = mmss_xo_dsi0pll_dsi1pll,
658 .num_parents = 3,
659 .ops = &clk_pixel_ops,
660 .flags = CLK_SET_RATE_PARENT,
661 },
662};
663
664static const struct freq_tbl ftbl_mdp_clk_src[] = {
665 F(85714286, P_GPLL0, 7, 0, 0),
666 F(100000000, P_GPLL0, 6, 0, 0),
667 F(150000000, P_GPLL0, 4, 0, 0),
668 F(171428571, P_GPLL0, 3.5, 0, 0),
669 F(200000000, P_GPLL0, 3, 0, 0),
670 F(275000000, P_MMPLL5, 3, 0, 0),
671 F(300000000, P_GPLL0, 2, 0, 0),
672 F(330000000, P_MMPLL5, 2.5, 0, 0),
673 F(412500000, P_MMPLL5, 2, 0, 0),
674 { }
675};
676
677static struct clk_rcg2 mdp_clk_src = {
678 .cmd_rcgr = 0x2040,
679 .hid_width = 5,
680 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
681 .freq_tbl = ftbl_mdp_clk_src,
682 .clkr.hw.init = &(struct clk_init_data){
683 .name = "mdp_clk_src",
684 .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
685 .num_parents = 5,
686 .ops = &clk_rcg2_ops,
687 },
688};
689
690static struct freq_tbl extpclk_freq_tbl[] = {
691 { .src = P_HDMIPLL },
692 { }
693};
694
695static struct clk_rcg2 extpclk_clk_src = {
696 .cmd_rcgr = 0x2060,
697 .hid_width = 5,
698 .parent_map = mmss_xo_hdmi_map,
699 .freq_tbl = extpclk_freq_tbl,
700 .clkr.hw.init = &(struct clk_init_data){
701 .name = "extpclk_clk_src",
702 .parent_names = mmss_xo_hdmi,
703 .num_parents = 2,
704 .ops = &clk_byte_ops,
705 .flags = CLK_SET_RATE_PARENT,
706 },
707};
708
709static struct freq_tbl ftbl_mdss_vsync_clk[] = {
710 F(19200000, P_XO, 1, 0, 0),
711 { }
712};
713
714static struct clk_rcg2 vsync_clk_src = {
715 .cmd_rcgr = 0x2080,
716 .hid_width = 5,
717 .parent_map = mmss_xo_gpll0_gpll0_div_map,
718 .freq_tbl = ftbl_mdss_vsync_clk,
719 .clkr.hw.init = &(struct clk_init_data){
720 .name = "vsync_clk_src",
721 .parent_names = mmss_xo_gpll0_gpll0_div,
722 .num_parents = 3,
723 .ops = &clk_rcg2_ops,
724 },
725};
726
727static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
728 F(19200000, P_XO, 1, 0, 0),
729 { }
730};
731
732static struct clk_rcg2 hdmi_clk_src = {
733 .cmd_rcgr = 0x2100,
734 .hid_width = 5,
735 .parent_map = mmss_xo_gpll0_gpll0_div_map,
736 .freq_tbl = ftbl_mdss_hdmi_clk,
737 .clkr.hw.init = &(struct clk_init_data){
738 .name = "hdmi_clk_src",
739 .parent_names = mmss_xo_gpll0_gpll0_div,
740 .num_parents = 3,
741 .ops = &clk_rcg2_ops,
742 },
743};
744
745static struct clk_rcg2 byte0_clk_src = {
746 .cmd_rcgr = 0x2120,
747 .hid_width = 5,
748 .parent_map = mmss_xo_dsibyte_map,
749 .clkr.hw.init = &(struct clk_init_data){
750 .name = "byte0_clk_src",
751 .parent_names = mmss_xo_dsibyte,
752 .num_parents = 3,
753 .ops = &clk_byte2_ops,
754 .flags = CLK_SET_RATE_PARENT,
755 },
756};
757
758static struct clk_rcg2 byte1_clk_src = {
759 .cmd_rcgr = 0x2140,
760 .hid_width = 5,
761 .parent_map = mmss_xo_dsibyte_map,
762 .clkr.hw.init = &(struct clk_init_data){
763 .name = "byte1_clk_src",
764 .parent_names = mmss_xo_dsibyte,
765 .num_parents = 3,
766 .ops = &clk_byte2_ops,
767 .flags = CLK_SET_RATE_PARENT,
768 },
769};
770
771static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
772 F(19200000, P_XO, 1, 0, 0),
773 { }
774};
775
776static struct clk_rcg2 esc0_clk_src = {
777 .cmd_rcgr = 0x2160,
778 .hid_width = 5,
779 .parent_map = mmss_xo_dsibyte_map,
780 .freq_tbl = ftbl_mdss_esc0_1_clk,
781 .clkr.hw.init = &(struct clk_init_data){
782 .name = "esc0_clk_src",
783 .parent_names = mmss_xo_dsibyte,
784 .num_parents = 3,
785 .ops = &clk_rcg2_ops,
786 },
787};
788
789static struct clk_rcg2 esc1_clk_src = {
790 .cmd_rcgr = 0x2180,
791 .hid_width = 5,
792 .parent_map = mmss_xo_dsibyte_map,
793 .freq_tbl = ftbl_mdss_esc0_1_clk,
794 .clkr.hw.init = &(struct clk_init_data){
795 .name = "esc1_clk_src",
796 .parent_names = mmss_xo_dsibyte,
797 .num_parents = 3,
798 .ops = &clk_rcg2_ops,
799 },
800};
801
802static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
803 F(10000, P_XO, 16, 1, 120),
804 F(24000, P_XO, 16, 1, 50),
805 F(6000000, P_GPLL0_DIV, 10, 1, 5),
806 F(12000000, P_GPLL0_DIV, 1, 1, 25),
807 F(13000000, P_GPLL0_DIV, 2, 13, 150),
808 F(24000000, P_GPLL0_DIV, 1, 2, 25),
809 { }
810};
811
812static struct clk_rcg2 camss_gp0_clk_src = {
813 .cmd_rcgr = 0x3420,
814 .mnd_width = 8,
815 .hid_width = 5,
816 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
817 .freq_tbl = ftbl_camss_gp0_clk_src,
818 .clkr.hw.init = &(struct clk_init_data){
819 .name = "camss_gp0_clk_src",
820 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
821 .num_parents = 5,
822 .ops = &clk_rcg2_ops,
823 },
824};
825
826static struct clk_rcg2 camss_gp1_clk_src = {
827 .cmd_rcgr = 0x3450,
828 .mnd_width = 8,
829 .hid_width = 5,
830 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
831 .freq_tbl = ftbl_camss_gp0_clk_src,
832 .clkr.hw.init = &(struct clk_init_data){
833 .name = "camss_gp1_clk_src",
834 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
835 .num_parents = 5,
836 .ops = &clk_rcg2_ops,
837 },
838};
839
840static const struct freq_tbl ftbl_mclk0_clk_src[] = {
841 F(4800000, P_XO, 4, 0, 0),
842 F(6000000, P_GPLL0_DIV, 10, 1, 5),
843 F(8000000, P_GPLL0_DIV, 1, 2, 75),
844 F(9600000, P_XO, 2, 0, 0),
845 F(16666667, P_GPLL0_DIV, 2, 1, 9),
846 F(19200000, P_XO, 1, 0, 0),
847 F(24000000, P_GPLL0_DIV, 1, 2, 25),
848 F(33333333, P_GPLL0_DIV, 1, 1, 9),
849 F(48000000, P_GPLL0, 1, 2, 25),
850 F(66666667, P_GPLL0, 1, 1, 9),
851 { }
852};
853
854static struct clk_rcg2 mclk0_clk_src = {
855 .cmd_rcgr = 0x3360,
856 .mnd_width = 8,
857 .hid_width = 5,
858 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
859 .freq_tbl = ftbl_mclk0_clk_src,
860 .clkr.hw.init = &(struct clk_init_data){
861 .name = "mclk0_clk_src",
862 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
863 .num_parents = 5,
864 .ops = &clk_rcg2_ops,
865 },
866};
867
868static struct clk_rcg2 mclk1_clk_src = {
869 .cmd_rcgr = 0x3390,
870 .mnd_width = 8,
871 .hid_width = 5,
872 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
873 .freq_tbl = ftbl_mclk0_clk_src,
874 .clkr.hw.init = &(struct clk_init_data){
875 .name = "mclk1_clk_src",
876 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
877 .num_parents = 5,
878 .ops = &clk_rcg2_ops,
879 },
880};
881
882static struct clk_rcg2 mclk2_clk_src = {
883 .cmd_rcgr = 0x33c0,
884 .mnd_width = 8,
885 .hid_width = 5,
886 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
887 .freq_tbl = ftbl_mclk0_clk_src,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "mclk2_clk_src",
890 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
891 .num_parents = 5,
892 .ops = &clk_rcg2_ops,
893 },
894};
895
896static struct clk_rcg2 mclk3_clk_src = {
897 .cmd_rcgr = 0x33f0,
898 .mnd_width = 8,
899 .hid_width = 5,
900 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
901 .freq_tbl = ftbl_mclk0_clk_src,
902 .clkr.hw.init = &(struct clk_init_data){
903 .name = "mclk3_clk_src",
904 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
905 .num_parents = 5,
906 .ops = &clk_rcg2_ops,
907 },
908};
909
910static const struct freq_tbl ftbl_cci_clk_src[] = {
911 F(19200000, P_XO, 1, 0, 0),
912 F(37500000, P_GPLL0, 16, 0, 0),
913 F(50000000, P_GPLL0, 12, 0, 0),
914 F(100000000, P_GPLL0, 6, 0, 0),
915 { }
916};
917
918static struct clk_rcg2 cci_clk_src = {
919 .cmd_rcgr = 0x3300,
920 .mnd_width = 8,
921 .hid_width = 5,
922 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
923 .freq_tbl = ftbl_cci_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "cci_clk_src",
926 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
927 .num_parents = 5,
928 .ops = &clk_rcg2_ops,
929 },
930};
931
932static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
933 F(100000000, P_GPLL0_DIV, 3, 0, 0),
934 F(200000000, P_GPLL0, 3, 0, 0),
935 F(266666667, P_MMPLL0, 3, 0, 0),
936 { }
937};
938
939static struct clk_rcg2 csi0phytimer_clk_src = {
940 .cmd_rcgr = 0x3000,
941 .hid_width = 5,
942 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
943 .freq_tbl = ftbl_csi0phytimer_clk_src,
944 .clkr.hw.init = &(struct clk_init_data){
945 .name = "csi0phytimer_clk_src",
946 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
947 .num_parents = 7,
948 .ops = &clk_rcg2_ops,
949 },
950};
951
952static struct clk_rcg2 csi1phytimer_clk_src = {
953 .cmd_rcgr = 0x3030,
954 .hid_width = 5,
955 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
956 .freq_tbl = ftbl_csi0phytimer_clk_src,
957 .clkr.hw.init = &(struct clk_init_data){
958 .name = "csi1phytimer_clk_src",
959 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
960 .num_parents = 7,
961 .ops = &clk_rcg2_ops,
962 },
963};
964
965static struct clk_rcg2 csi2phytimer_clk_src = {
966 .cmd_rcgr = 0x3060,
967 .hid_width = 5,
968 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
969 .freq_tbl = ftbl_csi0phytimer_clk_src,
970 .clkr.hw.init = &(struct clk_init_data){
971 .name = "csi2phytimer_clk_src",
972 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
973 .num_parents = 7,
974 .ops = &clk_rcg2_ops,
975 },
976};
977
978static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
979 F(100000000, P_GPLL0_DIV, 3, 0, 0),
980 F(200000000, P_GPLL0, 3, 0, 0),
981 F(320000000, P_MMPLL4, 3, 0, 0),
982 F(384000000, P_MMPLL4, 2.5, 0, 0),
983 { }
984};
985
986static struct clk_rcg2 csiphy0_3p_clk_src = {
987 .cmd_rcgr = 0x3240,
988 .hid_width = 5,
989 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
990 .freq_tbl = ftbl_csiphy0_3p_clk_src,
991 .clkr.hw.init = &(struct clk_init_data){
992 .name = "csiphy0_3p_clk_src",
993 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
994 .num_parents = 7,
995 .ops = &clk_rcg2_ops,
996 },
997};
998
999static struct clk_rcg2 csiphy1_3p_clk_src = {
1000 .cmd_rcgr = 0x3260,
1001 .hid_width = 5,
1002 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1003 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "csiphy1_3p_clk_src",
1006 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1007 .num_parents = 7,
1008 .ops = &clk_rcg2_ops,
1009 },
1010};
1011
1012static struct clk_rcg2 csiphy2_3p_clk_src = {
1013 .cmd_rcgr = 0x3280,
1014 .hid_width = 5,
1015 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1016 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1017 .clkr.hw.init = &(struct clk_init_data){
1018 .name = "csiphy2_3p_clk_src",
1019 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1020 .num_parents = 7,
1021 .ops = &clk_rcg2_ops,
1022 },
1023};
1024
1025static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1026 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1027 F(150000000, P_GPLL0, 4, 0, 0),
1028 F(228571429, P_MMPLL0, 3.5, 0, 0),
1029 F(266666667, P_MMPLL0, 3, 0, 0),
1030 F(320000000, P_MMPLL0, 2.5, 0, 0),
1031 F(480000000, P_MMPLL4, 2, 0, 0),
1032 { }
1033};
1034
1035static struct clk_rcg2 jpeg0_clk_src = {
1036 .cmd_rcgr = 0x3500,
1037 .hid_width = 5,
1038 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1039 .freq_tbl = ftbl_jpeg0_clk_src,
1040 .clkr.hw.init = &(struct clk_init_data){
1041 .name = "jpeg0_clk_src",
1042 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1043 .num_parents = 7,
1044 .ops = &clk_rcg2_ops,
1045 },
1046};
1047
1048static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
1049 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1050 F(150000000, P_GPLL0, 4, 0, 0),
1051 F(228571429, P_MMPLL0, 3.5, 0, 0),
1052 F(266666667, P_MMPLL0, 3, 0, 0),
1053 F(320000000, P_MMPLL0, 2.5, 0, 0),
1054 { }
1055};
1056
1057static struct clk_rcg2 jpeg2_clk_src = {
1058 .cmd_rcgr = 0x3540,
1059 .hid_width = 5,
1060 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1061 .freq_tbl = ftbl_jpeg2_clk_src,
1062 .clkr.hw.init = &(struct clk_init_data){
1063 .name = "jpeg2_clk_src",
1064 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1065 .num_parents = 7,
1066 .ops = &clk_rcg2_ops,
1067 },
1068};
1069
1070static struct clk_rcg2 jpeg_dma_clk_src = {
1071 .cmd_rcgr = 0x3560,
1072 .hid_width = 5,
1073 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1074 .freq_tbl = ftbl_jpeg0_clk_src,
1075 .clkr.hw.init = &(struct clk_init_data){
1076 .name = "jpeg_dma_clk_src",
1077 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1078 .num_parents = 7,
1079 .ops = &clk_rcg2_ops,
1080 },
1081};
1082
1083static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1084 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1085 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1086 F(300000000, P_GPLL0, 2, 0, 0),
1087 F(320000000, P_MMPLL0, 2.5, 0, 0),
1088 F(480000000, P_MMPLL4, 2, 0, 0),
1089 F(600000000, P_GPLL0, 1, 0, 0),
1090 { }
1091};
1092
1093static struct clk_rcg2 vfe0_clk_src = {
1094 .cmd_rcgr = 0x3600,
1095 .hid_width = 5,
1096 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1097 .freq_tbl = ftbl_vfe0_clk_src,
1098 .clkr.hw.init = &(struct clk_init_data){
1099 .name = "vfe0_clk_src",
1100 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1101 .num_parents = 7,
1102 .ops = &clk_rcg2_ops,
1103 },
1104};
1105
1106static struct clk_rcg2 vfe1_clk_src = {
1107 .cmd_rcgr = 0x3620,
1108 .hid_width = 5,
1109 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1110 .freq_tbl = ftbl_vfe0_clk_src,
1111 .clkr.hw.init = &(struct clk_init_data){
1112 .name = "vfe1_clk_src",
1113 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1114 .num_parents = 7,
1115 .ops = &clk_rcg2_ops,
1116 },
1117};
1118
1119static const struct freq_tbl ftbl_cpp_clk_src[] = {
1120 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1121 F(200000000, P_GPLL0, 3, 0, 0),
1122 F(320000000, P_MMPLL0, 2.5, 0, 0),
1123 F(480000000, P_MMPLL4, 2, 0, 0),
1124 F(640000000, P_MMPLL4, 1.5, 0, 0),
1125 { }
1126};
1127
1128static struct clk_rcg2 cpp_clk_src = {
1129 .cmd_rcgr = 0x3640,
1130 .hid_width = 5,
1131 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1132 .freq_tbl = ftbl_cpp_clk_src,
1133 .clkr.hw.init = &(struct clk_init_data){
1134 .name = "cpp_clk_src",
1135 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1136 .num_parents = 7,
1137 .ops = &clk_rcg2_ops,
1138 },
1139};
1140
1141static const struct freq_tbl ftbl_csi0_clk_src[] = {
1142 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1143 F(200000000, P_GPLL0, 3, 0, 0),
1144 F(266666667, P_MMPLL0, 3, 0, 0),
1145 F(480000000, P_MMPLL4, 2, 0, 0),
1146 F(600000000, P_GPLL0, 1, 0, 0),
1147 { }
1148};
1149
1150static struct clk_rcg2 csi0_clk_src = {
1151 .cmd_rcgr = 0x3090,
1152 .hid_width = 5,
1153 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1154 .freq_tbl = ftbl_csi0_clk_src,
1155 .clkr.hw.init = &(struct clk_init_data){
1156 .name = "csi0_clk_src",
1157 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1158 .num_parents = 7,
1159 .ops = &clk_rcg2_ops,
1160 },
1161};
1162
1163static struct clk_rcg2 csi1_clk_src = {
1164 .cmd_rcgr = 0x3100,
1165 .hid_width = 5,
1166 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1167 .freq_tbl = ftbl_csi0_clk_src,
1168 .clkr.hw.init = &(struct clk_init_data){
1169 .name = "csi1_clk_src",
1170 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1171 .num_parents = 7,
1172 .ops = &clk_rcg2_ops,
1173 },
1174};
1175
1176static struct clk_rcg2 csi2_clk_src = {
1177 .cmd_rcgr = 0x3160,
1178 .hid_width = 5,
1179 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1180 .freq_tbl = ftbl_csi0_clk_src,
1181 .clkr.hw.init = &(struct clk_init_data){
1182 .name = "csi2_clk_src",
1183 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1184 .num_parents = 7,
1185 .ops = &clk_rcg2_ops,
1186 },
1187};
1188
1189static struct clk_rcg2 csi3_clk_src = {
1190 .cmd_rcgr = 0x31c0,
1191 .hid_width = 5,
1192 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1193 .freq_tbl = ftbl_csi0_clk_src,
1194 .clkr.hw.init = &(struct clk_init_data){
1195 .name = "csi3_clk_src",
1196 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1197 .num_parents = 7,
1198 .ops = &clk_rcg2_ops,
1199 },
1200};
1201
1202static const struct freq_tbl ftbl_fd_core_clk_src[] = {
1203 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1204 F(200000000, P_GPLL0, 3, 0, 0),
1205 F(400000000, P_MMPLL0, 2, 0, 0),
1206 { }
1207};
1208
1209static struct clk_rcg2 fd_core_clk_src = {
1210 .cmd_rcgr = 0x3b00,
1211 .hid_width = 5,
1212 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
1213 .freq_tbl = ftbl_fd_core_clk_src,
1214 .clkr.hw.init = &(struct clk_init_data){
1215 .name = "fd_core_clk_src",
1216 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1217 .num_parents = 5,
1218 .ops = &clk_rcg2_ops,
1219 },
1220};
1221
1222static struct clk_branch mmss_mmagic_ahb_clk = {
1223 .halt_reg = 0x5024,
1224 .clkr = {
1225 .enable_reg = 0x5024,
1226 .enable_mask = BIT(0),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "mmss_mmagic_ahb_clk",
1229 .parent_names = (const char *[]){ "ahb_clk_src" },
1230 .num_parents = 1,
1231 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1232 .ops = &clk_branch2_ops,
1233 },
1234 },
1235};
1236
1237static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1238 .halt_reg = 0x5054,
1239 .clkr = {
1240 .enable_reg = 0x5054,
1241 .enable_mask = BIT(0),
1242 .hw.init = &(struct clk_init_data){
1243 .name = "mmss_mmagic_cfg_ahb_clk",
1244 .parent_names = (const char *[]){ "ahb_clk_src" },
1245 .num_parents = 1,
1246 .flags = CLK_SET_RATE_PARENT,
1247 .ops = &clk_branch2_ops,
1248 },
1249 },
1250};
1251
1252static struct clk_branch mmss_misc_ahb_clk = {
1253 .halt_reg = 0x5018,
1254 .clkr = {
1255 .enable_reg = 0x5018,
1256 .enable_mask = BIT(0),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "mmss_misc_ahb_clk",
1259 .parent_names = (const char *[]){ "ahb_clk_src" },
1260 .num_parents = 1,
1261 .flags = CLK_SET_RATE_PARENT,
1262 .ops = &clk_branch2_ops,
1263 },
1264 },
1265};
1266
1267static struct clk_branch mmss_misc_cxo_clk = {
1268 .halt_reg = 0x5014,
1269 .clkr = {
1270 .enable_reg = 0x5014,
1271 .enable_mask = BIT(0),
1272 .hw.init = &(struct clk_init_data){
1273 .name = "mmss_misc_cxo_clk",
1274 .parent_names = (const char *[]){ "xo" },
1275 .num_parents = 1,
1276 .ops = &clk_branch2_ops,
1277 },
1278 },
1279};
1280
1281static struct clk_branch mmss_mmagic_axi_clk = {
1282 .halt_reg = 0x506c,
1283 .clkr = {
1284 .enable_reg = 0x506c,
1285 .enable_mask = BIT(0),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "mmss_mmagic_axi_clk",
1288 .parent_names = (const char *[]){ "axi_clk_src" },
1289 .num_parents = 1,
1290 .flags = CLK_SET_RATE_PARENT,
1291 .ops = &clk_branch2_ops,
1292 },
1293 },
1294};
1295
1296static struct clk_branch mmss_mmagic_maxi_clk = {
1297 .halt_reg = 0x5074,
1298 .clkr = {
1299 .enable_reg = 0x5074,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "mmss_mmagic_maxi_clk",
1303 .parent_names = (const char *[]){ "maxi_clk_src" },
1304 .num_parents = 1,
1305 .flags = CLK_SET_RATE_PARENT,
1306 .ops = &clk_branch2_ops,
1307 },
1308 },
1309};
1310
1311static struct clk_branch mmagic_camss_axi_clk = {
1312 .halt_reg = 0x3c44,
1313 .clkr = {
1314 .enable_reg = 0x3c44,
1315 .enable_mask = BIT(0),
1316 .hw.init = &(struct clk_init_data){
1317 .name = "mmagic_camss_axi_clk",
1318 .parent_names = (const char *[]){ "axi_clk_src" },
1319 .num_parents = 1,
1320 .flags = CLK_SET_RATE_PARENT,
1321 .ops = &clk_branch2_ops,
1322 },
1323 },
1324};
1325
1326static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1327 .halt_reg = 0x3c48,
1328 .clkr = {
1329 .enable_reg = 0x3c48,
1330 .enable_mask = BIT(0),
1331 .hw.init = &(struct clk_init_data){
1332 .name = "mmagic_camss_noc_cfg_ahb_clk",
1333 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1334 .num_parents = 1,
1335 .flags = CLK_SET_RATE_PARENT,
1336 .ops = &clk_branch2_ops,
1337 },
1338 },
1339};
1340
1341static struct clk_branch smmu_vfe_ahb_clk = {
1342 .halt_reg = 0x3c04,
1343 .clkr = {
1344 .enable_reg = 0x3c04,
1345 .enable_mask = BIT(0),
1346 .hw.init = &(struct clk_init_data){
1347 .name = "smmu_vfe_ahb_clk",
1348 .parent_names = (const char *[]){ "ahb_clk_src" },
1349 .num_parents = 1,
1350 .flags = CLK_SET_RATE_PARENT,
1351 .ops = &clk_branch2_ops,
1352 },
1353 },
1354};
1355
1356static struct clk_branch smmu_vfe_axi_clk = {
1357 .halt_reg = 0x3c08,
1358 .clkr = {
1359 .enable_reg = 0x3c08,
1360 .enable_mask = BIT(0),
1361 .hw.init = &(struct clk_init_data){
1362 .name = "smmu_vfe_axi_clk",
1363 .parent_names = (const char *[]){ "axi_clk_src" },
1364 .num_parents = 1,
1365 .flags = CLK_SET_RATE_PARENT,
1366 .ops = &clk_branch2_ops,
1367 },
1368 },
1369};
1370
1371static struct clk_branch smmu_cpp_ahb_clk = {
1372 .halt_reg = 0x3c14,
1373 .clkr = {
1374 .enable_reg = 0x3c14,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data){
1377 .name = "smmu_cpp_ahb_clk",
1378 .parent_names = (const char *[]){ "ahb_clk_src" },
1379 .num_parents = 1,
1380 .flags = CLK_SET_RATE_PARENT,
1381 .ops = &clk_branch2_ops,
1382 },
1383 },
1384};
1385
1386static struct clk_branch smmu_cpp_axi_clk = {
1387 .halt_reg = 0x3c18,
1388 .clkr = {
1389 .enable_reg = 0x3c18,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "smmu_cpp_axi_clk",
1393 .parent_names = (const char *[]){ "axi_clk_src" },
1394 .num_parents = 1,
1395 .flags = CLK_SET_RATE_PARENT,
1396 .ops = &clk_branch2_ops,
1397 },
1398 },
1399};
1400
1401static struct clk_branch smmu_jpeg_ahb_clk = {
1402 .halt_reg = 0x3c24,
1403 .clkr = {
1404 .enable_reg = 0x3c24,
1405 .enable_mask = BIT(0),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "smmu_jpeg_ahb_clk",
1408 .parent_names = (const char *[]){ "ahb_clk_src" },
1409 .num_parents = 1,
1410 .flags = CLK_SET_RATE_PARENT,
1411 .ops = &clk_branch2_ops,
1412 },
1413 },
1414};
1415
1416static struct clk_branch smmu_jpeg_axi_clk = {
1417 .halt_reg = 0x3c28,
1418 .clkr = {
1419 .enable_reg = 0x3c28,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "smmu_jpeg_axi_clk",
1423 .parent_names = (const char *[]){ "axi_clk_src" },
1424 .num_parents = 1,
1425 .flags = CLK_SET_RATE_PARENT,
1426 .ops = &clk_branch2_ops,
1427 },
1428 },
1429};
1430
1431static struct clk_branch mmagic_mdss_axi_clk = {
1432 .halt_reg = 0x2474,
1433 .clkr = {
1434 .enable_reg = 0x2474,
1435 .enable_mask = BIT(0),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "mmagic_mdss_axi_clk",
1438 .parent_names = (const char *[]){ "axi_clk_src" },
1439 .num_parents = 1,
1440 .flags = CLK_SET_RATE_PARENT,
1441 .ops = &clk_branch2_ops,
1442 },
1443 },
1444};
1445
1446static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1447 .halt_reg = 0x2478,
1448 .clkr = {
1449 .enable_reg = 0x2478,
1450 .enable_mask = BIT(0),
1451 .hw.init = &(struct clk_init_data){
1452 .name = "mmagic_mdss_noc_cfg_ahb_clk",
1453 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1454 .num_parents = 1,
1455 .flags = CLK_SET_RATE_PARENT,
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch smmu_rot_ahb_clk = {
1462 .halt_reg = 0x2444,
1463 .clkr = {
1464 .enable_reg = 0x2444,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "smmu_rot_ahb_clk",
1468 .parent_names = (const char *[]){ "ahb_clk_src" },
1469 .num_parents = 1,
1470 .flags = CLK_SET_RATE_PARENT,
1471 .ops = &clk_branch2_ops,
1472 },
1473 },
1474};
1475
1476static struct clk_branch smmu_rot_axi_clk = {
1477 .halt_reg = 0x2448,
1478 .clkr = {
1479 .enable_reg = 0x2448,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "smmu_rot_axi_clk",
1483 .parent_names = (const char *[]){ "axi_clk_src" },
1484 .num_parents = 1,
1485 .flags = CLK_SET_RATE_PARENT,
1486 .ops = &clk_branch2_ops,
1487 },
1488 },
1489};
1490
1491static struct clk_branch smmu_mdp_ahb_clk = {
1492 .halt_reg = 0x2454,
1493 .clkr = {
1494 .enable_reg = 0x2454,
1495 .enable_mask = BIT(0),
1496 .hw.init = &(struct clk_init_data){
1497 .name = "smmu_mdp_ahb_clk",
1498 .parent_names = (const char *[]){ "ahb_clk_src" },
1499 .num_parents = 1,
1500 .flags = CLK_SET_RATE_PARENT,
1501 .ops = &clk_branch2_ops,
1502 },
1503 },
1504};
1505
1506static struct clk_branch smmu_mdp_axi_clk = {
1507 .halt_reg = 0x2458,
1508 .clkr = {
1509 .enable_reg = 0x2458,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "smmu_mdp_axi_clk",
1513 .parent_names = (const char *[]){ "axi_clk_src" },
1514 .num_parents = 1,
1515 .flags = CLK_SET_RATE_PARENT,
1516 .ops = &clk_branch2_ops,
1517 },
1518 },
1519};
1520
1521static struct clk_branch mmagic_video_axi_clk = {
1522 .halt_reg = 0x1194,
1523 .clkr = {
1524 .enable_reg = 0x1194,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "mmagic_video_axi_clk",
1528 .parent_names = (const char *[]){ "axi_clk_src" },
1529 .num_parents = 1,
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1532 },
1533 },
1534};
1535
1536static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1537 .halt_reg = 0x1198,
1538 .clkr = {
1539 .enable_reg = 0x1198,
1540 .enable_mask = BIT(0),
1541 .hw.init = &(struct clk_init_data){
1542 .name = "mmagic_video_noc_cfg_ahb_clk",
1543 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1544 .num_parents = 1,
1545 .flags = CLK_SET_RATE_PARENT,
1546 .ops = &clk_branch2_ops,
1547 },
1548 },
1549};
1550
1551static struct clk_branch smmu_video_ahb_clk = {
1552 .halt_reg = 0x1174,
1553 .clkr = {
1554 .enable_reg = 0x1174,
1555 .enable_mask = BIT(0),
1556 .hw.init = &(struct clk_init_data){
1557 .name = "smmu_video_ahb_clk",
1558 .parent_names = (const char *[]){ "ahb_clk_src" },
1559 .num_parents = 1,
1560 .flags = CLK_SET_RATE_PARENT,
1561 .ops = &clk_branch2_ops,
1562 },
1563 },
1564};
1565
1566static struct clk_branch smmu_video_axi_clk = {
1567 .halt_reg = 0x1178,
1568 .clkr = {
1569 .enable_reg = 0x1178,
1570 .enable_mask = BIT(0),
1571 .hw.init = &(struct clk_init_data){
1572 .name = "smmu_video_axi_clk",
1573 .parent_names = (const char *[]){ "axi_clk_src" },
1574 .num_parents = 1,
1575 .flags = CLK_SET_RATE_PARENT,
1576 .ops = &clk_branch2_ops,
1577 },
1578 },
1579};
1580
1581static struct clk_branch mmagic_bimc_axi_clk = {
1582 .halt_reg = 0x5294,
1583 .clkr = {
1584 .enable_reg = 0x5294,
1585 .enable_mask = BIT(0),
1586 .hw.init = &(struct clk_init_data){
1587 .name = "mmagic_bimc_axi_clk",
1588 .parent_names = (const char *[]){ "axi_clk_src" },
1589 .num_parents = 1,
1590 .flags = CLK_SET_RATE_PARENT,
1591 .ops = &clk_branch2_ops,
1592 },
1593 },
1594};
1595
1596static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
1597 .halt_reg = 0x5298,
1598 .clkr = {
1599 .enable_reg = 0x5298,
1600 .enable_mask = BIT(0),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "mmagic_bimc_noc_cfg_ahb_clk",
1603 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1604 .num_parents = 1,
1605 .flags = CLK_SET_RATE_PARENT,
1606 .ops = &clk_branch2_ops,
1607 },
1608 },
1609};
1610
1611static struct clk_branch gpu_gx_gfx3d_clk = {
1612 .halt_reg = 0x4028,
1613 .clkr = {
1614 .enable_reg = 0x4028,
1615 .enable_mask = BIT(0),
1616 .hw.init = &(struct clk_init_data){
1617 .name = "gpu_gx_gfx3d_clk",
1618 .parent_names = (const char *[]){ "gfx3d_clk_src" },
1619 .num_parents = 1,
1620 .flags = CLK_SET_RATE_PARENT,
1621 .ops = &clk_branch2_ops,
1622 },
1623 },
1624};
1625
1626static struct clk_branch gpu_gx_rbbmtimer_clk = {
1627 .halt_reg = 0x40b0,
1628 .clkr = {
1629 .enable_reg = 0x40b0,
1630 .enable_mask = BIT(0),
1631 .hw.init = &(struct clk_init_data){
1632 .name = "gpu_gx_rbbmtimer_clk",
1633 .parent_names = (const char *[]){ "rbbmtimer_clk_src" },
1634 .num_parents = 1,
1635 .flags = CLK_SET_RATE_PARENT,
1636 .ops = &clk_branch2_ops,
1637 },
1638 },
1639};
1640
1641static struct clk_branch gpu_ahb_clk = {
1642 .halt_reg = 0x403c,
1643 .clkr = {
1644 .enable_reg = 0x403c,
1645 .enable_mask = BIT(0),
1646 .hw.init = &(struct clk_init_data){
1647 .name = "gpu_ahb_clk",
1648 .parent_names = (const char *[]){ "ahb_clk_src" },
1649 .num_parents = 1,
1650 .flags = CLK_SET_RATE_PARENT,
1651 .ops = &clk_branch2_ops,
1652 },
1653 },
1654};
1655
1656static struct clk_branch gpu_aon_isense_clk = {
1657 .halt_reg = 0x4044,
1658 .clkr = {
1659 .enable_reg = 0x4044,
1660 .enable_mask = BIT(0),
1661 .hw.init = &(struct clk_init_data){
1662 .name = "gpu_aon_isense_clk",
1663 .parent_names = (const char *[]){ "isense_clk_src" },
1664 .num_parents = 1,
1665 .flags = CLK_SET_RATE_PARENT,
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669};
1670
1671static struct clk_branch vmem_maxi_clk = {
1672 .halt_reg = 0x1204,
1673 .clkr = {
1674 .enable_reg = 0x1204,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "vmem_maxi_clk",
1678 .parent_names = (const char *[]){ "maxi_clk_src" },
1679 .num_parents = 1,
1680 .flags = CLK_SET_RATE_PARENT,
1681 .ops = &clk_branch2_ops,
1682 },
1683 },
1684};
1685
1686static struct clk_branch vmem_ahb_clk = {
1687 .halt_reg = 0x1208,
1688 .clkr = {
1689 .enable_reg = 0x1208,
1690 .enable_mask = BIT(0),
1691 .hw.init = &(struct clk_init_data){
1692 .name = "vmem_ahb_clk",
1693 .parent_names = (const char *[]){ "ahb_clk_src" },
1694 .num_parents = 1,
1695 .flags = CLK_SET_RATE_PARENT,
1696 .ops = &clk_branch2_ops,
1697 },
1698 },
1699};
1700
1701static struct clk_branch mmss_rbcpr_clk = {
1702 .halt_reg = 0x4084,
1703 .clkr = {
1704 .enable_reg = 0x4084,
1705 .enable_mask = BIT(0),
1706 .hw.init = &(struct clk_init_data){
1707 .name = "mmss_rbcpr_clk",
1708 .parent_names = (const char *[]){ "rbcpr_clk_src" },
1709 .num_parents = 1,
1710 .flags = CLK_SET_RATE_PARENT,
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714};
1715
1716static struct clk_branch mmss_rbcpr_ahb_clk = {
1717 .halt_reg = 0x4088,
1718 .clkr = {
1719 .enable_reg = 0x4088,
1720 .enable_mask = BIT(0),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "mmss_rbcpr_ahb_clk",
1723 .parent_names = (const char *[]){ "ahb_clk_src" },
1724 .num_parents = 1,
1725 .flags = CLK_SET_RATE_PARENT,
1726 .ops = &clk_branch2_ops,
1727 },
1728 },
1729};
1730
1731static struct clk_branch video_core_clk = {
1732 .halt_reg = 0x1028,
1733 .clkr = {
1734 .enable_reg = 0x1028,
1735 .enable_mask = BIT(0),
1736 .hw.init = &(struct clk_init_data){
1737 .name = "video_core_clk",
1738 .parent_names = (const char *[]){ "video_core_clk_src" },
1739 .num_parents = 1,
1740 .flags = CLK_SET_RATE_PARENT,
1741 .ops = &clk_branch2_ops,
1742 },
1743 },
1744};
1745
1746static struct clk_branch video_axi_clk = {
1747 .halt_reg = 0x1034,
1748 .clkr = {
1749 .enable_reg = 0x1034,
1750 .enable_mask = BIT(0),
1751 .hw.init = &(struct clk_init_data){
1752 .name = "video_axi_clk",
1753 .parent_names = (const char *[]){ "axi_clk_src" },
1754 .num_parents = 1,
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1757 },
1758 },
1759};
1760
1761static struct clk_branch video_maxi_clk = {
1762 .halt_reg = 0x1038,
1763 .clkr = {
1764 .enable_reg = 0x1038,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "video_maxi_clk",
1768 .parent_names = (const char *[]){ "maxi_clk_src" },
1769 .num_parents = 1,
1770 .flags = CLK_SET_RATE_PARENT,
1771 .ops = &clk_branch2_ops,
1772 },
1773 },
1774};
1775
1776static struct clk_branch video_ahb_clk = {
1777 .halt_reg = 0x1030,
1778 .clkr = {
1779 .enable_reg = 0x1030,
1780 .enable_mask = BIT(0),
1781 .hw.init = &(struct clk_init_data){
1782 .name = "video_ahb_clk",
1783 .parent_names = (const char *[]){ "ahb_clk_src" },
1784 .num_parents = 1,
1785 .flags = CLK_SET_RATE_PARENT,
1786 .ops = &clk_branch2_ops,
1787 },
1788 },
1789};
1790
1791static struct clk_branch video_subcore0_clk = {
1792 .halt_reg = 0x1048,
1793 .clkr = {
1794 .enable_reg = 0x1048,
1795 .enable_mask = BIT(0),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "video_subcore0_clk",
1798 .parent_names = (const char *[]){ "video_subcore0_clk_src" },
1799 .num_parents = 1,
1800 .flags = CLK_SET_RATE_PARENT,
1801 .ops = &clk_branch2_ops,
1802 },
1803 },
1804};
1805
1806static struct clk_branch video_subcore1_clk = {
1807 .halt_reg = 0x104c,
1808 .clkr = {
1809 .enable_reg = 0x104c,
1810 .enable_mask = BIT(0),
1811 .hw.init = &(struct clk_init_data){
1812 .name = "video_subcore1_clk",
1813 .parent_names = (const char *[]){ "video_subcore1_clk_src" },
1814 .num_parents = 1,
1815 .flags = CLK_SET_RATE_PARENT,
1816 .ops = &clk_branch2_ops,
1817 },
1818 },
1819};
1820
1821static struct clk_branch mdss_ahb_clk = {
1822 .halt_reg = 0x2308,
1823 .clkr = {
1824 .enable_reg = 0x2308,
1825 .enable_mask = BIT(0),
1826 .hw.init = &(struct clk_init_data){
1827 .name = "mdss_ahb_clk",
1828 .parent_names = (const char *[]){ "ahb_clk_src" },
1829 .num_parents = 1,
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1832 },
1833 },
1834};
1835
1836static struct clk_branch mdss_hdmi_ahb_clk = {
1837 .halt_reg = 0x230c,
1838 .clkr = {
1839 .enable_reg = 0x230c,
1840 .enable_mask = BIT(0),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "mdss_hdmi_ahb_clk",
1843 .parent_names = (const char *[]){ "ahb_clk_src" },
1844 .num_parents = 1,
1845 .flags = CLK_SET_RATE_PARENT,
1846 .ops = &clk_branch2_ops,
1847 },
1848 },
1849};
1850
1851static struct clk_branch mdss_axi_clk = {
1852 .halt_reg = 0x2310,
1853 .clkr = {
1854 .enable_reg = 0x2310,
1855 .enable_mask = BIT(0),
1856 .hw.init = &(struct clk_init_data){
1857 .name = "mdss_axi_clk",
1858 .parent_names = (const char *[]){ "axi_clk_src" },
1859 .num_parents = 1,
1860 .flags = CLK_SET_RATE_PARENT,
1861 .ops = &clk_branch2_ops,
1862 },
1863 },
1864};
1865
1866static struct clk_branch mdss_pclk0_clk = {
1867 .halt_reg = 0x2314,
1868 .clkr = {
1869 .enable_reg = 0x2314,
1870 .enable_mask = BIT(0),
1871 .hw.init = &(struct clk_init_data){
1872 .name = "mdss_pclk0_clk",
1873 .parent_names = (const char *[]){ "pclk0_clk_src" },
1874 .num_parents = 1,
1875 .flags = CLK_SET_RATE_PARENT,
1876 .ops = &clk_branch2_ops,
1877 },
1878 },
1879};
1880
1881static struct clk_branch mdss_pclk1_clk = {
1882 .halt_reg = 0x2318,
1883 .clkr = {
1884 .enable_reg = 0x2318,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "mdss_pclk1_clk",
1888 .parent_names = (const char *[]){ "pclk1_clk_src" },
1889 .num_parents = 1,
1890 .flags = CLK_SET_RATE_PARENT,
1891 .ops = &clk_branch2_ops,
1892 },
1893 },
1894};
1895
1896static struct clk_branch mdss_mdp_clk = {
1897 .halt_reg = 0x231c,
1898 .clkr = {
1899 .enable_reg = 0x231c,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "mdss_mdp_clk",
1903 .parent_names = (const char *[]){ "mdp_clk_src" },
1904 .num_parents = 1,
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1907 },
1908 },
1909};
1910
1911static struct clk_branch mdss_extpclk_clk = {
1912 .halt_reg = 0x2324,
1913 .clkr = {
1914 .enable_reg = 0x2324,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data){
1917 .name = "mdss_extpclk_clk",
1918 .parent_names = (const char *[]){ "extpclk_clk_src" },
1919 .num_parents = 1,
1920 .flags = CLK_SET_RATE_PARENT,
1921 .ops = &clk_branch2_ops,
1922 },
1923 },
1924};
1925
1926static struct clk_branch mdss_vsync_clk = {
1927 .halt_reg = 0x2328,
1928 .clkr = {
1929 .enable_reg = 0x2328,
1930 .enable_mask = BIT(0),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "mdss_vsync_clk",
1933 .parent_names = (const char *[]){ "vsync_clk_src" },
1934 .num_parents = 1,
1935 .flags = CLK_SET_RATE_PARENT,
1936 .ops = &clk_branch2_ops,
1937 },
1938 },
1939};
1940
1941static struct clk_branch mdss_hdmi_clk = {
1942 .halt_reg = 0x2338,
1943 .clkr = {
1944 .enable_reg = 0x2338,
1945 .enable_mask = BIT(0),
1946 .hw.init = &(struct clk_init_data){
1947 .name = "mdss_hdmi_clk",
1948 .parent_names = (const char *[]){ "hdmi_clk_src" },
1949 .num_parents = 1,
1950 .flags = CLK_SET_RATE_PARENT,
1951 .ops = &clk_branch2_ops,
1952 },
1953 },
1954};
1955
1956static struct clk_branch mdss_byte0_clk = {
1957 .halt_reg = 0x233c,
1958 .clkr = {
1959 .enable_reg = 0x233c,
1960 .enable_mask = BIT(0),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "mdss_byte0_clk",
1963 .parent_names = (const char *[]){ "byte0_clk_src" },
1964 .num_parents = 1,
1965 .flags = CLK_SET_RATE_PARENT,
1966 .ops = &clk_branch2_ops,
1967 },
1968 },
1969};
1970
1971static struct clk_branch mdss_byte1_clk = {
1972 .halt_reg = 0x2340,
1973 .clkr = {
1974 .enable_reg = 0x2340,
1975 .enable_mask = BIT(0),
1976 .hw.init = &(struct clk_init_data){
1977 .name = "mdss_byte1_clk",
1978 .parent_names = (const char *[]){ "byte1_clk_src" },
1979 .num_parents = 1,
1980 .flags = CLK_SET_RATE_PARENT,
1981 .ops = &clk_branch2_ops,
1982 },
1983 },
1984};
1985
1986static struct clk_branch mdss_esc0_clk = {
1987 .halt_reg = 0x2344,
1988 .clkr = {
1989 .enable_reg = 0x2344,
1990 .enable_mask = BIT(0),
1991 .hw.init = &(struct clk_init_data){
1992 .name = "mdss_esc0_clk",
1993 .parent_names = (const char *[]){ "esc0_clk_src" },
1994 .num_parents = 1,
1995 .flags = CLK_SET_RATE_PARENT,
1996 .ops = &clk_branch2_ops,
1997 },
1998 },
1999};
2000
2001static struct clk_branch mdss_esc1_clk = {
2002 .halt_reg = 0x2348,
2003 .clkr = {
2004 .enable_reg = 0x2348,
2005 .enable_mask = BIT(0),
2006 .hw.init = &(struct clk_init_data){
2007 .name = "mdss_esc1_clk",
2008 .parent_names = (const char *[]){ "esc1_clk_src" },
2009 .num_parents = 1,
2010 .flags = CLK_SET_RATE_PARENT,
2011 .ops = &clk_branch2_ops,
2012 },
2013 },
2014};
2015
2016static struct clk_branch camss_top_ahb_clk = {
2017 .halt_reg = 0x3484,
2018 .clkr = {
2019 .enable_reg = 0x3484,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data){
2022 .name = "camss_top_ahb_clk",
2023 .parent_names = (const char *[]){ "ahb_clk_src" },
2024 .num_parents = 1,
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2027 },
2028 },
2029};
2030
2031static struct clk_branch camss_ahb_clk = {
2032 .halt_reg = 0x348c,
2033 .clkr = {
2034 .enable_reg = 0x348c,
2035 .enable_mask = BIT(0),
2036 .hw.init = &(struct clk_init_data){
2037 .name = "camss_ahb_clk",
2038 .parent_names = (const char *[]){ "ahb_clk_src" },
2039 .num_parents = 1,
2040 .flags = CLK_SET_RATE_PARENT,
2041 .ops = &clk_branch2_ops,
2042 },
2043 },
2044};
2045
2046static struct clk_branch camss_micro_ahb_clk = {
2047 .halt_reg = 0x3494,
2048 .clkr = {
2049 .enable_reg = 0x3494,
2050 .enable_mask = BIT(0),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "camss_micro_ahb_clk",
2053 .parent_names = (const char *[]){ "ahb_clk_src" },
2054 .num_parents = 1,
2055 .flags = CLK_SET_RATE_PARENT,
2056 .ops = &clk_branch2_ops,
2057 },
2058 },
2059};
2060
2061static struct clk_branch camss_gp0_clk = {
2062 .halt_reg = 0x3444,
2063 .clkr = {
2064 .enable_reg = 0x3444,
2065 .enable_mask = BIT(0),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "camss_gp0_clk",
2068 .parent_names = (const char *[]){ "camss_gp0_clk_src" },
2069 .num_parents = 1,
2070 .flags = CLK_SET_RATE_PARENT,
2071 .ops = &clk_branch2_ops,
2072 },
2073 },
2074};
2075
2076static struct clk_branch camss_gp1_clk = {
2077 .halt_reg = 0x3474,
2078 .clkr = {
2079 .enable_reg = 0x3474,
2080 .enable_mask = BIT(0),
2081 .hw.init = &(struct clk_init_data){
2082 .name = "camss_gp1_clk",
2083 .parent_names = (const char *[]){ "camss_gp1_clk_src" },
2084 .num_parents = 1,
2085 .flags = CLK_SET_RATE_PARENT,
2086 .ops = &clk_branch2_ops,
2087 },
2088 },
2089};
2090
2091static struct clk_branch camss_mclk0_clk = {
2092 .halt_reg = 0x3384,
2093 .clkr = {
2094 .enable_reg = 0x3384,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "camss_mclk0_clk",
2098 .parent_names = (const char *[]){ "mclk0_clk_src" },
2099 .num_parents = 1,
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2102 },
2103 },
2104};
2105
2106static struct clk_branch camss_mclk1_clk = {
2107 .halt_reg = 0x33b4,
2108 .clkr = {
2109 .enable_reg = 0x33b4,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "camss_mclk1_clk",
2113 .parent_names = (const char *[]){ "mclk1_clk_src" },
2114 .num_parents = 1,
2115 .flags = CLK_SET_RATE_PARENT,
2116 .ops = &clk_branch2_ops,
2117 },
2118 },
2119};
2120
2121static struct clk_branch camss_mclk2_clk = {
2122 .halt_reg = 0x33e4,
2123 .clkr = {
2124 .enable_reg = 0x33e4,
2125 .enable_mask = BIT(0),
2126 .hw.init = &(struct clk_init_data){
2127 .name = "camss_mclk2_clk",
2128 .parent_names = (const char *[]){ "mclk2_clk_src" },
2129 .num_parents = 1,
2130 .flags = CLK_SET_RATE_PARENT,
2131 .ops = &clk_branch2_ops,
2132 },
2133 },
2134};
2135
2136static struct clk_branch camss_mclk3_clk = {
2137 .halt_reg = 0x3414,
2138 .clkr = {
2139 .enable_reg = 0x3414,
2140 .enable_mask = BIT(0),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "camss_mclk3_clk",
2143 .parent_names = (const char *[]){ "mclk3_clk_src" },
2144 .num_parents = 1,
2145 .flags = CLK_SET_RATE_PARENT,
2146 .ops = &clk_branch2_ops,
2147 },
2148 },
2149};
2150
2151static struct clk_branch camss_cci_clk = {
2152 .halt_reg = 0x3344,
2153 .clkr = {
2154 .enable_reg = 0x3344,
2155 .enable_mask = BIT(0),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "camss_cci_clk",
2158 .parent_names = (const char *[]){ "cci_clk_src" },
2159 .num_parents = 1,
2160 .flags = CLK_SET_RATE_PARENT,
2161 .ops = &clk_branch2_ops,
2162 },
2163 },
2164};
2165
2166static struct clk_branch camss_cci_ahb_clk = {
2167 .halt_reg = 0x3348,
2168 .clkr = {
2169 .enable_reg = 0x3348,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "camss_cci_ahb_clk",
2173 .parent_names = (const char *[]){ "ahb_clk_src" },
2174 .num_parents = 1,
2175 .flags = CLK_SET_RATE_PARENT,
2176 .ops = &clk_branch2_ops,
2177 },
2178 },
2179};
2180
2181static struct clk_branch camss_csi0phytimer_clk = {
2182 .halt_reg = 0x3024,
2183 .clkr = {
2184 .enable_reg = 0x3024,
2185 .enable_mask = BIT(0),
2186 .hw.init = &(struct clk_init_data){
2187 .name = "camss_csi0phytimer_clk",
2188 .parent_names = (const char *[]){ "csi0phytimer_clk_src" },
2189 .num_parents = 1,
2190 .flags = CLK_SET_RATE_PARENT,
2191 .ops = &clk_branch2_ops,
2192 },
2193 },
2194};
2195
2196static struct clk_branch camss_csi1phytimer_clk = {
2197 .halt_reg = 0x3054,
2198 .clkr = {
2199 .enable_reg = 0x3054,
2200 .enable_mask = BIT(0),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "camss_csi1phytimer_clk",
2203 .parent_names = (const char *[]){ "csi1phytimer_clk_src" },
2204 .num_parents = 1,
2205 .flags = CLK_SET_RATE_PARENT,
2206 .ops = &clk_branch2_ops,
2207 },
2208 },
2209};
2210
2211static struct clk_branch camss_csi2phytimer_clk = {
2212 .halt_reg = 0x3084,
2213 .clkr = {
2214 .enable_reg = 0x3084,
2215 .enable_mask = BIT(0),
2216 .hw.init = &(struct clk_init_data){
2217 .name = "camss_csi2phytimer_clk",
2218 .parent_names = (const char *[]){ "csi2phytimer_clk_src" },
2219 .num_parents = 1,
2220 .flags = CLK_SET_RATE_PARENT,
2221 .ops = &clk_branch2_ops,
2222 },
2223 },
2224};
2225
2226static struct clk_branch camss_csiphy0_3p_clk = {
2227 .halt_reg = 0x3234,
2228 .clkr = {
2229 .enable_reg = 0x3234,
2230 .enable_mask = BIT(0),
2231 .hw.init = &(struct clk_init_data){
2232 .name = "camss_csiphy0_3p_clk",
2233 .parent_names = (const char *[]){ "csiphy0_3p_clk_src" },
2234 .num_parents = 1,
2235 .flags = CLK_SET_RATE_PARENT,
2236 .ops = &clk_branch2_ops,
2237 },
2238 },
2239};
2240
2241static struct clk_branch camss_csiphy1_3p_clk = {
2242 .halt_reg = 0x3254,
2243 .clkr = {
2244 .enable_reg = 0x3254,
2245 .enable_mask = BIT(0),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "camss_csiphy1_3p_clk",
2248 .parent_names = (const char *[]){ "csiphy1_3p_clk_src" },
2249 .num_parents = 1,
2250 .flags = CLK_SET_RATE_PARENT,
2251 .ops = &clk_branch2_ops,
2252 },
2253 },
2254};
2255
2256static struct clk_branch camss_csiphy2_3p_clk = {
2257 .halt_reg = 0x3274,
2258 .clkr = {
2259 .enable_reg = 0x3274,
2260 .enable_mask = BIT(0),
2261 .hw.init = &(struct clk_init_data){
2262 .name = "camss_csiphy2_3p_clk",
2263 .parent_names = (const char *[]){ "csiphy2_3p_clk_src" },
2264 .num_parents = 1,
2265 .flags = CLK_SET_RATE_PARENT,
2266 .ops = &clk_branch2_ops,
2267 },
2268 },
2269};
2270
2271static struct clk_branch camss_jpeg0_clk = {
2272 .halt_reg = 0x35a8,
2273 .clkr = {
2274 .enable_reg = 0x35a8,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "camss_jpeg0_clk",
2278 .parent_names = (const char *[]){ "jpeg0_clk_src" },
2279 .num_parents = 1,
2280 .flags = CLK_SET_RATE_PARENT,
2281 .ops = &clk_branch2_ops,
2282 },
2283 },
2284};
2285
2286static struct clk_branch camss_jpeg2_clk = {
2287 .halt_reg = 0x35b0,
2288 .clkr = {
2289 .enable_reg = 0x35b0,
2290 .enable_mask = BIT(0),
2291 .hw.init = &(struct clk_init_data){
2292 .name = "camss_jpeg2_clk",
2293 .parent_names = (const char *[]){ "jpeg2_clk_src" },
2294 .num_parents = 1,
2295 .flags = CLK_SET_RATE_PARENT,
2296 .ops = &clk_branch2_ops,
2297 },
2298 },
2299};
2300
2301static struct clk_branch camss_jpeg_dma_clk = {
2302 .halt_reg = 0x35c0,
2303 .clkr = {
2304 .enable_reg = 0x35c0,
2305 .enable_mask = BIT(0),
2306 .hw.init = &(struct clk_init_data){
2307 .name = "camss_jpeg_dma_clk",
2308 .parent_names = (const char *[]){ "jpeg_dma_clk_src" },
2309 .num_parents = 1,
2310 .flags = CLK_SET_RATE_PARENT,
2311 .ops = &clk_branch2_ops,
2312 },
2313 },
2314};
2315
2316static struct clk_branch camss_jpeg_ahb_clk = {
2317 .halt_reg = 0x35b4,
2318 .clkr = {
2319 .enable_reg = 0x35b4,
2320 .enable_mask = BIT(0),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "camss_jpeg_ahb_clk",
2323 .parent_names = (const char *[]){ "ahb_clk_src" },
2324 .num_parents = 1,
2325 .flags = CLK_SET_RATE_PARENT,
2326 .ops = &clk_branch2_ops,
2327 },
2328 },
2329};
2330
2331static struct clk_branch camss_jpeg_axi_clk = {
2332 .halt_reg = 0x35b8,
2333 .clkr = {
2334 .enable_reg = 0x35b8,
2335 .enable_mask = BIT(0),
2336 .hw.init = &(struct clk_init_data){
2337 .name = "camss_jpeg_axi_clk",
2338 .parent_names = (const char *[]){ "axi_clk_src" },
2339 .num_parents = 1,
2340 .flags = CLK_SET_RATE_PARENT,
2341 .ops = &clk_branch2_ops,
2342 },
2343 },
2344};
2345
2346static struct clk_branch camss_vfe_ahb_clk = {
2347 .halt_reg = 0x36b8,
2348 .clkr = {
2349 .enable_reg = 0x36b8,
2350 .enable_mask = BIT(0),
2351 .hw.init = &(struct clk_init_data){
2352 .name = "camss_vfe_ahb_clk",
2353 .parent_names = (const char *[]){ "ahb_clk_src" },
2354 .num_parents = 1,
2355 .flags = CLK_SET_RATE_PARENT,
2356 .ops = &clk_branch2_ops,
2357 },
2358 },
2359};
2360
2361static struct clk_branch camss_vfe_axi_clk = {
2362 .halt_reg = 0x36bc,
2363 .clkr = {
2364 .enable_reg = 0x36bc,
2365 .enable_mask = BIT(0),
2366 .hw.init = &(struct clk_init_data){
2367 .name = "camss_vfe_axi_clk",
2368 .parent_names = (const char *[]){ "axi_clk_src" },
2369 .num_parents = 1,
2370 .flags = CLK_SET_RATE_PARENT,
2371 .ops = &clk_branch2_ops,
2372 },
2373 },
2374};
2375
2376static struct clk_branch camss_vfe0_clk = {
2377 .halt_reg = 0x36a8,
2378 .clkr = {
2379 .enable_reg = 0x36a8,
2380 .enable_mask = BIT(0),
2381 .hw.init = &(struct clk_init_data){
2382 .name = "camss_vfe0_clk",
2383 .parent_names = (const char *[]){ "vfe0_clk_src" },
2384 .num_parents = 1,
2385 .flags = CLK_SET_RATE_PARENT,
2386 .ops = &clk_branch2_ops,
2387 },
2388 },
2389};
2390
2391static struct clk_branch camss_vfe0_stream_clk = {
2392 .halt_reg = 0x3720,
2393 .clkr = {
2394 .enable_reg = 0x3720,
2395 .enable_mask = BIT(0),
2396 .hw.init = &(struct clk_init_data){
2397 .name = "camss_vfe0_stream_clk",
2398 .parent_names = (const char *[]){ "vfe0_clk_src" },
2399 .num_parents = 1,
2400 .flags = CLK_SET_RATE_PARENT,
2401 .ops = &clk_branch2_ops,
2402 },
2403 },
2404};
2405
2406static struct clk_branch camss_vfe0_ahb_clk = {
2407 .halt_reg = 0x3668,
2408 .clkr = {
2409 .enable_reg = 0x3668,
2410 .enable_mask = BIT(0),
2411 .hw.init = &(struct clk_init_data){
2412 .name = "camss_vfe0_ahb_clk",
2413 .parent_names = (const char *[]){ "ahb_clk_src" },
2414 .num_parents = 1,
2415 .flags = CLK_SET_RATE_PARENT,
2416 .ops = &clk_branch2_ops,
2417 },
2418 },
2419};
2420
2421static struct clk_branch camss_vfe1_clk = {
2422 .halt_reg = 0x36ac,
2423 .clkr = {
2424 .enable_reg = 0x36ac,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "camss_vfe1_clk",
2428 .parent_names = (const char *[]){ "vfe1_clk_src" },
2429 .num_parents = 1,
2430 .flags = CLK_SET_RATE_PARENT,
2431 .ops = &clk_branch2_ops,
2432 },
2433 },
2434};
2435
2436static struct clk_branch camss_vfe1_stream_clk = {
2437 .halt_reg = 0x3724,
2438 .clkr = {
2439 .enable_reg = 0x3724,
2440 .enable_mask = BIT(0),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "camss_vfe1_stream_clk",
2443 .parent_names = (const char *[]){ "vfe1_clk_src" },
2444 .num_parents = 1,
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2447 },
2448 },
2449};
2450
2451static struct clk_branch camss_vfe1_ahb_clk = {
2452 .halt_reg = 0x3678,
2453 .clkr = {
2454 .enable_reg = 0x3678,
2455 .enable_mask = BIT(0),
2456 .hw.init = &(struct clk_init_data){
2457 .name = "camss_vfe1_ahb_clk",
2458 .parent_names = (const char *[]){ "ahb_clk_src" },
2459 .num_parents = 1,
2460 .flags = CLK_SET_RATE_PARENT,
2461 .ops = &clk_branch2_ops,
2462 },
2463 },
2464};
2465
2466static struct clk_branch camss_csi_vfe0_clk = {
2467 .halt_reg = 0x3704,
2468 .clkr = {
2469 .enable_reg = 0x3704,
2470 .enable_mask = BIT(0),
2471 .hw.init = &(struct clk_init_data){
2472 .name = "camss_csi_vfe0_clk",
2473 .parent_names = (const char *[]){ "vfe0_clk_src" },
2474 .num_parents = 1,
2475 .flags = CLK_SET_RATE_PARENT,
2476 .ops = &clk_branch2_ops,
2477 },
2478 },
2479};
2480
2481static struct clk_branch camss_csi_vfe1_clk = {
2482 .halt_reg = 0x3714,
2483 .clkr = {
2484 .enable_reg = 0x3714,
2485 .enable_mask = BIT(0),
2486 .hw.init = &(struct clk_init_data){
2487 .name = "camss_csi_vfe1_clk",
2488 .parent_names = (const char *[]){ "vfe1_clk_src" },
2489 .num_parents = 1,
2490 .flags = CLK_SET_RATE_PARENT,
2491 .ops = &clk_branch2_ops,
2492 },
2493 },
2494};
2495
2496static struct clk_branch camss_cpp_vbif_ahb_clk = {
2497 .halt_reg = 0x36c8,
2498 .clkr = {
2499 .enable_reg = 0x36c8,
2500 .enable_mask = BIT(0),
2501 .hw.init = &(struct clk_init_data){
2502 .name = "camss_cpp_vbif_ahb_clk",
2503 .parent_names = (const char *[]){ "ahb_clk_src" },
2504 .num_parents = 1,
2505 .flags = CLK_SET_RATE_PARENT,
2506 .ops = &clk_branch2_ops,
2507 },
2508 },
2509};
2510
2511static struct clk_branch camss_cpp_axi_clk = {
2512 .halt_reg = 0x36c4,
2513 .clkr = {
2514 .enable_reg = 0x36c4,
2515 .enable_mask = BIT(0),
2516 .hw.init = &(struct clk_init_data){
2517 .name = "camss_cpp_axi_clk",
2518 .parent_names = (const char *[]){ "axi_clk_src" },
2519 .num_parents = 1,
2520 .flags = CLK_SET_RATE_PARENT,
2521 .ops = &clk_branch2_ops,
2522 },
2523 },
2524};
2525
2526static struct clk_branch camss_cpp_clk = {
2527 .halt_reg = 0x36b0,
2528 .clkr = {
2529 .enable_reg = 0x36b0,
2530 .enable_mask = BIT(0),
2531 .hw.init = &(struct clk_init_data){
2532 .name = "camss_cpp_clk",
2533 .parent_names = (const char *[]){ "cpp_clk_src" },
2534 .num_parents = 1,
2535 .flags = CLK_SET_RATE_PARENT,
2536 .ops = &clk_branch2_ops,
2537 },
2538 },
2539};
2540
2541static struct clk_branch camss_cpp_ahb_clk = {
2542 .halt_reg = 0x36b4,
2543 .clkr = {
2544 .enable_reg = 0x36b4,
2545 .enable_mask = BIT(0),
2546 .hw.init = &(struct clk_init_data){
2547 .name = "camss_cpp_ahb_clk",
2548 .parent_names = (const char *[]){ "ahb_clk_src" },
2549 .num_parents = 1,
2550 .flags = CLK_SET_RATE_PARENT,
2551 .ops = &clk_branch2_ops,
2552 },
2553 },
2554};
2555
2556static struct clk_branch camss_csi0_clk = {
2557 .halt_reg = 0x30b4,
2558 .clkr = {
2559 .enable_reg = 0x30b4,
2560 .enable_mask = BIT(0),
2561 .hw.init = &(struct clk_init_data){
2562 .name = "camss_csi0_clk",
2563 .parent_names = (const char *[]){ "csi0_clk_src" },
2564 .num_parents = 1,
2565 .flags = CLK_SET_RATE_PARENT,
2566 .ops = &clk_branch2_ops,
2567 },
2568 },
2569};
2570
2571static struct clk_branch camss_csi0_ahb_clk = {
2572 .halt_reg = 0x30bc,
2573 .clkr = {
2574 .enable_reg = 0x30bc,
2575 .enable_mask = BIT(0),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "camss_csi0_ahb_clk",
2578 .parent_names = (const char *[]){ "ahb_clk_src" },
2579 .num_parents = 1,
2580 .flags = CLK_SET_RATE_PARENT,
2581 .ops = &clk_branch2_ops,
2582 },
2583 },
2584};
2585
2586static struct clk_branch camss_csi0phy_clk = {
2587 .halt_reg = 0x30c4,
2588 .clkr = {
2589 .enable_reg = 0x30c4,
2590 .enable_mask = BIT(0),
2591 .hw.init = &(struct clk_init_data){
2592 .name = "camss_csi0phy_clk",
2593 .parent_names = (const char *[]){ "csi0_clk_src" },
2594 .num_parents = 1,
2595 .flags = CLK_SET_RATE_PARENT,
2596 .ops = &clk_branch2_ops,
2597 },
2598 },
2599};
2600
2601static struct clk_branch camss_csi0rdi_clk = {
2602 .halt_reg = 0x30d4,
2603 .clkr = {
2604 .enable_reg = 0x30d4,
2605 .enable_mask = BIT(0),
2606 .hw.init = &(struct clk_init_data){
2607 .name = "camss_csi0rdi_clk",
2608 .parent_names = (const char *[]){ "csi0_clk_src" },
2609 .num_parents = 1,
2610 .flags = CLK_SET_RATE_PARENT,
2611 .ops = &clk_branch2_ops,
2612 },
2613 },
2614};
2615
2616static struct clk_branch camss_csi0pix_clk = {
2617 .halt_reg = 0x30e4,
2618 .clkr = {
2619 .enable_reg = 0x30e4,
2620 .enable_mask = BIT(0),
2621 .hw.init = &(struct clk_init_data){
2622 .name = "camss_csi0pix_clk",
2623 .parent_names = (const char *[]){ "csi0_clk_src" },
2624 .num_parents = 1,
2625 .flags = CLK_SET_RATE_PARENT,
2626 .ops = &clk_branch2_ops,
2627 },
2628 },
2629};
2630
2631static struct clk_branch camss_csi1_clk = {
2632 .halt_reg = 0x3124,
2633 .clkr = {
2634 .enable_reg = 0x3124,
2635 .enable_mask = BIT(0),
2636 .hw.init = &(struct clk_init_data){
2637 .name = "camss_csi1_clk",
2638 .parent_names = (const char *[]){ "csi1_clk_src" },
2639 .num_parents = 1,
2640 .flags = CLK_SET_RATE_PARENT,
2641 .ops = &clk_branch2_ops,
2642 },
2643 },
2644};
2645
2646static struct clk_branch camss_csi1_ahb_clk = {
2647 .halt_reg = 0x3128,
2648 .clkr = {
2649 .enable_reg = 0x3128,
2650 .enable_mask = BIT(0),
2651 .hw.init = &(struct clk_init_data){
2652 .name = "camss_csi1_ahb_clk",
2653 .parent_names = (const char *[]){ "ahb_clk_src" },
2654 .num_parents = 1,
2655 .flags = CLK_SET_RATE_PARENT,
2656 .ops = &clk_branch2_ops,
2657 },
2658 },
2659};
2660
2661static struct clk_branch camss_csi1phy_clk = {
2662 .halt_reg = 0x3134,
2663 .clkr = {
2664 .enable_reg = 0x3134,
2665 .enable_mask = BIT(0),
2666 .hw.init = &(struct clk_init_data){
2667 .name = "camss_csi1phy_clk",
2668 .parent_names = (const char *[]){ "csi1_clk_src" },
2669 .num_parents = 1,
2670 .flags = CLK_SET_RATE_PARENT,
2671 .ops = &clk_branch2_ops,
2672 },
2673 },
2674};
2675
2676static struct clk_branch camss_csi1rdi_clk = {
2677 .halt_reg = 0x3144,
2678 .clkr = {
2679 .enable_reg = 0x3144,
2680 .enable_mask = BIT(0),
2681 .hw.init = &(struct clk_init_data){
2682 .name = "camss_csi1rdi_clk",
2683 .parent_names = (const char *[]){ "csi1_clk_src" },
2684 .num_parents = 1,
2685 .flags = CLK_SET_RATE_PARENT,
2686 .ops = &clk_branch2_ops,
2687 },
2688 },
2689};
2690
2691static struct clk_branch camss_csi1pix_clk = {
2692 .halt_reg = 0x3154,
2693 .clkr = {
2694 .enable_reg = 0x3154,
2695 .enable_mask = BIT(0),
2696 .hw.init = &(struct clk_init_data){
2697 .name = "camss_csi1pix_clk",
2698 .parent_names = (const char *[]){ "csi1_clk_src" },
2699 .num_parents = 1,
2700 .flags = CLK_SET_RATE_PARENT,
2701 .ops = &clk_branch2_ops,
2702 },
2703 },
2704};
2705
2706static struct clk_branch camss_csi2_clk = {
2707 .halt_reg = 0x3184,
2708 .clkr = {
2709 .enable_reg = 0x3184,
2710 .enable_mask = BIT(0),
2711 .hw.init = &(struct clk_init_data){
2712 .name = "camss_csi2_clk",
2713 .parent_names = (const char *[]){ "csi2_clk_src" },
2714 .num_parents = 1,
2715 .flags = CLK_SET_RATE_PARENT,
2716 .ops = &clk_branch2_ops,
2717 },
2718 },
2719};
2720
2721static struct clk_branch camss_csi2_ahb_clk = {
2722 .halt_reg = 0x3188,
2723 .clkr = {
2724 .enable_reg = 0x3188,
2725 .enable_mask = BIT(0),
2726 .hw.init = &(struct clk_init_data){
2727 .name = "camss_csi2_ahb_clk",
2728 .parent_names = (const char *[]){ "ahb_clk_src" },
2729 .num_parents = 1,
2730 .flags = CLK_SET_RATE_PARENT,
2731 .ops = &clk_branch2_ops,
2732 },
2733 },
2734};
2735
2736static struct clk_branch camss_csi2phy_clk = {
2737 .halt_reg = 0x3194,
2738 .clkr = {
2739 .enable_reg = 0x3194,
2740 .enable_mask = BIT(0),
2741 .hw.init = &(struct clk_init_data){
2742 .name = "camss_csi2phy_clk",
2743 .parent_names = (const char *[]){ "csi2_clk_src" },
2744 .num_parents = 1,
2745 .flags = CLK_SET_RATE_PARENT,
2746 .ops = &clk_branch2_ops,
2747 },
2748 },
2749};
2750
2751static struct clk_branch camss_csi2rdi_clk = {
2752 .halt_reg = 0x31a4,
2753 .clkr = {
2754 .enable_reg = 0x31a4,
2755 .enable_mask = BIT(0),
2756 .hw.init = &(struct clk_init_data){
2757 .name = "camss_csi2rdi_clk",
2758 .parent_names = (const char *[]){ "csi2_clk_src" },
2759 .num_parents = 1,
2760 .flags = CLK_SET_RATE_PARENT,
2761 .ops = &clk_branch2_ops,
2762 },
2763 },
2764};
2765
2766static struct clk_branch camss_csi2pix_clk = {
2767 .halt_reg = 0x31b4,
2768 .clkr = {
2769 .enable_reg = 0x31b4,
2770 .enable_mask = BIT(0),
2771 .hw.init = &(struct clk_init_data){
2772 .name = "camss_csi2pix_clk",
2773 .parent_names = (const char *[]){ "csi2_clk_src" },
2774 .num_parents = 1,
2775 .flags = CLK_SET_RATE_PARENT,
2776 .ops = &clk_branch2_ops,
2777 },
2778 },
2779};
2780
2781static struct clk_branch camss_csi3_clk = {
2782 .halt_reg = 0x31e4,
2783 .clkr = {
2784 .enable_reg = 0x31e4,
2785 .enable_mask = BIT(0),
2786 .hw.init = &(struct clk_init_data){
2787 .name = "camss_csi3_clk",
2788 .parent_names = (const char *[]){ "csi3_clk_src" },
2789 .num_parents = 1,
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2792 },
2793 },
2794};
2795
2796static struct clk_branch camss_csi3_ahb_clk = {
2797 .halt_reg = 0x31e8,
2798 .clkr = {
2799 .enable_reg = 0x31e8,
2800 .enable_mask = BIT(0),
2801 .hw.init = &(struct clk_init_data){
2802 .name = "camss_csi3_ahb_clk",
2803 .parent_names = (const char *[]){ "ahb_clk_src" },
2804 .num_parents = 1,
2805 .flags = CLK_SET_RATE_PARENT,
2806 .ops = &clk_branch2_ops,
2807 },
2808 },
2809};
2810
2811static struct clk_branch camss_csi3phy_clk = {
2812 .halt_reg = 0x31f4,
2813 .clkr = {
2814 .enable_reg = 0x31f4,
2815 .enable_mask = BIT(0),
2816 .hw.init = &(struct clk_init_data){
2817 .name = "camss_csi3phy_clk",
2818 .parent_names = (const char *[]){ "csi3_clk_src" },
2819 .num_parents = 1,
2820 .flags = CLK_SET_RATE_PARENT,
2821 .ops = &clk_branch2_ops,
2822 },
2823 },
2824};
2825
2826static struct clk_branch camss_csi3rdi_clk = {
2827 .halt_reg = 0x3204,
2828 .clkr = {
2829 .enable_reg = 0x3204,
2830 .enable_mask = BIT(0),
2831 .hw.init = &(struct clk_init_data){
2832 .name = "camss_csi3rdi_clk",
2833 .parent_names = (const char *[]){ "csi3_clk_src" },
2834 .num_parents = 1,
2835 .flags = CLK_SET_RATE_PARENT,
2836 .ops = &clk_branch2_ops,
2837 },
2838 },
2839};
2840
2841static struct clk_branch camss_csi3pix_clk = {
2842 .halt_reg = 0x3214,
2843 .clkr = {
2844 .enable_reg = 0x3214,
2845 .enable_mask = BIT(0),
2846 .hw.init = &(struct clk_init_data){
2847 .name = "camss_csi3pix_clk",
2848 .parent_names = (const char *[]){ "csi3_clk_src" },
2849 .num_parents = 1,
2850 .flags = CLK_SET_RATE_PARENT,
2851 .ops = &clk_branch2_ops,
2852 },
2853 },
2854};
2855
2856static struct clk_branch camss_ispif_ahb_clk = {
2857 .halt_reg = 0x3224,
2858 .clkr = {
2859 .enable_reg = 0x3224,
2860 .enable_mask = BIT(0),
2861 .hw.init = &(struct clk_init_data){
2862 .name = "camss_ispif_ahb_clk",
2863 .parent_names = (const char *[]){ "ahb_clk_src" },
2864 .num_parents = 1,
2865 .flags = CLK_SET_RATE_PARENT,
2866 .ops = &clk_branch2_ops,
2867 },
2868 },
2869};
2870
2871static struct clk_branch fd_core_clk = {
2872 .halt_reg = 0x3b68,
2873 .clkr = {
2874 .enable_reg = 0x3b68,
2875 .enable_mask = BIT(0),
2876 .hw.init = &(struct clk_init_data){
2877 .name = "fd_core_clk",
2878 .parent_names = (const char *[]){ "fd_core_clk_src" },
2879 .num_parents = 1,
2880 .flags = CLK_SET_RATE_PARENT,
2881 .ops = &clk_branch2_ops,
2882 },
2883 },
2884};
2885
2886static struct clk_branch fd_core_uar_clk = {
2887 .halt_reg = 0x3b6c,
2888 .clkr = {
2889 .enable_reg = 0x3b6c,
2890 .enable_mask = BIT(0),
2891 .hw.init = &(struct clk_init_data){
2892 .name = "fd_core_uar_clk",
2893 .parent_names = (const char *[]){ "fd_core_clk_src" },
2894 .num_parents = 1,
2895 .flags = CLK_SET_RATE_PARENT,
2896 .ops = &clk_branch2_ops,
2897 },
2898 },
2899};
2900
2901static struct clk_branch fd_ahb_clk = {
2902 .halt_reg = 0x3ba74,
2903 .clkr = {
2904 .enable_reg = 0x3ba74,
2905 .enable_mask = BIT(0),
2906 .hw.init = &(struct clk_init_data){
2907 .name = "fd_ahb_clk",
2908 .parent_names = (const char *[]){ "ahb_clk_src" },
2909 .num_parents = 1,
2910 .flags = CLK_SET_RATE_PARENT,
2911 .ops = &clk_branch2_ops,
2912 },
2913 },
2914};
2915
2916static struct clk_hw *mmcc_msm8996_hws[] = {
2917 &gpll0_div.hw,
2918};
2919
2920static struct clk_regmap *mmcc_msm8996_clocks[] = {
2921 [MMPLL0_EARLY] = &mmpll0_early.clkr,
2922 [MMPLL0_PLL] = &mmpll0.clkr,
2923 [MMPLL1_EARLY] = &mmpll1_early.clkr,
2924 [MMPLL1_PLL] = &mmpll1.clkr,
2925 [MMPLL2_EARLY] = &mmpll2_early.clkr,
2926 [MMPLL2_PLL] = &mmpll2.clkr,
2927 [MMPLL3_EARLY] = &mmpll3_early.clkr,
2928 [MMPLL3_PLL] = &mmpll3.clkr,
2929 [MMPLL4_EARLY] = &mmpll4_early.clkr,
2930 [MMPLL4_PLL] = &mmpll4.clkr,
2931 [MMPLL5_EARLY] = &mmpll5_early.clkr,
2932 [MMPLL5_PLL] = &mmpll5.clkr,
2933 [MMPLL8_EARLY] = &mmpll8_early.clkr,
2934 [MMPLL8_PLL] = &mmpll8.clkr,
2935 [MMPLL9_EARLY] = &mmpll9_early.clkr,
2936 [MMPLL9_PLL] = &mmpll9.clkr,
2937 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2938 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2939 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2940 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2941 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2942 [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
2943 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
2944 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2945 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2946 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2947 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2948 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2949 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2950 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2951 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2952 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2953 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2954 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2955 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2956 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2957 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2958 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2959 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2960 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2961 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2962 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2963 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2964 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2965 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2966 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2967 [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
2968 [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
2969 [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
2970 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2971 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2972 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
2973 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2974 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2975 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2976 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2977 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2978 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2979 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2980 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2981 [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
2982 [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
2983 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2984 [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
2985 [MMSS_MMAGIC_AXI_CLK] = &mmss_mmagic_axi_clk.clkr,
2986 [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
2987 [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
2988 [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
2989 [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
2990 [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
2991 [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
2992 [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
2993 [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
2994 [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
2995 [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
2996 [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
2997 [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
2998 [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
2999 [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
3000 [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
3001 [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
3002 [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
3003 [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
3004 [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
3005 [MMAGIC_BIMC_AXI_CLK] = &mmagic_bimc_axi_clk.clkr,
3006 [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
3007 [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
3008 [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
3009 [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
3010 [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
3011 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
3012 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
3013 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3014 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3015 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
3016 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
3017 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
3018 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
3019 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
3020 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
3021 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3022 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3023 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3024 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3025 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3026 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3027 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3028 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3029 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3030 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3031 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3032 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3033 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3034 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3035 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3036 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3037 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3038 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3039 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3040 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3041 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3042 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3043 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
3044 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
3045 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
3046 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
3047 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
3048 [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
3049 [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
3050 [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
3051 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
3052 [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
3053 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
3054 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
3055 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
3056 [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
3057 [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
3058 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
3059 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
3060 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
3061 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
3062 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
3063 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
3064 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3065 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3066 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
3067 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
3068 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
3069 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
3070 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3071 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3072 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3073 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3074 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3075 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3076 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3077 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3078 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3079 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3080 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3081 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3082 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3083 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3084 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3085 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3086 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3087 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3088 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3089 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3090 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3091 [FD_CORE_CLK] = &fd_core_clk.clkr,
3092 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
3093 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
3094};
3095
3096static const struct qcom_reset_map mmcc_msm8996_resets[] = {
3097 [MMAGICAHB_BCR] = { 0x5020 },
3098 [MMAGIC_CFG_BCR] = { 0x5050 },
3099 [MISC_BCR] = { 0x5010 },
3100 [BTO_BCR] = { 0x5030 },
3101 [MMAGICAXI_BCR] = { 0x5060 },
3102 [MMAGICMAXI_BCR] = { 0x5070 },
3103 [DSA_BCR] = { 0x50a0 },
3104 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3105 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3106 [SMMU_VFE_BCR] = { 0x3c00 },
3107 [SMMU_CPP_BCR] = { 0x3c10 },
3108 [SMMU_JPEG_BCR] = { 0x3c20 },
3109 [MMAGIC_MDSS_BCR] = { 0x2470 },
3110 [THROTTLE_MDSS_BCR] = { 0x2460 },
3111 [SMMU_ROT_BCR] = { 0x2440 },
3112 [SMMU_MDP_BCR] = { 0x2450 },
3113 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3114 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3115 [SMMU_VIDEO_BCR] = { 0x1170 },
3116 [MMAGIC_BIMC_BCR] = { 0x5290 },
3117 [GPU_GX_BCR] = { 0x4020 },
3118 [GPU_BCR] = { 0x4030 },
3119 [GPU_AON_BCR] = { 0x4040 },
3120 [VMEM_BCR] = { 0x1200 },
3121 [MMSS_RBCPR_BCR] = { 0x4080 },
3122 [VIDEO_BCR] = { 0x1020 },
3123 [MDSS_BCR] = { 0x2300 },
3124 [CAMSS_TOP_BCR] = { 0x3480 },
3125 [CAMSS_AHB_BCR] = { 0x3488 },
3126 [CAMSS_MICRO_BCR] = { 0x3490 },
3127 [CAMSS_CCI_BCR] = { 0x3340 },
3128 [CAMSS_PHY0_BCR] = { 0x3020 },
3129 [CAMSS_PHY1_BCR] = { 0x3050 },
3130 [CAMSS_PHY2_BCR] = { 0x3080 },
3131 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3132 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3133 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3134 [CAMSS_JPEG_BCR] = { 0x35a0 },
3135 [CAMSS_VFE_BCR] = { 0x36a0 },
3136 [CAMSS_VFE0_BCR] = { 0x3660 },
3137 [CAMSS_VFE1_BCR] = { 0x3670 },
3138 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3139 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3140 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3141 [CAMSS_CPP_BCR] = { 0x36d0 },
3142 [CAMSS_CSI0_BCR] = { 0x30b0 },
3143 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3144 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3145 [CAMSS_CSI1_BCR] = { 0x3120 },
3146 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3147 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3148 [CAMSS_CSI2_BCR] = { 0x3180 },
3149 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3150 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3151 [CAMSS_CSI3_BCR] = { 0x31e0 },
3152 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3153 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3154 [CAMSS_ISPIF_BCR] = { 0x3220 },
3155 [FD_BCR] = { 0x3b60 },
3156 [MMSS_SPDM_RM_BCR] = { 0x300 },
3157};
3158
3159static const struct regmap_config mmcc_msm8996_regmap_config = {
3160 .reg_bits = 32,
3161 .reg_stride = 4,
3162 .val_bits = 32,
3163 .max_register = 0xb008,
3164 .fast_io = true,
3165};
3166
3167static const struct qcom_cc_desc mmcc_msm8996_desc = {
3168 .config = &mmcc_msm8996_regmap_config,
3169 .clks = mmcc_msm8996_clocks,
3170 .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
3171 .resets = mmcc_msm8996_resets,
3172 .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
3173};
3174
3175static const struct of_device_id mmcc_msm8996_match_table[] = {
3176 { .compatible = "qcom,mmcc-msm8996" },
3177 { }
3178};
3179MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
3180
3181static int mmcc_msm8996_probe(struct platform_device *pdev)
3182{
3183 struct clk *clk;
3184 struct device *dev = &pdev->dev;
3185 int i;
3186 struct regmap *regmap;
3187
3188 regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
3189 if (IS_ERR(regmap))
3190 return PTR_ERR(regmap);
3191
3192 /* Disable the AHB DCD */
3193 regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3194 /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
3195 regmap_update_bits(regmap, 0x5054, BIT(15), 0);
3196
3197 for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) {
3198 clk = devm_clk_register(dev, mmcc_msm8996_hws[i]);
3199 if (IS_ERR(clk))
3200 return PTR_ERR(clk);
3201 }
3202
3203 return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
3204}
3205
3206static struct platform_driver mmcc_msm8996_driver = {
3207 .probe = mmcc_msm8996_probe,
3208 .driver = {
3209 .name = "mmcc-msm8996",
3210 .of_match_table = mmcc_msm8996_match_table,
3211 },
3212};
3213module_platform_driver(mmcc_msm8996_driver);
3214
3215MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
3216MODULE_LICENSE("GPL v2");
3217MODULE_ALIAS("platform:mmcc-msm8996");
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6c8183..80b9a379beb4 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,8 @@ obj-y += clk-inverter.o
10obj-y += clk-mmc-phase.o 10obj-y += clk-mmc-phase.o
11obj-$(CONFIG_RESET_CONTROLLER) += softrst.o 11obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
12 12
13obj-y += clk-rk3036.o
13obj-y += clk-rk3188.o 14obj-y += clk-rk3188.o
15obj-y += clk-rk3228.o
14obj-y += clk-rk3288.o 16obj-y += clk-rk3288.o
15obj-y += clk-rk3368.o 17obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 330870a6d8bf..d07374f48caf 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -242,8 +242,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
242 struct clk *clk, *cclk; 242 struct clk *clk, *cclk;
243 int ret; 243 int ret;
244 244
245 if (num_parents != 2) { 245 if (num_parents < 2) {
246 pr_err("%s: needs two parent clocks\n", __func__); 246 pr_err("%s: needs at least two parent clocks\n", __func__);
247 return ERR_PTR(-EINVAL); 247 return ERR_PTR(-EINVAL);
248 } 248 }
249 249
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 4881eb8a1576..b7e66c9dd9f2 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -2,6 +2,9 @@
2 * Copyright (c) 2014 MundoReader S.L. 2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de> 3 * Author: Heiko Stuebner <heiko@sntech.de>
4 * 4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
5 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
@@ -19,6 +22,7 @@
19#include <linux/delay.h> 22#include <linux/delay.h>
20#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
21#include <linux/regmap.h> 24#include <linux/regmap.h>
25#include <linux/clk.h>
22#include "clk.h" 26#include "clk.h"
23 27
24#define PLL_MODE_MASK 0x3 28#define PLL_MODE_MASK 0x3
@@ -108,6 +112,252 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
108} 112}
109 113
110/** 114/**
115 * PLL used in RK3036
116 */
117
118#define RK3036_PLLCON(i) (i * 0x4)
119#define RK3036_PLLCON0_FBDIV_MASK 0xfff
120#define RK3036_PLLCON0_FBDIV_SHIFT 0
121#define RK3036_PLLCON0_POSTDIV1_MASK 0x7
122#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
123#define RK3036_PLLCON1_REFDIV_MASK 0x3f
124#define RK3036_PLLCON1_REFDIV_SHIFT 0
125#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
126#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
127#define RK3036_PLLCON1_DSMPD_MASK 0x1
128#define RK3036_PLLCON1_DSMPD_SHIFT 12
129#define RK3036_PLLCON2_FRAC_MASK 0xffffff
130#define RK3036_PLLCON2_FRAC_SHIFT 0
131
132#define RK3036_PLLCON1_PWRDOWN (1 << 13)
133
134static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
135 struct rockchip_pll_rate_table *rate)
136{
137 u32 pllcon;
138
139 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
140 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
141 & RK3036_PLLCON0_FBDIV_MASK);
142 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
143 & RK3036_PLLCON0_POSTDIV1_MASK);
144
145 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
146 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
147 & RK3036_PLLCON1_REFDIV_MASK);
148 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
149 & RK3036_PLLCON1_POSTDIV2_MASK);
150 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
151 & RK3036_PLLCON1_DSMPD_MASK);
152
153 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
154 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
155 & RK3036_PLLCON2_FRAC_MASK);
156}
157
158static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
159 unsigned long prate)
160{
161 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
162 struct rockchip_pll_rate_table cur;
163 u64 rate64 = prate;
164
165 rockchip_rk3036_pll_get_params(pll, &cur);
166
167 rate64 *= cur.fbdiv;
168 do_div(rate64, cur.refdiv);
169
170 if (cur.dsmpd == 0) {
171 /* fractional mode */
172 u64 frac_rate64 = prate * cur.frac;
173
174 do_div(frac_rate64, cur.refdiv);
175 rate64 += frac_rate64 >> 24;
176 }
177
178 do_div(rate64, cur.postdiv1);
179 do_div(rate64, cur.postdiv2);
180
181 return (unsigned long)rate64;
182}
183
184static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
185 const struct rockchip_pll_rate_table *rate)
186{
187 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
188 struct clk_mux *pll_mux = &pll->pll_mux;
189 struct rockchip_pll_rate_table cur;
190 u32 pllcon;
191 int rate_change_remuxed = 0;
192 int cur_parent;
193 int ret;
194
195 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
196 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
197 rate->postdiv2, rate->dsmpd, rate->frac);
198
199 rockchip_rk3036_pll_get_params(pll, &cur);
200 cur.rate = 0;
201
202 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
203 if (cur_parent == PLL_MODE_NORM) {
204 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
205 rate_change_remuxed = 1;
206 }
207
208 /* update pll values */
209 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
210 RK3036_PLLCON0_FBDIV_SHIFT) |
211 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
212 RK3036_PLLCON0_POSTDIV1_SHIFT),
213 pll->reg_base + RK3036_PLLCON(0));
214
215 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
216 RK3036_PLLCON1_REFDIV_SHIFT) |
217 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
218 RK3036_PLLCON1_POSTDIV2_SHIFT) |
219 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
220 RK3036_PLLCON1_DSMPD_SHIFT),
221 pll->reg_base + RK3036_PLLCON(1));
222
223 /* GPLL CON2 is not HIWORD_MASK */
224 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
225 pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
226 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
227 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
228
229 /* wait for the pll to lock */
230 ret = rockchip_pll_wait_lock(pll);
231 if (ret) {
232 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
233 __func__);
234 rockchip_rk3036_pll_set_params(pll, &cur);
235 }
236
237 if (rate_change_remuxed)
238 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
239
240 return ret;
241}
242
243static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
244 unsigned long prate)
245{
246 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
247 const struct rockchip_pll_rate_table *rate;
248 unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
249 struct regmap *grf = rockchip_clk_get_grf();
250
251 if (IS_ERR(grf)) {
252 pr_debug("%s: grf regmap not available, aborting rate change\n",
253 __func__);
254 return PTR_ERR(grf);
255 }
256
257 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
258 __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
259
260 /* Get required rate settings from table */
261 rate = rockchip_get_pll_settings(pll, drate);
262 if (!rate) {
263 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
264 drate, __clk_get_name(hw->clk));
265 return -EINVAL;
266 }
267
268 return rockchip_rk3036_pll_set_params(pll, rate);
269}
270
271static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
272{
273 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
274
275 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
276 pll->reg_base + RK3036_PLLCON(1));
277
278 return 0;
279}
280
281static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
282{
283 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
284
285 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
286 RK3036_PLLCON1_PWRDOWN, 0),
287 pll->reg_base + RK3036_PLLCON(1));
288}
289
290static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
291{
292 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
293 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
294
295 return !(pllcon & RK3036_PLLCON1_PWRDOWN);
296}
297
298static void rockchip_rk3036_pll_init(struct clk_hw *hw)
299{
300 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
301 const struct rockchip_pll_rate_table *rate;
302 struct rockchip_pll_rate_table cur;
303 unsigned long drate;
304
305 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
306 return;
307
308 drate = clk_hw_get_rate(hw);
309 rate = rockchip_get_pll_settings(pll, drate);
310
311 /* when no rate setting for the current rate, rely on clk_set_rate */
312 if (!rate)
313 return;
314
315 rockchip_rk3036_pll_get_params(pll, &cur);
316
317 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
318 drate);
319 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
320 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
321 cur.dsmpd, cur.frac);
322 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
323 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
324 rate->dsmpd, rate->frac);
325
326 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
327 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
328 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
329 struct clk *parent = clk_get_parent(hw->clk);
330
331 if (!parent) {
332 pr_warn("%s: parent of %s not available\n",
333 __func__, __clk_get_name(hw->clk));
334 return;
335 }
336
337 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
338 __func__, __clk_get_name(hw->clk));
339 rockchip_rk3036_pll_set_params(pll, rate);
340 }
341}
342
343static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
344 .recalc_rate = rockchip_rk3036_pll_recalc_rate,
345 .enable = rockchip_rk3036_pll_enable,
346 .disable = rockchip_rk3036_pll_disable,
347 .is_enabled = rockchip_rk3036_pll_is_enabled,
348};
349
350static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
351 .recalc_rate = rockchip_rk3036_pll_recalc_rate,
352 .round_rate = rockchip_pll_round_rate,
353 .set_rate = rockchip_rk3036_pll_set_rate,
354 .enable = rockchip_rk3036_pll_enable,
355 .disable = rockchip_rk3036_pll_disable,
356 .is_enabled = rockchip_rk3036_pll_is_enabled,
357 .init = rockchip_rk3036_pll_init,
358};
359
360/**
111 * PLL used in RK3066, RK3188 and RK3288 361 * PLL used in RK3066, RK3188 and RK3288
112 */ 362 */
113 363
@@ -376,7 +626,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
376 pll_mux->lock = lock; 626 pll_mux->lock = lock;
377 pll_mux->hw.init = &init; 627 pll_mux->hw.init = &init;
378 628
379 if (pll_type == pll_rk3066) 629 if (pll_type == pll_rk3036 || pll_type == pll_rk3066)
380 pll_mux->flags |= CLK_MUX_HIWORD_MASK; 630 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
381 631
382 /* the actual muxing is xin24m, pll-output, xin32k */ 632 /* the actual muxing is xin24m, pll-output, xin32k */
@@ -421,6 +671,12 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
421 } 671 }
422 672
423 switch (pll_type) { 673 switch (pll_type) {
674 case pll_rk3036:
675 if (!pll->rate_table)
676 init.ops = &rockchip_rk3036_pll_clk_norate_ops;
677 else
678 init.ops = &rockchip_rk3036_pll_clk_ops;
679 break;
424 case pll_rk3066: 680 case pll_rk3066:
425 if (!pll->rate_table) 681 if (!pll->rate_table)
426 init.ops = &rockchip_rk3066_pll_clk_norate_ops; 682 init.ops = &rockchip_rk3066_pll_clk_norate_ops;
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
new file mode 100644
index 000000000000..7333b05342ff
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,478 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/syscore_ops.h>
23#include <dt-bindings/clock/rk3036-cru.h>
24#include "clk.h"
25
26#define RK3036_GRF_SOC_STATUS0 0x14c
27
28enum rk3036_plls {
29 apll, dpll, gpll,
30};
31
32static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
55 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
56 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
57 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
58 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
59 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
60 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
61 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
62 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
63 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
64 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
65 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
66 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
67 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
68 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
69 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
70 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
71 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
72 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
73 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
74 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
75 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
76 { /* sentinel */ },
77};
78
79#define RK3036_DIV_CPU_MASK 0x1f
80#define RK3036_DIV_CPU_SHIFT 8
81
82#define RK3036_DIV_PERI_MASK 0xf
83#define RK3036_DIV_PERI_SHIFT 0
84#define RK3036_DIV_ACLK_MASK 0x7
85#define RK3036_DIV_ACLK_SHIFT 4
86#define RK3036_DIV_HCLK_MASK 0x3
87#define RK3036_DIV_HCLK_SHIFT 8
88#define RK3036_DIV_PCLK_MASK 0x7
89#define RK3036_DIV_PCLK_SHIFT 12
90
91#define RK3036_CLKSEL1(_core_periph_div) \
92 { \
93 .reg = RK2928_CLKSEL_CON(1), \
94 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
95 RK3036_DIV_PERI_SHIFT) \
96 }
97
98#define RK3036_CPUCLK_RATE(_prate, _core_periph_div) \
99 { \
100 .prate = _prate, \
101 .divs = { \
102 RK3036_CLKSEL1(_core_periph_div), \
103 }, \
104 }
105
106static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
107 RK3036_CPUCLK_RATE(816000000, 4),
108 RK3036_CPUCLK_RATE(600000000, 4),
109 RK3036_CPUCLK_RATE(312000000, 4),
110};
111
112static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
113 .core_reg = RK2928_CLKSEL_CON(0),
114 .div_core_shift = 0,
115 .div_core_mask = 0x1f,
116 .mux_core_shift = 7,
117};
118
119PNAME(mux_pll_p) = { "xin24m", "xin24m" };
120
121PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
122PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
123PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
124PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
125PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
126
127PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll" "usb480m" };
128
129PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
130PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
131PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
132PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
133PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
134PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
135PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
136PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
137PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" };
138
139static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
140 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
141 RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
142 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
143 RK2928_MODE_CON, 4, 4, 0, NULL),
144 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
145 RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates),
146};
147
148#define MFLAGS CLK_MUX_HIWORD_MASK
149#define DFLAGS CLK_DIVIDER_HIWORD_MASK
150#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
151
152static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
153 /*
154 * Clock-Architecture Diagram 1
155 */
156
157 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
158 RK2928_CLKGATE_CON(0), 6, GFLAGS),
159
160 /*
161 * Clock-Architecture Diagram 2
162 */
163
164 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
165 RK2928_CLKGATE_CON(0), 2, GFLAGS),
166 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
167 RK2928_CLKGATE_CON(0), 8, GFLAGS),
168 COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
169 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
170
171 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
172 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
173 RK2928_CLKGATE_CON(0), 7, GFLAGS),
174 COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
175 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
176 RK2928_CLKGATE_CON(0), 7, GFLAGS),
177
178 GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
179 GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
180 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0,
181 RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
182 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
183 RK2928_CLKGATE_CON(0), 3, GFLAGS),
184 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
185 RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
186 RK2928_CLKGATE_CON(0), 5, GFLAGS),
187 COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
188 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
189 RK2928_CLKGATE_CON(0), 4, GFLAGS),
190
191 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
192 RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
193 RK2928_CLKGATE_CON(2), 0, GFLAGS),
194
195 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
196 RK2928_CLKGATE_CON(2), 1, GFLAGS),
197 DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
198 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
199 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
200 RK2928_CLKGATE_CON(2), 3, GFLAGS),
201 DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
202 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
203 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
204 RK2928_CLKGATE_CON(2), 2, GFLAGS),
205
206 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
207 RK2928_CLKSEL_CON(2), 4, 1, DFLAGS,
208 RK2928_CLKGATE_CON(1), 0, GFLAGS),
209 COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
210 RK2928_CLKSEL_CON(2), 5, 1, DFLAGS,
211 RK2928_CLKGATE_CON(1), 1, GFLAGS),
212 COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
213 RK2928_CLKSEL_CON(2), 6, 1, DFLAGS,
214 RK2928_CLKGATE_CON(2), 4, GFLAGS),
215 COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
216 RK2928_CLKSEL_CON(2), 7, 1, DFLAGS,
217 RK2928_CLKGATE_CON(2), 5, GFLAGS),
218
219 MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
220 RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
221 COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
222 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
223 RK2928_CLKGATE_CON(1), 8, GFLAGS),
224 COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
225 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
226 RK2928_CLKGATE_CON(1), 8, GFLAGS),
227 COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
228 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
229 RK2928_CLKGATE_CON(1), 8, GFLAGS),
230 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
231 RK2928_CLKSEL_CON(17), 0,
232 RK2928_CLKGATE_CON(1), 9, GFLAGS),
233 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
234 RK2928_CLKSEL_CON(18), 0,
235 RK2928_CLKGATE_CON(1), 11, GFLAGS),
236 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
237 RK2928_CLKSEL_CON(19), 0,
238 RK2928_CLKGATE_CON(1), 13, GFLAGS),
239 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
240 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
241 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
242 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
243 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
244 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
245
246 COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
247 RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
248 RK2928_CLKGATE_CON(3), 11, GFLAGS),
249
250 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
251 RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
252 RK2928_CLKGATE_CON(10), 6, GFLAGS),
253
254 COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
255 RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
256 RK2928_CLKGATE_CON(1), 4, GFLAGS),
257 COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
258 RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
259 RK2928_CLKGATE_CON(0), 11, GFLAGS),
260 COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
261 RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
262 RK2928_CLKGATE_CON(3), 2, GFLAGS),
263
264 COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
265 RK2928_CLKSEL_CON(12), 8, 2, DFLAGS,
266 RK2928_CLKGATE_CON(2), 11, GFLAGS),
267 DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
268 RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
269
270 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
271 RK2928_CLKSEL_CON(12), 10, 2, DFLAGS,
272 RK2928_CLKGATE_CON(2), 13, GFLAGS),
273 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
274 RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
275
276 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
277 RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS,
278 RK2928_CLKGATE_CON(2), 14, GFLAGS),
279
280 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3036_SDMMC_CON0, 1),
281 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0),
282
283 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3036_SDIO_CON0, 1),
284 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3036_SDIO_CON1, 0),
285
286 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1),
287 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0),
288
289 COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
290 RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
291 RK2928_CLKGATE_CON(0), 9, GFLAGS),
292 COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
293 RK2928_CLKSEL_CON(7), 0,
294 RK2928_CLKGATE_CON(0), 10, GFLAGS),
295 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
296 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
297 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
298 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
299 RK2928_CLKGATE_CON(0), 13, GFLAGS),
300 GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
301 RK2928_CLKGATE_CON(0), 14, GFLAGS),
302
303 COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
304 RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
305 RK2928_CLKGATE_CON(2), 10, GFLAGS),
306 COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0,
307 RK2928_CLKSEL_CON(9), 0,
308 RK2928_CLKGATE_CON(2), 12, GFLAGS),
309 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
310 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
311
312 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
313 RK2928_CLKGATE_CON(1), 5, GFLAGS),
314
315 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
316 RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
317 RK2928_CLKGATE_CON(3), 13, GFLAGS),
318
319 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
320 RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
321 RK2928_CLKGATE_CON(2), 9, GFLAGS),
322
323 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
324 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
325 RK2928_CLKGATE_CON(10), 4, GFLAGS),
326
327 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
328 RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
329 RK2928_CLKGATE_CON(10), 5, GFLAGS),
330
331 COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
332 RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
333 MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
334 RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
335
336 COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
337 RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
338 RK2928_CLKGATE_CON(2), 6, GFLAGS),
339
340 MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
341 RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
342
343 /*
344 * Clock-Architecture Diagram 3
345 */
346
347 /* aclk_cpu gates */
348 GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
349 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
350
351 /* hclk_cpu gates */
352 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
353
354 /* pclk_cpu gates */
355 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
356 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
357 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
358 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
359
360 /* aclk_vio gates */
361 GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
362 GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
363
364 GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
365 GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
366
367 /* hclk_video gates */
368 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS),
369
370 /* xin24m gates */
371 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
372 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS),
373
374 /* aclk_peri gates */
375 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
376 GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
377 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
378 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
379
380 /* hclk_peri gates */
381 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
382 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
383 GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
384 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
385 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
386 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
387 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
388 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
389 GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
390 GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
391 GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
392 GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
393
394 /* pclk_peri gates */
395 GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
396 GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS),
397 GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
398 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
399 GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
400 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
401 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
402 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
403 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
404 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
405 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
406 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
407 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
408 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
409 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
410};
411
412static const char *const rk3036_critical_clocks[] __initconst = {
413 "aclk_cpu",
414 "aclk_peri",
415 "hclk_peri",
416 "pclk_peri",
417};
418
419static void __init rk3036_clk_init(struct device_node *np)
420{
421 void __iomem *reg_base;
422 struct clk *clk;
423
424 reg_base = of_iomap(np, 0);
425 if (!reg_base) {
426 pr_err("%s: could not map cru region\n", __func__);
427 return;
428 }
429
430 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
431
432 /* xin12m is created by an cru-internal divider */
433 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
434 if (IS_ERR(clk))
435 pr_warn("%s: could not register clock xin12m: %ld\n",
436 __func__, PTR_ERR(clk));
437
438 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
439 if (IS_ERR(clk))
440 pr_warn("%s: could not register clock usb480m: %ld\n",
441 __func__, PTR_ERR(clk));
442
443 clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2);
444 if (IS_ERR(clk))
445 pr_warn("%s: could not register clock ddrphy: %ld\n",
446 __func__, PTR_ERR(clk));
447
448 clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
449 "aclk_vcodec", 0, 1, 4);
450 if (IS_ERR(clk))
451 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
452 __func__, PTR_ERR(clk));
453
454 clk = clk_register_fixed_factor(NULL, "sclk_macref_out",
455 "hclk_peri_src", 0, 1, 2);
456 if (IS_ERR(clk))
457 pr_warn("%s: could not register clock sclk_macref_out: %ld\n",
458 __func__, PTR_ERR(clk));
459
460 rockchip_clk_register_plls(rk3036_pll_clks,
461 ARRAY_SIZE(rk3036_pll_clks),
462 RK3036_GRF_SOC_STATUS0);
463 rockchip_clk_register_branches(rk3036_clk_branches,
464 ARRAY_SIZE(rk3036_clk_branches));
465 rockchip_clk_protect_critical(rk3036_critical_clocks,
466 ARRAY_SIZE(rk3036_critical_clocks));
467
468 rockchip_clk_register_armclk(ARMCLK, "armclk",
469 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
470 &rk3036_cpuclk_data, rk3036_cpuclk_rates,
471 ARRAY_SIZE(rk3036_cpuclk_rates));
472
473 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
474 ROCKCHIP_SOFTRST_HIWORD_MASK);
475
476 rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
477}
478CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index abb47608713b..c2c35d4cdda8 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -750,7 +750,7 @@ static void __init rk3188_common_clk_init(struct device_node *np)
750 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), 750 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
751 ROCKCHIP_SOFTRST_HIWORD_MASK); 751 ROCKCHIP_SOFTRST_HIWORD_MASK);
752 752
753 rockchip_register_restart_notifier(RK2928_GLB_SRST_FST); 753 rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
754} 754}
755 755
756static void __init rk3066a_clk_init(struct device_node *np) 756static void __init rk3066a_clk_init(struct device_node *np)
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
new file mode 100644
index 000000000000..981a50205339
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -0,0 +1,678 @@
1/*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 * Jeffy Chen <jeffy.chen@rock-chips.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/syscore_ops.h>
21#include <dt-bindings/clock/rk3228-cru.h>
22#include "clk.h"
23
24#define RK3228_GRF_SOC_STATUS0 0x480
25
26enum rk3228_plls {
27 apll, dpll, cpll, gpll,
28};
29
30static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
53 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
54 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
55 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
56 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
57 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
58 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
59 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
60 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
61 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
62 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
63 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
64 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
65 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
66 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
67 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
68 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
69 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
70 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
71 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
72 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
73 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
74 { /* sentinel */ },
75};
76
77#define RK3228_DIV_CPU_MASK 0x1f
78#define RK3228_DIV_CPU_SHIFT 8
79
80#define RK3228_DIV_PERI_MASK 0xf
81#define RK3228_DIV_PERI_SHIFT 0
82#define RK3228_DIV_ACLK_MASK 0x7
83#define RK3228_DIV_ACLK_SHIFT 4
84#define RK3228_DIV_HCLK_MASK 0x3
85#define RK3228_DIV_HCLK_SHIFT 8
86#define RK3228_DIV_PCLK_MASK 0x7
87#define RK3228_DIV_PCLK_SHIFT 12
88
89#define RK3228_CLKSEL1(_core_peri_div) \
90 { \
91 .reg = RK2928_CLKSEL_CON(1), \
92 .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
93 RK3228_DIV_PERI_SHIFT) \
94 }
95
96#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \
97 { \
98 .prate = _prate, \
99 .divs = { \
100 RK3228_CLKSEL1(_core_peri_div), \
101 }, \
102 }
103
104static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
105 RK3228_CPUCLK_RATE(816000000, 4),
106 RK3228_CPUCLK_RATE(600000000, 4),
107 RK3228_CPUCLK_RATE(312000000, 4),
108};
109
110static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
111 .core_reg = RK2928_CLKSEL_CON(0),
112 .div_core_shift = 0,
113 .div_core_mask = 0x1f,
114 .mux_core_shift = 6,
115};
116
117PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
118
119PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
120PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
121PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
122PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
123PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
124PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
125
126PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" };
127PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
128PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
129PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
130PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
131PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
132PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
133
134PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
135
136PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
137PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
138
139PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
140PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
141PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
142PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
143PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
144
145PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" };
146
147PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
148PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
149PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
150
151PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" };
152PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" };
153PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
154
155static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
156 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
157 RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
158 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
159 RK2928_MODE_CON, 4, 6, 0, NULL),
160 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
161 RK2928_MODE_CON, 8, 8, 0, NULL),
162 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
163 RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
164};
165
166#define MFLAGS CLK_MUX_HIWORD_MASK
167#define DFLAGS CLK_DIVIDER_HIWORD_MASK
168#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
169
170static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
171 /*
172 * Clock-Architecture Diagram 1
173 */
174
175 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
176 RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
177
178 /* PD_DDR */
179 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
180 RK2928_CLKGATE_CON(0), 2, GFLAGS),
181 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
182 RK2928_CLKGATE_CON(0), 2, GFLAGS),
183 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
184 RK2928_CLKGATE_CON(0), 2, GFLAGS),
185 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
186 RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
187 RK2928_CLKGATE_CON(7), 1, GFLAGS),
188 GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
189 RK2928_CLKGATE_CON(8), 5, GFLAGS),
190 GATE(0, "ddrphy", "ddrphy_pre", CLK_IGNORE_UNUSED,
191 RK2928_CLKGATE_CON(7), 0, GFLAGS),
192
193 /* PD_CORE */
194 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
195 RK2928_CLKGATE_CON(0), 6, GFLAGS),
196 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
197 RK2928_CLKGATE_CON(0), 6, GFLAGS),
198 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
199 RK2928_CLKGATE_CON(0), 6, GFLAGS),
200 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
201 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
202 RK2928_CLKGATE_CON(4), 1, GFLAGS),
203 COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
204 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
205 RK2928_CLKGATE_CON(4), 0, GFLAGS),
206
207 /* PD_MISC */
208 MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
209 RK2928_MISC_CON, 13, 1, MFLAGS),
210 MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
211 RK2928_MISC_CON, 14, 1, MFLAGS),
212 MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
213 RK2928_MISC_CON, 15, 1, MFLAGS),
214
215 /* PD_BUS */
216 GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
217 RK2928_CLKGATE_CON(0), 1, GFLAGS),
218 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
219 RK2928_CLKGATE_CON(0), 1, GFLAGS),
220 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
221 RK2928_CLKGATE_CON(0), 1, GFLAGS),
222 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
223 RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
224 GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0,
225 RK2928_CLKGATE_CON(6), 0, GFLAGS),
226 COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0,
227 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
228 RK2928_CLKGATE_CON(6), 1, GFLAGS),
229 COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
230 RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
231 RK2928_CLKGATE_CON(6), 2, GFLAGS),
232 GATE(0, "pclk_cpu", "pclk_bus_src", 0,
233 RK2928_CLKGATE_CON(6), 3, GFLAGS),
234 GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
235 RK2928_CLKGATE_CON(6), 4, GFLAGS),
236 GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
237 RK2928_CLKGATE_CON(6), 13, GFLAGS),
238
239 /* PD_VIDEO */
240 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
241 RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
242 RK2928_CLKGATE_CON(3), 11, GFLAGS),
243 GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0,
244 RK2928_CLKGATE_CON(4), 4, GFLAGS),
245
246 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
247 RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
248 RK2928_CLKGATE_CON(3), 2, GFLAGS),
249 GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0,
250 RK2928_CLKGATE_CON(4), 5, GFLAGS),
251
252 COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
253 RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
254 RK2928_CLKGATE_CON(3), 3, GFLAGS),
255
256 COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
257 RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
258 RK2928_CLKGATE_CON(3), 4, GFLAGS),
259
260 /* PD_VIO */
261 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
262 RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
263 RK2928_CLKGATE_CON(3), 0, GFLAGS),
264 DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0,
265 RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
266
267 COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
268 RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
269 RK2928_CLKGATE_CON(1), 4, GFLAGS),
270
271 MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
272 RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
273 COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0,
274 RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
275 RK2928_CLKGATE_CON(1), 2, GFLAGS),
276 COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0,
277 RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
278 RK2928_CLKGATE_CON(3), 6, GFLAGS),
279
280 COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
281 RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
282 RK2928_CLKGATE_CON(1), 1, GFLAGS),
283
284 COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0,
285 RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
286 RK2928_CLKGATE_CON(3), 5, GFLAGS),
287
288 GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
289 RK2928_CLKGATE_CON(3), 7, GFLAGS),
290
291 COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
292 RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
293 RK2928_CLKGATE_CON(3), 8, GFLAGS),
294
295 /* PD_PERI */
296 GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
297 RK2928_CLKGATE_CON(2), 0, GFLAGS),
298 GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
299 RK2928_CLKGATE_CON(2), 0, GFLAGS),
300 GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
301 RK2928_CLKGATE_CON(2), 0, GFLAGS),
302 COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
303 RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
304 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
305 RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
306 RK2928_CLKGATE_CON(5), 2, GFLAGS),
307 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
308 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
309 RK2928_CLKGATE_CON(5), 1, GFLAGS),
310 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
311 RK2928_CLKGATE_CON(5), 0, GFLAGS),
312
313 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
314 RK2928_CLKGATE_CON(6), 5, GFLAGS),
315 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
316 RK2928_CLKGATE_CON(6), 6, GFLAGS),
317 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
318 RK2928_CLKGATE_CON(6), 7, GFLAGS),
319 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
320 RK2928_CLKGATE_CON(6), 8, GFLAGS),
321 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
322 RK2928_CLKGATE_CON(6), 9, GFLAGS),
323 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
324 RK2928_CLKGATE_CON(6), 10, GFLAGS),
325
326 COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0,
327 RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
328 RK2928_CLKGATE_CON(2), 7, GFLAGS),
329
330 COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0,
331 RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
332 RK2928_CLKGATE_CON(2), 6, GFLAGS),
333
334 GATE(0, "sclk_hsadc", "ext_hsadc", 0,
335 RK3288_CLKGATE_CON(10), 12, GFLAGS),
336
337 COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
338 RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
339 RK2928_CLKGATE_CON(2), 15, GFLAGS),
340
341 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
342 RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
343 RK2928_CLKGATE_CON(2), 11, GFLAGS),
344
345 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
346 RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
347 RK2928_CLKGATE_CON(2), 13, GFLAGS),
348 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
349 RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
350
351 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
352 RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
353 RK2928_CLKGATE_CON(2), 14, GFLAGS),
354 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
355 RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
356
357 /*
358 * Clock-Architecture Diagram 2
359 */
360
361 GATE(0, "gpll_vop", "gpll", 0,
362 RK2928_CLKGATE_CON(3), 1, GFLAGS),
363 GATE(0, "cpll_vop", "cpll", 0,
364 RK2928_CLKGATE_CON(3), 1, GFLAGS),
365 MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
366 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
367 DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0,
368 RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
369 DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
370 RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
371 MUX(0, "dclk_vop", mux_dclk_vop_p, 0,
372 RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
373
374 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
375 RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
376 RK2928_CLKGATE_CON(0), 3, GFLAGS),
377 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
378 RK3288_CLKSEL_CON(8), 0,
379 RK3288_CLKGATE_CON(0), 4, GFLAGS),
380 COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0,
381 RK2928_CLKSEL_CON(9), 8, 2, MFLAGS,
382 RK2928_CLKGATE_CON(0), 5, GFLAGS),
383
384 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
385 RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
386 RK2928_CLKGATE_CON(0), 10, GFLAGS),
387 COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
388 RK3288_CLKSEL_CON(7), 0,
389 RK3288_CLKGATE_CON(0), 11, GFLAGS),
390 MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0,
391 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
392 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
393 RK2928_CLKGATE_CON(0), 14, GFLAGS),
394 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
395 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
396 RK2928_CLKGATE_CON(0), 13, GFLAGS),
397
398 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
399 RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
400 RK2928_CLKGATE_CON(0), 7, GFLAGS),
401 COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
402 RK3288_CLKSEL_CON(30), 0,
403 RK3288_CLKGATE_CON(0), 8, GFLAGS),
404 COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0,
405 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS,
406 RK2928_CLKGATE_CON(0), 9, GFLAGS),
407
408 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
409 RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
410 RK2928_CLKGATE_CON(2), 10, GFLAGS),
411 COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
412 RK3288_CLKSEL_CON(20), 0,
413 RK3288_CLKGATE_CON(2), 12, GFLAGS),
414 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
415 RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),
416
417 GATE(0, "jtag", "ext_jtag", 0,
418 RK2928_CLKGATE_CON(1), 3, GFLAGS),
419
420 GATE(0, "sclk_otgphy0", "xin24m", 0,
421 RK2928_CLKGATE_CON(1), 5, GFLAGS),
422 GATE(0, "sclk_otgphy1", "xin24m", 0,
423 RK2928_CLKGATE_CON(1), 6, GFLAGS),
424
425 COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
426 RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
427 RK2928_CLKGATE_CON(2), 8, GFLAGS),
428
429 GATE(0, "cpll_gpu", "cpll", 0,
430 RK2928_CLKGATE_CON(3), 13, GFLAGS),
431 GATE(0, "gpll_gpu", "gpll", 0,
432 RK2928_CLKGATE_CON(3), 13, GFLAGS),
433 GATE(0, "hdmiphy_gpu", "hdmiphy", 0,
434 RK2928_CLKGATE_CON(3), 13, GFLAGS),
435 GATE(0, "usb480m_gpu", "usb480m", 0,
436 RK2928_CLKGATE_CON(3), 13, GFLAGS),
437 COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0,
438 RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS),
439
440 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
441 RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
442 RK2928_CLKGATE_CON(2), 9, GFLAGS),
443
444 /* PD_UART */
445 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
446 RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
447 RK2928_CLKGATE_CON(1), 8, GFLAGS),
448 COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
449 RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
450 RK2928_CLKGATE_CON(1), 10, GFLAGS),
451 COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
452 0, RK2928_CLKSEL_CON(15), 12, 2,
453 MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
454 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
455 RK2928_CLKSEL_CON(17), 0,
456 RK2928_CLKGATE_CON(1), 9, GFLAGS),
457 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
458 RK2928_CLKSEL_CON(18), 0,
459 RK2928_CLKGATE_CON(1), 11, GFLAGS),
460 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
461 RK2928_CLKSEL_CON(19), 0,
462 RK2928_CLKGATE_CON(1), 13, GFLAGS),
463 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
464 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
465 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
466 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
467 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
468 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
469
470 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
471 RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
472 RK2928_CLKGATE_CON(1), 0, GFLAGS),
473
474 COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
475 RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
476 RK2928_CLKGATE_CON(1), 7, GFLAGS),
477 MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0,
478 RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
479 MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
480 RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
481 GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0,
482 RK2928_CLKGATE_CON(5), 4, GFLAGS),
483 GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0,
484 RK2928_CLKGATE_CON(5), 3, GFLAGS),
485 GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0,
486 RK2928_CLKGATE_CON(5), 5, GFLAGS),
487 GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0,
488 RK2928_CLKGATE_CON(5), 6, GFLAGS),
489 COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0,
490 RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
491 RK2928_CLKGATE_CON(5), 7, GFLAGS),
492 COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
493 RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
494 RK2928_CLKGATE_CON(2), 2, GFLAGS),
495
496 /*
497 * Clock-Architecture Diagram 3
498 */
499
500 /* PD_VOP */
501 GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
502 GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
503 GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
504 GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
505
506 GATE(0, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
507 GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
508
509 GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
510 GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
511
512 GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
513 GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
514 GATE(0, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
515 GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
516 GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
517 GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
518 GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
519 GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
520 GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
521 GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
522 GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
523
524 /* PD_PERI */
525 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
526 GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
527
528 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
529 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
530 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
531 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
532 GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
533 GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
534 GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
535 GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
536 GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
537 GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
538 GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
539 GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
540 GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
541
542 GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
543 GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
544
545 /* PD_GPU */
546 GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
547 GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
548
549 /* PD_BUS */
550 GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
551 GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
552 GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
553 GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
554
555 GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
556 GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
557 GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
558 GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
559 GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
560 GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
561 GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
562 GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
563
564 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
565 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
566 GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
567
568 GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
569 GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
570 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
571 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
572 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
573 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
574 GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
575 GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
576 GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
577 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
578 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
579 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
580 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS),
581 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS),
582 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
583 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
584 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
585 GATE(0, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
586 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
587 GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
588 GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
589 GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
590
591 GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
592 GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
593 GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
594 GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
595 GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
596
597 GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
598 GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
599 GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
600 GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
601 GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
602 GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
603 GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
604 GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
605
606 /* PD_MMC */
607 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
608 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
609
610 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
611 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
612
613 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
614 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
615};
616
617static const char *const rk3228_critical_clocks[] __initconst = {
618 "aclk_cpu",
619 "aclk_peri",
620 "hclk_peri",
621 "pclk_peri",
622};
623
624static void __init rk3228_clk_init(struct device_node *np)
625{
626 void __iomem *reg_base;
627 struct clk *clk;
628
629 reg_base = of_iomap(np, 0);
630 if (!reg_base) {
631 pr_err("%s: could not map cru region\n", __func__);
632 return;
633 }
634
635 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
636
637 /* xin12m is created by an cru-internal divider */
638 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
639 if (IS_ERR(clk))
640 pr_warn("%s: could not register clock xin12m: %ld\n",
641 __func__, PTR_ERR(clk));
642
643 clk = clk_register_fixed_factor(NULL, "ddrphy_pre", "ddrphy4x", 0, 1, 4);
644 if (IS_ERR(clk))
645 pr_warn("%s: could not register clock ddrphy_pre: %ld\n",
646 __func__, PTR_ERR(clk));
647
648 clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre",
649 "hclk_vpu_src", 0, 1, 4);
650 if (IS_ERR(clk))
651 pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n",
652 __func__, PTR_ERR(clk));
653
654 clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre",
655 "hclk_rkvdec_src", 0, 1, 4);
656 if (IS_ERR(clk))
657 pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n",
658 __func__, PTR_ERR(clk));
659
660 rockchip_clk_register_plls(rk3228_pll_clks,
661 ARRAY_SIZE(rk3228_pll_clks),
662 RK3228_GRF_SOC_STATUS0);
663 rockchip_clk_register_branches(rk3228_clk_branches,
664 ARRAY_SIZE(rk3228_clk_branches));
665 rockchip_clk_protect_critical(rk3228_critical_clocks,
666 ARRAY_SIZE(rk3228_critical_clocks));
667
668 rockchip_clk_register_armclk(ARMCLK, "armclk",
669 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
670 &rk3228_cpuclk_data, rk3228_cpuclk_rates,
671 ARRAY_SIZE(rk3228_cpuclk_rates));
672
673 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
674 ROCKCHIP_SOFTRST_HIWORD_MASK);
675
676 rockchip_register_restart_notifier(RK3228_GLB_SRST_FST, NULL);
677}
678CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 9040878e3e2b..11b40fbc4a53 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -295,7 +295,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
295 RK3288_CLKGATE_CON(0), 4, GFLAGS), 295 RK3288_CLKGATE_CON(0), 4, GFLAGS),
296 GATE(0, "c2c_host", "aclk_cpu_src", 0, 296 GATE(0, "c2c_host", "aclk_cpu_src", 0,
297 RK3288_CLKGATE_CON(13), 8, GFLAGS), 297 RK3288_CLKGATE_CON(13), 8, GFLAGS),
298 COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0, 298 COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
299 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS, 299 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
300 RK3288_CLKGATE_CON(5), 4, GFLAGS), 300 RK3288_CLKGATE_CON(5), 4, GFLAGS),
301 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, 301 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
@@ -644,10 +644,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
644 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS), 644 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
645 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS), 645 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
646 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS), 646 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
647 GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS), 647 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
648 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), 648 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
649 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), 649 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
650 GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), 650 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
651 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS), 651 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
652 652
653 /* ddrctrl [DDR Controller PHY clock] gates */ 653 /* ddrctrl [DDR Controller PHY clock] gates */
@@ -709,7 +709,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
709 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS), 709 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
710 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS), 710 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
711 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS), 711 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
712 GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), 712 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
713 713
714 /* sclk_gpu gates */ 714 /* sclk_gpu gates */
715 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS), 715 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
@@ -783,10 +783,10 @@ static const char *const rk3288_critical_clocks[] __initconst = {
783 "pclk_pd_pmu", 783 "pclk_pd_pmu",
784}; 784};
785 785
786#ifdef CONFIG_PM_SLEEP
787static void __iomem *rk3288_cru_base; 786static void __iomem *rk3288_cru_base;
788 787
789/* Some CRU registers will be reset in maskrom when the system 788/*
789 * Some CRU registers will be reset in maskrom when the system
790 * wakes up from fastboot. 790 * wakes up from fastboot.
791 * So save them before suspend, restore them after resume. 791 * So save them before suspend, restore them after resume.
792 */ 792 */
@@ -840,33 +840,27 @@ static void rk3288_clk_resume(void)
840 } 840 }
841} 841}
842 842
843static void rk3288_clk_shutdown(void)
844{
845 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
846}
847
843static struct syscore_ops rk3288_clk_syscore_ops = { 848static struct syscore_ops rk3288_clk_syscore_ops = {
844 .suspend = rk3288_clk_suspend, 849 .suspend = rk3288_clk_suspend,
845 .resume = rk3288_clk_resume, 850 .resume = rk3288_clk_resume,
846}; 851};
847 852
848static void rk3288_clk_sleep_init(void __iomem *reg_base)
849{
850 rk3288_cru_base = reg_base;
851 register_syscore_ops(&rk3288_clk_syscore_ops);
852}
853
854#else /* CONFIG_PM_SLEEP */
855static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
856#endif
857
858static void __init rk3288_clk_init(struct device_node *np) 853static void __init rk3288_clk_init(struct device_node *np)
859{ 854{
860 void __iomem *reg_base;
861 struct clk *clk; 855 struct clk *clk;
862 856
863 reg_base = of_iomap(np, 0); 857 rk3288_cru_base = of_iomap(np, 0);
864 if (!reg_base) { 858 if (!rk3288_cru_base) {
865 pr_err("%s: could not map cru region\n", __func__); 859 pr_err("%s: could not map cru region\n", __func__);
866 return; 860 return;
867 } 861 }
868 862
869 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 863 rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
870 864
871 /* xin12m is created by an cru-internal divider */ 865 /* xin12m is created by an cru-internal divider */
872 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); 866 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
@@ -907,10 +901,12 @@ static void __init rk3288_clk_init(struct device_node *np)
907 &rk3288_cpuclk_data, rk3288_cpuclk_rates, 901 &rk3288_cpuclk_data, rk3288_cpuclk_rates,
908 ARRAY_SIZE(rk3288_cpuclk_rates)); 902 ARRAY_SIZE(rk3288_cpuclk_rates));
909 903
910 rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0), 904 rockchip_register_softrst(np, 12,
905 rk3288_cru_base + RK3288_SOFTRST_CON(0),
911 ROCKCHIP_SOFTRST_HIWORD_MASK); 906 ROCKCHIP_SOFTRST_HIWORD_MASK);
912 907
913 rockchip_register_restart_notifier(RK3288_GLB_SRST_FST); 908 rockchip_register_restart_notifier(RK3288_GLB_SRST_FST,
914 rk3288_clk_sleep_init(reg_base); 909 rk3288_clk_shutdown);
910 register_syscore_ops(&rk3288_clk_syscore_ops);
915} 911}
916CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init); 912CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 7e6b783e6eee..be0ede522269 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -184,13 +184,13 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
184 184
185#define RK3368_CLKSEL0(_offs, _aclkm) \ 185#define RK3368_CLKSEL0(_offs, _aclkm) \
186 { \ 186 { \
187 .reg = RK3288_CLKSEL_CON(0 + _offs), \ 187 .reg = RK3368_CLKSEL_CON(0 + _offs), \
188 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \ 188 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
189 RK3368_DIV_ACLKM_SHIFT), \ 189 RK3368_DIV_ACLKM_SHIFT), \
190 } 190 }
191#define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \ 191#define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \
192 { \ 192 { \
193 .reg = RK3288_CLKSEL_CON(1 + _offs), \ 193 .reg = RK3368_CLKSEL_CON(1 + _offs), \
194 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \ 194 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
195 RK3368_DIV_ATCLK_SHIFT) | \ 195 RK3368_DIV_ATCLK_SHIFT) | \
196 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \ 196 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
@@ -819,6 +819,13 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
819}; 819};
820 820
821static const char *const rk3368_critical_clocks[] __initconst = { 821static const char *const rk3368_critical_clocks[] __initconst = {
822 "aclk_bus",
823 "aclk_peri",
824 /*
825 * pwm1 supplies vdd_logic on a lot of boards, is currently unhandled
826 * but needs to stay enabled there (including its parents) at all times.
827 */
828 "pclk_pwm1",
822 "pclk_pd_pmu", 829 "pclk_pd_pmu",
823}; 830};
824 831
@@ -882,6 +889,6 @@ static void __init rk3368_clk_init(struct device_node *np)
882 rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0), 889 rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
883 ROCKCHIP_SOFTRST_HIWORD_MASK); 890 ROCKCHIP_SOFTRST_HIWORD_MASK);
884 891
885 rockchip_register_restart_notifier(RK3368_GLB_SRST_FST); 892 rockchip_register_restart_notifier(RK3368_GLB_SRST_FST, NULL);
886} 893}
887CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init); 894CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index be6c7fd8315d..443d6f07acad 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -341,9 +341,13 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
341} 341}
342 342
343static unsigned int reg_restart; 343static unsigned int reg_restart;
344static void (*cb_restart)(void);
344static int rockchip_restart_notify(struct notifier_block *this, 345static int rockchip_restart_notify(struct notifier_block *this,
345 unsigned long mode, void *cmd) 346 unsigned long mode, void *cmd)
346{ 347{
348 if (cb_restart)
349 cb_restart();
350
347 writel(0xfdb9, reg_base + reg_restart); 351 writel(0xfdb9, reg_base + reg_restart);
348 return NOTIFY_DONE; 352 return NOTIFY_DONE;
349} 353}
@@ -353,11 +357,12 @@ static struct notifier_block rockchip_restart_handler = {
353 .priority = 128, 357 .priority = 128,
354}; 358};
355 359
356void __init rockchip_register_restart_notifier(unsigned int reg) 360void __init rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void))
357{ 361{
358 int ret; 362 int ret;
359 363
360 reg_restart = reg; 364 reg_restart = reg;
365 cb_restart = cb;
361 ret = register_restart_handler(&rockchip_restart_handler); 366 ret = register_restart_handler(&rockchip_restart_handler);
362 if (ret) 367 if (ret)
363 pr_err("%s: cannot register restart handler, %d\n", 368 pr_err("%s: cannot register restart handler, %d\n",
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index dc8ecb2673b7..809ef81cf63b 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -2,6 +2,9 @@
2 * Copyright (c) 2014 MundoReader S.L. 2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de> 3 * Author: Heiko Stuebner <heiko@sntech.de>
4 * 4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
5 * based on 8 * based on
6 * 9 *
7 * samsung/clk.h 10 * samsung/clk.h
@@ -30,7 +33,7 @@ struct clk;
30#define HIWORD_UPDATE(val, mask, shift) \ 33#define HIWORD_UPDATE(val, mask, shift) \
31 ((val) << (shift) | (mask) << ((shift) + 16)) 34 ((val) << (shift) | (mask) << ((shift) + 16))
32 35
33/* register positions shared by RK2928, RK3066 and RK3188 */ 36/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
34#define RK2928_PLL_CON(x) ((x) * 0x4) 37#define RK2928_PLL_CON(x) ((x) * 0x4)
35#define RK2928_MODE_CON 0x40 38#define RK2928_MODE_CON 0x40
36#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) 39#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
@@ -40,6 +43,22 @@ struct clk;
40#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 43#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
41#define RK2928_MISC_CON 0x134 44#define RK2928_MISC_CON 0x134
42 45
46#define RK3036_SDMMC_CON0 0x144
47#define RK3036_SDMMC_CON1 0x148
48#define RK3036_SDIO_CON0 0x14c
49#define RK3036_SDIO_CON1 0x150
50#define RK3036_EMMC_CON0 0x154
51#define RK3036_EMMC_CON1 0x158
52
53#define RK3228_GLB_SRST_FST 0x1f0
54#define RK3228_GLB_SRST_SND 0x1f4
55#define RK3228_SDMMC_CON0 0x1c0
56#define RK3228_SDMMC_CON1 0x1c4
57#define RK3228_SDIO_CON0 0x1c8
58#define RK3228_SDIO_CON1 0x1cc
59#define RK3228_EMMC_CON0 0x1d8
60#define RK3228_EMMC_CON1 0x1dc
61
43#define RK3288_PLL_CON(x) RK2928_PLL_CON(x) 62#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
44#define RK3288_MODE_CON 0x50 63#define RK3288_MODE_CON 0x50
45#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 64#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
@@ -74,9 +93,22 @@ struct clk;
74#define RK3368_EMMC_CON1 0x41c 93#define RK3368_EMMC_CON1 0x41c
75 94
76enum rockchip_pll_type { 95enum rockchip_pll_type {
96 pll_rk3036,
77 pll_rk3066, 97 pll_rk3066,
78}; 98};
79 99
100#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
101 _postdiv2, _dsmpd, _frac) \
102{ \
103 .rate = _rate##U, \
104 .fbdiv = _fbdiv, \
105 .postdiv1 = _postdiv1, \
106 .refdiv = _refdiv, \
107 .postdiv2 = _postdiv2, \
108 .dsmpd = _dsmpd, \
109 .frac = _frac, \
110}
111
80#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ 112#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
81{ \ 113{ \
82 .rate = _rate##U, \ 114 .rate = _rate##U, \
@@ -101,6 +133,13 @@ struct rockchip_pll_rate_table {
101 unsigned int nf; 133 unsigned int nf;
102 unsigned int no; 134 unsigned int no;
103 unsigned int nb; 135 unsigned int nb;
136 /* for RK3036 */
137 unsigned int fbdiv;
138 unsigned int postdiv1;
139 unsigned int refdiv;
140 unsigned int postdiv2;
141 unsigned int dsmpd;
142 unsigned int frac;
104}; 143};
105 144
106/** 145/**
@@ -464,7 +503,7 @@ void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
464 const struct rockchip_cpuclk_rate_table *rates, 503 const struct rockchip_cpuclk_rate_table *rates,
465 int nrates); 504 int nrates);
466void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); 505void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
467void rockchip_register_restart_notifier(unsigned int reg); 506void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));
468 507
469#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) 508#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
470 509
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 97c71c885e4f..7e2579b30326 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -1,13 +1,13 @@
1obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o 1obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o 2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o clk-mstp.o
3obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o 3obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-mstp.o clk-div6.o
4obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o 4obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-mstp.o clk-div6.o
5obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o 5obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o clk-mstp.o
6obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o 6obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o clk-mstp.o
7obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o 7obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
8obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o 8obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
9obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o 9obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
10obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o 10obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
11obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o 11obj-$(CONFIG_ARCH_R8A7795) += renesas-cpg-mssr.o \
12obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o 12 r8a7795-cpg-mssr.o clk-div6.o
13obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o 13obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o
diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c
index b4c8d6746f68..999994769450 100644
--- a/drivers/clk/shmobile/clk-div6.c
+++ b/drivers/clk/shmobile/clk-div6.c
@@ -18,6 +18,8 @@
18#include <linux/of_address.h> 18#include <linux/of_address.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20 20
21#include "clk-div6.h"
22
21#define CPG_DIV6_CKSTP BIT(8) 23#define CPG_DIV6_CKSTP BIT(8)
22#define CPG_DIV6_DIV(d) ((d) & 0x3f) 24#define CPG_DIV6_DIV(d) ((d) & 0x3f)
23#define CPG_DIV6_DIV_MASK 0x3f 25#define CPG_DIV6_DIV_MASK 0x3f
@@ -172,67 +174,44 @@ static const struct clk_ops cpg_div6_clock_ops = {
172 .set_rate = cpg_div6_clock_set_rate, 174 .set_rate = cpg_div6_clock_set_rate,
173}; 175};
174 176
175static void __init cpg_div6_clock_init(struct device_node *np) 177
178/**
179 * cpg_div6_register - Register a DIV6 clock
180 * @name: Name of the DIV6 clock
181 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
182 * @parent_names: Array containing the names of the parent clocks
183 * @reg: Mapped register used to control the DIV6 clock
184 */
185struct clk * __init cpg_div6_register(const char *name,
186 unsigned int num_parents,
187 const char **parent_names,
188 void __iomem *reg)
176{ 189{
177 unsigned int num_parents, valid_parents; 190 unsigned int valid_parents;
178 const char **parent_names;
179 struct clk_init_data init; 191 struct clk_init_data init;
180 struct div6_clock *clock; 192 struct div6_clock *clock;
181 const char *name;
182 struct clk *clk; 193 struct clk *clk;
183 unsigned int i; 194 unsigned int i;
184 int ret;
185 195
186 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 196 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
187 if (!clock) 197 if (!clock)
188 return; 198 return ERR_PTR(-ENOMEM);
189 199
190 num_parents = of_clk_get_parent_count(np); 200 clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
191 if (num_parents < 1) { 201 GFP_KERNEL);
192 pr_err("%s: no parent found for %s DIV6 clock\n", 202 if (!clock->parents) {
193 __func__, np->name); 203 clk = ERR_PTR(-ENOMEM);
194 return; 204 goto free_clock;
195 } 205 }
196 206
197 clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents), 207 clock->reg = reg;
198 GFP_KERNEL);
199 parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
200 GFP_KERNEL);
201 if (!parent_names)
202 return;
203 208
204 /* Remap the clock register and read the divisor. Disabling the 209 /*
205 * clock overwrites the divisor, so we need to cache its value for the 210 * Read the divisor. Disabling the clock overwrites the divisor, so we
206 * enable operation. 211 * need to cache its value for the enable operation.
207 */ 212 */
208 clock->reg = of_iomap(np, 0);
209 if (clock->reg == NULL) {
210 pr_err("%s: failed to map %s DIV6 clock register\n",
211 __func__, np->name);
212 goto error;
213 }
214
215 clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; 213 clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
216 214
217 /* Parse the DT properties. */
218 ret = of_property_read_string(np, "clock-output-names", &name);
219 if (ret < 0) {
220 pr_err("%s: failed to get %s DIV6 clock output name\n",
221 __func__, np->name);
222 goto error;
223 }
224
225
226 for (i = 0, valid_parents = 0; i < num_parents; i++) {
227 const char *name = of_clk_get_parent_name(np, i);
228
229 if (name) {
230 parent_names[valid_parents] = name;
231 clock->parents[valid_parents] = i;
232 valid_parents++;
233 }
234 }
235
236 switch (num_parents) { 215 switch (num_parents) {
237 case 1: 216 case 1:
238 /* fixed parent clock */ 217 /* fixed parent clock */
@@ -250,8 +229,18 @@ static void __init cpg_div6_clock_init(struct device_node *np)
250 break; 229 break;
251 default: 230 default:
252 pr_err("%s: invalid number of parents for DIV6 clock %s\n", 231 pr_err("%s: invalid number of parents for DIV6 clock %s\n",
253 __func__, np->name); 232 __func__, name);
254 goto error; 233 clk = ERR_PTR(-EINVAL);
234 goto free_parents;
235 }
236
237 /* Filter out invalid parents */
238 for (i = 0, valid_parents = 0; i < num_parents; i++) {
239 if (parent_names[i]) {
240 parent_names[valid_parents] = parent_names[i];
241 clock->parents[valid_parents] = i;
242 valid_parents++;
243 }
255 } 244 }
256 245
257 /* Register the clock. */ 246 /* Register the clock. */
@@ -264,6 +253,53 @@ static void __init cpg_div6_clock_init(struct device_node *np)
264 clock->hw.init = &init; 253 clock->hw.init = &init;
265 254
266 clk = clk_register(NULL, &clock->hw); 255 clk = clk_register(NULL, &clock->hw);
256 if (IS_ERR(clk))
257 goto free_parents;
258
259 return clk;
260
261free_parents:
262 kfree(clock->parents);
263free_clock:
264 kfree(clock);
265 return clk;
266}
267
268static void __init cpg_div6_clock_init(struct device_node *np)
269{
270 unsigned int num_parents;
271 const char **parent_names;
272 const char *clk_name = np->name;
273 void __iomem *reg;
274 struct clk *clk;
275 unsigned int i;
276
277 num_parents = of_clk_get_parent_count(np);
278 if (num_parents < 1) {
279 pr_err("%s: no parent found for %s DIV6 clock\n",
280 __func__, np->name);
281 return;
282 }
283
284 parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
285 GFP_KERNEL);
286 if (!parent_names)
287 return;
288
289 reg = of_iomap(np, 0);
290 if (reg == NULL) {
291 pr_err("%s: failed to map %s DIV6 clock register\n",
292 __func__, np->name);
293 goto error;
294 }
295
296 /* Parse the DT properties. */
297 of_property_read_string(np, "clock-output-names", &clk_name);
298
299 for (i = 0; i < num_parents; i++)
300 parent_names[i] = of_clk_get_parent_name(np, i);
301
302 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg);
267 if (IS_ERR(clk)) { 303 if (IS_ERR(clk)) {
268 pr_err("%s: failed to register %s DIV6 clock (%ld)\n", 304 pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
269 __func__, np->name, PTR_ERR(clk)); 305 __func__, np->name, PTR_ERR(clk));
@@ -276,9 +312,8 @@ static void __init cpg_div6_clock_init(struct device_node *np)
276 return; 312 return;
277 313
278error: 314error:
279 if (clock->reg) 315 if (reg)
280 iounmap(clock->reg); 316 iounmap(reg);
281 kfree(parent_names); 317 kfree(parent_names);
282 kfree(clock);
283} 318}
284CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init); 319CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
diff --git a/drivers/clk/shmobile/clk-div6.h b/drivers/clk/shmobile/clk-div6.h
new file mode 100644
index 000000000000..9a85a95188da
--- /dev/null
+++ b/drivers/clk/shmobile/clk-div6.h
@@ -0,0 +1,7 @@
1#ifndef __SHMOBILE_CLK_DIV6_H__
2#define __SHMOBILE_CLK_DIV6_H__
3
4struct clk *cpg_div6_register(const char *name, unsigned int num_parents,
5 const char **parent_names, void __iomem *reg);
6
7#endif
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index 745496f7ee9c..841977240305 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -115,7 +115,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
115 * 115 *
116 * Using experimental measurements, it seems that no more than 116 * Using experimental measurements, it seems that no more than
117 * ~10 iterations are needed, independently of the CPU rate. 117 * ~10 iterations are needed, independently of the CPU rate.
118 * Since this value might be dependant of external xtal rate, pll1 118 * Since this value might be dependent on external xtal rate, pll1
119 * rate or even the other emulation clocks rate, use 1000 as a 119 * rate or even the other emulation clocks rate, use 1000 as a
120 * "super" safe value. 120 * "super" safe value.
121 */ 121 */
@@ -262,7 +262,7 @@ static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
262 * 1 1 0 30 / 2 x172/2 x208/2 x106 262 * 1 1 0 30 / 2 x172/2 x208/2 x106
263 * 1 1 1 30 / 2 x172/2 x208/2 x88 263 * 1 1 1 30 / 2 x172/2 x208/2 x88
264 * 264 *
265 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2) 265 * *1 : Table 7.6 indicates VCO output (PLLx = VCO/2)
266 */ 266 */
267#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ 267#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
268 (((md) & BIT(13)) >> 12) | \ 268 (((md) & BIT(13)) >> 12) | \
diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c
new file mode 100644
index 000000000000..57c413635d1a
--- /dev/null
+++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c
@@ -0,0 +1,382 @@
1/*
2 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2015 Glider bvba
5 *
6 * Based on clk-rcar-gen3.c
7 *
8 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */
14
15#include <linux/bug.h>
16#include <linux/clk-provider.h>
17#include <linux/device.h>
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/of.h>
23
24#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
25
26#include "renesas-cpg-mssr.h"
27
28
29enum clk_ids {
30 /* Core Clock Outputs exported to DT */
31 LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
32
33 /* External Input Clocks */
34 CLK_EXTAL,
35 CLK_EXTALR,
36
37 /* Internal Core Clocks */
38 CLK_MAIN,
39 CLK_PLL0,
40 CLK_PLL1,
41 CLK_PLL2,
42 CLK_PLL3,
43 CLK_PLL4,
44 CLK_PLL1_DIV2,
45 CLK_PLL1_DIV4,
46 CLK_S0,
47 CLK_S1,
48 CLK_S2,
49 CLK_S3,
50 CLK_SDSRC,
51 CLK_SSPSRC,
52
53 /* Module Clocks */
54 MOD_CLK_BASE
55};
56
57enum r8a7795_clk_types {
58 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
59 CLK_TYPE_GEN3_PLL0,
60 CLK_TYPE_GEN3_PLL1,
61 CLK_TYPE_GEN3_PLL2,
62 CLK_TYPE_GEN3_PLL3,
63 CLK_TYPE_GEN3_PLL4,
64};
65
66static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
67 /* External Clock Inputs */
68 DEF_INPUT("extal", CLK_EXTAL),
69 DEF_INPUT("extalr", CLK_EXTALR),
70
71 /* Internal Core Clocks */
72 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
73 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
74 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
75 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
76 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
77 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
78
79 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
80 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
81 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
82 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
83 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
84 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
85
86 /* Core Clock Outputs */
87 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
88 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
89 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
90 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
91 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
92 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
93 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
94 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
95 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
96 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
97 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
98 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
99 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
100 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
101 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
102 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
103 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
104
105 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
106 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
107};
108
109static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
110 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
111 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
112 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
113 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
114 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
115 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
116 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
117 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
118 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
119 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
120 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
121 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1),
122 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
123 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
124 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
125 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
126 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
127 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
128 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
129 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
130 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
131 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
132 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
133 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
134 DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
135 DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
136 DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1),
137 DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1),
138 DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1),
139 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1),
140 DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1),
141 DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1),
142 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
143 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
144 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
145 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
146 DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
147 DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
148 DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
149 DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
150 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
151 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
152 DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
153 DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
154 DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
155 DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
156 DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
157 DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
158 DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
159 DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
160 DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
161 DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
162 DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
163 DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
164 DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
165 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
166 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
167 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
168 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
169 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
170 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
171 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
172 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
173 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
174 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
175 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
176 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
177 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
178 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
179 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
180 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
181 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
182 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
183 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
184 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
185 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
186 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
187 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
188 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
189 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
190 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
191 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
192 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
193 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
194};
195
196static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
197 MOD_CLK_ID(408), /* INTC-AP (GIC) */
198};
199
200
201#define CPG_PLL0CR 0x00d8
202#define CPG_PLL2CR 0x002c
203#define CPG_PLL4CR 0x01f4
204
205/*
206 * CPG Clock Data
207 */
208
209/*
210 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
211 * 14 13 19 17 (MHz)
212 *-------------------------------------------------------------------
213 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
214 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
215 * 0 0 1 0 Prohibited setting
216 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
217 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
218 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
219 * 0 1 1 0 Prohibited setting
220 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
221 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
222 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
223 * 1 0 1 0 Prohibited setting
224 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
225 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
226 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
227 * 1 1 1 0 Prohibited setting
228 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
229 */
230#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
231 (((md) & BIT(13)) >> 11) | \
232 (((md) & BIT(19)) >> 18) | \
233 (((md) & BIT(17)) >> 17))
234
235struct cpg_pll_config {
236 unsigned int extal_div;
237 unsigned int pll1_mult;
238 unsigned int pll3_mult;
239};
240
241static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
242 /* EXTAL div PLL1 mult PLL3 mult */
243 { 1, 192, 192, },
244 { 1, 192, 128, },
245 { 0, /* Prohibited setting */ },
246 { 1, 192, 192, },
247 { 1, 160, 160, },
248 { 1, 160, 106, },
249 { 0, /* Prohibited setting */ },
250 { 1, 160, 160, },
251 { 1, 128, 128, },
252 { 1, 128, 84, },
253 { 0, /* Prohibited setting */ },
254 { 1, 128, 128, },
255 { 2, 192, 192, },
256 { 2, 192, 128, },
257 { 0, /* Prohibited setting */ },
258 { 2, 192, 192, },
259};
260
261static const struct cpg_pll_config *cpg_pll_config __initdata;
262
263static
264struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
265 const struct cpg_core_clk *core,
266 const struct cpg_mssr_info *info,
267 struct clk **clks,
268 void __iomem *base)
269{
270 const struct clk *parent;
271 unsigned int mult = 1;
272 unsigned int div = 1;
273 u32 value;
274
275 parent = clks[core->parent];
276 if (IS_ERR(parent))
277 return ERR_CAST(parent);
278
279 switch (core->type) {
280 case CLK_TYPE_GEN3_MAIN:
281 div = cpg_pll_config->extal_div;
282 break;
283
284 case CLK_TYPE_GEN3_PLL0:
285 /*
286 * PLL0 is a configurable multiplier clock. Register it as a
287 * fixed factor clock for now as there's no generic multiplier
288 * clock implementation and we currently have no need to change
289 * the multiplier value.
290 */
291 value = readl(base + CPG_PLL0CR);
292 mult = (((value >> 24) & 0x7f) + 1) * 2;
293 break;
294
295 case CLK_TYPE_GEN3_PLL1:
296 mult = cpg_pll_config->pll1_mult;
297 break;
298
299 case CLK_TYPE_GEN3_PLL2:
300 /*
301 * PLL2 is a configurable multiplier clock. Register it as a
302 * fixed factor clock for now as there's no generic multiplier
303 * clock implementation and we currently have no need to change
304 * the multiplier value.
305 */
306 value = readl(base + CPG_PLL2CR);
307 mult = (((value >> 24) & 0x7f) + 1) * 2;
308 break;
309
310 case CLK_TYPE_GEN3_PLL3:
311 mult = cpg_pll_config->pll3_mult;
312 break;
313
314 case CLK_TYPE_GEN3_PLL4:
315 /*
316 * PLL4 is a configurable multiplier clock. Register it as a
317 * fixed factor clock for now as there's no generic multiplier
318 * clock implementation and we currently have no need to change
319 * the multiplier value.
320 */
321 value = readl(base + CPG_PLL4CR);
322 mult = (((value >> 24) & 0x7f) + 1) * 2;
323 break;
324
325 default:
326 return ERR_PTR(-EINVAL);
327 }
328
329 return clk_register_fixed_factor(NULL, core->name,
330 __clk_get_name(parent), 0, mult, div);
331}
332
333/*
334 * Reset register definitions.
335 */
336#define MODEMR 0xe6160060
337
338static u32 rcar_gen3_read_mode_pins(void)
339{
340 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
341 u32 mode;
342
343 BUG_ON(!modemr);
344 mode = ioread32(modemr);
345 iounmap(modemr);
346
347 return mode;
348}
349
350static int __init r8a7795_cpg_mssr_init(struct device *dev)
351{
352 u32 cpg_mode = rcar_gen3_read_mode_pins();
353
354 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
355 if (!cpg_pll_config->extal_div) {
356 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
357 return -EINVAL;
358 }
359
360 return 0;
361}
362
363const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
364 /* Core Clocks */
365 .core_clks = r8a7795_core_clks,
366 .num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
367 .last_dt_core_clk = LAST_DT_CORE_CLK,
368 .num_total_core_clks = MOD_CLK_BASE,
369
370 /* Module Clocks */
371 .mod_clks = r8a7795_mod_clks,
372 .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
373 .num_hw_mod_clks = 12 * 32,
374
375 /* Critical Module Clocks */
376 .crit_mod_clks = r8a7795_crit_mod_clks,
377 .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
378
379 /* Callbacks */
380 .init = r8a7795_cpg_mssr_init,
381 .cpg_clk_register = r8a7795_cpg_clk_register,
382};
diff --git a/drivers/clk/shmobile/renesas-cpg-mssr.c b/drivers/clk/shmobile/renesas-cpg-mssr.c
new file mode 100644
index 000000000000..9a4d888164bb
--- /dev/null
+++ b/drivers/clk/shmobile/renesas-cpg-mssr.c
@@ -0,0 +1,596 @@
1/*
2 * Renesas Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2015 Glider bvba
5 *
6 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
7 *
8 * Copyright (C) 2013 Ideas On Board SPRL
9 * Copyright (C) 2015 Renesas Electronics Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 */
15
16#include <linux/clk.h>
17#include <linux/clk-provider.h>
18#include <linux/device.h>
19#include <linux/init.h>
20#include <linux/mod_devicetable.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/platform_device.h>
25#include <linux/pm_clock.h>
26#include <linux/pm_domain.h>
27#include <linux/slab.h>
28
29#include <dt-bindings/clock/renesas-cpg-mssr.h>
30
31#include "renesas-cpg-mssr.h"
32#include "clk-div6.h"
33
34#ifdef DEBUG
35#define WARN_DEBUG(x) do { } while (0)
36#else
37#define WARN_DEBUG(x) WARN_ON(x)
38#endif
39
40
41/*
42 * Module Standby and Software Reset register offets.
43 *
44 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
45 * R-Car Gen 2, and R-Car Gen 3.
46 * These are NOT valid for R-Car Gen1 and RZ/A1!
47 */
48
49/*
50 * Module Stop Status Register offsets
51 */
52
53static const u16 mstpsr[] = {
54 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
55 0x9A0, 0x9A4, 0x9A8, 0x9AC,
56};
57
58#define MSTPSR(i) mstpsr[i]
59
60
61/*
62 * System Module Stop Control Register offsets
63 */
64
65static const u16 smstpcr[] = {
66 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
67 0x990, 0x994, 0x998, 0x99C,
68};
69
70#define SMSTPCR(i) smstpcr[i]
71
72
73/*
74 * Software Reset Register offsets
75 */
76
77static const u16 srcr[] = {
78 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
79 0x920, 0x924, 0x928, 0x92C,
80};
81
82#define SRCR(i) srcr[i]
83
84
85/* Realtime Module Stop Control Register offsets */
86#define RMSTPCR(i) (smstpcr[i] - 0x20)
87
88/* Modem Module Stop Control Register offsets (r8a73a4) */
89#define MMSTPCR(i) (smstpcr[i] + 0x20)
90
91/* Software Reset Clearing Register offsets */
92#define SRSTCLR(i) (0x940 + (i) * 4)
93
94
95/**
96 * Clock Pulse Generator / Module Standby and Software Reset Private Data
97 *
98 * @dev: CPG/MSSR device
99 * @base: CPG/MSSR register block base address
100 * @mstp_lock: protects writes to SMSTPCR
101 * @clks: Array containing all Core and Module Clocks
102 * @num_core_clks: Number of Core Clocks in clks[]
103 * @num_mod_clks: Number of Module Clocks in clks[]
104 * @last_dt_core_clk: ID of the last Core Clock exported to DT
105 */
106struct cpg_mssr_priv {
107 struct device *dev;
108 void __iomem *base;
109 spinlock_t mstp_lock;
110
111 struct clk **clks;
112 unsigned int num_core_clks;
113 unsigned int num_mod_clks;
114 unsigned int last_dt_core_clk;
115};
116
117
118/**
119 * struct mstp_clock - MSTP gating clock
120 * @hw: handle between common and hardware-specific interfaces
121 * @index: MSTP clock number
122 * @priv: CPG/MSSR private data
123 */
124struct mstp_clock {
125 struct clk_hw hw;
126 u32 index;
127 struct cpg_mssr_priv *priv;
128};
129
130#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
131
132static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
133{
134 struct mstp_clock *clock = to_mstp_clock(hw);
135 struct cpg_mssr_priv *priv = clock->priv;
136 unsigned int reg = clock->index / 32;
137 unsigned int bit = clock->index % 32;
138 struct device *dev = priv->dev;
139 u32 bitmask = BIT(bit);
140 unsigned long flags;
141 unsigned int i;
142 u32 value;
143
144 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
145 enable ? "ON" : "OFF");
146 spin_lock_irqsave(&priv->mstp_lock, flags);
147
148 value = clk_readl(priv->base + SMSTPCR(reg));
149 if (enable)
150 value &= ~bitmask;
151 else
152 value |= bitmask;
153 clk_writel(value, priv->base + SMSTPCR(reg));
154
155 spin_unlock_irqrestore(&priv->mstp_lock, flags);
156
157 if (!enable)
158 return 0;
159
160 for (i = 1000; i > 0; --i) {
161 if (!(clk_readl(priv->base + MSTPSR(reg)) &
162 bitmask))
163 break;
164 cpu_relax();
165 }
166
167 if (!i) {
168 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
169 priv->base + SMSTPCR(reg), bit);
170 return -ETIMEDOUT;
171 }
172
173 return 0;
174}
175
176static int cpg_mstp_clock_enable(struct clk_hw *hw)
177{
178 return cpg_mstp_clock_endisable(hw, true);
179}
180
181static void cpg_mstp_clock_disable(struct clk_hw *hw)
182{
183 cpg_mstp_clock_endisable(hw, false);
184}
185
186static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
187{
188 struct mstp_clock *clock = to_mstp_clock(hw);
189 struct cpg_mssr_priv *priv = clock->priv;
190 u32 value;
191
192 value = clk_readl(priv->base + MSTPSR(clock->index / 32));
193
194 return !(value & BIT(clock->index % 32));
195}
196
197static const struct clk_ops cpg_mstp_clock_ops = {
198 .enable = cpg_mstp_clock_enable,
199 .disable = cpg_mstp_clock_disable,
200 .is_enabled = cpg_mstp_clock_is_enabled,
201};
202
203static
204struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
205 void *data)
206{
207 unsigned int clkidx = clkspec->args[1];
208 struct cpg_mssr_priv *priv = data;
209 struct device *dev = priv->dev;
210 unsigned int idx;
211 const char *type;
212 struct clk *clk;
213
214 switch (clkspec->args[0]) {
215 case CPG_CORE:
216 type = "core";
217 if (clkidx > priv->last_dt_core_clk) {
218 dev_err(dev, "Invalid %s clock index %u\n", type,
219 clkidx);
220 return ERR_PTR(-EINVAL);
221 }
222 clk = priv->clks[clkidx];
223 break;
224
225 case CPG_MOD:
226 type = "module";
227 idx = MOD_CLK_PACK(clkidx);
228 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
229 dev_err(dev, "Invalid %s clock index %u\n", type,
230 clkidx);
231 return ERR_PTR(-EINVAL);
232 }
233 clk = priv->clks[priv->num_core_clks + idx];
234 break;
235
236 default:
237 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
238 return ERR_PTR(-EINVAL);
239 }
240
241 if (IS_ERR(clk))
242 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
243 PTR_ERR(clk));
244 else
245 dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n",
246 clkspec->args[0], clkspec->args[1], clk, clk);
247 return clk;
248}
249
250static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
251 const struct cpg_mssr_info *info,
252 struct cpg_mssr_priv *priv)
253{
254 struct clk *clk = NULL, *parent;
255 struct device *dev = priv->dev;
256 unsigned int id = core->id;
257 const char *parent_name;
258
259 WARN_DEBUG(id >= priv->num_core_clks);
260 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
261
262 switch (core->type) {
263 case CLK_TYPE_IN:
264 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
265 break;
266
267 case CLK_TYPE_FF:
268 case CLK_TYPE_DIV6P1:
269 WARN_DEBUG(core->parent >= priv->num_core_clks);
270 parent = priv->clks[core->parent];
271 if (IS_ERR(parent)) {
272 clk = parent;
273 goto fail;
274 }
275
276 parent_name = __clk_get_name(parent);
277 if (core->type == CLK_TYPE_FF) {
278 clk = clk_register_fixed_factor(NULL, core->name,
279 parent_name, 0,
280 core->mult, core->div);
281 } else {
282 clk = cpg_div6_register(core->name, 1, &parent_name,
283 priv->base + core->offset);
284 }
285 break;
286
287 default:
288 if (info->cpg_clk_register)
289 clk = info->cpg_clk_register(dev, core, info,
290 priv->clks, priv->base);
291 else
292 dev_err(dev, "%s has unsupported core clock type %u\n",
293 core->name, core->type);
294 break;
295 }
296
297 if (IS_ERR_OR_NULL(clk))
298 goto fail;
299
300 dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk);
301 priv->clks[id] = clk;
302 return;
303
304fail:
305 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core,",
306 core->name, PTR_ERR(clk));
307}
308
309static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
310 const struct cpg_mssr_info *info,
311 struct cpg_mssr_priv *priv)
312{
313 struct mstp_clock *clock = NULL;
314 struct device *dev = priv->dev;
315 unsigned int id = mod->id;
316 struct clk_init_data init;
317 struct clk *parent, *clk;
318 const char *parent_name;
319 unsigned int i;
320
321 WARN_DEBUG(id < priv->num_core_clks);
322 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
323 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
324 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
325
326 parent = priv->clks[mod->parent];
327 if (IS_ERR(parent)) {
328 clk = parent;
329 goto fail;
330 }
331
332 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
333 if (!clock) {
334 clk = ERR_PTR(-ENOMEM);
335 goto fail;
336 }
337
338 init.name = mod->name;
339 init.ops = &cpg_mstp_clock_ops;
340 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
341 for (i = 0; i < info->num_crit_mod_clks; i++)
342 if (id == info->crit_mod_clks[i]) {
343#ifdef CLK_ENABLE_HAND_OFF
344 dev_dbg(dev, "MSTP %s setting CLK_ENABLE_HAND_OFF\n",
345 mod->name);
346 init.flags |= CLK_ENABLE_HAND_OFF;
347 break;
348#else
349 dev_dbg(dev, "Ignoring MSTP %s to prevent disabling\n",
350 mod->name);
351 return;
352#endif
353 }
354
355 parent_name = __clk_get_name(parent);
356 init.parent_names = &parent_name;
357 init.num_parents = 1;
358
359 clock->index = id - priv->num_core_clks;
360 clock->priv = priv;
361 clock->hw.init = &init;
362
363 clk = clk_register(NULL, &clock->hw);
364 if (IS_ERR(clk))
365 goto fail;
366
367 dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk);
368 priv->clks[id] = clk;
369 return;
370
371fail:
372 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module,",
373 mod->name, PTR_ERR(clk));
374 kfree(clock);
375}
376
377
378#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
379struct cpg_mssr_clk_domain {
380 struct generic_pm_domain genpd;
381 struct device_node *np;
382 unsigned int num_core_pm_clks;
383 unsigned int core_pm_clks[0];
384};
385
386static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
387 struct cpg_mssr_clk_domain *pd)
388{
389 unsigned int i;
390
391 if (clkspec->np != pd->np || clkspec->args_count != 2)
392 return false;
393
394 switch (clkspec->args[0]) {
395 case CPG_CORE:
396 for (i = 0; i < pd->num_core_pm_clks; i++)
397 if (clkspec->args[1] == pd->core_pm_clks[i])
398 return true;
399 return false;
400
401 case CPG_MOD:
402 return true;
403
404 default:
405 return false;
406 }
407}
408
409static int cpg_mssr_attach_dev(struct generic_pm_domain *genpd,
410 struct device *dev)
411{
412 struct cpg_mssr_clk_domain *pd =
413 container_of(genpd, struct cpg_mssr_clk_domain, genpd);
414 struct device_node *np = dev->of_node;
415 struct of_phandle_args clkspec;
416 struct clk *clk;
417 int i = 0;
418 int error;
419
420 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
421 &clkspec)) {
422 if (cpg_mssr_is_pm_clk(&clkspec, pd))
423 goto found;
424
425 of_node_put(clkspec.np);
426 i++;
427 }
428
429 return 0;
430
431found:
432 clk = of_clk_get_from_provider(&clkspec);
433 of_node_put(clkspec.np);
434
435 if (IS_ERR(clk))
436 return PTR_ERR(clk);
437
438 error = pm_clk_create(dev);
439 if (error) {
440 dev_err(dev, "pm_clk_create failed %d\n", error);
441 goto fail_put;
442 }
443
444 error = pm_clk_add_clk(dev, clk);
445 if (error) {
446 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
447 goto fail_destroy;
448 }
449
450 return 0;
451
452fail_destroy:
453 pm_clk_destroy(dev);
454fail_put:
455 clk_put(clk);
456 return error;
457}
458
459static void cpg_mssr_detach_dev(struct generic_pm_domain *genpd,
460 struct device *dev)
461{
462 if (!list_empty(&dev->power.subsys_data->clock_list))
463 pm_clk_destroy(dev);
464}
465
466static int __init cpg_mssr_add_clk_domain(struct device *dev,
467 const unsigned int *core_pm_clks,
468 unsigned int num_core_pm_clks)
469{
470 struct device_node *np = dev->of_node;
471 struct generic_pm_domain *genpd;
472 struct cpg_mssr_clk_domain *pd;
473 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
474
475 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
476 if (!pd)
477 return -ENOMEM;
478
479 pd->np = np;
480 pd->num_core_pm_clks = num_core_pm_clks;
481 memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
482
483 genpd = &pd->genpd;
484 genpd->name = np->name;
485 genpd->flags = GENPD_FLAG_PM_CLK;
486 pm_genpd_init(genpd, &simple_qos_governor, false);
487 genpd->attach_dev = cpg_mssr_attach_dev;
488 genpd->detach_dev = cpg_mssr_detach_dev;
489
490 of_genpd_add_provider_simple(np, genpd);
491 return 0;
492}
493#else
494static inline int cpg_mssr_add_clk_domain(struct device *dev,
495 const unsigned int *core_pm_clks,
496 unsigned int num_core_pm_clks)
497{
498 return 0;
499}
500#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
501
502
503static const struct of_device_id cpg_mssr_match[] = {
504#ifdef CONFIG_ARCH_R8A7795
505 {
506 .compatible = "renesas,r8a7795-cpg-mssr",
507 .data = &r8a7795_cpg_mssr_info,
508 },
509#endif
510 { /* sentinel */ }
511};
512
513static void cpg_mssr_del_clk_provider(void *data)
514{
515 of_clk_del_provider(data);
516}
517
518static int __init cpg_mssr_probe(struct platform_device *pdev)
519{
520 struct device *dev = &pdev->dev;
521 struct device_node *np = dev->of_node;
522 const struct cpg_mssr_info *info;
523 struct cpg_mssr_priv *priv;
524 unsigned int nclks, i;
525 struct resource *res;
526 struct clk **clks;
527 int error;
528
529 info = of_match_node(cpg_mssr_match, np)->data;
530 if (info->init) {
531 error = info->init(dev);
532 if (error)
533 return error;
534 }
535
536 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
537 if (!priv)
538 return -ENOMEM;
539
540 priv->dev = dev;
541 spin_lock_init(&priv->mstp_lock);
542
543 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
544 priv->base = devm_ioremap_resource(dev, res);
545 if (IS_ERR(priv->base))
546 return PTR_ERR(priv->base);
547
548 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
549 clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
550 if (!clks)
551 return -ENOMEM;
552
553 priv->clks = clks;
554 priv->num_core_clks = info->num_total_core_clks;
555 priv->num_mod_clks = info->num_hw_mod_clks;
556 priv->last_dt_core_clk = info->last_dt_core_clk;
557
558 for (i = 0; i < nclks; i++)
559 clks[i] = ERR_PTR(-ENOENT);
560
561 for (i = 0; i < info->num_core_clks; i++)
562 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
563
564 for (i = 0; i < info->num_mod_clks; i++)
565 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
566
567 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
568 if (error)
569 return error;
570
571 devm_add_action(dev, cpg_mssr_del_clk_provider, np);
572
573 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
574 info->num_core_pm_clks);
575 if (error)
576 return error;
577
578 return 0;
579}
580
581static struct platform_driver cpg_mssr_driver = {
582 .driver = {
583 .name = "renesas-cpg-mssr",
584 .of_match_table = cpg_mssr_match,
585 },
586};
587
588static int __init cpg_mssr_init(void)
589{
590 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
591}
592
593subsys_initcall(cpg_mssr_init);
594
595MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
596MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/shmobile/renesas-cpg-mssr.h b/drivers/clk/shmobile/renesas-cpg-mssr.h
new file mode 100644
index 000000000000..e09f03cbf086
--- /dev/null
+++ b/drivers/clk/shmobile/renesas-cpg-mssr.h
@@ -0,0 +1,132 @@
1/*
2 * Renesas Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2015 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#ifndef __CLK_RENESAS_CPG_MSSR_H__
12#define __CLK_RENESAS_CPG_MSSR_H__
13
14 /*
15 * Definitions of CPG Core Clocks
16 *
17 * These include:
18 * - Clock outputs exported to DT
19 * - External input clocks
20 * - Internal CPG clocks
21 */
22
23struct cpg_core_clk {
24 /* Common */
25 const char *name;
26 unsigned int id;
27 unsigned int type;
28 /* Depending on type */
29 unsigned int parent; /* Core Clocks only */
30 unsigned int div;
31 unsigned int mult;
32 unsigned int offset;
33};
34
35enum clk_types {
36 /* Generic */
37 CLK_TYPE_IN, /* External Clock Input */
38 CLK_TYPE_FF, /* Fixed Factor Clock */
39 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
40
41 /* Custom definitions start here */
42 CLK_TYPE_CUSTOM,
43};
44
45#define DEF_TYPE(_name, _id, _type...) \
46 { .name = _name, .id = _id, .type = _type }
47#define DEF_BASE(_name, _id, _type, _parent...) \
48 DEF_TYPE(_name, _id, _type, .parent = _parent)
49
50#define DEF_INPUT(_name, _id) \
51 DEF_TYPE(_name, _id, CLK_TYPE_IN)
52#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
53 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
54#define DEF_DIV6P1(_name, _id, _parent, _offset) \
55 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
56
57
58 /*
59 * Definitions of Module Clocks
60 */
61
62struct mssr_mod_clk {
63 const char *name;
64 unsigned int id;
65 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
66};
67
68/* Convert from sparse base-100 to packed index space */
69#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
70
71#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
72
73#define DEF_MOD(_name, _mod, _parent...) \
74 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
75
76
77struct device_node;
78
79 /**
80 * SoC-specific CPG/MSSR Description
81 *
82 * @core_clks: Array of Core Clock definitions
83 * @num_core_clks: Number of entries in core_clks[]
84 * @last_dt_core_clk: ID of the last Core Clock exported to DT
85 * @num_total_core_clks: Total number of Core Clocks (exported + internal)
86 *
87 * @mod_clks: Array of Module Clock definitions
88 * @num_mod_clks: Number of entries in mod_clks[]
89 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
90 *
91 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
92 * should not be disabled without a knowledgeable driver
93 * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
94 *
95 * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
96 * Management, in addition to Module Clocks
97 * @num_core_pm_clks: Number of entries in core_pm_clks[]
98 *
99 * @init: Optional callback to perform SoC-specific initialization
100 * @cpg_clk_register: Optional callback to handle special Core Clock types
101 */
102
103struct cpg_mssr_info {
104 /* Core Clocks */
105 const struct cpg_core_clk *core_clks;
106 unsigned int num_core_clks;
107 unsigned int last_dt_core_clk;
108 unsigned int num_total_core_clks;
109
110 /* Module Clocks */
111 const struct mssr_mod_clk *mod_clks;
112 unsigned int num_mod_clks;
113 unsigned int num_hw_mod_clks;
114
115 /* Critical Module Clocks that should not be disabled */
116 const unsigned int *crit_mod_clks;
117 unsigned int num_crit_mod_clks;
118
119 /* Core Clocks suitable for PM, in addition to the Module Clocks */
120 const unsigned int *core_pm_clks;
121 unsigned int num_core_pm_clks;
122
123 /* Callbacks */
124 int (*init)(struct device *dev);
125 struct clk *(*cpg_clk_register)(struct device *dev,
126 const struct cpg_core_clk *core,
127 const struct cpg_mssr_info *info,
128 struct clk **clks, void __iomem *base);
129};
130
131extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
132#endif
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 576cd0354d48..ccb324d97160 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -549,19 +549,20 @@ static int clk_fs660c32_vco_get_params(unsigned long input,
549 return 0; 549 return 0;
550} 550}
551 551
552static long quadfs_pll_fs660c32_round_rate(struct clk_hw *hw, unsigned long rate 552static long quadfs_pll_fs660c32_round_rate(struct clk_hw *hw,
553 , unsigned long *prate) 553 unsigned long rate,
554 unsigned long *prate)
554{ 555{
555 struct stm_fs params; 556 struct stm_fs params;
556 557
557 if (!clk_fs660c32_vco_get_params(*prate, rate, &params)) 558 if (clk_fs660c32_vco_get_params(*prate, rate, &params))
558 clk_fs660c32_vco_get_rate(*prate, &params, &rate); 559 return rate;
559 560
560 pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n", 561 clk_fs660c32_vco_get_rate(*prate, &params, &rate);
562
563 pr_debug("%s: %s new rate %ld [ndiv=%u]\n",
561 __func__, clk_hw_get_name(hw), 564 __func__, clk_hw_get_name(hw),
562 rate, (unsigned int)params.sdiv, 565 rate, (unsigned int)params.ndiv);
563 (unsigned int)params.mdiv,
564 (unsigned int)params.pe, (unsigned int)params.nsdiv);
565 566
566 return rate; 567 return rate;
567} 568}
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index f3eab6e79027..b336a8c11e2a 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -323,7 +323,7 @@ static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
323 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE); 323 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
324} 324}
325 325
326static struct clk_hw_omap_ops omap2_apll_hwops = { 326static const struct clk_hw_omap_ops omap2_apll_hwops = {
327 .allow_idle = &omap2_apll_allow_idle, 327 .allow_idle = &omap2_apll_allow_idle,
328 .deny_idle = &omap2_apll_deny_idle, 328 .deny_idle = &omap2_apll_deny_idle,
329}; 329};
diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c
index f4dec00fb684..1c300388782b 100644
--- a/drivers/clk/ti/dpll3xxx.c
+++ b/drivers/clk/ti/dpll3xxx.c
@@ -305,8 +305,9 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
305static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) 305static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
306{ 306{
307 struct dpll_data *dd = clk->dpll_data; 307 struct dpll_data *dd = clk->dpll_data;
308 u8 dco, sd_div; 308 u8 dco, sd_div, ai = 0;
309 u32 v; 309 u32 v;
310 bool errata_i810;
310 311
311 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ 312 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
312 _omap3_noncore_dpll_bypass(clk); 313 _omap3_noncore_dpll_bypass(clk);
@@ -350,6 +351,25 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
350 v |= sd_div << __ffs(dd->sddiv_mask); 351 v |= sd_div << __ffs(dd->sddiv_mask);
351 } 352 }
352 353
354 /*
355 * Errata i810 - DPLL controller can get stuck while transitioning
356 * to a power saving state. Software must ensure the DPLL can not
357 * transition to a low power state while changing M/N values.
358 * Easiest way to accomplish this is to prevent DPLL autoidle
359 * before doing the M/N re-program.
360 */
361 errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810;
362
363 if (errata_i810) {
364 ai = omap3_dpll_autoidle_read(clk);
365 if (ai) {
366 omap3_dpll_deny_idle(clk);
367
368 /* OCP barrier */
369 omap3_dpll_autoidle_read(clk);
370 }
371 }
372
353 ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); 373 ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg);
354 374
355 /* Set 4X multiplier and low-power mode */ 375 /* Set 4X multiplier and low-power mode */
@@ -379,6 +399,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
379 399
380 _omap3_noncore_dpll_lock(clk); 400 _omap3_noncore_dpll_lock(clk);
381 401
402 if (errata_i810 && ai)
403 omap3_dpll_allow_idle(clk);
404
382 return 0; 405 return 0;
383} 406}
384 407
diff --git a/drivers/clk/versatile/clk-sp810.c b/drivers/clk/versatile/clk-sp810.c
index a1cdef6b0f90..e78755e0ef78 100644
--- a/drivers/clk/versatile/clk-sp810.c
+++ b/drivers/clk/versatile/clk-sp810.c
@@ -95,13 +95,12 @@ static void __init clk_sp810_of_setup(struct device_node *node)
95 int i; 95 int i;
96 bool deprecated; 96 bool deprecated;
97 97
98 if (!sp810) { 98 if (!sp810)
99 pr_err("Failed to allocate memory for SP810!\n");
100 return; 99 return;
101 }
102 100
103 if (of_clk_parent_fill(node, parent_names, num) != num) { 101 if (of_clk_parent_fill(node, parent_names, num) != num) {
104 pr_warn("Failed to obtain parent clocks for SP810!\n"); 102 pr_warn("Failed to obtain parent clocks for SP810!\n");
103 kfree(sp810);
105 return; 104 return;
106 } 105 }
107 106
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index a4a7a9ce3457..edca8985c50e 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -447,5 +447,6 @@
447#define IMX7D_SEMA4_HS_ROOT_CLK 434 447#define IMX7D_SEMA4_HS_ROOT_CLK 434
448#define IMX7D_PLL_DRAM_TEST_DIV 435 448#define IMX7D_PLL_DRAM_TEST_DIV 435
449#define IMX7D_ADC_ROOT_CLK 436 449#define IMX7D_ADC_ROOT_CLK 436
450#define IMX7D_CLK_END 437 450#define IMX7D_CLK_ARM 437
451#define IMX7D_CLK_END 438
451#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ 452#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
new file mode 100644
index 000000000000..888e75ce8fec
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -0,0 +1,339 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
15#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
16
17#define GPLL0_EARLY 0
18#define GPLL0 1
19#define GPLL1_EARLY 2
20#define GPLL1 3
21#define GPLL2_EARLY 4
22#define GPLL2 5
23#define GPLL3_EARLY 6
24#define GPLL3 7
25#define GPLL4_EARLY 8
26#define GPLL4 9
27#define SYSTEM_NOC_CLK_SRC 10
28#define CONFIG_NOC_CLK_SRC 11
29#define PERIPH_NOC_CLK_SRC 12
30#define MMSS_BIMC_GFX_CLK_SRC 13
31#define USB30_MASTER_CLK_SRC 14
32#define USB30_MOCK_UTMI_CLK_SRC 15
33#define USB3_PHY_AUX_CLK_SRC 16
34#define USB20_MASTER_CLK_SRC 17
35#define USB20_MOCK_UTMI_CLK_SRC 18
36#define SDCC1_APPS_CLK_SRC 19
37#define SDCC1_ICE_CORE_CLK_SRC 20
38#define SDCC2_APPS_CLK_SRC 21
39#define SDCC3_APPS_CLK_SRC 22
40#define SDCC4_APPS_CLK_SRC 23
41#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24
42#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25
43#define BLSP1_UART1_APPS_CLK_SRC 26
44#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27
45#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28
46#define BLSP1_UART2_APPS_CLK_SRC 29
47#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30
48#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
49#define BLSP1_UART3_APPS_CLK_SRC 32
50#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33
51#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34
52#define BLSP1_UART4_APPS_CLK_SRC 35
53#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
54#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37
55#define BLSP1_UART5_APPS_CLK_SRC 38
56#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39
57#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40
58#define BLSP1_UART6_APPS_CLK_SRC 41
59#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42
60#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43
61#define BLSP2_UART1_APPS_CLK_SRC 44
62#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45
63#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46
64#define BLSP2_UART2_APPS_CLK_SRC 47
65#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48
66#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
67#define BLSP2_UART3_APPS_CLK_SRC 50
68#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51
69#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52
70#define BLSP2_UART4_APPS_CLK_SRC 53
71#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
72#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55
73#define BLSP2_UART5_APPS_CLK_SRC 56
74#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57
75#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58
76#define BLSP2_UART6_APPS_CLK_SRC 59
77#define PDM2_CLK_SRC 60
78#define TSIF_REF_CLK_SRC 61
79#define CE1_CLK_SRC 62
80#define GCC_SLEEP_CLK_SRC 63
81#define BIMC_CLK_SRC 64
82#define HMSS_AHB_CLK_SRC 65
83#define BIMC_HMSS_AXI_CLK_SRC 66
84#define HMSS_RBCPR_CLK_SRC 67
85#define HMSS_GPLL0_CLK_SRC 68
86#define GP1_CLK_SRC 69
87#define GP2_CLK_SRC 70
88#define GP3_CLK_SRC 71
89#define PCIE_AUX_CLK_SRC 72
90#define UFS_AXI_CLK_SRC 73
91#define UFS_ICE_CORE_CLK_SRC 74
92#define QSPI_SER_CLK_SRC 75
93#define GCC_SYS_NOC_AXI_CLK 76
94#define GCC_SYS_NOC_HMSS_AHB_CLK 77
95#define GCC_SNOC_CNOC_AHB_CLK 78
96#define GCC_SNOC_PNOC_AHB_CLK 79
97#define GCC_SYS_NOC_AT_CLK 80
98#define GCC_SYS_NOC_USB3_AXI_CLK 81
99#define GCC_SYS_NOC_UFS_AXI_CLK 82
100#define GCC_CFG_NOC_AHB_CLK 83
101#define GCC_PERIPH_NOC_AHB_CLK 84
102#define GCC_PERIPH_NOC_USB20_AHB_CLK 85
103#define GCC_TIC_CLK 86
104#define GCC_IMEM_AXI_CLK 87
105#define GCC_MMSS_SYS_NOC_AXI_CLK 88
106#define GCC_MMSS_NOC_CFG_AHB_CLK 89
107#define GCC_MMSS_BIMC_GFX_CLK 90
108#define GCC_USB30_MASTER_CLK 91
109#define GCC_USB30_SLEEP_CLK 92
110#define GCC_USB30_MOCK_UTMI_CLK 93
111#define GCC_USB3_PHY_AUX_CLK 94
112#define GCC_USB3_PHY_PIPE_CLK 95
113#define GCC_USB20_MASTER_CLK 96
114#define GCC_USB20_SLEEP_CLK 97
115#define GCC_USB20_MOCK_UTMI_CLK 98
116#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
117#define GCC_SDCC1_APPS_CLK 100
118#define GCC_SDCC1_AHB_CLK 101
119#define GCC_SDCC1_ICE_CORE_CLK 102
120#define GCC_SDCC2_APPS_CLK 103
121#define GCC_SDCC2_AHB_CLK 104
122#define GCC_SDCC3_APPS_CLK 105
123#define GCC_SDCC3_AHB_CLK 106
124#define GCC_SDCC4_APPS_CLK 107
125#define GCC_SDCC4_AHB_CLK 108
126#define GCC_BLSP1_AHB_CLK 109
127#define GCC_BLSP1_SLEEP_CLK 110
128#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111
129#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112
130#define GCC_BLSP1_UART1_APPS_CLK 113
131#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114
132#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115
133#define GCC_BLSP1_UART2_APPS_CLK 116
134#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117
135#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118
136#define GCC_BLSP1_UART3_APPS_CLK 119
137#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120
138#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121
139#define GCC_BLSP1_UART4_APPS_CLK 122
140#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123
141#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124
142#define GCC_BLSP1_UART5_APPS_CLK 125
143#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126
144#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127
145#define GCC_BLSP1_UART6_APPS_CLK 128
146#define GCC_BLSP2_AHB_CLK 129
147#define GCC_BLSP2_SLEEP_CLK 130
148#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131
149#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132
150#define GCC_BLSP2_UART1_APPS_CLK 133
151#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134
152#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135
153#define GCC_BLSP2_UART2_APPS_CLK 136
154#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137
155#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138
156#define GCC_BLSP2_UART3_APPS_CLK 139
157#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140
158#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141
159#define GCC_BLSP2_UART4_APPS_CLK 142
160#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143
161#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144
162#define GCC_BLSP2_UART5_APPS_CLK 145
163#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146
164#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147
165#define GCC_BLSP2_UART6_APPS_CLK 148
166#define GCC_PDM_AHB_CLK 149
167#define GCC_PDM_XO4_CLK 150
168#define GCC_PDM2_CLK 151
169#define GCC_PRNG_AHB_CLK 152
170#define GCC_TSIF_AHB_CLK 153
171#define GCC_TSIF_REF_CLK 154
172#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155
173#define GCC_TCSR_AHB_CLK 156
174#define GCC_BOOT_ROM_AHB_CLK 157
175#define GCC_MSG_RAM_AHB_CLK 158
176#define GCC_TLMM_AHB_CLK 159
177#define GCC_TLMM_CLK 160
178#define GCC_MPM_AHB_CLK 161
179#define GCC_SPMI_SER_CLK 162
180#define GCC_SPMI_CNOC_AHB_CLK 163
181#define GCC_CE1_CLK 164
182#define GCC_CE1_AXI_CLK 165
183#define GCC_CE1_AHB_CLK 166
184#define GCC_BIMC_HMSS_AXI_CLK 167
185#define GCC_BIMC_GFX_CLK 168
186#define GCC_HMSS_AHB_CLK 169
187#define GCC_HMSS_SLV_AXI_CLK 170
188#define GCC_HMSS_MSTR_AXI_CLK 171
189#define GCC_HMSS_RBCPR_CLK 172
190#define GCC_GP1_CLK 173
191#define GCC_GP2_CLK 174
192#define GCC_GP3_CLK 175
193#define GCC_PCIE_0_SLV_AXI_CLK 176
194#define GCC_PCIE_0_MSTR_AXI_CLK 177
195#define GCC_PCIE_0_CFG_AHB_CLK 178
196#define GCC_PCIE_0_AUX_CLK 179
197#define GCC_PCIE_0_PIPE_CLK 180
198#define GCC_PCIE_1_SLV_AXI_CLK 181
199#define GCC_PCIE_1_MSTR_AXI_CLK 182
200#define GCC_PCIE_1_CFG_AHB_CLK 183
201#define GCC_PCIE_1_AUX_CLK 184
202#define GCC_PCIE_1_PIPE_CLK 185
203#define GCC_PCIE_2_SLV_AXI_CLK 186
204#define GCC_PCIE_2_MSTR_AXI_CLK 187
205#define GCC_PCIE_2_CFG_AHB_CLK 188
206#define GCC_PCIE_2_AUX_CLK 189
207#define GCC_PCIE_2_PIPE_CLK 190
208#define GCC_PCIE_PHY_CFG_AHB_CLK 191
209#define GCC_PCIE_PHY_AUX_CLK 192
210#define GCC_UFS_AXI_CLK 193
211#define GCC_UFS_AHB_CLK 194
212#define GCC_UFS_TX_CFG_CLK 195
213#define GCC_UFS_RX_CFG_CLK 196
214#define GCC_UFS_TX_SYMBOL_0_CLK 197
215#define GCC_UFS_RX_SYMBOL_0_CLK 198
216#define GCC_UFS_RX_SYMBOL_1_CLK 199
217#define GCC_UFS_UNIPRO_CORE_CLK 200
218#define GCC_UFS_ICE_CORE_CLK 201
219#define GCC_UFS_SYS_CLK_CORE_CLK 202
220#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203
221#define GCC_AGGRE0_SNOC_AXI_CLK 204
222#define GCC_AGGRE0_CNOC_AHB_CLK 205
223#define GCC_SMMU_AGGRE0_AXI_CLK 206
224#define GCC_SMMU_AGGRE0_AHB_CLK 207
225#define GCC_AGGRE1_PNOC_AHB_CLK 208
226#define GCC_AGGRE2_UFS_AXI_CLK 209
227#define GCC_AGGRE2_USB3_AXI_CLK 210
228#define GCC_QSPI_AHB_CLK 211
229#define GCC_QSPI_SER_CLK 212
230#define GCC_USB3_CLKREF_CLK 213
231#define GCC_HDMI_CLKREF_CLK 214
232#define GCC_UFS_CLKREF_CLK 215
233#define GCC_PCIE_CLKREF_CLK 216
234#define GCC_RX2_USB2_CLKREF_CLK 217
235#define GCC_RX1_USB2_CLKREF_CLK 218
236
237#define GCC_SYSTEM_NOC_BCR 0
238#define GCC_CONFIG_NOC_BCR 1
239#define GCC_PERIPH_NOC_BCR 2
240#define GCC_IMEM_BCR 3
241#define GCC_MMSS_BCR 4
242#define GCC_PIMEM_BCR 5
243#define GCC_QDSS_BCR 6
244#define GCC_USB_30_BCR 7
245#define GCC_USB_20_BCR 8
246#define GCC_QUSB2PHY_PRIM_BCR 9
247#define GCC_QUSB2PHY_SEC_BCR 10
248#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11
249#define GCC_SDCC1_BCR 12
250#define GCC_SDCC2_BCR 13
251#define GCC_SDCC3_BCR 14
252#define GCC_SDCC4_BCR 15
253#define GCC_BLSP1_BCR 16
254#define GCC_BLSP1_QUP1_BCR 17
255#define GCC_BLSP1_UART1_BCR 18
256#define GCC_BLSP1_QUP2_BCR 19
257#define GCC_BLSP1_UART2_BCR 20
258#define GCC_BLSP1_QUP3_BCR 21
259#define GCC_BLSP1_UART3_BCR 22
260#define GCC_BLSP1_QUP4_BCR 23
261#define GCC_BLSP1_UART4_BCR 24
262#define GCC_BLSP1_QUP5_BCR 25
263#define GCC_BLSP1_UART5_BCR 26
264#define GCC_BLSP1_QUP6_BCR 27
265#define GCC_BLSP1_UART6_BCR 28
266#define GCC_BLSP2_BCR 29
267#define GCC_BLSP2_QUP1_BCR 30
268#define GCC_BLSP2_UART1_BCR 31
269#define GCC_BLSP2_QUP2_BCR 32
270#define GCC_BLSP2_UART2_BCR 33
271#define GCC_BLSP2_QUP3_BCR 34
272#define GCC_BLSP2_UART3_BCR 35
273#define GCC_BLSP2_QUP4_BCR 36
274#define GCC_BLSP2_UART4_BCR 37
275#define GCC_BLSP2_QUP5_BCR 38
276#define GCC_BLSP2_UART5_BCR 39
277#define GCC_BLSP2_QUP6_BCR 40
278#define GCC_BLSP2_UART6_BCR 41
279#define GCC_PDM_BCR 42
280#define GCC_PRNG_BCR 43
281#define GCC_TSIF_BCR 44
282#define GCC_TCSR_BCR 45
283#define GCC_BOOT_ROM_BCR 46
284#define GCC_MSG_RAM_BCR 47
285#define GCC_TLMM_BCR 48
286#define GCC_MPM_BCR 49
287#define GCC_SEC_CTRL_BCR 50
288#define GCC_SPMI_BCR 51
289#define GCC_SPDM_BCR 52
290#define GCC_CE1_BCR 53
291#define GCC_BIMC_BCR 54
292#define GCC_SNOC_BUS_TIMEOUT0_BCR 55
293#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
294#define GCC_SNOC_BUS_TIMEOUT1_BCR 57
295#define GCC_SNOC_BUS_TIMEOUT3_BCR 58
296#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59
297#define GCC_PNOC_BUS_TIMEOUT0_BCR 60
298#define GCC_PNOC_BUS_TIMEOUT1_BCR 61
299#define GCC_PNOC_BUS_TIMEOUT2_BCR 62
300#define GCC_PNOC_BUS_TIMEOUT3_BCR 63
301#define GCC_PNOC_BUS_TIMEOUT4_BCR 64
302#define GCC_CNOC_BUS_TIMEOUT0_BCR 65
303#define GCC_CNOC_BUS_TIMEOUT1_BCR 66
304#define GCC_CNOC_BUS_TIMEOUT2_BCR 67
305#define GCC_CNOC_BUS_TIMEOUT3_BCR 68
306#define GCC_CNOC_BUS_TIMEOUT4_BCR 69
307#define GCC_CNOC_BUS_TIMEOUT5_BCR 70
308#define GCC_CNOC_BUS_TIMEOUT6_BCR 71
309#define GCC_CNOC_BUS_TIMEOUT7_BCR 72
310#define GCC_CNOC_BUS_TIMEOUT8_BCR 73
311#define GCC_CNOC_BUS_TIMEOUT9_BCR 74
312#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75
313#define GCC_APB2JTAG_BCR 76
314#define GCC_RBCPR_CX_BCR 77
315#define GCC_RBCPR_MX_BCR 78
316#define GCC_PCIE_0_BCR 79
317#define GCC_PCIE_0_PHY_BCR 80
318#define GCC_PCIE_1_BCR 81
319#define GCC_PCIE_1_PHY_BCR 82
320#define GCC_PCIE_2_BCR 83
321#define GCC_PCIE_2_PHY_BCR 84
322#define GCC_PCIE_PHY_BCR 85
323#define GCC_DCD_BCR 86
324#define GCC_OBT_ODT_BCR 87
325#define GCC_UFS_BCR 88
326#define GCC_SSC_BCR 89
327#define GCC_VS_BCR 90
328#define GCC_AGGRE0_NOC_BCR 91
329#define GCC_AGGRE1_NOC_BCR 92
330#define GCC_AGGRE2_NOC_BCR 93
331#define GCC_DCC_BCR 94
332#define GCC_IPA_BCR 95
333#define GCC_QSPI_BCR 96
334#define GCC_SKL_BCR 97
335#define GCC_MSMPU_BCR 98
336#define GCC_MSS_Q6_BCR 99
337#define GCC_QREFS_VBG_CAL_BCR 100
338
339#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
new file mode 100644
index 000000000000..9b81ca65fcec
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
@@ -0,0 +1,285 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
15#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
16
17#define MMPLL0_EARLY 0
18#define MMPLL0_PLL 1
19#define MMPLL1_EARLY 2
20#define MMPLL1_PLL 3
21#define MMPLL2_EARLY 4
22#define MMPLL2_PLL 5
23#define MMPLL3_EARLY 6
24#define MMPLL3_PLL 7
25#define MMPLL4_EARLY 8
26#define MMPLL4_PLL 9
27#define MMPLL5_EARLY 10
28#define MMPLL5_PLL 11
29#define MMPLL8_EARLY 12
30#define MMPLL8_PLL 13
31#define MMPLL9_EARLY 14
32#define MMPLL9_PLL 15
33#define AHB_CLK_SRC 16
34#define AXI_CLK_SRC 17
35#define MAXI_CLK_SRC 18
36#define DSA_CORE_CLK_SRC 19
37#define GFX3D_CLK_SRC 20
38#define RBBMTIMER_CLK_SRC 21
39#define ISENSE_CLK_SRC 22
40#define RBCPR_CLK_SRC 23
41#define VIDEO_CORE_CLK_SRC 24
42#define VIDEO_SUBCORE0_CLK_SRC 25
43#define VIDEO_SUBCORE1_CLK_SRC 26
44#define PCLK0_CLK_SRC 27
45#define PCLK1_CLK_SRC 28
46#define MDP_CLK_SRC 29
47#define EXTPCLK_CLK_SRC 30
48#define VSYNC_CLK_SRC 31
49#define HDMI_CLK_SRC 32
50#define BYTE0_CLK_SRC 33
51#define BYTE1_CLK_SRC 34
52#define ESC0_CLK_SRC 35
53#define ESC1_CLK_SRC 36
54#define CAMSS_GP0_CLK_SRC 37
55#define CAMSS_GP1_CLK_SRC 38
56#define MCLK0_CLK_SRC 39
57#define MCLK1_CLK_SRC 40
58#define MCLK2_CLK_SRC 41
59#define MCLK3_CLK_SRC 42
60#define CCI_CLK_SRC 43
61#define CSI0PHYTIMER_CLK_SRC 44
62#define CSI1PHYTIMER_CLK_SRC 45
63#define CSI2PHYTIMER_CLK_SRC 46
64#define CSIPHY0_3P_CLK_SRC 47
65#define CSIPHY1_3P_CLK_SRC 48
66#define CSIPHY2_3P_CLK_SRC 49
67#define JPEG0_CLK_SRC 50
68#define JPEG2_CLK_SRC 51
69#define JPEG_DMA_CLK_SRC 52
70#define VFE0_CLK_SRC 53
71#define VFE1_CLK_SRC 54
72#define CPP_CLK_SRC 55
73#define CSI0_CLK_SRC 56
74#define CSI1_CLK_SRC 57
75#define CSI2_CLK_SRC 58
76#define CSI3_CLK_SRC 59
77#define FD_CORE_CLK_SRC 60
78#define MMSS_CXO_CLK 61
79#define MMSS_SLEEPCLK_CLK 62
80#define MMSS_MMAGIC_AHB_CLK 63
81#define MMSS_MMAGIC_CFG_AHB_CLK 64
82#define MMSS_MISC_AHB_CLK 65
83#define MMSS_MISC_CXO_CLK 66
84#define MMSS_BTO_AHB_CLK 67
85#define MMSS_MMAGIC_AXI_CLK 68
86#define MMSS_S0_AXI_CLK 69
87#define MMSS_MMAGIC_MAXI_CLK 70
88#define DSA_CORE_CLK 71
89#define DSA_NOC_CFG_AHB_CLK 72
90#define MMAGIC_CAMSS_AXI_CLK 73
91#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74
92#define THROTTLE_CAMSS_CXO_CLK 75
93#define THROTTLE_CAMSS_AHB_CLK 76
94#define THROTTLE_CAMSS_AXI_CLK 77
95#define SMMU_VFE_AHB_CLK 78
96#define SMMU_VFE_AXI_CLK 79
97#define SMMU_CPP_AHB_CLK 80
98#define SMMU_CPP_AXI_CLK 81
99#define SMMU_JPEG_AHB_CLK 82
100#define SMMU_JPEG_AXI_CLK 83
101#define MMAGIC_MDSS_AXI_CLK 84
102#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85
103#define THROTTLE_MDSS_CXO_CLK 86
104#define THROTTLE_MDSS_AHB_CLK 87
105#define THROTTLE_MDSS_AXI_CLK 88
106#define SMMU_ROT_AHB_CLK 89
107#define SMMU_ROT_AXI_CLK 90
108#define SMMU_MDP_AHB_CLK 91
109#define SMMU_MDP_AXI_CLK 92
110#define MMAGIC_VIDEO_AXI_CLK 93
111#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94
112#define THROTTLE_VIDEO_CXO_CLK 95
113#define THROTTLE_VIDEO_AHB_CLK 96
114#define THROTTLE_VIDEO_AXI_CLK 97
115#define SMMU_VIDEO_AHB_CLK 98
116#define SMMU_VIDEO_AXI_CLK 99
117#define MMAGIC_BIMC_AXI_CLK 100
118#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101
119#define GPU_GX_GFX3D_CLK 102
120#define GPU_GX_RBBMTIMER_CLK 103
121#define GPU_AHB_CLK 104
122#define GPU_AON_ISENSE_CLK 105
123#define VMEM_MAXI_CLK 106
124#define VMEM_AHB_CLK 107
125#define MMSS_RBCPR_CLK 108
126#define MMSS_RBCPR_AHB_CLK 109
127#define VIDEO_CORE_CLK 110
128#define VIDEO_AXI_CLK 111
129#define VIDEO_MAXI_CLK 112
130#define VIDEO_AHB_CLK 113
131#define VIDEO_SUBCORE0_CLK 114
132#define VIDEO_SUBCORE1_CLK 115
133#define MDSS_AHB_CLK 116
134#define MDSS_HDMI_AHB_CLK 117
135#define MDSS_AXI_CLK 118
136#define MDSS_PCLK0_CLK 119
137#define MDSS_PCLK1_CLK 120
138#define MDSS_MDP_CLK 121
139#define MDSS_EXTPCLK_CLK 122
140#define MDSS_VSYNC_CLK 123
141#define MDSS_HDMI_CLK 124
142#define MDSS_BYTE0_CLK 125
143#define MDSS_BYTE1_CLK 126
144#define MDSS_ESC0_CLK 127
145#define MDSS_ESC1_CLK 128
146#define CAMSS_TOP_AHB_CLK 129
147#define CAMSS_AHB_CLK 130
148#define CAMSS_MICRO_AHB_CLK 131
149#define CAMSS_GP0_CLK 132
150#define CAMSS_GP1_CLK 133
151#define CAMSS_MCLK0_CLK 134
152#define CAMSS_MCLK1_CLK 135
153#define CAMSS_MCLK2_CLK 136
154#define CAMSS_MCLK3_CLK 137
155#define CAMSS_CCI_CLK 138
156#define CAMSS_CCI_AHB_CLK 139
157#define CAMSS_CSI0PHYTIMER_CLK 140
158#define CAMSS_CSI1PHYTIMER_CLK 141
159#define CAMSS_CSI2PHYTIMER_CLK 142
160#define CAMSS_CSIPHY0_3P_CLK 143
161#define CAMSS_CSIPHY1_3P_CLK 144
162#define CAMSS_CSIPHY2_3P_CLK 145
163#define CAMSS_JPEG0_CLK 146
164#define CAMSS_JPEG2_CLK 147
165#define CAMSS_JPEG_DMA_CLK 148
166#define CAMSS_JPEG_AHB_CLK 149
167#define CAMSS_JPEG_AXI_CLK 150
168#define CAMSS_VFE_AHB_CLK 151
169#define CAMSS_VFE_AXI_CLK 152
170#define CAMSS_VFE0_CLK 153
171#define CAMSS_VFE0_STREAM_CLK 154
172#define CAMSS_VFE0_AHB_CLK 155
173#define CAMSS_VFE1_CLK 156
174#define CAMSS_VFE1_STREAM_CLK 157
175#define CAMSS_VFE1_AHB_CLK 158
176#define CAMSS_CSI_VFE0_CLK 159
177#define CAMSS_CSI_VFE1_CLK 160
178#define CAMSS_CPP_VBIF_AHB_CLK 161
179#define CAMSS_CPP_AXI_CLK 162
180#define CAMSS_CPP_CLK 163
181#define CAMSS_CPP_AHB_CLK 164
182#define CAMSS_CSI0_CLK 165
183#define CAMSS_CSI0_AHB_CLK 166
184#define CAMSS_CSI0PHY_CLK 167
185#define CAMSS_CSI0RDI_CLK 168
186#define CAMSS_CSI0PIX_CLK 169
187#define CAMSS_CSI1_CLK 170
188#define CAMSS_CSI1_AHB_CLK 171
189#define CAMSS_CSI1PHY_CLK 172
190#define CAMSS_CSI1RDI_CLK 173
191#define CAMSS_CSI1PIX_CLK 174
192#define CAMSS_CSI2_CLK 175
193#define CAMSS_CSI2_AHB_CLK 176
194#define CAMSS_CSI2PHY_CLK 177
195#define CAMSS_CSI2RDI_CLK 178
196#define CAMSS_CSI2PIX_CLK 179
197#define CAMSS_CSI3_CLK 180
198#define CAMSS_CSI3_AHB_CLK 181
199#define CAMSS_CSI3PHY_CLK 182
200#define CAMSS_CSI3RDI_CLK 183
201#define CAMSS_CSI3PIX_CLK 184
202#define CAMSS_ISPIF_AHB_CLK 185
203#define FD_CORE_CLK 186
204#define FD_CORE_UAR_CLK 187
205#define FD_AHB_CLK 188
206#define MMSS_SPDM_CSI0_CLK 189
207#define MMSS_SPDM_JPEG_DMA_CLK 190
208#define MMSS_SPDM_CPP_CLK 191
209#define MMSS_SPDM_PCLK0_CLK 192
210#define MMSS_SPDM_AHB_CLK 193
211#define MMSS_SPDM_GFX3D_CLK 194
212#define MMSS_SPDM_PCLK1_CLK 195
213#define MMSS_SPDM_JPEG2_CLK 196
214#define MMSS_SPDM_DEBUG_CLK 197
215#define MMSS_SPDM_VFE1_CLK 198
216#define MMSS_SPDM_VFE0_CLK 199
217#define MMSS_SPDM_VIDEO_CORE_CLK 200
218#define MMSS_SPDM_AXI_CLK 201
219#define MMSS_SPDM_MDP_CLK 202
220#define MMSS_SPDM_JPEG0_CLK 203
221#define MMSS_SPDM_RM_AXI_CLK 204
222#define MMSS_SPDM_RM_MAXI_CLK 205
223
224#define MMAGICAHB_BCR 0
225#define MMAGIC_CFG_BCR 1
226#define MISC_BCR 2
227#define BTO_BCR 3
228#define MMAGICAXI_BCR 4
229#define MMAGICMAXI_BCR 5
230#define DSA_BCR 6
231#define MMAGIC_CAMSS_BCR 7
232#define THROTTLE_CAMSS_BCR 8
233#define SMMU_VFE_BCR 9
234#define SMMU_CPP_BCR 10
235#define SMMU_JPEG_BCR 11
236#define MMAGIC_MDSS_BCR 12
237#define THROTTLE_MDSS_BCR 13
238#define SMMU_ROT_BCR 14
239#define SMMU_MDP_BCR 15
240#define MMAGIC_VIDEO_BCR 16
241#define THROTTLE_VIDEO_BCR 17
242#define SMMU_VIDEO_BCR 18
243#define MMAGIC_BIMC_BCR 19
244#define GPU_GX_BCR 20
245#define GPU_BCR 21
246#define GPU_AON_BCR 22
247#define VMEM_BCR 23
248#define MMSS_RBCPR_BCR 24
249#define VIDEO_BCR 25
250#define MDSS_BCR 26
251#define CAMSS_TOP_BCR 27
252#define CAMSS_AHB_BCR 28
253#define CAMSS_MICRO_BCR 29
254#define CAMSS_CCI_BCR 30
255#define CAMSS_PHY0_BCR 31
256#define CAMSS_PHY1_BCR 32
257#define CAMSS_PHY2_BCR 33
258#define CAMSS_CSIPHY0_3P_BCR 34
259#define CAMSS_CSIPHY1_3P_BCR 35
260#define CAMSS_CSIPHY2_3P_BCR 36
261#define CAMSS_JPEG_BCR 37
262#define CAMSS_VFE_BCR 38
263#define CAMSS_VFE0_BCR 39
264#define CAMSS_VFE1_BCR 40
265#define CAMSS_CSI_VFE0_BCR 41
266#define CAMSS_CSI_VFE1_BCR 42
267#define CAMSS_CPP_TOP_BCR 43
268#define CAMSS_CPP_BCR 44
269#define CAMSS_CSI0_BCR 45
270#define CAMSS_CSI0RDI_BCR 46
271#define CAMSS_CSI0PIX_BCR 47
272#define CAMSS_CSI1_BCR 48
273#define CAMSS_CSI1RDI_BCR 49
274#define CAMSS_CSI1PIX_BCR 50
275#define CAMSS_CSI2_BCR 51
276#define CAMSS_CSI2RDI_BCR 52
277#define CAMSS_CSI2PIX_BCR 53
278#define CAMSS_CSI3_BCR 54
279#define CAMSS_CSI3RDI_BCR 55
280#define CAMSS_CSI3PIX_BCR 56
281#define CAMSS_ISPIF_BCR 57
282#define FD_BCR 58
283#define MMSS_SPDM_RM_BCR 59
284
285#endif
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000000000000..ebc7a7b43f52
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,193 @@
1/*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
17#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
18
19/* core clocks */
20#define PLL_APLL 1
21#define PLL_DPLL 2
22#define PLL_GPLL 3
23#define ARMCLK 4
24
25/* sclk gates (special clocks) */
26#define SCLK_GPU 64
27#define SCLK_SPI 65
28#define SCLK_SDMMC 68
29#define SCLK_SDIO 69
30#define SCLK_EMMC 71
31#define SCLK_NANDC 76
32#define SCLK_UART0 77
33#define SCLK_UART1 78
34#define SCLK_UART2 79
35#define SCLK_I2S 82
36#define SCLK_SPDIF 83
37#define SCLK_TIMER0 85
38#define SCLK_TIMER1 86
39#define SCLK_TIMER2 87
40#define SCLK_TIMER3 88
41#define SCLK_OTGPHY0 93
42#define SCLK_LCDC 100
43#define SCLK_HDMI 109
44#define SCLK_HEVC 111
45#define SCLK_I2S_OUT 113
46#define SCLK_SDMMC_DRV 114
47#define SCLK_SDIO_DRV 115
48#define SCLK_EMMC_DRV 117
49#define SCLK_SDMMC_SAMPLE 118
50#define SCLK_SDIO_SAMPLE 119
51#define SCLK_EMMC_SAMPLE 121
52#define SCLK_PVTM_CORE 123
53#define SCLK_PVTM_GPU 124
54#define SCLK_PVTM_VIDEO 125
55#define SCLK_MAC 151
56#define SCLK_MACREF 152
57#define SCLK_SFC 160
58
59/* aclk gates */
60#define ACLK_DMAC2 194
61#define ACLK_LCDC 197
62#define ACLK_VIO 203
63#define ACLK_VCODEC 208
64#define ACLK_CPU 209
65#define ACLK_PERI 210
66
67/* pclk gates */
68#define PCLK_GPIO0 320
69#define PCLK_GPIO1 321
70#define PCLK_GPIO2 322
71#define PCLK_GRF 329
72#define PCLK_I2C0 332
73#define PCLK_I2C1 333
74#define PCLK_I2C2 334
75#define PCLK_SPI 338
76#define PCLK_UART0 341
77#define PCLK_UART1 342
78#define PCLK_UART2 343
79#define PCLK_PWM 350
80#define PCLK_TIMER 353
81#define PCLK_HDMI 360
82#define PCLK_CPU 362
83#define PCLK_PERI 363
84#define PCLK_DDRUPCTL 364
85#define PCLK_WDT 368
86#define PCLK_ACODEC 369
87
88/* hclk gates */
89#define HCLK_OTG0 449
90#define HCLK_OTG1 450
91#define HCLK_NANDC 453
92#define HCLK_SDMMC 456
93#define HCLK_SDIO 457
94#define HCLK_EMMC 459
95#define HCLK_I2S 462
96#define HCLK_LCDC 465
97#define HCLK_ROM 467
98#define HCLK_VIO_BUS 472
99#define HCLK_VCODEC 476
100#define HCLK_CPU 477
101#define HCLK_PERI 478
102
103#define CLK_NR_CLKS (HCLK_PERI + 1)
104
105/* soft-reset indices */
106#define SRST_CORE0 0
107#define SRST_CORE1 1
108#define SRST_CORE0_DBG 4
109#define SRST_CORE1_DBG 5
110#define SRST_CORE0_POR 8
111#define SRST_CORE1_POR 9
112#define SRST_L2C 12
113#define SRST_TOPDBG 13
114#define SRST_STRC_SYS_A 14
115#define SRST_PD_CORE_NIU 15
116
117#define SRST_TIMER2 16
118#define SRST_CPUSYS_H 17
119#define SRST_AHB2APB_H 19
120#define SRST_TIMER3 20
121#define SRST_INTMEM 21
122#define SRST_ROM 22
123#define SRST_PERI_NIU 23
124#define SRST_I2S 24
125#define SRST_DDR_PLL 25
126#define SRST_GPU_DLL 26
127#define SRST_TIMER0 27
128#define SRST_TIMER1 28
129#define SRST_CORE_DLL 29
130#define SRST_EFUSE_P 30
131#define SRST_ACODEC_P 31
132
133#define SRST_GPIO0 32
134#define SRST_GPIO1 33
135#define SRST_GPIO2 34
136#define SRST_UART0 39
137#define SRST_UART1 40
138#define SRST_UART2 41
139#define SRST_I2C0 43
140#define SRST_I2C1 44
141#define SRST_I2C2 45
142#define SRST_SFC 47
143
144#define SRST_PWM0 48
145#define SRST_DAP 51
146#define SRST_DAP_SYS 52
147#define SRST_GRF 55
148#define SRST_PERIPHSYS_A 57
149#define SRST_PERIPHSYS_H 58
150#define SRST_PERIPHSYS_P 59
151#define SRST_CPU_PERI 61
152#define SRST_EMEM_PERI 62
153#define SRST_USB_PERI 63
154
155#define SRST_DMA2 64
156#define SRST_MAC 66
157#define SRST_NANDC 68
158#define SRST_USBOTG0 69
159#define SRST_OTGC0 71
160#define SRST_USBOTG1 72
161#define SRST_OTGC1 74
162#define SRST_DDRMSCH 79
163
164#define SRST_MMC0 81
165#define SRST_SDIO 82
166#define SRST_EMMC 83
167#define SRST_SPI0 84
168#define SRST_WDT 86
169#define SRST_DDRPHY 88
170#define SRST_DDRPHY_P 89
171#define SRST_DDRCTRL 90
172#define SRST_DDRCTRL_P 91
173
174#define SRST_HDMI_P 96
175#define SRST_VIO_BUS_H 99
176#define SRST_UTMI0 103
177#define SRST_UTMI1 104
178#define SRST_USBPOR 105
179
180#define SRST_VCODEC_A 112
181#define SRST_VCODEC_H 113
182#define SRST_VIO1_A 114
183#define SRST_HEVC 115
184#define SRST_VCODEC_NIU_A 116
185#define SRST_LCDC1_A 117
186#define SRST_LCDC1_H 118
187#define SRST_LCDC1_D 119
188#define SRST_GPU 120
189#define SRST_GPU_NIU_A 122
190
191#define SRST_DBG_P 131
192
193#endif
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
new file mode 100644
index 000000000000..a78dd891e24a
--- /dev/null
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -0,0 +1,220 @@
1/*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
17#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
18
19/* core clocks */
20#define PLL_APLL 1
21#define PLL_DPLL 2
22#define PLL_CPLL 3
23#define PLL_GPLL 4
24#define ARMCLK 5
25
26/* sclk gates (special clocks) */
27#define SCLK_SPI0 65
28#define SCLK_NANDC 67
29#define SCLK_SDMMC 68
30#define SCLK_SDIO 69
31#define SCLK_EMMC 71
32#define SCLK_UART0 77
33#define SCLK_UART1 78
34#define SCLK_UART2 79
35#define SCLK_I2S0 80
36#define SCLK_I2S1 81
37#define SCLK_I2S2 82
38#define SCLK_SPDIF 83
39#define SCLK_TIMER0 85
40#define SCLK_TIMER1 86
41#define SCLK_TIMER2 87
42#define SCLK_TIMER3 88
43#define SCLK_TIMER4 89
44#define SCLK_TIMER5 90
45#define SCLK_I2S_OUT 113
46#define SCLK_SDMMC_DRV 114
47#define SCLK_SDIO_DRV 115
48#define SCLK_EMMC_DRV 117
49#define SCLK_SDMMC_SAMPLE 118
50#define SCLK_SDIO_SAMPLE 119
51#define SCLK_EMMC_SAMPLE 121
52
53/* aclk gates */
54#define ACLK_DMAC 194
55#define ACLK_PERI 210
56
57/* pclk gates */
58#define PCLK_GPIO0 320
59#define PCLK_GPIO1 321
60#define PCLK_GPIO2 322
61#define PCLK_GPIO3 323
62#define PCLK_GRF 329
63#define PCLK_I2C0 332
64#define PCLK_I2C1 333
65#define PCLK_I2C2 334
66#define PCLK_I2C3 335
67#define PCLK_SPI0 338
68#define PCLK_UART0 341
69#define PCLK_UART1 342
70#define PCLK_UART2 343
71#define PCLK_PWM 350
72#define PCLK_TIMER 353
73#define PCLK_PERI 363
74
75/* hclk gates */
76#define HCLK_NANDC 453
77#define HCLK_SDMMC 456
78#define HCLK_SDIO 457
79#define HCLK_EMMC 459
80#define HCLK_PERI 478
81
82#define CLK_NR_CLKS (HCLK_PERI + 1)
83
84/* soft-reset indices */
85#define SRST_CORE0_PO 0
86#define SRST_CORE1_PO 1
87#define SRST_CORE2_PO 2
88#define SRST_CORE3_PO 3
89#define SRST_CORE0 4
90#define SRST_CORE1 5
91#define SRST_CORE2 6
92#define SRST_CORE3 7
93#define SRST_CORE0_DBG 8
94#define SRST_CORE1_DBG 9
95#define SRST_CORE2_DBG 10
96#define SRST_CORE3_DBG 11
97#define SRST_TOPDBG 12
98#define SRST_ACLK_CORE 13
99#define SRST_NOC 14
100#define SRST_L2C 15
101
102#define SRST_CPUSYS_H 18
103#define SRST_BUSSYS_H 19
104#define SRST_SPDIF 20
105#define SRST_INTMEM 21
106#define SRST_ROM 22
107#define SRST_OTG_ADP 23
108#define SRST_I2S0 24
109#define SRST_I2S1 25
110#define SRST_I2S2 26
111#define SRST_ACODEC_P 27
112#define SRST_DFIMON 28
113#define SRST_MSCH 29
114#define SRST_EFUSE1024 30
115#define SRST_EFUSE256 31
116
117#define SRST_GPIO0 32
118#define SRST_GPIO1 33
119#define SRST_GPIO2 34
120#define SRST_GPIO3 35
121#define SRST_PERIPH_NOC_A 36
122#define SRST_PERIPH_NOC_BUS_H 37
123#define SRST_PERIPH_NOC_P 38
124#define SRST_UART0 39
125#define SRST_UART1 40
126#define SRST_UART2 41
127#define SRST_PHYNOC 42
128#define SRST_I2C0 43
129#define SRST_I2C1 44
130#define SRST_I2C2 45
131#define SRST_I2C3 46
132
133#define SRST_PWM 48
134#define SRST_A53_GIC 49
135#define SRST_DAP 51
136#define SRST_DAP_NOC 52
137#define SRST_CRYPTO 53
138#define SRST_SGRF 54
139#define SRST_GRF 55
140#define SRST_GMAC 56
141#define SRST_PERIPH_NOC_H 58
142#define SRST_MACPHY 63
143
144#define SRST_DMA 64
145#define SRST_NANDC 68
146#define SRST_USBOTG 69
147#define SRST_OTGC 70
148#define SRST_USBHOST0 71
149#define SRST_HOST_CTRL0 72
150#define SRST_USBHOST1 73
151#define SRST_HOST_CTRL1 74
152#define SRST_USBHOST2 75
153#define SRST_HOST_CTRL2 76
154#define SRST_USBPOR0 77
155#define SRST_USBPOR1 78
156#define SRST_DDRMSCH 79
157
158#define SRST_SMART_CARD 80
159#define SRST_SDMMC 81
160#define SRST_SDIO 82
161#define SRST_EMMC 83
162#define SRST_SPI 84
163#define SRST_TSP_H 85
164#define SRST_TSP 86
165#define SRST_TSADC 87
166#define SRST_DDRPHY 88
167#define SRST_DDRPHY_P 89
168#define SRST_DDRCTRL 90
169#define SRST_DDRCTRL_P 91
170#define SRST_HOST0_ECHI 92
171#define SRST_HOST1_ECHI 93
172#define SRST_HOST2_ECHI 94
173#define SRST_VOP_NOC_A 95
174
175#define SRST_HDMI_P 96
176#define SRST_VIO_ARBI_H 97
177#define SRST_IEP_NOC_A 98
178#define SRST_VIO_NOC_H 99
179#define SRST_VOP_A 100
180#define SRST_VOP_H 101
181#define SRST_VOP_D 102
182#define SRST_UTMI0 103
183#define SRST_UTMI1 104
184#define SRST_UTMI2 105
185#define SRST_UTMI3 106
186#define SRST_RGA 107
187#define SRST_RGA_NOC_A 108
188#define SRST_RGA_A 109
189#define SRST_RGA_H 110
190#define SRST_HDCP_A 111
191
192#define SRST_VPU_A 112
193#define SRST_VPU_H 113
194#define SRST_VPU_NOC_A 116
195#define SRST_VPU_NOC_H 117
196#define SRST_RKVDEC_A 118
197#define SRST_RKVDEC_NOC_A 119
198#define SRST_RKVDEC_H 120
199#define SRST_RKVDEC_NOC_H 121
200#define SRST_RKVDEC_CORE 122
201#define SRST_RKVDEC_CABAC 123
202#define SRST_IEP_A 124
203#define SRST_IEP_H 125
204#define SRST_GPU_A 126
205#define SRST_GPU_NOC_A 127
206
207#define SRST_CORE_DBG 128
208#define SRST_DBG_P 129
209#define SRST_TIMER0 130
210#define SRST_TIMER1 131
211#define SRST_TIMER2 132
212#define SRST_TIMER3 133
213#define SRST_TIMER4 134
214#define SRST_TIMER5 135
215#define SRST_VIO_H2P 136
216#define SRST_HDMIPHY 139
217#define SRST_VDAC 140
218#define SRST_TIMER_6CH_P 141
219
220#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index c719aacef14f..9a586e2d9c91 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -86,6 +86,8 @@
86#define SCLK_USBPHY480M_SRC 122 86#define SCLK_USBPHY480M_SRC 122
87#define SCLK_PVTM_CORE 123 87#define SCLK_PVTM_CORE 123
88#define SCLK_PVTM_GPU 124 88#define SCLK_PVTM_GPU 124
89#define SCLK_CRYPTO 125
90#define SCLK_MIPIDSI_24M 126
89 91
90#define SCLK_MAC 151 92#define SCLK_MAC 151
91#define SCLK_MACREF_OUT 152 93#define SCLK_MACREF_OUT 152
@@ -164,6 +166,8 @@
164#define PCLK_DDRUPCTL1 366 166#define PCLK_DDRUPCTL1 366
165#define PCLK_PUBL1 367 167#define PCLK_PUBL1 367
166#define PCLK_WDT 368 168#define PCLK_WDT 368
169#define PCLK_EFUSE256 369
170#define PCLK_EFUSE1024 370
167 171
168/* hclk gates */ 172/* hclk gates */
169#define HCLK_GPS 448 173#define HCLK_GPS 448
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c56988ac63f7..1796f7d8526c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -44,7 +44,7 @@ struct dentry;
44 * @rate: Requested clock rate. This field will be adjusted by 44 * @rate: Requested clock rate. This field will be adjusted by
45 * clock drivers according to hardware capabilities. 45 * clock drivers according to hardware capabilities.
46 * @min_rate: Minimum rate imposed by clk users. 46 * @min_rate: Minimum rate imposed by clk users.
47 * @max_rate: Maximum rate a imposed by clk users. 47 * @max_rate: Maximum rate imposed by clk users.
48 * @best_parent_rate: The best parent rate a parent can provide to fulfill the 48 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
49 * requested constraints. 49 * requested constraints.
50 * @best_parent_hw: The most appropriate parent clock that fulfills the 50 * @best_parent_hw: The most appropriate parent clock that fulfills the
@@ -715,8 +715,7 @@ static inline int of_clk_add_provider(struct device_node *np,
715{ 715{
716 return 0; 716 return 0;
717} 717}
718#define of_clk_del_provider(np) \ 718static inline void of_clk_del_provider(struct device_node *np) {}
719 { while (0); }
720static inline struct clk *of_clk_src_simple_get( 719static inline struct clk *of_clk_src_simple_get(
721 struct of_phandle_args *clkspec, void *data) 720 struct of_phandle_args *clkspec, void *data)
722{ 721{
@@ -741,8 +740,7 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
741{ 740{
742 return NULL; 741 return NULL;
743} 742}
744#define of_clk_init(matches) \ 743static inline void of_clk_init(const struct of_device_id *matches) {}
745 { while (0); }
746#endif /* CONFIG_OF */ 744#endif /* CONFIG_OF */
747 745
748/* 746/*
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 223be696df27..75205df29b9c 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -286,6 +286,7 @@ struct ti_clk_features {
286#define TI_CLK_DPLL_HAS_FREQSEL BIT(0) 286#define TI_CLK_DPLL_HAS_FREQSEL BIT(0)
287#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) 287#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
288#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) 288#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
289#define TI_CLK_ERRATA_I810 BIT(3)
289 290
290void ti_clk_setup_features(struct ti_clk_features *features); 291void ti_clk_setup_features(struct ti_clk_features *features);
291const struct ti_clk_features *ti_clk_get_features(void); 292const struct ti_clk_features *ti_clk_get_features(void);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 15:28:37 -0400