drm/amd/pp: use soc15 common macros instead of vega10 specific

pp_soc15.h is vega10 specific. Update powerplay code to use soc15 common
macros defined in soc15_common.h.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

10 files changed, 133 insertions, 280 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 055358b95fdf..6ba3b1fa57aa 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -34,7 +34,7 @@
 #include "rv_ppsmc.h"
 #include "smu10_hwmgr.h"
 #include "power_state.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 
 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5
 #define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
@@ -947,9 +947,8 @@ static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simpl
 
 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 {
-        uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0,
-                        mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP);
-        uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset);
+        struct amdgpu_device *adev = hwmgr->adev;
+        uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
         int cur_temp =
                 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index ba299424f8f6..f6427c88f6a7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -36,7 +36,7 @@
 #include "smu9.h"
 #include "smu9_driver_if.h"
 #include "vega10_inc.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 #include "pppcielanes.h"
 #include "vega10_hwmgr.h"
 #include "vega10_processpptables.h"
@@ -754,7 +754,6 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
         uint32_t config_telemetry = 0;
         struct pp_atomfwctrl_voltage_table vol_table;
         struct amdgpu_device *adev = hwmgr->adev;
-        uint32_t reg;
 
         data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
         if (data == NULL)
@@ -860,10 +859,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
                         advanceFanControlParameters.usFanPWMMinLimit *
                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 
-        reg = soc15_get_register_offset(DF_HWID, 0,
-                        mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
-                        mmDF_CS_AON0_DramBaseAddress0);
-        data->mem_channels = (cgs_read_register(hwmgr->device, reg) &
+        data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
         PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
@@ -3808,11 +3804,12 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
                               void *value, int *size)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t sclk_idx, mclk_idx, activity_percent = 0;
         struct vega10_hwmgr *data = hwmgr->backend;
         struct vega10_dpm_table *dpm_table = &data->dpm_table;
         int ret = 0;
-        uint32_t reg, val_vid;
+        uint32_t val_vid;
 
         switch (idx) {
         case AMDGPU_PP_SENSOR_GFX_SCLK:
@@ -3862,10 +3859,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
                 }
                 break;
         case AMDGPU_PP_SENSOR_VDDGFX:
-                reg = soc15_get_register_offset(SMUIO_HWID, 0,
-                        mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX,
-                        mmSMUSVI0_PLANE0_CURRENTVID);
-                val_vid = (cgs_read_register(hwmgr->device, reg) &
+                val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
                 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index 203a6918395b..a9efd8554fbc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -27,7 +27,7 @@
 #include "vega10_ppsmc.h"
 #include "vega10_inc.h"
 #include "pp_debug.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 
 static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] =
 {
@@ -888,36 +888,36 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
         if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
                 if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
-                        data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
-                        data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
+                        data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
+                        data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
                 }
 
                 if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
-                        data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
-                        data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
+                        data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
+                        data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
                 }
 
                 if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
-                        data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
-                        data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
+                        data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
+                        data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
                 }
 
                 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
-                        data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
-                        data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
+                        data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
+                        data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
                 }
 
                 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
-                        data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
-                        data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
+                        data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
+                        data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
                 }
         }
@@ -933,17 +933,15 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
         struct amdgpu_device *adev = hwmgr->adev;
         int result;
         uint32_t num_se = 0, count, data;
-        uint32_t reg;
 
         num_se = adev->gfx.config.max_shader_engines;
 
         adev->gfx.rlc.funcs->enter_safe_mode(adev);
 
         mutex_lock(&adev->grbm_idx_mutex);
-        reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
         for (count = 0; count < num_se; count++) {
                 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
-                cgs_write_register(hwmgr->device, reg, data);
+                WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 
                 result =  vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
@@ -958,7 +956,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
                 if (0 != result)
                         break;
         }
-        cgs_write_register(hwmgr->device, reg, 0xE0000000);
+        WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
         mutex_unlock(&adev->grbm_idx_mutex);
 
         vega10_didt_set_mask(hwmgr, true);
@@ -986,17 +984,15 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
         struct amdgpu_device *adev = hwmgr->adev;
         int result;
         uint32_t num_se = 0, count, data;
-        uint32_t reg;
 
         num_se = adev->gfx.config.max_shader_engines;
 
         adev->gfx.rlc.funcs->enter_safe_mode(adev);
 
         mutex_lock(&adev->grbm_idx_mutex);
-        reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
         for (count = 0; count < num_se; count++) {
                 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
-                cgs_write_register(hwmgr->device, reg, data);
+                WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 
                 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
@@ -1005,7 +1001,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
                 if (0 != result)
                         break;
         }
-        cgs_write_register(hwmgr->device, reg, 0xE0000000);
+        WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
         mutex_unlock(&adev->grbm_idx_mutex);
 
         vega10_didt_set_mask(hwmgr, true);
@@ -1049,17 +1045,15 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
         struct amdgpu_device *adev = hwmgr->adev;
         int result;
         uint32_t num_se = 0, count, data;
-        uint32_t reg;
 
         num_se = adev->gfx.config.max_shader_engines;
 
         adev->gfx.rlc.funcs->enter_safe_mode(adev);
 
         mutex_lock(&adev->grbm_idx_mutex);
-        reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
         for (count = 0; count < num_se; count++) {
                 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
-                cgs_write_register(hwmgr->device, reg, data);
+                WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
                 result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
                 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
                 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
@@ -1070,7 +1064,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
                 if (0 != result)
                         break;
         }
-        cgs_write_register(hwmgr->device, reg, 0xE0000000);
+        WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
         mutex_unlock(&adev->grbm_idx_mutex);
 
         vega10_didt_set_mask(hwmgr, true);
@@ -1099,7 +1093,6 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
         int result;
         uint32_t num_se = 0;
         uint32_t count, data;
-        uint32_t reg;
 
         num_se = adev->gfx.config.max_shader_engines;
 
@@ -1108,10 +1101,9 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
         vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
 
         mutex_lock(&adev->grbm_idx_mutex);
-        reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
         for (count = 0; count < num_se; count++) {
                 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
-                cgs_write_register(hwmgr->device, reg, data);
+                WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
                 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
                 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
                 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
@@ -1120,7 +1112,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
                 if (0 != result)
                         break;
         }
-        cgs_write_register(hwmgr->device, reg, 0xE0000000);
+        WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
         mutex_unlock(&adev->grbm_idx_mutex);
 
         vega10_didt_set_mask(hwmgr, true);
@@ -1165,14 +1157,12 @@ static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
 static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
 {
         struct amdgpu_device *adev = hwmgr->adev;
-        uint32_t reg;
         int result;
 
         adev->gfx.rlc.funcs->enter_safe_mode(adev);
 
         mutex_lock(&adev->grbm_idx_mutex);
-        reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
-        cgs_write_register(hwmgr->device, reg, 0xE0000000);
+        WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
         mutex_unlock(&adev->grbm_idx_mutex);
 
         result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index 9f18226a56ea..aa044c1955fe 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -25,7 +25,7 @@
 #include "vega10_hwmgr.h"
 #include "vega10_ppsmc.h"
 #include "vega10_inc.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 #include "pp_debug.h"
 
 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
@@ -89,6 +89,7 @@ int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
 
 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         struct vega10_hwmgr *data = hwmgr->backend;
         uint32_t tach_period;
         uint32_t crystal_clock_freq;
@@ -100,10 +101,8 @@ int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
                 result = vega10_get_current_rpm(hwmgr, speed);
         } else {
-                uint32_t reg = soc15_get_register_offset(THM_HWID, 0,
-                                mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
                 tach_period =
-                        CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
+                        REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
                                           CG_TACH_STATUS,
                                           TACH_PERIOD);
 
@@ -127,26 +126,23 @@ int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
 */
 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 {
-        uint32_t reg;
-
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
+        struct amdgpu_device *adev = hwmgr->adev;
 
         if (hwmgr->fan_ctrl_is_in_default_mode) {
                 hwmgr->fan_ctrl_default_mode =
-                        CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
+                        REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
                                 CG_FDO_CTRL2, FDO_PWM_MODE);
                 hwmgr->tmin =
-                        CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
+                        REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
                                 CG_FDO_CTRL2, TMIN);
                 hwmgr->fan_ctrl_is_in_default_mode = false;
         }
 
-        cgs_write_register(hwmgr->device, reg,
-                        CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+        WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+                        REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
                                 CG_FDO_CTRL2, TMIN, 0));
-        cgs_write_register(hwmgr->device, reg,
-                        CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+        WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+                        REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
                                 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
 
         return 0;
@@ -159,18 +155,15 @@ int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 */
 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
 {
-        uint32_t reg;
-
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
+        struct amdgpu_device *adev = hwmgr->adev;
 
         if (!hwmgr->fan_ctrl_is_in_default_mode) {
-                cgs_write_register(hwmgr->device, reg,
-                        CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+                WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+                        REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
                                 CG_FDO_CTRL2, FDO_PWM_MODE,
                                 hwmgr->fan_ctrl_default_mode));
-                cgs_write_register(hwmgr->device, reg,
-                        CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+                WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+                        REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
                                 CG_FDO_CTRL2, TMIN,
                                 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
                 hwmgr->fan_ctrl_is_in_default_mode = true;
@@ -257,10 +250,10 @@ int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
                 uint32_t speed)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t duty100;
         uint32_t duty;
         uint64_t tmp64;
-        uint32_t reg;
 
         if (hwmgr->thermal_controller.fanInfo.bNoFan)
                 return 0;
@@ -271,10 +264,7 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
         if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
-
-        duty100 = CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
+        duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
                                     CG_FDO_CTRL1, FMAX_DUTY100);
 
         if (duty100 == 0)
@@ -284,10 +274,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
         do_div(tmp64, 100);
         duty = (uint32_t)tmp64;
 
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
-        cgs_write_register(hwmgr->device, reg,
-                CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+        WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
+                REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
                         CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
 
         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
@@ -317,10 +305,10 @@ int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
 */
 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t tach_period;
         uint32_t crystal_clock_freq;
         int result = 0;
-        uint32_t reg;
 
         if (hwmgr->thermal_controller.fanInfo.bNoFan ||
             (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
@@ -333,10 +321,8 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
         if (!result) {
                 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
                 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
-                reg = soc15_get_register_offset(THM_HWID, 0,
-                                mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
-                cgs_write_register(hwmgr->device, reg,
-                                CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+                WREG32_SOC15(THM, 0, mmCG_TACH_STATUS,
+                                REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
                                         CG_TACH_STATUS, TACH_PERIOD,
                                         tach_period));
         }
@@ -350,13 +336,10 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
 */
 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         int temp;
-        uint32_t reg;
 
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmCG_MULT_THERMAL_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);
-
-        temp = cgs_read_register(hwmgr->device, reg);
+        temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
 
         temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
                         CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
@@ -379,11 +362,12 @@ int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
                 struct PP_TemperatureRange *range)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
         int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-        uint32_t val, reg;
+        uint32_t val;
 
         if (low < range->min)
                 low = range->min;
@@ -393,20 +377,17 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
         if (low > high)
                 return -EINVAL;
 
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
-
-        val = cgs_read_register(hwmgr->device, reg);
+        val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
 
-        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
-        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
-        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
+        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
+        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
         val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
                         (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
                         (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
 
-        cgs_write_register(hwmgr->device, reg, val);
+        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
 
         return 0;
 }
@@ -418,21 +399,17 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 */
 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
         if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
-                reg = soc15_get_register_offset(THM_HWID, 0,
-                                mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
-                cgs_write_register(hwmgr->device, reg,
-                        CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+                WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
+                        REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
                                 CG_TACH_CTRL, EDGE_PER_REV,
                                 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
         }
 
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
-        cgs_write_register(hwmgr->device, reg,
-                CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
+        WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+                REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
                         CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
 
         return 0;
@@ -445,9 +422,9 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 */
 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         struct vega10_hwmgr *data = hwmgr->backend;
         uint32_t val = 0;
-        uint32_t reg;
 
         if (data->smu_features[GNLD_FW_CTF].supported) {
                 if (data->smu_features[GNLD_FW_CTF].enabled)
@@ -465,8 +442,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
 
-        reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
-        cgs_write_register(hwmgr->device, reg, val);
+        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
 
         return 0;
 }
@@ -477,8 +453,8 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 */
 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         struct vega10_hwmgr *data = hwmgr->backend;
-        uint32_t reg;
 
         if (data->smu_features[GNLD_FW_CTF].supported) {
                 if (!data->smu_features[GNLD_FW_CTF].enabled)
@@ -493,8 +469,7 @@ int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
                 data->smu_features[GNLD_FW_CTF].enabled = false;
         }
 
-        reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
-        cgs_write_register(hwmgr->device, reg, 0);
+        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 6a85238ae20f..7dca75cdf722 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -34,7 +34,6 @@
 #include "atomfirmware.h"
 #include "cgs_common.h"
 #include "vega12_inc.h"
-#include "pp_soc15.h"
 #include "pppcielanes.h"
 #include "vega12_hwmgr.h"
 #include "vega12_processpptables.h"
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c
index df0fa815cd6e..cfd9e6ccb790 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c
@@ -26,7 +26,7 @@
 #include "vega12_smumgr.h"
 #include "vega12_ppsmc.h"
 #include "vega12_inc.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 #include "pp_debug.h"
 
 static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
@@ -147,13 +147,10 @@ int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
 */
 int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         int temp = 0;
-        uint32_t reg;
 
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmCG_MULT_THERMAL_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);
-
-        temp = cgs_read_register(hwmgr->device, reg);
+        temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
 
         temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
                         CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
@@ -175,11 +172,12 @@ int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
                 struct PP_TemperatureRange *range)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP *
                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
         int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP *
                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-        uint32_t val, reg;
+        uint32_t val;
 
         if (low < range->min)
                 low = range->min;
@@ -189,18 +187,15 @@ static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
         if (low > high)
                 return -EINVAL;
 
-        reg = soc15_get_register_offset(THM_HWID, 0,
-                        mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
-
-        val = cgs_read_register(hwmgr->device, reg);
+        val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
 
-        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
-        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
-        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-        val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
+        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
+        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+        val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 
-        cgs_write_register(hwmgr->device, reg, val);
+        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
 
         return 0;
 }
@@ -212,15 +207,14 @@ static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 */
 static int vega12_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t val = 0;
-        uint32_t reg;
 
         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
 
-        reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
-        cgs_write_register(hwmgr->device, reg, val);
+        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
 
         return 0;
 }
@@ -231,10 +225,9 @@ static int vega12_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 */
 int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
-        reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
-        cgs_write_register(hwmgr->device, reg, 0);
+        WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
deleted file mode 100644
index 214f370c5efd..000000000000
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef PP_SOC15_H
-#define PP_SOC15_H
-
-#include "soc15_hw_ip.h"
-#include "vega10_ip_offset.h"
-
-inline static uint32_t soc15_get_register_offset(
-                uint32_t hw_id,
-                uint32_t inst,
-                uint32_t segment,
-                uint32_t offset)
-{
-        uint32_t reg = 0;
-
-        if (hw_id == THM_HWID)
-                reg = THM_BASE.instance[inst].segment[segment] + offset;
-        else if (hw_id == NBIF_HWID)
-                reg = NBIF_BASE.instance[inst].segment[segment] + offset;
-        else if (hw_id == MP1_HWID)
-                reg = MP1_BASE.instance[inst].segment[segment] + offset;
-        else if (hw_id == DF_HWID)
-                reg = DF_BASE.instance[inst].segment[segment] + offset;
-        else if (hw_id == GC_HWID)
-                reg = GC_BASE.instance[inst].segment[segment] + offset;
-        else if (hw_id == SMUIO_HWID)
-                reg = SMUIO_BASE.instance[inst].segment[segment] + offset;
-        return reg;
-}
-
-#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index bc53f2beda30..9adea7263774 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -23,7 +23,7 @@
 
 #include "smumgr.h"
 #include "smu10_inc.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 #include "smu10_smumgr.h"
 #include "ppatomctrl.h"
 #include "rv_ppsmc.h"
@@ -49,48 +49,41 @@
 
 static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t reg;
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+        reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 
         phm_wait_for_register_unequal(hwmgr, reg,
                         0, MP1_C2PMSG_90__CONTENT_MASK);
 
-        return cgs_read_register(hwmgr->device, reg);
+        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
 
 static int smu10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
                 uint16_t msg)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
-        cgs_write_register(hwmgr->device, reg, msg);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
 
         return 0;
 }
 
 static int smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)
 {
-        uint32_t reg;
-
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
+        struct amdgpu_device *adev = hwmgr->adev;
 
-        return cgs_read_register(hwmgr->device, reg);
+        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
 }
 
 static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
         smu10_wait_for_response(hwmgr);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
-        cgs_write_register(hwmgr->device, reg, 0);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
         smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
 
@@ -104,17 +97,13 @@ static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 static int smu10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
                 uint16_t msg, uint32_t parameter)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
         smu10_wait_for_response(hwmgr);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
-        cgs_write_register(hwmgr->device, reg, 0);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
-        cgs_write_register(hwmgr->device, reg, parameter);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 
         smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 4aafb043bcb0..14ac6d15c7a7 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -23,7 +23,7 @@
 
 #include "smumgr.h"
 #include "vega10_inc.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 #include "vega10_smumgr.h"
 #include "vega10_hwmgr.h"
 #include "vega10_ppsmc.h"
@@ -54,18 +54,13 @@
 
 static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr)
 {
-        uint32_t mp1_fw_flags, reg;
-
-        reg = soc15_get_register_offset(NBIF_HWID, 0,
-                        mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
+        struct amdgpu_device *adev = hwmgr->adev;
+        uint32_t mp1_fw_flags;
 
-        cgs_write_register(hwmgr->device, reg,
+        WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
                         (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
 
-        reg = soc15_get_register_offset(NBIF_HWID, 0,
-                        mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
-
-        mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
+        mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
 
         if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
                 return true;
@@ -81,11 +76,11 @@ static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr)
  */
 static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t reg;
         uint32_t ret;
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+        reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 
         ret = phm_wait_for_register_unequal(hwmgr, reg,
                         0, MP1_C2PMSG_90__CONTENT_MASK);
@@ -93,7 +88,7 @@ static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr)
         if (ret)
                 pr_err("No response from smu\n");
 
-        return cgs_read_register(hwmgr->device, reg);
+        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
 
 /*
@@ -105,11 +100,9 @@ static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr)
 static int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
                 uint16_t msg)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
-        cgs_write_register(hwmgr->device, reg, msg);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
 
         return 0;
 }
@@ -122,14 +115,12 @@ static int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
  */
 static int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t ret;
 
         vega10_wait_for_response(hwmgr);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
-        cgs_write_register(hwmgr->device, reg, 0);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
         vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
 
@@ -150,18 +141,14 @@ static int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 static int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
                 uint16_t msg, uint32_t parameter)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t ret;
 
         vega10_wait_for_response(hwmgr);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
-        cgs_write_register(hwmgr->device, reg, 0);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
-        cgs_write_register(hwmgr->device, reg, parameter);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 
         vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
 
@@ -174,12 +161,9 @@ static int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
 
 static int vega10_get_argument(struct pp_hwmgr *hwmgr)
 {
-        uint32_t reg;
-
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
+        struct amdgpu_device *adev = hwmgr->adev;
 
-        return cgs_read_register(hwmgr->device, reg);
+        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
 }
 
 static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
index 651a3f28734b..7d9b40e8b1bf 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
@@ -23,7 +23,7 @@
 
 #include "smumgr.h"
 #include "vega12_inc.h"
-#include "pp_soc15.h"
+#include "soc15_common.h"
 #include "vega12_smumgr.h"
 #include "vega12_ppsmc.h"
 #include "vega12/smu9_driver_if.h"
@@ -44,18 +44,13 @@
 
 static bool vega12_is_smc_ram_running(struct pp_hwmgr *hwmgr)
 {
-        uint32_t mp1_fw_flags, reg;
+        struct amdgpu_device *adev = hwmgr->adev;
+        uint32_t mp1_fw_flags;
 
-        reg = soc15_get_register_offset(NBIF_HWID, 0,
-                        mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
-
-        cgs_write_register(hwmgr->device, reg,
+        WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
                         (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
 
-        reg = soc15_get_register_offset(NBIF_HWID, 0,
-                        mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
-
-        mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
+        mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
 
         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
                                 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
@@ -72,15 +67,15 @@ static bool vega12_is_smc_ram_running(struct pp_hwmgr *hwmgr)
  */
 static uint32_t vega12_wait_for_response(struct pp_hwmgr *hwmgr)
 {
+        struct amdgpu_device *adev = hwmgr->adev;
         uint32_t reg;
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+        reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 
         phm_wait_for_register_unequal(hwmgr, reg,
                         0, MP1_C2PMSG_90__CONTENT_MASK);
 
-        return cgs_read_register(hwmgr->device, reg);
+        return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
 
 /*
@@ -92,11 +87,9 @@ static uint32_t vega12_wait_for_response(struct pp_hwmgr *hwmgr)
 int vega12_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
                 uint16_t msg)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
-        cgs_write_register(hwmgr->device, reg, msg);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
 
         return 0;
 }
@@ -109,13 +102,11 @@ int vega12_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
  */
 int vega12_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
         vega12_wait_for_response(hwmgr);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
-        cgs_write_register(hwmgr->device, reg, 0);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
         vega12_send_msg_to_smc_without_waiting(hwmgr, msg);
 
@@ -135,17 +126,13 @@ int vega12_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 int vega12_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
                 uint16_t msg, uint32_t parameter)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
         vega12_wait_for_response(hwmgr);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
-        cgs_write_register(hwmgr->device, reg, 0);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
-        cgs_write_register(hwmgr->device, reg, parameter);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 
         vega12_send_msg_to_smc_without_waiting(hwmgr, msg);
 
@@ -166,11 +153,9 @@ int vega12_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
 int vega12_send_msg_to_smc_with_parameter_without_waiting(
                 struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
 {
-        uint32_t reg;
+        struct amdgpu_device *adev = hwmgr->adev;
 
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
-        cgs_write_register(hwmgr->device, reg, parameter);
+        WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, parameter);
 
         return vega12_send_msg_to_smc_without_waiting(hwmgr, msg);
 }
@@ -183,12 +168,9 @@ int vega12_send_msg_to_smc_with_parameter_without_waiting(
  */
 int vega12_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
 {
-        uint32_t reg;
-
-        reg = soc15_get_register_offset(MP1_HWID, 0,
-                        mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
+        struct amdgpu_device *adev = hwmgr->adev;
 
-        *arg = cgs_read_register(hwmgr->device, reg);
+        *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
 
         return 0;
 }