powerpc/8xx: Use SPRG2 instead of DAR for saving r3

We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>

1 files changed, 4 insertions, 5 deletions

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 150d03f79ad8..ba2dc53cd5a1 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -309,7 +309,7 @@ SystemCall:
 
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
-        mtspr   SPRN_DAR, r3
+        mtspr   SPRN_SPRG_SCRATCH2, r3
 #endif
         EXCEPTION_PROLOG_0
 
@@ -362,8 +362,7 @@ InstructionTLBMiss:
 
         /* Restore registers */
 #ifdef CONFIG_8xx_CPU6
-        mfspr   r3, SPRN_DAR
-        mtspr   SPRN_DAR, r11   /* Tag DAR */
+        mfspr   r3, SPRN_SPRG_SCRATCH2
 #endif
         EXCEPTION_EPILOG_0
         rfi
@@ -371,7 +370,7 @@ InstructionTLBMiss:
         . = 0x1200
 DataStoreTLBMiss:
 #ifdef CONFIG_8xx_CPU6
-        mtspr   SPRN_DAR, r3
+        mtspr   SPRN_SPRG_SCRATCH2, r3
 #endif
         EXCEPTION_PROLOG_0
         mfcr    r10
@@ -438,7 +437,7 @@ DataStoreTLBMiss:
 
         /* Restore registers */
 #ifdef CONFIG_8xx_CPU6
-        mfspr   r3, SPRN_DAR
+        mfspr   r3, SPRN_SPRG_SCRATCH2
 #endif
         mtspr   SPRN_DAR, r11   /* Tag DAR */
         EXCEPTION_EPILOG_0