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authorBjorn Helgaas <bhelgaas@google.com>2018-10-20 12:45:47 -0400
committerBjorn Helgaas <bhelgaas@google.com>2018-10-20 12:45:47 -0400
commitb7c18dc06ad12059abc0961522d446553f8a755b (patch)
treed5d94228ffacb6df390e7fa7d92c0901a0665ea4
parent61ce5809570b38710f08ebfcd44a5b067eeee77d (diff)
parent8a3ebd8de328301aacbe328650a59253be2ac82c (diff)
Merge branch 'remotes/lorenzo/pci/controller-misc'
- Remove redundant controller tests for "device_type == pci" (Rob Herring) - Document R-Car E3 (R8A77990) bindings (Tho Vu) - Add device tree support for R-Car r8a7744 (Biju Das) - Drop unused mvebu PCIe capability code (Thomas Petazzoni) - Add shared PCI bridge emulation code (Thomas Petazzoni) - Convert mvebu to use shared PCI bridge emulation (Thomas Petazzoni) - Add aardvark Root Port emulation (Thomas Petazzoni) * remotes/lorenzo/pci/controller-misc: PCI: aardvark: Implement emulated root PCI bridge config space PCI: mvebu: Convert to PCI emulated bridge config space PCI: mvebu: Drop unused PCI express capability code PCI: Introduce PCI bridge emulated config space common logic dt-bindings: PCI: rcar: Add device tree support for r8a7744 dt-bindings: PCI: rcar: Add device tree support for r8a7744 DT: pci: rcar-pci: document R8A77990 bindings PCI: Remove unnecessary check of device_type == pci
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt1
-rw-r--r--Documentation/devicetree/bindings/pci/rcar-pci.txt2
-rw-r--r--drivers/pci/Kconfig3
-rw-r--r--drivers/pci/Makefile1
-rw-r--r--drivers/pci/controller/Kconfig2
-rw-r--r--drivers/pci/controller/pci-aardvark.c129
-rw-r--r--drivers/pci/controller/pci-host-common.c8
-rw-r--r--drivers/pci/controller/pci-mvebu.c384
-rw-r--r--drivers/pci/controller/pcie-cadence-host.c7
-rw-r--r--drivers/pci/controller/pcie-mobiveil.c7
-rw-r--r--drivers/pci/controller/pcie-xilinx-nwl.c9
-rw-r--r--drivers/pci/controller/pcie-xilinx.c7
-rw-r--r--drivers/pci/pci-bridge-emul.c408
-rw-r--r--drivers/pci/pci-bridge-emul.h124
14 files changed, 767 insertions, 325 deletions
diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index 9fe7e12a7bf3..b94078f58d8e 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -7,6 +7,7 @@ OHCI and EHCI controllers.
7 7
8Required properties: 8Required properties:
9- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC; 9- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC;
10 "renesas,pci-r8a7744" for the R8A7744 SoC;
10 "renesas,pci-r8a7745" for the R8A7745 SoC; 11 "renesas,pci-r8a7745" for the R8A7745 SoC;
11 "renesas,pci-r8a7790" for the R8A7790 SoC; 12 "renesas,pci-r8a7790" for the R8A7790 SoC;
12 "renesas,pci-r8a7791" for the R8A7791 SoC; 13 "renesas,pci-r8a7791" for the R8A7791 SoC;
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
index a5f7fc62d10e..976ef7bfff93 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
@@ -2,6 +2,7 @@
2 2
3Required properties: 3Required properties:
4compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; 4compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
5 "renesas,pcie-r8a7744" for the R8A7744 SoC;
5 "renesas,pcie-r8a7779" for the R8A7779 SoC; 6 "renesas,pcie-r8a7779" for the R8A7779 SoC;
6 "renesas,pcie-r8a7790" for the R8A7790 SoC; 7 "renesas,pcie-r8a7790" for the R8A7790 SoC;
7 "renesas,pcie-r8a7791" for the R8A7791 SoC; 8 "renesas,pcie-r8a7791" for the R8A7791 SoC;
@@ -9,6 +10,7 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
9 "renesas,pcie-r8a7795" for the R8A7795 SoC; 10 "renesas,pcie-r8a7795" for the R8A7795 SoC;
10 "renesas,pcie-r8a7796" for the R8A7796 SoC; 11 "renesas,pcie-r8a7796" for the R8A7796 SoC;
11 "renesas,pcie-r8a77980" for the R8A77980 SoC; 12 "renesas,pcie-r8a77980" for the R8A77980 SoC;
13 "renesas,pcie-r8a77990" for the R8A77990 SoC;
12 "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or 14 "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
13 RZ/G1 compatible device. 15 RZ/G1 compatible device.
14 "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. 16 "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index deb68be4fdac..2dcc30429e8b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -98,6 +98,9 @@ config PCI_ECAM
98config PCI_LOCKLESS_CONFIG 98config PCI_LOCKLESS_CONFIG
99 bool 99 bool
100 100
101config PCI_BRIDGE_EMUL
102 bool
103
101config PCI_IOV 104config PCI_IOV
102 bool "PCI IOV support" 105 bool "PCI IOV support"
103 depends on PCI 106 depends on PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 85f4a703b2be..f2bda77a2df1 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_HOTPLUG_PCI) += hotplug/
19obj-$(CONFIG_PCI_MSI) += msi.o 19obj-$(CONFIG_PCI_MSI) += msi.o
20obj-$(CONFIG_PCI_ATS) += ats.o 20obj-$(CONFIG_PCI_ATS) += ats.o
21obj-$(CONFIG_PCI_IOV) += iov.o 21obj-$(CONFIG_PCI_IOV) += iov.o
22obj-$(CONFIG_PCI_BRIDGE_EMUL) += pci-bridge-emul.o
22obj-$(CONFIG_ACPI) += pci-acpi.o 23obj-$(CONFIG_ACPI) += pci-acpi.o
23obj-$(CONFIG_PCI_LABEL) += pci-label.o 24obj-$(CONFIG_PCI_LABEL) += pci-label.o
24obj-$(CONFIG_X86_INTEL_MID) += pci-mid.o 25obj-$(CONFIG_X86_INTEL_MID) += pci-mid.o
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 028b287466fb..5d76ef51532d 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -9,12 +9,14 @@ config PCI_MVEBU
9 depends on MVEBU_MBUS 9 depends on MVEBU_MBUS
10 depends on ARM 10 depends on ARM
11 depends on OF 11 depends on OF
12 select PCI_BRIDGE_EMUL
12 13
13config PCI_AARDVARK 14config PCI_AARDVARK
14 bool "Aardvark PCIe controller" 15 bool "Aardvark PCIe controller"
15 depends on (ARCH_MVEBU && ARM64) || COMPILE_TEST 16 depends on (ARCH_MVEBU && ARM64) || COMPILE_TEST
16 depends on OF 17 depends on OF
17 depends on PCI_MSI_IRQ_DOMAIN 18 depends on PCI_MSI_IRQ_DOMAIN
19 select PCI_BRIDGE_EMUL
18 help 20 help
19 Add support for Aardvark 64bit PCIe Host Controller. This 21 Add support for Aardvark 64bit PCIe Host Controller. This
20 controller is part of the South Bridge of the Marvel Armada 22 controller is part of the South Bridge of the Marvel Armada
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 6b4555ff2548..750081c1cb48 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -20,12 +20,16 @@
20#include <linux/of_pci.h> 20#include <linux/of_pci.h>
21 21
22#include "../pci.h" 22#include "../pci.h"
23#include "../pci-bridge-emul.h"
23 24
24/* PCIe core registers */ 25/* PCIe core registers */
26#define PCIE_CORE_DEV_ID_REG 0x0
25#define PCIE_CORE_CMD_STATUS_REG 0x4 27#define PCIE_CORE_CMD_STATUS_REG 0x4
26#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) 28#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
27#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) 29#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
28#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) 30#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
31#define PCIE_CORE_DEV_REV_REG 0x8
32#define PCIE_CORE_PCIEXP_CAP 0xc0
29#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 33#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
30#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) 34#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
31#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 35#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
@@ -41,7 +45,10 @@
41#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 45#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
42#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 46#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
43#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 47#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
44 48#define PCIE_CORE_INT_A_ASSERT_ENABLE 1
49#define PCIE_CORE_INT_B_ASSERT_ENABLE 2
50#define PCIE_CORE_INT_C_ASSERT_ENABLE 3
51#define PCIE_CORE_INT_D_ASSERT_ENABLE 4
45/* PIO registers base address and register offsets */ 52/* PIO registers base address and register offsets */
46#define PIO_BASE_ADDR 0x4000 53#define PIO_BASE_ADDR 0x4000
47#define PIO_CTRL (PIO_BASE_ADDR + 0x0) 54#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
@@ -93,7 +100,9 @@
93#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 100#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
94#define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 101#define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
95#define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 102#define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
103#define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
96#define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 104#define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
105#define PCIE_MSG_PM_PME_MASK BIT(7)
97#define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 106#define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
98#define PCIE_ISR0_MSI_INT_PENDING BIT(24) 107#define PCIE_ISR0_MSI_INT_PENDING BIT(24)
99#define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 108#define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
@@ -189,6 +198,7 @@ struct advk_pcie {
189 struct mutex msi_used_lock; 198 struct mutex msi_used_lock;
190 u16 msi_msg; 199 u16 msi_msg;
191 int root_bus_nr; 200 int root_bus_nr;
201 struct pci_bridge_emul bridge;
192}; 202};
193 203
194static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 204static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
@@ -390,6 +400,109 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
390 return -ETIMEDOUT; 400 return -ETIMEDOUT;
391} 401}
392 402
403
404static pci_bridge_emul_read_status_t
405advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
406 int reg, u32 *value)
407{
408 struct advk_pcie *pcie = bridge->data;
409
410
411 switch (reg) {
412 case PCI_EXP_SLTCTL:
413 *value = PCI_EXP_SLTSTA_PDS << 16;
414 return PCI_BRIDGE_EMUL_HANDLED;
415
416 case PCI_EXP_RTCTL: {
417 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
418 *value = (val & PCIE_MSG_PM_PME_MASK) ? PCI_EXP_RTCTL_PMEIE : 0;
419 return PCI_BRIDGE_EMUL_HANDLED;
420 }
421
422 case PCI_EXP_RTSTA: {
423 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);
424 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);
425 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16);
426 return PCI_BRIDGE_EMUL_HANDLED;
427 }
428
429 case PCI_CAP_LIST_ID:
430 case PCI_EXP_DEVCAP:
431 case PCI_EXP_DEVCTL:
432 case PCI_EXP_LNKCAP:
433 case PCI_EXP_LNKCTL:
434 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
435 return PCI_BRIDGE_EMUL_HANDLED;
436 default:
437 return PCI_BRIDGE_EMUL_NOT_HANDLED;
438 }
439
440}
441
442static void
443advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
444 int reg, u32 old, u32 new, u32 mask)
445{
446 struct advk_pcie *pcie = bridge->data;
447
448 switch (reg) {
449 case PCI_EXP_DEVCTL:
450 case PCI_EXP_LNKCTL:
451 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
452 break;
453
454 case PCI_EXP_RTCTL:
455 new = (new & PCI_EXP_RTCTL_PMEIE) << 3;
456 advk_writel(pcie, new, PCIE_ISR0_MASK_REG);
457 break;
458
459 case PCI_EXP_RTSTA:
460 new = (new & PCI_EXP_RTSTA_PME) >> 9;
461 advk_writel(pcie, new, PCIE_ISR0_REG);
462 break;
463
464 default:
465 break;
466 }
467}
468
469struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
470 .read_pcie = advk_pci_bridge_emul_pcie_conf_read,
471 .write_pcie = advk_pci_bridge_emul_pcie_conf_write,
472};
473
474/*
475 * Initialize the configuration space of the PCI-to-PCI bridge
476 * associated with the given PCIe interface.
477 */
478static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
479{
480 struct pci_bridge_emul *bridge = &pcie->bridge;
481
482 bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
483 bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
484 bridge->conf.class_revision =
485 advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
486
487 /* Support 32 bits I/O addressing */
488 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
489 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
490
491 /* Support 64 bits memory pref */
492 bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
493 bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
494
495 /* Support interrupt A for MSI feature */
496 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
497
498 bridge->has_pcie = true;
499 bridge->data = pcie;
500 bridge->ops = &advk_pci_bridge_emul_ops;
501
502 pci_bridge_emul_init(bridge);
503
504}
505
393static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 506static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
394 int devfn) 507 int devfn)
395{ 508{
@@ -411,6 +524,10 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
411 return PCIBIOS_DEVICE_NOT_FOUND; 524 return PCIBIOS_DEVICE_NOT_FOUND;
412 } 525 }
413 526
527 if (bus->number == pcie->root_bus_nr)
528 return pci_bridge_emul_conf_read(&pcie->bridge, where,
529 size, val);
530
414 /* Start PIO */ 531 /* Start PIO */
415 advk_writel(pcie, 0, PIO_START); 532 advk_writel(pcie, 0, PIO_START);
416 advk_writel(pcie, 1, PIO_ISR); 533 advk_writel(pcie, 1, PIO_ISR);
@@ -418,7 +535,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
418 /* Program the control register */ 535 /* Program the control register */
419 reg = advk_readl(pcie, PIO_CTRL); 536 reg = advk_readl(pcie, PIO_CTRL);
420 reg &= ~PIO_CTRL_TYPE_MASK; 537 reg &= ~PIO_CTRL_TYPE_MASK;
421 if (bus->number == pcie->root_bus_nr) 538 if (bus->primary == pcie->root_bus_nr)
422 reg |= PCIE_CONFIG_RD_TYPE0; 539 reg |= PCIE_CONFIG_RD_TYPE0;
423 else 540 else
424 reg |= PCIE_CONFIG_RD_TYPE1; 541 reg |= PCIE_CONFIG_RD_TYPE1;
@@ -463,6 +580,10 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
463 if (!advk_pcie_valid_device(pcie, bus, devfn)) 580 if (!advk_pcie_valid_device(pcie, bus, devfn))
464 return PCIBIOS_DEVICE_NOT_FOUND; 581 return PCIBIOS_DEVICE_NOT_FOUND;
465 582
583 if (bus->number == pcie->root_bus_nr)
584 return pci_bridge_emul_conf_write(&pcie->bridge, where,
585 size, val);
586
466 if (where % size) 587 if (where % size)
467 return PCIBIOS_SET_FAILED; 588 return PCIBIOS_SET_FAILED;
468 589
@@ -473,7 +594,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
473 /* Program the control register */ 594 /* Program the control register */
474 reg = advk_readl(pcie, PIO_CTRL); 595 reg = advk_readl(pcie, PIO_CTRL);
475 reg &= ~PIO_CTRL_TYPE_MASK; 596 reg &= ~PIO_CTRL_TYPE_MASK;
476 if (bus->number == pcie->root_bus_nr) 597 if (bus->primary == pcie->root_bus_nr)
477 reg |= PCIE_CONFIG_WR_TYPE0; 598 reg |= PCIE_CONFIG_WR_TYPE0;
478 else 599 else
479 reg |= PCIE_CONFIG_WR_TYPE1; 600 reg |= PCIE_CONFIG_WR_TYPE1;
@@ -875,6 +996,8 @@ static int advk_pcie_probe(struct platform_device *pdev)
875 996
876 advk_pcie_setup_hw(pcie); 997 advk_pcie_setup_hw(pcie);
877 998
999 advk_sw_pci_bridge_init(pcie);
1000
878 ret = advk_pcie_init_irq_domain(pcie); 1001 ret = advk_pcie_init_irq_domain(pcie);
879 if (ret) { 1002 if (ret) {
880 dev_err(dev, "Failed to initialize irq\n"); 1003 dev_err(dev, "Failed to initialize irq\n");
diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c
index d8f10451f273..c742881b5061 100644
--- a/drivers/pci/controller/pci-host-common.c
+++ b/drivers/pci/controller/pci-host-common.c
@@ -58,9 +58,7 @@ err_out:
58int pci_host_common_probe(struct platform_device *pdev, 58int pci_host_common_probe(struct platform_device *pdev,
59 struct pci_ecam_ops *ops) 59 struct pci_ecam_ops *ops)
60{ 60{
61 const char *type;
62 struct device *dev = &pdev->dev; 61 struct device *dev = &pdev->dev;
63 struct device_node *np = dev->of_node;
64 struct pci_host_bridge *bridge; 62 struct pci_host_bridge *bridge;
65 struct pci_config_window *cfg; 63 struct pci_config_window *cfg;
66 struct list_head resources; 64 struct list_head resources;
@@ -70,12 +68,6 @@ int pci_host_common_probe(struct platform_device *pdev,
70 if (!bridge) 68 if (!bridge)
71 return -ENOMEM; 69 return -ENOMEM;
72 70
73 type = of_get_property(np, "device_type", NULL);
74 if (!type || strcmp(type, "pci")) {
75 dev_err(dev, "invalid \"device_type\" %s\n", type);
76 return -EINVAL;
77 }
78
79 of_pci_check_probe_only(); 71 of_pci_check_probe_only();
80 72
81 /* Parse and map our Configuration Space windows */ 73 /* Parse and map our Configuration Space windows */
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index 50eb0729385b..4711ca8fa5d4 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -22,6 +22,7 @@
22#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23 23
24#include "../pci.h" 24#include "../pci.h"
25#include "../pci-bridge-emul.h"
25 26
26/* 27/*
27 * PCIe unit register offsets. 28 * PCIe unit register offsets.
@@ -63,61 +64,6 @@
63#define PCIE_DEBUG_CTRL 0x1a60 64#define PCIE_DEBUG_CTRL 0x1a60
64#define PCIE_DEBUG_SOFT_RESET BIT(20) 65#define PCIE_DEBUG_SOFT_RESET BIT(20)
65 66
66enum {
67 PCISWCAP = PCI_BRIDGE_CONTROL + 2,
68 PCISWCAP_EXP_LIST_ID = PCISWCAP + PCI_CAP_LIST_ID,
69 PCISWCAP_EXP_DEVCAP = PCISWCAP + PCI_EXP_DEVCAP,
70 PCISWCAP_EXP_DEVCTL = PCISWCAP + PCI_EXP_DEVCTL,
71 PCISWCAP_EXP_LNKCAP = PCISWCAP + PCI_EXP_LNKCAP,
72 PCISWCAP_EXP_LNKCTL = PCISWCAP + PCI_EXP_LNKCTL,
73 PCISWCAP_EXP_SLTCAP = PCISWCAP + PCI_EXP_SLTCAP,
74 PCISWCAP_EXP_SLTCTL = PCISWCAP + PCI_EXP_SLTCTL,
75 PCISWCAP_EXP_RTCTL = PCISWCAP + PCI_EXP_RTCTL,
76 PCISWCAP_EXP_RTSTA = PCISWCAP + PCI_EXP_RTSTA,
77 PCISWCAP_EXP_DEVCAP2 = PCISWCAP + PCI_EXP_DEVCAP2,
78 PCISWCAP_EXP_DEVCTL2 = PCISWCAP + PCI_EXP_DEVCTL2,
79 PCISWCAP_EXP_LNKCAP2 = PCISWCAP + PCI_EXP_LNKCAP2,
80 PCISWCAP_EXP_LNKCTL2 = PCISWCAP + PCI_EXP_LNKCTL2,
81 PCISWCAP_EXP_SLTCAP2 = PCISWCAP + PCI_EXP_SLTCAP2,
82 PCISWCAP_EXP_SLTCTL2 = PCISWCAP + PCI_EXP_SLTCTL2,
83};
84
85/* PCI configuration space of a PCI-to-PCI bridge */
86struct mvebu_sw_pci_bridge {
87 u16 vendor;
88 u16 device;
89 u16 command;
90 u16 status;
91 u16 class;
92 u8 interface;
93 u8 revision;
94 u8 bist;
95 u8 header_type;
96 u8 latency_timer;
97 u8 cache_line_size;
98 u32 bar[2];
99 u8 primary_bus;
100 u8 secondary_bus;
101 u8 subordinate_bus;
102 u8 secondary_latency_timer;
103 u8 iobase;
104 u8 iolimit;
105 u16 secondary_status;
106 u16 membase;
107 u16 memlimit;
108 u16 iobaseupper;
109 u16 iolimitupper;
110 u32 romaddr;
111 u8 intline;
112 u8 intpin;
113 u16 bridgectrl;
114
115 /* PCI express capability */
116 u32 pcie_sltcap;
117 u16 pcie_devctl;
118 u16 pcie_rtctl;
119};
120
121struct mvebu_pcie_port; 67struct mvebu_pcie_port;
122 68
123/* Structure representing all PCIe interfaces */ 69/* Structure representing all PCIe interfaces */
@@ -153,7 +99,7 @@ struct mvebu_pcie_port {
153 struct clk *clk; 99 struct clk *clk;
154 struct gpio_desc *reset_gpio; 100 struct gpio_desc *reset_gpio;
155 char *reset_name; 101 char *reset_name;
156 struct mvebu_sw_pci_bridge bridge; 102 struct pci_bridge_emul bridge;
157 struct device_node *dn; 103 struct device_node *dn;
158 struct mvebu_pcie *pcie; 104 struct mvebu_pcie *pcie;
159 struct mvebu_pcie_window memwin; 105 struct mvebu_pcie_window memwin;
@@ -415,11 +361,12 @@ static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
415static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 361static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
416{ 362{
417 struct mvebu_pcie_window desired = {}; 363 struct mvebu_pcie_window desired = {};
364 struct pci_bridge_emul_conf *conf = &port->bridge.conf;
418 365
419 /* Are the new iobase/iolimit values invalid? */ 366 /* Are the new iobase/iolimit values invalid? */
420 if (port->bridge.iolimit < port->bridge.iobase || 367 if (conf->iolimit < conf->iobase ||
421 port->bridge.iolimitupper < port->bridge.iobaseupper || 368 conf->iolimitupper < conf->iobaseupper ||
422 !(port->bridge.command & PCI_COMMAND_IO)) { 369 !(conf->command & PCI_COMMAND_IO)) {
423 mvebu_pcie_set_window(port, port->io_target, port->io_attr, 370 mvebu_pcie_set_window(port, port->io_target, port->io_attr,
424 &desired, &port->iowin); 371 &desired, &port->iowin);
425 return; 372 return;
@@ -438,11 +385,11 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
438 * specifications. iobase is the bus address, port->iowin_base 385 * specifications. iobase is the bus address, port->iowin_base
439 * is the CPU address. 386 * is the CPU address.
440 */ 387 */
441 desired.remap = ((port->bridge.iobase & 0xF0) << 8) | 388 desired.remap = ((conf->iobase & 0xF0) << 8) |
442 (port->bridge.iobaseupper << 16); 389 (conf->iobaseupper << 16);
443 desired.base = port->pcie->io.start + desired.remap; 390 desired.base = port->pcie->io.start + desired.remap;
444 desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | 391 desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) |
445 (port->bridge.iolimitupper << 16)) - 392 (conf->iolimitupper << 16)) -
446 desired.remap) + 393 desired.remap) +
447 1; 394 1;
448 395
@@ -453,10 +400,11 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
453static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 400static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
454{ 401{
455 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP}; 402 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
403 struct pci_bridge_emul_conf *conf = &port->bridge.conf;
456 404
457 /* Are the new membase/memlimit values invalid? */ 405 /* Are the new membase/memlimit values invalid? */
458 if (port->bridge.memlimit < port->bridge.membase || 406 if (conf->memlimit < conf->membase ||
459 !(port->bridge.command & PCI_COMMAND_MEMORY)) { 407 !(conf->command & PCI_COMMAND_MEMORY)) {
460 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, 408 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
461 &desired, &port->memwin); 409 &desired, &port->memwin);
462 return; 410 return;
@@ -468,130 +416,32 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
468 * window to setup, according to the PCI-to-PCI bridge 416 * window to setup, according to the PCI-to-PCI bridge
469 * specifications. 417 * specifications.
470 */ 418 */
471 desired.base = ((port->bridge.membase & 0xFFF0) << 16); 419 desired.base = ((conf->membase & 0xFFF0) << 16);
472 desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - 420 desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) -
473 desired.base + 1; 421 desired.base + 1;
474 422
475 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, 423 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
476 &port->memwin); 424 &port->memwin);
477} 425}
478 426
479/* 427static pci_bridge_emul_read_status_t
480 * Initialize the configuration space of the PCI-to-PCI bridge 428mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
481 * associated with the given PCIe interface. 429 int reg, u32 *value)
482 */
483static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
484{
485 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
486
487 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
488
489 bridge->class = PCI_CLASS_BRIDGE_PCI;
490 bridge->vendor = PCI_VENDOR_ID_MARVELL;
491 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
492 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
493 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
494 bridge->cache_line_size = 0x10;
495
496 /* We support 32 bits I/O addressing */
497 bridge->iobase = PCI_IO_RANGE_TYPE_32;
498 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
499
500 /* Add capabilities */
501 bridge->status = PCI_STATUS_CAP_LIST;
502}
503
504/*
505 * Read the configuration space of the PCI-to-PCI bridge associated to
506 * the given PCIe interface.
507 */
508static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
509 unsigned int where, int size, u32 *value)
510{ 430{
511 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 431 struct mvebu_pcie_port *port = bridge->data;
512
513 switch (where & ~3) {
514 case PCI_VENDOR_ID:
515 *value = bridge->device << 16 | bridge->vendor;
516 break;
517
518 case PCI_COMMAND:
519 *value = bridge->command | bridge->status << 16;
520 break;
521
522 case PCI_CLASS_REVISION:
523 *value = bridge->class << 16 | bridge->interface << 8 |
524 bridge->revision;
525 break;
526
527 case PCI_CACHE_LINE_SIZE:
528 *value = bridge->bist << 24 | bridge->header_type << 16 |
529 bridge->latency_timer << 8 | bridge->cache_line_size;
530 break;
531
532 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
533 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
534 break;
535
536 case PCI_PRIMARY_BUS:
537 *value = (bridge->secondary_latency_timer << 24 |
538 bridge->subordinate_bus << 16 |
539 bridge->secondary_bus << 8 |
540 bridge->primary_bus);
541 break;
542
543 case PCI_IO_BASE:
544 if (!mvebu_has_ioport(port))
545 *value = bridge->secondary_status << 16;
546 else
547 *value = (bridge->secondary_status << 16 |
548 bridge->iolimit << 8 |
549 bridge->iobase);
550 break;
551
552 case PCI_MEMORY_BASE:
553 *value = (bridge->memlimit << 16 | bridge->membase);
554 break;
555
556 case PCI_PREF_MEMORY_BASE:
557 *value = 0;
558 break;
559
560 case PCI_IO_BASE_UPPER16:
561 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
562 break;
563
564 case PCI_CAPABILITY_LIST:
565 *value = PCISWCAP;
566 break;
567
568 case PCI_ROM_ADDRESS1:
569 *value = 0;
570 break;
571 432
572 case PCI_INTERRUPT_LINE: 433 switch (reg) {
573 /* LINE PIN MIN_GNT MAX_LAT */ 434 case PCI_EXP_DEVCAP:
574 *value = 0;
575 break;
576
577 case PCISWCAP_EXP_LIST_ID:
578 /* Set PCIe v2, root port, slot support */
579 *value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
580 PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP;
581 break;
582
583 case PCISWCAP_EXP_DEVCAP:
584 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP); 435 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
585 break; 436 break;
586 437
587 case PCISWCAP_EXP_DEVCTL: 438 case PCI_EXP_DEVCTL:
588 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) & 439 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
589 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | 440 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
590 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); 441 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
591 *value |= bridge->pcie_devctl;
592 break; 442 break;
593 443
594 case PCISWCAP_EXP_LNKCAP: 444 case PCI_EXP_LNKCAP:
595 /* 445 /*
596 * PCIe requires the clock power management capability to be 446 * PCIe requires the clock power management capability to be
597 * hard-wired to zero for downstream ports 447 * hard-wired to zero for downstream ports
@@ -600,176 +450,140 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
600 ~PCI_EXP_LNKCAP_CLKPM; 450 ~PCI_EXP_LNKCAP_CLKPM;
601 break; 451 break;
602 452
603 case PCISWCAP_EXP_LNKCTL: 453 case PCI_EXP_LNKCTL:
604 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); 454 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
605 break; 455 break;
606 456
607 case PCISWCAP_EXP_SLTCAP: 457 case PCI_EXP_SLTCTL:
608 *value = bridge->pcie_sltcap;
609 break;
610
611 case PCISWCAP_EXP_SLTCTL:
612 *value = PCI_EXP_SLTSTA_PDS << 16; 458 *value = PCI_EXP_SLTSTA_PDS << 16;
613 break; 459 break;
614 460
615 case PCISWCAP_EXP_RTCTL: 461 case PCI_EXP_RTSTA:
616 *value = bridge->pcie_rtctl;
617 break;
618
619 case PCISWCAP_EXP_RTSTA:
620 *value = mvebu_readl(port, PCIE_RC_RTSTA); 462 *value = mvebu_readl(port, PCIE_RC_RTSTA);
621 break; 463 break;
622 464
623 /* PCIe requires the v2 fields to be hard-wired to zero */
624 case PCISWCAP_EXP_DEVCAP2:
625 case PCISWCAP_EXP_DEVCTL2:
626 case PCISWCAP_EXP_LNKCAP2:
627 case PCISWCAP_EXP_LNKCTL2:
628 case PCISWCAP_EXP_SLTCAP2:
629 case PCISWCAP_EXP_SLTCTL2:
630 default: 465 default:
631 /* 466 return PCI_BRIDGE_EMUL_NOT_HANDLED;
632 * PCI defines configuration read accesses to reserved or
633 * unimplemented registers to read as zero and complete
634 * normally.
635 */
636 *value = 0;
637 return PCIBIOS_SUCCESSFUL;
638 } 467 }
639 468
640 if (size == 2) 469 return PCI_BRIDGE_EMUL_HANDLED;
641 *value = (*value >> (8 * (where & 3))) & 0xffff;
642 else if (size == 1)
643 *value = (*value >> (8 * (where & 3))) & 0xff;
644
645 return PCIBIOS_SUCCESSFUL;
646} 470}
647 471
648/* Write to the PCI-to-PCI bridge configuration space */ 472static void
649static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, 473mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
650 unsigned int where, int size, u32 value) 474 int reg, u32 old, u32 new, u32 mask)
651{ 475{
652 struct mvebu_sw_pci_bridge *bridge = &port->bridge; 476 struct mvebu_pcie_port *port = bridge->data;
653 u32 mask, reg; 477 struct pci_bridge_emul_conf *conf = &bridge->conf;
654 int err;
655
656 if (size == 4)
657 mask = 0x0;
658 else if (size == 2)
659 mask = ~(0xffff << ((where & 3) * 8));
660 else if (size == 1)
661 mask = ~(0xff << ((where & 3) * 8));
662 else
663 return PCIBIOS_BAD_REGISTER_NUMBER;
664
665 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
666 if (err)
667 return err;
668 478
669 value = (reg & mask) | value << ((where & 3) * 8); 479 switch (reg) {
670
671 switch (where & ~3) {
672 case PCI_COMMAND: 480 case PCI_COMMAND:
673 { 481 {
674 u32 old = bridge->command;
675
676 if (!mvebu_has_ioport(port)) 482 if (!mvebu_has_ioport(port))
677 value &= ~PCI_COMMAND_IO; 483 conf->command &= ~PCI_COMMAND_IO;
678 484
679 bridge->command = value & 0xffff; 485 if ((old ^ new) & PCI_COMMAND_IO)
680 if ((old ^ bridge->command) & PCI_COMMAND_IO)
681 mvebu_pcie_handle_iobase_change(port); 486 mvebu_pcie_handle_iobase_change(port);
682 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) 487 if ((old ^ new) & PCI_COMMAND_MEMORY)
683 mvebu_pcie_handle_membase_change(port); 488 mvebu_pcie_handle_membase_change(port);
684 break;
685 }
686 489
687 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
688 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
689 break; 490 break;
491 }
690 492
691 case PCI_IO_BASE: 493 case PCI_IO_BASE:
692 /* 494 /*
693 * We also keep bit 1 set, it is a read-only bit that 495 * We keep bit 1 set, it is a read-only bit that
694 * indicates we support 32 bits addressing for the 496 * indicates we support 32 bits addressing for the
695 * I/O 497 * I/O
696 */ 498 */
697 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; 499 conf->iobase |= PCI_IO_RANGE_TYPE_32;
698 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; 500 conf->iolimit |= PCI_IO_RANGE_TYPE_32;
699 mvebu_pcie_handle_iobase_change(port); 501 mvebu_pcie_handle_iobase_change(port);
700 break; 502 break;
701 503
702 case PCI_MEMORY_BASE: 504 case PCI_MEMORY_BASE:
703 bridge->membase = value & 0xffff;
704 bridge->memlimit = value >> 16;
705 mvebu_pcie_handle_membase_change(port); 505 mvebu_pcie_handle_membase_change(port);
706 break; 506 break;
707 507
708 case PCI_IO_BASE_UPPER16: 508 case PCI_IO_BASE_UPPER16:
709 bridge->iobaseupper = value & 0xffff;
710 bridge->iolimitupper = value >> 16;
711 mvebu_pcie_handle_iobase_change(port); 509 mvebu_pcie_handle_iobase_change(port);
712 break; 510 break;
713 511
714 case PCI_PRIMARY_BUS: 512 case PCI_PRIMARY_BUS:
715 bridge->primary_bus = value & 0xff; 513 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
716 bridge->secondary_bus = (value >> 8) & 0xff; 514 break;
717 bridge->subordinate_bus = (value >> 16) & 0xff; 515
718 bridge->secondary_latency_timer = (value >> 24) & 0xff; 516 default:
719 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
720 break; 517 break;
518 }
519}
520
521static void
522mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
523 int reg, u32 old, u32 new, u32 mask)
524{
525 struct mvebu_pcie_port *port = bridge->data;
721 526
722 case PCISWCAP_EXP_DEVCTL: 527 switch (reg) {
528 case PCI_EXP_DEVCTL:
723 /* 529 /*
724 * Armada370 data says these bits must always 530 * Armada370 data says these bits must always
725 * be zero when in root complex mode. 531 * be zero when in root complex mode.
726 */ 532 */
727 value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | 533 new &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
728 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); 534 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
729
730 /*
731 * If the mask is 0xffff0000, then we only want to write
732 * the device control register, rather than clearing the
733 * RW1C bits in the device status register. Mask out the
734 * status register bits.
735 */
736 if (mask == 0xffff0000)
737 value &= 0xffff;
738 535
739 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); 536 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
740 break; 537 break;
741 538
742 case PCISWCAP_EXP_LNKCTL: 539 case PCI_EXP_LNKCTL:
743 /* 540 /*
744 * If we don't support CLKREQ, we must ensure that the 541 * If we don't support CLKREQ, we must ensure that the
745 * CLKREQ enable bit always reads zero. Since we haven't 542 * CLKREQ enable bit always reads zero. Since we haven't
746 * had this capability, and it's dependent on board wiring, 543 * had this capability, and it's dependent on board wiring,
747 * disable it for the time being. 544 * disable it for the time being.
748 */ 545 */
749 value &= ~PCI_EXP_LNKCTL_CLKREQ_EN; 546 new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
750 547
751 /* 548 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
752 * If the mask is 0xffff0000, then we only want to write
753 * the link control register, rather than clearing the
754 * RW1C bits in the link status register. Mask out the
755 * RW1C status register bits.
756 */
757 if (mask == 0xffff0000)
758 value &= ~((PCI_EXP_LNKSTA_LABS |
759 PCI_EXP_LNKSTA_LBMS) << 16);
760
761 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
762 break; 549 break;
763 550
764 case PCISWCAP_EXP_RTSTA: 551 case PCI_EXP_RTSTA:
765 mvebu_writel(port, value, PCIE_RC_RTSTA); 552 mvebu_writel(port, new, PCIE_RC_RTSTA);
766 break; 553 break;
554 }
555}
767 556
768 default: 557struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
769 break; 558 .write_base = mvebu_pci_bridge_emul_base_conf_write,
559 .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
560 .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
561};
562
563/*
564 * Initialize the configuration space of the PCI-to-PCI bridge
565 * associated with the given PCIe interface.
566 */
567static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
568{
569 struct pci_bridge_emul *bridge = &port->bridge;
570
571 bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
572 bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
573 bridge->conf.class_revision =
574 mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
575
576 if (mvebu_has_ioport(port)) {
577 /* We support 32 bits I/O addressing */
578 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
579 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
770 } 580 }
771 581
772 return PCIBIOS_SUCCESSFUL; 582 bridge->has_pcie = true;
583 bridge->data = port;
584 bridge->ops = &mvebu_pci_bridge_emul_ops;
585
586 pci_bridge_emul_init(bridge);
773} 587}
774 588
775static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) 589static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
@@ -789,8 +603,8 @@ static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
789 if (bus->number == 0 && port->devfn == devfn) 603 if (bus->number == 0 && port->devfn == devfn)
790 return port; 604 return port;
791 if (bus->number != 0 && 605 if (bus->number != 0 &&
792 bus->number >= port->bridge.secondary_bus && 606 bus->number >= port->bridge.conf.secondary_bus &&
793 bus->number <= port->bridge.subordinate_bus) 607 bus->number <= port->bridge.conf.subordinate_bus)
794 return port; 608 return port;
795 } 609 }
796 610
@@ -811,7 +625,8 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
811 625
812 /* Access the emulated PCI-to-PCI bridge */ 626 /* Access the emulated PCI-to-PCI bridge */
813 if (bus->number == 0) 627 if (bus->number == 0)
814 return mvebu_sw_pci_bridge_write(port, where, size, val); 628 return pci_bridge_emul_conf_write(&port->bridge, where,
629 size, val);
815 630
816 if (!mvebu_pcie_link_up(port)) 631 if (!mvebu_pcie_link_up(port))
817 return PCIBIOS_DEVICE_NOT_FOUND; 632 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -839,7 +654,8 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
839 654
840 /* Access the emulated PCI-to-PCI bridge */ 655 /* Access the emulated PCI-to-PCI bridge */
841 if (bus->number == 0) 656 if (bus->number == 0)
842 return mvebu_sw_pci_bridge_read(port, where, size, val); 657 return pci_bridge_emul_conf_read(&port->bridge, where,
658 size, val);
843 659
844 if (!mvebu_pcie_link_up(port)) { 660 if (!mvebu_pcie_link_up(port)) {
845 *val = 0xffffffff; 661 *val = 0xffffffff;
@@ -1253,7 +1069,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
1253 1069
1254 mvebu_pcie_setup_hw(port); 1070 mvebu_pcie_setup_hw(port);
1255 mvebu_pcie_set_local_dev_nr(port, 1); 1071 mvebu_pcie_set_local_dev_nr(port, 1);
1256 mvebu_sw_pci_bridge_init(port); 1072 mvebu_pci_bridge_emul_init(port);
1257 } 1073 }
1258 1074
1259 pcie->nports = i; 1075 pcie->nports = i;
diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
index ec394f6a19c8..97e251090b4f 100644
--- a/drivers/pci/controller/pcie-cadence-host.c
+++ b/drivers/pci/controller/pcie-cadence-host.c
@@ -235,7 +235,6 @@ static int cdns_pcie_host_init(struct device *dev,
235 235
236static int cdns_pcie_host_probe(struct platform_device *pdev) 236static int cdns_pcie_host_probe(struct platform_device *pdev)
237{ 237{
238 const char *type;
239 struct device *dev = &pdev->dev; 238 struct device *dev = &pdev->dev;
240 struct device_node *np = dev->of_node; 239 struct device_node *np = dev->of_node;
241 struct pci_host_bridge *bridge; 240 struct pci_host_bridge *bridge;
@@ -268,12 +267,6 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
268 rc->device_id = 0xffff; 267 rc->device_id = 0xffff;
269 of_property_read_u16(np, "device-id", &rc->device_id); 268 of_property_read_u16(np, "device-id", &rc->device_id);
270 269
271 type = of_get_property(np, "device_type", NULL);
272 if (!type || strcmp(type, "pci")) {
273 dev_err(dev, "invalid \"device_type\" %s\n", type);
274 return -EINVAL;
275 }
276
277 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg"); 270 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
278 pcie->reg_base = devm_ioremap_resource(dev, res); 271 pcie->reg_base = devm_ioremap_resource(dev, res);
279 if (IS_ERR(pcie->reg_base)) { 272 if (IS_ERR(pcie->reg_base)) {
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index a939e8d31735..77052a0712d0 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -301,13 +301,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
301 struct platform_device *pdev = pcie->pdev; 301 struct platform_device *pdev = pcie->pdev;
302 struct device_node *node = dev->of_node; 302 struct device_node *node = dev->of_node;
303 struct resource *res; 303 struct resource *res;
304 const char *type;
305
306 type = of_get_property(node, "device_type", NULL);
307 if (!type || strcmp(type, "pci")) {
308 dev_err(dev, "invalid \"device_type\" %s\n", type);
309 return -EINVAL;
310 }
311 304
312 /* map config resource */ 305 /* map config resource */
313 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 306 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index fb32840ce8e6..81538d77f790 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -777,16 +777,7 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
777 struct platform_device *pdev) 777 struct platform_device *pdev)
778{ 778{
779 struct device *dev = pcie->dev; 779 struct device *dev = pcie->dev;
780 struct device_node *node = dev->of_node;
781 struct resource *res; 780 struct resource *res;
782 const char *type;
783
784 /* Check for device type */
785 type = of_get_property(node, "device_type", NULL);
786 if (!type || strcmp(type, "pci")) {
787 dev_err(dev, "invalid \"device_type\" %s\n", type);
788 return -EINVAL;
789 }
790 781
791 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); 782 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
792 pcie->breg_base = devm_ioremap_resource(dev, res); 783 pcie->breg_base = devm_ioremap_resource(dev, res);
diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c
index 7b1389d8e2a5..9bd1a35cd5d8 100644
--- a/drivers/pci/controller/pcie-xilinx.c
+++ b/drivers/pci/controller/pcie-xilinx.c
@@ -574,15 +574,8 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
574 struct device *dev = port->dev; 574 struct device *dev = port->dev;
575 struct device_node *node = dev->of_node; 575 struct device_node *node = dev->of_node;
576 struct resource regs; 576 struct resource regs;
577 const char *type;
578 int err; 577 int err;
579 578
580 type = of_get_property(node, "device_type", NULL);
581 if (!type || strcmp(type, "pci")) {
582 dev_err(dev, "invalid \"device_type\" %s\n", type);
583 return -EINVAL;
584 }
585
586 err = of_address_to_resource(node, 0, &regs); 579 err = of_address_to_resource(node, 0, &regs);
587 if (err) { 580 if (err) {
588 dev_err(dev, "missing \"reg\" property\n"); 581 dev_err(dev, "missing \"reg\" property\n");
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
new file mode 100644
index 000000000000..129738362d90
--- /dev/null
+++ b/drivers/pci/pci-bridge-emul.c
@@ -0,0 +1,408 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Marvell
4 *
5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
6 *
7 * This file helps PCI controller drivers implement a fake root port
8 * PCI bridge when the HW doesn't provide such a root port PCI
9 * bridge.
10 *
11 * It emulates a PCI bridge by providing a fake PCI configuration
12 * space (and optionally a PCIe capability configuration space) in
13 * memory. By default the read/write operations simply read and update
14 * this fake configuration space in memory. However, PCI controller
15 * drivers can provide through the 'struct pci_sw_bridge_ops'
16 * structure a set of operations to override or complement this
17 * default behavior.
18 */
19
20#include <linux/pci.h>
21#include "pci-bridge-emul.h"
22
23#define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
24#define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
25#define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
26
27/*
28 * Initialize a pci_bridge_emul structure to represent a fake PCI
29 * bridge configuration space. The caller needs to have initialized
30 * the PCI configuration space with whatever values make sense
31 * (typically at least vendor, device, revision), the ->ops pointer,
32 * and optionally ->data and ->has_pcie.
33 */
34void pci_bridge_emul_init(struct pci_bridge_emul *bridge)
35{
36 bridge->conf.class_revision |= PCI_CLASS_BRIDGE_PCI << 16;
37 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
38 bridge->conf.cache_line_size = 0x10;
39 bridge->conf.status = PCI_STATUS_CAP_LIST;
40
41 if (bridge->has_pcie) {
42 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
43 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
44 /* Set PCIe v2, root port, slot support */
45 bridge->pcie_conf.cap = PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
46 PCI_EXP_FLAGS_SLOT;
47 }
48}
49
50struct pci_bridge_reg_behavior {
51 /* Read-only bits */
52 u32 ro;
53
54 /* Read-write bits */
55 u32 rw;
56
57 /* Write-1-to-clear bits */
58 u32 w1c;
59
60 /* Reserved bits (hardwired to 0) */
61 u32 rsvd;
62};
63
64const static struct pci_bridge_reg_behavior pci_regs_behavior[] = {
65 [PCI_VENDOR_ID / 4] = { .ro = ~0 },
66 [PCI_COMMAND / 4] = {
67 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
68 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
69 PCI_COMMAND_SERR),
70 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
71 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
72 PCI_COMMAND_FAST_BACK) |
73 (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
74 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
75 .rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16),
76 .w1c = (PCI_STATUS_PARITY |
77 PCI_STATUS_SIG_TARGET_ABORT |
78 PCI_STATUS_REC_TARGET_ABORT |
79 PCI_STATUS_REC_MASTER_ABORT |
80 PCI_STATUS_SIG_SYSTEM_ERROR |
81 PCI_STATUS_DETECTED_PARITY) << 16,
82 },
83 [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
84
85 /*
86 * Cache Line Size register: implement as read-only, we do not
87 * pretend implementing "Memory Write and Invalidate"
88 * transactions"
89 *
90 * Latency Timer Register: implemented as read-only, as "A
91 * bridge that is not capable of a burst transfer of more than
92 * two data phases on its primary interface is permitted to
93 * hardwire the Latency Timer to a value of 16 or less"
94 *
95 * Header Type: always read-only
96 *
97 * BIST register: implemented as read-only, as "A bridge that
98 * does not support BIST must implement this register as a
99 * read-only register that returns 0 when read"
100 */
101 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
102
103 /*
104 * Base Address registers not used must be implemented as
105 * read-only registers that return 0 when read.
106 */
107 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
108 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
109
110 [PCI_PRIMARY_BUS / 4] = {
111 /* Primary, secondary and subordinate bus are RW */
112 .rw = GENMASK(24, 0),
113 /* Secondary latency is read-only */
114 .ro = GENMASK(31, 24),
115 },
116
117 [PCI_IO_BASE / 4] = {
118 /* The high four bits of I/O base/limit are RW */
119 .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
120
121 /* The low four bits of I/O base/limit are RO */
122 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
123 PCI_STATUS_DEVSEL_MASK) << 16) |
124 GENMASK(11, 8) | GENMASK(3, 0)),
125
126 .w1c = (PCI_STATUS_PARITY |
127 PCI_STATUS_SIG_TARGET_ABORT |
128 PCI_STATUS_REC_TARGET_ABORT |
129 PCI_STATUS_REC_MASTER_ABORT |
130 PCI_STATUS_SIG_SYSTEM_ERROR |
131 PCI_STATUS_DETECTED_PARITY) << 16,
132
133 .rsvd = ((BIT(6) | GENMASK(4, 0)) << 16),
134 },
135
136 [PCI_MEMORY_BASE / 4] = {
137 /* The high 12-bits of mem base/limit are RW */
138 .rw = GENMASK(31, 20) | GENMASK(15, 4),
139
140 /* The low four bits of mem base/limit are RO */
141 .ro = GENMASK(19, 16) | GENMASK(3, 0),
142 },
143
144 [PCI_PREF_MEMORY_BASE / 4] = {
145 /* The high 12-bits of pref mem base/limit are RW */
146 .rw = GENMASK(31, 20) | GENMASK(15, 4),
147
148 /* The low four bits of pref mem base/limit are RO */
149 .ro = GENMASK(19, 16) | GENMASK(3, 0),
150 },
151
152 [PCI_PREF_BASE_UPPER32 / 4] = {
153 .rw = ~0,
154 },
155
156 [PCI_PREF_LIMIT_UPPER32 / 4] = {
157 .rw = ~0,
158 },
159
160 [PCI_IO_BASE_UPPER16 / 4] = {
161 .rw = ~0,
162 },
163
164 [PCI_CAPABILITY_LIST / 4] = {
165 .ro = GENMASK(7, 0),
166 .rsvd = GENMASK(31, 8),
167 },
168
169 [PCI_ROM_ADDRESS1 / 4] = {
170 .rw = GENMASK(31, 11) | BIT(0),
171 .rsvd = GENMASK(10, 1),
172 },
173
174 /*
175 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
176 * are RO, and bridge control (31:16) are a mix of RW, RO,
177 * reserved and W1C bits
178 */
179 [PCI_INTERRUPT_LINE / 4] = {
180 /* Interrupt line is RW */
181 .rw = (GENMASK(7, 0) |
182 ((PCI_BRIDGE_CTL_PARITY |
183 PCI_BRIDGE_CTL_SERR |
184 PCI_BRIDGE_CTL_ISA |
185 PCI_BRIDGE_CTL_VGA |
186 PCI_BRIDGE_CTL_MASTER_ABORT |
187 PCI_BRIDGE_CTL_BUS_RESET |
188 BIT(8) | BIT(9) | BIT(11)) << 16)),
189
190 /* Interrupt pin is RO */
191 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
192
193 .w1c = BIT(10) << 16,
194
195 .rsvd = (GENMASK(15, 12) | BIT(4)) << 16,
196 },
197};
198
199const static struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
200 [PCI_CAP_LIST_ID / 4] = {
201 /*
202 * Capability ID, Next Capability Pointer and
203 * Capabilities register are all read-only.
204 */
205 .ro = ~0,
206 },
207
208 [PCI_EXP_DEVCAP / 4] = {
209 .ro = ~0,
210 },
211
212 [PCI_EXP_DEVCTL / 4] = {
213 /* Device control register is RW */
214 .rw = GENMASK(15, 0),
215
216 /*
217 * Device status register has 4 bits W1C, then 2 bits
218 * RO, the rest is reserved
219 */
220 .w1c = GENMASK(19, 16),
221 .ro = GENMASK(20, 19),
222 .rsvd = GENMASK(31, 21),
223 },
224
225 [PCI_EXP_LNKCAP / 4] = {
226 /* All bits are RO, except bit 23 which is reserved */
227 .ro = lower_32_bits(~BIT(23)),
228 .rsvd = BIT(23),
229 },
230
231 [PCI_EXP_LNKCTL / 4] = {
232 /*
233 * Link control has bits [1:0] and [11:3] RW, the
234 * other bits are reserved.
235 * Link status has bits [13:0] RO, and bits [14:15]
236 * W1C.
237 */
238 .rw = GENMASK(11, 3) | GENMASK(1, 0),
239 .ro = GENMASK(13, 0) << 16,
240 .w1c = GENMASK(15, 14) << 16,
241 .rsvd = GENMASK(15, 12) | BIT(2),
242 },
243
244 [PCI_EXP_SLTCAP / 4] = {
245 .ro = ~0,
246 },
247
248 [PCI_EXP_SLTCTL / 4] = {
249 /*
250 * Slot control has bits [12:0] RW, the rest is
251 * reserved.
252 *
253 * Slot status has a mix of W1C and RO bits, as well
254 * as reserved bits.
255 */
256 .rw = GENMASK(12, 0),
257 .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
258 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
259 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
260 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
261 PCI_EXP_SLTSTA_EIS) << 16,
262 .rsvd = GENMASK(15, 12) | (GENMASK(15, 9) << 16),
263 },
264
265 [PCI_EXP_RTCTL / 4] = {
266 /*
267 * Root control has bits [4:0] RW, the rest is
268 * reserved.
269 *
270 * Root status has bit 0 RO, the rest is reserved.
271 */
272 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
273 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
274 PCI_EXP_RTCTL_CRSSVE),
275 .ro = PCI_EXP_RTCAP_CRSVIS << 16,
276 .rsvd = GENMASK(15, 5) | (GENMASK(15, 1) << 16),
277 },
278
279 [PCI_EXP_RTSTA / 4] = {
280 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
281 .w1c = PCI_EXP_RTSTA_PME,
282 .rsvd = GENMASK(31, 18),
283 },
284};
285
286/*
287 * Should be called by the PCI controller driver when reading the PCI
288 * configuration space of the fake bridge. It will call back the
289 * ->ops->read_base or ->ops->read_pcie operations.
290 */
291int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
292 int size, u32 *value)
293{
294 int ret;
295 int reg = where & ~3;
296 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
297 int reg, u32 *value);
298 u32 *cfgspace;
299 const struct pci_bridge_reg_behavior *behavior;
300
301 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
302 *value = 0;
303 return PCIBIOS_SUCCESSFUL;
304 }
305
306 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
307 *value = 0;
308 return PCIBIOS_SUCCESSFUL;
309 }
310
311 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
312 reg -= PCI_CAP_PCIE_START;
313 read_op = bridge->ops->read_pcie;
314 cfgspace = (u32 *) &bridge->pcie_conf;
315 behavior = pcie_cap_regs_behavior;
316 } else {
317 read_op = bridge->ops->read_base;
318 cfgspace = (u32 *) &bridge->conf;
319 behavior = pci_regs_behavior;
320 }
321
322 if (read_op)
323 ret = read_op(bridge, reg, value);
324 else
325 ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
326
327 if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
328 *value = cfgspace[reg / 4];
329
330 /*
331 * Make sure we never return any reserved bit with a value
332 * different from 0.
333 */
334 *value &= ~behavior[reg / 4].rsvd;
335
336 if (size == 1)
337 *value = (*value >> (8 * (where & 3))) & 0xff;
338 else if (size == 2)
339 *value = (*value >> (8 * (where & 3))) & 0xffff;
340 else if (size != 4)
341 return PCIBIOS_BAD_REGISTER_NUMBER;
342
343 return PCIBIOS_SUCCESSFUL;
344}
345
346/*
347 * Should be called by the PCI controller driver when writing the PCI
348 * configuration space of the fake bridge. It will call back the
349 * ->ops->write_base or ->ops->write_pcie operations.
350 */
351int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
352 int size, u32 value)
353{
354 int reg = where & ~3;
355 int mask, ret, old, new, shift;
356 void (*write_op)(struct pci_bridge_emul *bridge, int reg,
357 u32 old, u32 new, u32 mask);
358 u32 *cfgspace;
359 const struct pci_bridge_reg_behavior *behavior;
360
361 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
362 return PCIBIOS_SUCCESSFUL;
363
364 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
365 return PCIBIOS_SUCCESSFUL;
366
367 shift = (where & 0x3) * 8;
368
369 if (size == 4)
370 mask = 0xffffffff;
371 else if (size == 2)
372 mask = 0xffff << shift;
373 else if (size == 1)
374 mask = 0xff << shift;
375 else
376 return PCIBIOS_BAD_REGISTER_NUMBER;
377
378 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
379 if (ret != PCIBIOS_SUCCESSFUL)
380 return ret;
381
382 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
383 reg -= PCI_CAP_PCIE_START;
384 write_op = bridge->ops->write_pcie;
385 cfgspace = (u32 *) &bridge->pcie_conf;
386 behavior = pcie_cap_regs_behavior;
387 } else {
388 write_op = bridge->ops->write_base;
389 cfgspace = (u32 *) &bridge->conf;
390 behavior = pci_regs_behavior;
391 }
392
393 /* Keep all bits, except the RW bits */
394 new = old & (~mask | ~behavior[reg / 4].rw);
395
396 /* Update the value of the RW bits */
397 new |= (value << shift) & (behavior[reg / 4].rw & mask);
398
399 /* Clear the W1C bits */
400 new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
401
402 cfgspace[reg / 4] = new;
403
404 if (write_op)
405 write_op(bridge, reg, old, new, mask);
406
407 return PCIBIOS_SUCCESSFUL;
408}
diff --git a/drivers/pci/pci-bridge-emul.h b/drivers/pci/pci-bridge-emul.h
new file mode 100644
index 000000000000..9d510ccf738b
--- /dev/null
+++ b/drivers/pci/pci-bridge-emul.h
@@ -0,0 +1,124 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __PCI_BRIDGE_EMUL_H__
3#define __PCI_BRIDGE_EMUL_H__
4
5#include <linux/kernel.h>
6
7/* PCI configuration space of a PCI-to-PCI bridge. */
8struct pci_bridge_emul_conf {
9 u16 vendor;
10 u16 device;
11 u16 command;
12 u16 status;
13 u32 class_revision;
14 u8 cache_line_size;
15 u8 latency_timer;
16 u8 header_type;
17 u8 bist;
18 u32 bar[2];
19 u8 primary_bus;
20 u8 secondary_bus;
21 u8 subordinate_bus;
22 u8 secondary_latency_timer;
23 u8 iobase;
24 u8 iolimit;
25 u16 secondary_status;
26 u16 membase;
27 u16 memlimit;
28 u16 pref_mem_base;
29 u16 pref_mem_limit;
30 u32 prefbaseupper;
31 u32 preflimitupper;
32 u16 iobaseupper;
33 u16 iolimitupper;
34 u8 capabilities_pointer;
35 u8 reserve[3];
36 u32 romaddr;
37 u8 intline;
38 u8 intpin;
39 u16 bridgectrl;
40};
41
42/* PCI configuration space of the PCIe capabilities */
43struct pci_bridge_emul_pcie_conf {
44 u8 cap_id;
45 u8 next;
46 u16 cap;
47 u32 devcap;
48 u16 devctl;
49 u16 devsta;
50 u32 lnkcap;
51 u16 lnkctl;
52 u16 lnksta;
53 u32 slotcap;
54 u16 slotctl;
55 u16 slotsta;
56 u16 rootctl;
57 u16 rsvd;
58 u32 rootsta;
59 u32 devcap2;
60 u16 devctl2;
61 u16 devsta2;
62 u32 lnkcap2;
63 u16 lnkctl2;
64 u16 lnksta2;
65 u32 slotcap2;
66 u16 slotctl2;
67 u16 slotsta2;
68};
69
70struct pci_bridge_emul;
71
72typedef enum { PCI_BRIDGE_EMUL_HANDLED,
73 PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;
74
75struct pci_bridge_emul_ops {
76 /*
77 * Called when reading from the regular PCI bridge
78 * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
79 * operation has handled the read operation and filled in the
80 * *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should
81 * be emulated by the common code by reading from the
82 * in-memory copy of the configuration space.
83 */
84 pci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *bridge,
85 int reg, u32 *value);
86
87 /*
88 * Same as ->read_base(), except it is for reading from the
89 * PCIe capability configuration space.
90 */
91 pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
92 int reg, u32 *value);
93 /*
94 * Called when writing to the regular PCI bridge configuration
95 * space. old is the current value, new is the new value being
96 * written, and mask indicates which parts of the value are
97 * being changed.
98 */
99 void (*write_base)(struct pci_bridge_emul *bridge, int reg,
100 u32 old, u32 new, u32 mask);
101
102 /*
103 * Same as ->write_base(), except it is for writing from the
104 * PCIe capability configuration space.
105 */
106 void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
107 u32 old, u32 new, u32 mask);
108};
109
110struct pci_bridge_emul {
111 struct pci_bridge_emul_conf conf;
112 struct pci_bridge_emul_pcie_conf pcie_conf;
113 struct pci_bridge_emul_ops *ops;
114 void *data;
115 bool has_pcie;
116};
117
118void pci_bridge_emul_init(struct pci_bridge_emul *bridge);
119int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
120 int size, u32 *value);
121int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
122 int size, u32 value);
123
124#endif /* __PCI_BRIDGE_EMUL_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 12:49:51 -0400