Merge tag 'drm-fixes-for-v4.14-rc2' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
 "amdkfd, i915 and exynos fixes.

  I've ended up on unplanned + planned leave this week, but there were
  some fixes I decided to dequeue, some amdkfd bits missed the next pull
  but they are pretty trivial, so I included them.

  I'm not sure I'll see much else for rc2, lots of people are at XDC"

* tag 'drm-fixes-for-v4.14-rc2' of git://people.freedesktop.org/~airlied/linux:
  drm/exynos/hdmi: Fix unsafe list iteration
  drm: exynos: include linux/irq.h
  drm/exynos: Fix suspend/resume support
  drm/exynos: Fix locking in the suspend/resume paths
  drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos()
  drm/i915/cnp: set min brightness from VBT
  Revert "drm/i915/bxt: Disable device ready before shutdown command"
  drm/i915/bxt: set min brightness from VBT
  drm/i915: Fix an error handling in 'intel_framebuffer_init()'
  drm/i915/gvt: Fix incorrect PCI BARs reporting
  drm/amdkfd: pass queue's mqd when destroying mqd
  drm/amdkfd: remove memset before memcpy
  uapi linux/kfd_ioctl.h: only use __u32 and __u64

14 files changed, 195 insertions, 195 deletions

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 681b639f5133..0649dd43e780 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -183,7 +183,7 @@ static void uninitialize(struct kernel_queue *kq)
 {
         if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
                 kq->mqd->destroy_mqd(kq->mqd,
-                                        NULL,
+                                        kq->queue->mqd,
                                         false,
                                         QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
                                         kq->queue->pipe,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 1cae95e2b13a..03bec765b03d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -143,7 +143,6 @@ int pqm_create_queue(struct process_queue_manager *pqm,
         int num_queues = 0;
         struct queue *cur;
 
-        memset(&q_properties, 0, sizeof(struct queue_properties));
         memcpy(&q_properties, properties, sizeof(struct queue_properties));
         q = NULL;
         kq = NULL;
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 730b8d9db187..6be5b53c3b27 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -14,6 +14,7 @@
 #include <linux/clk.h>
 #include <linux/component.h>
 #include <linux/iopoll.h>
+#include <linux/irq.h>
 #include <linux/mfd/syscon.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index b1f7299600f0..e651a58c18cf 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -168,23 +168,19 @@ static struct drm_driver exynos_drm_driver = {
 static int exynos_drm_suspend(struct device *dev)
 {
         struct drm_device *drm_dev = dev_get_drvdata(dev);
-        struct drm_connector *connector;
-        struct drm_connector_list_iter conn_iter;
+        struct exynos_drm_private *private = drm_dev->dev_private;
 
         if (pm_runtime_suspended(dev) || !drm_dev)
                 return 0;
 
-        drm_connector_list_iter_begin(drm_dev, &conn_iter);
-        drm_for_each_connector_iter(connector, &conn_iter) {
-                int old_dpms = connector->dpms;
-
-                if (connector->funcs->dpms)
-                        connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
-
-                /* Set the old mode back to the connector for resume */
-                connector->dpms = old_dpms;
+        drm_kms_helper_poll_disable(drm_dev);
+        exynos_drm_fbdev_suspend(drm_dev);
+        private->suspend_state = drm_atomic_helper_suspend(drm_dev);
+        if (IS_ERR(private->suspend_state)) {
+                exynos_drm_fbdev_resume(drm_dev);
+                drm_kms_helper_poll_enable(drm_dev);
+                return PTR_ERR(private->suspend_state);
         }
-        drm_connector_list_iter_end(&conn_iter);
 
         return 0;
 }
@@ -192,22 +188,14 @@ static int exynos_drm_suspend(struct device *dev)
 static int exynos_drm_resume(struct device *dev)
 {
         struct drm_device *drm_dev = dev_get_drvdata(dev);
-        struct drm_connector *connector;
-        struct drm_connector_list_iter conn_iter;
+        struct exynos_drm_private *private = drm_dev->dev_private;
 
         if (pm_runtime_suspended(dev) || !drm_dev)
                 return 0;
 
-        drm_connector_list_iter_begin(drm_dev, &conn_iter);
-        drm_for_each_connector_iter(connector, &conn_iter) {
-                if (connector->funcs->dpms) {
-                        int dpms = connector->dpms;
-
-                        connector->dpms = DRM_MODE_DPMS_OFF;
-                        connector->funcs->dpms(connector, dpms);
-                }
-        }
-        drm_connector_list_iter_end(&conn_iter);
+        drm_atomic_helper_resume(drm_dev, private->suspend_state);
+        exynos_drm_fbdev_resume(drm_dev);
+        drm_kms_helper_poll_enable(drm_dev);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index cf131c2aa23e..f8bae4cb4823 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -202,6 +202,7 @@ struct drm_exynos_file_private {
  */
 struct exynos_drm_private {
         struct drm_fb_helper *fb_helper;
+        struct drm_atomic_state *suspend_state;
 
         struct device *dma_dev;
         void *mapping;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index c3a068409b48..dfb66ecf417b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -18,6 +18,8 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/exynos_drm.h>
 
+#include <linux/console.h>
+
 #include "exynos_drm_drv.h"
 #include "exynos_drm_fb.h"
 #include "exynos_drm_fbdev.h"
@@ -285,3 +287,21 @@ void exynos_drm_output_poll_changed(struct drm_device *dev)
 
         drm_fb_helper_hotplug_event(fb_helper);
 }
+
+void exynos_drm_fbdev_suspend(struct drm_device *dev)
+{
+        struct exynos_drm_private *private = dev->dev_private;
+
+        console_lock();
+        drm_fb_helper_set_suspend(private->fb_helper, 1);
+        console_unlock();
+}
+
+void exynos_drm_fbdev_resume(struct drm_device *dev)
+{
+        struct exynos_drm_private *private = dev->dev_private;
+
+        console_lock();
+        drm_fb_helper_set_suspend(private->fb_helper, 0);
+        console_unlock();
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
index 330eef87f718..645d1bb7f665 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.h
@@ -21,6 +21,8 @@ int exynos_drm_fbdev_init(struct drm_device *dev);
 void exynos_drm_fbdev_fini(struct drm_device *dev);
 void exynos_drm_fbdev_restore_mode(struct drm_device *dev);
 void exynos_drm_output_poll_changed(struct drm_device *dev);
+void exynos_drm_fbdev_suspend(struct drm_device *drm);
+void exynos_drm_fbdev_resume(struct drm_device *drm);
 
 #else
 
@@ -39,6 +41,14 @@ static inline void exynos_drm_fbdev_restore_mode(struct drm_device *dev)
 
 #define exynos_drm_output_poll_changed (NULL)
 
+static inline void exynos_drm_fbdev_suspend(struct drm_device *drm)
+{
+}
+
+static inline void exynos_drm_fbdev_resume(struct drm_device *drm)
+{
+}
+
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 214fa5e51963..0109ff40b1db 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -944,22 +944,27 @@ static bool hdmi_mode_fixup(struct drm_encoder *encoder,
         struct drm_device *dev = encoder->dev;
         struct drm_connector *connector;
         struct drm_display_mode *m;
+        struct drm_connector_list_iter conn_iter;
         int mode_ok;
 
         drm_mode_set_crtcinfo(adjusted_mode, 0);
 
-        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+        drm_connector_list_iter_begin(dev, &conn_iter);
+        drm_for_each_connector_iter(connector, &conn_iter) {
                 if (connector->encoder == encoder)
                         break;
         }
+        if (connector)
+                drm_connector_get(connector);
+        drm_connector_list_iter_end(&conn_iter);
 
-        if (connector->encoder != encoder)
+        if (!connector)
                 return true;
 
         mode_ok = hdmi_mode_valid(connector, adjusted_mode);
 
         if (mode_ok == MODE_OK)
-                return true;
+                goto cleanup;
 
         /*
          * Find the most suitable mode and copy it to adjusted_mode.
@@ -979,6 +984,9 @@ static bool hdmi_mode_fixup(struct drm_encoder *encoder,
                 }
         }
 
+cleanup:
+        drm_connector_put(connector);
+
         return true;
 }
 
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
index 40af17ec6312..ff3154fe6588 100644
--- a/drivers/gpu/drm/i915/gvt/cfg_space.c
+++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
@@ -197,78 +197,65 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu,
 static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
         void *p_data, unsigned int bytes)
 {
-        unsigned int bar_index =
-                (rounddown(offset, 8) % PCI_BASE_ADDRESS_0) / 8;
         u32 new = *(u32 *)(p_data);
         bool lo = IS_ALIGNED(offset, 8);
         u64 size;
         int ret = 0;
         bool mmio_enabled =
                 vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
+        struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
 
-        if (WARN_ON(bar_index >= INTEL_GVT_PCI_BAR_MAX))
-                return -EINVAL;
-
+        /*
+         * Power-up software can determine how much address
+         * space the device requires by writing a value of
+         * all 1's to the register and then reading the value
+         * back. The device will return 0's in all don't-care
+         * address bits.
+         */
         if (new == 0xffffffff) {
-                /*
-                 * Power-up software can determine how much address
-                 * space the device requires by writing a value of
-                 * all 1's to the register and then reading the value
-                 * back. The device will return 0's in all don't-care
-                 * address bits.
-                 */
-                size = vgpu->cfg_space.bar[bar_index].size;
-                if (lo) {
-                        new = rounddown(new, size);
-                } else {
-                        u32 val = vgpu_cfg_space(vgpu)[rounddown(offset, 8)];
-                        /* for 32bit mode bar it returns all-0 in upper 32
-                         * bit, for 64bit mode bar it will calculate the
-                         * size with lower 32bit and return the corresponding
-                         * value
+                switch (offset) {
+                case PCI_BASE_ADDRESS_0:
+                case PCI_BASE_ADDRESS_1:
+                        size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1);
+                        intel_vgpu_write_pci_bar(vgpu, offset,
+                                                size >> (lo ? 0 : 32), lo);
+                        /*
+                         * Untrap the BAR, since guest hasn't configured a
+                         * valid GPA
                          */
-                        if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
-                                new &= (~(size-1)) >> 32;
-                        else
-                                new = 0;
-                }
-                /*
-                 * Unmapp & untrap the BAR, since guest hasn't configured a
-                 * valid GPA
-                 */
-                switch (bar_index) {
-                case INTEL_GVT_PCI_BAR_GTTMMIO:
                         ret = trap_gttmmio(vgpu, false);
                         break;
-                case INTEL_GVT_PCI_BAR_APERTURE:
+                case PCI_BASE_ADDRESS_2:
+                case PCI_BASE_ADDRESS_3:
+                        size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);
+                        intel_vgpu_write_pci_bar(vgpu, offset,
+                                                size >> (lo ? 0 : 32), lo);
                         ret = map_aperture(vgpu, false);
                         break;
+                default:
+                        /* Unimplemented BARs */
+                        intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);
                 }
-                intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
         } else {
-                /*
-                 * Unmapp & untrap the old BAR first, since guest has
-                 * re-configured the BAR
-                 */
-                switch (bar_index) {
-                case INTEL_GVT_PCI_BAR_GTTMMIO:
-                        ret = trap_gttmmio(vgpu, false);
+                switch (offset) {
+                case PCI_BASE_ADDRESS_0:
+                case PCI_BASE_ADDRESS_1:
+                        /*
+                         * Untrap the old BAR first, since guest has
+                         * re-configured the BAR
+                         */
+                        trap_gttmmio(vgpu, false);
+                        intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
+                        ret = trap_gttmmio(vgpu, mmio_enabled);
                         break;
-                case INTEL_GVT_PCI_BAR_APERTURE:
-                        ret = map_aperture(vgpu, false);
+                case PCI_BASE_ADDRESS_2:
+                case PCI_BASE_ADDRESS_3:
+                        map_aperture(vgpu, false);
+                        intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
+                        ret = map_aperture(vgpu, mmio_enabled);
                         break;
-                }
-                intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
-                /* Track the new BAR */
-                if (mmio_enabled) {
-                        switch (bar_index) {
-                        case INTEL_GVT_PCI_BAR_GTTMMIO:
-                                ret = trap_gttmmio(vgpu, true);
-                                break;
-                        case INTEL_GVT_PCI_BAR_APERTURE:
-                                ret = map_aperture(vgpu, true);
-                                break;
-                        }
+                default:
+                        intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
                 }
         }
         return ret;
@@ -299,10 +286,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
         }
 
         switch (rounddown(offset, 4)) {
-        case PCI_BASE_ADDRESS_0:
-        case PCI_BASE_ADDRESS_1:
-        case PCI_BASE_ADDRESS_2:
-        case PCI_BASE_ADDRESS_3:
+        case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
                 if (WARN_ON(!IS_ALIGNED(offset, 4)))
                         return -EINVAL;
                 return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
@@ -344,7 +328,6 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
         struct intel_gvt *gvt = vgpu->gvt;
         const struct intel_gvt_device_info *info = &gvt->device_info;
         u16 *gmch_ctl;
-        int i;
 
         memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
                info->cfg_space_size);
@@ -371,13 +354,13 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
          */
         memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
         memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
+        memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
         memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
 
-        for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) {
-                vgpu->cfg_space.bar[i].size = pci_resource_len(
-                                              gvt->dev_priv->drm.pdev, i * 2);
-                vgpu->cfg_space.bar[i].tracked = false;
-        }
+        vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
+                                pci_resource_len(gvt->dev_priv->drm.pdev, 0);
+        vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
+                                pci_resource_len(gvt->dev_priv->drm.pdev, 2);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e21ce9c18b6e..b63893eeca73 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -839,7 +839,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
                                                                 pipe);
         int position;
         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
-        bool in_vbl = true;
         unsigned long irqflags;
 
         if (WARN_ON(!mode->crtc_clock)) {
@@ -922,8 +921,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 
         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 
-        in_vbl = position >= vbl_start && position < vbl_end;
-
         /*
          * While in vblank, position will be negative
          * counting up towards 0 at vbl_end. And outside
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f17275519484..00cd17c76fdc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14030,7 +14030,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 
                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
-                        return -EINVAL;
+                        goto err;
                 }
 
                 stride_alignment = intel_fb_stride_alignment(fb, i);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index f0c11aec5ea5..7442891762be 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -892,8 +892,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder,
                               struct intel_crtc_state *old_crtc_state,
                               struct drm_connector_state *old_conn_state)
 {
-        struct drm_device *dev = encoder->base.dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
         enum port port;
 
@@ -903,15 +901,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder,
         intel_panel_disable_backlight(old_conn_state);
 
         /*
-         * Disable Device ready before the port shutdown in order
-         * to avoid split screen
-         */
-        if (IS_BROXTON(dev_priv)) {
-                for_each_dsi_port(port, intel_dsi->ports)
-                        I915_WRITE(MIPI_DEVICE_READY(port), 0);
-        }
-
-        /*
          * According to the spec we should send SHUTDOWN before
          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
          * has shown that the v3 sequence works for v2 VBTs too
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index a17b1de7d7e0..3b1c5d783ee7 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1699,6 +1699,8 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
         if (!panel->backlight.max)
                 return -ENODEV;
 
+        panel->backlight.min = get_backlight_min_vbt(connector);
+
         val = bxt_get_backlight(connector);
         val = intel_panel_compute_brightness(connector, val);
         panel->backlight.level = clamp(val, panel->backlight.min,
@@ -1735,6 +1737,8 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
         if (!panel->backlight.max)
                 return -ENODEV;
 
+        panel->backlight.min = get_backlight_min_vbt(connector);
+
         val = bxt_get_backlight(connector);
         val = intel_panel_compute_brightness(connector, val);
         panel->backlight.level = clamp(val, panel->backlight.min,
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 7b4567bacfc2..26283fefdf5f 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -23,15 +23,15 @@
 #ifndef KFD_IOCTL_H_INCLUDED
 #define KFD_IOCTL_H_INCLUDED
 
-#include <linux/types.h>
+#include <drm/drm.h>
 #include <linux/ioctl.h>
 
 #define KFD_IOCTL_MAJOR_VERSION 1
 #define KFD_IOCTL_MINOR_VERSION 1
 
 struct kfd_ioctl_get_version_args {
-        uint32_t major_version; /* from KFD */
-        uint32_t minor_version; /* from KFD */
+        __u32 major_version;    /* from KFD */
+        __u32 minor_version;    /* from KFD */
 };
 
 /* For kfd_ioctl_create_queue_args.queue_type. */
@@ -43,36 +43,36 @@ struct kfd_ioctl_get_version_args {
 #define KFD_MAX_QUEUE_PRIORITY          15
 
 struct kfd_ioctl_create_queue_args {
-        uint64_t ring_base_address;     /* to KFD */
-        uint64_t write_pointer_address; /* from KFD */
-        uint64_t read_pointer_address;  /* from KFD */
-        uint64_t doorbell_offset;       /* from KFD */
-
-        uint32_t ring_size;             /* to KFD */
-        uint32_t gpu_id;                /* to KFD */
-        uint32_t queue_type;            /* to KFD */
-        uint32_t queue_percentage;      /* to KFD */
-        uint32_t queue_priority;        /* to KFD */
-        uint32_t queue_id;              /* from KFD */
-
-        uint64_t eop_buffer_address;    /* to KFD */
-        uint64_t eop_buffer_size;       /* to KFD */
-        uint64_t ctx_save_restore_address; /* to KFD */
-        uint64_t ctx_save_restore_size; /* to KFD */
+        __u64 ring_base_address;        /* to KFD */
+        __u64 write_pointer_address;    /* from KFD */
+        __u64 read_pointer_address;     /* from KFD */
+        __u64 doorbell_offset;  /* from KFD */
+
+        __u32 ring_size;                /* to KFD */
+        __u32 gpu_id;           /* to KFD */
+        __u32 queue_type;               /* to KFD */
+        __u32 queue_percentage; /* to KFD */
+        __u32 queue_priority;   /* to KFD */
+        __u32 queue_id;         /* from KFD */
+
+        __u64 eop_buffer_address;       /* to KFD */
+        __u64 eop_buffer_size;  /* to KFD */
+        __u64 ctx_save_restore_address; /* to KFD */
+        __u64 ctx_save_restore_size;    /* to KFD */
 };
 
 struct kfd_ioctl_destroy_queue_args {
-        uint32_t queue_id;              /* to KFD */
-        uint32_t pad;
+        __u32 queue_id;         /* to KFD */
+        __u32 pad;
 };
 
 struct kfd_ioctl_update_queue_args {
-        uint64_t ring_base_address;     /* to KFD */
+        __u64 ring_base_address;        /* to KFD */
 
-        uint32_t queue_id;              /* to KFD */
-        uint32_t ring_size;             /* to KFD */
-        uint32_t queue_percentage;      /* to KFD */
-        uint32_t queue_priority;        /* to KFD */
+        __u32 queue_id;         /* to KFD */
+        __u32 ring_size;                /* to KFD */
+        __u32 queue_percentage; /* to KFD */
+        __u32 queue_priority;   /* to KFD */
 };
 
 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
@@ -80,13 +80,13 @@ struct kfd_ioctl_update_queue_args {
 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
 
 struct kfd_ioctl_set_memory_policy_args {
-        uint64_t alternate_aperture_base;       /* to KFD */
-        uint64_t alternate_aperture_size;       /* to KFD */
+        __u64 alternate_aperture_base;  /* to KFD */
+        __u64 alternate_aperture_size;  /* to KFD */
 
-        uint32_t gpu_id;                        /* to KFD */
-        uint32_t default_policy;                /* to KFD */
-        uint32_t alternate_policy;              /* to KFD */
-        uint32_t pad;
+        __u32 gpu_id;                   /* to KFD */
+        __u32 default_policy;           /* to KFD */
+        __u32 alternate_policy;         /* to KFD */
+        __u32 pad;
 };
 
 /*
@@ -97,26 +97,26 @@ struct kfd_ioctl_set_memory_policy_args {
  */
 
 struct kfd_ioctl_get_clock_counters_args {
-        uint64_t gpu_clock_counter;     /* from KFD */
-        uint64_t cpu_clock_counter;     /* from KFD */
-        uint64_t system_clock_counter;  /* from KFD */
-        uint64_t system_clock_freq;     /* from KFD */
+        __u64 gpu_clock_counter;        /* from KFD */
+        __u64 cpu_clock_counter;        /* from KFD */
+        __u64 system_clock_counter;     /* from KFD */
+        __u64 system_clock_freq;        /* from KFD */
 
-        uint32_t gpu_id;                /* to KFD */
-        uint32_t pad;
+        __u32 gpu_id;           /* to KFD */
+        __u32 pad;
 };
 
 #define NUM_OF_SUPPORTED_GPUS 7
 
 struct kfd_process_device_apertures {
-        uint64_t lds_base;              /* from KFD */
-        uint64_t lds_limit;             /* from KFD */
-        uint64_t scratch_base;          /* from KFD */
-        uint64_t scratch_limit;         /* from KFD */
-        uint64_t gpuvm_base;            /* from KFD */
-        uint64_t gpuvm_limit;           /* from KFD */
-        uint32_t gpu_id;                /* from KFD */
-        uint32_t pad;
+        __u64 lds_base;         /* from KFD */
+        __u64 lds_limit;                /* from KFD */
+        __u64 scratch_base;             /* from KFD */
+        __u64 scratch_limit;            /* from KFD */
+        __u64 gpuvm_base;               /* from KFD */
+        __u64 gpuvm_limit;              /* from KFD */
+        __u32 gpu_id;           /* from KFD */
+        __u32 pad;
 };
 
 struct kfd_ioctl_get_process_apertures_args {
@@ -124,8 +124,8 @@ struct kfd_ioctl_get_process_apertures_args {
                         process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */
 
         /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
-        uint32_t num_of_nodes;
-        uint32_t pad;
+        __u32 num_of_nodes;
+        __u32 pad;
 };
 
 #define MAX_ALLOWED_NUM_POINTS    100
@@ -133,25 +133,25 @@ struct kfd_ioctl_get_process_apertures_args {
 #define MAX_ALLOWED_WAC_BUFF_SIZE  128
 
 struct kfd_ioctl_dbg_register_args {
-        uint32_t gpu_id;                /* to KFD */
-        uint32_t pad;
+        __u32 gpu_id;           /* to KFD */
+        __u32 pad;
 };
 
 struct kfd_ioctl_dbg_unregister_args {
-        uint32_t gpu_id;                /* to KFD */
-        uint32_t pad;
+        __u32 gpu_id;           /* to KFD */
+        __u32 pad;
 };
 
 struct kfd_ioctl_dbg_address_watch_args {
-        uint64_t content_ptr;           /* a pointer to the actual content */
-        uint32_t gpu_id;                /* to KFD */
-        uint32_t buf_size_in_bytes;     /*including gpu_id and buf_size */
+        __u64 content_ptr;              /* a pointer to the actual content */
+        __u32 gpu_id;           /* to KFD */
+        __u32 buf_size_in_bytes;        /*including gpu_id and buf_size */
 };
 
 struct kfd_ioctl_dbg_wave_control_args {
-        uint64_t content_ptr;           /* a pointer to the actual content */
-        uint32_t gpu_id;                /* to KFD */
-        uint32_t buf_size_in_bytes;     /*including gpu_id and buf_size */
+        __u64 content_ptr;              /* a pointer to the actual content */
+        __u32 gpu_id;           /* to KFD */
+        __u32 buf_size_in_bytes;        /*including gpu_id and buf_size */
 };
 
 /* Matching HSA_EVENTTYPE */
@@ -172,44 +172,44 @@ struct kfd_ioctl_dbg_wave_control_args {
 #define KFD_SIGNAL_EVENT_LIMIT                  256
 
 struct kfd_ioctl_create_event_args {
-        uint64_t event_page_offset;     /* from KFD */
-        uint32_t event_trigger_data;    /* from KFD - signal events only */
-        uint32_t event_type;            /* to KFD */
-        uint32_t auto_reset;            /* to KFD */
-        uint32_t node_id;               /* to KFD - only valid for certain
+        __u64 event_page_offset;        /* from KFD */
+        __u32 event_trigger_data;       /* from KFD - signal events only */
+        __u32 event_type;               /* to KFD */
+        __u32 auto_reset;               /* to KFD */
+        __u32 node_id;          /* to KFD - only valid for certain
                                                         event types */
-        uint32_t event_id;              /* from KFD */
-        uint32_t event_slot_index;      /* from KFD */
+        __u32 event_id;         /* from KFD */
+        __u32 event_slot_index; /* from KFD */
 };
 
 struct kfd_ioctl_destroy_event_args {
-        uint32_t event_id;              /* to KFD */
-        uint32_t pad;
+        __u32 event_id;         /* to KFD */
+        __u32 pad;
 };
 
 struct kfd_ioctl_set_event_args {
-        uint32_t event_id;              /* to KFD */
-        uint32_t pad;
+        __u32 event_id;         /* to KFD */
+        __u32 pad;
 };
 
 struct kfd_ioctl_reset_event_args {
-        uint32_t event_id;              /* to KFD */
-        uint32_t pad;
+        __u32 event_id;         /* to KFD */
+        __u32 pad;
 };
 
 struct kfd_memory_exception_failure {
-        uint32_t NotPresent;    /* Page not present or supervisor privilege */
-        uint32_t ReadOnly;      /* Write access to a read-only page */
-        uint32_t NoExecute;     /* Execute access to a page marked NX */
-        uint32_t pad;
+        __u32 NotPresent;       /* Page not present or supervisor privilege */
+        __u32 ReadOnly; /* Write access to a read-only page */
+        __u32 NoExecute;        /* Execute access to a page marked NX */
+        __u32 pad;
 };
 
 /* memory exception data*/
 struct kfd_hsa_memory_exception_data {
         struct kfd_memory_exception_failure failure;
-        uint64_t va;
-        uint32_t gpu_id;
-        uint32_t pad;
+        __u64 va;
+        __u32 gpu_id;
+        __u32 pad;
 };
 
 /* Event data*/
@@ -217,19 +217,19 @@ struct kfd_event_data {
         union {
                 struct kfd_hsa_memory_exception_data memory_exception_data;
         };                              /* From KFD */
-        uint64_t kfd_event_data_ext;    /* pointer to an extension structure
+        __u64 kfd_event_data_ext;       /* pointer to an extension structure
                                            for future exception types */
-        uint32_t event_id;              /* to KFD */
-        uint32_t pad;
+        __u32 event_id;         /* to KFD */
+        __u32 pad;
 };
 
 struct kfd_ioctl_wait_events_args {
-        uint64_t events_ptr;            /* pointed to struct
+        __u64 events_ptr;               /* pointed to struct
                                            kfd_event_data array, to KFD */
-        uint32_t num_events;            /* to KFD */
-        uint32_t wait_for_all;          /* to KFD */
-        uint32_t timeout;               /* to KFD */
-        uint32_t wait_result;           /* from KFD */
+        __u32 num_events;               /* to KFD */
+        __u32 wait_for_all;             /* to KFD */
+        __u32 timeout;          /* to KFD */
+        __u32 wait_result;              /* from KFD */
 };
 
 struct kfd_ioctl_set_scratch_backing_va_args {