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authorMaarten Lankhorst <dev@mblankhorst.nl>2015-11-17 05:15:45 -0500
committerThierry Reding <treding@nvidia.com>2016-04-12 11:10:21 -0400
commitb664129459f529d403d05570115254534611b52d (patch)
tree81b81a558e23c7a099110f6be8e0d3158350dce6
parentc90bb7b9b968272aa4ee7fed605105b00407395a (diff)
ARM: tegra: Enable watchdog support for Tegra114 and Tegra124
Watchdog support was added to the timer block with Tegra30. Tegra20 did not have this yet. However, the Tegra114 and Tegra124 DTSI files had an entry in the compatible string list for "nvidia,tegra20-timer", but not for "nvidia,tegra30-timer", which is why watchdog support isn't enabled on them. Fix this by adding an entry for "nvidia,tegra30-timer" to the compatible string list of the timer block on Tegra114 and Tegra124. This allows the watchdog to work on Jetson TK1. Signed-off-by: Maarten Lankhorst <dev@mblankhorst.nl> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 5017ed8ad5c4..cb9393a53422 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -150,7 +150,7 @@
150 }; 150 };
151 151
152 timer@60005000 { 152 timer@60005000 {
153 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; 153 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
154 reg = <0x60005000 0x400>; 154 reg = <0x60005000 0x400>;
155 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 155 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 995289b59e11..e4eac1f01e64 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -208,7 +208,7 @@
208 }; 208 };
209 209
210 timer@0,60005000 { 210 timer@0,60005000 {
211 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 211 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
212 reg = <0x0 0x60005000 0x0 0x400>; 212 reg = <0x0 0x60005000 0x0 0x400>;
213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,