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authorDave Airlie <airlied@redhat.com>2017-03-30 21:50:56 -0400
committerDave Airlie <airlied@redhat.com>2017-03-30 21:50:56 -0400
commitb61d60753dc6c7c62669ebb9cacd7dfa5313cd1e (patch)
tree8ad9c62ab766bdf10fb1f41ba060019024aa2b4e
parent4adf04361b97ae198394cf44839e481aac317023 (diff)
parent0abfe7e2570d7c729a7662e82c09a23f00f29346 (diff)
Merge tag 'drm-intel-fixes-2017-03-29' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes
drm/i915 fixes for v4.11-rc5 * tag 'drm-intel-fixes-2017-03-29' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: Restore marking context objects as dirty on pinning drm/i915/gvt: Use force single submit flag to distinguish gvt request from i915 request drm/i915/gvt: set shadow entry to scratch page while p2m failed drm/i915/gvt: Fix guest fail to read EDID leading to black guest console issue. drm/i915/gvt: fix wrong offset when loading RCS mocs drm/i915/gvt: add write handler for mmio mbctl drm/i915/kvmgt: Hold struct kvm reference
-rw-r--r--drivers/gpu/drm/i915/gvt/edid.c3
-rw-r--r--drivers/gpu/drm/i915/gvt/gtt.c8
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c10
-rw-r--r--drivers/gpu/drm/i915/gvt/kvmgt.c2
-rw-r--r--drivers/gpu/drm/i915/gvt/render.c2
-rw-r--r--drivers/gpu/drm/i915/gvt/scheduler.c7
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c2
7 files changed, 28 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index f1648fe5e5ea..42cd09ec63fa 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -495,7 +495,8 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
495 unsigned char val = edid_get_byte(vgpu); 495 unsigned char val = edid_get_byte(vgpu);
496 496
497 aux_data_for_write = (val << 16); 497 aux_data_for_write = (val << 16);
498 } 498 } else
499 aux_data_for_write = (0xff << 16);
499 } 500 }
500 /* write the return value in AUX_CH_DATA reg which includes: 501 /* write the return value in AUX_CH_DATA reg which includes:
501 * ACK of I2C_WRITE 502 * ACK of I2C_WRITE
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index da7312715824..b832bea64e03 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1837,11 +1837,15 @@ static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
1837 ret = gtt_entry_p2m(vgpu, &e, &m); 1837 ret = gtt_entry_p2m(vgpu, &e, &m);
1838 if (ret) { 1838 if (ret) {
1839 gvt_vgpu_err("fail to translate guest gtt entry\n"); 1839 gvt_vgpu_err("fail to translate guest gtt entry\n");
1840 return ret; 1840 /* guest driver may read/write the entry when partial
1841 * update the entry in this situation p2m will fail
1842 * settting the shadow entry to point to a scratch page
1843 */
1844 ops->set_pfn(&m, gvt->gtt.scratch_ggtt_mfn);
1841 } 1845 }
1842 } else { 1846 } else {
1843 m = e; 1847 m = e;
1844 m.val64 = 0; 1848 ops->set_pfn(&m, gvt->gtt.scratch_ggtt_mfn);
1845 } 1849 }
1846 1850
1847 ggtt_set_shadow_entry(ggtt_mm, &m, g_gtt_index); 1851 ggtt_set_shadow_entry(ggtt_mm, &m, g_gtt_index);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index eaff45d417e8..6da9ae1618e3 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -970,6 +970,14 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
970 return 0; 970 return 0;
971} 971}
972 972
973static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
974 void *p_data, unsigned int bytes)
975{
976 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
977 write_vreg(vgpu, offset, p_data, bytes);
978 return 0;
979}
980
973static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 981static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
974 void *p_data, unsigned int bytes) 982 void *p_data, unsigned int bytes)
975{ 983{
@@ -2238,7 +2246,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2238 MMIO_D(0x7180, D_ALL); 2246 MMIO_D(0x7180, D_ALL);
2239 MMIO_D(0x7408, D_ALL); 2247 MMIO_D(0x7408, D_ALL);
2240 MMIO_D(0x7c00, D_ALL); 2248 MMIO_D(0x7c00, D_ALL);
2241 MMIO_D(GEN6_MBCTL, D_ALL); 2249 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2242 MMIO_D(0x911c, D_ALL); 2250 MMIO_D(0x911c, D_ALL);
2243 MMIO_D(0x9120, D_ALL); 2251 MMIO_D(0x9120, D_ALL);
2244 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2252 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ea3eb270de8..d641214578a7 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1326,6 +1326,7 @@ static int kvmgt_guest_init(struct mdev_device *mdev)
1326 vgpu->handle = (unsigned long)info; 1326 vgpu->handle = (unsigned long)info;
1327 info->vgpu = vgpu; 1327 info->vgpu = vgpu;
1328 info->kvm = kvm; 1328 info->kvm = kvm;
1329 kvm_get_kvm(info->kvm);
1329 1330
1330 kvmgt_protect_table_init(info); 1331 kvmgt_protect_table_init(info);
1331 gvt_cache_init(vgpu); 1332 gvt_cache_init(vgpu);
@@ -1347,6 +1348,7 @@ static bool kvmgt_guest_exit(struct kvmgt_guest_info *info)
1347 } 1348 }
1348 1349
1349 kvm_page_track_unregister_notifier(info->kvm, &info->track_node); 1350 kvm_page_track_unregister_notifier(info->kvm, &info->track_node);
1351 kvm_put_kvm(info->kvm);
1350 kvmgt_protect_table_destroy(info); 1352 kvmgt_protect_table_destroy(info);
1351 gvt_cache_destroy(info->vgpu); 1353 gvt_cache_destroy(info->vgpu);
1352 vfree(info); 1354 vfree(info);
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index 95ee091ce085..0beb83563b08 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -207,7 +207,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
207 l3_offset.reg = 0xb020; 207 l3_offset.reg = 0xb020;
208 for (i = 0; i < 32; i++) { 208 for (i = 0; i < 32; i++) {
209 gen9_render_mocs_L3[i] = I915_READ(l3_offset); 209 gen9_render_mocs_L3[i] = I915_READ(l3_offset);
210 I915_WRITE(l3_offset, vgpu_vreg(vgpu, offset)); 210 I915_WRITE(l3_offset, vgpu_vreg(vgpu, l3_offset));
211 POSTING_READ(l3_offset); 211 POSTING_READ(l3_offset);
212 l3_offset.reg += 4; 212 l3_offset.reg += 4;
213 } 213 }
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index c4353ed86d4b..a44782412f2c 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -127,6 +127,11 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
127 return 0; 127 return 0;
128} 128}
129 129
130static inline bool is_gvt_request(struct drm_i915_gem_request *req)
131{
132 return i915_gem_context_force_single_submission(req->ctx);
133}
134
130static int shadow_context_status_change(struct notifier_block *nb, 135static int shadow_context_status_change(struct notifier_block *nb,
131 unsigned long action, void *data) 136 unsigned long action, void *data)
132{ 137{
@@ -137,7 +142,7 @@ static int shadow_context_status_change(struct notifier_block *nb,
137 struct intel_vgpu_workload *workload = 142 struct intel_vgpu_workload *workload =
138 scheduler->current_workload[req->engine->id]; 143 scheduler->current_workload[req->engine->id];
139 144
140 if (unlikely(!workload)) 145 if (!is_gvt_request(req) || unlikely(!workload))
141 return NOTIFY_OK; 146 return NOTIFY_OK;
142 147
143 switch (action) { 148 switch (action) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 91bc4abf5d3e..6c5f9958197d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2024,6 +2024,8 @@ static int intel_ring_context_pin(struct intel_engine_cs *engine,
2024 ret = context_pin(ctx, flags); 2024 ret = context_pin(ctx, flags);
2025 if (ret) 2025 if (ret)
2026 goto error; 2026 goto error;
2027
2028 ce->state->obj->mm.dirty = true;
2027 } 2029 }
2028 2030
2029 /* The kernel context is only used as a placeholder for flushing the 2031 /* The kernel context is only used as a placeholder for flushing the