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authorYu Zhao <yuzhao@google.com>2018-09-11 17:14:04 -0400
committerMark Brown <broonie@kernel.org>2018-09-12 06:21:55 -0400
commitb61749a89f826eb61fc59794d9e4697bd246eb61 (patch)
tree2e31d960f7f106143d27a3819c230ccc5f07e05d
parent542cedec53c9e8b73f3f05bf8468823598c50489 (diff)
sound: enable interrupt after dma buffer initialization
In snd_hdac_bus_init_chip(), we enable interrupt before snd_hdac_bus_init_cmd_io() initializing dma buffers. If irq has been acquired and irq handler uses the dma buffer, kernel may crash when interrupt comes in. Fix the problem by postponing enabling irq after dma buffer initialization. And warn once on null dma buffer pointer during the initialization. Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Yu Zhao <yuzhao@google.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/hda/hdac_controller.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/sound/hda/hdac_controller.c b/sound/hda/hdac_controller.c
index 560ec0986e1a..11057d9f84ec 100644
--- a/sound/hda/hdac_controller.c
+++ b/sound/hda/hdac_controller.c
@@ -40,6 +40,8 @@ static void azx_clear_corbrp(struct hdac_bus *bus)
40 */ 40 */
41void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus) 41void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
42{ 42{
43 WARN_ON_ONCE(!bus->rb.area);
44
43 spin_lock_irq(&bus->reg_lock); 45 spin_lock_irq(&bus->reg_lock);
44 /* CORB set up */ 46 /* CORB set up */
45 bus->corb.addr = bus->rb.addr; 47 bus->corb.addr = bus->rb.addr;
@@ -479,13 +481,15 @@ bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
479 /* reset controller */ 481 /* reset controller */
480 azx_reset(bus, full_reset); 482 azx_reset(bus, full_reset);
481 483
482 /* initialize interrupts */ 484 /* clear interrupts */
483 azx_int_clear(bus); 485 azx_int_clear(bus);
484 azx_int_enable(bus);
485 486
486 /* initialize the codec command I/O */ 487 /* initialize the codec command I/O */
487 snd_hdac_bus_init_cmd_io(bus); 488 snd_hdac_bus_init_cmd_io(bus);
488 489
490 /* enable interrupts after CORB/RIRB buffers are initialized above */
491 azx_int_enable(bus);
492
489 /* program the position buffer */ 493 /* program the position buffer */
490 if (bus->use_posbuf && bus->posbuf.addr) { 494 if (bus->use_posbuf && bus->posbuf.addr) {
491 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr); 495 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);