diff options
| author | James Zhu <James.Zhu@amd.com> | 2018-09-10 14:58:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-09-26 22:09:23 -0400 |
| commit | b604545b921b0b6af1785db85bab8e790a18ddad (patch) | |
| tree | fe191256abb7a9cade854159f9b7fc81728729af | |
| parent | 21cbe2f38cd94c180c4b3aad00bcb95b5f323134 (diff) | |
drm/amdgpu:Add new register offset/mask to support VCN DPG mode
New register offset/mask need to be added to support VCN DPG mode.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 25 |
2 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h index 216a401028de..4b7da589e14a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | |||
| @@ -33,6 +33,14 @@ | |||
| 33 | #define mmUVD_POWER_STATUS_BASE_IDX 1 | 33 | #define mmUVD_POWER_STATUS_BASE_IDX 1 |
| 34 | #define mmCC_UVD_HARVESTING 0x00c7 | 34 | #define mmCC_UVD_HARVESTING 0x00c7 |
| 35 | #define mmCC_UVD_HARVESTING_BASE_IDX 1 | 35 | #define mmCC_UVD_HARVESTING_BASE_IDX 1 |
| 36 | #define mmUVD_DPG_LMA_CTL 0x00d1 | ||
| 37 | #define mmUVD_DPG_LMA_CTL_BASE_IDX 1 | ||
| 38 | #define mmUVD_DPG_LMA_DATA 0x00d2 | ||
| 39 | #define mmUVD_DPG_LMA_DATA_BASE_IDX 1 | ||
| 40 | #define mmUVD_DPG_LMA_MASK 0x00d3 | ||
| 41 | #define mmUVD_DPG_LMA_MASK_BASE_IDX 1 | ||
| 42 | #define mmUVD_DPG_PAUSE 0x00d4 | ||
| 43 | #define mmUVD_DPG_PAUSE_BASE_IDX 1 | ||
| 36 | #define mmUVD_SCRATCH1 0x00d5 | 44 | #define mmUVD_SCRATCH1 0x00d5 |
| 37 | #define mmUVD_SCRATCH1_BASE_IDX 1 | 45 | #define mmUVD_SCRATCH1_BASE_IDX 1 |
| 38 | #define mmUVD_SCRATCH2 0x00d6 | 46 | #define mmUVD_SCRATCH2 0x00d6 |
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h index 124383dac284..26382f5d5354 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | |||
| @@ -87,6 +87,26 @@ | |||
| 87 | //CC_UVD_HARVESTING | 87 | //CC_UVD_HARVESTING |
| 88 | #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 | 88 | #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 |
| 89 | #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L | 89 | #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L |
| 90 | //UVD_DPG_LMA_CTL | ||
| 91 | #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 | ||
| 92 | #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 | ||
| 93 | #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 | ||
| 94 | #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 | ||
| 95 | #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 | ||
| 96 | #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L | ||
| 97 | #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L | ||
| 98 | #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L | ||
| 99 | #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L | ||
| 100 | #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L | ||
| 101 | //UVD_DPG_PAUSE | ||
| 102 | #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 | ||
| 103 | #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 | ||
| 104 | #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 | ||
| 105 | #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 | ||
| 106 | #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L | ||
| 107 | #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L | ||
| 108 | #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L | ||
| 109 | #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L | ||
| 90 | //UVD_SCRATCH1 | 110 | //UVD_SCRATCH1 |
| 91 | #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 | 111 | #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 |
| 92 | #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL | 112 | #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL |
| @@ -983,6 +1003,7 @@ | |||
| 983 | #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L | 1003 | #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L |
| 984 | #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L | 1004 | #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L |
| 985 | //UVD_SYS_INT_EN | 1005 | //UVD_SYS_INT_EN |
| 1006 | #define UVD_SYS_INT_EN__UVD_JRBC_EN__SHIFT 0x4 | ||
| 986 | #define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK 0x00000010L | 1007 | #define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK 0x00000010L |
| 987 | //JPEG_CGC_CTRL | 1008 | //JPEG_CGC_CTRL |
| 988 | #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 | 1009 | #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 |
| @@ -1138,7 +1159,11 @@ | |||
| 1138 | #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL | 1159 | #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL |
| 1139 | //UVD_VCPU_CNTL | 1160 | //UVD_VCPU_CNTL |
| 1140 | #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 | 1161 | #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 |
| 1162 | #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 | ||
| 1163 | #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 | ||
| 1141 | #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L | 1164 | #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L |
| 1165 | #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L | ||
| 1166 | #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L | ||
| 1142 | //UVD_SOFT_RESET | 1167 | //UVD_SOFT_RESET |
| 1143 | #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 | 1168 | #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 |
| 1144 | #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 | 1169 | #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 |