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authorKukjin Kim <kgene.kim@samsung.com>2013-12-18 14:22:09 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-12-18 15:21:19 -0500
commitb5fd13008e26e10481f2ae65a2a5ed47959a9343 (patch)
tree34e9ee144c7a8457fcc1627d4701e5130667f88b
parentdf3e9c057e502c0d46ba37cbb67d52904e97b4c4 (diff)
ARM: EXYNOS: local definitions for cpuidle.c into mach-exynos dir
This moves definitions for cpuidle into mach-exynos/cpuidle.c, because we don't need to keep them in the <mach/regs-clock.h>. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--arch/arm/mach-exynos/cpuidle.c23
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h21
2 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 6ba13ea61ad2..da65b036af2b 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -22,11 +22,13 @@
22#include <asm/suspend.h> 22#include <asm/suspend.h>
23#include <asm/unified.h> 23#include <asm/unified.h>
24#include <asm/cpuidle.h> 24#include <asm/cpuidle.h>
25#include <mach/regs-clock.h>
26 25
27#include <plat/cpu.h> 26#include <plat/cpu.h>
28#include <plat/pm.h> 27#include <plat/pm.h>
29 28
29#include <mach/pm-core.h>
30#include <mach/map.h>
31
30#include "common.h" 32#include "common.h"
31#include "regs-pmu.h" 33#include "regs-pmu.h"
32 34
@@ -39,6 +41,25 @@
39 41
40#define S5P_CHECK_AFTR 0xFCBA0D10 42#define S5P_CHECK_AFTR 0xFCBA0D10
41 43
44#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020)
45#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024)
46
47#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
48#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
49#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
50#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
51#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
52#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
53#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
54#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
55
56#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
57#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
58#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
59#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
60#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
61#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
62
42static int exynos4_enter_lowpower(struct cpuidle_device *dev, 63static int exynos4_enter_lowpower(struct cpuidle_device *dev,
43 struct cpuidle_driver *drv, 64 struct cpuidle_driver *drv,
44 int index); 65 int index);
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 22afe63e8c30..cc121a582d2f 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -16,25 +16,4 @@
16#include <plat/cpu.h> 16#include <plat/cpu.h>
17#include <mach/map.h> 17#include <mach/map.h>
18 18
19#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
20
21#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
22#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
23
24#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
25#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
26#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
27#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
28#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
29#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
30#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
31#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
32
33#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
34#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
35#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
36#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
37#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
38#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
39
40#endif /* __ASM_ARCH_REGS_CLOCK_H */ 19#endif /* __ASM_ARCH_REGS_CLOCK_H */