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authorArnd Bergmann <arnd@arndb.de>2018-01-05 11:06:04 -0500
committerArnd Bergmann <arnd@arndb.de>2018-01-05 11:06:04 -0500
commitb55eb1ae91e986ff75b1cd6ff8889d056ad68a10 (patch)
tree3af373d0910b5d1eed54471cfc95e9ff505aaa53
parent7598a4e035b81c5e2a3dae17b33d77232141124a (diff)
parente40ed274489a5f516da120186578eb379b452ac6 (diff)
Merge tag 'aspeed-4.16-devicetree' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into next/dt
Pull "ASPEED device tree updates for 4.16" from Joel Stanley: Clock driver support: Rework all platforms to use proper clock bindings. Linux should now boot upstream kernels on ast2400 and ast2500 platforms without out of tree patches. New systems: Witherspoon: OpenPower Power9 server manufactured by IBM that uses the ASPEED ast2500 Zaius: OpenPower Power9 server manufactured by Invatech that uses the ASPEED ast2500 Q71L: Intel Xeon server manufactured by Qanta that uses the ASPEED ast2400 We also see updates to the Palmetto and Romulus systems to bring them in line with the functionality of those above. The systems take advantage of recently added drivers for LPC Snoop device and the PWM/Tachometer fan controller. OpenBMC flash layout: The flash layout used OpenBMC systems is added and the device trees now use it. * tag 'aspeed-4.16-devicetree' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: ARM: dts: aspeed-evb: Add unit name to memory node ARM: dts: aspeed-plametto: Add flash layout and fix memory node ARM: dts: aspeed-romulus: Update Romulus system ARM: dts: aspeed: Add Qanta Q71L BMC machine ARM: dts: aspeed: Add Ingrasys Zaius BMC machine ARM: dts: aspeed: Add Witherspoon BMC machine ARM: dts: aspeed: Sort ASPEED entries in makefile ARM: dts: Add OpenBMC flash layout ARM: dts: aspeed: Update license headers ARM: dts: aspeed: Remove skeleton.dtsi ARM: dts: aspeed: Add LPC Snoop device ARM: dts: aspeed: Add PWM and tachometer node ARM: dts: aspeed: Add clock phandle to GPIO ARM: dts: aspeed: Add flash controller clocks ARM: dts: aspeed: Add watchdog clocks ARM: dts: aspeed: Add MAC clocks ARM: dts: aspeed: Add proper clock references ARM: dts: aspeed: Add LPC and child devices dt-bindings: gpio: Add ASPEED constants dt-bindings: clock: Add ASPEED constants Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile8
-rw-r--r--arch/arm/boot/dts/aspeed-ast2500-evb.dts4
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts5
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts135
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts548
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts426
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts458
-rw-r--r--arch/arm/boot/dts/aspeed-g4.dtsi165
-rw-r--r--arch/arm/boot/dts/aspeed-g5.dtsi156
-rw-r--r--arch/arm/boot/dts/openbmc-flash-layout.dtsi32
-rw-r--r--include/dt-bindings/clock/aspeed-clock.h52
-rw-r--r--include/dt-bindings/gpio/aspeed-gpio.h49
12 files changed, 1888 insertions, 150 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 33c9f3358dff..a89ffaff8e8f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1107,6 +1107,10 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
1107 mt8127-moose.dtb \ 1107 mt8127-moose.dtb \
1108 mt8135-evbp1.dtb 1108 mt8135-evbp1.dtb
1109dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb 1109dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
1110dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \ 1110dtb-$(CONFIG_ARCH_ASPEED) += \
1111 aspeed-ast2500-evb.dtb \
1112 aspeed-bmc-opp-palmetto.dtb \
1111 aspeed-bmc-opp-romulus.dtb \ 1113 aspeed-bmc-opp-romulus.dtb \
1112 aspeed-ast2500-evb.dtb 1114 aspeed-bmc-opp-witherspoon.dtb \
1115 aspeed-bmc-opp-zaius.dtb \
1116 aspeed-bmc-quanta-q71l.dtb
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 602bc10fdaf4..91a36c1f029b 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2/dts-v1/; 2/dts-v1/;
3 3
4#include "aspeed-g5.dtsi" 4#include "aspeed-g5.dtsi"
@@ -16,7 +16,7 @@
16 bootargs = "console=ttyS4,115200 earlyprintk"; 16 bootargs = "console=ttyS4,115200 earlyprintk";
17 }; 17 };
18 18
19 memory { 19 memory@80000000 {
20 reg = <0x80000000 0x20000000>; 20 reg = <0x80000000 0x20000000>;
21 }; 21 };
22}; 22};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index c786bc2f2919..4379d09a261f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2/dts-v1/; 2/dts-v1/;
3 3
4#include "aspeed-g4.dtsi" 4#include "aspeed-g4.dtsi"
@@ -12,7 +12,7 @@
12 bootargs = "console=ttyS4,115200 earlyprintk"; 12 bootargs = "console=ttyS4,115200 earlyprintk";
13 }; 13 };
14 14
15 memory { 15 memory@40000000 {
16 reg = <0x40000000 0x20000000>; 16 reg = <0x40000000 0x20000000>;
17 }; 17 };
18 18
@@ -34,6 +34,7 @@
34 status = "okay"; 34 status = "okay";
35 m25p,fast-read; 35 m25p,fast-read;
36 label = "bmc"; 36 label = "bmc";
37#include "openbmc-flash-layout.dtsi"
37 }; 38 };
38}; 39};
39 40
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 8067793129ea..623b6ab42021 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -1,23 +1,19 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2/dts-v1/; 2/dts-v1/;
3
4#include "aspeed-g5.dtsi" 3#include "aspeed-g5.dtsi"
4#include <dt-bindings/gpio/aspeed-gpio.h>
5 5
6/ { 6/ {
7 model = "Romulus BMC"; 7 model = "Romulus BMC";
8 compatible = "ibm,romulus-bmc", "aspeed,ast2500"; 8 compatible = "ibm,romulus-bmc", "aspeed,ast2500";
9 9
10 aliases {
11 serial4 = &uart5;
12 };
13
14 chosen { 10 chosen {
15 stdout-path = &uart5; 11 stdout-path = &uart5;
16 bootargs = "console=ttyS4,115200 earlyprintk"; 12 bootargs = "console=ttyS4,115200 earlyprintk";
17 }; 13 };
18 14
19 memory { 15 memory@80000000 {
20 reg = <0x80000000 0x40000000>; 16 reg = <0x80000000 0x20000000>;
21 }; 17 };
22 18
23 reserved-memory { 19 reserved-memory {
@@ -29,6 +25,49 @@
29 no-map; 25 no-map;
30 reg = <0xbf000000 0x01000000>; /* 16M */ 26 reg = <0xbf000000 0x01000000>; /* 16M */
31 }; 27 };
28
29 flash_memory: region@98000000 {
30 no-map;
31 reg = <0x98000000 0x04000000>; /* 64M */
32 };
33 };
34
35 leds {
36 compatible = "gpio-leds";
37
38 fault {
39 gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
40 };
41
42 identify {
43 gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
44 };
45
46 power {
47 gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
48 };
49 };
50
51 fsi: gpio-fsi {
52 compatible = "fsi-master-gpio", "fsi-master";
53 #address-cells = <2>;
54 #size-cells = <0>;
55
56 clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
57 data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
58 mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
59 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
60 trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
61 };
62
63 gpio-keys {
64 compatible = "gpio-keys";
65
66 checkstop {
67 label = "checkstop";
68 gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
69 linux,code = <ASPEED_GPIO(J, 2)>;
70 };
32 }; 71 };
33}; 72};
34 73
@@ -38,6 +77,7 @@
38 status = "okay"; 77 status = "okay";
39 m25p,fast-read; 78 m25p,fast-read;
40 label = "bmc"; 79 label = "bmc";
80#include "openbmc-flash-layout.dtsi"
41 }; 81 };
42}; 82};
43 83
@@ -53,6 +93,12 @@
53 }; 93 };
54}; 94};
55 95
96&lpc_ctrl {
97 status = "okay";
98 memory-region = <&flash_memory>;
99 flash = <&spi1>;
100};
101
56&uart1 { 102&uart1 {
57 /* Rear RS-232 connector */ 103 /* Rear RS-232 connector */
58 status = "okay"; 104 status = "okay";
@@ -81,6 +127,10 @@
81 pinctrl-0 = <&pinctrl_rmii1_default>; 127 pinctrl-0 = <&pinctrl_rmii1_default>;
82}; 128};
83 129
130&i2c1 {
131 status = "okay";
132};
133
84&i2c2 { 134&i2c2 {
85 status = "okay"; 135 status = "okay";
86}; 136};
@@ -133,8 +183,77 @@
133 183
134&i2c12 { 184&i2c12 {
135 status = "okay"; 185 status = "okay";
186
187 max31785@52 {
188 compatible = "maxim,max31785";
189 reg = <0x52>;
190 };
191};
192
193&gpio {
194 nic_func_mode0 {
195 gpio-hog;
196 gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
197 output-low;
198 line-name = "nic_func_mode0";
199 };
200 nic_func_mode1 {
201 gpio-hog;
202 gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
203 output-low;
204 line-name = "nic_func_mode1";
205 };
136}; 206};
137 207
138&vuart { 208&vuart {
139 status = "okay"; 209 status = "okay";
140}; 210};
211
212&gfx {
213 status = "okay";
214};
215
216&pinctrl {
217 aspeed,external-nodes = <&gfx &lhc>;
218};
219
220&pwm_tacho {
221 status = "okay";
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
224
225 fan@0 {
226 reg = <0x00>;
227 aspeed,fan-tach-ch = /bits/ 8 <0x08>;
228 };
229
230 fan@1 {
231 reg = <0x00>;
232 aspeed,fan-tach-ch = /bits/ 8 <0x09>;
233 };
234
235 fan@2 {
236 reg = <0x01>;
237 aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
238 };
239
240 fan@3 {
241 reg = <0x01>;
242 aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
243 };
244
245 fan@4 {
246 reg = <0x00>;
247 aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
248 };
249
250 fan@5 {
251 reg = <0x00>;
252 aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
253 };
254
255 fan@6 {
256 reg = <0x01>;
257 aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
258 };
259};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
new file mode 100644
index 000000000000..5f9049d2c4c3
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -0,0 +1,548 @@
1// SPDX-License-Identifier: GPL-2.0+
2/dts-v1/;
3#include "aspeed-g5.dtsi"
4#include <dt-bindings/gpio/aspeed-gpio.h>
5#include <dt-bindings/leds/leds-pca955x.h>
6
7/ {
8 model = "Witherspoon BMC";
9 compatible = "ibm,witherspoon-bmc", "aspeed,ast2500";
10
11 chosen {
12 stdout-path = &uart5;
13 bootargs = "console=ttyS4,115200 earlyprintk";
14 };
15
16 memory@80000000 {
17 reg = <0x80000000 0x20000000>;
18 };
19
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges;
24
25 flash_memory: region@98000000 {
26 no-map;
27 reg = <0x98000000 0x04000000>; /* 64M */
28 };
29 };
30
31 gpio-keys-polled {
32 compatible = "gpio-keys-polled";
33 #address-cells = <1>;
34 #size-cells = <0>;
35 poll-interval = <1000>;
36
37 fan0-presence {
38 label = "fan0-presence";
39 gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
40 linux,code = <4>;
41 };
42
43 fan1-presence {
44 label = "fan1-presence";
45 gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
46 linux,code = <5>;
47 };
48
49 fan2-presence {
50 label = "fan2-presence";
51 gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
52 linux,code = <6>;
53 };
54
55 fan3-presence {
56 label = "fan3-presence";
57 gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
58 linux,code = <7>;
59 };
60 };
61
62 leds {
63 compatible = "gpio-leds";
64
65 fan0 {
66 retain-state-shutdown;
67 default-state = "keep";
68 gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
69 };
70
71 fan1 {
72 retain-state-shutdown;
73 default-state = "keep";
74 gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
75 };
76
77 fan2 {
78 retain-state-shutdown;
79 default-state = "keep";
80 gpios = <&pca0 2 GPIO_ACTIVE_LOW>;
81 };
82
83 fan3 {
84 retain-state-shutdown;
85 default-state = "keep";
86 gpios = <&pca0 3 GPIO_ACTIVE_LOW>;
87 };
88
89 front-fault {
90 retain-state-shutdown;
91 default-state = "keep";
92 gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
93 };
94
95 front-power {
96 retain-state-shutdown;
97 default-state = "keep";
98 gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
99 };
100
101 front-id {
102 retain-state-shutdown;
103 default-state = "keep";
104 gpios = <&pca0 15 GPIO_ACTIVE_LOW>;
105 };
106
107 rear-fault {
108 gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
109 };
110
111 rear-id {
112 gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;
113 };
114
115 rear-power {
116 gpios = <&gpio ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>;
117 };
118
119 power-button {
120 gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
121 };
122 };
123
124 fsi: gpio-fsi {
125 compatible = "fsi-master-gpio", "fsi-master";
126 #address-cells = <2>;
127 #size-cells = <0>;
128
129 clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
130 data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
131 mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
132 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
133 trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
134 };
135
136 iio-hwmon-dps310 {
137 compatible = "iio-hwmon";
138 io-channels = <&dps 0>;
139 };
140
141 iio-hwmon-bmp280 {
142 compatible = "iio-hwmon";
143 io-channels = <&bmp 1>;
144 };
145
146};
147
148&fmc {
149 status = "okay";
150
151 flash@0 {
152 status = "okay";
153 label = "bmc";
154 m25p,fast-read;
155#include "openbmc-flash-layout.dtsi"
156 };
157
158 flash@1 {
159 status = "okay";
160 label = "alt";
161 m25p,fast-read;
162 };
163};
164
165&spi1 {
166 status = "okay";
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_spi1_default>;
169
170 flash@0 {
171 status = "okay";
172 label = "pnor";
173 m25p,fast-read;
174 };
175};
176
177&uart1 {
178 /* Rear RS-232 connector */
179 status = "okay";
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_txd1_default
182 &pinctrl_rxd1_default
183 &pinctrl_nrts1_default
184 &pinctrl_ndtr1_default
185 &pinctrl_ndsr1_default
186 &pinctrl_ncts1_default
187 &pinctrl_ndcd1_default
188 &pinctrl_nri1_default>;
189};
190
191&uart2 {
192 /* APSS */
193 status = "okay";
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
196};
197
198&uart5 {
199 status = "okay";
200};
201
202&lpc_ctrl {
203 status = "okay";
204 memory-region = <&flash_memory>;
205 flash = <&spi1>;
206};
207
208&mac0 {
209 status = "okay";
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_rmii1_default>;
212 use-ncsi;
213};
214
215&i2c2 {
216 status = "okay";
217
218 /* MUX ->
219 * Samtec 1
220 * Samtec 2
221 */
222};
223
224&i2c3 {
225 status = "okay";
226
227 bmp: bmp280@77 {
228 compatible = "bosch,bmp280";
229 reg = <0x77>;
230 #io-channel-cells = <1>;
231 };
232
233 max31785@52 {
234 compatible = "maxim,max31785a";
235 reg = <0x52>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 dps: dps310@76 {
241 compatible = "infineon,dps310";
242 reg = <0x76>;
243 #io-channel-cells = <0>;
244 };
245
246 pca0: pca9552@60 {
247 compatible = "nxp,pca9552";
248 reg = <0x60>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251
252 gpio-controller;
253 #gpio-cells = <2>;
254
255 gpio@0 {
256 reg = <0>;
257 type = <PCA955X_TYPE_GPIO>;
258 };
259
260 gpio@1 {
261 reg = <1>;
262 type = <PCA955X_TYPE_GPIO>;
263 };
264
265 gpio@2 {
266 reg = <2>;
267 type = <PCA955X_TYPE_GPIO>;
268 };
269
270 gpio@3 {
271 reg = <3>;
272 type = <PCA955X_TYPE_GPIO>;
273 };
274
275 gpio@4 {
276 reg = <4>;
277 type = <PCA955X_TYPE_GPIO>;
278 };
279
280 gpio@5 {
281 reg = <5>;
282 type = <PCA955X_TYPE_GPIO>;
283 };
284
285 gpio@6 {
286 reg = <6>;
287 type = <PCA955X_TYPE_GPIO>;
288 };
289
290 gpio@7 {
291 reg = <7>;
292 type = <PCA955X_TYPE_GPIO>;
293 };
294
295 gpio@8 {
296 reg = <8>;
297 type = <PCA955X_TYPE_GPIO>;
298 };
299
300 gpio@9 {
301 reg = <9>;
302 type = <PCA955X_TYPE_GPIO>;
303 };
304
305 gpio@10 {
306 reg = <10>;
307 type = <PCA955X_TYPE_GPIO>;
308 };
309
310 gpio@11 {
311 reg = <11>;
312 type = <PCA955X_TYPE_GPIO>;
313 };
314
315 gpio@12 {
316 reg = <12>;
317 type = <PCA955X_TYPE_GPIO>;
318 };
319
320 gpio@13 {
321 reg = <13>;
322 type = <PCA955X_TYPE_GPIO>;
323 };
324
325 gpio@14 {
326 reg = <14>;
327 type = <PCA955X_TYPE_GPIO>;
328 };
329
330 gpio@15 {
331 reg = <15>;
332 type = <PCA955X_TYPE_GPIO>;
333 };
334 };
335
336 power-supply@68 {
337 compatible = "ibm,cffps1";
338 reg = <0x68>;
339 };
340
341 power-supply@69 {
342 compatible = "ibm,cffps1";
343 reg = <0x69>;
344 };
345};
346
347&i2c4 {
348 status = "okay";
349
350 tmp423a@4c {
351 compatible = "ti,tmp423";
352 reg = <0x4c>;
353 };
354
355 ir35221@70 {
356 compatible = "infineon,ir35221";
357 reg = <0x70>;
358 };
359
360 ir35221@71 {
361 compatible = "infineon,ir35221";
362 reg = <0x71>;
363 };
364};
365
366
367&i2c5 {
368 status = "okay";
369
370 tmp423a@4c {
371 compatible = "ti,tmp423";
372 reg = <0x4c>;
373 };
374
375 ir35221@70 {
376 compatible = "infineon,ir35221";
377 reg = <0x70>;
378 };
379
380 ir35221@71 {
381 compatible = "infineon,ir35221";
382 reg = <0x71>;
383 };
384};
385
386&i2c9 {
387 status = "okay";
388
389 tmp275@4a {
390 compatible = "ti,tmp275";
391 reg = <0x4a>;
392 };
393};
394
395&i2c10 {
396 /* MUX
397 * -> PCIe Slot 3
398 * -> PCIe Slot 4
399 */
400 status = "okay";
401};
402
403&i2c11 {
404 status = "okay";
405
406 pca9552: pca9552@60 {
407 compatible = "nxp,pca9552";
408 reg = <0x60>;
409 #address-cells = <1>;
410 #size-cells = <0>;
411 gpio-controller;
412 #gpio-cells = <2>;
413
414 gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
415 "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
416 "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
417 "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
418 "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
419 "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
420 "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
421 "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
422
423 gpio@0 {
424 reg = <0>;
425 type = <PCA955X_TYPE_GPIO>;
426 };
427
428 gpio@1 {
429 reg = <1>;
430 type = <PCA955X_TYPE_GPIO>;
431 };
432
433 gpio@2 {
434 reg = <2>;
435 type = <PCA955X_TYPE_GPIO>;
436 };
437
438 gpio@3 {
439 reg = <3>;
440 type = <PCA955X_TYPE_GPIO>;
441 };
442
443 gpio@4 {
444 reg = <4>;
445 type = <PCA955X_TYPE_GPIO>;
446 };
447
448 gpio@5 {
449 reg = <5>;
450 type = <PCA955X_TYPE_GPIO>;
451 };
452
453 gpio@6 {
454 reg = <6>;
455 type = <PCA955X_TYPE_GPIO>;
456 };
457
458 gpio@7 {
459 reg = <7>;
460 type = <PCA955X_TYPE_GPIO>;
461 };
462
463 gpio@8 {
464 reg = <8>;
465 type = <PCA955X_TYPE_GPIO>;
466 };
467
468 gpio@9 {
469 reg = <9>;
470 type = <PCA955X_TYPE_GPIO>;
471 };
472
473 gpio@10 {
474 reg = <10>;
475 type = <PCA955X_TYPE_GPIO>;
476 };
477
478 gpio@11 {
479 reg = <11>;
480 type = <PCA955X_TYPE_GPIO>;
481 };
482
483 gpio@12 {
484 reg = <12>;
485 type = <PCA955X_TYPE_GPIO>;
486 };
487
488 gpio@13 {
489 reg = <13>;
490 type = <PCA955X_TYPE_GPIO>;
491 };
492
493 gpio@14 {
494 reg = <14>;
495 type = <PCA955X_TYPE_GPIO>;
496 };
497
498 gpio@15 {
499 reg = <15>;
500 type = <PCA955X_TYPE_GPIO>;
501 };
502 };
503
504 rtc@32 {
505 compatible = "epson,rx8900";
506 reg = <0x32>;
507 };
508
509 eeprom@51 {
510 compatible = "atmel,24c64";
511 reg = <0x51>;
512 };
513
514 ucd90160@64 {
515 compatible = "ti,ucd90160";
516 reg = <0x64>;
517 };
518};
519
520&i2c12 {
521 status = "okay";
522};
523
524&i2c13 {
525 status = "okay";
526};
527
528&vuart {
529 status = "okay";
530};
531
532&gfx {
533 status = "okay";
534};
535
536&pinctrl {
537 aspeed,external-nodes = <&gfx &lhc>;
538};
539
540&wdt1 {
541 aspeed,reset-type = "none";
542 aspeed,external-signal;
543 aspeed,ext-push-pull;
544 aspeed,ext-active-high;
545
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_wdtrst1_default>;
548};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
new file mode 100644
index 000000000000..c881484a85cf
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -0,0 +1,426 @@
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3#include "aspeed-g5.dtsi"
4#include <dt-bindings/gpio/aspeed-gpio.h>
5
6/ {
7 model = "Zaius BMC";
8 compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
9
10 chosen {
11 stdout-path = &uart5;
12 bootargs = "console=ttyS4,115200 earlyprintk";
13 };
14
15 memory@80000000 {
16 reg = <0x80000000 0x40000000>;
17 };
18
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 flash_memory: region@98000000 {
25 no-map;
26 reg = <0x98000000 0x04000000>; /* 64M */
27 };
28 };
29
30 onewire0 {
31 compatible = "w1-gpio";
32 gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
33 };
34
35 onewire1 {
36 compatible = "w1-gpio";
37 gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
38 };
39
40 onewire2 {
41 compatible = "w1-gpio";
42 gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
43 };
44
45 onewire3 {
46 compatible = "w1-gpio";
47 gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
48 };
49
50 gpio-keys {
51 compatible = "gpio-keys";
52
53 checkstop {
54 label = "checkstop";
55 gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
56 linux,code = <ASPEED_GPIO(F, 7)>;
57 };
58 };
59
60 leds {
61 compatible = "gpio-leds";
62
63 sys_boot_status {
64 label = "System boot status";
65 gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>;
66 };
67
68 attention {
69 label = "Attention";
70 gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>;
71 };
72
73 plt_fault {
74 label = "Platform fault";
75 gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>;
76 };
77
78 hdd_fault {
79 label = "Onboard drive fault";
80 gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
81 };
82 };
83
84 fsi: gpio-fsi {
85 compatible = "fsi-master-gpio", "fsi-master";
86 #address-cells = <2>;
87 #size-cells = <0>;
88
89 trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>;
90 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
91 clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
92 data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
93 mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
94 };
95
96 iio-hwmon {
97 compatible = "iio-hwmon";
98 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
99 <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
100 <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
101 <&adc 13>, <&adc 14>, <&adc 15>;
102 };
103
104 iio-hwmon-battery {
105 compatible = "iio-hwmon";
106 io-channels = <&adc 12>;
107 };
108
109};
110
111&fmc {
112 status = "okay";
113
114 flash@0 {
115 status = "okay";
116 label = "bmc";
117 m25p,fast-read;
118#include "openbmc-flash-layout.dtsi"
119 };
120};
121
122&spi1 {
123 status = "okay";
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_spi1_default>;
126
127 flash@0 {
128 status = "okay";
129 label = "pnor";
130 m25p,fast-read;
131 };
132};
133
134&spi2 {
135 status = "okay";
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_spi2ck_default
138 &pinctrl_spi2cs0_default
139 &pinctrl_spi2cs1_default
140 &pinctrl_spi2miso_default
141 &pinctrl_spi2mosi_default>;
142
143 flash@0 {
144 status = "okay";
145 };
146};
147
148&uart1 {
149 status = "okay";
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_txd1_default
152 &pinctrl_rxd1_default>;
153};
154
155&lpc_ctrl {
156 status = "okay";
157 memory-region = <&flash_memory>;
158 flash = <&spi1>;
159};
160
161&lpc_snoop {
162 status = "okay";
163 snoop-ports = <0x80>;
164};
165
166
167&uart5 {
168 status = "okay";
169};
170
171&mac0 {
172 status = "okay";
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_rmii1_default>;
175 use-ncsi;
176};
177
178&mac1 {
179 status = "okay";
180
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
183};
184
185&i2c0 {
186 status = "okay";
187
188 eeprom@50 {
189 compatible = "atmel,24c64";
190 reg = <0x50>;
191 pagesize = <32>;
192 };
193
194 rtc@68 {
195 compatible = "nxp,pcf8523";
196 reg = <0x68>;
197 };
198
199 ucd90160@64 {
200 compatible = "ti,ucd90160";
201 reg = <0x64>;
202 };
203
204 /* Power sequencer UCD90160 PMBUS @64h
205 * FRU AT24C64D @50h
206 * RTC PCF8523 @68h
207 * Clock buffer 9DBL04 @6dh
208 */
209};
210
211&i2c1 {
212 status = "okay";
213
214 i2c-switch@71 {
215 compatible = "nxp,pca9546";
216 reg = <0x71>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 };
220
221 /* MUX1 PCA9546A @71h
222 * PCIe 0
223 * PCIe 1
224 * PCIe 2
225 * TPM header
226 */
227};
228
229&i2c2 {
230 status = "disabled";
231
232 /* OCP Mezz Connector A (OOB SMBUS) */
233};
234
235&i2c3 {
236 status = "disabled";
237
238 /* OCP Mezz Connector A (PCIe slot SMBUS) */
239};
240
241&i2c4 {
242 status = "okay";
243
244 i2c-switch@71 {
245 compatible = "nxp,pca9546";
246 reg = <0x71>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 };
250
251 /* MUX1 PCA9546A @71h
252 * PCIe 3
253 * PCIe 4
254 */
255};
256
257
258&i2c5 {
259 status = "disabled";
260
261 /* CPU0 PRM 0.7V */
262 /* CPU0 PRM 1.2V CH03 */
263 /* CPU0 PRM 0.8V */
264 /* CPU0 PRM 1.2V CH47 */
265};
266
267&i2c6 {
268 status = "disabled";
269
270 /* CPU1 PRM 0.7V */
271 /* CPU1 PRM 1.2V CH03 */
272 /* CPU1 PRM 0.8V */
273 /* CPU1 PRM 1.2V CH47 */
274};
275
276&i2c7 {
277 status = "okay";
278
279 pca9541a@70 {
280 compatible = "nxp,pca9541";
281 reg = <0x70>;
282
283 i2c-arb {
284 #address-cells = <1>;
285 #size-cells = <0>;
286
287 hotswap@54 {
288 compatible = "ti,lm5066i";
289 reg = <0x54>;
290 };
291 };
292 };
293
294 /* Master selector PCA9541A @70h (other master: CPU0)
295 * LM5066I PMBUS @10h
296 */
297
298 /* 12V Quarter Brick DC/DC Converter Q54SJ12050 @61h */
299 power-brick@61 {
300 compatible = "delta,dps800";
301 reg = <0x61>;
302 };
303
304 /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
305 /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
306 /* CPU0 VR ISL68137 0.8V PMBUS @60h */
307 /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
308 /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
309};
310
311&i2c8 {
312 status = "okay";
313
314 /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
315 /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
316 /* CPU1 VR ISL68137 0.8V PMBUS @61h */
317 /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
318 /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
319};
320
321
322&i2c9 {
323 status = "disabled";
324
325 /* Fan board */
326};
327
328&i2c10 {
329 status = "disabled";
330};
331
332&i2c11 {
333 status = "disabled";
334
335 /* GPU sideband */
336};
337
338&i2c12 {
339 status = "disabled";
340};
341
342&i2c13 {
343 status = "disabled";
344
345 /* MUX PI3USB102
346 * CPU0 debug
347 * CPU1 debug
348 */
349};
350
351&pinctrl {
352 aspeed,external-nodes = <&gfx &lhc>;
353
354 pinctrl_gpioh_unbiased: gpioi_unbiased {
355 pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
356 bias-disable;
357 };
358};
359
360&gpio {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_gpioh_unbiased>;
363
364 line_iso_u146_en {
365 gpio-hog;
366 gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>;
367 output-high;
368 line-name = "iso_u164_en";
369 };
370
371 ncsi_mux_en_n {
372 gpio-hog;
373 gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
374 output-low;
375 line-name = "ncsi_mux_en_n";
376 };
377
378 line_bmc_i2c2_sw_rst_n {
379 gpio-hog;
380 gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
381 output-high;
382 line-name = "bmc_i2c2_sw_rst_n";
383 };
384
385 line_bmc_i2c5_sw_rst_n {
386 gpio-hog;
387 gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
388 output-high;
389 line-name = "bmc_i2c5_sw_rst_n";
390 };
391};
392
393&vuart {
394 status = "okay";
395};
396
397&gfx {
398 status = "okay";
399};
400
401&pwm_tacho {
402 status = "okay";
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
405 &pinctrl_pwm2_default &pinctrl_pwm3_default>;
406
407 fan@0 {
408 reg = <0x00>;
409 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
410 };
411
412 fan@1 {
413 reg = <0x01>;
414 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
415 };
416
417 fan@2 {
418 reg = <0x02>;
419 aspeed,fan-tach-ch = /bits/ 8 <0x02>;
420 };
421
422 fan@3 {
423 reg = <0x03>;
424 aspeed,fan-tach-ch = /bits/ 8 <0x03>;
425 };
426};
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
new file mode 100644
index 000000000000..76aa6ea1f988
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
@@ -0,0 +1,458 @@
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3#include "aspeed-g4.dtsi"
4#include <dt-bindings/gpio/aspeed-gpio.h>
5
6/ {
7 model = "Quanta Q71L BMC";
8 compatible = "quanta,q71l-bmc", "aspeed,ast2400";
9
10 chosen {
11 stdout-path = &uart5;
12 bootargs = "console=ttyS4,115200 earlyprintk";
13 };
14
15 memory@40000000 {
16 reg = <0x40000000 0x8000000>;
17 };
18
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 vga_memory: framebuffer@47800000 {
25 no-map;
26 reg = <0x47800000 0x00800000>; /* 8MB */
27 };
28 };
29
30 leds {
31 compatible = "gpio-leds";
32
33 heartbeat {
34 gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
35 };
36
37 power {
38 gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
39 };
40
41 identify {
42 gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
43 };
44 };
45
46 iio-hwmon {
47 compatible = "iio-hwmon";
48 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
49 <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
50 <&adc 8>, <&adc 9>, <&adc 10>;
51 };
52
53 iio-hwmon-battery {
54 compatible = "iio-hwmon";
55 io-channels = <&adc 11>;
56 };
57
58 i2c1mux: i2cmux {
59 compatible = "i2c-mux-gpio";
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
64 i2c-parent = <&i2c1>;
65 };
66};
67
68&fmc {
69 status = "okay";
70 flash@0 {
71 status = "okay";
72 label = "bmc";
73 m25p,fast-read;
74#include "openbmc-flash-layout.dtsi"
75 };
76};
77
78&spi {
79 status = "okay";
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_spi1_default>;
82
83 flash@0 {
84 status = "okay";
85 m25p,fast-read;
86 label = "pnor";
87 };
88};
89
90&pinctrl {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
93 &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
94};
95
96&lpc_snoop {
97 status = "okay";
98 snoop-ports = <0x80>;
99};
100
101&mac0 {
102 status = "okay";
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_rmii1_default>;
105 use-ncsi;
106};
107
108&mac1 {
109 status = "okay";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
112};
113
114&uart5 {
115 status = "okay";
116};
117
118&i2c0 {
119 status = "okay";
120};
121
122&i2c1 {
123 status = "okay";
124
125 /* temp2 inlet */
126 tmp75@4c {
127 compatible = "ti,tmp75";
128 reg = <0x4c>;
129 };
130
131 /* temp3 */
132 tmp75@4e {
133 compatible = "ti,tmp75";
134 reg = <0x4e>;
135 };
136
137 /* temp1 */
138 tmp75@4f {
139 compatible = "ti,tmp75";
140 reg = <0x4f>;
141 };
142
143 /* Baseboard FRU */
144 eeprom@54 {
145 compatible = "atmel,24c64";
146 reg = <0x54>;
147 };
148
149 /* FP FRU */
150 eeprom@57 {
151 compatible = "atmel,24c64";
152 reg = <0x57>;
153 };
154};
155
156&i2c2 {
157 status = "okay";
158
159 /* 0: PCIe Slot 2,
160 * Slot 3,
161 * Slot 6,
162 * Slot 7
163 */
164 i2c-switch@74 {
165 compatible = "nxp,pca9546";
166 reg = <0x74>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 i2c-mux-idle-disconnect; /* may use mux@77 next. */
170
171 i2c_pcie2: i2c@0 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 reg = <0>;
175 };
176
177 i2c_pcie3: i2c@1 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 reg = <1>;
181 };
182
183 i2c_pcie6: i2c@2 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 reg = <2>;
187 };
188
189 i2c_pcie7: i2c@3 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 reg = <3>;
193 };
194 };
195
196 /* 0: PCIe Slot 1,
197 * Slot 4,
198 * Slot 5,
199 * Slot 8,
200 * Slot 9,
201 * Slot 10,
202 * SSD 1,
203 * SSD 2
204 */
205 i2c-switch@77 {
206 compatible = "nxp,pca9548";
207 #address-cells = <1>;
208 #size-cells = <0>;
209 reg = <0x77>;
210 i2c-mux-idle-disconnect; /* may use mux@74 next. */
211
212 i2c_pcie1: i2c@0 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 reg = <0>;
216 };
217
218 i2c_pcie4: i2c@1 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 reg = <1>;
222 };
223
224 i2c_pcie5: i2c@2 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 reg = <2>;
228 };
229
230 i2c_pcie8: i2c@3 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <3>;
234 };
235
236 i2c_pcie9: i2c@4 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 reg = <4>;
240 };
241
242 i2c_pcie10: i2c@5 {
243 #address-cells = <1>;
244 #size-cells = <0>;
245 reg = <5>;
246 };
247
248 i2c_ssd1: i2c@6 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 reg = <6>;
252 };
253
254 i2c_ssd2: i2c@7 {
255 #address-cells = <1>;
256 #size-cells = <0>;
257 reg = <7>;
258 };
259 };
260};
261
262&i2c3 {
263 status = "okay";
264
265 /* BIOS FRU */
266 eeprom@56 {
267 compatible = "atmel,24c64";
268 reg = <0x56>;
269 };
270};
271
272&i2c4 {
273 status = "okay";
274};
275
276&i2c5 {
277 status = "okay";
278};
279
280&i2c6 {
281 status = "okay";
282};
283
284&i2c7 {
285 status = "okay";
286
287 /* 0: PSU4
288 * PSU1
289 * PSU3
290 * PSU2
291 */
292 i2c-switch@70 {
293 compatible = "nxp,pca9546";
294 reg = <0x70>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297
298 i2c_psu4: i2c@0 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <0>;
302 };
303
304 i2c_psu1: i2c@1 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 reg = <1>;
308 };
309
310 i2c_psu3: i2c@2 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <2>;
314 };
315
316 i2c_psu2: i2c@3 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 reg = <3>;
320 };
321 };
322
323 /* PDB FRU */
324 eeprom@52 {
325 compatible = "atmel,24c64";
326 reg = <0x52>;
327 };
328};
329
330&i2c8 {
331 status = "okay";
332
333 /* BMC FRU */
334 eeprom@50 {
335 compatible = "atmel,24c64";
336 reg = <0x50>;
337 };
338};
339
340&vuart {
341 status = "okay";
342};
343
344&wdt2 {
345 status = "okay";
346};
347
348&pwm_tacho {
349 status = "okay";
350
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_pwm0_default
353 &pinctrl_pwm1_default
354 &pinctrl_pwm2_default
355 &pinctrl_pwm3_default>;
356
357 fan@0 {
358 reg = <0x00>;
359 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
360 };
361
362 fan@1 {
363 reg = <0x01>;
364 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
365 };
366
367 fan@2 {
368 reg = <0x02>;
369 aspeed,fan-tach-ch = /bits/ 8 <0x02>;
370 };
371
372 fan@3 {
373 reg = <0x03>;
374 aspeed,fan-tach-ch = /bits/ 8 <0x03>;
375 };
376
377 fan@4 {
378 reg = <0x00>;
379 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
380 };
381
382 fan@5 {
383 reg = <0x01>;
384 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
385 };
386
387 fan@6 {
388 reg = <0x02>;
389 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
390 };
391
392 fan@7 {
393 reg = <0x03>;
394 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
395 };
396};
397
398&i2c1mux {
399 i2c@0 {
400 reg = <0>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403
404 /* Memory Riser 1 FRU */
405 eeprom@50 {
406 compatible = "atmel,24c02";
407 reg = <0x50>;
408 };
409
410 /* Memory Riser 2 FRU */
411 eeprom@51 {
412 compatible = "atmel,24c02";
413 reg = <0x51>;
414 };
415
416 /* Memory Riser 3 FRU */
417 eeprom@52 {
418 compatible = "atmel,24c02";
419 reg = <0x52>;
420 };
421
422 /* Memory Riser 4 FRU */
423 eeprom@53 {
424 compatible = "atmel,24c02";
425 reg = <0x53>;
426 };
427 };
428
429 i2c@1 {
430 reg = <1>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433
434 /* Memory Riser 5 FRU */
435 eeprom@50 {
436 compatible = "atmel,24c02";
437 reg = <0x50>;
438 };
439
440 /* Memory Riser 6 FRU */
441 eeprom@51 {
442 compatible = "atmel,24c02";
443 reg = <0x51>;
444 };
445
446 /* Memory Riser 7 FRU */
447 eeprom@52 {
448 compatible = "atmel,24c02";
449 reg = <0x52>;
450 };
451
452 /* Memory Riser 8 FRU */
453 eeprom@53 {
454 compatible = "atmel,24c02";
455 reg = <0x53>;
456 };
457 };
458};
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 45d815a86d42..b0d8431a3700 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -1,5 +1,5 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2#include "skeleton.dtsi" 2#include <dt-bindings/clock/aspeed-clock.h>
3 3
4/ { 4/ {
5 model = "Aspeed BMC"; 5 model = "Aspeed BMC";
@@ -54,6 +54,7 @@
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <0>; 55 #size-cells = <0>;
56 compatible = "aspeed,ast2400-fmc"; 56 compatible = "aspeed,ast2400-fmc";
57 clocks = <&syscon ASPEED_CLK_AHB>;
57 status = "disabled"; 58 status = "disabled";
58 interrupts = <19>; 59 interrupts = <19>;
59 flash@0 { 60 flash@0 {
@@ -69,6 +70,7 @@
69 #address-cells = <1>; 70 #address-cells = <1>;
70 #size-cells = <0>; 71 #size-cells = <0>;
71 compatible = "aspeed,ast2400-spi"; 72 compatible = "aspeed,ast2400-spi";
73 clocks = <&syscon ASPEED_CLK_AHB>;
72 status = "disabled"; 74 status = "disabled";
73 flash@0 { 75 flash@0 {
74 reg = < 0 >; 76 reg = < 0 >;
@@ -89,6 +91,7 @@
89 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 91 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
90 reg = <0x1e660000 0x180>; 92 reg = <0x1e660000 0x180>;
91 interrupts = <2>; 93 interrupts = <2>;
94 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
92 status = "disabled"; 95 status = "disabled";
93 }; 96 };
94 97
@@ -96,6 +99,7 @@
96 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; 99 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
97 reg = <0x1e680000 0x180>; 100 reg = <0x1e680000 0x180>;
98 interrupts = <3>; 101 interrupts = <3>;
102 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
99 status = "disabled"; 103 status = "disabled";
100 }; 104 };
101 105
@@ -106,47 +110,12 @@
106 ranges; 110 ranges;
107 111
108 syscon: syscon@1e6e2000 { 112 syscon: syscon@1e6e2000 {
109 compatible = "aspeed,g4-scu", "syscon", "simple-mfd"; 113 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
110 reg = <0x1e6e2000 0x1a8>; 114 reg = <0x1e6e2000 0x1a8>;
111 #address-cells = <1>; 115 #address-cells = <1>;
112 #size-cells = <0>; 116 #size-cells = <0>;
113 117 #clock-cells = <1>;
114 clk_clkin: clk_clkin { 118 #reset-cells = <1>;
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
117 clock-frequency = <48000000>;
118 };
119
120 clk_hpll: clk_hpll@70 {
121 #clock-cells = <0>;
122 compatible = "aspeed,g4-hpll-clock", "fixed-clock";
123 reg = <0x70>;
124 clocks = <&clk_clkin>;
125 clock-frequency = <384000000>;
126 };
127
128 clk_ahb: clk_ahb@70 {
129 #clock-cells = <0>;
130 compatible = "aspeed,g4-ahb-clock", "fixed-clock";
131 reg = <0x70>;
132 clocks = <&clk_hpll>;
133 clock-frequency = <192000000>;
134 };
135
136 clk_apb: clk_apb@8 {
137 #clock-cells = <0>;
138 compatible = "aspeed,g4-apb-clock", "fixed-clock";
139 reg = <0x08>;
140 clocks = <&clk_hpll>;
141 clock-frequency = <48000000>;
142 };
143
144 clk_uart: clk_uart@2c{
145 #clock-cells = <0>;
146 compatible = "aspeed,g4-uart-clock", "fixed-clock";
147 reg = <0x2c>;
148 clock-frequency = <24000000>;
149 };
150 119
151 pinctrl: pinctrl { 120 pinctrl: pinctrl {
152 compatible = "aspeed,g4-pinctrl"; 121 compatible = "aspeed,g4-pinctrl";
@@ -156,7 +125,8 @@
156 adc: adc@1e6e9000 { 125 adc: adc@1e6e9000 {
157 compatible = "aspeed,ast2400-adc"; 126 compatible = "aspeed,ast2400-adc";
158 reg = <0x1e6e9000 0xb0>; 127 reg = <0x1e6e9000 0xb0>;
159 clocks = <&clk_apb>; 128 clocks = <&syscon ASPEED_CLK_APB>;
129 resets = <&syscon ASPEED_RESET_ADC>;
160 #io-channel-cells = <1>; 130 #io-channel-cells = <1>;
161 status = "disabled"; 131 status = "disabled";
162 }; 132 };
@@ -173,6 +143,7 @@
173 reg = <0x1e780000 0x1000>; 143 reg = <0x1e780000 0x1000>;
174 interrupts = <20>; 144 interrupts = <20>;
175 gpio-ranges = <&pinctrl 0 0 220>; 145 gpio-ranges = <&pinctrl 0 0 220>;
146 clocks = <&syscon ASPEED_CLK_APB>;
176 interrupt-controller; 147 interrupt-controller;
177 }; 148 };
178 149
@@ -181,7 +152,7 @@
181 compatible = "aspeed,ast2400-timer"; 152 compatible = "aspeed,ast2400-timer";
182 reg = <0x1e782000 0x90>; 153 reg = <0x1e782000 0x90>;
183 interrupts = <16 17 18 35 36 37 38 39>; 154 interrupts = <16 17 18 35 36 37 38 39>;
184 clocks = <&clk_apb>; 155 clocks = <&syscon ASPEED_CLK_APB>;
185 clock-names = "PCLK"; 156 clock-names = "PCLK";
186 }; 157 };
187 158
@@ -190,7 +161,7 @@
190 reg = <0x1e783000 0x20>; 161 reg = <0x1e783000 0x20>;
191 reg-shift = <2>; 162 reg-shift = <2>;
192 interrupts = <9>; 163 interrupts = <9>;
193 clocks = <&clk_uart>; 164 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
194 no-loopback-test; 165 no-loopback-test;
195 status = "disabled"; 166 status = "disabled";
196 }; 167 };
@@ -200,7 +171,7 @@
200 reg = <0x1e784000 0x20>; 171 reg = <0x1e784000 0x20>;
201 reg-shift = <2>; 172 reg-shift = <2>;
202 interrupts = <10>; 173 interrupts = <10>;
203 clocks = <&clk_uart>; 174 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
204 no-loopback-test; 175 no-loopback-test;
205 status = "disabled"; 176 status = "disabled";
206 }; 177 };
@@ -208,29 +179,83 @@
208 wdt1: watchdog@1e785000 { 179 wdt1: watchdog@1e785000 {
209 compatible = "aspeed,ast2400-wdt"; 180 compatible = "aspeed,ast2400-wdt";
210 reg = <0x1e785000 0x1c>; 181 reg = <0x1e785000 0x1c>;
182 clocks = <&syscon ASPEED_CLK_APB>;
211 }; 183 };
212 184
213 wdt2: watchdog@1e785020 { 185 wdt2: watchdog@1e785020 {
214 compatible = "aspeed,ast2400-wdt"; 186 compatible = "aspeed,ast2400-wdt";
215 reg = <0x1e785020 0x1c>; 187 reg = <0x1e785020 0x1c>;
188 clocks = <&syscon ASPEED_CLK_APB>;
189 };
190
191 pwm_tacho: pwm-tacho-controller@1e786000 {
192 compatible = "aspeed,ast2400-pwm-tacho";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 reg = <0x1e786000 0x1000>;
196 clocks = <&syscon ASPEED_CLK_APB>;
197 resets = <&syscon ASPEED_RESET_PWM>;
198 status = "disabled";
216 }; 199 };
217 200
218 vuart: serial@1e787000 { 201 vuart: serial@1e787000 {
219 compatible = "aspeed,ast2400-vuart"; 202 compatible = "aspeed,ast2400-vuart";
220 reg = <0x1e787000 0x40>; 203 reg = <0x1e787000 0x40>;
221 reg-shift = <2>; 204 reg-shift = <2>;
222 interrupts = <10>; 205 interrupts = <8>;
223 clocks = <&clk_uart>; 206 clocks = <&syscon ASPEED_CLK_APB>;
224 no-loopback-test; 207 no-loopback-test;
225 status = "disabled"; 208 status = "disabled";
226 }; 209 };
227 210
211 lpc: lpc@1e789000 {
212 compatible = "aspeed,ast2400-lpc", "simple-mfd";
213 reg = <0x1e789000 0x1000>;
214
215 #address-cells = <1>;
216 #size-cells = <1>;
217 ranges = <0x0 0x1e789000 0x1000>;
218
219 lpc_bmc: lpc-bmc@0 {
220 compatible = "aspeed,ast2400-lpc-bmc";
221 reg = <0x0 0x80>;
222 };
223
224 lpc_host: lpc-host@80 {
225 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
226 reg = <0x80 0x1e0>;
227 reg-io-width = <4>;
228
229 #address-cells = <1>;
230 #size-cells = <1>;
231 ranges = <0x0 0x80 0x1e0>;
232
233 lpc_ctrl: lpc-ctrl@0 {
234 compatible = "aspeed,ast2400-lpc-ctrl";
235 reg = <0x0 0x80>;
236 status = "disabled";
237 };
238
239 lpc_snoop: lpc-snoop@0 {
240 compatible = "aspeed,ast2400-lpc-snoop";
241 reg = <0x0 0x80>;
242 interrupts = <8>;
243 status = "disabled";
244 };
245
246 lhc: lhc@20 {
247 compatible = "aspeed,ast2400-lhc";
248 reg = <0x20 0x24 0x48 0x8>;
249 };
250 };
251 };
252
228 uart2: serial@1e78d000 { 253 uart2: serial@1e78d000 {
229 compatible = "ns16550a"; 254 compatible = "ns16550a";
230 reg = <0x1e78d000 0x20>; 255 reg = <0x1e78d000 0x20>;
231 reg-shift = <2>; 256 reg-shift = <2>;
232 interrupts = <32>; 257 interrupts = <32>;
233 clocks = <&clk_uart>; 258 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
234 no-loopback-test; 259 no-loopback-test;
235 status = "disabled"; 260 status = "disabled";
236 }; 261 };
@@ -240,7 +265,7 @@
240 reg = <0x1e78e000 0x20>; 265 reg = <0x1e78e000 0x20>;
241 reg-shift = <2>; 266 reg-shift = <2>;
242 interrupts = <33>; 267 interrupts = <33>;
243 clocks = <&clk_uart>; 268 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
244 no-loopback-test; 269 no-loopback-test;
245 status = "disabled"; 270 status = "disabled";
246 }; 271 };
@@ -250,7 +275,7 @@
250 reg = <0x1e78f000 0x20>; 275 reg = <0x1e78f000 0x20>;
251 reg-shift = <2>; 276 reg-shift = <2>;
252 interrupts = <34>; 277 interrupts = <34>;
253 clocks = <&clk_uart>; 278 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
254 no-loopback-test; 279 no-loopback-test;
255 status = "disabled"; 280 status = "disabled";
256 }; 281 };
@@ -281,7 +306,8 @@
281 306
282 reg = <0x40 0x40>; 307 reg = <0x40 0x40>;
283 compatible = "aspeed,ast2400-i2c-bus"; 308 compatible = "aspeed,ast2400-i2c-bus";
284 clocks = <&clk_apb>; 309 clocks = <&syscon ASPEED_CLK_APB>;
310 resets = <&syscon ASPEED_RESET_I2C>;
285 bus-frequency = <100000>; 311 bus-frequency = <100000>;
286 interrupts = <0>; 312 interrupts = <0>;
287 interrupt-parent = <&i2c_ic>; 313 interrupt-parent = <&i2c_ic>;
@@ -296,7 +322,8 @@
296 322
297 reg = <0x80 0x40>; 323 reg = <0x80 0x40>;
298 compatible = "aspeed,ast2400-i2c-bus"; 324 compatible = "aspeed,ast2400-i2c-bus";
299 clocks = <&clk_apb>; 325 clocks = <&syscon ASPEED_CLK_APB>;
326 resets = <&syscon ASPEED_RESET_I2C>;
300 bus-frequency = <100000>; 327 bus-frequency = <100000>;
301 interrupts = <1>; 328 interrupts = <1>;
302 interrupt-parent = <&i2c_ic>; 329 interrupt-parent = <&i2c_ic>;
@@ -311,7 +338,8 @@
311 338
312 reg = <0xc0 0x40>; 339 reg = <0xc0 0x40>;
313 compatible = "aspeed,ast2400-i2c-bus"; 340 compatible = "aspeed,ast2400-i2c-bus";
314 clocks = <&clk_apb>; 341 clocks = <&syscon ASPEED_CLK_APB>;
342 resets = <&syscon ASPEED_RESET_I2C>;
315 bus-frequency = <100000>; 343 bus-frequency = <100000>;
316 interrupts = <2>; 344 interrupts = <2>;
317 interrupt-parent = <&i2c_ic>; 345 interrupt-parent = <&i2c_ic>;
@@ -327,7 +355,8 @@
327 355
328 reg = <0x100 0x40>; 356 reg = <0x100 0x40>;
329 compatible = "aspeed,ast2400-i2c-bus"; 357 compatible = "aspeed,ast2400-i2c-bus";
330 clocks = <&clk_apb>; 358 clocks = <&syscon ASPEED_CLK_APB>;
359 resets = <&syscon ASPEED_RESET_I2C>;
331 bus-frequency = <100000>; 360 bus-frequency = <100000>;
332 interrupts = <3>; 361 interrupts = <3>;
333 interrupt-parent = <&i2c_ic>; 362 interrupt-parent = <&i2c_ic>;
@@ -343,7 +372,8 @@
343 372
344 reg = <0x140 0x40>; 373 reg = <0x140 0x40>;
345 compatible = "aspeed,ast2400-i2c-bus"; 374 compatible = "aspeed,ast2400-i2c-bus";
346 clocks = <&clk_apb>; 375 clocks = <&syscon ASPEED_CLK_APB>;
376 resets = <&syscon ASPEED_RESET_I2C>;
347 bus-frequency = <100000>; 377 bus-frequency = <100000>;
348 interrupts = <4>; 378 interrupts = <4>;
349 interrupt-parent = <&i2c_ic>; 379 interrupt-parent = <&i2c_ic>;
@@ -359,7 +389,8 @@
359 389
360 reg = <0x180 0x40>; 390 reg = <0x180 0x40>;
361 compatible = "aspeed,ast2400-i2c-bus"; 391 compatible = "aspeed,ast2400-i2c-bus";
362 clocks = <&clk_apb>; 392 clocks = <&syscon ASPEED_CLK_APB>;
393 resets = <&syscon ASPEED_RESET_I2C>;
363 bus-frequency = <100000>; 394 bus-frequency = <100000>;
364 interrupts = <5>; 395 interrupts = <5>;
365 interrupt-parent = <&i2c_ic>; 396 interrupt-parent = <&i2c_ic>;
@@ -375,7 +406,8 @@
375 406
376 reg = <0x1c0 0x40>; 407 reg = <0x1c0 0x40>;
377 compatible = "aspeed,ast2400-i2c-bus"; 408 compatible = "aspeed,ast2400-i2c-bus";
378 clocks = <&clk_apb>; 409 clocks = <&syscon ASPEED_CLK_APB>;
410 resets = <&syscon ASPEED_RESET_I2C>;
379 bus-frequency = <100000>; 411 bus-frequency = <100000>;
380 interrupts = <6>; 412 interrupts = <6>;
381 interrupt-parent = <&i2c_ic>; 413 interrupt-parent = <&i2c_ic>;
@@ -391,7 +423,8 @@
391 423
392 reg = <0x300 0x40>; 424 reg = <0x300 0x40>;
393 compatible = "aspeed,ast2400-i2c-bus"; 425 compatible = "aspeed,ast2400-i2c-bus";
394 clocks = <&clk_apb>; 426 clocks = <&syscon ASPEED_CLK_APB>;
427 resets = <&syscon ASPEED_RESET_I2C>;
395 bus-frequency = <100000>; 428 bus-frequency = <100000>;
396 interrupts = <7>; 429 interrupts = <7>;
397 interrupt-parent = <&i2c_ic>; 430 interrupt-parent = <&i2c_ic>;
@@ -407,7 +440,8 @@
407 440
408 reg = <0x340 0x40>; 441 reg = <0x340 0x40>;
409 compatible = "aspeed,ast2400-i2c-bus"; 442 compatible = "aspeed,ast2400-i2c-bus";
410 clocks = <&clk_apb>; 443 clocks = <&syscon ASPEED_CLK_APB>;
444 resets = <&syscon ASPEED_RESET_I2C>;
411 bus-frequency = <100000>; 445 bus-frequency = <100000>;
412 interrupts = <8>; 446 interrupts = <8>;
413 interrupt-parent = <&i2c_ic>; 447 interrupt-parent = <&i2c_ic>;
@@ -423,7 +457,8 @@
423 457
424 reg = <0x380 0x40>; 458 reg = <0x380 0x40>;
425 compatible = "aspeed,ast2400-i2c-bus"; 459 compatible = "aspeed,ast2400-i2c-bus";
426 clocks = <&clk_apb>; 460 clocks = <&syscon ASPEED_CLK_APB>;
461 resets = <&syscon ASPEED_RESET_I2C>;
427 bus-frequency = <100000>; 462 bus-frequency = <100000>;
428 interrupts = <9>; 463 interrupts = <9>;
429 interrupt-parent = <&i2c_ic>; 464 interrupt-parent = <&i2c_ic>;
@@ -439,7 +474,8 @@
439 474
440 reg = <0x3c0 0x40>; 475 reg = <0x3c0 0x40>;
441 compatible = "aspeed,ast2400-i2c-bus"; 476 compatible = "aspeed,ast2400-i2c-bus";
442 clocks = <&clk_apb>; 477 clocks = <&syscon ASPEED_CLK_APB>;
478 resets = <&syscon ASPEED_RESET_I2C>;
443 bus-frequency = <100000>; 479 bus-frequency = <100000>;
444 interrupts = <10>; 480 interrupts = <10>;
445 interrupt-parent = <&i2c_ic>; 481 interrupt-parent = <&i2c_ic>;
@@ -455,7 +491,8 @@
455 491
456 reg = <0x400 0x40>; 492 reg = <0x400 0x40>;
457 compatible = "aspeed,ast2400-i2c-bus"; 493 compatible = "aspeed,ast2400-i2c-bus";
458 clocks = <&clk_apb>; 494 clocks = <&syscon ASPEED_CLK_APB>;
495 resets = <&syscon ASPEED_RESET_I2C>;
459 bus-frequency = <100000>; 496 bus-frequency = <100000>;
460 interrupts = <11>; 497 interrupts = <11>;
461 interrupt-parent = <&i2c_ic>; 498 interrupt-parent = <&i2c_ic>;
@@ -471,7 +508,8 @@
471 508
472 reg = <0x440 0x40>; 509 reg = <0x440 0x40>;
473 compatible = "aspeed,ast2400-i2c-bus"; 510 compatible = "aspeed,ast2400-i2c-bus";
474 clocks = <&clk_apb>; 511 clocks = <&syscon ASPEED_CLK_APB>;
512 resets = <&syscon ASPEED_RESET_I2C>;
475 bus-frequency = <100000>; 513 bus-frequency = <100000>;
476 interrupts = <12>; 514 interrupts = <12>;
477 interrupt-parent = <&i2c_ic>; 515 interrupt-parent = <&i2c_ic>;
@@ -487,7 +525,8 @@
487 525
488 reg = <0x480 0x40>; 526 reg = <0x480 0x40>;
489 compatible = "aspeed,ast2400-i2c-bus"; 527 compatible = "aspeed,ast2400-i2c-bus";
490 clocks = <&clk_apb>; 528 clocks = <&syscon ASPEED_CLK_APB>;
529 resets = <&syscon ASPEED_RESET_I2C>;
491 bus-frequency = <100000>; 530 bus-frequency = <100000>;
492 interrupts = <13>; 531 interrupts = <13>;
493 interrupt-parent = <&i2c_ic>; 532 interrupt-parent = <&i2c_ic>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5c4ecdba3a6b..40de3b66c33f 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,5 +1,5 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0+
2#include "skeleton.dtsi" 2#include <dt-bindings/clock/aspeed-clock.h>
3 3
4/ { 4/ {
5 model = "Aspeed BMC"; 5 model = "Aspeed BMC";
@@ -54,6 +54,7 @@
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <0>; 55 #size-cells = <0>;
56 compatible = "aspeed,ast2500-fmc"; 56 compatible = "aspeed,ast2500-fmc";
57 clocks = <&syscon ASPEED_CLK_AHB>;
57 status = "disabled"; 58 status = "disabled";
58 interrupts = <19>; 59 interrupts = <19>;
59 flash@0 { 60 flash@0 {
@@ -79,6 +80,7 @@
79 #address-cells = <1>; 80 #address-cells = <1>;
80 #size-cells = <0>; 81 #size-cells = <0>;
81 compatible = "aspeed,ast2500-spi"; 82 compatible = "aspeed,ast2500-spi";
83 clocks = <&syscon ASPEED_CLK_AHB>;
82 status = "disabled"; 84 status = "disabled";
83 flash@0 { 85 flash@0 {
84 reg = < 0 >; 86 reg = < 0 >;
@@ -98,6 +100,7 @@
98 #address-cells = <1>; 100 #address-cells = <1>;
99 #size-cells = <0>; 101 #size-cells = <0>;
100 compatible = "aspeed,ast2500-spi"; 102 compatible = "aspeed,ast2500-spi";
103 clocks = <&syscon ASPEED_CLK_AHB>;
101 status = "disabled"; 104 status = "disabled";
102 flash@0 { 105 flash@0 {
103 reg = < 0 >; 106 reg = < 0 >;
@@ -123,6 +126,7 @@
123 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 126 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
124 reg = <0x1e660000 0x180>; 127 reg = <0x1e660000 0x180>;
125 interrupts = <2>; 128 interrupts = <2>;
129 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
126 status = "disabled"; 130 status = "disabled";
127 }; 131 };
128 132
@@ -130,6 +134,7 @@
130 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 134 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
131 reg = <0x1e680000 0x180>; 135 reg = <0x1e680000 0x180>;
132 interrupts = <3>; 136 interrupts = <3>;
137 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
133 status = "disabled"; 138 status = "disabled";
134 }; 139 };
135 140
@@ -140,55 +145,18 @@
140 ranges; 145 ranges;
141 146
142 syscon: syscon@1e6e2000 { 147 syscon: syscon@1e6e2000 {
143 compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; 148 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
144 reg = <0x1e6e2000 0x1a8>; 149 reg = <0x1e6e2000 0x1a8>;
145 #address-cells = <1>; 150 #address-cells = <1>;
146 #size-cells = <0>; 151 #size-cells = <0>;
147 152 #clock-cells = <1>;
148 clk_clkin: clk_clkin@70 { 153 #reset-cells = <1>;
149 #clock-cells = <0>;
150 compatible = "aspeed,g5-clkin-clock", "fixed-clock";
151 reg = <0x70>;
152 clock-frequency = <24000000>;
153 };
154
155 clk_hpll: clk_hpll@24 {
156 #clock-cells = <0>;
157 compatible = "aspeed,g5-hpll-clock", "fixed-clock";
158 reg = <0x24>;
159 clocks = <&clk_clkin>;
160 clock-frequency = <792000000>;
161 };
162
163 clk_ahb: clk_ahb@70 {
164 #clock-cells = <0>;
165 compatible = "aspeed,g5-ahb-clock", "fixed-clock";
166 reg = <0x70>;
167 clocks = <&clk_hpll>;
168 clock-frequency = <198000000>;
169 };
170
171 clk_apb: clk_apb@8 {
172 #clock-cells = <0>;
173 compatible = "aspeed,g5-apb-clock", "fixed-clock";
174 reg = <0x08>;
175 clocks = <&clk_hpll>;
176 clock-frequency = <24750000>;
177 };
178
179 clk_uart: clk_uart@2c {
180 #clock-cells = <0>;
181 compatible = "aspeed,uart-clock", "fixed-clock";
182 reg = <0x2c>;
183 clock-frequency = <24000000>;
184 };
185 154
186 pinctrl: pinctrl { 155 pinctrl: pinctrl {
187 compatible = "aspeed,g5-pinctrl"; 156 compatible = "aspeed,g5-pinctrl";
188 aspeed,external-nodes = <&gfx &lhc>; 157 aspeed,external-nodes = <&gfx &lhc>;
189 158
190 }; 159 };
191
192 }; 160 };
193 161
194 gfx: display@1e6e6000 { 162 gfx: display@1e6e6000 {
@@ -200,7 +168,8 @@
200 adc: adc@1e6e9000 { 168 adc: adc@1e6e9000 {
201 compatible = "aspeed,ast2500-adc"; 169 compatible = "aspeed,ast2500-adc";
202 reg = <0x1e6e9000 0xb0>; 170 reg = <0x1e6e9000 0xb0>;
203 clocks = <&clk_apb>; 171 clocks = <&syscon ASPEED_CLK_APB>;
172 resets = <&syscon ASPEED_RESET_ADC>;
204 #io-channel-cells = <1>; 173 #io-channel-cells = <1>;
205 status = "disabled"; 174 status = "disabled";
206 }; 175 };
@@ -217,6 +186,7 @@
217 reg = <0x1e780000 0x1000>; 186 reg = <0x1e780000 0x1000>;
218 interrupts = <20>; 187 interrupts = <20>;
219 gpio-ranges = <&pinctrl 0 0 220>; 188 gpio-ranges = <&pinctrl 0 0 220>;
189 clocks = <&syscon ASPEED_CLK_APB>;
220 interrupt-controller; 190 interrupt-controller;
221 }; 191 };
222 192
@@ -225,7 +195,7 @@
225 compatible = "aspeed,ast2400-timer"; 195 compatible = "aspeed,ast2400-timer";
226 reg = <0x1e782000 0x90>; 196 reg = <0x1e782000 0x90>;
227 interrupts = <16 17 18 35 36 37 38 39>; 197 interrupts = <16 17 18 35 36 37 38 39>;
228 clocks = <&clk_apb>; 198 clocks = <&syscon ASPEED_CLK_APB>;
229 clock-names = "PCLK"; 199 clock-names = "PCLK";
230 }; 200 };
231 201
@@ -234,7 +204,7 @@
234 reg = <0x1e783000 0x20>; 204 reg = <0x1e783000 0x20>;
235 reg-shift = <2>; 205 reg-shift = <2>;
236 interrupts = <9>; 206 interrupts = <9>;
237 clocks = <&clk_uart>; 207 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
238 no-loopback-test; 208 no-loopback-test;
239 status = "disabled"; 209 status = "disabled";
240 }; 210 };
@@ -244,7 +214,7 @@
244 reg = <0x1e784000 0x20>; 214 reg = <0x1e784000 0x20>;
245 reg-shift = <2>; 215 reg-shift = <2>;
246 interrupts = <10>; 216 interrupts = <10>;
247 clocks = <&clk_uart>; 217 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
248 no-loopback-test; 218 no-loopback-test;
249 status = "disabled"; 219 status = "disabled";
250 }; 220 };
@@ -252,16 +222,39 @@
252 wdt1: watchdog@1e785000 { 222 wdt1: watchdog@1e785000 {
253 compatible = "aspeed,ast2500-wdt"; 223 compatible = "aspeed,ast2500-wdt";
254 reg = <0x1e785000 0x20>; 224 reg = <0x1e785000 0x20>;
225 clocks = <&syscon ASPEED_CLK_APB>;
255 }; 226 };
256 227
257 wdt2: watchdog@1e785020 { 228 wdt2: watchdog@1e785020 {
258 compatible = "aspeed,ast2500-wdt"; 229 compatible = "aspeed,ast2500-wdt";
259 reg = <0x1e785020 0x20>; 230 reg = <0x1e785020 0x20>;
231 clocks = <&syscon ASPEED_CLK_APB>;
260 }; 232 };
261 233
262 wdt3: watchdog@1e785040 { 234 wdt3: watchdog@1e785040 {
263 compatible = "aspeed,ast2500-wdt"; 235 compatible = "aspeed,ast2500-wdt";
264 reg = <0x1e785040 0x20>; 236 reg = <0x1e785040 0x20>;
237 clocks = <&syscon ASPEED_CLK_APB>;
238 status = "disabled";
239 };
240
241 pwm_tacho: pwm-tacho-controller@1e786000 {
242 compatible = "aspeed,ast2500-pwm-tacho";
243 #address-cells = <1>;
244 #size-cells = <0>;
245 reg = <0x1e786000 0x1000>;
246 clocks = <&syscon ASPEED_CLK_APB>;
247 resets = <&syscon ASPEED_RESET_PWM>;
248 status = "disabled";
249 };
250
251 vuart: serial@1e787000 {
252 compatible = "aspeed,ast2500-vuart";
253 reg = <0x1e787000 0x40>;
254 reg-shift = <2>;
255 interrupts = <8>;
256 clocks = <&syscon ASPEED_CLK_APB>;
257 no-loopback-test;
265 status = "disabled"; 258 status = "disabled";
266 }; 259 };
267 260
@@ -288,6 +281,19 @@
288 281
289 reg-io-width = <4>; 282 reg-io-width = <4>;
290 283
284 lpc_ctrl: lpc-ctrl@0 {
285 compatible = "aspeed,ast2500-lpc-ctrl";
286 reg = <0x0 0x80>;
287 status = "disabled";
288 };
289
290 lpc_snoop: lpc-snoop@0 {
291 compatible = "aspeed,ast2500-lpc-snoop";
292 reg = <0x0 0x80>;
293 interrupts = <8>;
294 status = "disabled";
295 };
296
291 lhc: lhc@20 { 297 lhc: lhc@20 {
292 compatible = "aspeed,ast2500-lhc"; 298 compatible = "aspeed,ast2500-lhc";
293 reg = <0x20 0x24 0x48 0x8>; 299 reg = <0x20 0x24 0x48 0x8>;
@@ -295,22 +301,12 @@
295 }; 301 };
296 }; 302 };
297 303
298 vuart: serial@1e787000 {
299 compatible = "aspeed,ast2500-vuart";
300 reg = <0x1e787000 0x40>;
301 reg-shift = <2>;
302 interrupts = <10>;
303 clocks = <&clk_uart>;
304 no-loopback-test;
305 status = "disabled";
306 };
307
308 uart2: serial@1e78d000 { 304 uart2: serial@1e78d000 {
309 compatible = "ns16550a"; 305 compatible = "ns16550a";
310 reg = <0x1e78d000 0x20>; 306 reg = <0x1e78d000 0x20>;
311 reg-shift = <2>; 307 reg-shift = <2>;
312 interrupts = <32>; 308 interrupts = <32>;
313 clocks = <&clk_uart>; 309 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
314 no-loopback-test; 310 no-loopback-test;
315 status = "disabled"; 311 status = "disabled";
316 }; 312 };
@@ -320,7 +316,7 @@
320 reg = <0x1e78e000 0x20>; 316 reg = <0x1e78e000 0x20>;
321 reg-shift = <2>; 317 reg-shift = <2>;
322 interrupts = <33>; 318 interrupts = <33>;
323 clocks = <&clk_uart>; 319 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
324 no-loopback-test; 320 no-loopback-test;
325 status = "disabled"; 321 status = "disabled";
326 }; 322 };
@@ -330,7 +326,7 @@
330 reg = <0x1e78f000 0x20>; 326 reg = <0x1e78f000 0x20>;
331 reg-shift = <2>; 327 reg-shift = <2>;
332 interrupts = <34>; 328 interrupts = <34>;
333 clocks = <&clk_uart>; 329 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
334 no-loopback-test; 330 no-loopback-test;
335 status = "disabled"; 331 status = "disabled";
336 }; 332 };
@@ -361,7 +357,8 @@
361 357
362 reg = <0x40 0x40>; 358 reg = <0x40 0x40>;
363 compatible = "aspeed,ast2500-i2c-bus"; 359 compatible = "aspeed,ast2500-i2c-bus";
364 clocks = <&clk_apb>; 360 clocks = <&syscon ASPEED_CLK_APB>;
361 resets = <&syscon ASPEED_RESET_I2C>;
365 bus-frequency = <100000>; 362 bus-frequency = <100000>;
366 interrupts = <0>; 363 interrupts = <0>;
367 interrupt-parent = <&i2c_ic>; 364 interrupt-parent = <&i2c_ic>;
@@ -376,7 +373,8 @@
376 373
377 reg = <0x80 0x40>; 374 reg = <0x80 0x40>;
378 compatible = "aspeed,ast2500-i2c-bus"; 375 compatible = "aspeed,ast2500-i2c-bus";
379 clocks = <&clk_apb>; 376 clocks = <&syscon ASPEED_CLK_APB>;
377 resets = <&syscon ASPEED_RESET_I2C>;
380 bus-frequency = <100000>; 378 bus-frequency = <100000>;
381 interrupts = <1>; 379 interrupts = <1>;
382 interrupt-parent = <&i2c_ic>; 380 interrupt-parent = <&i2c_ic>;
@@ -391,7 +389,8 @@
391 389
392 reg = <0xc0 0x40>; 390 reg = <0xc0 0x40>;
393 compatible = "aspeed,ast2500-i2c-bus"; 391 compatible = "aspeed,ast2500-i2c-bus";
394 clocks = <&clk_apb>; 392 clocks = <&syscon ASPEED_CLK_APB>;
393 resets = <&syscon ASPEED_RESET_I2C>;
395 bus-frequency = <100000>; 394 bus-frequency = <100000>;
396 interrupts = <2>; 395 interrupts = <2>;
397 interrupt-parent = <&i2c_ic>; 396 interrupt-parent = <&i2c_ic>;
@@ -407,7 +406,8 @@
407 406
408 reg = <0x100 0x40>; 407 reg = <0x100 0x40>;
409 compatible = "aspeed,ast2500-i2c-bus"; 408 compatible = "aspeed,ast2500-i2c-bus";
410 clocks = <&clk_apb>; 409 clocks = <&syscon ASPEED_CLK_APB>;
410 resets = <&syscon ASPEED_RESET_I2C>;
411 bus-frequency = <100000>; 411 bus-frequency = <100000>;
412 interrupts = <3>; 412 interrupts = <3>;
413 interrupt-parent = <&i2c_ic>; 413 interrupt-parent = <&i2c_ic>;
@@ -423,7 +423,8 @@
423 423
424 reg = <0x140 0x40>; 424 reg = <0x140 0x40>;
425 compatible = "aspeed,ast2500-i2c-bus"; 425 compatible = "aspeed,ast2500-i2c-bus";
426 clocks = <&clk_apb>; 426 clocks = <&syscon ASPEED_CLK_APB>;
427 resets = <&syscon ASPEED_RESET_I2C>;
427 bus-frequency = <100000>; 428 bus-frequency = <100000>;
428 interrupts = <4>; 429 interrupts = <4>;
429 interrupt-parent = <&i2c_ic>; 430 interrupt-parent = <&i2c_ic>;
@@ -439,7 +440,8 @@
439 440
440 reg = <0x180 0x40>; 441 reg = <0x180 0x40>;
441 compatible = "aspeed,ast2500-i2c-bus"; 442 compatible = "aspeed,ast2500-i2c-bus";
442 clocks = <&clk_apb>; 443 clocks = <&syscon ASPEED_CLK_APB>;
444 resets = <&syscon ASPEED_RESET_I2C>;
443 bus-frequency = <100000>; 445 bus-frequency = <100000>;
444 interrupts = <5>; 446 interrupts = <5>;
445 interrupt-parent = <&i2c_ic>; 447 interrupt-parent = <&i2c_ic>;
@@ -455,7 +457,8 @@
455 457
456 reg = <0x1c0 0x40>; 458 reg = <0x1c0 0x40>;
457 compatible = "aspeed,ast2500-i2c-bus"; 459 compatible = "aspeed,ast2500-i2c-bus";
458 clocks = <&clk_apb>; 460 clocks = <&syscon ASPEED_CLK_APB>;
461 resets = <&syscon ASPEED_RESET_I2C>;
459 bus-frequency = <100000>; 462 bus-frequency = <100000>;
460 interrupts = <6>; 463 interrupts = <6>;
461 interrupt-parent = <&i2c_ic>; 464 interrupt-parent = <&i2c_ic>;
@@ -471,7 +474,8 @@
471 474
472 reg = <0x300 0x40>; 475 reg = <0x300 0x40>;
473 compatible = "aspeed,ast2500-i2c-bus"; 476 compatible = "aspeed,ast2500-i2c-bus";
474 clocks = <&clk_apb>; 477 clocks = <&syscon ASPEED_CLK_APB>;
478 resets = <&syscon ASPEED_RESET_I2C>;
475 bus-frequency = <100000>; 479 bus-frequency = <100000>;
476 interrupts = <7>; 480 interrupts = <7>;
477 interrupt-parent = <&i2c_ic>; 481 interrupt-parent = <&i2c_ic>;
@@ -487,7 +491,8 @@
487 491
488 reg = <0x340 0x40>; 492 reg = <0x340 0x40>;
489 compatible = "aspeed,ast2500-i2c-bus"; 493 compatible = "aspeed,ast2500-i2c-bus";
490 clocks = <&clk_apb>; 494 clocks = <&syscon ASPEED_CLK_APB>;
495 resets = <&syscon ASPEED_RESET_I2C>;
491 bus-frequency = <100000>; 496 bus-frequency = <100000>;
492 interrupts = <8>; 497 interrupts = <8>;
493 interrupt-parent = <&i2c_ic>; 498 interrupt-parent = <&i2c_ic>;
@@ -503,7 +508,8 @@
503 508
504 reg = <0x380 0x40>; 509 reg = <0x380 0x40>;
505 compatible = "aspeed,ast2500-i2c-bus"; 510 compatible = "aspeed,ast2500-i2c-bus";
506 clocks = <&clk_apb>; 511 clocks = <&syscon ASPEED_CLK_APB>;
512 resets = <&syscon ASPEED_RESET_I2C>;
507 bus-frequency = <100000>; 513 bus-frequency = <100000>;
508 interrupts = <9>; 514 interrupts = <9>;
509 interrupt-parent = <&i2c_ic>; 515 interrupt-parent = <&i2c_ic>;
@@ -519,7 +525,8 @@
519 525
520 reg = <0x3c0 0x40>; 526 reg = <0x3c0 0x40>;
521 compatible = "aspeed,ast2500-i2c-bus"; 527 compatible = "aspeed,ast2500-i2c-bus";
522 clocks = <&clk_apb>; 528 clocks = <&syscon ASPEED_CLK_APB>;
529 resets = <&syscon ASPEED_RESET_I2C>;
523 bus-frequency = <100000>; 530 bus-frequency = <100000>;
524 interrupts = <10>; 531 interrupts = <10>;
525 interrupt-parent = <&i2c_ic>; 532 interrupt-parent = <&i2c_ic>;
@@ -535,7 +542,8 @@
535 542
536 reg = <0x400 0x40>; 543 reg = <0x400 0x40>;
537 compatible = "aspeed,ast2500-i2c-bus"; 544 compatible = "aspeed,ast2500-i2c-bus";
538 clocks = <&clk_apb>; 545 clocks = <&syscon ASPEED_CLK_APB>;
546 resets = <&syscon ASPEED_RESET_I2C>;
539 bus-frequency = <100000>; 547 bus-frequency = <100000>;
540 interrupts = <11>; 548 interrupts = <11>;
541 interrupt-parent = <&i2c_ic>; 549 interrupt-parent = <&i2c_ic>;
@@ -551,7 +559,8 @@
551 559
552 reg = <0x440 0x40>; 560 reg = <0x440 0x40>;
553 compatible = "aspeed,ast2500-i2c-bus"; 561 compatible = "aspeed,ast2500-i2c-bus";
554 clocks = <&clk_apb>; 562 clocks = <&syscon ASPEED_CLK_APB>;
563 resets = <&syscon ASPEED_RESET_I2C>;
555 bus-frequency = <100000>; 564 bus-frequency = <100000>;
556 interrupts = <12>; 565 interrupts = <12>;
557 interrupt-parent = <&i2c_ic>; 566 interrupt-parent = <&i2c_ic>;
@@ -567,7 +576,8 @@
567 576
568 reg = <0x480 0x40>; 577 reg = <0x480 0x40>;
569 compatible = "aspeed,ast2500-i2c-bus"; 578 compatible = "aspeed,ast2500-i2c-bus";
570 clocks = <&clk_apb>; 579 clocks = <&syscon ASPEED_CLK_APB>;
580 resets = <&syscon ASPEED_RESET_I2C>;
571 bus-frequency = <100000>; 581 bus-frequency = <100000>;
572 interrupts = <13>; 582 interrupts = <13>;
573 interrupt-parent = <&i2c_ic>; 583 interrupt-parent = <&i2c_ic>;
diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
new file mode 100644
index 000000000000..6c26524e93e1
--- /dev/null
+++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi
@@ -0,0 +1,32 @@
1// SPDX-License-Identifier: GPL-2.0+
2
3partitions {
4 compatible = "fixed-partitions";
5 #address-cells = <1>;
6 #size-cells = <1>;
7
8 u-boot@0 {
9 reg = <0x0 0x60000>;
10 label = "u-boot";
11 };
12
13 u-boot-env@60000 {
14 reg = <0x60000 0x20000>;
15 label = "u-boot-env";
16 };
17
18 kernel@80000 {
19 reg = <0x80000 0x440000>;
20 label = "kernel";
21 };
22
23 rofs@c0000 {
24 reg = <0x4c0000 0x1740000>;
25 label = "rofs";
26 };
27
28 rwfs@1c00000 {
29 reg = <0x1c00000 0x400000>;
30 label = "rwfs";
31 };
32};
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
new file mode 100644
index 000000000000..d3558d897a4d
--- /dev/null
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -0,0 +1,52 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
3#ifndef DT_BINDINGS_ASPEED_CLOCK_H
4#define DT_BINDINGS_ASPEED_CLOCK_H
5
6#define ASPEED_CLK_GATE_ECLK 0
7#define ASPEED_CLK_GATE_GCLK 1
8#define ASPEED_CLK_GATE_MCLK 2
9#define ASPEED_CLK_GATE_VCLK 3
10#define ASPEED_CLK_GATE_BCLK 4
11#define ASPEED_CLK_GATE_DCLK 5
12#define ASPEED_CLK_GATE_REFCLK 6
13#define ASPEED_CLK_GATE_USBPORT2CLK 7
14#define ASPEED_CLK_GATE_LCLK 8
15#define ASPEED_CLK_GATE_USBUHCICLK 9
16#define ASPEED_CLK_GATE_D1CLK 10
17#define ASPEED_CLK_GATE_YCLK 11
18#define ASPEED_CLK_GATE_USBPORT1CLK 12
19#define ASPEED_CLK_GATE_UART1CLK 13
20#define ASPEED_CLK_GATE_UART2CLK 14
21#define ASPEED_CLK_GATE_UART5CLK 15
22#define ASPEED_CLK_GATE_ESPICLK 16
23#define ASPEED_CLK_GATE_MAC1CLK 17
24#define ASPEED_CLK_GATE_MAC2CLK 18
25#define ASPEED_CLK_GATE_RSACLK 19
26#define ASPEED_CLK_GATE_UART3CLK 20
27#define ASPEED_CLK_GATE_UART4CLK 21
28#define ASPEED_CLK_GATE_SDCLKCLK 22
29#define ASPEED_CLK_GATE_LHCCLK 23
30#define ASPEED_CLK_HPLL 24
31#define ASPEED_CLK_AHB 25
32#define ASPEED_CLK_APB 26
33#define ASPEED_CLK_UART 27
34#define ASPEED_CLK_SDIO 28
35#define ASPEED_CLK_ECLK 29
36#define ASPEED_CLK_ECLK_MUX 30
37#define ASPEED_CLK_LHCLK 31
38#define ASPEED_CLK_MAC 32
39#define ASPEED_CLK_BCLK 33
40#define ASPEED_CLK_MPLL 34
41
42#define ASPEED_RESET_XDMA 0
43#define ASPEED_RESET_MCTP 1
44#define ASPEED_RESET_ADC 2
45#define ASPEED_RESET_JTAG_MASTER 3
46#define ASPEED_RESET_MIC 4
47#define ASPEED_RESET_PWM 5
48#define ASPEED_RESET_PCIVGA 6
49#define ASPEED_RESET_I2C 7
50#define ASPEED_RESET_AHB 8
51
52#endif
diff --git a/include/dt-bindings/gpio/aspeed-gpio.h b/include/dt-bindings/gpio/aspeed-gpio.h
new file mode 100644
index 000000000000..56fc4889b2c4
--- /dev/null
+++ b/include/dt-bindings/gpio/aspeed-gpio.h
@@ -0,0 +1,49 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * This header provides constants for binding aspeed,*-gpio.
4 *
5 * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below
6 * provide names for this.
7 *
8 * The second cell contains standard flag values specified in gpio.h.
9 */
10
11#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H
12#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H
13
14#include <dt-bindings/gpio/gpio.h>
15
16#define ASPEED_GPIO_PORT_A 0
17#define ASPEED_GPIO_PORT_B 1
18#define ASPEED_GPIO_PORT_C 2
19#define ASPEED_GPIO_PORT_D 3
20#define ASPEED_GPIO_PORT_E 4
21#define ASPEED_GPIO_PORT_F 5
22#define ASPEED_GPIO_PORT_G 6
23#define ASPEED_GPIO_PORT_H 7
24#define ASPEED_GPIO_PORT_I 8
25#define ASPEED_GPIO_PORT_J 9
26#define ASPEED_GPIO_PORT_K 10
27#define ASPEED_GPIO_PORT_L 11
28#define ASPEED_GPIO_PORT_M 12
29#define ASPEED_GPIO_PORT_N 13
30#define ASPEED_GPIO_PORT_O 14
31#define ASPEED_GPIO_PORT_P 15
32#define ASPEED_GPIO_PORT_Q 16
33#define ASPEED_GPIO_PORT_R 17
34#define ASPEED_GPIO_PORT_S 18
35#define ASPEED_GPIO_PORT_T 19
36#define ASPEED_GPIO_PORT_U 20
37#define ASPEED_GPIO_PORT_V 21
38#define ASPEED_GPIO_PORT_W 22
39#define ASPEED_GPIO_PORT_X 23
40#define ASPEED_GPIO_PORT_Y 24
41#define ASPEED_GPIO_PORT_Z 25
42#define ASPEED_GPIO_PORT_AA 26
43#define ASPEED_GPIO_PORT_AB 27
44#define ASPEED_GPIO_PORT_AC 28
45
46#define ASPEED_GPIO(port, offset) \
47 ((ASPEED_GPIO_PORT_##port * 8) + offset)
48
49#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 04:13:06 -0400