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authorLaxman Dewangan <ldewangan@nvidia.com>2016-04-25 06:38:33 -0400
committerLinus Walleij <linus.walleij@linaro.org>2016-04-29 05:00:51 -0400
commitb546be0db955840e2c14aae5d8e5f93a456f9982 (patch)
treec7612c74202063aa37b2f5b4565a420c5cad5928
parent804f56804d480edc3463a91bbcb39e3b4abd2ac6 (diff)
gpio: tegra: Get rid of all file scoped global variables
Move the file scoped multiple global variable from Tegra GPIO driver to the structure and make this as gpiochip data which can be referred from GPIO chip callbacks. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--drivers/gpio/gpio-tegra.c350
1 files changed, 198 insertions, 152 deletions
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index cd69422f3646..653825db4baa 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -35,24 +35,24 @@
35#define GPIO_PORT(x) (((x) >> 3) & 0x3) 35#define GPIO_PORT(x) (((x) >> 3) & 0x3)
36#define GPIO_BIT(x) ((x) & 0x7) 36#define GPIO_BIT(x) ((x) & 0x7)
37 37
38#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \ 38#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
39 GPIO_PORT(x) * 4) 39 GPIO_PORT(x) * 4)
40 40
41#define GPIO_CNF(x) (GPIO_REG(x) + 0x00) 41#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42#define GPIO_OE(x) (GPIO_REG(x) + 0x10) 42#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43#define GPIO_OUT(x) (GPIO_REG(x) + 0X20) 43#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44#define GPIO_IN(x) (GPIO_REG(x) + 0x30) 44#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) 45#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) 46#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) 47#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) 48#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
49 49
50#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00) 50#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
51#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10) 51#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
52#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20) 52#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
53#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40) 53#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
54#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50) 54#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
55#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60) 55#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
56 56
57#define GPIO_INT_LVL_MASK 0x010101 57#define GPIO_INT_LVL_MASK 0x010101
58#define GPIO_INT_LVL_EDGE_RISING 0x000101 58#define GPIO_INT_LVL_EDGE_RISING 0x000101
@@ -61,6 +61,8 @@
61#define GPIO_INT_LVL_LEVEL_HIGH 0x000001 61#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
62#define GPIO_INT_LVL_LEVEL_LOW 0x000000 62#define GPIO_INT_LVL_LEVEL_LOW 0x000000
63 63
64struct tegra_gpio_info;
65
64struct tegra_gpio_bank { 66struct tegra_gpio_bank {
65 int bank; 67 int bank;
66 int irq; 68 int irq;
@@ -73,6 +75,7 @@ struct tegra_gpio_bank {
73 u32 int_lvl[4]; 75 u32 int_lvl[4];
74 u32 wake_enb[4]; 76 u32 wake_enb[4];
75#endif 77#endif
78 struct tegra_gpio_info *tgi;
76}; 79};
77 80
78struct tegra_gpio_soc_config { 81struct tegra_gpio_soc_config {
@@ -80,22 +83,27 @@ struct tegra_gpio_soc_config {
80 u32 upper_offset; 83 u32 upper_offset;
81}; 84};
82 85
83static struct device *dev; 86struct tegra_gpio_info {
84static struct irq_domain *irq_domain; 87 struct device *dev;
85static void __iomem *regs; 88 void __iomem *regs;
86static u32 tegra_gpio_bank_count; 89 struct irq_domain *irq_domain;
87static u32 tegra_gpio_bank_stride; 90 struct tegra_gpio_bank *bank_info;
88static u32 tegra_gpio_upper_offset; 91 const struct tegra_gpio_soc_config *soc;
89static struct tegra_gpio_bank *tegra_gpio_banks; 92 struct gpio_chip gc;
93 struct irq_chip ic;
94 struct lock_class_key lock_class;
95 u32 bank_count;
96};
90 97
91static inline void tegra_gpio_writel(u32 val, u32 reg) 98static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
99 u32 val, u32 reg)
92{ 100{
93 __raw_writel(val, regs + reg); 101 __raw_writel(val, tgi->regs + reg);
94} 102}
95 103
96static inline u32 tegra_gpio_readl(u32 reg) 104static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
97{ 105{
98 return __raw_readl(regs + reg); 106 return __raw_readl(tgi->regs + reg);
99} 107}
100 108
101static int tegra_gpio_compose(int bank, int port, int bit) 109static int tegra_gpio_compose(int bank, int port, int bit)
@@ -103,24 +111,25 @@ static int tegra_gpio_compose(int bank, int port, int bit)
103 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 111 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
104} 112}
105 113
106static void tegra_gpio_mask_write(u32 reg, int gpio, int value) 114static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
115 int gpio, int value)
107{ 116{
108 u32 val; 117 u32 val;
109 118
110 val = 0x100 << GPIO_BIT(gpio); 119 val = 0x100 << GPIO_BIT(gpio);
111 if (value) 120 if (value)
112 val |= 1 << GPIO_BIT(gpio); 121 val |= 1 << GPIO_BIT(gpio);
113 tegra_gpio_writel(val, reg); 122 tegra_gpio_writel(tgi, val, reg);
114} 123}
115 124
116static void tegra_gpio_enable(int gpio) 125static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio)
117{ 126{
118 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); 127 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
119} 128}
120 129
121static void tegra_gpio_disable(int gpio) 130static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio)
122{ 131{
123 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); 132 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
124} 133}
125 134
126static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) 135static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
@@ -130,83 +139,90 @@ static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
130 139
131static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) 140static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
132{ 141{
142 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
143
133 pinctrl_free_gpio(offset); 144 pinctrl_free_gpio(offset);
134 tegra_gpio_disable(offset); 145 tegra_gpio_disable(tgi, offset);
135} 146}
136 147
137static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 148static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
138{ 149{
139 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); 150 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
151
152 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
140} 153}
141 154
142static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) 155static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
143{ 156{
157 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
158 int bval = BIT(GPIO_BIT(offset));
159
144 /* If gpio is in output mode then read from the out value */ 160 /* If gpio is in output mode then read from the out value */
145 if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1) 161 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
146 return (tegra_gpio_readl(GPIO_OUT(offset)) >> 162 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
147 GPIO_BIT(offset)) & 0x1;
148 163
149 return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; 164 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
150} 165}
151 166
152static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 167static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
153{ 168{
154 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); 169 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
155 tegra_gpio_enable(offset); 170
171 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
172 tegra_gpio_enable(tgi, offset);
156 return 0; 173 return 0;
157} 174}
158 175
159static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 176static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
160 int value) 177 int value)
161{ 178{
179 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
180
162 tegra_gpio_set(chip, offset, value); 181 tegra_gpio_set(chip, offset, value);
163 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); 182 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
164 tegra_gpio_enable(offset); 183 tegra_gpio_enable(tgi, offset);
165 return 0; 184 return 0;
166} 185}
167 186
168static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 187static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
169{ 188{
170 return irq_find_mapping(irq_domain, offset); 189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
171}
172 190
173static struct gpio_chip tegra_gpio_chip = { 191 return irq_find_mapping(tgi->irq_domain, offset);
174 .label = "tegra-gpio", 192}
175 .request = tegra_gpio_request,
176 .free = tegra_gpio_free,
177 .direction_input = tegra_gpio_direction_input,
178 .get = tegra_gpio_get,
179 .direction_output = tegra_gpio_direction_output,
180 .set = tegra_gpio_set,
181 .to_irq = tegra_gpio_to_irq,
182 .base = 0,
183};
184 193
185static void tegra_gpio_irq_ack(struct irq_data *d) 194static void tegra_gpio_irq_ack(struct irq_data *d)
186{ 195{
196 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
197 struct tegra_gpio_info *tgi = bank->tgi;
187 int gpio = d->hwirq; 198 int gpio = d->hwirq;
188 199
189 tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); 200 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
190} 201}
191 202
192static void tegra_gpio_irq_mask(struct irq_data *d) 203static void tegra_gpio_irq_mask(struct irq_data *d)
193{ 204{
205 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
206 struct tegra_gpio_info *tgi = bank->tgi;
194 int gpio = d->hwirq; 207 int gpio = d->hwirq;
195 208
196 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); 209 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
197} 210}
198 211
199static void tegra_gpio_irq_unmask(struct irq_data *d) 212static void tegra_gpio_irq_unmask(struct irq_data *d)
200{ 213{
214 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
215 struct tegra_gpio_info *tgi = bank->tgi;
201 int gpio = d->hwirq; 216 int gpio = d->hwirq;
202 217
203 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); 218 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
204} 219}
205 220
206static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 221static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
207{ 222{
208 int gpio = d->hwirq; 223 int gpio = d->hwirq;
209 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 224 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
225 struct tegra_gpio_info *tgi = bank->tgi;
210 int port = GPIO_PORT(gpio); 226 int port = GPIO_PORT(gpio);
211 int lvl_type; 227 int lvl_type;
212 int val; 228 int val;
@@ -238,23 +254,24 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
238 return -EINVAL; 254 return -EINVAL;
239 } 255 }
240 256
241 ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio); 257 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
242 if (ret) { 258 if (ret) {
243 dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio); 259 dev_err(tgi->dev,
260 "unable to lock Tegra GPIO %d as IRQ\n", gpio);
244 return ret; 261 return ret;
245 } 262 }
246 263
247 spin_lock_irqsave(&bank->lvl_lock[port], flags); 264 spin_lock_irqsave(&bank->lvl_lock[port], flags);
248 265
249 val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 266 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
250 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 267 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
251 val |= lvl_type << GPIO_BIT(gpio); 268 val |= lvl_type << GPIO_BIT(gpio);
252 tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); 269 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
253 270
254 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 271 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
255 272
256 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); 273 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
257 tegra_gpio_enable(gpio); 274 tegra_gpio_enable(tgi, gpio);
258 275
259 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 276 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
260 irq_set_handler_locked(d, handle_level_irq); 277 irq_set_handler_locked(d, handle_level_irq);
@@ -266,9 +283,11 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
266 283
267static void tegra_gpio_irq_shutdown(struct irq_data *d) 284static void tegra_gpio_irq_shutdown(struct irq_data *d)
268{ 285{
286 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
287 struct tegra_gpio_info *tgi = bank->tgi;
269 int gpio = d->hwirq; 288 int gpio = d->hwirq;
270 289
271 gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio); 290 gpiochip_unlock_as_irq(&tgi->gc, gpio);
272} 291}
273 292
274static void tegra_gpio_irq_handler(struct irq_desc *desc) 293static void tegra_gpio_irq_handler(struct irq_desc *desc)
@@ -276,19 +295,24 @@ static void tegra_gpio_irq_handler(struct irq_desc *desc)
276 int port; 295 int port;
277 int pin; 296 int pin;
278 int unmasked = 0; 297 int unmasked = 0;
298 int gpio;
299 u32 lvl;
300 unsigned long sta;
279 struct irq_chip *chip = irq_desc_get_chip(desc); 301 struct irq_chip *chip = irq_desc_get_chip(desc);
280 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); 302 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
303 struct tegra_gpio_info *tgi = bank->tgi;
281 304
282 chained_irq_enter(chip, desc); 305 chained_irq_enter(chip, desc);
283 306
284 for (port = 0; port < 4; port++) { 307 for (port = 0; port < 4; port++) {
285 int gpio = tegra_gpio_compose(bank->bank, port, 0); 308 gpio = tegra_gpio_compose(bank->bank, port, 0);
286 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & 309 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
287 tegra_gpio_readl(GPIO_INT_ENB(gpio)); 310 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
288 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 311 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
289 312
290 for_each_set_bit(pin, &sta, 8) { 313 for_each_set_bit(pin, &sta, 8) {
291 tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); 314 tegra_gpio_writel(tgi, 1 << pin,
315 GPIO_INT_CLR(tgi, gpio));
292 316
293 /* if gpio is edge triggered, clear condition 317 /* if gpio is edge triggered, clear condition
294 * before executing the handler so that we don't 318 * before executing the handler so that we don't
@@ -311,22 +335,29 @@ static void tegra_gpio_irq_handler(struct irq_desc *desc)
311#ifdef CONFIG_PM_SLEEP 335#ifdef CONFIG_PM_SLEEP
312static int tegra_gpio_resume(struct device *dev) 336static int tegra_gpio_resume(struct device *dev)
313{ 337{
338 struct platform_device *pdev = to_platform_device(dev);
339 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
314 unsigned long flags; 340 unsigned long flags;
315 int b; 341 int b;
316 int p; 342 int p;
317 343
318 local_irq_save(flags); 344 local_irq_save(flags);
319 345
320 for (b = 0; b < tegra_gpio_bank_count; b++) { 346 for (b = 0; b < tgi->bank_count; b++) {
321 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 347 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
322 348
323 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 349 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
324 unsigned int gpio = (b<<5) | (p<<3); 350 unsigned int gpio = (b<<5) | (p<<3);
325 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); 351 tegra_gpio_writel(tgi, bank->cnf[p],
326 tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); 352 GPIO_CNF(tgi, gpio));
327 tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); 353 tegra_gpio_writel(tgi, bank->out[p],
328 tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); 354 GPIO_OUT(tgi, gpio));
329 tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); 355 tegra_gpio_writel(tgi, bank->oe[p],
356 GPIO_OE(tgi, gpio));
357 tegra_gpio_writel(tgi, bank->int_lvl[p],
358 GPIO_INT_LVL(tgi, gpio));
359 tegra_gpio_writel(tgi, bank->int_enb[p],
360 GPIO_INT_ENB(tgi, gpio));
330 } 361 }
331 } 362 }
332 363
@@ -336,25 +367,32 @@ static int tegra_gpio_resume(struct device *dev)
336 367
337static int tegra_gpio_suspend(struct device *dev) 368static int tegra_gpio_suspend(struct device *dev)
338{ 369{
370 struct platform_device *pdev = to_platform_device(dev);
371 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
339 unsigned long flags; 372 unsigned long flags;
340 int b; 373 int b;
341 int p; 374 int p;
342 375
343 local_irq_save(flags); 376 local_irq_save(flags);
344 for (b = 0; b < tegra_gpio_bank_count; b++) { 377 for (b = 0; b < tgi->bank_count; b++) {
345 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 378 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
346 379
347 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 380 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
348 unsigned int gpio = (b<<5) | (p<<3); 381 unsigned int gpio = (b<<5) | (p<<3);
349 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); 382 bank->cnf[p] = tegra_gpio_readl(tgi,
350 bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); 383 GPIO_CNF(tgi, gpio));
351 bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); 384 bank->out[p] = tegra_gpio_readl(tgi,
352 bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); 385 GPIO_OUT(tgi, gpio));
353 bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 386 bank->oe[p] = tegra_gpio_readl(tgi,
387 GPIO_OE(tgi, gpio));
388 bank->int_enb[p] = tegra_gpio_readl(tgi,
389 GPIO_INT_ENB(tgi, gpio));
390 bank->int_lvl[p] = tegra_gpio_readl(tgi,
391 GPIO_INT_LVL(tgi, gpio));
354 392
355 /* Enable gpio irq for wake up source */ 393 /* Enable gpio irq for wake up source */
356 tegra_gpio_writel(bank->wake_enb[p], 394 tegra_gpio_writel(tgi, bank->wake_enb[p],
357 GPIO_INT_ENB(gpio)); 395 GPIO_INT_ENB(tgi, gpio));
358 } 396 }
359 } 397 }
360 local_irq_restore(flags); 398 local_irq_restore(flags);
@@ -387,22 +425,23 @@ static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
387 425
388static int dbg_gpio_show(struct seq_file *s, void *unused) 426static int dbg_gpio_show(struct seq_file *s, void *unused)
389{ 427{
428 struct tegra_gpio_info *tgi = s->private;
390 int i; 429 int i;
391 int j; 430 int j;
392 431
393 for (i = 0; i < tegra_gpio_bank_count; i++) { 432 for (i = 0; i < tgi->bank_count; i++) {
394 for (j = 0; j < 4; j++) { 433 for (j = 0; j < 4; j++) {
395 int gpio = tegra_gpio_compose(i, j, 0); 434 int gpio = tegra_gpio_compose(i, j, 0);
396 seq_printf(s, 435 seq_printf(s,
397 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", 436 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
398 i, j, 437 i, j,
399 tegra_gpio_readl(GPIO_CNF(gpio)), 438 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
400 tegra_gpio_readl(GPIO_OE(gpio)), 439 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
401 tegra_gpio_readl(GPIO_OUT(gpio)), 440 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
402 tegra_gpio_readl(GPIO_IN(gpio)), 441 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
403 tegra_gpio_readl(GPIO_INT_STA(gpio)), 442 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
404 tegra_gpio_readl(GPIO_INT_ENB(gpio)), 443 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
405 tegra_gpio_readl(GPIO_INT_LVL(gpio))); 444 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
406 } 445 }
407 } 446 }
408 return 0; 447 return 0;
@@ -410,7 +449,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
410 449
411static int dbg_gpio_open(struct inode *inode, struct file *file) 450static int dbg_gpio_open(struct inode *inode, struct file *file)
412{ 451{
413 return single_open(file, dbg_gpio_show, &inode->i_private); 452 return single_open(file, dbg_gpio_show, inode->i_private);
414} 453}
415 454
416static const struct file_operations debug_fops = { 455static const struct file_operations debug_fops = {
@@ -420,44 +459,28 @@ static const struct file_operations debug_fops = {
420 .release = single_release, 459 .release = single_release,
421}; 460};
422 461
423static void tegra_gpio_debuginit(void) 462static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
424{ 463{
425 (void) debugfs_create_file("tegra_gpio", S_IRUGO, 464 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
426 NULL, NULL, &debug_fops); 465 NULL, tgi, &debug_fops);
427} 466}
428 467
429#else 468#else
430 469
431static inline void tegra_gpio_debuginit(void) 470static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
432{ 471{
433} 472}
434 473
435#endif 474#endif
436 475
437static struct irq_chip tegra_gpio_irq_chip = {
438 .name = "GPIO",
439 .irq_ack = tegra_gpio_irq_ack,
440 .irq_mask = tegra_gpio_irq_mask,
441 .irq_unmask = tegra_gpio_irq_unmask,
442 .irq_set_type = tegra_gpio_irq_set_type,
443 .irq_shutdown = tegra_gpio_irq_shutdown,
444#ifdef CONFIG_PM_SLEEP
445 .irq_set_wake = tegra_gpio_irq_set_wake,
446#endif
447};
448
449static const struct dev_pm_ops tegra_gpio_pm_ops = { 476static const struct dev_pm_ops tegra_gpio_pm_ops = {
450 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 477 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
451}; 478};
452 479
453/* This lock class tells lockdep that GPIO irqs are in a different
454 * category than their parents, so it won't report false recursion.
455 */
456static struct lock_class_key gpio_lock_class;
457
458static int tegra_gpio_probe(struct platform_device *pdev) 480static int tegra_gpio_probe(struct platform_device *pdev)
459{ 481{
460 const struct tegra_gpio_soc_config *config; 482 const struct tegra_gpio_soc_config *config;
483 struct tegra_gpio_info *tgi;
461 struct resource *res; 484 struct resource *res;
462 struct tegra_gpio_bank *bank; 485 struct tegra_gpio_bank *bank;
463 int ret; 486 int ret;
@@ -465,88 +488,111 @@ static int tegra_gpio_probe(struct platform_device *pdev)
465 int i; 488 int i;
466 int j; 489 int j;
467 490
468 dev = &pdev->dev;
469
470 config = of_device_get_match_data(&pdev->dev); 491 config = of_device_get_match_data(&pdev->dev);
471 if (!config) { 492 if (!config) {
472 dev_err(&pdev->dev, "Error: No device match found\n"); 493 dev_err(&pdev->dev, "Error: No device match found\n");
473 return -ENODEV; 494 return -ENODEV;
474 } 495 }
475 496
476 tegra_gpio_bank_stride = config->bank_stride; 497 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
477 tegra_gpio_upper_offset = config->upper_offset; 498 if (!tgi)
499 return -ENODEV;
500
501 tgi->soc = config;
502 tgi->dev = &pdev->dev;
478 503
479 for (;;) { 504 for (;;) {
480 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); 505 res = platform_get_resource(pdev, IORESOURCE_IRQ,
506 tgi->bank_count);
481 if (!res) 507 if (!res)
482 break; 508 break;
483 tegra_gpio_bank_count++; 509 tgi->bank_count++;
484 } 510 }
485 if (!tegra_gpio_bank_count) { 511 if (!tgi->bank_count) {
486 dev_err(&pdev->dev, "Missing IRQ resource\n"); 512 dev_err(&pdev->dev, "Missing IRQ resource\n");
487 return -ENODEV; 513 return -ENODEV;
488 } 514 }
489 515
490 tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32; 516 tgi->gc.label = "tegra-gpio";
517 tgi->gc.request = tegra_gpio_request;
518 tgi->gc.free = tegra_gpio_free;
519 tgi->gc.direction_input = tegra_gpio_direction_input;
520 tgi->gc.get = tegra_gpio_get;
521 tgi->gc.direction_output = tegra_gpio_direction_output;
522 tgi->gc.set = tegra_gpio_set;
523 tgi->gc.to_irq = tegra_gpio_to_irq;
524 tgi->gc.base = 0;
525 tgi->gc.ngpio = tgi->bank_count * 32;
526 tgi->gc.parent = &pdev->dev;
527 tgi->gc.of_node = pdev->dev.of_node;
528
529 tgi->ic.name = "GPIO";
530 tgi->ic.irq_ack = tegra_gpio_irq_ack;
531 tgi->ic.irq_mask = tegra_gpio_irq_mask;
532 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
533 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
534 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
535#ifdef CONFIG_PM_SLEEP
536 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
537#endif
538
539 platform_set_drvdata(pdev, tgi);
491 540
492 tegra_gpio_banks = devm_kzalloc(&pdev->dev, 541 tgi->bank_info = devm_kzalloc(&pdev->dev, tgi->bank_count *
493 tegra_gpio_bank_count * sizeof(*tegra_gpio_banks), 542 sizeof(*tgi->bank_info), GFP_KERNEL);
494 GFP_KERNEL); 543 if (!tgi->bank_info)
495 if (!tegra_gpio_banks)
496 return -ENODEV; 544 return -ENODEV;
497 545
498 irq_domain = irq_domain_add_linear(pdev->dev.of_node, 546 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
499 tegra_gpio_chip.ngpio, 547 tgi->gc.ngpio,
500 &irq_domain_simple_ops, NULL); 548 &irq_domain_simple_ops, NULL);
501 if (!irq_domain) 549 if (!tgi->irq_domain)
502 return -ENODEV; 550 return -ENODEV;
503 551
504 for (i = 0; i < tegra_gpio_bank_count; i++) { 552 for (i = 0; i < tgi->bank_count; i++) {
505 res = platform_get_resource(pdev, IORESOURCE_IRQ, i); 553 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
506 if (!res) { 554 if (!res) {
507 dev_err(&pdev->dev, "Missing IRQ resource\n"); 555 dev_err(&pdev->dev, "Missing IRQ resource\n");
508 return -ENODEV; 556 return -ENODEV;
509 } 557 }
510 558
511 bank = &tegra_gpio_banks[i]; 559 bank = &tgi->bank_info[i];
512 bank->bank = i; 560 bank->bank = i;
513 bank->irq = res->start; 561 bank->irq = res->start;
562 bank->tgi = tgi;
514 } 563 }
515 564
516 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 565 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
517 regs = devm_ioremap_resource(&pdev->dev, res); 566 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
518 if (IS_ERR(regs)) 567 if (IS_ERR(tgi->regs))
519 return PTR_ERR(regs); 568 return PTR_ERR(tgi->regs);
520 569
521 for (i = 0; i < tegra_gpio_bank_count; i++) { 570 for (i = 0; i < tgi->bank_count; i++) {
522 for (j = 0; j < 4; j++) { 571 for (j = 0; j < 4; j++) {
523 int gpio = tegra_gpio_compose(i, j, 0); 572 int gpio = tegra_gpio_compose(i, j, 0);
524 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); 573 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
525 } 574 }
526 } 575 }
527 576
528 tegra_gpio_chip.of_node = pdev->dev.of_node; 577 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
529
530 ret = devm_gpiochip_add_data(&pdev->dev, &tegra_gpio_chip, NULL);
531 if (ret < 0) { 578 if (ret < 0) {
532 irq_domain_remove(irq_domain); 579 irq_domain_remove(tgi->irq_domain);
533 return ret; 580 return ret;
534 } 581 }
535 582
536 for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) { 583 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
537 int irq = irq_create_mapping(irq_domain, gpio); 584 int irq = irq_create_mapping(tgi->irq_domain, gpio);
538 /* No validity check; all Tegra GPIOs are valid IRQs */ 585 /* No validity check; all Tegra GPIOs are valid IRQs */
539 586
540 bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; 587 bank = &tgi->bank_info[GPIO_BANK(gpio)];
541 588
542 irq_set_lockdep_class(irq, &gpio_lock_class); 589 irq_set_lockdep_class(irq, &tgi->lock_class);
543 irq_set_chip_data(irq, bank); 590 irq_set_chip_data(irq, bank);
544 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, 591 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
545 handle_simple_irq);
546 } 592 }
547 593
548 for (i = 0; i < tegra_gpio_bank_count; i++) { 594 for (i = 0; i < tgi->bank_count; i++) {
549 bank = &tegra_gpio_banks[i]; 595 bank = &tgi->bank_info[i];
550 596
551 irq_set_chained_handler_and_data(bank->irq, 597 irq_set_chained_handler_and_data(bank->irq,
552 tegra_gpio_irq_handler, bank); 598 tegra_gpio_irq_handler, bank);
@@ -555,7 +601,7 @@ static int tegra_gpio_probe(struct platform_device *pdev)
555 spin_lock_init(&bank->lvl_lock[j]); 601 spin_lock_init(&bank->lvl_lock[j]);
556 } 602 }
557 603
558 tegra_gpio_debuginit(); 604 tegra_gpio_debuginit(tgi);
559 605
560 return 0; 606 return 0;
561} 607}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 04:06:55 -0400