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authorLinus Torvalds <torvalds@linux-foundation.org>2015-05-11 13:54:20 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-05-11 13:54:20 -0400
commitb3e5838ac01c6815fc3d15fd00c8eb23889e5962 (patch)
treedacd93518d825c3b621234e3426d103aa1a8e27a
parentc91aa67eede4cdee97844854bdf5b695ab26893e (diff)
parentdbfe8ef5599a5370abc441fcdbb382b656563eb4 (diff)
Merge branch 'for-4.1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata fixes from Tejun Heo: "Rather big for fixes pull. - SCC controllers never lived to see the light of the day. Both libata and ide drivers removed. - In some configurations, link power management policy changes sometimes cause delayed spurious PHY events which can develop into noticeable failures. This has been reported several times over the years. Gabriele's patches suppress PHY events for a while after LPM policy changes which should help most of these failures without causing too much problem for hotplug use cases. - A few controller specific fixes" [ Hmm. I don't think removing SSC support is really a "fix", but hey, it removes a lot of lines of code. Which I like. So ... good riddance ] * 'for-4.1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ahci: avoton port-disable reset-quirk ata: select DW_DMAC in case of SATA_DWC libata: Blacklist queued TRIM on all Samsung 800-series libata: Ignore spurious PHY event on LPM policy change libata: Add helper to determine when PHY events should be ignored ata: ahci_st: fixup layering violations / drvdata errors Remove celleb-only SCC PATA drivers
Diffstat
-rw-r--r--drivers/ata/Kconfig10
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/ahci.c103
-rw-r--r--drivers/ata/ahci_st.c49
-rw-r--r--drivers/ata/libahci.c3
-rw-r--r--drivers/ata/libata-core.c34
-rw-r--r--drivers/ata/libata-eh.c3
-rw-r--r--drivers/ata/pata_scc.c1110
-rw-r--r--drivers/ide/Kconfig9
-rw-r--r--drivers/ide/Makefile1
-rw-r--r--drivers/ide/scc_pata.c887
-rw-r--r--include/linux/libata.h10
12 files changed, 167 insertions, 2053 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 5f601553b9b0..9dca4b995be0 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -270,6 +270,7 @@ config ATA_PIIX
270config SATA_DWC 270config SATA_DWC
271 tristate "DesignWare Cores SATA support" 271 tristate "DesignWare Cores SATA support"
272 depends on 460EX 272 depends on 460EX
273 select DW_DMAC
273 help 274 help
274 This option enables support for the on-chip SATA controller of the 275 This option enables support for the on-chip SATA controller of the
275 AppliedMicro processor 460EX. 276 AppliedMicro processor 460EX.
@@ -729,15 +730,6 @@ config PATA_SC1200
729 730
730 If unsure, say N. 731 If unsure, say N.
731 732
732config PATA_SCC
733 tristate "Toshiba's Cell Reference Set IDE support"
734 depends on PCI && PPC_CELLEB
735 help
736 This option enables support for the built-in IDE controller on
737 Toshiba Cell Reference Board.
738
739 If unsure, say N.
740
741config PATA_SCH 733config PATA_SCH
742 tristate "Intel SCH PATA support" 734 tristate "Intel SCH PATA support"
743 depends on PCI 735 depends on PCI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index b67e995179a9..40f7865f20a1 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -75,7 +75,6 @@ obj-$(CONFIG_PATA_PDC_OLD) += pata_pdc202xx_old.o
75obj-$(CONFIG_PATA_RADISYS) += pata_radisys.o 75obj-$(CONFIG_PATA_RADISYS) += pata_radisys.o
76obj-$(CONFIG_PATA_RDC) += pata_rdc.o 76obj-$(CONFIG_PATA_RDC) += pata_rdc.o
77obj-$(CONFIG_PATA_SC1200) += pata_sc1200.o 77obj-$(CONFIG_PATA_SC1200) += pata_sc1200.o
78obj-$(CONFIG_PATA_SCC) += pata_scc.o
79obj-$(CONFIG_PATA_SCH) += pata_sch.o 78obj-$(CONFIG_PATA_SCH) += pata_sch.o
80obj-$(CONFIG_PATA_SERVERWORKS) += pata_serverworks.o 79obj-$(CONFIG_PATA_SERVERWORKS) += pata_serverworks.o
81obj-$(CONFIG_PATA_SIL680) += pata_sil680.o 80obj-$(CONFIG_PATA_SIL680) += pata_sil680.o
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index c7a92a743ed0..65ee94454bbd 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -66,6 +66,7 @@ enum board_ids {
66 board_ahci_yes_fbs, 66 board_ahci_yes_fbs,
67 67
68 /* board IDs for specific chipsets in alphabetical order */ 68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_avn,
69 board_ahci_mcp65, 70 board_ahci_mcp65,
70 board_ahci_mcp77, 71 board_ahci_mcp77,
71 board_ahci_mcp89, 72 board_ahci_mcp89,
@@ -84,6 +85,8 @@ enum board_ids {
84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 85static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 86static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline); 87 unsigned long deadline);
88static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
87static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 90static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88static bool is_mcp89_apple(struct pci_dev *pdev); 91static bool is_mcp89_apple(struct pci_dev *pdev);
89static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 92static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
@@ -107,6 +110,11 @@ static struct ata_port_operations ahci_p5wdh_ops = {
107 .hardreset = ahci_p5wdh_hardreset, 110 .hardreset = ahci_p5wdh_hardreset,
108}; 111};
109 112
113static struct ata_port_operations ahci_avn_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_avn_hardreset,
116};
117
110static const struct ata_port_info ahci_port_info[] = { 118static const struct ata_port_info ahci_port_info[] = {
111 /* by features */ 119 /* by features */
112 [board_ahci] = { 120 [board_ahci] = {
@@ -151,6 +159,12 @@ static const struct ata_port_info ahci_port_info[] = {
151 .port_ops = &ahci_ops, 159 .port_ops = &ahci_ops,
152 }, 160 },
153 /* by chipsets */ 161 /* by chipsets */
162 [board_ahci_avn] = {
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_avn_ops,
167 },
154 [board_ahci_mcp65] = { 168 [board_ahci_mcp65] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
156 AHCI_HFLAG_YES_NCQ), 170 AHCI_HFLAG_YES_NCQ),
@@ -290,14 +304,14 @@ static const struct pci_device_id ahci_pci_tbl[] = {
290 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 304 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 305 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 306 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */ 307 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */ 308 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
295 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */ 309 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */ 310 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */ 311 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */ 312 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */ 313 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */ 314 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
301 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 315 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 316 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 317 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
@@ -670,6 +684,79 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
670 return rc; 684 return rc;
671} 685}
672 686
687/*
688 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
689 *
690 * It has been observed with some SSDs that the timing of events in the
691 * link synchronization phase can leave the port in a state that can not
692 * be recovered by a SATA-hard-reset alone. The failing signature is
693 * SStatus.DET stuck at 1 ("Device presence detected but Phy
694 * communication not established"). It was found that unloading and
695 * reloading the driver when this problem occurs allows the drive
696 * connection to be recovered (DET advanced to 0x3). The critical
697 * component of reloading the driver is that the port state machines are
698 * reset by bouncing "port enable" in the AHCI PCS configuration
699 * register. So, reproduce that effect by bouncing a port whenever we
700 * see DET==1 after a reset.
701 */
702static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
703 unsigned long deadline)
704{
705 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
706 struct ata_port *ap = link->ap;
707 struct ahci_port_priv *pp = ap->private_data;
708 struct ahci_host_priv *hpriv = ap->host->private_data;
709 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
710 unsigned long tmo = deadline - jiffies;
711 struct ata_taskfile tf;
712 bool online;
713 int rc, i;
714
715 DPRINTK("ENTER\n");
716
717 ahci_stop_engine(ap);
718
719 for (i = 0; i < 2; i++) {
720 u16 val;
721 u32 sstatus;
722 int port = ap->port_no;
723 struct ata_host *host = ap->host;
724 struct pci_dev *pdev = to_pci_dev(host->dev);
725
726 /* clear D2H reception area to properly wait for D2H FIS */
727 ata_tf_init(link->device, &tf);
728 tf.command = ATA_BUSY;
729 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
730
731 rc = sata_link_hardreset(link, timing, deadline, &online,
732 ahci_check_ready);
733
734 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
735 (sstatus & 0xf) != 1)
736 break;
737
738 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
739 port);
740
741 pci_read_config_word(pdev, 0x92, &val);
742 val &= ~(1 << port);
743 pci_write_config_word(pdev, 0x92, val);
744 ata_msleep(ap, 1000);
745 val |= 1 << port;
746 pci_write_config_word(pdev, 0x92, val);
747 deadline += tmo;
748 }
749
750 hpriv->start_engine(ap);
751
752 if (online)
753 *class = ahci_dev_classify(ap);
754
755 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
756 return rc;
757}
758
759
673#ifdef CONFIG_PM 760#ifdef CONFIG_PM
674static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 761static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
675{ 762{
diff --git a/drivers/ata/ahci_st.c b/drivers/ata/ahci_st.c
index ea0ff005b86c..8ff428fe8e0f 100644
--- a/drivers/ata/ahci_st.c
+++ b/drivers/ata/ahci_st.c
@@ -37,7 +37,6 @@ struct st_ahci_drv_data {
37 struct reset_control *pwr; 37 struct reset_control *pwr;
38 struct reset_control *sw_rst; 38 struct reset_control *sw_rst;
39 struct reset_control *pwr_rst; 39 struct reset_control *pwr_rst;
40 struct ahci_host_priv *hpriv;
41}; 40};
42 41
43static void st_ahci_configure_oob(void __iomem *mmio) 42static void st_ahci_configure_oob(void __iomem *mmio)
@@ -55,9 +54,10 @@ static void st_ahci_configure_oob(void __iomem *mmio)
55 writel(new_val, mmio + ST_AHCI_OOBR); 54 writel(new_val, mmio + ST_AHCI_OOBR);
56} 55}
57 56
58static int st_ahci_deassert_resets(struct device *dev) 57static int st_ahci_deassert_resets(struct ahci_host_priv *hpriv,
58 struct device *dev)
59{ 59{
60 struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev); 60 struct st_ahci_drv_data *drv_data = hpriv->plat_data;
61 int err; 61 int err;
62 62
63 if (drv_data->pwr) { 63 if (drv_data->pwr) {
@@ -90,8 +90,8 @@ static int st_ahci_deassert_resets(struct device *dev)
90static void st_ahci_host_stop(struct ata_host *host) 90static void st_ahci_host_stop(struct ata_host *host)
91{ 91{
92 struct ahci_host_priv *hpriv = host->private_data; 92 struct ahci_host_priv *hpriv = host->private_data;
93 struct st_ahci_drv_data *drv_data = hpriv->plat_data;
93 struct device *dev = host->dev; 94 struct device *dev = host->dev;
94 struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev);
95 int err; 95 int err;
96 96
97 if (drv_data->pwr) { 97 if (drv_data->pwr) {
@@ -103,29 +103,30 @@ static void st_ahci_host_stop(struct ata_host *host)
103 ahci_platform_disable_resources(hpriv); 103 ahci_platform_disable_resources(hpriv);
104} 104}
105 105
106static int st_ahci_probe_resets(struct platform_device *pdev) 106static int st_ahci_probe_resets(struct ahci_host_priv *hpriv,
107 struct device *dev)
107{ 108{
108 struct st_ahci_drv_data *drv_data = platform_get_drvdata(pdev); 109 struct st_ahci_drv_data *drv_data = hpriv->plat_data;
109 110
110 drv_data->pwr = devm_reset_control_get(&pdev->dev, "pwr-dwn"); 111 drv_data->pwr = devm_reset_control_get(dev, "pwr-dwn");
111 if (IS_ERR(drv_data->pwr)) { 112 if (IS_ERR(drv_data->pwr)) {
112 dev_info(&pdev->dev, "power reset control not defined\n"); 113 dev_info(dev, "power reset control not defined\n");
113 drv_data->pwr = NULL; 114 drv_data->pwr = NULL;
114 } 115 }
115 116
116 drv_data->sw_rst = devm_reset_control_get(&pdev->dev, "sw-rst"); 117 drv_data->sw_rst = devm_reset_control_get(dev, "sw-rst");
117 if (IS_ERR(drv_data->sw_rst)) { 118 if (IS_ERR(drv_data->sw_rst)) {
118 dev_info(&pdev->dev, "soft reset control not defined\n"); 119 dev_info(dev, "soft reset control not defined\n");
119 drv_data->sw_rst = NULL; 120 drv_data->sw_rst = NULL;
120 } 121 }
121 122
122 drv_data->pwr_rst = devm_reset_control_get(&pdev->dev, "pwr-rst"); 123 drv_data->pwr_rst = devm_reset_control_get(dev, "pwr-rst");
123 if (IS_ERR(drv_data->pwr_rst)) { 124 if (IS_ERR(drv_data->pwr_rst)) {
124 dev_dbg(&pdev->dev, "power soft reset control not defined\n"); 125 dev_dbg(dev, "power soft reset control not defined\n");
125 drv_data->pwr_rst = NULL; 126 drv_data->pwr_rst = NULL;
126 } 127 }
127 128
128 return st_ahci_deassert_resets(&pdev->dev); 129 return st_ahci_deassert_resets(hpriv, dev);
129} 130}
130 131
131static struct ata_port_operations st_ahci_port_ops = { 132static struct ata_port_operations st_ahci_port_ops = {
@@ -154,15 +155,12 @@ static int st_ahci_probe(struct platform_device *pdev)
154 if (!drv_data) 155 if (!drv_data)
155 return -ENOMEM; 156 return -ENOMEM;
156 157
157 platform_set_drvdata(pdev, drv_data);
158
159 hpriv = ahci_platform_get_resources(pdev); 158 hpriv = ahci_platform_get_resources(pdev);
160 if (IS_ERR(hpriv)) 159 if (IS_ERR(hpriv))
161 return PTR_ERR(hpriv); 160 return PTR_ERR(hpriv);
161 hpriv->plat_data = drv_data;
162 162
163 drv_data->hpriv = hpriv; 163 err = st_ahci_probe_resets(hpriv, &pdev->dev);
164
165 err = st_ahci_probe_resets(pdev);
166 if (err) 164 if (err)
167 return err; 165 return err;
168 166
@@ -170,7 +168,7 @@ static int st_ahci_probe(struct platform_device *pdev)
170 if (err) 168 if (err)
171 return err; 169 return err;
172 170
173 st_ahci_configure_oob(drv_data->hpriv->mmio); 171 st_ahci_configure_oob(hpriv->mmio);
174 172
175 err = ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info, 173 err = ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info,
176 &ahci_platform_sht); 174 &ahci_platform_sht);
@@ -185,8 +183,9 @@ static int st_ahci_probe(struct platform_device *pdev)
185#ifdef CONFIG_PM_SLEEP 183#ifdef CONFIG_PM_SLEEP
186static int st_ahci_suspend(struct device *dev) 184static int st_ahci_suspend(struct device *dev)
187{ 185{
188 struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev); 186 struct ata_host *host = dev_get_drvdata(dev);
189 struct ahci_host_priv *hpriv = drv_data->hpriv; 187 struct ahci_host_priv *hpriv = host->private_data;
188 struct st_ahci_drv_data *drv_data = hpriv->plat_data;
190 int err; 189 int err;
191 190
192 err = ahci_platform_suspend_host(dev); 191 err = ahci_platform_suspend_host(dev);
@@ -208,21 +207,21 @@ static int st_ahci_suspend(struct device *dev)
208 207
209static int st_ahci_resume(struct device *dev) 208static int st_ahci_resume(struct device *dev)
210{ 209{
211 struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev); 210 struct ata_host *host = dev_get_drvdata(dev);
212 struct ahci_host_priv *hpriv = drv_data->hpriv; 211 struct ahci_host_priv *hpriv = host->private_data;
213 int err; 212 int err;
214 213
215 err = ahci_platform_enable_resources(hpriv); 214 err = ahci_platform_enable_resources(hpriv);
216 if (err) 215 if (err)
217 return err; 216 return err;
218 217
219 err = st_ahci_deassert_resets(dev); 218 err = st_ahci_deassert_resets(hpriv, dev);
220 if (err) { 219 if (err) {
221 ahci_platform_disable_resources(hpriv); 220 ahci_platform_disable_resources(hpriv);
222 return err; 221 return err;
223 } 222 }
224 223
225 st_ahci_configure_oob(drv_data->hpriv->mmio); 224 st_ahci_configure_oob(hpriv->mmio);
226 225
227 return ahci_platform_resume_host(dev); 226 return ahci_platform_resume_host(dev);
228} 227}
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index 61a9c07e0dff..287c4ba0219f 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -1707,8 +1707,7 @@ static void ahci_handle_port_interrupt(struct ata_port *ap,
1707 if (unlikely(resetting)) 1707 if (unlikely(resetting))
1708 status &= ~PORT_IRQ_BAD_PMP; 1708 status &= ~PORT_IRQ_BAD_PMP;
1709 1709
1710 /* if LPM is enabled, PHYRDY doesn't mean anything */ 1710 if (sata_lpm_ignore_phy_events(&ap->link)) {
1711 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
1712 status &= ~PORT_IRQ_PHYRDY; 1711 status &= ~PORT_IRQ_PHYRDY;
1713 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1712 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1714 } 1713 }
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index f6cb1f1b30b7..577849c6611a 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -4235,7 +4235,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
4235 ATA_HORKAGE_ZERO_AFTER_TRIM, }, 4235 ATA_HORKAGE_ZERO_AFTER_TRIM, },
4236 { "Crucial_CT*MX100*", "MU01", ATA_HORKAGE_NO_NCQ_TRIM | 4236 { "Crucial_CT*MX100*", "MU01", ATA_HORKAGE_NO_NCQ_TRIM |
4237 ATA_HORKAGE_ZERO_AFTER_TRIM, }, 4237 ATA_HORKAGE_ZERO_AFTER_TRIM, },
4238 { "Samsung SSD 850 PRO*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | 4238 { "Samsung SSD 8*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
4239 ATA_HORKAGE_ZERO_AFTER_TRIM, }, 4239 ATA_HORKAGE_ZERO_AFTER_TRIM, },
4240 4240
4241 /* 4241 /*
@@ -6752,6 +6752,38 @@ u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, u32 val,
6752 return tmp; 6752 return tmp;
6753} 6753}
6754 6754
6755/**
6756 * sata_lpm_ignore_phy_events - test if PHY event should be ignored
6757 * @link: Link receiving the event
6758 *
6759 * Test whether the received PHY event has to be ignored or not.
6760 *
6761 * LOCKING:
6762 * None:
6763 *
6764 * RETURNS:
6765 * True if the event has to be ignored.
6766 */
6767bool sata_lpm_ignore_phy_events(struct ata_link *link)
6768{
6769 unsigned long lpm_timeout = link->last_lpm_change +
6770 msecs_to_jiffies(ATA_TMOUT_SPURIOUS_PHY);
6771
6772 /* if LPM is enabled, PHYRDY doesn't mean anything */
6773 if (link->lpm_policy > ATA_LPM_MAX_POWER)
6774 return true;
6775
6776 /* ignore the first PHY event after the LPM policy changed
6777 * as it is might be spurious
6778 */
6779 if ((link->flags & ATA_LFLAG_CHANGED) &&
6780 time_before(jiffies, lpm_timeout))
6781 return true;
6782
6783 return false;
6784}
6785EXPORT_SYMBOL_GPL(sata_lpm_ignore_phy_events);
6786
6755/* 6787/*
6756 * Dummy port_ops 6788 * Dummy port_ops
6757 */ 6789 */
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index 07f41be38fbe..cf0022ec07f2 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -3597,6 +3597,9 @@ static int ata_eh_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
3597 } 3597 }
3598 } 3598 }
3599 3599
3600 link->last_lpm_change = jiffies;
3601 link->flags |= ATA_LFLAG_CHANGED;
3602
3600 return 0; 3603 return 0;
3601 3604
3602fail: 3605fail:
diff --git a/drivers/ata/pata_scc.c b/drivers/ata/pata_scc.c
deleted file mode 100644
index 5cd60d6388ec..000000000000
--- a/drivers/ata/pata_scc.c
+++ /dev/null
@@ -1,1110 +0,0 @@
1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc
12 *
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
15 *
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/device.h>
41#include <scsi/scsi_host.h>
42#include <linux/libata.h>
43
44#define DRV_NAME "pata_scc"
45#define DRV_VERSION "0.3"
46
47#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
48
49/* PCI BARs */
50#define SCC_CTRL_BAR 0
51#define SCC_BMID_BAR 1
52
53/* offset of CTRL registers */
54#define SCC_CTL_PIOSHT 0x000
55#define SCC_CTL_PIOCT 0x004
56#define SCC_CTL_MDMACT 0x008
57#define SCC_CTL_MCRCST 0x00C
58#define SCC_CTL_SDMACT 0x010
59#define SCC_CTL_SCRCST 0x014
60#define SCC_CTL_UDENVT 0x018
61#define SCC_CTL_TDVHSEL 0x020
62#define SCC_CTL_MODEREG 0x024
63#define SCC_CTL_ECMODE 0xF00
64#define SCC_CTL_MAEA0 0xF50
65#define SCC_CTL_MAEC0 0xF54
66#define SCC_CTL_CCKCTRL 0xFF0
67
68/* offset of BMID registers */
69#define SCC_DMA_CMD 0x000
70#define SCC_DMA_STATUS 0x004
71#define SCC_DMA_TABLE_OFS 0x008
72#define SCC_DMA_INTMASK 0x010
73#define SCC_DMA_INTST 0x014
74#define SCC_DMA_PTERADD 0x018
75#define SCC_REG_CMD_ADDR 0x020
76#define SCC_REG_DATA 0x000
77#define SCC_REG_ERR 0x004
78#define SCC_REG_FEATURE 0x004
79#define SCC_REG_NSECT 0x008
80#define SCC_REG_LBAL 0x00C
81#define SCC_REG_LBAM 0x010
82#define SCC_REG_LBAH 0x014
83#define SCC_REG_DEVICE 0x018
84#define SCC_REG_STATUS 0x01C
85#define SCC_REG_CMD 0x01C
86#define SCC_REG_ALTSTATUS 0x020
87
88/* register value */
89#define TDVHSEL_MASTER 0x00000001
90#define TDVHSEL_SLAVE 0x00000004
91
92#define MODE_JCUSFEN 0x00000080
93
94#define ECMODE_VALUE 0x01
95
96#define CCKCTRL_ATARESET 0x00040000
97#define CCKCTRL_BUFCNT 0x00020000
98#define CCKCTRL_CRST 0x00010000
99#define CCKCTRL_OCLKEN 0x00000100
100#define CCKCTRL_ATACLKOEN 0x00000002
101#define CCKCTRL_LCLKEN 0x00000001
102
103#define QCHCD_IOS_SS 0x00000001
104
105#define QCHSD_STPDIAG 0x00020000
106
107#define INTMASK_MSK 0xD1000012
108#define INTSTS_SERROR 0x80000000
109#define INTSTS_PRERR 0x40000000
110#define INTSTS_RERR 0x10000000
111#define INTSTS_ICERR 0x01000000
112#define INTSTS_BMSINT 0x00000010
113#define INTSTS_BMHE 0x00000008
114#define INTSTS_IOIRQS 0x00000004
115#define INTSTS_INTRQ 0x00000002
116#define INTSTS_ACTEINT 0x00000001
117
118
119/* PIO transfer mode table */
120/* JCHST */
121static const unsigned long JCHSTtbl[2][7] = {
122 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
123 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
124};
125
126/* JCHHT */
127static const unsigned long JCHHTtbl[2][7] = {
128 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
129 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
130};
131
132/* JCHCT */
133static const unsigned long JCHCTtbl[2][7] = {
134 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
135 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
136};
137
138/* DMA transfer mode table */
139/* JCHDCTM/JCHDCTS */
140static const unsigned long JCHDCTxtbl[2][7] = {
141 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
142 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
143};
144
145/* JCSTWTM/JCSTWTS */
146static const unsigned long JCSTWTxtbl[2][7] = {
147 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
148 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
149};
150
151/* JCTSS */
152static const unsigned long JCTSStbl[2][7] = {
153 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
155};
156
157/* JCENVT */
158static const unsigned long JCENVTtbl[2][7] = {
159 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
160 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
161};
162
163/* JCACTSELS/JCACTSELM */
164static const unsigned long JCACTSELtbl[2][7] = {
165 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
166 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
167};
168
169static const struct pci_device_id scc_pci_tbl[] = {
170 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
171 { } /* terminate list */
172};
173
174/**
175 * scc_set_piomode - Initialize host controller PATA PIO timings
176 * @ap: Port whose timings we are configuring
177 * @adev: um
178 *
179 * Set PIO mode for device.
180 *
181 * LOCKING:
182 * None (inherited from caller).
183 */
184
185static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
186{
187 unsigned int pio = adev->pio_mode - XFER_PIO_0;
188 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
189 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
190 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
191 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
192 unsigned long reg;
193 int offset;
194
195 reg = in_be32(cckctrl_port);
196 if (reg & CCKCTRL_ATACLKOEN)
197 offset = 1; /* 133MHz */
198 else
199 offset = 0; /* 100MHz */
200
201 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
202 out_be32(piosht_port, reg);
203 reg = JCHCTtbl[offset][pio];
204 out_be32(pioct_port, reg);
205}
206
207/**
208 * scc_set_dmamode - Initialize host controller PATA DMA timings
209 * @ap: Port whose timings we are configuring
210 * @adev: um
211 *
212 * Set UDMA mode for device.
213 *
214 * LOCKING:
215 * None (inherited from caller).
216 */
217
218static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
219{
220 unsigned int udma = adev->dma_mode;
221 unsigned int is_slave = (adev->devno != 0);
222 u8 speed = udma;
223 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
224 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
225 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
226 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
227 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
228 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
229 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
230 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
231 int offset, idx;
232
233 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
234 offset = 1; /* 133MHz */
235 else
236 offset = 0; /* 100MHz */
237
238 if (speed >= XFER_UDMA_0)
239 idx = speed - XFER_UDMA_0;
240 else
241 return;
242
243 if (is_slave) {
244 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
245 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
246 out_be32(tdvhsel_port,
247 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
248 } else {
249 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
250 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
251 out_be32(tdvhsel_port,
252 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
253 }
254 out_be32(udenvt_port,
255 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
256}
257
258unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
259{
260 /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
261 if (adev->class == ATA_DEV_ATAPI &&
262 (mask & (0xE0 << ATA_SHIFT_UDMA))) {
263 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
264 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
265 }
266 return mask;
267}
268
269/**
270 * scc_tf_load - send taskfile registers to host controller
271 * @ap: Port to which output is sent
272 * @tf: ATA taskfile register set
273 *
274 * Note: Original code is ata_sff_tf_load().
275 */
276
277static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
278{
279 struct ata_ioports *ioaddr = &ap->ioaddr;
280 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
281
282 if (tf->ctl != ap->last_ctl) {
283 out_be32(ioaddr->ctl_addr, tf->ctl);
284 ap->last_ctl = tf->ctl;
285 ata_wait_idle(ap);
286 }
287
288 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
289 out_be32(ioaddr->feature_addr, tf->hob_feature);
290 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
291 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
292 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
293 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
294 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
295 tf->hob_feature,
296 tf->hob_nsect,
297 tf->hob_lbal,
298 tf->hob_lbam,
299 tf->hob_lbah);
300 }
301
302 if (is_addr) {
303 out_be32(ioaddr->feature_addr, tf->feature);
304 out_be32(ioaddr->nsect_addr, tf->nsect);
305 out_be32(ioaddr->lbal_addr, tf->lbal);
306 out_be32(ioaddr->lbam_addr, tf->lbam);
307 out_be32(ioaddr->lbah_addr, tf->lbah);
308 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
309 tf->feature,
310 tf->nsect,
311 tf->lbal,
312 tf->lbam,
313 tf->lbah);
314 }
315
316 if (tf->flags & ATA_TFLAG_DEVICE) {
317 out_be32(ioaddr->device_addr, tf->device);
318 VPRINTK("device 0x%X\n", tf->device);
319 }
320
321 ata_wait_idle(ap);
322}
323
324/**
325 * scc_check_status - Read device status reg & clear interrupt
326 * @ap: port where the device is
327 *
328 * Note: Original code is ata_check_status().
329 */
330
331static u8 scc_check_status (struct ata_port *ap)
332{
333 return in_be32(ap->ioaddr.status_addr);
334}
335
336/**
337 * scc_tf_read - input device's ATA taskfile shadow registers
338 * @ap: Port from which input is read
339 * @tf: ATA taskfile register set for storing input
340 *
341 * Note: Original code is ata_sff_tf_read().
342 */
343
344static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
345{
346 struct ata_ioports *ioaddr = &ap->ioaddr;
347
348 tf->command = scc_check_status(ap);
349 tf->feature = in_be32(ioaddr->error_addr);
350 tf->nsect = in_be32(ioaddr->nsect_addr);
351 tf->lbal = in_be32(ioaddr->lbal_addr);
352 tf->lbam = in_be32(ioaddr->lbam_addr);
353 tf->lbah = in_be32(ioaddr->lbah_addr);
354 tf->device = in_be32(ioaddr->device_addr);
355
356 if (tf->flags & ATA_TFLAG_LBA48) {
357 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
358 tf->hob_feature = in_be32(ioaddr->error_addr);
359 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
360 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
361 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
362 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
363 out_be32(ioaddr->ctl_addr, tf->ctl);
364 ap->last_ctl = tf->ctl;
365 }
366}
367
368/**
369 * scc_exec_command - issue ATA command to host controller
370 * @ap: port to which command is being issued
371 * @tf: ATA taskfile register set
372 *
373 * Note: Original code is ata_sff_exec_command().
374 */
375
376static void scc_exec_command (struct ata_port *ap,
377 const struct ata_taskfile *tf)
378{
379 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
380
381 out_be32(ap->ioaddr.command_addr, tf->command);
382 ata_sff_pause(ap);
383}
384
385/**
386 * scc_check_altstatus - Read device alternate status reg
387 * @ap: port where the device is
388 */
389
390static u8 scc_check_altstatus (struct ata_port *ap)
391{
392 return in_be32(ap->ioaddr.altstatus_addr);
393}
394
395/**
396 * scc_dev_select - Select device 0/1 on ATA bus
397 * @ap: ATA channel to manipulate
398 * @device: ATA device (numbered from zero) to select
399 *
400 * Note: Original code is ata_sff_dev_select().
401 */
402
403static void scc_dev_select (struct ata_port *ap, unsigned int device)
404{
405 u8 tmp;
406
407 if (device == 0)
408 tmp = ATA_DEVICE_OBS;
409 else
410 tmp = ATA_DEVICE_OBS | ATA_DEV1;
411
412 out_be32(ap->ioaddr.device_addr, tmp);
413 ata_sff_pause(ap);
414}
415
416/**
417 * scc_set_devctl - Write device control reg
418 * @ap: port where the device is
419 * @ctl: value to write
420 */
421
422static void scc_set_devctl(struct ata_port *ap, u8 ctl)
423{
424 out_be32(ap->ioaddr.ctl_addr, ctl);
425}
426
427/**
428 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
429 * @qc: Info associated with this ATA transaction.
430 *
431 * Note: Original code is ata_bmdma_setup().
432 */
433
434static void scc_bmdma_setup (struct ata_queued_cmd *qc)
435{
436 struct ata_port *ap = qc->ap;
437 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
438 u8 dmactl;
439 void __iomem *mmio = ap->ioaddr.bmdma_addr;
440
441 /* load PRD table addr */
442 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma);
443
444 /* specify data direction, triple-check start bit is clear */
445 dmactl = in_be32(mmio + SCC_DMA_CMD);
446 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
447 if (!rw)
448 dmactl |= ATA_DMA_WR;
449 out_be32(mmio + SCC_DMA_CMD, dmactl);
450
451 /* issue r/w command */
452 ap->ops->sff_exec_command(ap, &qc->tf);
453}
454
455/**
456 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
457 * @qc: Info associated with this ATA transaction.
458 *
459 * Note: Original code is ata_bmdma_start().
460 */
461
462static void scc_bmdma_start (struct ata_queued_cmd *qc)
463{
464 struct ata_port *ap = qc->ap;
465 u8 dmactl;
466 void __iomem *mmio = ap->ioaddr.bmdma_addr;
467
468 /* start host DMA transaction */
469 dmactl = in_be32(mmio + SCC_DMA_CMD);
470 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
471}
472
473/**
474 * scc_devchk - PATA device presence detection
475 * @ap: ATA channel to examine
476 * @device: Device to examine (starting at zero)
477 *
478 * Note: Original code is ata_devchk().
479 */
480
481static unsigned int scc_devchk (struct ata_port *ap,
482 unsigned int device)
483{
484 struct ata_ioports *ioaddr = &ap->ioaddr;
485 u8 nsect, lbal;
486
487 ap->ops->sff_dev_select(ap, device);
488
489 out_be32(ioaddr->nsect_addr, 0x55);
490 out_be32(ioaddr->lbal_addr, 0xaa);
491
492 out_be32(ioaddr->nsect_addr, 0xaa);
493 out_be32(ioaddr->lbal_addr, 0x55);
494
495 out_be32(ioaddr->nsect_addr, 0x55);
496 out_be32(ioaddr->lbal_addr, 0xaa);
497
498 nsect = in_be32(ioaddr->nsect_addr);
499 lbal = in_be32(ioaddr->lbal_addr);
500
501 if ((nsect == 0x55) && (lbal == 0xaa))
502 return 1; /* we found a device */
503
504 return 0; /* nothing found */
505}
506
507/**
508 * scc_wait_after_reset - wait for devices to become ready after reset
509 *
510 * Note: Original code is ata_sff_wait_after_reset
511 */
512
513static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
514 unsigned long deadline)
515{
516 struct ata_port *ap = link->ap;
517 struct ata_ioports *ioaddr = &ap->ioaddr;
518 unsigned int dev0 = devmask & (1 << 0);
519 unsigned int dev1 = devmask & (1 << 1);
520 int rc, ret = 0;
521
522 /* Spec mandates ">= 2ms" before checking status. We wait
523 * 150ms, because that was the magic delay used for ATAPI
524 * devices in Hale Landis's ATADRVR, for the period of time
525 * between when the ATA command register is written, and then
526 * status is checked. Because waiting for "a while" before
527 * checking status is fine, post SRST, we perform this magic
528 * delay here as well.
529 *
530 * Old drivers/ide uses the 2mS rule and then waits for ready.
531 */
532 ata_msleep(ap, 150);
533
534 /* always check readiness of the master device */
535 rc = ata_sff_wait_ready(link, deadline);
536 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
537 * and TF status is 0xff, bail out on it too.
538 */
539 if (rc)
540 return rc;
541
542 /* if device 1 was found in ata_devchk, wait for register
543 * access briefly, then wait for BSY to clear.
544 */
545 if (dev1) {
546 int i;
547
548 ap->ops->sff_dev_select(ap, 1);
549
550 /* Wait for register access. Some ATAPI devices fail
551 * to set nsect/lbal after reset, so don't waste too
552 * much time on it. We're gonna wait for !BSY anyway.
553 */
554 for (i = 0; i < 2; i++) {
555 u8 nsect, lbal;
556
557 nsect = in_be32(ioaddr->nsect_addr);
558 lbal = in_be32(ioaddr->lbal_addr);
559 if ((nsect == 1) && (lbal == 1))
560 break;
561 ata_msleep(ap, 50); /* give drive a breather */
562 }
563
564 rc = ata_sff_wait_ready(link, deadline);
565 if (rc) {
566 if (rc != -ENODEV)
567 return rc;
568 ret = rc;
569 }
570 }
571
572 /* is all this really necessary? */
573 ap->ops->sff_dev_select(ap, 0);
574 if (dev1)
575 ap->ops->sff_dev_select(ap, 1);
576 if (dev0)
577 ap->ops->sff_dev_select(ap, 0);
578
579 return ret;
580}
581
582/**
583 * scc_bus_softreset - PATA device software reset
584 *
585 * Note: Original code is ata_bus_softreset().
586 */
587
588static int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
589 unsigned long deadline)
590{
591 struct ata_ioports *ioaddr = &ap->ioaddr;
592
593 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
594
595 /* software reset. causes dev0 to be selected */
596 out_be32(ioaddr->ctl_addr, ap->ctl);
597 udelay(20);
598 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
599 udelay(20);
600 out_be32(ioaddr->ctl_addr, ap->ctl);
601
602 return scc_wait_after_reset(&ap->link, devmask, deadline);
603}
604
605/**
606 * scc_softreset - reset host port via ATA SRST
607 * @ap: port to reset
608 * @classes: resulting classes of attached devices
609 * @deadline: deadline jiffies for the operation
610 *
611 * Note: Original code is ata_sff_softreset().
612 */
613
614static int scc_softreset(struct ata_link *link, unsigned int *classes,
615 unsigned long deadline)
616{
617 struct ata_port *ap = link->ap;
618 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
619 unsigned int devmask = 0;
620 int rc;
621 u8 err;
622
623 DPRINTK("ENTER\n");
624
625 /* determine if device 0/1 are present */
626 if (scc_devchk(ap, 0))
627 devmask |= (1 << 0);
628 if (slave_possible && scc_devchk(ap, 1))
629 devmask |= (1 << 1);
630
631 /* select device 0 again */
632 ap->ops->sff_dev_select(ap, 0);
633
634 /* issue bus reset */
635 DPRINTK("about to softreset, devmask=%x\n", devmask);
636 rc = scc_bus_softreset(ap, devmask, deadline);
637 if (rc) {
638 ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", rc);
639 return -EIO;
640 }
641
642 /* determine by signature whether we have ATA or ATAPI devices */
643 classes[0] = ata_sff_dev_classify(&ap->link.device[0],
644 devmask & (1 << 0), &err);
645 if (slave_possible && err != 0x81)
646 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
647 devmask & (1 << 1), &err);
648
649 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
650 return 0;
651}
652
653/**
654 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
655 * @qc: Command we are ending DMA for
656 */
657
658static void scc_bmdma_stop (struct ata_queued_cmd *qc)
659{
660 struct ata_port *ap = qc->ap;
661 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
662 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
663 u32 reg;
664
665 while (1) {
666 reg = in_be32(bmid_base + SCC_DMA_INTST);
667
668 if (reg & INTSTS_SERROR) {
669 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
670 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
671 out_be32(bmid_base + SCC_DMA_CMD,
672 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
673 continue;
674 }
675
676 if (reg & INTSTS_PRERR) {
677 u32 maea0, maec0;
678 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
679 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
680 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
681 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
682 out_be32(bmid_base + SCC_DMA_CMD,
683 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
684 continue;
685 }
686
687 if (reg & INTSTS_RERR) {
688 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
689 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
690 out_be32(bmid_base + SCC_DMA_CMD,
691 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
692 continue;
693 }
694
695 if (reg & INTSTS_ICERR) {
696 out_be32(bmid_base + SCC_DMA_CMD,
697 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
698 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
699 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
700 continue;
701 }
702
703 if (reg & INTSTS_BMSINT) {
704 unsigned int classes;
705 unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
706 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
707 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
708 /* TBD: SW reset */
709 scc_softreset(&ap->link, &classes, deadline);
710 continue;
711 }
712
713 if (reg & INTSTS_BMHE) {
714 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
715 continue;
716 }
717
718 if (reg & INTSTS_ACTEINT) {
719 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
720 continue;
721 }
722
723 if (reg & INTSTS_IOIRQS) {
724 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
725 continue;
726 }
727 break;
728 }
729
730 /* clear start/stop bit */
731 out_be32(bmid_base + SCC_DMA_CMD,
732 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
733
734 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
735 ata_sff_dma_pause(ap); /* dummy read */
736}
737
738/**
739 * scc_bmdma_status - Read PCI IDE BMDMA status
740 * @ap: Port associated with this ATA transaction.
741 */
742
743static u8 scc_bmdma_status (struct ata_port *ap)
744{
745 void __iomem *mmio = ap->ioaddr.bmdma_addr;
746 u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
747 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
748 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
749 static int retry = 0;
750
751 /* return if IOS_SS is cleared */
752 if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
753 return host_stat;
754
755 /* errata A252,A308 workaround: Step4 */
756 if ((scc_check_altstatus(ap) & ATA_ERR)
757 && (int_status & INTSTS_INTRQ))
758 return (host_stat | ATA_DMA_INTR);
759
760 /* errata A308 workaround Step5 */
761 if (int_status & INTSTS_IOIRQS) {
762 host_stat |= ATA_DMA_INTR;
763
764 /* We don't check ATAPI DMA because it is limited to UDMA4 */
765 if ((qc->tf.protocol == ATA_PROT_DMA &&
766 qc->dev->xfer_mode > XFER_UDMA_4)) {
767 if (!(int_status & INTSTS_ACTEINT)) {
768 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
769 ap->print_id);
770 host_stat |= ATA_DMA_ERR;
771 if (retry++)
772 ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
773 } else
774 retry = 0;
775 }
776 }
777
778 return host_stat;
779}
780
781/**
782 * scc_data_xfer - Transfer data by PIO
783 * @dev: device for this I/O
784 * @buf: data buffer
785 * @buflen: buffer length
786 * @rw: read/write
787 *
788 * Note: Original code is ata_sff_data_xfer().
789 */
790
791static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
792 unsigned int buflen, int rw)
793{
794 struct ata_port *ap = dev->link->ap;
795 unsigned int words = buflen >> 1;
796 unsigned int i;
797 __le16 *buf16 = (__le16 *) buf;
798 void __iomem *mmio = ap->ioaddr.data_addr;
799
800 /* Transfer multiple of 2 bytes */
801 if (rw == READ)
802 for (i = 0; i < words; i++)
803 buf16[i] = cpu_to_le16(in_be32(mmio));
804 else
805 for (i = 0; i < words; i++)
806 out_be32(mmio, le16_to_cpu(buf16[i]));
807
808 /* Transfer trailing 1 byte, if any. */
809 if (unlikely(buflen & 0x01)) {
810 __le16 align_buf[1] = { 0 };
811 unsigned char *trailing_buf = buf + buflen - 1;
812
813 if (rw == READ) {
814 align_buf[0] = cpu_to_le16(in_be32(mmio));
815 memcpy(trailing_buf, align_buf, 1);
816 } else {
817 memcpy(align_buf, trailing_buf, 1);
818 out_be32(mmio, le16_to_cpu(align_buf[0]));
819 }
820 words++;
821 }
822
823 return words << 1;
824}
825
826/**
827 * scc_postreset - standard postreset callback
828 * @ap: the target ata_port
829 * @classes: classes of attached devices
830 *
831 * Note: Original code is ata_sff_postreset().
832 */
833
834static void scc_postreset(struct ata_link *link, unsigned int *classes)
835{
836 struct ata_port *ap = link->ap;
837
838 DPRINTK("ENTER\n");
839
840 /* is double-select really necessary? */
841 if (classes[0] != ATA_DEV_NONE)
842 ap->ops->sff_dev_select(ap, 1);
843 if (classes[1] != ATA_DEV_NONE)
844 ap->ops->sff_dev_select(ap, 0);
845
846 /* bail out if no device is present */
847 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
848 DPRINTK("EXIT, no device\n");
849 return;
850 }
851
852 /* set up device control */
853 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
854
855 DPRINTK("EXIT\n");
856}
857
858/**
859 * scc_irq_clear - Clear PCI IDE BMDMA interrupt.
860 * @ap: Port associated with this ATA transaction.
861 *
862 * Note: Original code is ata_bmdma_irq_clear().
863 */
864
865static void scc_irq_clear (struct ata_port *ap)
866{
867 void __iomem *mmio = ap->ioaddr.bmdma_addr;
868
869 if (!mmio)
870 return;
871
872 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
873}
874
875/**
876 * scc_port_start - Set port up for dma.
877 * @ap: Port to initialize
878 *
879 * Allocate space for PRD table using ata_bmdma_port_start().
880 * Set PRD table address for PTERADD. (PRD Transfer End Read)
881 */
882
883static int scc_port_start (struct ata_port *ap)
884{
885 void __iomem *mmio = ap->ioaddr.bmdma_addr;
886 int rc;
887
888 rc = ata_bmdma_port_start(ap);
889 if (rc)
890 return rc;
891
892 out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma);
893 return 0;
894}
895
896/**
897 * scc_port_stop - Undo scc_port_start()
898 * @ap: Port to shut down
899 *
900 * Reset PTERADD.
901 */
902
903static void scc_port_stop (struct ata_port *ap)
904{
905 void __iomem *mmio = ap->ioaddr.bmdma_addr;
906
907 out_be32(mmio + SCC_DMA_PTERADD, 0);
908}
909
910static struct scsi_host_template scc_sht = {
911 ATA_BMDMA_SHT(DRV_NAME),
912};
913
914static struct ata_port_operations scc_pata_ops = {
915 .inherits = &ata_bmdma_port_ops,
916
917 .set_piomode = scc_set_piomode,
918 .set_dmamode = scc_set_dmamode,
919 .mode_filter = scc_mode_filter,
920
921 .sff_tf_load = scc_tf_load,
922 .sff_tf_read = scc_tf_read,
923 .sff_exec_command = scc_exec_command,
924 .sff_check_status = scc_check_status,
925 .sff_check_altstatus = scc_check_altstatus,
926 .sff_dev_select = scc_dev_select,
927 .sff_set_devctl = scc_set_devctl,
928
929 .bmdma_setup = scc_bmdma_setup,
930 .bmdma_start = scc_bmdma_start,
931 .bmdma_stop = scc_bmdma_stop,
932 .bmdma_status = scc_bmdma_status,
933 .sff_data_xfer = scc_data_xfer,
934
935 .cable_detect = ata_cable_80wire,
936 .softreset = scc_softreset,
937 .postreset = scc_postreset,
938
939 .sff_irq_clear = scc_irq_clear,
940
941 .port_start = scc_port_start,
942 .port_stop = scc_port_stop,
943};
944
945static struct ata_port_info scc_port_info[] = {
946 {
947 .flags = ATA_FLAG_SLAVE_POSS,
948 .pio_mask = ATA_PIO4,
949 /* No MWDMA */
950 .udma_mask = ATA_UDMA6,
951 .port_ops = &scc_pata_ops,
952 },
953};
954
955/**
956 * scc_reset_controller - initialize SCC PATA controller.
957 */
958
959static int scc_reset_controller(struct ata_host *host)
960{
961 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
962 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
963 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
964 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
965 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
966 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
967 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
968 u32 reg = 0;
969
970 out_be32(cckctrl_port, reg);
971 reg |= CCKCTRL_ATACLKOEN;
972 out_be32(cckctrl_port, reg);
973 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
974 out_be32(cckctrl_port, reg);
975 reg |= CCKCTRL_CRST;
976 out_be32(cckctrl_port, reg);
977
978 for (;;) {
979 reg = in_be32(cckctrl_port);
980 if (reg & CCKCTRL_CRST)
981 break;
982 udelay(5000);
983 }
984
985 reg |= CCKCTRL_ATARESET;
986 out_be32(cckctrl_port, reg);
987 out_be32(ecmode_port, ECMODE_VALUE);
988 out_be32(mode_port, MODE_JCUSFEN);
989 out_be32(intmask_port, INTMASK_MSK);
990
991 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
992 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
993 return -EIO;
994 }
995
996 return 0;
997}
998
999/**
1000 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1001 * @ioaddr: IO address structure to be initialized
1002 * @base: base address of BMID region
1003 */
1004
1005static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1006{
1007 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1008 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1009 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1010 ioaddr->bmdma_addr = base;
1011 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1012 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1013 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1014 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1015 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1016 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1017 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1018 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1019 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1020 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1021}
1022
1023static int scc_host_init(struct ata_host *host)
1024{
1025 struct pci_dev *pdev = to_pci_dev(host->dev);
1026 int rc;
1027
1028 rc = scc_reset_controller(host);
1029 if (rc)
1030 return rc;
1031
1032 rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
1033 if (rc)
1034 return rc;
1035 rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
1036 if (rc)
1037 return rc;
1038
1039 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
1040
1041 pci_set_master(pdev);
1042
1043 return 0;
1044}
1045
1046/**
1047 * scc_init_one - Register SCC PATA device with kernel services
1048 * @pdev: PCI device to register
1049 * @ent: Entry in scc_pci_tbl matching with @pdev
1050 *
1051 * LOCKING:
1052 * Inherited from PCI layer (may sleep).
1053 *
1054 * RETURNS:
1055 * Zero on success, or -ERRNO value.
1056 */
1057
1058static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1059{
1060 unsigned int board_idx = (unsigned int) ent->driver_data;
1061 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
1062 struct ata_host *host;
1063 int rc;
1064
1065 ata_print_version_once(&pdev->dev, DRV_VERSION);
1066
1067 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1068 if (!host)
1069 return -ENOMEM;
1070
1071 rc = pcim_enable_device(pdev);
1072 if (rc)
1073 return rc;
1074
1075 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1076 if (rc == -EBUSY)
1077 pcim_pin_device(pdev);
1078 if (rc)
1079 return rc;
1080 host->iomap = pcim_iomap_table(pdev);
1081
1082 ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1083 ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1084
1085 rc = scc_host_init(host);
1086 if (rc)
1087 return rc;
1088
1089 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
1090 IRQF_SHARED, &scc_sht);
1091}
1092
1093static struct pci_driver scc_pci_driver = {
1094 .name = DRV_NAME,
1095 .id_table = scc_pci_tbl,
1096 .probe = scc_init_one,
1097 .remove = ata_pci_remove_one,
1098#ifdef CONFIG_PM_SLEEP
1099 .suspend = ata_pci_device_suspend,
1100 .resume = ata_pci_device_resume,
1101#endif
1102};
1103
1104module_pci_driver(scc_pci_driver);
1105
1106MODULE_AUTHOR("Toshiba corp");
1107MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1108MODULE_LICENSE("GPL");
1109MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1110MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index a04c49f2a011..39ea67f9b066 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -643,15 +643,6 @@ config BLK_DEV_TC86C001
643 help 643 help
644 This driver adds support for Toshiba TC86C001 GOKU-S chip. 644 This driver adds support for Toshiba TC86C001 GOKU-S chip.
645 645
646config BLK_DEV_CELLEB
647 tristate "Toshiba's Cell Reference Set IDE support"
648 depends on PPC_CELLEB
649 select BLK_DEV_IDEDMA_PCI
650 help
651 This driver provides support for the on-board IDE controller on
652 Toshiba Cell Reference Board.
653 If unsure, say Y.
654
655endif 646endif
656 647
657# TODO: BLK_DEV_IDEDMA_PCI -> BLK_DEV_IDEDMA_SFF 648# TODO: BLK_DEV_IDEDMA_PCI -> BLK_DEV_IDEDMA_SFF
diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile
index a04ee82f1c8f..2a8c417d4081 100644
--- a/drivers/ide/Makefile
+++ b/drivers/ide/Makefile
@@ -38,7 +38,6 @@ obj-$(CONFIG_BLK_DEV_AEC62XX) += aec62xx.o
38obj-$(CONFIG_BLK_DEV_ALI15X3) += alim15x3.o 38obj-$(CONFIG_BLK_DEV_ALI15X3) += alim15x3.o
39obj-$(CONFIG_BLK_DEV_AMD74XX) += amd74xx.o 39obj-$(CONFIG_BLK_DEV_AMD74XX) += amd74xx.o
40obj-$(CONFIG_BLK_DEV_ATIIXP) += atiixp.o 40obj-$(CONFIG_BLK_DEV_ATIIXP) += atiixp.o
41obj-$(CONFIG_BLK_DEV_CELLEB) += scc_pata.o
42obj-$(CONFIG_BLK_DEV_CMD64X) += cmd64x.o 41obj-$(CONFIG_BLK_DEV_CMD64X) += cmd64x.o
43obj-$(CONFIG_BLK_DEV_CS5520) += cs5520.o 42obj-$(CONFIG_BLK_DEV_CS5520) += cs5520.o
44obj-$(CONFIG_BLK_DEV_CS5530) += cs5530.o 43obj-$(CONFIG_BLK_DEV_CS5530) += cs5530.o
diff --git a/drivers/ide/scc_pata.c b/drivers/ide/scc_pata.c
deleted file mode 100644
index 2a2d188b5d5b..000000000000
--- a/drivers/ide/scc_pata.c
+++ /dev/null
@@ -1,887 +0,0 @@
1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/init.h>
31
32#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
33
34#define SCC_PATA_NAME "scc IDE"
35
36#define TDVHSEL_MASTER 0x00000001
37#define TDVHSEL_SLAVE 0x00000004
38
39#define MODE_JCUSFEN 0x00000080
40
41#define CCKCTRL_ATARESET 0x00040000
42#define CCKCTRL_BUFCNT 0x00020000
43#define CCKCTRL_CRST 0x00010000
44#define CCKCTRL_OCLKEN 0x00000100
45#define CCKCTRL_ATACLKOEN 0x00000002
46#define CCKCTRL_LCLKEN 0x00000001
47
48#define QCHCD_IOS_SS 0x00000001
49
50#define QCHSD_STPDIAG 0x00020000
51
52#define INTMASK_MSK 0xD1000012
53#define INTSTS_SERROR 0x80000000
54#define INTSTS_PRERR 0x40000000
55#define INTSTS_RERR 0x10000000
56#define INTSTS_ICERR 0x01000000
57#define INTSTS_BMSINT 0x00000010
58#define INTSTS_BMHE 0x00000008
59#define INTSTS_IOIRQS 0x00000004
60#define INTSTS_INTRQ 0x00000002
61#define INTSTS_ACTEINT 0x00000001
62
63#define ECMODE_VALUE 0x01
64
65static struct scc_ports {
66 unsigned long ctl, dma;
67 struct ide_host *host; /* for removing port from system */
68} scc_ports[MAX_HWIFS];
69
70/* PIO transfer mode table */
71/* JCHST */
72static unsigned long JCHSTtbl[2][7] = {
73 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
74 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
75};
76
77/* JCHHT */
78static unsigned long JCHHTtbl[2][7] = {
79 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
80 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
81};
82
83/* JCHCT */
84static unsigned long JCHCTtbl[2][7] = {
85 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
86 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
87};
88
89
90/* DMA transfer mode table */
91/* JCHDCTM/JCHDCTS */
92static unsigned long JCHDCTxtbl[2][7] = {
93 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
94 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
95};
96
97/* JCSTWTM/JCSTWTS */
98static unsigned long JCSTWTxtbl[2][7] = {
99 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
100 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
101};
102
103/* JCTSS */
104static unsigned long JCTSStbl[2][7] = {
105 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
107};
108
109/* JCENVT */
110static unsigned long JCENVTtbl[2][7] = {
111 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
112 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
113};
114
115/* JCACTSELS/JCACTSELM */
116static unsigned long JCACTSELtbl[2][7] = {
117 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
118 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
119};
120
121
122static u8 scc_ide_inb(unsigned long port)
123{
124 u32 data = in_be32((void*)port);
125 return (u8)data;
126}
127
128static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
129{
130 out_be32((void *)hwif->io_ports.command_addr, cmd);
131 eieio();
132 in_be32((void *)(hwif->dma_base + 0x01c));
133 eieio();
134}
135
136static u8 scc_read_status(ide_hwif_t *hwif)
137{
138 return (u8)in_be32((void *)hwif->io_ports.status_addr);
139}
140
141static u8 scc_read_altstatus(ide_hwif_t *hwif)
142{
143 return (u8)in_be32((void *)hwif->io_ports.ctl_addr);
144}
145
146static u8 scc_dma_sff_read_status(ide_hwif_t *hwif)
147{
148 return (u8)in_be32((void *)(hwif->dma_base + 4));
149}
150
151static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl)
152{
153 out_be32((void *)hwif->io_ports.ctl_addr, ctl);
154 eieio();
155 in_be32((void *)(hwif->dma_base + 0x01c));
156 eieio();
157}
158
159static void scc_ide_insw(unsigned long port, void *addr, u32 count)
160{
161 u16 *ptr = (u16 *)addr;
162 while (count--) {
163 *ptr++ = le16_to_cpu(in_be32((void*)port));
164 }
165}
166
167static void scc_ide_insl(unsigned long port, void *addr, u32 count)
168{
169 u16 *ptr = (u16 *)addr;
170 while (count--) {
171 *ptr++ = le16_to_cpu(in_be32((void*)port));
172 *ptr++ = le16_to_cpu(in_be32((void*)port));
173 }
174}
175
176static void scc_ide_outb(u8 addr, unsigned long port)
177{
178 out_be32((void*)port, addr);
179}
180
181static void
182scc_ide_outsw(unsigned long port, void *addr, u32 count)
183{
184 u16 *ptr = (u16 *)addr;
185 while (count--) {
186 out_be32((void*)port, cpu_to_le16(*ptr++));
187 }
188}
189
190static void
191scc_ide_outsl(unsigned long port, void *addr, u32 count)
192{
193 u16 *ptr = (u16 *)addr;
194 while (count--) {
195 out_be32((void*)port, cpu_to_le16(*ptr++));
196 out_be32((void*)port, cpu_to_le16(*ptr++));
197 }
198}
199
200/**
201 * scc_set_pio_mode - set host controller for PIO mode
202 * @hwif: port
203 * @drive: drive
204 *
205 * Load the timing settings for this device mode into the
206 * controller.
207 */
208
209static void scc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
210{
211 struct scc_ports *ports = ide_get_hwifdata(hwif);
212 unsigned long ctl_base = ports->ctl;
213 unsigned long cckctrl_port = ctl_base + 0xff0;
214 unsigned long piosht_port = ctl_base + 0x000;
215 unsigned long pioct_port = ctl_base + 0x004;
216 unsigned long reg;
217 int offset;
218 const u8 pio = drive->pio_mode - XFER_PIO_0;
219
220 reg = in_be32((void __iomem *)cckctrl_port);
221 if (reg & CCKCTRL_ATACLKOEN) {
222 offset = 1; /* 133MHz */
223 } else {
224 offset = 0; /* 100MHz */
225 }
226 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
227 out_be32((void __iomem *)piosht_port, reg);
228 reg = JCHCTtbl[offset][pio];
229 out_be32((void __iomem *)pioct_port, reg);
230}
231
232/**
233 * scc_set_dma_mode - set host controller for DMA mode
234 * @hwif: port
235 * @drive: drive
236 *
237 * Load the timing settings for this device mode into the
238 * controller.
239 */
240
241static void scc_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
242{
243 struct scc_ports *ports = ide_get_hwifdata(hwif);
244 unsigned long ctl_base = ports->ctl;
245 unsigned long cckctrl_port = ctl_base + 0xff0;
246 unsigned long mdmact_port = ctl_base + 0x008;
247 unsigned long mcrcst_port = ctl_base + 0x00c;
248 unsigned long sdmact_port = ctl_base + 0x010;
249 unsigned long scrcst_port = ctl_base + 0x014;
250 unsigned long udenvt_port = ctl_base + 0x018;
251 unsigned long tdvhsel_port = ctl_base + 0x020;
252 int is_slave = drive->dn & 1;
253 int offset, idx;
254 unsigned long reg;
255 unsigned long jcactsel;
256 const u8 speed = drive->dma_mode;
257
258 reg = in_be32((void __iomem *)cckctrl_port);
259 if (reg & CCKCTRL_ATACLKOEN) {
260 offset = 1; /* 133MHz */
261 } else {
262 offset = 0; /* 100MHz */
263 }
264
265 idx = speed - XFER_UDMA_0;
266
267 jcactsel = JCACTSELtbl[offset][idx];
268 if (is_slave) {
269 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
270 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
271 jcactsel = jcactsel << 2;
272 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
273 } else {
274 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
275 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
276 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
277 }
278 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
279 out_be32((void __iomem *)udenvt_port, reg);
280}
281
282static void scc_dma_host_set(ide_drive_t *drive, int on)
283{
284 ide_hwif_t *hwif = drive->hwif;
285 u8 unit = drive->dn & 1;
286 u8 dma_stat = scc_dma_sff_read_status(hwif);
287
288 if (on)
289 dma_stat |= (1 << (5 + unit));
290 else
291 dma_stat &= ~(1 << (5 + unit));
292
293 scc_ide_outb(dma_stat, hwif->dma_base + 4);
294}
295
296/**
297 * scc_dma_setup - begin a DMA phase
298 * @drive: target device
299 * @cmd: command
300 *
301 * Build an IDE DMA PRD (IDE speak for scatter gather table)
302 * and then set up the DMA transfer registers.
303 *
304 * Returns 0 on success. If a PIO fallback is required then 1
305 * is returned.
306 */
307
308static int scc_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
309{
310 ide_hwif_t *hwif = drive->hwif;
311 u32 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
312 u8 dma_stat;
313
314 /* fall back to pio! */
315 if (ide_build_dmatable(drive, cmd) == 0)
316 return 1;
317
318 /* PRD table */
319 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
320
321 /* specify r/w */
322 out_be32((void __iomem *)hwif->dma_base, rw);
323
324 /* read DMA status for INTR & ERROR flags */
325 dma_stat = scc_dma_sff_read_status(hwif);
326
327 /* clear INTR & ERROR flags */
328 out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);
329
330 return 0;
331}
332
333static void scc_dma_start(ide_drive_t *drive)
334{
335 ide_hwif_t *hwif = drive->hwif;
336 u8 dma_cmd = scc_ide_inb(hwif->dma_base);
337
338 /* start DMA */
339 scc_ide_outb(dma_cmd | 1, hwif->dma_base);
340}
341
342static int __scc_dma_end(ide_drive_t *drive)
343{
344 ide_hwif_t *hwif = drive->hwif;
345 u8 dma_stat, dma_cmd;
346
347 /* get DMA command mode */
348 dma_cmd = scc_ide_inb(hwif->dma_base);
349 /* stop DMA */
350 scc_ide_outb(dma_cmd & ~1, hwif->dma_base);
351 /* get DMA status */
352 dma_stat = scc_dma_sff_read_status(hwif);
353 /* clear the INTR & ERROR bits */
354 scc_ide_outb(dma_stat | 6, hwif->dma_base + 4);
355 /* verify good DMA status */
356 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
357}
358
359/**
360 * scc_dma_end - Stop DMA
361 * @drive: IDE drive
362 *
363 * Check and clear INT Status register.
364 * Then call __scc_dma_end().
365 */
366
367static int scc_dma_end(ide_drive_t *drive)
368{
369 ide_hwif_t *hwif = drive->hwif;
370 void __iomem *dma_base = (void __iomem *)hwif->dma_base;
371 unsigned long intsts_port = hwif->dma_base + 0x014;
372 u32 reg;
373 int dma_stat, data_loss = 0;
374 static int retry = 0;
375
376 /* errata A308 workaround: Step5 (check data loss) */
377 /* We don't check non ide_disk because it is limited to UDMA4 */
378 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
379 & ATA_ERR) &&
380 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
381 reg = in_be32((void __iomem *)intsts_port);
382 if (!(reg & INTSTS_ACTEINT)) {
383 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
384 drive->name);
385 data_loss = 1;
386 if (retry++) {
387 struct request *rq = hwif->rq;
388 ide_drive_t *drive;
389 int i;
390
391 /* ERROR_RESET and drive->crc_count are needed
392 * to reduce DMA transfer mode in retry process.
393 */
394 if (rq)
395 rq->errors |= ERROR_RESET;
396
397 ide_port_for_each_dev(i, drive, hwif)
398 drive->crc_count++;
399 }
400 }
401 }
402
403 while (1) {
404 reg = in_be32((void __iomem *)intsts_port);
405
406 if (reg & INTSTS_SERROR) {
407 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
408 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
409
410 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
411 continue;
412 }
413
414 if (reg & INTSTS_PRERR) {
415 u32 maea0, maec0;
416 unsigned long ctl_base = hwif->config_data;
417
418 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
419 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
420
421 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
422
423 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
424
425 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
426 continue;
427 }
428
429 if (reg & INTSTS_RERR) {
430 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
431 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
432
433 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
434 continue;
435 }
436
437 if (reg & INTSTS_ICERR) {
438 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
439
440 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
441 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
442 continue;
443 }
444
445 if (reg & INTSTS_BMSINT) {
446 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
447 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
448
449 ide_do_reset(drive);
450 continue;
451 }
452
453 if (reg & INTSTS_BMHE) {
454 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
455 continue;
456 }
457
458 if (reg & INTSTS_ACTEINT) {
459 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
460 continue;
461 }
462
463 if (reg & INTSTS_IOIRQS) {
464 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
465 continue;
466 }
467 break;
468 }
469
470 dma_stat = __scc_dma_end(drive);
471 if (data_loss)
472 dma_stat |= 2; /* emulate DMA error (to retry command) */
473 return dma_stat;
474}
475
476/* returns 1 if dma irq issued, 0 otherwise */
477static int scc_dma_test_irq(ide_drive_t *drive)
478{
479 ide_hwif_t *hwif = drive->hwif;
480 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
481
482 /* SCC errata A252,A308 workaround: Step4 */
483 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
484 & ATA_ERR) &&
485 (int_stat & INTSTS_INTRQ))
486 return 1;
487
488 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
489 if (int_stat & INTSTS_IOIRQS)
490 return 1;
491
492 return 0;
493}
494
495static u8 scc_udma_filter(ide_drive_t *drive)
496{
497 ide_hwif_t *hwif = drive->hwif;
498 u8 mask = hwif->ultra_mask;
499
500 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
501 if ((drive->media != ide_disk) && (mask & 0xE0)) {
502 printk(KERN_INFO "%s: limit %s to UDMA4\n",
503 SCC_PATA_NAME, drive->name);
504 mask = ATA_UDMA4;
505 }
506
507 return mask;
508}
509
510/**
511 * setup_mmio_scc - map CTRL/BMID region
512 * @dev: PCI device we are configuring
513 * @name: device name
514 *
515 */
516
517static int setup_mmio_scc (struct pci_dev *dev, const char *name)
518{
519 void __iomem *ctl_addr;
520 void __iomem *dma_addr;
521 int i, ret;
522
523 for (i = 0; i < MAX_HWIFS; i++) {
524 if (scc_ports[i].ctl == 0)
525 break;
526 }
527 if (i >= MAX_HWIFS)
528 return -ENOMEM;
529
530 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
531 if (ret < 0) {
532 printk(KERN_ERR "%s: can't reserve resources\n", name);
533 return ret;
534 }
535
536 ctl_addr = pci_ioremap_bar(dev, 0);
537 if (!ctl_addr)
538 goto fail_0;
539
540 dma_addr = pci_ioremap_bar(dev, 1);
541 if (!dma_addr)
542 goto fail_1;
543
544 pci_set_master(dev);
545 scc_ports[i].ctl = (unsigned long)ctl_addr;
546 scc_ports[i].dma = (unsigned long)dma_addr;
547 pci_set_drvdata(dev, (void *) &scc_ports[i]);
548
549 return 1;
550
551 fail_1:
552 iounmap(ctl_addr);
553 fail_0:
554 return -ENOMEM;
555}
556
557static int scc_ide_setup_pci_device(struct pci_dev *dev,
558 const struct ide_port_info *d)
559{
560 struct scc_ports *ports = pci_get_drvdata(dev);
561 struct ide_host *host;
562 struct ide_hw hw, *hws[] = { &hw };
563 int i, rc;
564
565 memset(&hw, 0, sizeof(hw));
566 for (i = 0; i <= 8; i++)
567 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
568 hw.irq = dev->irq;
569 hw.dev = &dev->dev;
570
571 rc = ide_host_add(d, hws, 1, &host);
572 if (rc)
573 return rc;
574
575 ports->host = host;
576
577 return 0;
578}
579
580/**
581 * init_setup_scc - set up an SCC PATA Controller
582 * @dev: PCI device
583 * @d: IDE port info
584 *
585 * Perform the initial set up for this device.
586 */
587
588static int init_setup_scc(struct pci_dev *dev, const struct ide_port_info *d)
589{
590 unsigned long ctl_base;
591 unsigned long dma_base;
592 unsigned long cckctrl_port;
593 unsigned long intmask_port;
594 unsigned long mode_port;
595 unsigned long ecmode_port;
596 u32 reg = 0;
597 struct scc_ports *ports;
598 int rc;
599
600 rc = pci_enable_device(dev);
601 if (rc)
602 goto end;
603
604 rc = setup_mmio_scc(dev, d->name);
605 if (rc < 0)
606 goto end;
607
608 ports = pci_get_drvdata(dev);
609 ctl_base = ports->ctl;
610 dma_base = ports->dma;
611 cckctrl_port = ctl_base + 0xff0;
612 intmask_port = dma_base + 0x010;
613 mode_port = ctl_base + 0x024;
614 ecmode_port = ctl_base + 0xf00;
615
616 /* controller initialization */
617 reg = 0;
618 out_be32((void*)cckctrl_port, reg);
619 reg |= CCKCTRL_ATACLKOEN;
620 out_be32((void*)cckctrl_port, reg);
621 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
622 out_be32((void*)cckctrl_port, reg);
623 reg |= CCKCTRL_CRST;
624 out_be32((void*)cckctrl_port, reg);
625
626 for (;;) {
627 reg = in_be32((void*)cckctrl_port);
628 if (reg & CCKCTRL_CRST)
629 break;
630 udelay(5000);
631 }
632
633 reg |= CCKCTRL_ATARESET;
634 out_be32((void*)cckctrl_port, reg);
635
636 out_be32((void*)ecmode_port, ECMODE_VALUE);
637 out_be32((void*)mode_port, MODE_JCUSFEN);
638 out_be32((void*)intmask_port, INTMASK_MSK);
639
640 rc = scc_ide_setup_pci_device(dev, d);
641
642 end:
643 return rc;
644}
645
646static void scc_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
647{
648 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
649
650 if (valid & IDE_VALID_FEATURE)
651 scc_ide_outb(tf->feature, io_ports->feature_addr);
652 if (valid & IDE_VALID_NSECT)
653 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
654 if (valid & IDE_VALID_LBAL)
655 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
656 if (valid & IDE_VALID_LBAM)
657 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
658 if (valid & IDE_VALID_LBAH)
659 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
660 if (valid & IDE_VALID_DEVICE)
661 scc_ide_outb(tf->device, io_ports->device_addr);
662}
663
664static void scc_tf_read(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
665{
666 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
667
668 if (valid & IDE_VALID_ERROR)
669 tf->error = scc_ide_inb(io_ports->feature_addr);
670 if (valid & IDE_VALID_NSECT)
671 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
672 if (valid & IDE_VALID_LBAL)
673 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
674 if (valid & IDE_VALID_LBAM)
675 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
676 if (valid & IDE_VALID_LBAH)
677 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
678 if (valid & IDE_VALID_DEVICE)
679 tf->device = scc_ide_inb(io_ports->device_addr);
680}
681
682static void scc_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
683 void *buf, unsigned int len)
684{
685 unsigned long data_addr = drive->hwif->io_ports.data_addr;
686
687 len++;
688
689 if (drive->io_32bit) {
690 scc_ide_insl(data_addr, buf, len / 4);
691
692 if ((len & 3) >= 2)
693 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
694 } else
695 scc_ide_insw(data_addr, buf, len / 2);
696}
697
698static void scc_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
699 void *buf, unsigned int len)
700{
701 unsigned long data_addr = drive->hwif->io_ports.data_addr;
702
703 len++;
704
705 if (drive->io_32bit) {
706 scc_ide_outsl(data_addr, buf, len / 4);
707
708 if ((len & 3) >= 2)
709 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
710 } else
711 scc_ide_outsw(data_addr, buf, len / 2);
712}
713
714/**
715 * init_mmio_iops_scc - set up the iops for MMIO
716 * @hwif: interface to set up
717 *
718 */
719
720static void init_mmio_iops_scc(ide_hwif_t *hwif)
721{
722 struct pci_dev *dev = to_pci_dev(hwif->dev);
723 struct scc_ports *ports = pci_get_drvdata(dev);
724 unsigned long dma_base = ports->dma;
725
726 ide_set_hwifdata(hwif, ports);
727
728 hwif->dma_base = dma_base;
729 hwif->config_data = ports->ctl;
730}
731
732/**
733 * init_iops_scc - set up iops
734 * @hwif: interface to set up
735 *
736 * Do the basic setup for the SCC hardware interface
737 * and then do the MMIO setup.
738 */
739
740static void init_iops_scc(ide_hwif_t *hwif)
741{
742 struct pci_dev *dev = to_pci_dev(hwif->dev);
743
744 hwif->hwif_data = NULL;
745 if (pci_get_drvdata(dev) == NULL)
746 return;
747 init_mmio_iops_scc(hwif);
748}
749
750static int scc_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
751{
752 return ide_allocate_dma_engine(hwif);
753}
754
755static u8 scc_cable_detect(ide_hwif_t *hwif)
756{
757 return ATA_CBL_PATA80;
758}
759
760/**
761 * init_hwif_scc - set up hwif
762 * @hwif: interface to set up
763 *
764 * We do the basic set up of the interface structure. The SCC
765 * requires several custom handlers so we override the default
766 * ide DMA handlers appropriately.
767 */
768
769static void init_hwif_scc(ide_hwif_t *hwif)
770{
771 /* PTERADD */
772 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
773
774 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
775 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
776 else
777 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
778}
779
780static const struct ide_tp_ops scc_tp_ops = {
781 .exec_command = scc_exec_command,
782 .read_status = scc_read_status,
783 .read_altstatus = scc_read_altstatus,
784 .write_devctl = scc_write_devctl,
785
786 .dev_select = ide_dev_select,
787 .tf_load = scc_tf_load,
788 .tf_read = scc_tf_read,
789
790 .input_data = scc_input_data,
791 .output_data = scc_output_data,
792};
793
794static const struct ide_port_ops scc_port_ops = {
795 .set_pio_mode = scc_set_pio_mode,
796 .set_dma_mode = scc_set_dma_mode,
797 .udma_filter = scc_udma_filter,
798 .cable_detect = scc_cable_detect,
799};
800
801static const struct ide_dma_ops scc_dma_ops = {
802 .dma_host_set = scc_dma_host_set,
803 .dma_setup = scc_dma_setup,
804 .dma_start = scc_dma_start,
805 .dma_end = scc_dma_end,
806 .dma_test_irq = scc_dma_test_irq,
807 .dma_lost_irq = ide_dma_lost_irq,
808 .dma_timer_expiry = ide_dma_sff_timer_expiry,
809 .dma_sff_read_status = scc_dma_sff_read_status,
810};
811
812static const struct ide_port_info scc_chipset = {
813 .name = "sccIDE",
814 .init_iops = init_iops_scc,
815 .init_dma = scc_init_dma,
816 .init_hwif = init_hwif_scc,
817 .tp_ops = &scc_tp_ops,
818 .port_ops = &scc_port_ops,
819 .dma_ops = &scc_dma_ops,
820 .host_flags = IDE_HFLAG_SINGLE,
821 .irq_flags = IRQF_SHARED,
822 .pio_mask = ATA_PIO4,
823 .chipset = ide_pci,
824};
825
826/**
827 * scc_init_one - pci layer discovery entry
828 * @dev: PCI device
829 * @id: ident table entry
830 *
831 * Called by the PCI code when it finds an SCC PATA controller.
832 * We then use the IDE PCI generic helper to do most of the work.
833 */
834
835static int scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
836{
837 return init_setup_scc(dev, &scc_chipset);
838}
839
840/**
841 * scc_remove - pci layer remove entry
842 * @dev: PCI device
843 *
844 * Called by the PCI code when it removes an SCC PATA controller.
845 */
846
847static void scc_remove(struct pci_dev *dev)
848{
849 struct scc_ports *ports = pci_get_drvdata(dev);
850 struct ide_host *host = ports->host;
851
852 ide_host_remove(host);
853
854 iounmap((void*)ports->dma);
855 iounmap((void*)ports->ctl);
856 pci_release_selected_regions(dev, (1 << 2) - 1);
857 memset(ports, 0, sizeof(*ports));
858}
859
860static const struct pci_device_id scc_pci_tbl[] = {
861 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
862 { 0, },
863};
864MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
865
866static struct pci_driver scc_pci_driver = {
867 .name = "SCC IDE",
868 .id_table = scc_pci_tbl,
869 .probe = scc_init_one,
870 .remove = scc_remove,
871};
872
873static int __init scc_ide_init(void)
874{
875 return ide_pci_register_driver(&scc_pci_driver);
876}
877
878static void __exit scc_ide_exit(void)
879{
880 pci_unregister_driver(&scc_pci_driver);
881}
882
883module_init(scc_ide_init);
884module_exit(scc_ide_exit);
885
886MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
887MODULE_LICENSE("GPL");
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 8dad4a307bb8..28aeae46f355 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -205,6 +205,7 @@ enum {
205 ATA_LFLAG_SW_ACTIVITY = (1 << 7), /* keep activity stats */ 205 ATA_LFLAG_SW_ACTIVITY = (1 << 7), /* keep activity stats */
206 ATA_LFLAG_NO_LPM = (1 << 8), /* disable LPM on this link */ 206 ATA_LFLAG_NO_LPM = (1 << 8), /* disable LPM on this link */
207 ATA_LFLAG_RST_ONCE = (1 << 9), /* limit recovery to one reset */ 207 ATA_LFLAG_RST_ONCE = (1 << 9), /* limit recovery to one reset */
208 ATA_LFLAG_CHANGED = (1 << 10), /* LPM state changed on this link */
208 209
209 /* struct ata_port flags */ 210 /* struct ata_port flags */
210 ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */ 211 ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */
@@ -309,6 +310,12 @@ enum {
309 */ 310 */
310 ATA_TMOUT_PMP_SRST_WAIT = 5000, 311 ATA_TMOUT_PMP_SRST_WAIT = 5000,
311 312
313 /* When the LPM policy is set to ATA_LPM_MAX_POWER, there might
314 * be a spurious PHY event, so ignore the first PHY event that
315 * occurs within 10s after the policy change.
316 */
317 ATA_TMOUT_SPURIOUS_PHY = 10000,
318
312 /* ATA bus states */ 319 /* ATA bus states */
313 BUS_UNKNOWN = 0, 320 BUS_UNKNOWN = 0,
314 BUS_DMA = 1, 321 BUS_DMA = 1,
@@ -788,6 +795,8 @@ struct ata_link {
788 struct ata_eh_context eh_context; 795 struct ata_eh_context eh_context;
789 796
790 struct ata_device device[ATA_MAX_DEVICES]; 797 struct ata_device device[ATA_MAX_DEVICES];
798
799 unsigned long last_lpm_change; /* when last LPM change happened */
791}; 800};
792#define ATA_LINK_CLEAR_BEGIN offsetof(struct ata_link, active_tag) 801#define ATA_LINK_CLEAR_BEGIN offsetof(struct ata_link, active_tag)
793#define ATA_LINK_CLEAR_END offsetof(struct ata_link, device[0]) 802#define ATA_LINK_CLEAR_END offsetof(struct ata_link, device[0])
@@ -1201,6 +1210,7 @@ extern struct ata_device *ata_dev_pair(struct ata_device *adev);
1201extern int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev); 1210extern int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev);
1202extern void ata_scsi_port_error_handler(struct Scsi_Host *host, struct ata_port *ap); 1211extern void ata_scsi_port_error_handler(struct Scsi_Host *host, struct ata_port *ap);
1203extern void ata_scsi_cmd_error_handler(struct Scsi_Host *host, struct ata_port *ap, struct list_head *eh_q); 1212extern void ata_scsi_cmd_error_handler(struct Scsi_Host *host, struct ata_port *ap, struct list_head *eh_q);
1213extern bool sata_lpm_ignore_phy_events(struct ata_link *link);
1204 1214
1205extern int ata_cable_40wire(struct ata_port *ap); 1215extern int ata_cable_40wire(struct ata_port *ap);
1206extern int ata_cable_80wire(struct ata_port *ap); 1216extern int ata_cable_80wire(struct ata_port *ap);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 03:52:55 -0400