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authorRex Zhu <Rex.Zhu@amd.com>2017-09-26 13:28:27 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 15:14:27 -0400
commitb3b030520df05fca7f2dcca455c9628f483a1f95 (patch)
treec68214a9e91982075f41862dc8b588ef13c79bb0
parent221c89f980ea96a6baf80b17b6c6a618fc366e73 (diff)
drm/amd/powerplay: refine powerplay code.
delete struct smumgr, put smu backend function table in struct hwmgr Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c62
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c19
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hwmgr.h40
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/pp_instance.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smumgr.h62
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c58
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c38
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c54
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c10
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c50
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c67
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c10
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c20
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c22
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c148
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c64
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c22
22 files changed, 339 insertions, 425 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index c37ea9543ca3..9f3f3b8cf64f 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -35,13 +35,13 @@ static inline int pp_check(struct pp_instance *handle)
35 if (handle == NULL || handle->pp_valid != PP_VALID) 35 if (handle == NULL || handle->pp_valid != PP_VALID)
36 return -EINVAL; 36 return -EINVAL;
37 37
38 if (handle->smu_mgr == NULL || handle->smu_mgr->smumgr_funcs == NULL) 38 if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
39 return -EINVAL; 39 return -EINVAL;
40 40
41 if (handle->pm_en == 0) 41 if (handle->pm_en == 0)
42 return PP_DPM_DISABLED; 42 return PP_DPM_DISABLED;
43 43
44 if (handle->hwmgr == NULL || handle->hwmgr->hwmgr_func == NULL) 44 if (handle->hwmgr->hwmgr_func == NULL)
45 return PP_DPM_DISABLED; 45 return PP_DPM_DISABLED;
46 46
47 return 0; 47 return 0;
@@ -52,38 +52,32 @@ static int pp_early_init(void *handle)
52 int ret; 52 int ret;
53 struct pp_instance *pp_handle = (struct pp_instance *)handle; 53 struct pp_instance *pp_handle = (struct pp_instance *)handle;
54 54
55 ret = smum_early_init(pp_handle); 55 ret = hwmgr_early_init(pp_handle);
56 if (ret) 56 if (ret)
57 return ret; 57 return -EINVAL;
58 58
59 if ((pp_handle->pm_en == 0) 59 if ((pp_handle->pm_en == 0)
60 || cgs_is_virtualization_enabled(pp_handle->device)) 60 || cgs_is_virtualization_enabled(pp_handle->device))
61 return PP_DPM_DISABLED; 61 return PP_DPM_DISABLED;
62 62
63 ret = hwmgr_early_init(pp_handle);
64 if (ret) {
65 pp_handle->pm_en = 0;
66 return PP_DPM_DISABLED;
67 }
68
69 return 0; 63 return 0;
70} 64}
71 65
72static int pp_sw_init(void *handle) 66static int pp_sw_init(void *handle)
73{ 67{
74 struct pp_smumgr *smumgr; 68 struct pp_hwmgr *hwmgr;
75 int ret = 0; 69 int ret = 0;
76 struct pp_instance *pp_handle = (struct pp_instance *)handle; 70 struct pp_instance *pp_handle = (struct pp_instance *)handle;
77 71
78 ret = pp_check(pp_handle); 72 ret = pp_check(pp_handle);
79 73
80 if (ret == 0 || ret == PP_DPM_DISABLED) { 74 if (ret == 0 || ret == PP_DPM_DISABLED) {
81 smumgr = pp_handle->smu_mgr; 75 hwmgr = pp_handle->hwmgr;
82 76
83 if (smumgr->smumgr_funcs->smu_init == NULL) 77 if (hwmgr->smumgr_funcs->smu_init == NULL)
84 return -EINVAL; 78 return -EINVAL;
85 79
86 ret = smumgr->smumgr_funcs->smu_init(pp_handle->hwmgr); 80 ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
87 81
88 pr_info("amdgpu: powerplay sw initialized\n"); 82 pr_info("amdgpu: powerplay sw initialized\n");
89 } 83 }
@@ -92,39 +86,39 @@ static int pp_sw_init(void *handle)
92 86
93static int pp_sw_fini(void *handle) 87static int pp_sw_fini(void *handle)
94{ 88{
95 struct pp_smumgr *smumgr; 89 struct pp_hwmgr *hwmgr;
96 int ret = 0; 90 int ret = 0;
97 struct pp_instance *pp_handle = (struct pp_instance *)handle; 91 struct pp_instance *pp_handle = (struct pp_instance *)handle;
98 92
99 ret = pp_check(pp_handle); 93 ret = pp_check(pp_handle);
100 if (ret == 0 || ret == PP_DPM_DISABLED) { 94 if (ret == 0 || ret == PP_DPM_DISABLED) {
101 smumgr = pp_handle->smu_mgr; 95 hwmgr = pp_handle->hwmgr;
102 96
103 if (smumgr->smumgr_funcs->smu_fini == NULL) 97 if (hwmgr->smumgr_funcs->smu_fini == NULL)
104 return -EINVAL; 98 return -EINVAL;
105 99
106 ret = smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); 100 ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
107 } 101 }
108 return ret; 102 return ret;
109} 103}
110 104
111static int pp_hw_init(void *handle) 105static int pp_hw_init(void *handle)
112{ 106{
113 struct pp_smumgr *smumgr;
114 int ret = 0; 107 int ret = 0;
115 struct pp_instance *pp_handle = (struct pp_instance *)handle; 108 struct pp_instance *pp_handle = (struct pp_instance *)handle;
109 struct pp_hwmgr *hwmgr;
116 110
117 ret = pp_check(pp_handle); 111 ret = pp_check(pp_handle);
118 112
119 if (ret == 0 || ret == PP_DPM_DISABLED) { 113 if (ret == 0 || ret == PP_DPM_DISABLED) {
120 smumgr = pp_handle->smu_mgr; 114 hwmgr = pp_handle->hwmgr;
121 115
122 if (smumgr->smumgr_funcs->start_smu == NULL) 116 if (hwmgr->smumgr_funcs->start_smu == NULL)
123 return -EINVAL; 117 return -EINVAL;
124 118
125 if(smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) { 119 if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
126 pr_err("smc start failed\n"); 120 pr_err("smc start failed\n");
127 smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); 121 hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
128 return -EINVAL;; 122 return -EINVAL;;
129 } 123 }
130 if (ret == PP_DPM_DISABLED) 124 if (ret == PP_DPM_DISABLED)
@@ -137,8 +131,6 @@ static int pp_hw_init(void *handle)
137 return 0; 131 return 0;
138err: 132err:
139 pp_handle->pm_en = 0; 133 pp_handle->pm_en = 0;
140 kfree(pp_handle->hwmgr);
141 pp_handle->hwmgr = NULL;
142 return PP_DPM_DISABLED; 134 return PP_DPM_DISABLED;
143} 135}
144 136
@@ -232,7 +224,7 @@ static int pp_suspend(void *handle)
232 224
233static int pp_resume(void *handle) 225static int pp_resume(void *handle)
234{ 226{
235 struct pp_smumgr *smumgr; 227 struct pp_hwmgr *hwmgr;
236 int ret, ret1; 228 int ret, ret1;
237 struct pp_instance *pp_handle = (struct pp_instance *)handle; 229 struct pp_instance *pp_handle = (struct pp_instance *)handle;
238 230
@@ -241,15 +233,15 @@ static int pp_resume(void *handle)
241 if (ret1 != 0 && ret1 != PP_DPM_DISABLED) 233 if (ret1 != 0 && ret1 != PP_DPM_DISABLED)
242 return ret1; 234 return ret1;
243 235
244 smumgr = pp_handle->smu_mgr; 236 hwmgr = pp_handle->hwmgr;
245 237
246 if (smumgr->smumgr_funcs->start_smu == NULL) 238 if (hwmgr->smumgr_funcs->start_smu == NULL)
247 return -EINVAL; 239 return -EINVAL;
248 240
249 ret = smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr); 241 ret = hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr);
250 if (ret) { 242 if (ret) {
251 pr_err("smc start failed\n"); 243 pr_err("smc start failed\n");
252 smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr); 244 hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
253 return ret; 245 return ret;
254 } 246 }
255 247
@@ -1157,13 +1149,9 @@ int amd_powerplay_destroy(void *handle)
1157{ 1149{
1158 struct pp_instance *instance = (struct pp_instance *)handle; 1150 struct pp_instance *instance = (struct pp_instance *)handle;
1159 1151
1160 if (instance->pm_en) { 1152 kfree(instance->hwmgr);
1161 kfree(instance->hwmgr); 1153 instance->hwmgr = NULL;
1162 instance->hwmgr = NULL;
1163 }
1164 1154
1165 kfree(instance->smu_mgr);
1166 instance->smu_mgr = NULL;
1167 kfree(instance); 1155 kfree(instance);
1168 instance = NULL; 1156 instance = NULL;
1169 return 0; 1157 return 0;
@@ -1174,7 +1162,7 @@ int amd_powerplay_reset(void *handle)
1174 struct pp_instance *instance = (struct pp_instance *)handle; 1162 struct pp_instance *instance = (struct pp_instance *)handle;
1175 int ret; 1163 int ret;
1176 1164
1177 if (cgs_is_virtualization_enabled(instance->smu_mgr->device)) 1165 if (cgs_is_virtualization_enabled(instance->hwmgr->device))
1178 return PP_DPM_DISABLED; 1166 return PP_DPM_DISABLED;
1179 1167
1180 ret = pp_check(instance); 1168 ret = pp_check(instance);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 16101c392c3b..9c1479dcf79c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -37,6 +37,15 @@
37#include "amd_acpi.h" 37#include "amd_acpi.h"
38#include "pp_psm.h" 38#include "pp_psm.h"
39 39
40extern const struct pp_smumgr_func ci_smu_funcs;
41extern const struct pp_smumgr_func cz_smu_funcs;
42extern const struct pp_smumgr_func iceland_smu_funcs;
43extern const struct pp_smumgr_func tonga_smu_funcs;
44extern const struct pp_smumgr_func fiji_smu_funcs;
45extern const struct pp_smumgr_func polaris10_smu_funcs;
46extern const struct pp_smumgr_func vega10_smu_funcs;
47extern const struct pp_smumgr_func rv_smu_funcs;
48
40extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr); 49extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);
41static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr); 50static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
42static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr); 51static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
@@ -132,7 +141,6 @@ int hwmgr_early_init(struct pp_instance *handle)
132 return -ENOMEM; 141 return -ENOMEM;
133 142
134 handle->hwmgr = hwmgr; 143 handle->hwmgr = hwmgr;
135 hwmgr->smumgr = handle->smu_mgr;
136 hwmgr->device = handle->device; 144 hwmgr->device = handle->device;
137 hwmgr->chip_family = handle->chip_family; 145 hwmgr->chip_family = handle->chip_family;
138 hwmgr->chip_id = handle->chip_id; 146 hwmgr->chip_id = handle->chip_id;
@@ -144,9 +152,11 @@ int hwmgr_early_init(struct pp_instance *handle)
144 hwmgr_init_default_caps(hwmgr); 152 hwmgr_init_default_caps(hwmgr);
145 hwmgr_set_user_specify_caps(hwmgr); 153 hwmgr_set_user_specify_caps(hwmgr);
146 hwmgr->fan_ctrl_is_in_default_mode = true; 154 hwmgr->fan_ctrl_is_in_default_mode = true;
155 hwmgr->reload_fw = 1;
147 156
148 switch (hwmgr->chip_family) { 157 switch (hwmgr->chip_family) {
149 case AMDGPU_FAMILY_CI: 158 case AMDGPU_FAMILY_CI:
159 hwmgr->smumgr_funcs = &ci_smu_funcs;
150 ci_set_asic_special_caps(hwmgr); 160 ci_set_asic_special_caps(hwmgr);
151 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | 161 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
152 PP_ENABLE_GFX_CG_THRU_SMU); 162 PP_ENABLE_GFX_CG_THRU_SMU);
@@ -154,21 +164,25 @@ int hwmgr_early_init(struct pp_instance *handle)
154 smu7_init_function_pointers(hwmgr); 164 smu7_init_function_pointers(hwmgr);
155 break; 165 break;
156 case AMDGPU_FAMILY_CZ: 166 case AMDGPU_FAMILY_CZ:
167 hwmgr->smumgr_funcs = &cz_smu_funcs;
157 cz_init_function_pointers(hwmgr); 168 cz_init_function_pointers(hwmgr);
158 break; 169 break;
159 case AMDGPU_FAMILY_VI: 170 case AMDGPU_FAMILY_VI:
160 switch (hwmgr->chip_id) { 171 switch (hwmgr->chip_id) {
161 case CHIP_TOPAZ: 172 case CHIP_TOPAZ:
173 hwmgr->smumgr_funcs = &iceland_smu_funcs;
162 topaz_set_asic_special_caps(hwmgr); 174 topaz_set_asic_special_caps(hwmgr);
163 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | 175 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
164 PP_ENABLE_GFX_CG_THRU_SMU); 176 PP_ENABLE_GFX_CG_THRU_SMU);
165 hwmgr->pp_table_version = PP_TABLE_V0; 177 hwmgr->pp_table_version = PP_TABLE_V0;
166 break; 178 break;
167 case CHIP_TONGA: 179 case CHIP_TONGA:
180 hwmgr->smumgr_funcs = &tonga_smu_funcs;
168 tonga_set_asic_special_caps(hwmgr); 181 tonga_set_asic_special_caps(hwmgr);
169 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; 182 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
170 break; 183 break;
171 case CHIP_FIJI: 184 case CHIP_FIJI:
185 hwmgr->smumgr_funcs = &fiji_smu_funcs;
172 fiji_set_asic_special_caps(hwmgr); 186 fiji_set_asic_special_caps(hwmgr);
173 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | 187 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
174 PP_ENABLE_GFX_CG_THRU_SMU); 188 PP_ENABLE_GFX_CG_THRU_SMU);
@@ -176,6 +190,7 @@ int hwmgr_early_init(struct pp_instance *handle)
176 case CHIP_POLARIS11: 190 case CHIP_POLARIS11:
177 case CHIP_POLARIS10: 191 case CHIP_POLARIS10:
178 case CHIP_POLARIS12: 192 case CHIP_POLARIS12:
193 hwmgr->smumgr_funcs = &polaris10_smu_funcs;
179 polaris_set_asic_special_caps(hwmgr); 194 polaris_set_asic_special_caps(hwmgr);
180 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); 195 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
181 break; 196 break;
@@ -187,6 +202,7 @@ int hwmgr_early_init(struct pp_instance *handle)
187 case AMDGPU_FAMILY_AI: 202 case AMDGPU_FAMILY_AI:
188 switch (hwmgr->chip_id) { 203 switch (hwmgr->chip_id) {
189 case CHIP_VEGA10: 204 case CHIP_VEGA10:
205 hwmgr->smumgr_funcs = &vega10_smu_funcs;
190 vega10_hwmgr_init(hwmgr); 206 vega10_hwmgr_init(hwmgr);
191 break; 207 break;
192 default: 208 default:
@@ -196,6 +212,7 @@ int hwmgr_early_init(struct pp_instance *handle)
196 case AMDGPU_FAMILY_RV: 212 case AMDGPU_FAMILY_RV:
197 switch (hwmgr->chip_id) { 213 switch (hwmgr->chip_id) {
198 case CHIP_RAVEN: 214 case CHIP_RAVEN:
215 hwmgr->smumgr_funcs = &rv_smu_funcs;
199 rv_init_function_pointers(hwmgr); 216 rv_init_function_pointers(hwmgr);
200 break; 217 break;
201 default: 218 default:
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index bc2f227559cd..8dbe9148aad3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1382,7 +1382,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1382 data->force_pcie_gen = PP_PCIEGenInvalid; 1382 data->force_pcie_gen = PP_PCIEGenInvalid;
1383 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; 1383 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1384 1384
1385 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) { 1385 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
1386 uint8_t tmp1, tmp2; 1386 uint8_t tmp1, tmp2;
1387 uint16_t tmp3 = 0; 1387 uint16_t tmp3 = 0;
1388 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2, 1388 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
@@ -4623,7 +4623,7 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
4623 4623
4624static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) 4624static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
4625{ 4625{
4626 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 4626 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
4627 4627
4628 if (smu_data == NULL) 4628 if (smu_data == NULL)
4629 return -EINVAL; 4629 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index a20d67a78b70..85ca16abb626 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -763,7 +763,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
763 } else if (hwmgr->chip_id == CHIP_POLARIS11) { 763 } else if (hwmgr->chip_id == CHIP_POLARIS11) {
764 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11); 764 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
765 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result); 765 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
766 if (hwmgr->smumgr->is_kicker) 766 if (hwmgr->is_kicker)
767 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker); 767 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
768 else 768 else
769 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11); 769 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 1b212b57edc0..859cca496b44 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -235,6 +235,39 @@ struct phm_vce_clock_voltage_dependency_table {
235 struct phm_vce_clock_voltage_dependency_record entries[1]; 235 struct phm_vce_clock_voltage_dependency_record entries[1];
236}; 236};
237 237
238struct pp_smumgr_func {
239 int (*smu_init)(struct pp_hwmgr *hwmgr);
240 int (*smu_fini)(struct pp_hwmgr *hwmgr);
241 int (*start_smu)(struct pp_hwmgr *hwmgr);
242 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
243 uint32_t firmware);
244 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
245 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
246 uint32_t firmware);
247 int (*get_argument)(struct pp_hwmgr *hwmgr);
248 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
249 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
250 uint16_t msg, uint32_t parameter);
251 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
252 void **table);
253 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
254 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
255 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
256 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
257 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
258 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
259 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
260 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
261 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
262 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
263 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
264 uint32_t (*get_mac_definition)(uint32_t value);
265 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
266 int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
267 struct amd_pp_profile *request);
268 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
269};
270
238struct pp_hwmgr_func { 271struct pp_hwmgr_func {
239 int (*backend_init)(struct pp_hwmgr *hw_mgr); 272 int (*backend_init)(struct pp_hwmgr *hw_mgr);
240 int (*backend_fini)(struct pp_hwmgr *hw_mgr); 273 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
@@ -706,10 +739,17 @@ struct pp_hwmgr {
706 void *pptable; 739 void *pptable;
707 struct phm_platform_descriptor platform_descriptor; 740 struct phm_platform_descriptor platform_descriptor;
708 void *backend; 741 void *backend;
742
743 void *smu_backend;
744 const struct pp_smumgr_func *smumgr_funcs;
745 bool is_kicker;
746 bool reload_fw;
747
709 enum PP_DAL_POWERLEVEL dal_power_level; 748 enum PP_DAL_POWERLEVEL dal_power_level;
710 struct phm_dynamic_state_info dyn_state; 749 struct phm_dynamic_state_info dyn_state;
711 const struct pp_hwmgr_func *hwmgr_func; 750 const struct pp_hwmgr_func *hwmgr_func;
712 const struct pp_table_func *pptable_func; 751 const struct pp_table_func *pptable_func;
752
713 struct pp_power_state *ps; 753 struct pp_power_state *ps;
714 enum pp_power_source power_source; 754 enum pp_power_source power_source;
715 uint32_t num_ps; 755 uint32_t num_ps;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
index 5bf2ee449e42..25fb1460a194 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
@@ -23,7 +23,6 @@
23#ifndef _PP_INSTANCE_H_ 23#ifndef _PP_INSTANCE_H_
24#define _PP_INSTANCE_H_ 24#define _PP_INSTANCE_H_
25 25
26#include "smumgr.h"
27#include "hwmgr.h" 26#include "hwmgr.h"
28 27
29#define PP_VALID 0x1F1F1F1F 28#define PP_VALID 0x1F1F1F1F
@@ -35,7 +34,6 @@ struct pp_instance {
35 bool pm_en; 34 bool pm_en;
36 uint32_t feature_mask; 35 uint32_t feature_mask;
37 void *device; 36 void *device;
38 struct pp_smumgr *smu_mgr;
39 struct pp_hwmgr *hwmgr; 37 struct pp_hwmgr *hwmgr;
40 struct mutex pp_lock; 38 struct mutex pp_lock;
41}; 39};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 58581e1bbf50..8bdffaa14b43 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -23,24 +23,13 @@
23#ifndef _SMUMGR_H_ 23#ifndef _SMUMGR_H_
24#define _SMUMGR_H_ 24#define _SMUMGR_H_
25#include <linux/types.h> 25#include <linux/types.h>
26#include "pp_instance.h"
27#include "amd_powerplay.h" 26#include "amd_powerplay.h"
28 27#include "hwmgr.h"
29struct pp_smumgr;
30struct pp_instance;
31struct pp_hwmgr;
32 28
33#define smu_lower_32_bits(n) ((uint32_t)(n)) 29#define smu_lower_32_bits(n) ((uint32_t)(n))
34#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16)) 30#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
35 31
36extern const struct pp_smumgr_func ci_smu_funcs; 32
37extern const struct pp_smumgr_func cz_smu_funcs;
38extern const struct pp_smumgr_func iceland_smu_funcs;
39extern const struct pp_smumgr_func tonga_smu_funcs;
40extern const struct pp_smumgr_func fiji_smu_funcs;
41extern const struct pp_smumgr_func polaris10_smu_funcs;
42extern const struct pp_smumgr_func vega10_smu_funcs;
43extern const struct pp_smumgr_func rv_smu_funcs;
44 33
45enum AVFS_BTC_STATUS { 34enum AVFS_BTC_STATUS {
46 AVFS_BTC_BOOT = 0, 35 AVFS_BTC_BOOT = 0,
@@ -101,53 +90,6 @@ enum SMU_MAC_DEFINITION {
101 SMU_UVD_MCLK_HANDSHAKE_DISABLE, 90 SMU_UVD_MCLK_HANDSHAKE_DISABLE,
102}; 91};
103 92
104
105struct pp_smumgr_func {
106 int (*smu_init)(struct pp_hwmgr *hwmgr);
107 int (*smu_fini)(struct pp_hwmgr *hwmgr);
108 int (*start_smu)(struct pp_hwmgr *hwmgr);
109 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
110 uint32_t firmware);
111 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
112 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
113 uint32_t firmware);
114 int (*get_argument)(struct pp_hwmgr *hwmgr);
115 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
116 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
117 uint16_t msg, uint32_t parameter);
118 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
119 void **table);
120 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
121 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
122 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
123 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
124 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
125 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
126 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
127 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
128 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
129 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
130 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
131 uint32_t (*get_mac_definition)(uint32_t value);
132 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
133 int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
134 struct amd_pp_profile *request);
135 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
136};
137
138struct pp_smumgr {
139 uint32_t chip_family;
140 uint32_t chip_id;
141 void *device;
142 void *backend;
143 uint32_t usec_timeout;
144 bool reload_fw;
145 const struct pp_smumgr_func *smumgr_funcs;
146 bool is_kicker;
147};
148
149extern int smum_early_init(struct pp_instance *handle);
150
151extern int smum_get_argument(struct pp_hwmgr *hwmgr); 93extern int smum_get_argument(struct pp_hwmgr *hwmgr);
152 94
153extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table); 95extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index 2710a6fa3df0..c2fc237a136a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -236,7 +236,7 @@ int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
236 236
237static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 237static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
238{ 238{
239 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 239 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
240 struct cgs_system_info sys_info = {0}; 240 struct cgs_system_info sys_info = {0};
241 uint32_t dev_id; 241 uint32_t dev_id;
242 242
@@ -479,7 +479,7 @@ static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
479int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 479int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
480{ 480{
481 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 481 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
482 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 482 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
483 struct smu7_dpm_table *dpm_table = &data->dpm_table; 483 struct smu7_dpm_table *dpm_table = &data->dpm_table;
484 int result = 0; 484 int result = 0;
485 uint32_t array = smu_data->dpm_table_start + 485 uint32_t array = smu_data->dpm_table_start +
@@ -520,7 +520,7 @@ int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
520 520
521static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr) 521static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr)
522{ 522{
523 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 523 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
524 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; 524 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
525 525
526 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; 526 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
@@ -534,7 +534,7 @@ static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr)
534static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr) 534static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr)
535{ 535{
536 uint16_t tdc_limit; 536 uint16_t tdc_limit;
537 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 537 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
538 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; 538 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
539 539
540 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); 540 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
@@ -549,7 +549,7 @@ static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr)
549 549
550static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 550static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
551{ 551{
552 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 552 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
553 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; 553 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
554 uint32_t temp; 554 uint32_t temp;
555 555
@@ -568,8 +568,8 @@ static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
568 568
569static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 569static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
570{ 570{
571 uint16_t tmp = 0; 571 uint16_t tmp;
572 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 572 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
573 573
574 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) 574 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
575 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) 575 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
@@ -585,7 +585,7 @@ static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_off
585static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) 585static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
586{ 586{
587 int i; 587 int i;
588 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 588 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
589 uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; 589 uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
590 uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; 590 uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
591 uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2; 591 uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2;
@@ -614,7 +614,7 @@ static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
614static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr) 614static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr)
615{ 615{
616 int i; 616 int i;
617 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 617 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
618 uint8_t *vid = smu_data->power_tune_table.VddCVid; 618 uint8_t *vid = smu_data->power_tune_table.VddCVid;
619 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 619 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
620 620
@@ -630,7 +630,7 @@ static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr)
630 630
631static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr) 631static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
632{ 632{
633 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 633 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
634 u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; 634 u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
635 u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; 635 u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
636 int i, min, max; 636 int i, min, max;
@@ -662,7 +662,7 @@ static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
662 662
663static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) 663static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
664{ 664{
665 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 665 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
666 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; 666 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
667 uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; 667 uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
668 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; 668 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
@@ -680,7 +680,7 @@ static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
680 680
681static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr) 681static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
682{ 682{
683 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 683 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
684 uint32_t pm_fuse_table_offset; 684 uint32_t pm_fuse_table_offset;
685 int ret = 0; 685 int ret = 0;
686 686
@@ -722,7 +722,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
722 722
723static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) 723static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
724{ 724{
725 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 725 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
726 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 726 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
727 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults; 727 const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
728 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); 728 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
@@ -997,7 +997,7 @@ static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmT
997{ 997{
998 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 998 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
999 struct smu7_dpm_table *dpm_table = &data->dpm_table; 999 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1000 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1000 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1001 uint32_t i; 1001 uint32_t i;
1002 1002
1003/* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/ 1003/* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/
@@ -1300,7 +1300,7 @@ static int ci_populate_single_memory_level(
1300int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1300int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1301{ 1301{
1302 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1302 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1303 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1303 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1304 struct smu7_dpm_table *dpm_table = &data->dpm_table; 1304 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1305 int result; 1305 int result;
1306 struct cgs_system_info sys_info = {0}; 1306 struct cgs_system_info sys_info = {0};
@@ -1684,7 +1684,7 @@ static int ci_populate_memory_timing_parameters(
1684static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) 1684static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1685{ 1685{
1686 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1686 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1687 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1687 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1688 int result = 0; 1688 int result = 0;
1689 SMU7_Discrete_MCArbDramTimingTable arb_regs; 1689 SMU7_Discrete_MCArbDramTimingTable arb_regs;
1690 uint32_t i, j; 1690 uint32_t i, j;
@@ -1721,7 +1721,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1721{ 1721{
1722 int result = 0; 1722 int result = 0;
1723 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1723 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1724 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1724 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1725 1725
1726 table->GraphicsBootLevel = 0; 1726 table->GraphicsBootLevel = 0;
1727 table->MemoryBootLevel = 0; 1727 table->MemoryBootLevel = 0;
@@ -1759,7 +1759,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1759static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr, 1759static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1760 SMU7_Discrete_MCRegisters *mc_reg_table) 1760 SMU7_Discrete_MCRegisters *mc_reg_table)
1761{ 1761{
1762 const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smumgr->backend; 1762 const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend;
1763 1763
1764 uint32_t i, j; 1764 uint32_t i, j;
1765 1765
@@ -1801,7 +1801,7 @@ static int ci_convert_mc_reg_table_entry_to_smc(
1801 SMU7_Discrete_MCRegisterSet *mc_reg_table_data 1801 SMU7_Discrete_MCRegisterSet *mc_reg_table_data
1802 ) 1802 )
1803{ 1803{
1804 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1804 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1805 uint32_t i = 0; 1805 uint32_t i = 0;
1806 1806
1807 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { 1807 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
@@ -1845,7 +1845,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1845 1845
1846static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) 1846static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1847{ 1847{
1848 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1848 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1849 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1849 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1850 uint32_t address; 1850 uint32_t address;
1851 int32_t result; 1851 int32_t result;
@@ -1872,7 +1872,7 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1872static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) 1872static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1873{ 1873{
1874 int result; 1874 int result;
1875 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1875 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1876 1876
1877 memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters)); 1877 memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));
1878 result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); 1878 result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
@@ -1890,7 +1890,7 @@ static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1890static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr) 1890static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1891{ 1891{
1892 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1892 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1893 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1893 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1894 uint8_t count, level; 1894 uint8_t count, level;
1895 1895
1896 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); 1896 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
@@ -1948,7 +1948,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
1948{ 1948{
1949 int result; 1949 int result;
1950 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1950 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1951 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 1951 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
1952 SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1952 SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1953 struct pp_atomctrl_gpio_pin_assignment gpio_pin; 1953 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1954 u32 i; 1954 u32 i;
@@ -2127,7 +2127,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
2127 2127
2128int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 2128int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2129{ 2129{
2130 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 2130 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
2131 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 2131 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2132 uint32_t duty100; 2132 uint32_t duty100;
2133 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; 2133 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
@@ -2214,7 +2214,7 @@ static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2214int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr) 2214int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2215{ 2215{
2216 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2216 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2217 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 2217 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
2218 2218
2219 int result = 0; 2219 int result = 0;
2220 uint32_t low_sclk_interrupt_threshold = 0; 2220 uint32_t low_sclk_interrupt_threshold = 0;
@@ -2311,7 +2311,7 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
2311 2311
2312 cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info); 2312 cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
2313 2313
2314 hwmgr->smumgr->is_kicker = info.is_kicker; 2314 hwmgr->is_kicker = info.is_kicker;
2315 byte_count = info.image_size; 2315 byte_count = info.image_size;
2316 src = (uint8_t *)info.kptr; 2316 src = (uint8_t *)info.kptr;
2317 start_addr = info.ucode_start_address; 2317 start_addr = info.ucode_start_address;
@@ -2358,7 +2358,7 @@ static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
2358int ci_process_firmware_header(struct pp_hwmgr *hwmgr) 2358int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
2359{ 2359{
2360 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2360 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2361 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 2361 struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
2362 2362
2363 uint32_t tmp = 0; 2363 uint32_t tmp = 0;
2364 int result; 2364 int result;
@@ -2670,7 +2670,7 @@ static int ci_set_valid_flag(struct ci_mc_reg_table *table)
2670int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) 2670int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2671{ 2671{
2672 int result; 2672 int result;
2673 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend); 2673 struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
2674 pp_atomctrl_mc_reg_table *table; 2674 pp_atomctrl_mc_reg_table *table;
2675 struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table; 2675 struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table;
2676 uint8_t module_index = ci_get_memory_modile_index(hwmgr); 2676 uint8_t module_index = ci_get_memory_modile_index(hwmgr);
@@ -2731,7 +2731,7 @@ int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
2731 struct amd_pp_profile *request) 2731 struct amd_pp_profile *request)
2732{ 2732{
2733 struct ci_smumgr *smu_data = (struct ci_smumgr *) 2733 struct ci_smumgr *smu_data = (struct ci_smumgr *)
2734 (hwmgr->smumgr->backend); 2734 (hwmgr->smu_backend);
2735 struct SMU7_Discrete_GraphicsLevel *levels = 2735 struct SMU7_Discrete_GraphicsLevel *levels =
2736 smu_data->smc_state_table.GraphicsLevel; 2736 smu_data->smc_state_table.GraphicsLevel;
2737 uint32_t array = smu_data->dpm_table_start + 2737 uint32_t array = smu_data->dpm_table_start +
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index d2e24e3a963d..f265f42a7ed3 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -43,15 +43,15 @@ static int ci_smu_init(struct pp_hwmgr *hwmgr)
43 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) 43 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
44 ci_priv->activity_target[i] = 30; 44 ci_priv->activity_target[i] = 30;
45 45
46 hwmgr->smumgr->backend = ci_priv; 46 hwmgr->smu_backend = ci_priv;
47 47
48 return 0; 48 return 0;
49} 49}
50 50
51static int ci_smu_fini(struct pp_hwmgr *hwmgr) 51static int ci_smu_fini(struct pp_hwmgr *hwmgr)
52{ 52{
53 kfree(hwmgr->smumgr->backend); 53 kfree(hwmgr->smu_backend);
54 hwmgr->smumgr->backend = NULL; 54 hwmgr->smu_backend = NULL;
55 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU); 55 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
56 return 0; 56 return 0;
57} 57}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index a6fa0e86a8fd..8aee9c817ff9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -181,7 +181,7 @@ static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
181 if (hwmgr == NULL || hwmgr->device == NULL) 181 if (hwmgr == NULL || hwmgr->device == NULL)
182 return -EINVAL; 182 return -EINVAL;
183 183
184 cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 184 cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
185 ret = cgs_get_firmware_info(hwmgr->device, 185 ret = cgs_get_firmware_info(hwmgr->device,
186 CGS_UCODE_ID_CP_MEC, &info); 186 CGS_UCODE_ID_CP_MEC, &info);
187 187
@@ -330,7 +330,7 @@ static int cz_smu_populate_single_scratch_task(
330 uint8_t type, bool is_last) 330 uint8_t type, bool is_last)
331{ 331{
332 uint8_t i; 332 uint8_t i;
333 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 333 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
334 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 334 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
335 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; 335 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
336 336
@@ -367,7 +367,7 @@ static int cz_smu_populate_single_ucode_load_task(
367 bool is_last) 367 bool is_last)
368{ 368{
369 uint8_t i; 369 uint8_t i;
370 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 370 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
371 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 371 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
372 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++]; 372 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
373 373
@@ -393,7 +393,7 @@ static int cz_smu_populate_single_ucode_load_task(
393 393
394static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr) 394static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
395{ 395{
396 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 396 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
397 397
398 cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count; 398 cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
399 cz_smu_populate_single_scratch_task(hwmgr, 399 cz_smu_populate_single_scratch_task(hwmgr,
@@ -406,7 +406,7 @@ static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
406static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr) 406static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
407{ 407{
408 int i; 408 int i;
409 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 409 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
410 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 410 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
411 411
412 for (i = 0; i < NUM_JOBLIST_ENTRIES; i++) 412 for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
@@ -417,7 +417,7 @@ static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
417 417
418static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr) 418static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
419{ 419{
420 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 420 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
421 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 421 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
422 422
423 toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count; 423 toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
@@ -435,7 +435,7 @@ static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
435 435
436static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr) 436static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
437{ 437{
438 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 438 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
439 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr; 439 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
440 440
441 toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count; 441 toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
@@ -477,7 +477,7 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
477 477
478static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr) 478static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
479{ 479{
480 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 480 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
481 481
482 cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count; 482 cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
483 483
@@ -489,7 +489,7 @@ static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
489 489
490static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr) 490static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
491{ 491{
492 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 492 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
493 493
494 cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count; 494 cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
495 495
@@ -517,7 +517,7 @@ static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
517 517
518static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr) 518static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
519{ 519{
520 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 520 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
521 521
522 cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count; 522 cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
523 523
@@ -530,7 +530,7 @@ static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
530 530
531static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr) 531static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
532{ 532{
533 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 533 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
534 534
535 cz_smu->toc_entry_used_count = 0; 535 cz_smu->toc_entry_used_count = 0;
536 cz_smu_initialize_toc_empty_job_list(hwmgr); 536 cz_smu_initialize_toc_empty_job_list(hwmgr);
@@ -546,7 +546,7 @@ static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
546 546
547static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr) 547static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
548{ 548{
549 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 549 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
550 uint32_t firmware_type; 550 uint32_t firmware_type;
551 uint32_t i; 551 uint32_t i;
552 int ret; 552 int ret;
@@ -588,7 +588,7 @@ static int cz_smu_populate_single_scratch_entry(
588 uint32_t ulsize_byte, 588 uint32_t ulsize_byte,
589 struct cz_buffer_entry *entry) 589 struct cz_buffer_entry *entry)
590{ 590{
591 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 591 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
592 long long mc_addr = 592 long long mc_addr =
593 ((long long)(cz_smu->smu_buffer.mc_addr_high) << 32) 593 ((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)
594 | cz_smu->smu_buffer.mc_addr_low; 594 | cz_smu->smu_buffer.mc_addr_low;
@@ -611,7 +611,7 @@ static int cz_smu_populate_single_scratch_entry(
611 611
612static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table) 612static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
613{ 613{
614 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 614 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
615 unsigned long i; 615 unsigned long i;
616 616
617 for (i = 0; i < cz_smu->scratch_buffer_length; i++) { 617 for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
@@ -640,7 +640,7 @@ static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
640 640
641static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr) 641static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
642{ 642{
643 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 643 struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
644 unsigned long i; 644 unsigned long i;
645 645
646 for (i = 0; i < cz_smu->scratch_buffer_length; i++) { 646 for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
@@ -667,10 +667,10 @@ static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
667 667
668static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr) 668static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
669{ 669{
670 struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smumgr->backend); 670 struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smu_backend);
671 uint32_t smc_address; 671 uint32_t smc_address;
672 672
673 if (!hwmgr->smumgr->reload_fw) { 673 if (!hwmgr->reload_fw) {
674 pr_info("skip reloading...\n"); 674 pr_info("skip reloading...\n");
675 return 0; 675 return 0;
676 } 676 }
@@ -745,7 +745,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
745 if (cz_smu == NULL) 745 if (cz_smu == NULL)
746 return -ENOMEM; 746 return -ENOMEM;
747 747
748 hwmgr->smumgr->backend = cz_smu; 748 hwmgr->smu_backend = cz_smu;
749 749
750 cz_smu->toc_buffer.data_size = 4096; 750 cz_smu->toc_buffer.data_size = 4096;
751 cz_smu->smu_buffer.data_size = 751 cz_smu->smu_buffer.data_size =
@@ -830,7 +830,7 @@ static int cz_smu_fini(struct pp_hwmgr *hwmgr)
830 if (hwmgr == NULL || hwmgr->device == NULL) 830 if (hwmgr == NULL || hwmgr->device == NULL)
831 return -EINVAL; 831 return -EINVAL;
832 832
833 cz_smu = (struct cz_smumgr *)hwmgr->smumgr->backend; 833 cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
834 if (cz_smu) { 834 if (cz_smu) {
835 cgs_free_gpu_mem(hwmgr->device, 835 cgs_free_gpu_mem(hwmgr->device,
836 cz_smu->toc_buffer.handle); 836 cz_smu->toc_buffer.handle);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index 843ed7a665f6..b1a66b5ada4a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -198,7 +198,7 @@ static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda)
198 198
199static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 199static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
200{ 200{
201 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 201 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
202 struct phm_ppt_v1_information *table_info = 202 struct phm_ppt_v1_information *table_info =
203 (struct phm_ppt_v1_information *)(hwmgr->pptable); 203 (struct phm_ppt_v1_information *)(hwmgr->pptable);
204 204
@@ -216,7 +216,7 @@ static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
216static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) 216static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
217{ 217{
218 218
219 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 219 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
220 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; 220 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
221 221
222 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); 222 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
@@ -299,7 +299,7 @@ static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
299 299
300static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr) 300static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
301{ 301{
302 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 302 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
303 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; 303 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
304 304
305 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; 305 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
@@ -314,7 +314,7 @@ static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
314static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr) 314static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
315{ 315{
316 uint16_t tdc_limit; 316 uint16_t tdc_limit;
317 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 317 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
318 struct phm_ppt_v1_information *table_info = 318 struct phm_ppt_v1_information *table_info =
319 (struct phm_ppt_v1_information *)(hwmgr->pptable); 319 (struct phm_ppt_v1_information *)(hwmgr->pptable);
320 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; 320 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
@@ -334,7 +334,7 @@ static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
334 334
335static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 335static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
336{ 336{
337 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 337 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
338 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults; 338 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
339 uint32_t temp; 339 uint32_t temp;
340 340
@@ -359,7 +359,7 @@ static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
359static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr) 359static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
360{ 360{
361 int i; 361 int i;
362 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 362 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
363 363
364 /* Currently not used. Set all to zero. */ 364 /* Currently not used. Set all to zero. */
365 for (i = 0; i < 16; i++) 365 for (i = 0; i < 16; i++)
@@ -370,7 +370,7 @@ static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
370 370
371static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) 371static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
372{ 372{
373 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 373 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
374 374
375 if ((hwmgr->thermal_controller.advanceFanControlParameters. 375 if ((hwmgr->thermal_controller.advanceFanControlParameters.
376 usFanOutputSensitivity & (1 << 15)) || 376 usFanOutputSensitivity & (1 << 15)) ||
@@ -389,7 +389,7 @@ static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
389static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr) 389static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
390{ 390{
391 int i; 391 int i;
392 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 392 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
393 393
394 /* Currently not used. Set all to zero. */ 394 /* Currently not used. Set all to zero. */
395 for (i = 0; i < 16; i++) 395 for (i = 0; i < 16; i++)
@@ -400,7 +400,7 @@ static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
400 400
401static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) 401static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
402{ 402{
403 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 403 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
404 struct phm_ppt_v1_information *table_info = 404 struct phm_ppt_v1_information *table_info =
405 (struct phm_ppt_v1_information *)(hwmgr->pptable); 405 (struct phm_ppt_v1_information *)(hwmgr->pptable);
406 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; 406 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
@@ -421,7 +421,7 @@ static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
421static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr) 421static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
422{ 422{
423 uint32_t pm_fuse_table_offset; 423 uint32_t pm_fuse_table_offset;
424 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 424 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
425 425
426 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 426 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
427 PHM_PlatformCaps_PowerContainment)) { 427 PHM_PlatformCaps_PowerContainment)) {
@@ -575,7 +575,7 @@ static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
575{ 575{
576 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 576 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
577 struct smu7_dpm_table *dpm_table = &data->dpm_table; 577 struct smu7_dpm_table *dpm_table = &data->dpm_table;
578 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 578 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
579 int i; 579 int i;
580 580
581 /* Index (dpm_table->pcie_speed_table.count) 581 /* Index (dpm_table->pcie_speed_table.count)
@@ -763,7 +763,7 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
763int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 763int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
764{ 764{
765 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 765 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
766 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 766 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
767 767
768 struct smu7_dpm_table *dpm_table = &data->dpm_table; 768 struct smu7_dpm_table *dpm_table = &data->dpm_table;
769 struct phm_ppt_v1_information *table_info = 769 struct phm_ppt_v1_information *table_info =
@@ -989,7 +989,7 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
989int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 989int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
990{ 990{
991 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 991 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
992 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 992 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
993 struct smu7_dpm_table *dpm_table = &data->dpm_table; 993 struct smu7_dpm_table *dpm_table = &data->dpm_table;
994 int result; 994 int result;
995 /* populate MCLK dpm table to SMU7 */ 995 /* populate MCLK dpm table to SMU7 */
@@ -1341,7 +1341,7 @@ static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1341static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) 1341static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1342{ 1342{
1343 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1343 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1344 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 1344 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1345 struct SMU73_Discrete_MCArbDramTimingTable arb_regs; 1345 struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
1346 uint32_t i, j; 1346 uint32_t i, j;
1347 int result = 0; 1347 int result = 0;
@@ -1449,7 +1449,7 @@ static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1449static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) 1449static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1450{ 1450{
1451 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1451 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1452 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 1452 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1453 struct phm_ppt_v1_information *table_info = 1453 struct phm_ppt_v1_information *table_info =
1454 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1454 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1455 uint8_t count, level; 1455 uint8_t count, level;
@@ -1480,7 +1480,7 @@ static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1480 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, 1480 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1481 volt_with_cks, value; 1481 volt_with_cks, value;
1482 uint16_t clock_freq_u16; 1482 uint16_t clock_freq_u16;
1483 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 1483 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1484 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, 1484 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1485 volt_offset = 0; 1485 volt_offset = 0;
1486 struct phm_ppt_v1_information *table_info = 1486 struct phm_ppt_v1_information *table_info =
@@ -1685,7 +1685,7 @@ static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
1685 1685
1686static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr) 1686static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
1687{ 1687{
1688 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 1688 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1689 uint32_t tmp; 1689 uint32_t tmp;
1690 int result; 1690 int result;
1691 1691
@@ -1712,7 +1712,7 @@ static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
1712 1712
1713static int fiji_save_default_power_profile(struct pp_hwmgr *hwmgr) 1713static int fiji_save_default_power_profile(struct pp_hwmgr *hwmgr)
1714{ 1714{
1715 struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 1715 struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1716 struct SMU73_Discrete_GraphicsLevel *levels = 1716 struct SMU73_Discrete_GraphicsLevel *levels =
1717 data->smc_state_table.GraphicsLevel; 1717 data->smc_state_table.GraphicsLevel;
1718 unsigned min_level = 1; 1718 unsigned min_level = 1;
@@ -1788,7 +1788,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
1788{ 1788{
1789 int result; 1789 int result;
1790 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1790 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1791 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 1791 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1792 struct phm_ppt_v1_information *table_info = 1792 struct phm_ppt_v1_information *table_info =
1793 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1793 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1794 struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1794 struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);
@@ -2011,7 +2011,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2011*/ 2011*/
2012int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 2012int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2013{ 2013{
2014 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 2014 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2015 2015
2016 SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 2016 SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2017 uint32_t duty100; 2017 uint32_t duty100;
@@ -2122,7 +2122,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2122int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr) 2122int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2123{ 2123{
2124 int ret; 2124 int ret;
2125 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 2125 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2126 2126
2127 if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) 2127 if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
2128 return 0; 2128 return 0;
@@ -2150,7 +2150,7 @@ static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2150int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr) 2150int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2151{ 2151{
2152 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2152 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2153 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 2153 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2154 2154
2155 int result = 0; 2155 int result = 0;
2156 uint32_t low_sclk_interrupt_threshold = 0; 2156 uint32_t low_sclk_interrupt_threshold = 0;
@@ -2244,7 +2244,7 @@ uint32_t fiji_get_mac_definition(uint32_t value)
2244 2244
2245static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr) 2245static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2246{ 2246{
2247 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 2247 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2248 uint32_t mm_boot_level_offset, mm_boot_level_value; 2248 uint32_t mm_boot_level_offset, mm_boot_level_value;
2249 struct phm_ppt_v1_information *table_info = 2249 struct phm_ppt_v1_information *table_info =
2250 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2250 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -2276,7 +2276,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2276 2276
2277static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr) 2277static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2278{ 2278{
2279 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 2279 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2280 uint32_t mm_boot_level_offset, mm_boot_level_value; 2280 uint32_t mm_boot_level_offset, mm_boot_level_value;
2281 struct phm_ppt_v1_information *table_info = 2281 struct phm_ppt_v1_information *table_info =
2282 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2282 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -2308,7 +2308,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2308 2308
2309static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr) 2309static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2310{ 2310{
2311 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 2311 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2312 uint32_t mm_boot_level_offset, mm_boot_level_value; 2312 uint32_t mm_boot_level_offset, mm_boot_level_value;
2313 2313
2314 2314
@@ -2361,7 +2361,7 @@ int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2361int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) 2361int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2362{ 2362{
2363 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2363 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2364 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 2364 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2365 uint32_t tmp; 2365 uint32_t tmp;
2366 int result; 2366 int result;
2367 bool error = false; 2367 bool error = false;
@@ -2464,7 +2464,7 @@ int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
2464 struct amd_pp_profile *request) 2464 struct amd_pp_profile *request)
2465{ 2465{
2466 struct fiji_smumgr *smu_data = (struct fiji_smumgr *) 2466 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)
2467 (hwmgr->smumgr->backend); 2467 (hwmgr->smu_backend);
2468 struct SMU73_Discrete_GraphicsLevel *levels = 2468 struct SMU73_Discrete_GraphicsLevel *levels =
2469 smu_data->smc_state_table.GraphicsLevel; 2469 smu_data->smc_state_table.GraphicsLevel;
2470 uint32_t array = smu_data->smu7_data.dpm_table_start + 2470 uint32_t array = smu_data->smu7_data.dpm_table_start +
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index dfdcff54947a..eafac957b0f6 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -166,7 +166,7 @@ static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr)
166 uint32_t reg, data; 166 uint32_t reg, data;
167 167
168 const PWR_Command_Table *pvirus = PwrVirusTable; 168 const PWR_Command_Table *pvirus = PwrVirusTable;
169 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 169 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
170 170
171 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { 171 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
172 switch (pvirus->command) { 172 switch (pvirus->command) {
@@ -195,7 +195,7 @@ static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr)
195static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr) 195static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
196{ 196{
197 int result = 0; 197 int result = 0;
198 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 198 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
199 199
200 if (0 != smu_data->avfs.avfs_btc_param) { 200 if (0 != smu_data->avfs.avfs_btc_param) {
201 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, 201 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
@@ -255,7 +255,7 @@ static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
255 255
256static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started) 256static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started)
257{ 257{
258 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 258 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
259 259
260 switch (smu_data->avfs.avfs_btc_status) { 260 switch (smu_data->avfs.avfs_btc_status) {
261 case AVFS_BTC_COMPLETED_PREVIOUSLY: 261 case AVFS_BTC_COMPLETED_PREVIOUSLY:
@@ -296,7 +296,7 @@ static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started)
296static int fiji_start_smu(struct pp_hwmgr *hwmgr) 296static int fiji_start_smu(struct pp_hwmgr *hwmgr)
297{ 297{
298 int result = 0; 298 int result = 0;
299 struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smumgr->backend); 299 struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend);
300 300
301 /* Only start SMC if SMC RAM is not running */ 301 /* Only start SMC if SMC RAM is not running */
302 if (!(smu7_is_smc_ram_running(hwmgr) 302 if (!(smu7_is_smc_ram_running(hwmgr)
@@ -375,7 +375,7 @@ static int fiji_smu_init(struct pp_hwmgr *hwmgr)
375 if (fiji_priv == NULL) 375 if (fiji_priv == NULL)
376 return -ENOMEM; 376 return -ENOMEM;
377 377
378 hwmgr->smumgr->backend = fiji_priv; 378 hwmgr->smu_backend = fiji_priv;
379 379
380 if (smu7_init(hwmgr)) 380 if (smu7_init(hwmgr))
381 return -EINVAL; 381 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
index 89d5a272e236..efb0fc033274 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
@@ -101,7 +101,7 @@ static const struct iceland_pt_defaults defaults_icelandpro = {
101 101
102static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 102static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
103{ 103{
104 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 104 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
105 struct cgs_system_info sys_info = {0}; 105 struct cgs_system_info sys_info = {0};
106 uint32_t dev_id; 106 uint32_t dev_id;
107 107
@@ -130,7 +130,7 @@ static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
130 130
131static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr) 131static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
132{ 132{
133 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 133 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
134 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; 134 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
135 135
136 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; 136 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
@@ -144,7 +144,7 @@ static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
144static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr) 144static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
145{ 145{
146 uint16_t tdc_limit; 146 uint16_t tdc_limit;
147 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 147 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
148 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; 148 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
149 149
150 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); 150 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
@@ -159,7 +159,7 @@ static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
159 159
160static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 160static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
161{ 161{
162 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 162 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
163 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; 163 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
164 uint32_t temp; 164 uint32_t temp;
165 165
@@ -184,7 +184,7 @@ static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
184static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr) 184static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
185{ 185{
186 int i; 186 int i;
187 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 187 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
188 188
189 /* Currently not used. Set all to zero. */ 189 /* Currently not used. Set all to zero. */
190 for (i = 0; i < 8; i++) 190 for (i = 0; i < 8; i++)
@@ -195,7 +195,7 @@ static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
195 195
196static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) 196static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
197{ 197{
198 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 198 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
199 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; 199 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
200 uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; 200 uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
201 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; 201 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
@@ -214,7 +214,7 @@ static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
214static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr) 214static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
215{ 215{
216 int i; 216 int i;
217 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 217 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
218 uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd; 218 uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
219 uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd; 219 uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
220 220
@@ -240,7 +240,7 @@ static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
240static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr) 240static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
241{ 241{
242 int i; 242 int i;
243 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 243 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
244 uint8_t *vid = smu_data->power_tune_table.VddCVid; 244 uint8_t *vid = smu_data->power_tune_table.VddCVid;
245 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 245 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
246 246
@@ -259,7 +259,7 @@ static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
259 259
260static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr) 260static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
261{ 261{
262 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 262 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
263 uint32_t pm_fuse_table_offset; 263 uint32_t pm_fuse_table_offset;
264 264
265 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 265 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -590,7 +590,7 @@ static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discret
590{ 590{
591 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 591 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
592 struct smu7_dpm_table *dpm_table = &data->dpm_table; 592 struct smu7_dpm_table *dpm_table = &data->dpm_table;
593 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 593 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
594 uint32_t i; 594 uint32_t i;
595 595
596 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ 596 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
@@ -805,7 +805,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
805int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 805int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
806{ 806{
807 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 807 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
808 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 808 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
809 struct smu7_dpm_table *dpm_table = &data->dpm_table; 809 struct smu7_dpm_table *dpm_table = &data->dpm_table;
810 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + 810 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
811 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel); 811 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
@@ -1207,7 +1207,7 @@ static int iceland_populate_single_memory_level(
1207int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1207int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1208{ 1208{
1209 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1209 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1210 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1210 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1211 struct smu7_dpm_table *dpm_table = &data->dpm_table; 1211 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1212 int result; 1212 int result;
1213 1213
@@ -1485,7 +1485,7 @@ static int iceland_populate_memory_timing_parameters(
1485static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) 1485static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1486{ 1486{
1487 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1487 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1488 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1488 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1489 int result = 0; 1489 int result = 0;
1490 SMU71_Discrete_MCArbDramTimingTable arb_regs; 1490 SMU71_Discrete_MCArbDramTimingTable arb_regs;
1491 uint32_t i, j; 1491 uint32_t i, j;
@@ -1523,7 +1523,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1523{ 1523{
1524 int result = 0; 1524 int result = 0;
1525 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1525 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1526 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1526 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1527 table->GraphicsBootLevel = 0; 1527 table->GraphicsBootLevel = 0;
1528 table->MemoryBootLevel = 0; 1528 table->MemoryBootLevel = 0;
1529 1529
@@ -1564,7 +1564,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1564static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, 1564static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1565 SMU71_Discrete_MCRegisters *mc_reg_table) 1565 SMU71_Discrete_MCRegisters *mc_reg_table)
1566{ 1566{
1567 const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smumgr->backend; 1567 const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
1568 1568
1569 uint32_t i, j; 1569 uint32_t i, j;
1570 1570
@@ -1606,7 +1606,7 @@ static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
1606 SMU71_Discrete_MCRegisterSet *mc_reg_table_data 1606 SMU71_Discrete_MCRegisterSet *mc_reg_table_data
1607 ) 1607 )
1608{ 1608{
1609 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1609 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1610 uint32_t i = 0; 1610 uint32_t i = 0;
1611 1611
1612 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { 1612 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
@@ -1650,7 +1650,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1650 1650
1651static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) 1651static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1652{ 1652{
1653 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1653 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1654 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1654 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1655 uint32_t address; 1655 uint32_t address;
1656 int32_t result; 1656 int32_t result;
@@ -1678,7 +1678,7 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1678static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) 1678static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1679{ 1679{
1680 int result; 1680 int result;
1681 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1681 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1682 1682
1683 memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters)); 1683 memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
1684 result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); 1684 result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
@@ -1696,7 +1696,7 @@ static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1696static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr) 1696static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1697{ 1697{
1698 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1698 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1699 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1699 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1700 uint8_t count, level; 1700 uint8_t count, level;
1701 1701
1702 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); 1702 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
@@ -1725,7 +1725,7 @@ static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1725static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) 1725static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1726{ 1726{
1727 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1727 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1728 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1728 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1729 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; 1729 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
1730 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); 1730 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
1731 struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; 1731 struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
@@ -1813,7 +1813,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
1813{ 1813{
1814 int result; 1814 int result;
1815 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1815 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1816 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 1816 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1817 SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1817 SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1818 1818
1819 1819
@@ -1980,7 +1980,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
1980*/ 1980*/
1981int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 1981int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
1982{ 1982{
1983 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 1983 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
1984 SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 1984 SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1985 uint32_t duty100; 1985 uint32_t duty100;
1986 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; 1986 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
@@ -2070,7 +2070,7 @@ static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2070int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) 2070int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2071{ 2071{
2072 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2072 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2073 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 2073 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2074 2074
2075 int result = 0; 2075 int result = 0;
2076 uint32_t low_sclk_interrupt_threshold = 0; 2076 uint32_t low_sclk_interrupt_threshold = 0;
@@ -2168,7 +2168,7 @@ uint32_t iceland_get_mac_definition(uint32_t value)
2168int iceland_process_firmware_header(struct pp_hwmgr *hwmgr) 2168int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2169{ 2169{
2170 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2170 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2171 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 2171 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2172 2172
2173 uint32_t tmp; 2173 uint32_t tmp;
2174 int result; 2174 int result;
@@ -2508,7 +2508,7 @@ static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)
2508int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) 2508int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2509{ 2509{
2510 int result; 2510 int result;
2511 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); 2511 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2512 pp_atomctrl_mc_reg_table *table; 2512 pp_atomctrl_mc_reg_table *table;
2513 struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table; 2513 struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
2514 uint8_t module_index = iceland_get_memory_modile_index(hwmgr); 2514 uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index d66527299308..fd63d2800d05 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -208,7 +208,7 @@ static int iceland_smu_init(struct pp_hwmgr *hwmgr)
208 if (iceland_priv == NULL) 208 if (iceland_priv == NULL)
209 return -ENOMEM; 209 return -ENOMEM;
210 210
211 hwmgr->smumgr->backend = iceland_priv; 211 hwmgr->smu_backend = iceland_priv;
212 212
213 if (smu7_init(hwmgr)) 213 if (smu7_init(hwmgr))
214 return -EINVAL; 214 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index 118315186bc3..d0913a6696fd 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -148,7 +148,7 @@ static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
148 148
149static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) 149static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
150{ 150{
151 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 151 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
152 152
153 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 153 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
154 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 154 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
@@ -196,7 +196,7 @@ static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmg
196 196
197static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) 197static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
198{ 198{
199 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 199 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
200 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 200 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
201 201
202 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; 202 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
@@ -210,7 +210,7 @@ static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
210static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) 210static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
211{ 211{
212 uint16_t tdc_limit; 212 uint16_t tdc_limit;
213 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 213 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
214 struct phm_ppt_v1_information *table_info = 214 struct phm_ppt_v1_information *table_info =
215 (struct phm_ppt_v1_information *)(hwmgr->pptable); 215 (struct phm_ppt_v1_information *)(hwmgr->pptable);
216 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 216 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
@@ -227,7 +227,7 @@ static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
227 227
228static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 228static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
229{ 229{
230 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 230 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
231 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 231 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
232 uint32_t temp; 232 uint32_t temp;
233 233
@@ -252,7 +252,7 @@ static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of
252static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) 252static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
253{ 253{
254 int i; 254 int i;
255 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 255 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
256 256
257 /* Currently not used. Set all to zero. */ 257 /* Currently not used. Set all to zero. */
258 for (i = 0; i < 16; i++) 258 for (i = 0; i < 16; i++)
@@ -263,7 +263,7 @@ static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
263 263
264static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) 264static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
265{ 265{
266 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 266 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
267 267
268/* TO DO move to hwmgr */ 268/* TO DO move to hwmgr */
269 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) 269 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
@@ -279,7 +279,7 @@ static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
279static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) 279static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
280{ 280{
281 int i; 281 int i;
282 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 282 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
283 283
284 /* Currently not used. Set all to zero. */ 284 /* Currently not used. Set all to zero. */
285 for (i = 0; i < 16; i++) 285 for (i = 0; i < 16; i++)
@@ -290,7 +290,7 @@ static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
290 290
291static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) 291static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
292{ 292{
293 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 293 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
294 struct phm_ppt_v1_information *table_info = 294 struct phm_ppt_v1_information *table_info =
295 (struct phm_ppt_v1_information *)(hwmgr->pptable); 295 (struct phm_ppt_v1_information *)(hwmgr->pptable);
296 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; 296 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
@@ -310,7 +310,7 @@ static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr
310 310
311static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) 311static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
312{ 312{
313 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 313 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
314 uint32_t pm_fuse_table_offset; 314 uint32_t pm_fuse_table_offset;
315 315
316 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 316 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -492,7 +492,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
492 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * 492 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
493 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 493 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
494 494
495 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) 495 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
496 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; 496 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
497 else 497 else
498 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; 498 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
@@ -514,7 +514,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
514 struct SMU74_Discrete_DpmTable *table) 514 struct SMU74_Discrete_DpmTable *table)
515{ 515{
516 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 516 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
517 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 517 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
518 struct smu7_dpm_table *dpm_table = &data->dpm_table; 518 struct smu7_dpm_table *dpm_table = &data->dpm_table;
519 int i; 519 int i;
520 520
@@ -545,7 +545,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
545static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, 545static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
546 SMU74_Discrete_DpmTable *table) 546 SMU74_Discrete_DpmTable *table)
547{ 547{
548 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 548 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
549 uint32_t i, ref_clk; 549 uint32_t i, ref_clk;
550 550
551 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; 551 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
@@ -595,7 +595,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
595static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, 595static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
596 uint32_t clock, SMU_SclkSetting *sclk_setting) 596 uint32_t clock, SMU_SclkSetting *sclk_setting)
597{ 597{
598 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 598 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
599 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 599 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
600 struct pp_atomctrl_clock_dividers_ai dividers; 600 struct pp_atomctrl_clock_dividers_ai dividers;
601 uint32_t ref_clock; 601 uint32_t ref_clock;
@@ -739,7 +739,7 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
739int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 739int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
740{ 740{
741 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 741 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
742 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 742 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
743 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; 743 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
744 struct phm_ppt_v1_information *table_info = 744 struct phm_ppt_v1_information *table_info =
745 (struct phm_ppt_v1_information *)(hwmgr->pptable); 745 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -887,7 +887,7 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
887int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 887int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
888{ 888{
889 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 889 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
890 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 890 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
891 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; 891 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
892 int result; 892 int result;
893 /* populate MCLK dpm table to SMU7 */ 893 /* populate MCLK dpm table to SMU7 */
@@ -1187,7 +1187,7 @@ static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1187static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) 1187static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1188{ 1188{
1189 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1189 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1190 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1190 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1191 struct SMU74_Discrete_MCArbDramTimingTable arb_regs; 1191 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1192 uint32_t i, j; 1192 uint32_t i, j;
1193 int result = 0; 1193 int result = 0;
@@ -1306,7 +1306,7 @@ static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1306static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) 1306static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1307{ 1307{
1308 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1308 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1309 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1309 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1310 struct phm_ppt_v1_information *table_info = 1310 struct phm_ppt_v1_information *table_info =
1311 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1311 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1312 uint8_t count, level; 1312 uint8_t count, level;
@@ -1337,7 +1337,7 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1337static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) 1337static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1338{ 1338{
1339 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; 1339 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1340 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1340 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1341 1341
1342 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0; 1342 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1343 struct phm_ppt_v1_information *table_info = 1343 struct phm_ppt_v1_information *table_info =
@@ -1420,7 +1420,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1420 struct SMU74_Discrete_DpmTable *table) 1420 struct SMU74_Discrete_DpmTable *table)
1421{ 1421{
1422 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1422 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1423 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1423 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1424 uint16_t config; 1424 uint16_t config;
1425 1425
1426 config = VR_MERGED_WITH_VDDC; 1426 config = VR_MERGED_WITH_VDDC;
@@ -1464,7 +1464,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1464static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 1464static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1465{ 1465{
1466 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1466 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1467 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1467 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1468 1468
1469 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1469 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1470 int result = 0; 1470 int result = 0;
@@ -1552,7 +1552,7 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1552*/ 1552*/
1553static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr) 1553static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
1554{ 1554{
1555 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1555 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1556 uint32_t tmp; 1556 uint32_t tmp;
1557 int result; 1557 int result;
1558 1558
@@ -1579,7 +1579,7 @@ static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
1579 1579
1580static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 1580static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1581{ 1581{
1582 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1582 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1583 struct phm_ppt_v1_information *table_info = 1583 struct phm_ppt_v1_information *table_info =
1584 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1584 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1585 1585
@@ -1596,7 +1596,7 @@ static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1596 1596
1597static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr) 1597static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
1598{ 1598{
1599 struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1599 struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1600 struct SMU74_Discrete_GraphicsLevel *levels = 1600 struct SMU74_Discrete_GraphicsLevel *levels =
1601 data->smc_state_table.GraphicsLevel; 1601 data->smc_state_table.GraphicsLevel;
1602 unsigned min_level = 1; 1602 unsigned min_level = 1;
@@ -1640,7 +1640,8 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1640{ 1640{
1641 int result; 1641 int result;
1642 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1642 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1643 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1643 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1644
1644 struct phm_ppt_v1_information *table_info = 1645 struct phm_ppt_v1_information *table_info =
1645 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1646 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1646 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1647 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
@@ -1868,7 +1869,7 @@ static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
1868int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr) 1869int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
1869{ 1870{
1870 int ret; 1871 int ret;
1871 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 1872 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
1872 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1873 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1873 1874
1874 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED) 1875 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
@@ -1898,7 +1899,7 @@ int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
1898*/ 1899*/
1899int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 1900int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
1900{ 1901{
1901 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 1902 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1902 SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 1903 SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1903 uint32_t duty100; 1904 uint32_t duty100;
1904 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; 1905 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
@@ -2006,7 +2007,7 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2006 2007
2007static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr) 2008static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2008{ 2009{
2009 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 2010 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2010 uint32_t mm_boot_level_offset, mm_boot_level_value; 2011 uint32_t mm_boot_level_offset, mm_boot_level_value;
2011 struct phm_ppt_v1_information *table_info = 2012 struct phm_ppt_v1_information *table_info =
2012 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2013 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -2038,7 +2039,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2038 2039
2039static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr) 2040static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2040{ 2041{
2041 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 2042 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2042 uint32_t mm_boot_level_offset, mm_boot_level_value; 2043 uint32_t mm_boot_level_offset, mm_boot_level_value;
2043 struct phm_ppt_v1_information *table_info = 2044 struct phm_ppt_v1_information *table_info =
2044 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2045 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -2070,7 +2071,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2070 2071
2071static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr) 2072static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2072{ 2073{
2073 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 2074 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2074 uint32_t mm_boot_level_offset, mm_boot_level_value; 2075 uint32_t mm_boot_level_offset, mm_boot_level_value;
2075 2076
2076 2077
@@ -2098,7 +2099,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2098 2099
2099static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr) 2100static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2100{ 2101{
2101 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 2102 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2102 struct phm_ppt_v1_information *table_info = 2103 struct phm_ppt_v1_information *table_info =
2103 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2104 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2104 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; 2105 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
@@ -2136,7 +2137,7 @@ int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2136int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) 2137int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2137{ 2138{
2138 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2139 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2139 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 2140 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2140 2141
2141 int result = 0; 2142 int result = 0;
2142 uint32_t low_sclk_interrupt_threshold = 0; 2143 uint32_t low_sclk_interrupt_threshold = 0;
@@ -2241,7 +2242,7 @@ uint32_t polaris10_get_mac_definition(uint32_t value)
2241*/ 2242*/
2242int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) 2243int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2243{ 2244{
2244 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 2245 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2245 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2246 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2246 uint32_t tmp; 2247 uint32_t tmp;
2247 int result; 2248 int result;
@@ -2321,7 +2322,7 @@ int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
2321 struct amd_pp_profile *request) 2322 struct amd_pp_profile *request)
2322{ 2323{
2323 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *) 2324 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2324 (hwmgr->smumgr->backend); 2325 (hwmgr->smu_backend);
2325 struct SMU74_Discrete_GraphicsLevel *levels = 2326 struct SMU74_Discrete_GraphicsLevel *levels =
2326 smu_data->smc_state_table.GraphicsLevel; 2327 smu_data->smc_state_table.GraphicsLevel;
2327 uint32_t array = smu_data->smu7_data.dpm_table_start + 2328 uint32_t array = smu_data->smu7_data.dpm_table_start +
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 55ba76202aa3..884ba2ca5399 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -67,7 +67,7 @@ static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
67 uint32_t reg, data; 67 uint32_t reg, data;
68 68
69 const PWR_Command_Table *pvirus = pwr_virus_table; 69 const PWR_Command_Table *pvirus = pwr_virus_table;
70 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 70 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
71 71
72 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { 72 for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
73 switch (pvirus->command) { 73 switch (pvirus->command) {
@@ -96,7 +96,7 @@ static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
96static int polaris10_perform_btc(struct pp_hwmgr *hwmgr) 96static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
97{ 97{
98 int result = 0; 98 int result = 0;
99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
100 100
101 if (0 != smu_data->avfs.avfs_btc_param) { 101 if (0 != smu_data->avfs.avfs_btc_param) {
102 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { 102 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
@@ -174,7 +174,7 @@ static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
174static int 174static int
175polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT) 175polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT)
176{ 176{
177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
178 178
179 switch (smu_data->avfs.avfs_btc_status) { 179 switch (smu_data->avfs.avfs_btc_status) {
180 case AVFS_BTC_COMPLETED_PREVIOUSLY: 180 case AVFS_BTC_COMPLETED_PREVIOUSLY:
@@ -310,7 +310,7 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
310static int polaris10_start_smu(struct pp_hwmgr *hwmgr) 310static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
311{ 311{
312 int result = 0; 312 int result = 0;
313 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); 313 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
314 bool SMU_VFT_INTACT; 314 bool SMU_VFT_INTACT;
315 315
316 /* Only start SMC if SMC RAM is not running */ 316 /* Only start SMC if SMC RAM is not running */
@@ -371,7 +371,7 @@ static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
371 if (smu_data == NULL) 371 if (smu_data == NULL)
372 return -ENOMEM; 372 return -ENOMEM;
373 373
374 hwmgr->smumgr->backend = smu_data; 374 hwmgr->smu_backend = smu_data;
375 375
376 if (smu7_init(hwmgr)) 376 if (smu7_init(hwmgr))
377 return -EINVAL; 377 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index 54d3052dd157..f9afe88569d1 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -159,7 +159,7 @@ int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
159 uint8_t *table, int16_t table_id) 159 uint8_t *table, int16_t table_id)
160{ 160{
161 struct rv_smumgr *priv = 161 struct rv_smumgr *priv =
162 (struct rv_smumgr *)(hwmgr->smumgr->backend); 162 (struct rv_smumgr *)(hwmgr->smu_backend);
163 163
164 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 164 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
165 "Invalid SMU Table ID!", return -EINVAL;); 165 "Invalid SMU Table ID!", return -EINVAL;);
@@ -192,7 +192,7 @@ int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
192 uint8_t *table, int16_t table_id) 192 uint8_t *table, int16_t table_id)
193{ 193{
194 struct rv_smumgr *priv = 194 struct rv_smumgr *priv =
195 (struct rv_smumgr *)(hwmgr->smumgr->backend); 195 (struct rv_smumgr *)(hwmgr->smu_backend);
196 196
197 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 197 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
198 "Invalid SMU Table ID!", return -EINVAL;); 198 "Invalid SMU Table ID!", return -EINVAL;);
@@ -287,7 +287,7 @@ static int rv_smc_disable_vcn(struct pp_hwmgr *hwmgr)
287static int rv_smu_fini(struct pp_hwmgr *hwmgr) 287static int rv_smu_fini(struct pp_hwmgr *hwmgr)
288{ 288{
289 struct rv_smumgr *priv = 289 struct rv_smumgr *priv =
290 (struct rv_smumgr *)(hwmgr->smumgr->backend); 290 (struct rv_smumgr *)(hwmgr->smu_backend);
291 291
292 if (priv) { 292 if (priv) {
293 rv_smc_disable_sdma(hwmgr); 293 rv_smc_disable_sdma(hwmgr);
@@ -296,8 +296,8 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr)
296 priv->smu_tables.entry[WMTABLE].handle); 296 priv->smu_tables.entry[WMTABLE].handle);
297 cgs_free_gpu_mem(hwmgr->device, 297 cgs_free_gpu_mem(hwmgr->device,
298 priv->smu_tables.entry[CLOCKTABLE].handle); 298 priv->smu_tables.entry[CLOCKTABLE].handle);
299 kfree(hwmgr->smumgr->backend); 299 kfree(hwmgr->smu_backend);
300 hwmgr->smumgr->backend = NULL; 300 hwmgr->smu_backend = NULL;
301 } 301 }
302 302
303 return 0; 303 return 0;
@@ -327,7 +327,7 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
327 if (!priv) 327 if (!priv)
328 return -ENOMEM; 328 return -ENOMEM;
329 329
330 hwmgr->smumgr->backend = priv; 330 hwmgr->smu_backend = priv;
331 331
332 /* allocate space for watermarks table */ 332 /* allocate space for watermarks table */
333 smu_allocate_memory(hwmgr->device, 333 smu_allocate_memory(hwmgr->device,
@@ -340,8 +340,8 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
340 340
341 PP_ASSERT_WITH_CODE(kaddr, 341 PP_ASSERT_WITH_CODE(kaddr,
342 "[rv_smu_init] Out of memory for wmtable.", 342 "[rv_smu_init] Out of memory for wmtable.",
343 kfree(hwmgr->smumgr->backend); 343 kfree(hwmgr->smu_backend);
344 hwmgr->smumgr->backend = NULL; 344 hwmgr->smu_backend = NULL;
345 return -EINVAL); 345 return -EINVAL);
346 346
347 priv->smu_tables.entry[WMTABLE].version = 0x01; 347 priv->smu_tables.entry[WMTABLE].version = 0x01;
@@ -367,8 +367,8 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
367 "[rv_smu_init] Out of memory for CLOCKTABLE.", 367 "[rv_smu_init] Out of memory for CLOCKTABLE.",
368 cgs_free_gpu_mem(hwmgr->device, 368 cgs_free_gpu_mem(hwmgr->device,
369 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle); 369 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
370 kfree(hwmgr->smumgr->backend); 370 kfree(hwmgr->smu_backend);
371 hwmgr->smumgr->backend = NULL; 371 hwmgr->smu_backend = NULL;
372 return -EINVAL); 372 return -EINVAL);
373 373
374 priv->smu_tables.entry[CLOCKTABLE].version = 0x01; 374 priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index cd283e5af68c..412cf6f74f67 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -391,12 +391,12 @@ static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
391 391
392int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr) 392int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
393{ 393{
394 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 394 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
395 uint32_t fw_to_load; 395 uint32_t fw_to_load;
396 int result = 0; 396 int result = 0;
397 struct SMU_DRAMData_TOC *toc; 397 struct SMU_DRAMData_TOC *toc;
398 398
399 if (!hwmgr->smumgr->reload_fw) { 399 if (!hwmgr->reload_fw) {
400 pr_info("skip reloading...\n"); 400 pr_info("skip reloading...\n");
401 return 0; 401 return 0;
402 } 402 }
@@ -483,7 +483,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
483/* Check if the FW has been loaded, SMU will not return if loading has not finished. */ 483/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
484int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type) 484int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
485{ 485{
486 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 486 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
487 uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type); 487 uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
488 uint32_t ret; 488 uint32_t ret;
489 489
@@ -497,7 +497,7 @@ int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
497 497
498int smu7_reload_firmware(struct pp_hwmgr *hwmgr) 498int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
499{ 499{
500 return hwmgr->smumgr->smumgr_funcs->start_smu(hwmgr); 500 return hwmgr->smumgr_funcs->start_smu(hwmgr);
501} 501}
502 502
503static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit) 503static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
@@ -523,7 +523,7 @@ static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length
523int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr) 523int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
524{ 524{
525 int result = 0; 525 int result = 0;
526 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 526 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
527 527
528 struct cgs_firmware_info info = {0}; 528 struct cgs_firmware_info info = {0};
529 529
@@ -534,7 +534,7 @@ int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
534 cgs_get_firmware_info(hwmgr->device, 534 cgs_get_firmware_info(hwmgr->device,
535 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); 535 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
536 536
537 hwmgr->smumgr->is_kicker = info.is_kicker; 537 hwmgr->is_kicker = info.is_kicker;
538 538
539 result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE); 539 result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
540 540
@@ -548,7 +548,7 @@ int smu7_init(struct pp_hwmgr *hwmgr)
548 uint64_t mc_addr = 0; 548 uint64_t mc_addr = 0;
549 549
550 /* Allocate memory for backend private data */ 550 /* Allocate memory for backend private data */
551 smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend); 551 smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
552 smu_data->header_buffer.data_size = 552 smu_data->header_buffer.data_size =
553 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; 553 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
554 554
@@ -568,7 +568,7 @@ int smu7_init(struct pp_hwmgr *hwmgr)
568 568
569 PP_ASSERT_WITH_CODE((NULL != smu_data->header), 569 PP_ASSERT_WITH_CODE((NULL != smu_data->header),
570 "Out of memory.", 570 "Out of memory.",
571 kfree(hwmgr->smumgr->backend); 571 kfree(hwmgr->smu_backend);
572 cgs_free_gpu_mem(hwmgr->device, 572 cgs_free_gpu_mem(hwmgr->device,
573 (cgs_handle_t)smu_data->header_buffer.handle); 573 (cgs_handle_t)smu_data->header_buffer.handle);
574 return -EINVAL); 574 return -EINVAL);
@@ -591,7 +591,7 @@ int smu7_init(struct pp_hwmgr *hwmgr)
591 591
592 PP_ASSERT_WITH_CODE((NULL != internal_buf), 592 PP_ASSERT_WITH_CODE((NULL != internal_buf),
593 "Out of memory.", 593 "Out of memory.",
594 kfree(hwmgr->smumgr->backend); 594 kfree(hwmgr->smu_backend);
595 cgs_free_gpu_mem(hwmgr->device, 595 cgs_free_gpu_mem(hwmgr->device,
596 (cgs_handle_t)smu_data->smu_buffer.handle); 596 (cgs_handle_t)smu_data->smu_buffer.handle);
597 return -EINVAL); 597 return -EINVAL);
@@ -607,8 +607,8 @@ int smu7_init(struct pp_hwmgr *hwmgr)
607 607
608int smu7_smu_fini(struct pp_hwmgr *hwmgr) 608int smu7_smu_fini(struct pp_hwmgr *hwmgr)
609{ 609{
610 kfree(hwmgr->smumgr->backend); 610 kfree(hwmgr->smu_backend);
611 hwmgr->smumgr->backend = NULL; 611 hwmgr->smu_backend = NULL;
612 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU); 612 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
613 return 0; 613 return 0;
614} 614}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index a58346e78c35..d3c12e0ca464 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -27,7 +27,6 @@
27#include <linux/slab.h> 27#include <linux/slab.h>
28#include <linux/types.h> 28#include <linux/types.h>
29#include <drm/amdgpu_drm.h> 29#include <drm/amdgpu_drm.h>
30#include "pp_instance.h"
31#include "smumgr.h" 30#include "smumgr.h"
32#include "cgs_common.h" 31#include "cgs_common.h"
33 32
@@ -46,89 +45,18 @@ MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
46MODULE_FIRMWARE("amdgpu/vega10_smc.bin"); 45MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
47MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin"); 46MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
48 47
49int smum_early_init(struct pp_instance *handle)
50{
51 struct pp_smumgr *smumgr;
52
53 if (handle == NULL)
54 return -EINVAL;
55
56 smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
57 if (smumgr == NULL)
58 return -ENOMEM;
59
60 smumgr->device = handle->device;
61 smumgr->chip_family = handle->chip_family;
62 smumgr->chip_id = handle->chip_id;
63 smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
64 smumgr->reload_fw = 1;
65 handle->smu_mgr = smumgr;
66
67 switch (smumgr->chip_family) {
68 case AMDGPU_FAMILY_CI:
69 smumgr->smumgr_funcs = &ci_smu_funcs;
70 break;
71 case AMDGPU_FAMILY_CZ:
72 smumgr->smumgr_funcs = &cz_smu_funcs;
73 break;
74 case AMDGPU_FAMILY_VI:
75 switch (smumgr->chip_id) {
76 case CHIP_TOPAZ:
77 smumgr->smumgr_funcs = &iceland_smu_funcs;
78 break;
79 case CHIP_TONGA:
80 smumgr->smumgr_funcs = &tonga_smu_funcs;
81 break;
82 case CHIP_FIJI:
83 smumgr->smumgr_funcs = &fiji_smu_funcs;
84 break;
85 case CHIP_POLARIS11:
86 case CHIP_POLARIS10:
87 case CHIP_POLARIS12:
88 smumgr->smumgr_funcs = &polaris10_smu_funcs;
89 break;
90 default:
91 return -EINVAL;
92 }
93 break;
94 case AMDGPU_FAMILY_AI:
95 switch (smumgr->chip_id) {
96 case CHIP_VEGA10:
97 smumgr->smumgr_funcs = &vega10_smu_funcs;
98 break;
99 default:
100 return -EINVAL;
101 }
102 break;
103 case AMDGPU_FAMILY_RV:
104 switch (smumgr->chip_id) {
105 case CHIP_RAVEN:
106 smumgr->smumgr_funcs = &rv_smu_funcs;
107 break;
108 default:
109 return -EINVAL;
110 }
111 break;
112 default:
113 kfree(smumgr);
114 return -EINVAL;
115 }
116
117 return 0;
118}
119
120int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr) 48int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
121{ 49{
122 if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable) 50 if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable)
123 return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr); 51 return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
124 52
125 return 0; 53 return 0;
126} 54}
127 55
128int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 56int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
129{ 57{
130 if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table) 58 if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table)
131 return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr); 59 return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
132 60
133 return 0; 61 return 0;
134} 62}
@@ -136,8 +64,8 @@ int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
136int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr) 64int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
137{ 65{
138 66
139 if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold) 67 if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold)
140 return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr); 68 return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr);
141 69
142 return 0; 70 return 0;
143} 71}
@@ -145,74 +73,74 @@ int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
145int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) 73int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
146{ 74{
147 75
148 if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table) 76 if (NULL != hwmgr->smumgr_funcs->update_smc_table)
149 return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type); 77 return hwmgr->smumgr_funcs->update_smc_table(hwmgr, type);
150 78
151 return 0; 79 return 0;
152} 80}
153 81
154uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member) 82uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)
155{ 83{
156 if (NULL != hwmgr->smumgr->smumgr_funcs->get_offsetof) 84 if (NULL != hwmgr->smumgr_funcs->get_offsetof)
157 return hwmgr->smumgr->smumgr_funcs->get_offsetof(type, member); 85 return hwmgr->smumgr_funcs->get_offsetof(type, member);
158 86
159 return 0; 87 return 0;
160} 88}
161 89
162int smum_process_firmware_header(struct pp_hwmgr *hwmgr) 90int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
163{ 91{
164 if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header) 92 if (NULL != hwmgr->smumgr_funcs->process_firmware_header)
165 return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr); 93 return hwmgr->smumgr_funcs->process_firmware_header(hwmgr);
166 return 0; 94 return 0;
167} 95}
168 96
169int smum_get_argument(struct pp_hwmgr *hwmgr) 97int smum_get_argument(struct pp_hwmgr *hwmgr)
170{ 98{
171 if (NULL != hwmgr->smumgr->smumgr_funcs->get_argument) 99 if (NULL != hwmgr->smumgr_funcs->get_argument)
172 return hwmgr->smumgr->smumgr_funcs->get_argument(hwmgr); 100 return hwmgr->smumgr_funcs->get_argument(hwmgr);
173 101
174 return 0; 102 return 0;
175} 103}
176 104
177uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value) 105uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)
178{ 106{
179 if (NULL != hwmgr->smumgr->smumgr_funcs->get_mac_definition) 107 if (NULL != hwmgr->smumgr_funcs->get_mac_definition)
180 return hwmgr->smumgr->smumgr_funcs->get_mac_definition(value); 108 return hwmgr->smumgr_funcs->get_mac_definition(value);
181 109
182 return 0; 110 return 0;
183} 111}
184 112
185int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table) 113int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)
186{ 114{
187 if (NULL != hwmgr->smumgr->smumgr_funcs->download_pptable_settings) 115 if (NULL != hwmgr->smumgr_funcs->download_pptable_settings)
188 return hwmgr->smumgr->smumgr_funcs->download_pptable_settings(hwmgr, 116 return hwmgr->smumgr_funcs->download_pptable_settings(hwmgr,
189 table); 117 table);
190 return 0; 118 return 0;
191} 119}
192 120
193int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr) 121int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr)
194{ 122{
195 if (NULL != hwmgr->smumgr->smumgr_funcs->upload_pptable_settings) 123 if (NULL != hwmgr->smumgr_funcs->upload_pptable_settings)
196 return hwmgr->smumgr->smumgr_funcs->upload_pptable_settings(hwmgr); 124 return hwmgr->smumgr_funcs->upload_pptable_settings(hwmgr);
197 125
198 return 0; 126 return 0;
199} 127}
200 128
201int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) 129int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
202{ 130{
203 if (hwmgr == NULL || hwmgr->smumgr->smumgr_funcs->send_msg_to_smc == NULL) 131 if (hwmgr == NULL || hwmgr->smumgr_funcs->send_msg_to_smc == NULL)
204 return -EINVAL; 132 return -EINVAL;
205 133
206 return hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg); 134 return hwmgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg);
207} 135}
208 136
209int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, 137int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
210 uint16_t msg, uint32_t parameter) 138 uint16_t msg, uint32_t parameter)
211{ 139{
212 if (hwmgr == NULL || 140 if (hwmgr == NULL ||
213 hwmgr->smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL) 141 hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
214 return -EINVAL; 142 return -EINVAL;
215 return hwmgr->smumgr->smumgr_funcs->send_msg_to_smc_with_parameter( 143 return hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter(
216 hwmgr, msg, parameter); 144 hwmgr, msg, parameter);
217} 145}
218 146
@@ -356,24 +284,24 @@ int smu_free_memory(void *device, void *handle)
356 284
357int smum_init_smc_table(struct pp_hwmgr *hwmgr) 285int smum_init_smc_table(struct pp_hwmgr *hwmgr)
358{ 286{
359 if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table) 287 if (NULL != hwmgr->smumgr_funcs->init_smc_table)
360 return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr); 288 return hwmgr->smumgr_funcs->init_smc_table(hwmgr);
361 289
362 return 0; 290 return 0;
363} 291}
364 292
365int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 293int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
366{ 294{
367 if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels) 295 if (NULL != hwmgr->smumgr_funcs->populate_all_graphic_levels)
368 return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr); 296 return hwmgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
369 297
370 return 0; 298 return 0;
371} 299}
372 300
373int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 301int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
374{ 302{
375 if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels) 303 if (NULL != hwmgr->smumgr_funcs->populate_all_memory_levels)
376 return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr); 304 return hwmgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
377 305
378 return 0; 306 return 0;
379} 307}
@@ -381,16 +309,16 @@ int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
381/*this interface is needed by island ci/vi */ 309/*this interface is needed by island ci/vi */
382int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) 310int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
383{ 311{
384 if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table) 312 if (NULL != hwmgr->smumgr_funcs->initialize_mc_reg_table)
385 return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr); 313 return hwmgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
386 314
387 return 0; 315 return 0;
388} 316}
389 317
390bool smum_is_dpm_running(struct pp_hwmgr *hwmgr) 318bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
391{ 319{
392 if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running) 320 if (NULL != hwmgr->smumgr_funcs->is_dpm_running)
393 return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr); 321 return hwmgr->smumgr_funcs->is_dpm_running(hwmgr);
394 322
395 return true; 323 return true;
396} 324}
@@ -398,8 +326,8 @@ bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
398int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr, 326int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
399 struct amd_pp_profile *request) 327 struct amd_pp_profile *request)
400{ 328{
401 if (hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels) 329 if (hwmgr->smumgr_funcs->populate_requested_graphic_levels)
402 return hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels( 330 return hwmgr->smumgr_funcs->populate_requested_graphic_levels(
403 hwmgr, request); 331 hwmgr, request);
404 332
405 return 0; 333 return 0;
@@ -407,8 +335,8 @@ int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
407 335
408bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr) 336bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
409{ 337{
410 if (hwmgr->smumgr->smumgr_funcs->is_hw_avfs_present) 338 if (hwmgr->smumgr_funcs->is_hw_avfs_present)
411 return hwmgr->smumgr->smumgr_funcs->is_hw_avfs_present(hwmgr); 339 return hwmgr->smumgr_funcs->is_hw_avfs_present(hwmgr);
412 340
413 return false; 341 return false;
414} 342}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
index 68e1e19b971b..1f720ccdaf99 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
@@ -406,7 +406,7 @@ static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_
406{ 406{
407 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 407 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
408 struct smu7_dpm_table *dpm_table = &data->dpm_table; 408 struct smu7_dpm_table *dpm_table = &data->dpm_table;
409 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 409 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
410 uint32_t i; 410 uint32_t i;
411 411
412 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ 412 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
@@ -598,7 +598,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
598int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 598int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
599{ 599{
600 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 600 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
601 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 601 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
602 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 602 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
603 struct smu7_dpm_table *dpm_table = &data->dpm_table; 603 struct smu7_dpm_table *dpm_table = &data->dpm_table;
604 struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; 604 struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
@@ -1002,7 +1002,7 @@ int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1002{ 1002{
1003 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1003 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1004 struct tonga_smumgr *smu_data = 1004 struct tonga_smumgr *smu_data =
1005 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1005 (struct tonga_smumgr *)(hwmgr->smu_backend);
1006 struct smu7_dpm_table *dpm_table = &data->dpm_table; 1006 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1007 int result; 1007 int result;
1008 1008
@@ -1090,7 +1090,7 @@ static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1090{ 1090{
1091 int result = 0; 1091 int result = 0;
1092 struct tonga_smumgr *smu_data = 1092 struct tonga_smumgr *smu_data =
1093 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1093 (struct tonga_smumgr *)(hwmgr->smu_backend);
1094 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1094 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1095 struct pp_atomctrl_clock_dividers_vi dividers; 1095 struct pp_atomctrl_clock_dividers_vi dividers;
1096 1096
@@ -1454,7 +1454,7 @@ static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1454{ 1454{
1455 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1455 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1456 struct tonga_smumgr *smu_data = 1456 struct tonga_smumgr *smu_data =
1457 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1457 (struct tonga_smumgr *)(hwmgr->smu_backend);
1458 int result = 0; 1458 int result = 0;
1459 SMU72_Discrete_MCArbDramTimingTable arb_regs; 1459 SMU72_Discrete_MCArbDramTimingTable arb_regs;
1460 uint32_t i, j; 1460 uint32_t i, j;
@@ -1492,7 +1492,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1492 int result = 0; 1492 int result = 0;
1493 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1493 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1494 struct tonga_smumgr *smu_data = 1494 struct tonga_smumgr *smu_data =
1495 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1495 (struct tonga_smumgr *)(hwmgr->smu_backend);
1496 table->GraphicsBootLevel = 0; 1496 table->GraphicsBootLevel = 0;
1497 table->MemoryBootLevel = 0; 1497 table->MemoryBootLevel = 0;
1498 1498
@@ -1543,7 +1543,7 @@ static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1543 volt_with_cks, value; 1543 volt_with_cks, value;
1544 uint16_t clock_freq_u16; 1544 uint16_t clock_freq_u16;
1545 struct tonga_smumgr *smu_data = 1545 struct tonga_smumgr *smu_data =
1546 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1546 (struct tonga_smumgr *)(hwmgr->smu_backend);
1547 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, 1547 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1548 volt_offset = 0; 1548 volt_offset = 0;
1549 struct phm_ppt_v1_information *table_info = 1549 struct phm_ppt_v1_information *table_info =
@@ -1784,7 +1784,7 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1784 */ 1784 */
1785static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) 1785static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
1786{ 1786{
1787 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1787 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
1788 uint32_t tmp; 1788 uint32_t tmp;
1789 int result; 1789 int result;
1790 1790
@@ -1814,7 +1814,7 @@ static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
1814static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) 1814static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1815{ 1815{
1816 struct tonga_smumgr *smu_data = 1816 struct tonga_smumgr *smu_data =
1817 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1817 (struct tonga_smumgr *)(hwmgr->smu_backend);
1818 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1818 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1819 SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); 1819 SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
1820 struct phm_ppt_v1_information *table_info = 1820 struct phm_ppt_v1_information *table_info =
@@ -1861,7 +1861,7 @@ static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1861static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr) 1861static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1862{ 1862{
1863 struct tonga_smumgr *smu_data = 1863 struct tonga_smumgr *smu_data =
1864 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1864 (struct tonga_smumgr *)(hwmgr->smu_backend);
1865 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1865 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1866 1866
1867 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; 1867 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
@@ -1876,7 +1876,7 @@ static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1876{ 1876{
1877 uint16_t tdc_limit; 1877 uint16_t tdc_limit;
1878 struct tonga_smumgr *smu_data = 1878 struct tonga_smumgr *smu_data =
1879 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1879 (struct tonga_smumgr *)(hwmgr->smu_backend);
1880 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1880 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1881 struct phm_ppt_v1_information *table_info = 1881 struct phm_ppt_v1_information *table_info =
1882 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1882 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -1897,7 +1897,7 @@ static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1897static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 1897static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1898{ 1898{
1899 struct tonga_smumgr *smu_data = 1899 struct tonga_smumgr *smu_data =
1900 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1900 (struct tonga_smumgr *)(hwmgr->smu_backend);
1901 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1901 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
1902 uint32_t temp; 1902 uint32_t temp;
1903 1903
@@ -1919,7 +1919,7 @@ static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1919{ 1919{
1920 int i; 1920 int i;
1921 struct tonga_smumgr *smu_data = 1921 struct tonga_smumgr *smu_data =
1922 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1922 (struct tonga_smumgr *)(hwmgr->smu_backend);
1923 1923
1924 /* Currently not used. Set all to zero. */ 1924 /* Currently not used. Set all to zero. */
1925 for (i = 0; i < 16; i++) 1925 for (i = 0; i < 16; i++)
@@ -1930,7 +1930,7 @@ static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1930 1930
1931static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) 1931static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1932{ 1932{
1933 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1933 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
1934 1934
1935 if ((hwmgr->thermal_controller.advanceFanControlParameters. 1935 if ((hwmgr->thermal_controller.advanceFanControlParameters.
1936 usFanOutputSensitivity & (1 << 15)) || 1936 usFanOutputSensitivity & (1 << 15)) ||
@@ -1949,7 +1949,7 @@ static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1949{ 1949{
1950 int i; 1950 int i;
1951 struct tonga_smumgr *smu_data = 1951 struct tonga_smumgr *smu_data =
1952 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1952 (struct tonga_smumgr *)(hwmgr->smu_backend);
1953 1953
1954 /* Currently not used. Set all to zero. */ 1954 /* Currently not used. Set all to zero. */
1955 for (i = 0; i < 16; i++) 1955 for (i = 0; i < 16; i++)
@@ -1961,7 +1961,7 @@ static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1961static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) 1961static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1962{ 1962{
1963 struct tonga_smumgr *smu_data = 1963 struct tonga_smumgr *smu_data =
1964 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1964 (struct tonga_smumgr *)(hwmgr->smu_backend);
1965 struct phm_ppt_v1_information *table_info = 1965 struct phm_ppt_v1_information *table_info =
1966 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1966 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1967 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; 1967 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
@@ -1982,7 +1982,7 @@ static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1982static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) 1982static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1983{ 1983{
1984 struct tonga_smumgr *smu_data = 1984 struct tonga_smumgr *smu_data =
1985 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 1985 (struct tonga_smumgr *)(hwmgr->smu_backend);
1986 uint32_t pm_fuse_table_offset; 1986 uint32_t pm_fuse_table_offset;
1987 1987
1988 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1988 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -2051,7 +2051,7 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
2051static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, 2051static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
2052 SMU72_Discrete_MCRegisters *mc_reg_table) 2052 SMU72_Discrete_MCRegisters *mc_reg_table)
2053{ 2053{
2054 const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smumgr->backend; 2054 const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend;
2055 2055
2056 uint32_t i, j; 2056 uint32_t i, j;
2057 2057
@@ -2097,7 +2097,7 @@ static int tonga_convert_mc_reg_table_entry_to_smc(
2097 SMU72_Discrete_MCRegisterSet *mc_reg_table_data 2097 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
2098 ) 2098 )
2099{ 2099{
2100 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2100 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2101 uint32_t i = 0; 2101 uint32_t i = 0;
2102 2102
2103 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { 2103 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
@@ -2141,7 +2141,7 @@ static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
2141 2141
2142static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) 2142static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
2143{ 2143{
2144 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2144 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2145 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2145 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2146 uint32_t address; 2146 uint32_t address;
2147 int32_t result; 2147 int32_t result;
@@ -2172,7 +2172,7 @@ static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
2172static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) 2172static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
2173{ 2173{
2174 int result; 2174 int result;
2175 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2175 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2176 2176
2177 memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters)); 2177 memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
2178 result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); 2178 result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
@@ -2191,7 +2191,7 @@ static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
2191 2191
2192static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 2192static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
2193{ 2193{
2194 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2194 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2195 struct phm_ppt_v1_information *table_info = 2195 struct phm_ppt_v1_information *table_info =
2196 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2196 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2197 2197
@@ -2207,7 +2207,7 @@ static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
2207 2207
2208static void tonga_save_default_power_profile(struct pp_hwmgr *hwmgr) 2208static void tonga_save_default_power_profile(struct pp_hwmgr *hwmgr)
2209{ 2209{
2210 struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2210 struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2211 struct SMU72_Discrete_GraphicsLevel *levels = 2211 struct SMU72_Discrete_GraphicsLevel *levels =
2212 data->smc_state_table.GraphicsLevel; 2212 data->smc_state_table.GraphicsLevel;
2213 unsigned min_level = 1; 2213 unsigned min_level = 1;
@@ -2253,7 +2253,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2253 int result; 2253 int result;
2254 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2254 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2255 struct tonga_smumgr *smu_data = 2255 struct tonga_smumgr *smu_data =
2256 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2256 (struct tonga_smumgr *)(hwmgr->smu_backend);
2257 SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table); 2257 SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
2258 struct phm_ppt_v1_information *table_info = 2258 struct phm_ppt_v1_information *table_info =
2259 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2259 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -2507,7 +2507,7 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2507int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 2507int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2508{ 2508{
2509 struct tonga_smumgr *smu_data = 2509 struct tonga_smumgr *smu_data =
2510 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2510 (struct tonga_smumgr *)(hwmgr->smu_backend);
2511 SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 2511 SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2512 uint32_t duty100; 2512 uint32_t duty100;
2513 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; 2513 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
@@ -2611,7 +2611,7 @@ int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2611{ 2611{
2612 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2612 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2613 struct tonga_smumgr *smu_data = 2613 struct tonga_smumgr *smu_data =
2614 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2614 (struct tonga_smumgr *)(hwmgr->smu_backend);
2615 2615
2616 int result = 0; 2616 int result = 0;
2617 uint32_t low_sclk_interrupt_threshold = 0; 2617 uint32_t low_sclk_interrupt_threshold = 0;
@@ -2714,7 +2714,7 @@ uint32_t tonga_get_mac_definition(uint32_t value)
2714static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr) 2714static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2715{ 2715{
2716 struct tonga_smumgr *smu_data = 2716 struct tonga_smumgr *smu_data =
2717 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2717 (struct tonga_smumgr *)(hwmgr->smu_backend);
2718 uint32_t mm_boot_level_offset, mm_boot_level_value; 2718 uint32_t mm_boot_level_offset, mm_boot_level_value;
2719 struct phm_ppt_v1_information *table_info = 2719 struct phm_ppt_v1_information *table_info =
2720 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2720 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -2748,7 +2748,7 @@ static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2748static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr) 2748static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2749{ 2749{
2750 struct tonga_smumgr *smu_data = 2750 struct tonga_smumgr *smu_data =
2751 (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2751 (struct tonga_smumgr *)(hwmgr->smu_backend);
2752 uint32_t mm_boot_level_offset, mm_boot_level_value; 2752 uint32_t mm_boot_level_offset, mm_boot_level_value;
2753 struct phm_ppt_v1_information *table_info = 2753 struct phm_ppt_v1_information *table_info =
2754 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2754 (struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -2778,7 +2778,7 @@ static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2778 2778
2779static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr) 2779static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2780{ 2780{
2781 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2781 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2782 uint32_t mm_boot_level_offset, mm_boot_level_value; 2782 uint32_t mm_boot_level_offset, mm_boot_level_value;
2783 2783
2784 smu_data->smc_state_table.SamuBootLevel = 0; 2784 smu_data->smc_state_table.SamuBootLevel = 0;
@@ -2830,7 +2830,7 @@ int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2830int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) 2830int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2831{ 2831{
2832 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2832 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2833 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 2833 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2834 2834
2835 uint32_t tmp; 2835 uint32_t tmp;
2836 int result; 2836 int result;
@@ -3156,7 +3156,7 @@ static int tonga_set_valid_flag(struct tonga_mc_reg_table *table)
3156int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) 3156int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
3157{ 3157{
3158 int result; 3158 int result;
3159 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); 3159 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
3160 pp_atomctrl_mc_reg_table *table; 3160 pp_atomctrl_mc_reg_table *table;
3161 struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table; 3161 struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table;
3162 uint8_t module_index = tonga_get_memory_modile_index(hwmgr); 3162 uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
@@ -3239,7 +3239,7 @@ int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
3239 struct amd_pp_profile *request) 3239 struct amd_pp_profile *request)
3240{ 3240{
3241 struct tonga_smumgr *smu_data = (struct tonga_smumgr *) 3241 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)
3242 (hwmgr->smumgr->backend); 3242 (hwmgr->smu_backend);
3243 struct SMU72_Discrete_GraphicsLevel *levels = 3243 struct SMU72_Discrete_GraphicsLevel *levels =
3244 smu_data->smc_state_table.GraphicsLevel; 3244 smu_data->smc_state_table.GraphicsLevel;
3245 uint32_t array = smu_data->smu7_data.dpm_table_start + 3245 uint32_t array = smu_data->smu7_data.dpm_table_start +
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index c10e6f89dbae..105cb2a3ff6d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -176,7 +176,7 @@ static int tonga_smu_init(struct pp_hwmgr *hwmgr)
176 if (tonga_priv == NULL) 176 if (tonga_priv == NULL)
177 return -ENOMEM; 177 return -ENOMEM;
178 178
179 hwmgr->smumgr->backend = tonga_priv; 179 hwmgr->smu_backend = tonga_priv;
180 180
181 if (smu7_init(hwmgr)) 181 if (smu7_init(hwmgr))
182 return -EINVAL; 182 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index c63127058090..4cb5d3460fef 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -224,7 +224,7 @@ int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
224 uint8_t *table, int16_t table_id) 224 uint8_t *table, int16_t table_id)
225{ 225{
226 struct vega10_smumgr *priv = 226 struct vega10_smumgr *priv =
227 (struct vega10_smumgr *)(hwmgr->smumgr->backend); 227 (struct vega10_smumgr *)(hwmgr->smu_backend);
228 228
229 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 229 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
230 "Invalid SMU Table ID!", return -EINVAL); 230 "Invalid SMU Table ID!", return -EINVAL);
@@ -262,7 +262,7 @@ int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
262 uint8_t *table, int16_t table_id) 262 uint8_t *table, int16_t table_id)
263{ 263{
264 struct vega10_smumgr *priv = 264 struct vega10_smumgr *priv =
265 (struct vega10_smumgr *)(hwmgr->smumgr->backend); 265 (struct vega10_smumgr *)(hwmgr->smu_backend);
266 266
267 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 267 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
268 "Invalid SMU Table ID!", return -EINVAL); 268 "Invalid SMU Table ID!", return -EINVAL);
@@ -339,7 +339,7 @@ int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
339int vega10_set_tools_address(struct pp_hwmgr *hwmgr) 339int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
340{ 340{
341 struct vega10_smumgr *priv = 341 struct vega10_smumgr *priv =
342 (struct vega10_smumgr *)(hwmgr->smumgr->backend); 342 (struct vega10_smumgr *)(hwmgr->smu_backend);
343 343
344 if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high || 344 if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high ||
345 priv->smu_tables.entry[TOOLSTABLE].table_addr_low) { 345 priv->smu_tables.entry[TOOLSTABLE].table_addr_low) {
@@ -412,7 +412,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
412 if (!priv) 412 if (!priv)
413 return -ENOMEM; 413 return -ENOMEM;
414 414
415 hwmgr->smumgr->backend = priv; 415 hwmgr->smu_backend = priv;
416 416
417 /* allocate space for pptable */ 417 /* allocate space for pptable */
418 smu_allocate_memory(hwmgr->device, 418 smu_allocate_memory(hwmgr->device,
@@ -425,7 +425,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
425 425
426 PP_ASSERT_WITH_CODE(kaddr, 426 PP_ASSERT_WITH_CODE(kaddr,
427 "[vega10_smu_init] Out of memory for pptable.", 427 "[vega10_smu_init] Out of memory for pptable.",
428 kfree(hwmgr->smumgr->backend); 428 kfree(hwmgr->smu_backend);
429 cgs_free_gpu_mem(hwmgr->device, 429 cgs_free_gpu_mem(hwmgr->device,
430 (cgs_handle_t)handle); 430 (cgs_handle_t)handle);
431 return -EINVAL); 431 return -EINVAL);
@@ -451,7 +451,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
451 451
452 PP_ASSERT_WITH_CODE(kaddr, 452 PP_ASSERT_WITH_CODE(kaddr,
453 "[vega10_smu_init] Out of memory for wmtable.", 453 "[vega10_smu_init] Out of memory for wmtable.",
454 kfree(hwmgr->smumgr->backend); 454 kfree(hwmgr->smu_backend);
455 cgs_free_gpu_mem(hwmgr->device, 455 cgs_free_gpu_mem(hwmgr->device,
456 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); 456 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
457 cgs_free_gpu_mem(hwmgr->device, 457 cgs_free_gpu_mem(hwmgr->device,
@@ -479,7 +479,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
479 479
480 PP_ASSERT_WITH_CODE(kaddr, 480 PP_ASSERT_WITH_CODE(kaddr,
481 "[vega10_smu_init] Out of memory for avfs table.", 481 "[vega10_smu_init] Out of memory for avfs table.",
482 kfree(hwmgr->smumgr->backend); 482 kfree(hwmgr->smu_backend);
483 cgs_free_gpu_mem(hwmgr->device, 483 cgs_free_gpu_mem(hwmgr->device,
484 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); 484 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
485 cgs_free_gpu_mem(hwmgr->device, 485 cgs_free_gpu_mem(hwmgr->device,
@@ -532,7 +532,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
532 532
533 PP_ASSERT_WITH_CODE(kaddr, 533 PP_ASSERT_WITH_CODE(kaddr,
534 "[vega10_smu_init] Out of memory for avfs fuse table.", 534 "[vega10_smu_init] Out of memory for avfs fuse table.",
535 kfree(hwmgr->smumgr->backend); 535 kfree(hwmgr->smu_backend);
536 cgs_free_gpu_mem(hwmgr->device, 536 cgs_free_gpu_mem(hwmgr->device,
537 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle); 537 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
538 cgs_free_gpu_mem(hwmgr->device, 538 cgs_free_gpu_mem(hwmgr->device,
@@ -561,7 +561,7 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr)
561static int vega10_smu_fini(struct pp_hwmgr *hwmgr) 561static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
562{ 562{
563 struct vega10_smumgr *priv = 563 struct vega10_smumgr *priv =
564 (struct vega10_smumgr *)(hwmgr->smumgr->backend); 564 (struct vega10_smumgr *)(hwmgr->smu_backend);
565 565
566 if (priv) { 566 if (priv) {
567 cgs_free_gpu_mem(hwmgr->device, 567 cgs_free_gpu_mem(hwmgr->device,
@@ -575,8 +575,8 @@ static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
575 (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle); 575 (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
576 cgs_free_gpu_mem(hwmgr->device, 576 cgs_free_gpu_mem(hwmgr->device,
577 (cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle); 577 (cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle);
578 kfree(hwmgr->smumgr->backend); 578 kfree(hwmgr->smu_backend);
579 hwmgr->smumgr->backend = NULL; 579 hwmgr->smu_backend = NULL;
580 } 580 }
581 return 0; 581 return 0;
582} 582}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 10:16:26 -0400