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authorMichael Turquette <mturquette@baylibre.com>2016-01-04 19:16:45 -0500
committerMichael Turquette <mturquette@baylibre.com>2016-01-04 19:16:45 -0500
commitb360ada3f1534a37b264274cad55932d2a214ec3 (patch)
tree052ded4d0172924ee55d3d4e2c3ea18146e3b629
parent7ed88aa2efa5422f9d93fd99f2a01c56e28a7409 (diff)
parent2d7f61f37731f635af47615a8a331ffe7f884934 (diff)
Merge tag 'tegra-for-4.5-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.5-rc1 This set of changes adds support for the Tegra210 SoC and contains a couple fixes and cleanups.
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt56
-rw-r--r--drivers/clk/tegra/Makefile1
-rw-r--r--drivers/clk/tegra/clk-id.h75
-rw-r--r--drivers/clk/tegra/clk-pll.c834
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c371
-rw-r--r--drivers/clk/tegra/clk-tegra-super-gen4.c142
-rw-r--r--drivers/clk/tegra/clk-tegra114.c339
-rw-r--r--drivers/clk/tegra/clk-tegra124.c453
-rw-r--r--drivers/clk/tegra/clk-tegra20.c314
-rw-r--r--drivers/clk/tegra/clk-tegra210.c2852
-rw-r--r--drivers/clk/tegra/clk-tegra30.c426
-rw-r--r--drivers/clk/tegra/clk.h101
-rw-r--r--include/dt-bindings/clock/tegra210-car.h401
13 files changed, 5437 insertions, 928 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt
new file mode 100644
index 000000000000..26f237f641b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt
@@ -0,0 +1,56 @@
1NVIDIA Tegra210 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra210-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
16 CAR. The assignments may be found in header file
17 <dt-bindings/clock/tegra210-car.h>.
18- #reset-cells : Should be 1.
19 In clock consumers, this cell represents the bit number in the CAR's
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
21
22Example SoC include file:
23
24/ {
25 tegra_car: clock {
26 compatible = "nvidia,tegra210-car";
27 reg = <0x60006000 0x1000>;
28 #clock-cells = <1>;
29 #reset-cells = <1>;
30 };
31
32 usb@c5004000 {
33 clocks = <&tegra_car TEGRA210_CLK_USB2>;
34 };
35};
36
37Example board file:
38
39/ {
40 clocks {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 clk_32k: clock@1 {
46 compatible = "fixed-clock";
47 reg = <1>;
48 #clock-cells = <0>;
49 clock-frequency = <32768>;
50 };
51 };
52
53 &tegra_car {
54 clocks = <&clk_32k>;
55 };
56};
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 826c325dc2e8..97984c503bbb 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
20obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o 20obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o
21obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o 21obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
22obj-y += cvb.o 22obj-y += cvb.o
23obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 60738cc954cb..19ce0738ee76 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -13,6 +13,7 @@ enum clk_id {
13 tegra_clk_amx1, 13 tegra_clk_amx1,
14 tegra_clk_apbdma, 14 tegra_clk_apbdma,
15 tegra_clk_apbif, 15 tegra_clk_apbif,
16 tegra_clk_ape,
16 tegra_clk_audio0, 17 tegra_clk_audio0,
17 tegra_clk_audio0_2x, 18 tegra_clk_audio0_2x,
18 tegra_clk_audio0_mux, 19 tegra_clk_audio0_mux,
@@ -38,6 +39,7 @@ enum clk_id {
38 tegra_clk_cile, 39 tegra_clk_cile,
39 tegra_clk_clk_32k, 40 tegra_clk_clk_32k,
40 tegra_clk_clk72Mhz, 41 tegra_clk_clk72Mhz,
42 tegra_clk_clk72Mhz_8,
41 tegra_clk_clk_m, 43 tegra_clk_clk_m,
42 tegra_clk_clk_m_div2, 44 tegra_clk_clk_m_div2,
43 tegra_clk_clk_m_div4, 45 tegra_clk_clk_m_div4,
@@ -51,17 +53,21 @@ enum clk_id {
51 tegra_clk_cml1, 53 tegra_clk_cml1,
52 tegra_clk_csi, 54 tegra_clk_csi,
53 tegra_clk_csite, 55 tegra_clk_csite,
56 tegra_clk_csite_8,
54 tegra_clk_csus, 57 tegra_clk_csus,
55 tegra_clk_cve, 58 tegra_clk_cve,
56 tegra_clk_dam0, 59 tegra_clk_dam0,
57 tegra_clk_dam1, 60 tegra_clk_dam1,
58 tegra_clk_dam2, 61 tegra_clk_dam2,
59 tegra_clk_d_audio, 62 tegra_clk_d_audio,
63 tegra_clk_dbgapb,
60 tegra_clk_dds, 64 tegra_clk_dds,
61 tegra_clk_dfll_ref, 65 tegra_clk_dfll_ref,
62 tegra_clk_dfll_soc, 66 tegra_clk_dfll_soc,
63 tegra_clk_disp1, 67 tegra_clk_disp1,
68 tegra_clk_disp1_8,
64 tegra_clk_disp2, 69 tegra_clk_disp2,
70 tegra_clk_disp2_8,
65 tegra_clk_dp2, 71 tegra_clk_dp2,
66 tegra_clk_dpaux, 72 tegra_clk_dpaux,
67 tegra_clk_dsialp, 73 tegra_clk_dsialp,
@@ -71,6 +77,7 @@ enum clk_id {
71 tegra_clk_dtv, 77 tegra_clk_dtv,
72 tegra_clk_emc, 78 tegra_clk_emc,
73 tegra_clk_entropy, 79 tegra_clk_entropy,
80 tegra_clk_entropy_8,
74 tegra_clk_epp, 81 tegra_clk_epp,
75 tegra_clk_epp_8, 82 tegra_clk_epp_8,
76 tegra_clk_extern1, 83 tegra_clk_extern1,
@@ -85,12 +92,16 @@ enum clk_id {
85 tegra_clk_gr3d_8, 92 tegra_clk_gr3d_8,
86 tegra_clk_hclk, 93 tegra_clk_hclk,
87 tegra_clk_hda, 94 tegra_clk_hda,
95 tegra_clk_hda_8,
88 tegra_clk_hda2codec_2x, 96 tegra_clk_hda2codec_2x,
97 tegra_clk_hda2codec_2x_8,
89 tegra_clk_hda2hdmi, 98 tegra_clk_hda2hdmi,
90 tegra_clk_hdmi, 99 tegra_clk_hdmi,
91 tegra_clk_hdmi_audio, 100 tegra_clk_hdmi_audio,
92 tegra_clk_host1x, 101 tegra_clk_host1x,
93 tegra_clk_host1x_8, 102 tegra_clk_host1x_8,
103 tegra_clk_host1x_9,
104 tegra_clk_hsic_trk,
94 tegra_clk_i2c1, 105 tegra_clk_i2c1,
95 tegra_clk_i2c2, 106 tegra_clk_i2c2,
96 tegra_clk_i2c3, 107 tegra_clk_i2c3,
@@ -110,11 +121,14 @@ enum clk_id {
110 tegra_clk_i2s4_sync, 121 tegra_clk_i2s4_sync,
111 tegra_clk_isp, 122 tegra_clk_isp,
112 tegra_clk_isp_8, 123 tegra_clk_isp_8,
124 tegra_clk_isp_9,
113 tegra_clk_ispb, 125 tegra_clk_ispb,
114 tegra_clk_kbc, 126 tegra_clk_kbc,
115 tegra_clk_kfuse, 127 tegra_clk_kfuse,
116 tegra_clk_la, 128 tegra_clk_la,
129 tegra_clk_maud,
117 tegra_clk_mipi, 130 tegra_clk_mipi,
131 tegra_clk_mipibif,
118 tegra_clk_mipi_cal, 132 tegra_clk_mipi_cal,
119 tegra_clk_mpe, 133 tegra_clk_mpe,
120 tegra_clk_mselect, 134 tegra_clk_mselect,
@@ -124,15 +138,24 @@ enum clk_id {
124 tegra_clk_ndspeed, 138 tegra_clk_ndspeed,
125 tegra_clk_ndspeed_8, 139 tegra_clk_ndspeed_8,
126 tegra_clk_nor, 140 tegra_clk_nor,
141 tegra_clk_nvdec,
142 tegra_clk_nvenc,
143 tegra_clk_nvjpg,
127 tegra_clk_owr, 144 tegra_clk_owr,
145 tegra_clk_owr_8,
128 tegra_clk_pcie, 146 tegra_clk_pcie,
129 tegra_clk_pclk, 147 tegra_clk_pclk,
130 tegra_clk_pll_a, 148 tegra_clk_pll_a,
131 tegra_clk_pll_a_out0, 149 tegra_clk_pll_a_out0,
150 tegra_clk_pll_a1,
132 tegra_clk_pll_c, 151 tegra_clk_pll_c,
133 tegra_clk_pll_c2, 152 tegra_clk_pll_c2,
134 tegra_clk_pll_c3, 153 tegra_clk_pll_c3,
135 tegra_clk_pll_c4, 154 tegra_clk_pll_c4,
155 tegra_clk_pll_c4_out0,
156 tegra_clk_pll_c4_out1,
157 tegra_clk_pll_c4_out2,
158 tegra_clk_pll_c4_out3,
136 tegra_clk_pll_c_out1, 159 tegra_clk_pll_c_out1,
137 tegra_clk_pll_d, 160 tegra_clk_pll_d,
138 tegra_clk_pll_d2, 161 tegra_clk_pll_d2,
@@ -140,19 +163,29 @@ enum clk_id {
140 tegra_clk_pll_d_out0, 163 tegra_clk_pll_d_out0,
141 tegra_clk_pll_dp, 164 tegra_clk_pll_dp,
142 tegra_clk_pll_e_out0, 165 tegra_clk_pll_e_out0,
166 tegra_clk_pll_g_ref,
143 tegra_clk_pll_m, 167 tegra_clk_pll_m,
144 tegra_clk_pll_m_out1, 168 tegra_clk_pll_m_out1,
169 tegra_clk_pll_mb,
145 tegra_clk_pll_p, 170 tegra_clk_pll_p,
146 tegra_clk_pll_p_out1, 171 tegra_clk_pll_p_out1,
147 tegra_clk_pll_p_out2, 172 tegra_clk_pll_p_out2,
148 tegra_clk_pll_p_out2_int, 173 tegra_clk_pll_p_out2_int,
149 tegra_clk_pll_p_out3, 174 tegra_clk_pll_p_out3,
150 tegra_clk_pll_p_out4, 175 tegra_clk_pll_p_out4,
176 tegra_clk_pll_p_out4_cpu,
151 tegra_clk_pll_p_out5, 177 tegra_clk_pll_p_out5,
178 tegra_clk_pll_p_out_hsio,
179 tegra_clk_pll_p_out_xusb,
180 tegra_clk_pll_p_out_cpu,
181 tegra_clk_pll_p_out_adsp,
152 tegra_clk_pll_ref, 182 tegra_clk_pll_ref,
153 tegra_clk_pll_re_out, 183 tegra_clk_pll_re_out,
154 tegra_clk_pll_re_vco, 184 tegra_clk_pll_re_vco,
155 tegra_clk_pll_u, 185 tegra_clk_pll_u,
186 tegra_clk_pll_u_out,
187 tegra_clk_pll_u_out1,
188 tegra_clk_pll_u_out2,
156 tegra_clk_pll_u_12m, 189 tegra_clk_pll_u_12m,
157 tegra_clk_pll_u_480m, 190 tegra_clk_pll_u_480m,
158 tegra_clk_pll_u_48m, 191 tegra_clk_pll_u_48m,
@@ -160,53 +193,80 @@ enum clk_id {
160 tegra_clk_pll_x, 193 tegra_clk_pll_x,
161 tegra_clk_pll_x_out0, 194 tegra_clk_pll_x_out0,
162 tegra_clk_pwm, 195 tegra_clk_pwm,
196 tegra_clk_qspi,
163 tegra_clk_rtc, 197 tegra_clk_rtc,
164 tegra_clk_sata, 198 tegra_clk_sata,
199 tegra_clk_sata_8,
165 tegra_clk_sata_cold, 200 tegra_clk_sata_cold,
166 tegra_clk_sata_oob, 201 tegra_clk_sata_oob,
202 tegra_clk_sata_oob_8,
167 tegra_clk_sbc1, 203 tegra_clk_sbc1,
168 tegra_clk_sbc1_8, 204 tegra_clk_sbc1_8,
205 tegra_clk_sbc1_9,
169 tegra_clk_sbc2, 206 tegra_clk_sbc2,
170 tegra_clk_sbc2_8, 207 tegra_clk_sbc2_8,
208 tegra_clk_sbc2_9,
171 tegra_clk_sbc3, 209 tegra_clk_sbc3,
172 tegra_clk_sbc3_8, 210 tegra_clk_sbc3_8,
211 tegra_clk_sbc3_9,
173 tegra_clk_sbc4, 212 tegra_clk_sbc4,
174 tegra_clk_sbc4_8, 213 tegra_clk_sbc4_8,
214 tegra_clk_sbc4_9,
175 tegra_clk_sbc5, 215 tegra_clk_sbc5,
176 tegra_clk_sbc5_8, 216 tegra_clk_sbc5_8,
177 tegra_clk_sbc6, 217 tegra_clk_sbc6,
178 tegra_clk_sbc6_8, 218 tegra_clk_sbc6_8,
179 tegra_clk_sclk, 219 tegra_clk_sclk,
220 tegra_clk_sdmmc_legacy,
180 tegra_clk_sdmmc1, 221 tegra_clk_sdmmc1,
181 tegra_clk_sdmmc1_8, 222 tegra_clk_sdmmc1_8,
223 tegra_clk_sdmmc1_9,
182 tegra_clk_sdmmc2, 224 tegra_clk_sdmmc2,
183 tegra_clk_sdmmc2_8, 225 tegra_clk_sdmmc2_8,
226 tegra_clk_sdmmc2_9,
184 tegra_clk_sdmmc3, 227 tegra_clk_sdmmc3,
185 tegra_clk_sdmmc3_8, 228 tegra_clk_sdmmc3_8,
229 tegra_clk_sdmmc3_9,
186 tegra_clk_sdmmc4, 230 tegra_clk_sdmmc4,
187 tegra_clk_sdmmc4_8, 231 tegra_clk_sdmmc4_8,
232 tegra_clk_sdmmc4_9,
188 tegra_clk_se, 233 tegra_clk_se,
189 tegra_clk_soc_therm, 234 tegra_clk_soc_therm,
235 tegra_clk_soc_therm_8,
190 tegra_clk_sor0, 236 tegra_clk_sor0,
191 tegra_clk_sor0_lvds, 237 tegra_clk_sor0_lvds,
238 tegra_clk_sor1,
239 tegra_clk_sor1_brick,
240 tegra_clk_sor1_src,
192 tegra_clk_spdif, 241 tegra_clk_spdif,
193 tegra_clk_spdif_2x, 242 tegra_clk_spdif_2x,
194 tegra_clk_spdif_in, 243 tegra_clk_spdif_in,
244 tegra_clk_spdif_in_8,
195 tegra_clk_spdif_in_sync, 245 tegra_clk_spdif_in_sync,
196 tegra_clk_spdif_mux, 246 tegra_clk_spdif_mux,
197 tegra_clk_spdif_out, 247 tegra_clk_spdif_out,
198 tegra_clk_timer, 248 tegra_clk_timer,
199 tegra_clk_trace, 249 tegra_clk_trace,
200 tegra_clk_tsec, 250 tegra_clk_tsec,
251 tegra_clk_tsec_8,
252 tegra_clk_tsecb,
201 tegra_clk_tsensor, 253 tegra_clk_tsensor,
202 tegra_clk_tvdac, 254 tegra_clk_tvdac,
203 tegra_clk_tvo, 255 tegra_clk_tvo,
204 tegra_clk_uarta, 256 tegra_clk_uarta,
257 tegra_clk_uarta_8,
205 tegra_clk_uartb, 258 tegra_clk_uartb,
259 tegra_clk_uartb_8,
206 tegra_clk_uartc, 260 tegra_clk_uartc,
261 tegra_clk_uartc_8,
207 tegra_clk_uartd, 262 tegra_clk_uartd,
263 tegra_clk_uartd_8,
208 tegra_clk_uarte, 264 tegra_clk_uarte,
265 tegra_clk_uarte_8,
266 tegra_clk_uartape,
209 tegra_clk_usb2, 267 tegra_clk_usb2,
268 tegra_clk_usb2_hsic_trk,
269 tegra_clk_usb2_trk,
210 tegra_clk_usb3, 270 tegra_clk_usb3,
211 tegra_clk_usbd, 271 tegra_clk_usbd,
212 tegra_clk_vcp, 272 tegra_clk_vcp,
@@ -216,22 +276,35 @@ enum clk_id {
216 tegra_clk_vi, 276 tegra_clk_vi,
217 tegra_clk_vi_8, 277 tegra_clk_vi_8,
218 tegra_clk_vi_9, 278 tegra_clk_vi_9,
279 tegra_clk_vi_10,
280 tegra_clk_vi_i2c,
219 tegra_clk_vic03, 281 tegra_clk_vic03,
282 tegra_clk_vic03_8,
220 tegra_clk_vim2_clk, 283 tegra_clk_vim2_clk,
221 tegra_clk_vimclk_sync, 284 tegra_clk_vimclk_sync,
222 tegra_clk_vi_sensor, 285 tegra_clk_vi_sensor,
223 tegra_clk_vi_sensor2,
224 tegra_clk_vi_sensor_8, 286 tegra_clk_vi_sensor_8,
287 tegra_clk_vi_sensor_9,
288 tegra_clk_vi_sensor2,
289 tegra_clk_vi_sensor2_8,
225 tegra_clk_xusb_dev, 290 tegra_clk_xusb_dev,
226 tegra_clk_xusb_dev_src, 291 tegra_clk_xusb_dev_src,
292 tegra_clk_xusb_dev_src_8,
227 tegra_clk_xusb_falcon_src, 293 tegra_clk_xusb_falcon_src,
294 tegra_clk_xusb_falcon_src_8,
228 tegra_clk_xusb_fs_src, 295 tegra_clk_xusb_fs_src,
296 tegra_clk_xusb_gate,
229 tegra_clk_xusb_host, 297 tegra_clk_xusb_host,
230 tegra_clk_xusb_host_src, 298 tegra_clk_xusb_host_src,
299 tegra_clk_xusb_host_src_8,
231 tegra_clk_xusb_hs_src, 300 tegra_clk_xusb_hs_src,
301 tegra_clk_xusb_hs_src_4,
232 tegra_clk_xusb_ss, 302 tegra_clk_xusb_ss,
233 tegra_clk_xusb_ss_src, 303 tegra_clk_xusb_ss_src,
304 tegra_clk_xusb_ss_src_8,
234 tegra_clk_xusb_ss_div2, 305 tegra_clk_xusb_ss_div2,
306 tegra_clk_xusb_ssp_src,
307 tegra_clk_sclk_mux,
235 tegra_clk_max, 308 tegra_clk_max,
236}; 309};
237 310
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index d6d4ecb88e94..a534bfab30b3 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -65,6 +65,7 @@
65#define PLLE_BASE_DIVN_WIDTH 8 65#define PLLE_BASE_DIVN_WIDTH 8
66#define PLLE_BASE_DIVM_SHIFT 0 66#define PLLE_BASE_DIVM_SHIFT 0
67#define PLLE_BASE_DIVM_WIDTH 8 67#define PLLE_BASE_DIVM_WIDTH 8
68#define PLLE_BASE_ENABLE BIT(31)
68 69
69#define PLLE_MISC_SETUP_BASE_SHIFT 16 70#define PLLE_MISC_SETUP_BASE_SHIFT 16
70#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 71#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
@@ -102,6 +103,7 @@
102#define PLLE_AUX_SEQ_ENABLE BIT(24) 103#define PLLE_AUX_SEQ_ENABLE BIT(24)
103#define PLLE_AUX_SEQ_START_STATE BIT(25) 104#define PLLE_AUX_SEQ_START_STATE BIT(25)
104#define PLLE_AUX_PLLRE_SEL BIT(28) 105#define PLLE_AUX_PLLRE_SEL BIT(28)
106#define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
105 107
106#define XUSBIO_PLL_CFG0 0x51c 108#define XUSBIO_PLL_CFG0 0x51c
107#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 109#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
@@ -187,17 +189,23 @@
187#define pll_readl_base(p) pll_readl(p->params->base_reg, p) 189#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
188#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 190#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
189#define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset) 191#define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
192#define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
193#define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
190 194
191#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 195#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
192#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 196#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
193#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 197#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
194#define pll_override_writel(val, offset, p) writel(val, p->pmc + offset) 198#define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
199#define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
200#define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
195 201
196#define mask(w) ((1 << (w)) - 1) 202#define mask(w) ((1 << (w)) - 1)
197#define divm_mask(p) mask(p->params->div_nmp->divm_width) 203#define divm_mask(p) mask(p->params->div_nmp->divm_width)
198#define divn_mask(p) mask(p->params->div_nmp->divn_width) 204#define divn_mask(p) mask(p->params->div_nmp->divn_width)
199#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 205#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
200 mask(p->params->div_nmp->divp_width)) 206 mask(p->params->div_nmp->divp_width))
207#define sdm_din_mask(p) p->params->sdm_din_mask
208#define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
201 209
202#define divm_shift(p) (p)->params->div_nmp->divm_shift 210#define divm_shift(p) (p)->params->div_nmp->divm_shift
203#define divn_shift(p) (p)->params->div_nmp->divn_shift 211#define divn_shift(p) (p)->params->div_nmp->divn_shift
@@ -211,6 +219,9 @@
211#define divn_max(p) (divn_mask(p)) 219#define divn_max(p) (divn_mask(p))
212#define divp_max(p) (1 << (divp_mask(p))) 220#define divp_max(p) (1 << (divp_mask(p)))
213 221
222#define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
223#define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
224
214static struct div_nmp default_nmp = { 225static struct div_nmp default_nmp = {
215 .divn_shift = PLL_BASE_DIVN_SHIFT, 226 .divn_shift = PLL_BASE_DIVN_SHIFT,
216 .divn_width = PLL_BASE_DIVN_WIDTH, 227 .divn_width = PLL_BASE_DIVN_WIDTH,
@@ -269,6 +280,11 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
269 return -1; 280 return -1;
270} 281}
271 282
283int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
284{
285 return clk_pll_wait_for_lock(pll);
286}
287
272static int clk_pll_is_enabled(struct clk_hw *hw) 288static int clk_pll_is_enabled(struct clk_hw *hw)
273{ 289{
274 struct tegra_clk_pll *pll = to_clk_pll(hw); 290 struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -290,6 +306,19 @@ static void _clk_pll_enable(struct clk_hw *hw)
290 struct tegra_clk_pll *pll = to_clk_pll(hw); 306 struct tegra_clk_pll *pll = to_clk_pll(hw);
291 u32 val; 307 u32 val;
292 308
309 if (pll->params->iddq_reg) {
310 val = pll_readl(pll->params->iddq_reg, pll);
311 val &= ~BIT(pll->params->iddq_bit_idx);
312 pll_writel(val, pll->params->iddq_reg, pll);
313 udelay(2);
314 }
315
316 if (pll->params->reset_reg) {
317 val = pll_readl(pll->params->reset_reg, pll);
318 val &= ~BIT(pll->params->reset_bit_idx);
319 pll_writel(val, pll->params->reset_reg, pll);
320 }
321
293 clk_pll_enable_lock(pll); 322 clk_pll_enable_lock(pll);
294 323
295 val = pll_readl_base(pll); 324 val = pll_readl_base(pll);
@@ -321,6 +350,19 @@ static void _clk_pll_disable(struct clk_hw *hw)
321 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 350 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
322 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 351 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
323 } 352 }
353
354 if (pll->params->reset_reg) {
355 val = pll_readl(pll->params->reset_reg, pll);
356 val |= BIT(pll->params->reset_bit_idx);
357 pll_writel(val, pll->params->reset_reg, pll);
358 }
359
360 if (pll->params->iddq_reg) {
361 val = pll_readl(pll->params->iddq_reg, pll);
362 val |= BIT(pll->params->iddq_bit_idx);
363 pll_writel(val, pll->params->iddq_reg, pll);
364 udelay(2);
365 }
324} 366}
325 367
326static int clk_pll_enable(struct clk_hw *hw) 368static int clk_pll_enable(struct clk_hw *hw)
@@ -359,7 +401,7 @@ static void clk_pll_disable(struct clk_hw *hw)
359static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 401static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
360{ 402{
361 struct tegra_clk_pll *pll = to_clk_pll(hw); 403 struct tegra_clk_pll *pll = to_clk_pll(hw);
362 struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 404 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
363 405
364 if (p_tohw) { 406 if (p_tohw) {
365 while (p_tohw->pdiv) { 407 while (p_tohw->pdiv) {
@@ -372,10 +414,15 @@ static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
372 return -EINVAL; 414 return -EINVAL;
373} 415}
374 416
417int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
418{
419 return _p_div_to_hw(&pll->hw, p_div);
420}
421
375static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 422static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
376{ 423{
377 struct tegra_clk_pll *pll = to_clk_pll(hw); 424 struct tegra_clk_pll *pll = to_clk_pll(hw);
378 struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 425 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
379 426
380 if (p_tohw) { 427 if (p_tohw) {
381 while (p_tohw->pdiv) { 428 while (p_tohw->pdiv) {
@@ -395,6 +442,7 @@ static int _get_table_rate(struct clk_hw *hw,
395{ 442{
396 struct tegra_clk_pll *pll = to_clk_pll(hw); 443 struct tegra_clk_pll *pll = to_clk_pll(hw);
397 struct tegra_clk_pll_freq_table *sel; 444 struct tegra_clk_pll_freq_table *sel;
445 int p;
398 446
399 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) 447 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
400 if (sel->input_rate == parent_rate && 448 if (sel->input_rate == parent_rate &&
@@ -404,12 +452,21 @@ static int _get_table_rate(struct clk_hw *hw,
404 if (sel->input_rate == 0) 452 if (sel->input_rate == 0)
405 return -EINVAL; 453 return -EINVAL;
406 454
455 if (pll->params->pdiv_tohw) {
456 p = _p_div_to_hw(hw, sel->p);
457 if (p < 0)
458 return p;
459 } else {
460 p = ilog2(sel->p);
461 }
462
407 cfg->input_rate = sel->input_rate; 463 cfg->input_rate = sel->input_rate;
408 cfg->output_rate = sel->output_rate; 464 cfg->output_rate = sel->output_rate;
409 cfg->m = sel->m; 465 cfg->m = sel->m;
410 cfg->n = sel->n; 466 cfg->n = sel->n;
411 cfg->p = sel->p; 467 cfg->p = p;
412 cfg->cpcon = sel->cpcon; 468 cfg->cpcon = sel->cpcon;
469 cfg->sdm_data = sel->sdm_data;
413 470
414 return 0; 471 return 0;
415} 472}
@@ -439,7 +496,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
439 /* 496 /*
440 * PLL_P_OUT1 rate is not listed in PLLA table 497 * PLL_P_OUT1 rate is not listed in PLLA table
441 */ 498 */
442 cfreq = parent_rate/(parent_rate/1000000); 499 cfreq = parent_rate / (parent_rate / 1000000);
443 break; 500 break;
444 default: 501 default:
445 pr_err("%s Unexpected reference rate %lu\n", 502 pr_err("%s Unexpected reference rate %lu\n",
@@ -476,6 +533,42 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
476 return 0; 533 return 0;
477} 534}
478 535
536/*
537 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
538 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
539 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
540 * to indicate that SDM is disabled.
541 *
542 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
543 */
544static void clk_pll_set_sdm_data(struct clk_hw *hw,
545 struct tegra_clk_pll_freq_table *cfg)
546{
547 struct tegra_clk_pll *pll = to_clk_pll(hw);
548 u32 val;
549 bool enabled;
550
551 if (!pll->params->sdm_din_reg)
552 return;
553
554 if (cfg->sdm_data) {
555 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
556 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
557 pll_writel_sdm_din(val, pll);
558 }
559
560 val = pll_readl_sdm_ctrl(pll);
561 enabled = (val & sdm_en_mask(pll));
562
563 if (cfg->sdm_data == 0 && enabled)
564 val &= ~pll->params->sdm_ctrl_en_mask;
565
566 if (cfg->sdm_data != 0 && !enabled)
567 val |= pll->params->sdm_ctrl_en_mask;
568
569 pll_writel_sdm_ctrl(val, pll);
570}
571
479static void _update_pll_mnp(struct tegra_clk_pll *pll, 572static void _update_pll_mnp(struct tegra_clk_pll *pll,
480 struct tegra_clk_pll_freq_table *cfg) 573 struct tegra_clk_pll_freq_table *cfg)
481{ 574{
@@ -483,7 +576,7 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll,
483 struct tegra_clk_pll_params *params = pll->params; 576 struct tegra_clk_pll_params *params = pll->params;
484 struct div_nmp *div_nmp = params->div_nmp; 577 struct div_nmp *div_nmp = params->div_nmp;
485 578
486 if ((params->flags & TEGRA_PLLM) && 579 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
487 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 580 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
488 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 581 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
489 val = pll_override_readl(params->pmc_divp_reg, pll); 582 val = pll_override_readl(params->pmc_divp_reg, pll);
@@ -508,6 +601,8 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll,
508 (cfg->p << divp_shift(pll)); 601 (cfg->p << divp_shift(pll));
509 602
510 pll_writel_base(val, pll); 603 pll_writel_base(val, pll);
604
605 clk_pll_set_sdm_data(&pll->hw, cfg);
511 } 606 }
512} 607}
513 608
@@ -518,7 +613,7 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll,
518 struct tegra_clk_pll_params *params = pll->params; 613 struct tegra_clk_pll_params *params = pll->params;
519 struct div_nmp *div_nmp = params->div_nmp; 614 struct div_nmp *div_nmp = params->div_nmp;
520 615
521 if ((params->flags & TEGRA_PLLM) && 616 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
522 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 617 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
523 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 618 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
524 val = pll_override_readl(params->pmc_divp_reg, pll); 619 val = pll_override_readl(params->pmc_divp_reg, pll);
@@ -533,6 +628,14 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll,
533 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); 628 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
534 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); 629 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
535 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); 630 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
631
632 if (pll->params->sdm_din_reg) {
633 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
634 val = pll_readl_sdm_din(pll);
635 val &= sdm_din_mask(pll);
636 cfg->sdm_data = sdin_din_to_data(val);
637 }
638 }
536 } 639 }
537} 640}
538 641
@@ -560,16 +663,51 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
560 pll_writel_misc(val, pll); 663 pll_writel_misc(val, pll);
561} 664}
562 665
666static void pll_clk_start_ss(struct tegra_clk_pll *pll)
667{
668 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
669 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
670
671 val |= pll->params->ssc_ctrl_en_mask;
672 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
673 }
674}
675
676static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
677{
678 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
679 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
680
681 val &= ~pll->params->ssc_ctrl_en_mask;
682 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
683 }
684}
685
563static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 686static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
564 unsigned long rate) 687 unsigned long rate)
565{ 688{
566 struct tegra_clk_pll *pll = to_clk_pll(hw); 689 struct tegra_clk_pll *pll = to_clk_pll(hw);
690 struct tegra_clk_pll_freq_table old_cfg;
567 int state, ret = 0; 691 int state, ret = 0;
568 692
569 state = clk_pll_is_enabled(hw); 693 state = clk_pll_is_enabled(hw);
570 694
571 if (state) 695 _get_pll_mnp(pll, &old_cfg);
696
697 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
698 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
699 ret = pll->params->dyn_ramp(pll, cfg);
700 if (!ret)
701 return 0;
702 }
703
704 if (state) {
705 pll_clk_stop_ss(pll);
572 _clk_pll_disable(hw); 706 _clk_pll_disable(hw);
707 }
708
709 if (!pll->params->defaults_set && pll->params->set_defaults)
710 pll->params->set_defaults(pll);
573 711
574 _update_pll_mnp(pll, cfg); 712 _update_pll_mnp(pll, cfg);
575 713
@@ -579,6 +717,7 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
579 if (state) { 717 if (state) {
580 _clk_pll_enable(hw); 718 _clk_pll_enable(hw);
581 ret = clk_pll_wait_for_lock(pll); 719 ret = clk_pll_wait_for_lock(pll);
720 pll_clk_start_ss(pll);
582 } 721 }
583 722
584 return ret; 723 return ret;
@@ -603,7 +742,7 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
603 } 742 }
604 743
605 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 744 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
606 _calc_rate(hw, &cfg, rate, parent_rate)) { 745 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
607 pr_err("%s: Failed to set %s rate %lu\n", __func__, 746 pr_err("%s: Failed to set %s rate %lu\n", __func__,
608 clk_hw_get_name(hw), rate); 747 clk_hw_get_name(hw), rate);
609 WARN_ON(1); 748 WARN_ON(1);
@@ -613,8 +752,11 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
613 spin_lock_irqsave(pll->lock, flags); 752 spin_lock_irqsave(pll->lock, flags);
614 753
615 _get_pll_mnp(pll, &old_cfg); 754 _get_pll_mnp(pll, &old_cfg);
755 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
756 cfg.p = old_cfg.p;
616 757
617 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 758 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
759 old_cfg.sdm_data != cfg.sdm_data)
618 ret = _program_pll(hw, &cfg, rate); 760 ret = _program_pll(hw, &cfg, rate);
619 761
620 if (pll->lock) 762 if (pll->lock)
@@ -629,15 +771,15 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
629 struct tegra_clk_pll *pll = to_clk_pll(hw); 771 struct tegra_clk_pll *pll = to_clk_pll(hw);
630 struct tegra_clk_pll_freq_table cfg; 772 struct tegra_clk_pll_freq_table cfg;
631 773
632 if (pll->params->flags & TEGRA_PLL_FIXED) 774 if (pll->params->flags & TEGRA_PLL_FIXED) {
775 /* PLLM/MB are used for memory; we do not change rate */
776 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
777 return clk_hw_get_rate(hw);
633 return pll->params->fixed_rate; 778 return pll->params->fixed_rate;
634 779 }
635 /* PLLM is used for memory; we do not change rate */
636 if (pll->params->flags & TEGRA_PLLM)
637 return clk_hw_get_rate(hw);
638 780
639 if (_get_table_rate(hw, &cfg, rate, *prate) && 781 if (_get_table_rate(hw, &cfg, rate, *prate) &&
640 _calc_rate(hw, &cfg, rate, *prate)) 782 pll->params->calc_rate(hw, &cfg, rate, *prate))
641 return -EINVAL; 783 return -EINVAL;
642 784
643 return cfg.output_rate; 785 return cfg.output_rate;
@@ -658,6 +800,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
658 return parent_rate; 800 return parent_rate;
659 801
660 if ((pll->params->flags & TEGRA_PLL_FIXED) && 802 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
803 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
661 !(val & PLL_BASE_OVERRIDE)) { 804 !(val & PLL_BASE_OVERRIDE)) {
662 struct tegra_clk_pll_freq_table sel; 805 struct tegra_clk_pll_freq_table sel;
663 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, 806 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
@@ -671,12 +814,20 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
671 814
672 _get_pll_mnp(pll, &cfg); 815 _get_pll_mnp(pll, &cfg);
673 816
674 pdiv = _hw_to_p_div(hw, cfg.p); 817 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
675 if (pdiv < 0) {
676 WARN_ON(1);
677 pdiv = 1; 818 pdiv = 1;
819 } else {
820 pdiv = _hw_to_p_div(hw, cfg.p);
821 if (pdiv < 0) {
822 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
823 clk_hw_get_name(hw), cfg.p);
824 pdiv = 1;
825 }
678 } 826 }
679 827
828 if (pll->params->set_gain)
829 pll->params->set_gain(&cfg);
830
680 cfg.m *= pdiv; 831 cfg.m *= pdiv;
681 832
682 rate *= cfg.n; 833 rate *= cfg.n;
@@ -816,19 +967,65 @@ const struct clk_ops tegra_clk_plle_ops = {
816 .enable = clk_plle_enable, 967 .enable = clk_plle_enable,
817}; 968};
818 969
819#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
820 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
821 defined(CONFIG_ARCH_TEGRA_132_SOC)
822
823static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 970static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
824 unsigned long parent_rate) 971 unsigned long parent_rate)
825{ 972{
973 u16 mdiv = parent_rate / pll_params->cf_min;
974
975 if (pll_params->flags & TEGRA_MDIV_NEW)
976 return (!pll_params->mdiv_default ? mdiv :
977 min(mdiv, pll_params->mdiv_default));
978
979 if (pll_params->mdiv_default)
980 return pll_params->mdiv_default;
981
826 if (parent_rate > pll_params->cf_max) 982 if (parent_rate > pll_params->cf_max)
827 return 2; 983 return 2;
828 else 984 else
829 return 1; 985 return 1;
830} 986}
831 987
988static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
989 struct tegra_clk_pll_freq_table *cfg,
990 unsigned long rate, unsigned long parent_rate)
991{
992 struct tegra_clk_pll *pll = to_clk_pll(hw);
993 unsigned int p;
994 int p_div;
995
996 if (!rate)
997 return -EINVAL;
998
999 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1000 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1001 cfg->output_rate = rate * p;
1002 cfg->n = cfg->output_rate * cfg->m / parent_rate;
1003 cfg->input_rate = parent_rate;
1004
1005 p_div = _p_div_to_hw(hw, p);
1006 if (p_div < 0)
1007 return p_div;
1008
1009 cfg->p = p_div;
1010
1011 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1012 return -EINVAL;
1013
1014 return 0;
1015}
1016
1017#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1018 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1019 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1020 defined(CONFIG_ARCH_TEGRA_210_SOC)
1021
1022u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1023{
1024 struct tegra_clk_pll *pll = to_clk_pll(hw);
1025
1026 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1027}
1028
832static unsigned long _clip_vco_min(unsigned long vco_min, 1029static unsigned long _clip_vco_min(unsigned long vco_min,
833 unsigned long parent_rate) 1030 unsigned long parent_rate)
834{ 1031{
@@ -871,86 +1068,12 @@ static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
871 return 0; 1068 return 0;
872} 1069}
873 1070
874static int clk_pll_iddq_enable(struct clk_hw *hw)
875{
876 struct tegra_clk_pll *pll = to_clk_pll(hw);
877 unsigned long flags = 0;
878
879 u32 val;
880 int ret;
881
882 if (pll->lock)
883 spin_lock_irqsave(pll->lock, flags);
884
885 val = pll_readl(pll->params->iddq_reg, pll);
886 val &= ~BIT(pll->params->iddq_bit_idx);
887 pll_writel(val, pll->params->iddq_reg, pll);
888 udelay(2);
889
890 _clk_pll_enable(hw);
891
892 ret = clk_pll_wait_for_lock(pll);
893
894 if (pll->lock)
895 spin_unlock_irqrestore(pll->lock, flags);
896
897 return 0;
898}
899
900static void clk_pll_iddq_disable(struct clk_hw *hw)
901{
902 struct tegra_clk_pll *pll = to_clk_pll(hw);
903 unsigned long flags = 0;
904 u32 val;
905
906 if (pll->lock)
907 spin_lock_irqsave(pll->lock, flags);
908
909 _clk_pll_disable(hw);
910
911 val = pll_readl(pll->params->iddq_reg, pll);
912 val |= BIT(pll->params->iddq_bit_idx);
913 pll_writel(val, pll->params->iddq_reg, pll);
914 udelay(2);
915
916 if (pll->lock)
917 spin_unlock_irqrestore(pll->lock, flags);
918}
919
920static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
921 struct tegra_clk_pll_freq_table *cfg,
922 unsigned long rate, unsigned long parent_rate)
923{
924 struct tegra_clk_pll *pll = to_clk_pll(hw);
925 unsigned int p;
926 int p_div;
927
928 if (!rate)
929 return -EINVAL;
930
931 p = DIV_ROUND_UP(pll->params->vco_min, rate);
932 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
933 cfg->output_rate = rate * p;
934 cfg->n = cfg->output_rate * cfg->m / parent_rate;
935
936 p_div = _p_div_to_hw(hw, p);
937 if (p_div < 0)
938 return p_div;
939 else
940 cfg->p = p_div;
941
942 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
943 return -EINVAL;
944
945 return 0;
946}
947
948static int _pll_ramp_calc_pll(struct clk_hw *hw, 1071static int _pll_ramp_calc_pll(struct clk_hw *hw,
949 struct tegra_clk_pll_freq_table *cfg, 1072 struct tegra_clk_pll_freq_table *cfg,
950 unsigned long rate, unsigned long parent_rate) 1073 unsigned long rate, unsigned long parent_rate)
951{ 1074{
952 struct tegra_clk_pll *pll = to_clk_pll(hw); 1075 struct tegra_clk_pll *pll = to_clk_pll(hw);
953 int err = 0, p_div; 1076 int err = 0;
954 1077
955 err = _get_table_rate(hw, cfg, rate, parent_rate); 1078 err = _get_table_rate(hw, cfg, rate, parent_rate);
956 if (err < 0) 1079 if (err < 0)
@@ -961,11 +1084,6 @@ static int _pll_ramp_calc_pll(struct clk_hw *hw,
961 err = -EINVAL; 1084 err = -EINVAL;
962 goto out; 1085 goto out;
963 } 1086 }
964 p_div = _p_div_to_hw(hw, cfg->p);
965 if (p_div < 0)
966 return p_div;
967 else
968 cfg->p = p_div;
969 } 1087 }
970 1088
971 if (cfg->p > pll->params->max_p) 1089 if (cfg->p > pll->params->max_p)
@@ -991,6 +1109,8 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
991 spin_lock_irqsave(pll->lock, flags); 1109 spin_lock_irqsave(pll->lock, flags);
992 1110
993 _get_pll_mnp(pll, &old_cfg); 1111 _get_pll_mnp(pll, &old_cfg);
1112 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1113 cfg.p = old_cfg.p;
994 1114
995 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 1115 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
996 ret = _program_pll(hw, &cfg, rate); 1116 ret = _program_pll(hw, &cfg, rate);
@@ -1004,6 +1124,7 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1004static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 1124static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1005 unsigned long *prate) 1125 unsigned long *prate)
1006{ 1126{
1127 struct tegra_clk_pll *pll = to_clk_pll(hw);
1007 struct tegra_clk_pll_freq_table cfg; 1128 struct tegra_clk_pll_freq_table cfg;
1008 int ret, p_div; 1129 int ret, p_div;
1009 u64 output_rate = *prate; 1130 u64 output_rate = *prate;
@@ -1016,46 +1137,15 @@ static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1016 if (p_div < 0) 1137 if (p_div < 0)
1017 return p_div; 1138 return p_div;
1018 1139
1140 if (pll->params->set_gain)
1141 pll->params->set_gain(&cfg);
1142
1019 output_rate *= cfg.n; 1143 output_rate *= cfg.n;
1020 do_div(output_rate, cfg.m * p_div); 1144 do_div(output_rate, cfg.m * p_div);
1021 1145
1022 return output_rate; 1146 return output_rate;
1023} 1147}
1024 1148
1025static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
1026 unsigned long parent_rate)
1027{
1028 struct tegra_clk_pll_freq_table cfg;
1029 struct tegra_clk_pll *pll = to_clk_pll(hw);
1030 unsigned long flags = 0;
1031 int state, ret = 0;
1032
1033 if (pll->lock)
1034 spin_lock_irqsave(pll->lock, flags);
1035
1036 state = clk_pll_is_enabled(hw);
1037 if (state) {
1038 if (rate != clk_get_rate(hw->clk)) {
1039 pr_err("%s: Cannot change active PLLM\n", __func__);
1040 ret = -EINVAL;
1041 goto out;
1042 }
1043 goto out;
1044 }
1045
1046 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1047 if (ret < 0)
1048 goto out;
1049
1050 _update_pll_mnp(pll, &cfg);
1051
1052out:
1053 if (pll->lock)
1054 spin_unlock_irqrestore(pll->lock, flags);
1055
1056 return ret;
1057}
1058
1059static void _pllcx_strobe(struct tegra_clk_pll *pll) 1149static void _pllcx_strobe(struct tegra_clk_pll *pll)
1060{ 1150{
1061 u32 val; 1151 u32 val;
@@ -1445,6 +1535,17 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1445 init.parent_names = (parent_name ? &parent_name : NULL); 1535 init.parent_names = (parent_name ? &parent_name : NULL);
1446 init.num_parents = (parent_name ? 1 : 0); 1536 init.num_parents = (parent_name ? 1 : 0);
1447 1537
1538 /* Default to _calc_rate if unspecified */
1539 if (!pll->params->calc_rate) {
1540 if (pll->params->flags & TEGRA_PLLM)
1541 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1542 else
1543 pll->params->calc_rate = _calc_rate;
1544 }
1545
1546 if (pll->params->set_defaults)
1547 pll->params->set_defaults(pll);
1548
1448 /* Data in .init is copied by clk_register(), so stack variable OK */ 1549 /* Data in .init is copied by clk_register(), so stack variable OK */
1449 pll->hw.init = &init; 1550 pll->hw.init = &init;
1450 1551
@@ -1460,7 +1561,7 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1460 struct clk *clk; 1561 struct clk *clk;
1461 1562
1462 pll_params->flags |= TEGRA_PLL_BYPASS; 1563 pll_params->flags |= TEGRA_PLL_BYPASS;
1463 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1564
1464 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1565 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1465 if (IS_ERR(pll)) 1566 if (IS_ERR(pll))
1466 return ERR_CAST(pll); 1567 return ERR_CAST(pll);
@@ -1490,8 +1591,7 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1490 struct tegra_clk_pll *pll; 1591 struct tegra_clk_pll *pll;
1491 struct clk *clk; 1592 struct clk *clk;
1492 1593
1493 pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; 1594 pll_params->flags |= TEGRA_PLL_BYPASS;
1494 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1495 1595
1496 if (!pll_params->div_nmp) 1596 if (!pll_params->div_nmp)
1497 pll_params->div_nmp = &pll_e_nmp; 1597 pll_params->div_nmp = &pll_e_nmp;
@@ -1510,25 +1610,17 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1510 1610
1511#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1611#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1512 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1612 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1513 defined(CONFIG_ARCH_TEGRA_132_SOC) 1613 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1614 defined(CONFIG_ARCH_TEGRA_210_SOC)
1514static const struct clk_ops tegra_clk_pllxc_ops = { 1615static const struct clk_ops tegra_clk_pllxc_ops = {
1515 .is_enabled = clk_pll_is_enabled, 1616 .is_enabled = clk_pll_is_enabled,
1516 .enable = clk_pll_iddq_enable, 1617 .enable = clk_pll_enable,
1517 .disable = clk_pll_iddq_disable, 1618 .disable = clk_pll_disable,
1518 .recalc_rate = clk_pll_recalc_rate, 1619 .recalc_rate = clk_pll_recalc_rate,
1519 .round_rate = clk_pll_ramp_round_rate, 1620 .round_rate = clk_pll_ramp_round_rate,
1520 .set_rate = clk_pllxc_set_rate, 1621 .set_rate = clk_pllxc_set_rate,
1521}; 1622};
1522 1623
1523static const struct clk_ops tegra_clk_pllm_ops = {
1524 .is_enabled = clk_pll_is_enabled,
1525 .enable = clk_pll_iddq_enable,
1526 .disable = clk_pll_iddq_disable,
1527 .recalc_rate = clk_pll_recalc_rate,
1528 .round_rate = clk_pll_ramp_round_rate,
1529 .set_rate = clk_pllm_set_rate,
1530};
1531
1532static const struct clk_ops tegra_clk_pllc_ops = { 1624static const struct clk_ops tegra_clk_pllc_ops = {
1533 .is_enabled = clk_pll_is_enabled, 1625 .is_enabled = clk_pll_is_enabled,
1534 .enable = clk_pllc_enable, 1626 .enable = clk_pllc_enable,
@@ -1540,8 +1632,8 @@ static const struct clk_ops tegra_clk_pllc_ops = {
1540 1632
1541static const struct clk_ops tegra_clk_pllre_ops = { 1633static const struct clk_ops tegra_clk_pllre_ops = {
1542 .is_enabled = clk_pll_is_enabled, 1634 .is_enabled = clk_pll_is_enabled,
1543 .enable = clk_pll_iddq_enable, 1635 .enable = clk_pll_enable,
1544 .disable = clk_pll_iddq_disable, 1636 .disable = clk_pll_disable,
1545 .recalc_rate = clk_pllre_recalc_rate, 1637 .recalc_rate = clk_pllre_recalc_rate,
1546 .round_rate = clk_pllre_round_rate, 1638 .round_rate = clk_pllre_round_rate,
1547 .set_rate = clk_pllre_set_rate, 1639 .set_rate = clk_pllre_set_rate,
@@ -1564,7 +1656,6 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1564 struct tegra_clk_pll *pll; 1656 struct tegra_clk_pll *pll;
1565 struct clk *clk, *parent; 1657 struct clk *clk, *parent;
1566 unsigned long parent_rate; 1658 unsigned long parent_rate;
1567 int err;
1568 u32 val, val_iddq; 1659 u32 val, val_iddq;
1569 1660
1570 parent = __clk_lookup(parent_name); 1661 parent = __clk_lookup(parent_name);
@@ -1581,21 +1672,33 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1581 1672
1582 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1673 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1583 1674
1584 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); 1675 if (pll_params->adjust_vco)
1585 if (err) 1676 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1586 return ERR_PTR(err); 1677 parent_rate);
1587 1678
1588 val = readl_relaxed(clk_base + pll_params->base_reg); 1679 /*
1589 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1680 * If the pll has a set_defaults callback, it will take care of
1681 * configuring dynamic ramping and setting IDDQ in that path.
1682 */
1683 if (!pll_params->set_defaults) {
1684 int err;
1590 1685
1591 if (val & PLL_BASE_ENABLE) 1686 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1592 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1687 if (err)
1593 else { 1688 return ERR_PTR(err);
1594 val_iddq |= BIT(pll_params->iddq_bit_idx); 1689
1595 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1690 val = readl_relaxed(clk_base + pll_params->base_reg);
1691 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1692
1693 if (val & PLL_BASE_ENABLE)
1694 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1695 else {
1696 val_iddq |= BIT(pll_params->iddq_bit_idx);
1697 writel_relaxed(val_iddq,
1698 clk_base + pll_params->iddq_reg);
1699 }
1596 } 1700 }
1597 1701
1598 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1599 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1702 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1600 if (IS_ERR(pll)) 1703 if (IS_ERR(pll))
1601 return ERR_CAST(pll); 1704 return ERR_CAST(pll);
@@ -1618,10 +1721,12 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1618 struct tegra_clk_pll *pll; 1721 struct tegra_clk_pll *pll;
1619 struct clk *clk; 1722 struct clk *clk;
1620 1723
1621 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1622
1623 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1724 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1624 1725
1726 if (pll_params->adjust_vco)
1727 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1728 parent_rate);
1729
1625 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1730 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1626 if (IS_ERR(pll)) 1731 if (IS_ERR(pll))
1627 return ERR_CAST(pll); 1732 return ERR_CAST(pll);
@@ -1630,7 +1735,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1630 1735
1631 val = pll_readl_base(pll); 1736 val = pll_readl_base(pll);
1632 if (val & PLL_BASE_ENABLE) 1737 if (val & PLL_BASE_ENABLE)
1633 WARN_ON(val & pll_params->iddq_bit_idx); 1738 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
1739 BIT(pll_params->iddq_bit_idx));
1634 else { 1740 else {
1635 int m; 1741 int m;
1636 1742
@@ -1678,15 +1784,18 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1678 1784
1679 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); 1785 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1680 1786
1787 if (pll_params->adjust_vco)
1788 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1789 parent_rate);
1790
1681 pll_params->flags |= TEGRA_PLL_BYPASS; 1791 pll_params->flags |= TEGRA_PLL_BYPASS;
1682 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1683 pll_params->flags |= TEGRA_PLLM; 1792 pll_params->flags |= TEGRA_PLLM;
1684 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); 1793 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1685 if (IS_ERR(pll)) 1794 if (IS_ERR(pll))
1686 return ERR_CAST(pll); 1795 return ERR_CAST(pll);
1687 1796
1688 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1797 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1689 &tegra_clk_pllm_ops); 1798 &tegra_clk_pll_ops);
1690 if (IS_ERR(clk)) 1799 if (IS_ERR(clk))
1691 kfree(pll); 1800 kfree(pll);
1692 1801
@@ -1700,7 +1809,7 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1700 spinlock_t *lock) 1809 spinlock_t *lock)
1701{ 1810{
1702 struct clk *parent, *clk; 1811 struct clk *parent, *clk;
1703 struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1812 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1704 struct tegra_clk_pll *pll; 1813 struct tegra_clk_pll *pll;
1705 struct tegra_clk_pll_freq_table cfg; 1814 struct tegra_clk_pll_freq_table cfg;
1706 unsigned long parent_rate; 1815 unsigned long parent_rate;
@@ -1777,7 +1886,6 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1777 struct clk *clk; 1886 struct clk *clk;
1778 u32 val, val_aux; 1887 u32 val, val_aux;
1779 1888
1780 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1781 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1889 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1782 if (IS_ERR(pll)) 1890 if (IS_ERR(pll))
1783 return ERR_CAST(pll); 1891 return ERR_CAST(pll);
@@ -1810,8 +1918,8 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1810#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 1918#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
1811static const struct clk_ops tegra_clk_pllss_ops = { 1919static const struct clk_ops tegra_clk_pllss_ops = {
1812 .is_enabled = clk_pll_is_enabled, 1920 .is_enabled = clk_pll_is_enabled,
1813 .enable = clk_pll_iddq_enable, 1921 .enable = clk_pll_enable,
1814 .disable = clk_pll_iddq_disable, 1922 .disable = clk_pll_disable,
1815 .recalc_rate = clk_pll_recalc_rate, 1923 .recalc_rate = clk_pll_recalc_rate,
1816 .round_rate = clk_pll_ramp_round_rate, 1924 .round_rate = clk_pll_ramp_round_rate,
1817 .set_rate = clk_pllxc_set_rate, 1925 .set_rate = clk_pllxc_set_rate,
@@ -1826,7 +1934,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1826 struct clk *clk, *parent; 1934 struct clk *clk, *parent;
1827 struct tegra_clk_pll_freq_table cfg; 1935 struct tegra_clk_pll_freq_table cfg;
1828 unsigned long parent_rate; 1936 unsigned long parent_rate;
1829 u32 val; 1937 u32 val, val_iddq;
1830 int i; 1938 int i;
1831 1939
1832 if (!pll_params->div_nmp) 1940 if (!pll_params->div_nmp)
@@ -1839,7 +1947,6 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1839 return ERR_PTR(-EINVAL); 1947 return ERR_PTR(-EINVAL);
1840 } 1948 }
1841 1949
1842 pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1843 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); 1950 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1844 if (IS_ERR(pll)) 1951 if (IS_ERR(pll))
1845 return ERR_CAST(pll); 1952 return ERR_CAST(pll);
@@ -1874,6 +1981,337 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1874 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); 1981 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1875 1982
1876 val = pll_readl_base(pll); 1983 val = pll_readl_base(pll);
1984 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1985 if (val & PLL_BASE_ENABLE) {
1986 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
1987 WARN(1, "%s is on but IDDQ set\n", name);
1988 kfree(pll);
1989 return ERR_PTR(-EINVAL);
1990 }
1991 } else {
1992 val_iddq |= BIT(pll_params->iddq_bit_idx);
1993 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1994 }
1995
1996 val &= ~PLLSS_LOCK_OVERRIDE;
1997 pll_writel_base(val, pll);
1998
1999 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2000 &tegra_clk_pllss_ops);
2001
2002 if (IS_ERR(clk))
2003 kfree(pll);
2004
2005 return clk;
2006}
2007#endif
2008
2009#if defined(CONFIG_ARCH_TEGRA_210_SOC)
2010static int clk_plle_tegra210_enable(struct clk_hw *hw)
2011{
2012 struct tegra_clk_pll *pll = to_clk_pll(hw);
2013 struct tegra_clk_pll_freq_table sel;
2014 u32 val;
2015 int ret;
2016 unsigned long flags = 0;
2017 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
2018
2019 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2020 return -EINVAL;
2021
2022 if (pll->lock)
2023 spin_lock_irqsave(pll->lock, flags);
2024
2025 val = pll_readl_base(pll);
2026 val &= ~BIT(30); /* Disable lock override */
2027 pll_writel_base(val, pll);
2028
2029 val = pll_readl(pll->params->aux_reg, pll);
2030 val |= PLLE_AUX_ENABLE_SWCTL;
2031 val &= ~PLLE_AUX_SEQ_ENABLE;
2032 pll_writel(val, pll->params->aux_reg, pll);
2033 udelay(1);
2034
2035 val = pll_readl_misc(pll);
2036 val |= PLLE_MISC_LOCK_ENABLE;
2037 val |= PLLE_MISC_IDDQ_SW_CTRL;
2038 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2039 val |= PLLE_MISC_PLLE_PTS;
2040 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
2041 pll_writel_misc(val, pll);
2042 udelay(5);
2043
2044 val = pll_readl(PLLE_SS_CTRL, pll);
2045 val |= PLLE_SS_DISABLE;
2046 pll_writel(val, PLLE_SS_CTRL, pll);
2047
2048 val = pll_readl_base(pll);
2049 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2050 divm_mask_shifted(pll));
2051 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2052 val |= sel.m << divm_shift(pll);
2053 val |= sel.n << divn_shift(pll);
2054 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2055 pll_writel_base(val, pll);
2056 udelay(1);
2057
2058 val = pll_readl_base(pll);
2059 val |= PLLE_BASE_ENABLE;
2060 pll_writel_base(val, pll);
2061
2062 ret = clk_pll_wait_for_lock(pll);
2063
2064 if (ret < 0)
2065 goto out;
2066
2067 val = pll_readl(PLLE_SS_CTRL, pll);
2068 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2069 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2070 val |= PLLE_SS_COEFFICIENTS_VAL;
2071 pll_writel(val, PLLE_SS_CTRL, pll);
2072 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2073 pll_writel(val, PLLE_SS_CTRL, pll);
2074 udelay(1);
2075 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2076 pll_writel(val, PLLE_SS_CTRL, pll);
2077 udelay(1);
2078
2079 val = pll_readl_misc(pll);
2080 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2081 pll_writel_misc(val, pll);
2082
2083 val = pll_readl(pll->params->aux_reg, pll);
2084 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2085 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2086 pll_writel(val, pll->params->aux_reg, pll);
2087 udelay(1);
2088 val |= PLLE_AUX_SEQ_ENABLE;
2089 pll_writel(val, pll->params->aux_reg, pll);
2090
2091out:
2092 if (pll->lock)
2093 spin_unlock_irqrestore(pll->lock, flags);
2094
2095 return ret;
2096}
2097
2098static void clk_plle_tegra210_disable(struct clk_hw *hw)
2099{
2100 struct tegra_clk_pll *pll = to_clk_pll(hw);
2101 unsigned long flags = 0;
2102 u32 val;
2103
2104 if (pll->lock)
2105 spin_lock_irqsave(pll->lock, flags);
2106
2107 val = pll_readl_base(pll);
2108 val &= ~PLLE_BASE_ENABLE;
2109 pll_writel_base(val, pll);
2110
2111 val = pll_readl_misc(pll);
2112 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2113 pll_writel_misc(val, pll);
2114 udelay(1);
2115
2116 if (pll->lock)
2117 spin_unlock_irqrestore(pll->lock, flags);
2118}
2119
2120static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2121{
2122 struct tegra_clk_pll *pll = to_clk_pll(hw);
2123 u32 val;
2124
2125 val = pll_readl_base(pll);
2126
2127 return val & PLLE_BASE_ENABLE ? 1 : 0;
2128}
2129
2130static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2131 .is_enabled = clk_plle_tegra210_is_enabled,
2132 .enable = clk_plle_tegra210_enable,
2133 .disable = clk_plle_tegra210_disable,
2134 .recalc_rate = clk_pll_recalc_rate,
2135};
2136
2137struct clk *tegra_clk_register_plle_tegra210(const char *name,
2138 const char *parent_name,
2139 void __iomem *clk_base, unsigned long flags,
2140 struct tegra_clk_pll_params *pll_params,
2141 spinlock_t *lock)
2142{
2143 struct tegra_clk_pll *pll;
2144 struct clk *clk;
2145 u32 val, val_aux;
2146
2147 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2148 if (IS_ERR(pll))
2149 return ERR_CAST(pll);
2150
2151 /* ensure parent is set to pll_re_vco */
2152
2153 val = pll_readl_base(pll);
2154 val_aux = pll_readl(pll_params->aux_reg, pll);
2155
2156 if (val & PLLE_BASE_ENABLE) {
2157 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2158 (val_aux & PLLE_AUX_PLLP_SEL))
2159 WARN(1, "pll_e enabled with unsupported parent %s\n",
2160 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2161 "pll_re_vco");
2162 } else {
2163 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2164 pll_writel(val_aux, pll_params->aux_reg, pll);
2165 }
2166
2167 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2168 &tegra_clk_plle_tegra210_ops);
2169 if (IS_ERR(clk))
2170 kfree(pll);
2171
2172 return clk;
2173}
2174
2175struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2176 const char *parent_name, void __iomem *clk_base,
2177 void __iomem *pmc, unsigned long flags,
2178 struct tegra_clk_pll_params *pll_params,
2179 spinlock_t *lock)
2180{
2181 struct clk *parent, *clk;
2182 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2183 struct tegra_clk_pll *pll;
2184 unsigned long parent_rate;
2185
2186 if (!p_tohw)
2187 return ERR_PTR(-EINVAL);
2188
2189 parent = __clk_lookup(parent_name);
2190 if (!parent) {
2191 WARN(1, "parent clk %s of %s must be registered first\n",
2192 name, parent_name);
2193 return ERR_PTR(-EINVAL);
2194 }
2195
2196 parent_rate = clk_get_rate(parent);
2197
2198 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2199
2200 if (pll_params->adjust_vco)
2201 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2202 parent_rate);
2203
2204 pll_params->flags |= TEGRA_PLL_BYPASS;
2205 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2206 if (IS_ERR(pll))
2207 return ERR_CAST(pll);
2208
2209 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2210 &tegra_clk_pll_ops);
2211 if (IS_ERR(clk))
2212 kfree(pll);
2213
2214 return clk;
2215}
2216
2217struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
2218 const char *parent_name, void __iomem *clk_base,
2219 void __iomem *pmc, unsigned long flags,
2220 struct tegra_clk_pll_params *pll_params,
2221 spinlock_t *lock)
2222{
2223 struct tegra_clk_pll *pll;
2224 struct clk *clk, *parent;
2225 unsigned long parent_rate;
2226
2227 parent = __clk_lookup(parent_name);
2228 if (!parent) {
2229 WARN(1, "parent clk %s of %s must be registered first\n",
2230 name, parent_name);
2231 return ERR_PTR(-EINVAL);
2232 }
2233
2234 if (!pll_params->pdiv_tohw)
2235 return ERR_PTR(-EINVAL);
2236
2237 parent_rate = clk_get_rate(parent);
2238
2239 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2240
2241 if (pll_params->adjust_vco)
2242 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2243 parent_rate);
2244
2245 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2246 if (IS_ERR(pll))
2247 return ERR_CAST(pll);
2248
2249 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2250 &tegra_clk_pll_ops);
2251 if (IS_ERR(clk))
2252 kfree(pll);
2253
2254 return clk;
2255}
2256
2257struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2258 const char *parent_name, void __iomem *clk_base,
2259 unsigned long flags,
2260 struct tegra_clk_pll_params *pll_params,
2261 spinlock_t *lock)
2262{
2263 struct tegra_clk_pll *pll;
2264 struct clk *clk, *parent;
2265 struct tegra_clk_pll_freq_table cfg;
2266 unsigned long parent_rate;
2267 u32 val;
2268 int i;
2269
2270 if (!pll_params->div_nmp)
2271 return ERR_PTR(-EINVAL);
2272
2273 parent = __clk_lookup(parent_name);
2274 if (!parent) {
2275 WARN(1, "parent clk %s of %s must be registered first\n",
2276 name, parent_name);
2277 return ERR_PTR(-EINVAL);
2278 }
2279
2280 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2281 if (IS_ERR(pll))
2282 return ERR_CAST(pll);
2283
2284 val = pll_readl_base(pll);
2285 val &= ~PLLSS_REF_SRC_SEL_MASK;
2286 pll_writel_base(val, pll);
2287
2288 parent_rate = clk_get_rate(parent);
2289
2290 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2291
2292 if (pll_params->adjust_vco)
2293 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2294 parent_rate);
2295
2296 /* initialize PLL to minimum rate */
2297
2298 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2299 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2300
2301 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2302 ;
2303 if (!i) {
2304 kfree(pll);
2305 return ERR_PTR(-EINVAL);
2306 }
2307
2308 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2309
2310 _update_pll_mnp(pll, &cfg);
2311
2312 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2313
2314 val = pll_readl_base(pll);
1877 if (val & PLL_BASE_ENABLE) { 2315 if (val & PLL_BASE_ENABLE) {
1878 if (val & BIT(pll_params->iddq_bit_idx)) { 2316 if (val & BIT(pll_params->iddq_bit_idx)) {
1879 WARN(1, "%s is on but IDDQ set\n", name); 2317 WARN(1, "%s is on but IDDQ set\n", name);
@@ -1887,8 +2325,50 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1887 pll_writel_base(val, pll); 2325 pll_writel_base(val, pll);
1888 2326
1889 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 2327 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1890 &tegra_clk_pllss_ops); 2328 &tegra_clk_pll_ops);
2329
2330 if (IS_ERR(clk))
2331 kfree(pll);
2332
2333 return clk;
2334}
2335
2336struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2337 void __iomem *clk_base, void __iomem *pmc,
2338 unsigned long flags,
2339 struct tegra_clk_pll_params *pll_params,
2340 spinlock_t *lock)
2341{
2342 struct tegra_clk_pll *pll;
2343 struct clk *clk, *parent;
2344 unsigned long parent_rate;
1891 2345
2346 if (!pll_params->pdiv_tohw)
2347 return ERR_PTR(-EINVAL);
2348
2349 parent = __clk_lookup(parent_name);
2350 if (!parent) {
2351 WARN(1, "parent clk %s of %s must be registered first\n",
2352 parent_name, name);
2353 return ERR_PTR(-EINVAL);
2354 }
2355
2356 parent_rate = clk_get_rate(parent);
2357
2358 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2359
2360 if (pll_params->adjust_vco)
2361 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2362 parent_rate);
2363
2364 pll_params->flags |= TEGRA_PLL_BYPASS;
2365 pll_params->flags |= TEGRA_PLLMB;
2366 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2367 if (IS_ERR(pll))
2368 return ERR_CAST(pll);
2369
2370 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2371 &tegra_clk_pll_ops);
1892 if (IS_ERR(clk)) 2372 if (IS_ERR(clk))
1893 kfree(pll); 2373 kfree(pll);
1894 2374
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index cb6ab830941d..6ad381a888a6 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -124,6 +124,20 @@
124#define CLK_SOURCE_HDMI_AUDIO 0x668 124#define CLK_SOURCE_HDMI_AUDIO 0x668
125#define CLK_SOURCE_VIC03 0x678 125#define CLK_SOURCE_VIC03 0x678
126#define CLK_SOURCE_CLK72MHZ 0x66c 126#define CLK_SOURCE_CLK72MHZ 0x66c
127#define CLK_SOURCE_DBGAPB 0x718
128#define CLK_SOURCE_NVENC 0x6a0
129#define CLK_SOURCE_NVDEC 0x698
130#define CLK_SOURCE_NVJPG 0x69c
131#define CLK_SOURCE_APE 0x6c0
132#define CLK_SOURCE_SOR1 0x410
133#define CLK_SOURCE_SDMMC_LEGACY 0x694
134#define CLK_SOURCE_QSPI 0x6c4
135#define CLK_SOURCE_VI_I2C 0x6c8
136#define CLK_SOURCE_MIPIBIF 0x660
137#define CLK_SOURCE_UARTAPE 0x710
138#define CLK_SOURCE_TSECB 0x6d8
139#define CLK_SOURCE_MAUD 0x6d4
140#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
127 141
128#define MASK(x) (BIT(x) - 1) 142#define MASK(x) (BIT(x) - 1)
129 143
@@ -182,6 +196,13 @@
182 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\ 196 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
183 _parents##_idx, 0, NULL) 197 _parents##_idx, 0, NULL)
184 198
199#define UART8(_name, _parents, _offset,\
200 _clk_num, _clk_id) \
201 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
202 29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
203 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
204 _parents##_idx, 0, NULL)
205
185#define I2C(_name, _parents, _offset,\ 206#define I2C(_name, _parents, _offset,\
186 _clk_num, _clk_id) \ 207 _clk_num, _clk_id) \
187 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 208 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
@@ -221,8 +242,21 @@
221 .flags = _flags \ 242 .flags = _flags \
222 } 243 }
223 244
245#define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \
246 { \
247 .name = _name, \
248 .clk_id = _clk_id, \
249 .p.parent_name = _parent_name, \
250 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1, \
251 TEGRA_DIVIDER_ROUND_UP, 0, 0, \
252 NULL, NULL), \
253 .offset = _offset, \
254 .flags = _flags, \
255 }
256
224#define PLLP_BASE 0xa0 257#define PLLP_BASE 0xa0
225#define PLLP_MISC 0xac 258#define PLLP_MISC 0xac
259#define PLLP_MISC1 0x680
226#define PLLP_OUTA 0xa4 260#define PLLP_OUTA 0xa4
227#define PLLP_OUTB 0xa8 261#define PLLP_OUTB 0xa8
228#define PLLP_OUTC 0x67c 262#define PLLP_OUTC 0x67c
@@ -234,6 +268,7 @@ static DEFINE_SPINLOCK(PLLP_OUTA_lock);
234static DEFINE_SPINLOCK(PLLP_OUTB_lock); 268static DEFINE_SPINLOCK(PLLP_OUTB_lock);
235static DEFINE_SPINLOCK(PLLP_OUTC_lock); 269static DEFINE_SPINLOCK(PLLP_OUTC_lock);
236static DEFINE_SPINLOCK(sor0_lock); 270static DEFINE_SPINLOCK(sor0_lock);
271static DEFINE_SPINLOCK(sor1_lock);
237 272
238#define MUX_I2S_SPDIF(_id) \ 273#define MUX_I2S_SPDIF(_id) \
239static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 274static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
@@ -285,6 +320,68 @@ static u32 mux_pllp_clkm_idx[] = {
285 [0] = 0, [1] = 3, 320 [0] = 0, [1] = 3,
286}; 321};
287 322
323static const char *mux_pllp_clkm_2[] = {
324 "pll_p", "clk_m"
325};
326static u32 mux_pllp_clkm_2_idx[] = {
327 [0] = 2, [1] = 6,
328};
329
330static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = {
331 "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
332};
333static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = {
334 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7,
335};
336
337static const char *
338mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = {
339 "pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
340 "pll_a_out0", "pll_c4_out0"
341};
342static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = {
343 [0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
344};
345
346static const char *mux_pllc_pllp_plla[] = {
347 "pll_c", "pll_p", "pll_a_out0"
348};
349static u32 mux_pllc_pllp_plla_idx[] = {
350 [0] = 1, [1] = 2, [2] = 3,
351};
352
353static const char *mux_clkm_pllc_pllp_plla[] = {
354 "clk_m", "pll_c", "pll_p", "pll_a_out0"
355};
356#define mux_clkm_pllc_pllp_plla_idx NULL
357
358static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = {
359 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m"
360};
361static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = {
362 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6,
363};
364
365static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = {
366 "pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0",
367};
368static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = {
369 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
370};
371
372static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = {
373 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0",
374};
375#define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \
376 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx
377
378static const char *
379mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = {
380 "pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p",
381 "pll_c4_out2", "clk_m"
382};
383#define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL
384
288static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 385static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
289 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 386 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
290}; 387};
@@ -302,12 +399,93 @@ static const char *mux_pllm_pllc_pllp_plla[] = {
302#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 399#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
303 400
304static const char *mux_pllp_pllc_clkm[] = { 401static const char *mux_pllp_pllc_clkm[] = {
305 "pll_p", "pll_c", "pll_m" 402 "pll_p", "pll_c", "clk_m"
306}; 403};
307static u32 mux_pllp_pllc_clkm_idx[] = { 404static u32 mux_pllp_pllc_clkm_idx[] = {
308 [0] = 0, [1] = 1, [2] = 3, 405 [0] = 0, [1] = 1, [2] = 3,
309}; 406};
310 407
408static const char *mux_pllp_pllc_clkm_1[] = {
409 "pll_p", "pll_c", "clk_m"
410};
411static u32 mux_pllp_pllc_clkm_1_idx[] = {
412 [0] = 0, [1] = 2, [2] = 5,
413};
414
415static const char *mux_pllp_pllc_plla_clkm[] = {
416 "pll_p", "pll_c", "pll_a_out0", "clk_m"
417};
418static u32 mux_pllp_pllc_plla_clkm_idx[] = {
419 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
420};
421
422static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = {
423 "pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2"
424};
425static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = {
426 [0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7,
427};
428
429static const char *
430mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
431 "pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1",
432 "clk_m", "pll_c4_out0"
433};
434static u32
435mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
436 [0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
437};
438
439static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
440 "pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0"
441};
442static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
443 [0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
444};
445
446static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
447 "pll_p",
448 "pll_c4_out2", "pll_c4_out0", /* LJ input */
449 "pll_c4_out2", "pll_c4_out1",
450 "pll_c4_out1", /* LJ input */
451 "clk_m", "pll_c4_out0"
452};
453#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
454
455static const char *mux_pllp_pllc2_c_c3_clkm[] = {
456 "pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
457};
458static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = {
459 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6,
460};
461
462static const char *mux_pllp_clkm_clk32_plle[] = {
463 "pll_p", "clk_m", "clk_32k", "pll_e"
464};
465static u32 mux_pllp_clkm_clk32_plle_idx[] = {
466 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
467};
468
469static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = {
470 "pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
471};
472#define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL
473
474static const char *mux_pllp_out3_clkm_pllp_pllc4[] = {
475 "pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1",
476 "pll_c4_out2"
477};
478static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = {
479 [0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7,
480};
481
482static const char *mux_clkm_pllp_pllre[] = {
483 "clk_m", "pll_p_out_xusb", "pll_re_out"
484};
485static u32 mux_clkm_pllp_pllre_idx[] = {
486 [0] = 0, [1] = 1, [2] = 5,
487};
488
311static const char *mux_pllp_pllc_clkm_clk32[] = { 489static const char *mux_pllp_pllc_clkm_clk32[] = {
312 "pll_p", "pll_c", "clk_m", "clk_32k" 490 "pll_p", "pll_c", "clk_m", "clk_32k"
313}; 491};
@@ -332,6 +510,11 @@ static u32 mux_clkm_48M_pllp_480M_idx[] = {
332 [0] = 0, [1] = 2, [2] = 4, [3] = 6, 510 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
333}; 511};
334 512
513static const char *mux_clkm_pllre_clk32_480M[] = {
514 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
515};
516#define mux_clkm_pllre_clk32_480M_idx NULL
517
335static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 518static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
336 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 519 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
337}; 520};
@@ -339,10 +522,27 @@ static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
339 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 522 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
340}; 523};
341 524
342static const char *mux_ss_60M[] = { 525static const char *mux_pllp_out3_pllp_pllc_clkm[] = {
526 "pll_p_out3", "pll_p", "pll_c", "clk_m"
527};
528static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = {
529 [0] = 0, [1] = 1, [2] = 2, [3] = 6,
530};
531
532static const char *mux_ss_div2_60M[] = {
343 "xusb_ss_div2", "pll_u_60M" 533 "xusb_ss_div2", "pll_u_60M"
344}; 534};
345#define mux_ss_60M_idx NULL 535#define mux_ss_div2_60M_idx NULL
536
537static const char *mux_ss_div2_60M_ss[] = {
538 "xusb_ss_div2", "pll_u_60M", "xusb_ss_src"
539};
540#define mux_ss_div2_60M_ss_idx NULL
541
542static const char *mux_ss_clkm[] = {
543 "xusb_ss_src", "clk_m"
544};
545#define mux_ss_clkm_idx NULL
346 546
347static const char *mux_d_audio_clk[] = { 547static const char *mux_d_audio_clk[] = {
348 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 548 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
@@ -386,6 +586,32 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
386 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7, 586 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
387}; 587};
388 588
589/* SOR1 mux'es */
590static const char *mux_pllp_plld_plld2_clkm[] = {
591 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m"
592};
593static u32 mux_pllp_plld_plld2_clkm_idx[] = {
594 [0] = 0, [1] = 2, [2] = 5, [3] = 6
595};
596
597static const char *mux_plldp_sor1_src[] = {
598 "pll_dp", "clk_sor1_src"
599};
600#define mux_plldp_sor1_src_idx NULL
601
602static const char *mux_clkm_sor1_brick_sor1_src[] = {
603 "clk_m", "sor1_brick", "sor1_src", "sor1_brick"
604};
605#define mux_clkm_sor1_brick_sor1_src_idx NULL
606
607static const char *mux_pllp_pllre_clkm[] = {
608 "pll_p", "pll_re_out1", "clk_m"
609};
610
611static u32 mux_pllp_pllre_clkm_idx[] = {
612 [0] = 0, [1] = 2, [2] = 3,
613};
614
389static const char *mux_clkm_plldp_sor0lvds[] = { 615static const char *mux_clkm_plldp_sor0lvds[] = {
390 "clk_m", "pll_dp", "sor0_lvds", 616 "clk_m", "pll_dp", "sor0_lvds",
391}; 617};
@@ -401,6 +627,7 @@ static struct tegra_periph_init_data periph_clks[] = {
401 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3), 627 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
402 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4), 628 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
403 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5), 629 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
630 I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
404 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), 631 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
405 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), 632 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
406 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), 633 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
@@ -411,14 +638,19 @@ static struct tegra_periph_init_data periph_clks[] = {
411 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8), 638 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
412 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8), 639 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
413 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9), 640 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
641 INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10),
414 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8), 642 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
415 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc), 643 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
416 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec), 644 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
645 INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8),
417 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8), 646 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
647 INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),
418 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), 648 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
649 INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
419 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8), 650 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
420 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8), 651 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
421 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03), 652 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
653 INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8),
422 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED), 654 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
423 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0), 655 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
424 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1), 656 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
@@ -427,22 +659,31 @@ static struct tegra_periph_init_data periph_clks[] = {
427 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4), 659 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
428 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out), 660 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
429 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in), 661 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
662 MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8),
430 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm), 663 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
431 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx), 664 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
432 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx), 665 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
433 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), 666 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
667 MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8),
434 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), 668 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
669 MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8),
435 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), 670 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
436 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1), 671 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
437 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2), 672 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
438 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3), 673 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
439 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4), 674 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
675 MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
676 MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
677 MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
678 MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
440 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la), 679 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
441 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace), 680 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
442 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr), 681 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
682 MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8),
443 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor), 683 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
444 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi), 684 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
445 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor), 685 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
686 MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9),
446 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab), 687 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
447 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd), 688 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
448 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile), 689 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
@@ -465,10 +706,13 @@ static struct tegra_periph_init_data periph_clks[] = {
465 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash), 706 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
466 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed), 707 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
467 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob), 708 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
709 MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8),
468 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata), 710 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
711 MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8),
469 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1), 712 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
470 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1), 713 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
471 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2), 714 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
715 MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8),
472 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8), 716 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
473 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8), 717 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
474 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8), 718 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
@@ -479,6 +723,10 @@ static struct tegra_periph_init_data periph_clks[] = {
479 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8), 723 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
480 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8), 724 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
481 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8), 725 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
726 MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9),
727 MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9),
728 MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9),
729 MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9),
482 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8), 730 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
483 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8), 731 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
484 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), 732 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
@@ -486,27 +734,59 @@ static struct tegra_periph_init_data periph_clks[] = {
486 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2), 734 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
487 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3), 735 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
488 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), 736 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
737 MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
489 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), 738 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
490 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8), 739 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
740 MUX8("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_9),
491 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy), 741 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
742 MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
492 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio), 743 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
493 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz), 744 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
745 MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
494 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock), 746 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
495 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED), 747 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
748 MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
496 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL), 749 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
750 NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
497 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL), 751 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
752 NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
498 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock), 753 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
499 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta), 754 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
500 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), 755 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
501 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), 756 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
502 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), 757 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
503 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), 758 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
759 UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8),
760 UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8),
761 UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8),
762 UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8),
504 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), 763 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
764 XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8),
505 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), 765 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
766 XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8),
506 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), 767 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
507 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src), 768 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
508 NODIV("xusb_hs_src", mux_ss_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL), 769 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8),
770 NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
771 NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL),
772 NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL),
509 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), 773 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
774 XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
775 MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
776 MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
777 MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
778 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
779 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
780 MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
781 NODIV("sor1_brick", mux_plldp_sor1_src, CLK_SOURCE_SOR1, 14, MASK(1), 183, 0, tegra_clk_sor1_brick, &sor1_lock),
782 NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),
783 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
784 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
785 MUX("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, TEGRA_PERIPH_ON_APB, tegra_clk_vi_i2c),
786 MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
787 MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
788 MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
789 MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
510}; 790};
511 791
512static struct tegra_periph_init_data gate_clks[] = { 792static struct tegra_periph_init_data gate_clks[] = {
@@ -543,6 +823,16 @@ static struct tegra_periph_init_data gate_clks[] = {
543 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0), 823 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
544 GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0), 824 GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
545 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0), 825 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
826 GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
827 GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
828 GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
829 GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
830 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
831 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
832};
833
834static struct tegra_periph_init_data div_clks[] = {
835 DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0),
546}; 836};
547 837
548struct pll_out_data { 838struct pll_out_data {
@@ -633,6 +923,33 @@ static void __init gate_clk_init(void __iomem *clk_base,
633 } 923 }
634} 924}
635 925
926static void __init div_clk_init(void __iomem *clk_base,
927 struct tegra_clk *tegra_clks)
928{
929 int i;
930 struct clk *clk;
931 struct clk **dt_clk;
932
933 for (i = 0; i < ARRAY_SIZE(div_clks); i++) {
934 struct tegra_periph_init_data *data;
935
936 data = div_clks + i;
937
938 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
939 if (!dt_clk)
940 continue;
941
942 clk = tegra_clk_register_divider(data->name,
943 data->p.parent_name, clk_base + data->offset,
944 data->flags, data->periph.divider.flags,
945 data->periph.divider.shift,
946 data->periph.divider.width,
947 data->periph.divider.frac_width,
948 data->periph.divider.lock);
949 *dt_clk = clk;
950 }
951}
952
636static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, 953static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
637 struct tegra_clk *tegra_clks, 954 struct tegra_clk *tegra_clks,
638 struct tegra_clk_pll_params *pll_params) 955 struct tegra_clk_pll_params *pll_params)
@@ -669,6 +986,51 @@ static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
669 data->lock); 986 data->lock);
670 *dt_clk = clk; 987 *dt_clk = clk;
671 } 988 }
989
990 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
991 tegra_clks);
992 if (dt_clk) {
993 /*
994 * Tegra210 has control on enabling/disabling PLLP branches to
995 * CPU, register a gate clock "pll_p_out_cpu" for this gating
996 * function and parent "pll_p_out4" to it, so when we are
997 * re-parenting CPU off from "pll_p_out4" the PLLP branching to
998 * CPU can be disabled automatically.
999 */
1000 clk = tegra_clk_register_divider("pll_p_out4_div",
1001 "pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
1002 8, 1, &PLLP_OUTB_lock);
1003
1004 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
1005 if (dt_clk) {
1006 clk = tegra_clk_register_pll_out("pll_p_out4",
1007 "pll_p_out4_div", clk_base + PLLP_OUTB,
1008 17, 16, CLK_IGNORE_UNUSED |
1009 CLK_SET_RATE_PARENT, 0,
1010 &PLLP_OUTB_lock);
1011 *dt_clk = clk;
1012 }
1013 }
1014
1015 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
1016 if (dt_clk) {
1017 /* PLLP_OUT_HSIO */
1018 clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
1019 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1020 clk_base + PLLP_MISC1, 29, 0, NULL);
1021 *dt_clk = clk;
1022 }
1023
1024 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
1025 if (dt_clk) {
1026 /* PLLP_OUT_XUSB */
1027 clk = clk_register_gate(NULL, "pll_p_out_xusb",
1028 "pll_p_out_hsio", CLK_SET_RATE_PARENT |
1029 CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
1030 NULL);
1031 clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
1032 *dt_clk = clk;
1033 }
672} 1034}
673 1035
674void __init tegra_periph_clk_init(void __iomem *clk_base, 1036void __init tegra_periph_clk_init(void __iomem *clk_base,
@@ -678,4 +1040,5 @@ void __init tegra_periph_clk_init(void __iomem *clk_base,
678 init_pllp(clk_base, pmc_base, tegra_clks, pll_params); 1040 init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
679 periph_clk_init(clk_base, tegra_clks); 1041 periph_clk_init(clk_base, tegra_clks);
680 gate_clk_init(clk_base, tegra_clks); 1042 gate_clk_init(clk_base, tegra_clks);
1043 div_clk_init(clk_base, tegra_clks);
681} 1044}
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
index 5b1d723932c5..4559a20e3af6 100644
--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -34,9 +34,25 @@
34#define CCLKLP_BURST_POLICY 0x370 34#define CCLKLP_BURST_POLICY 0x370
35#define SCLK_BURST_POLICY 0x028 35#define SCLK_BURST_POLICY 0x028
36#define SYSTEM_CLK_RATE 0x030 36#define SYSTEM_CLK_RATE 0x030
37#define SCLK_DIVIDER 0x2c
37 38
38static DEFINE_SPINLOCK(sysrate_lock); 39static DEFINE_SPINLOCK(sysrate_lock);
39 40
41enum tegra_super_gen {
42 gen4 = 4,
43 gen5,
44};
45
46struct tegra_super_gen_info {
47 enum tegra_super_gen gen;
48 const char **sclk_parents;
49 const char **cclk_g_parents;
50 const char **cclk_lp_parents;
51 int num_sclk_parents;
52 int num_cclk_g_parents;
53 int num_cclk_lp_parents;
54};
55
40static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 56static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
41 "pll_p", "pll_p_out2", "unused", 57 "pll_p", "pll_p_out2", "unused",
42 "clk_32k", "pll_m_out1" }; 58 "clk_32k", "pll_m_out1" };
@@ -51,21 +67,81 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
51 "pll_p", "pll_p_out4", "unused", 67 "pll_p", "pll_p_out4", "unused",
52 "unused", "pll_x", "pll_x_out0" }; 68 "unused", "pll_x", "pll_x_out0" };
53 69
70const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
71 .gen = gen4,
72 .sclk_parents = sclk_parents,
73 .cclk_g_parents = cclk_g_parents,
74 .cclk_lp_parents = cclk_lp_parents,
75 .num_sclk_parents = ARRAY_SIZE(sclk_parents),
76 .num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents),
77 .num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents),
78};
79
80static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
81 "pll_p", "pll_p_out2", "pll_c4_out1",
82 "clk_32k", "pll_c4_out2" };
83
84static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
85 "pll_p", "pll_p_out4", "unused",
86 "unused", "pll_x", "unused", "unused",
87 "unused", "unused", "unused", "unused",
88 "dfllCPU_out" };
89
90static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
91 "pll_p", "pll_p_out4", "unused",
92 "unused", "pll_x", "unused", "unused",
93 "unused", "unused", "unused", "unused",
94 "dfllCPU_out" };
95
96const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
97 .gen = gen5,
98 .sclk_parents = sclk_parents_gen5,
99 .cclk_g_parents = cclk_g_parents_gen5,
100 .cclk_lp_parents = cclk_lp_parents_gen5,
101 .num_sclk_parents = ARRAY_SIZE(sclk_parents_gen5),
102 .num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents_gen5),
103 .num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents_gen5),
104};
105
54static void __init tegra_sclk_init(void __iomem *clk_base, 106static void __init tegra_sclk_init(void __iomem *clk_base,
55 struct tegra_clk *tegra_clks) 107 struct tegra_clk *tegra_clks,
108 const struct tegra_super_gen_info *gen_info)
56{ 109{
57 struct clk *clk; 110 struct clk *clk;
58 struct clk **dt_clk; 111 struct clk **dt_clk;
59 112
60 /* SCLK */ 113 /* SCLK_MUX */
61 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks); 114 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk_mux, tegra_clks);
62 if (dt_clk) { 115 if (dt_clk) {
63 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 116 clk = tegra_clk_register_super_mux("sclk_mux",
64 ARRAY_SIZE(sclk_parents), 117 gen_info->sclk_parents,
118 gen_info->num_sclk_parents,
65 CLK_SET_RATE_PARENT, 119 CLK_SET_RATE_PARENT,
66 clk_base + SCLK_BURST_POLICY, 120 clk_base + SCLK_BURST_POLICY,
67 0, 4, 0, 0, NULL); 121 0, 4, 0, 0, NULL);
68 *dt_clk = clk; 122 *dt_clk = clk;
123
124
125 /* SCLK */
126 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
127 if (dt_clk) {
128 clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,
129 clk_base + SCLK_DIVIDER, 0, 8,
130 0, &sysrate_lock);
131 *dt_clk = clk;
132 }
133 } else {
134 /* SCLK */
135 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
136 if (dt_clk) {
137 clk = tegra_clk_register_super_mux("sclk",
138 gen_info->sclk_parents,
139 gen_info->num_sclk_parents,
140 CLK_SET_RATE_PARENT,
141 clk_base + SCLK_BURST_POLICY,
142 0, 4, 0, 0, NULL);
143 *dt_clk = clk;
144 }
69 } 145 }
70 146
71 /* HCLK */ 147 /* HCLK */
@@ -95,10 +171,11 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
95 *dt_clk = clk; 171 *dt_clk = clk;
96} 172}
97 173
98void __init tegra_super_clk_gen4_init(void __iomem *clk_base, 174void __init tegra_super_clk_init(void __iomem *clk_base,
99 void __iomem *pmc_base, 175 void __iomem *pmc_base,
100 struct tegra_clk *tegra_clks, 176 struct tegra_clk *tegra_clks,
101 struct tegra_clk_pll_params *params) 177 struct tegra_clk_pll_params *params,
178 const struct tegra_super_gen_info *gen_info)
102{ 179{
103 struct clk *clk; 180 struct clk *clk;
104 struct clk **dt_clk; 181 struct clk **dt_clk;
@@ -106,28 +183,50 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
106 /* CCLKG */ 183 /* CCLKG */
107 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks); 184 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
108 if (dt_clk) { 185 if (dt_clk) {
109 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 186 if (gen_info->gen == gen5) {
110 ARRAY_SIZE(cclk_g_parents), 187 clk = tegra_clk_register_super_mux("cclk_g",
188 gen_info->cclk_g_parents,
189 gen_info->num_cclk_g_parents,
190 CLK_SET_RATE_PARENT,
191 clk_base + CCLKG_BURST_POLICY,
192 0, 4, 8, 0, NULL);
193 } else {
194 clk = tegra_clk_register_super_mux("cclk_g",
195 gen_info->cclk_g_parents,
196 gen_info->num_cclk_g_parents,
111 CLK_SET_RATE_PARENT, 197 CLK_SET_RATE_PARENT,
112 clk_base + CCLKG_BURST_POLICY, 198 clk_base + CCLKG_BURST_POLICY,
113 0, 4, 0, 0, NULL); 199 0, 4, 0, 0, NULL);
200 }
114 *dt_clk = clk; 201 *dt_clk = clk;
115 } 202 }
116 203
117 /* CCLKLP */ 204 /* CCLKLP */
118 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks); 205 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
119 if (dt_clk) { 206 if (dt_clk) {
120 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 207 if (gen_info->gen == gen5) {
121 ARRAY_SIZE(cclk_lp_parents), 208 clk = tegra_clk_register_super_mux("cclk_lp",
209 gen_info->cclk_lp_parents,
210 gen_info->num_cclk_lp_parents,
211 CLK_SET_RATE_PARENT,
212 clk_base + CCLKLP_BURST_POLICY,
213 0, 4, 8, 0, NULL);
214 } else {
215 clk = tegra_clk_register_super_mux("cclk_lp",
216 gen_info->cclk_lp_parents,
217 gen_info->num_cclk_lp_parents,
122 CLK_SET_RATE_PARENT, 218 CLK_SET_RATE_PARENT,
123 clk_base + CCLKLP_BURST_POLICY, 219 clk_base + CCLKLP_BURST_POLICY,
124 TEGRA_DIVIDER_2, 4, 8, 9, NULL); 220 TEGRA_DIVIDER_2, 4, 8, 9, NULL);
221 }
125 *dt_clk = clk; 222 *dt_clk = clk;
126 } 223 }
127 224
128 tegra_sclk_init(clk_base, tegra_clks); 225 tegra_sclk_init(clk_base, tegra_clks, gen_info);
129 226
130#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) 227#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
228 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
229 defined(CONFIG_ARCH_TEGRA_210_SOC)
131 /* PLLX */ 230 /* PLLX */
132 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks); 231 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
133 if (!dt_clk) 232 if (!dt_clk)
@@ -148,3 +247,20 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
148#endif 247#endif
149} 248}
150 249
250void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
251 void __iomem *pmc_base,
252 struct tegra_clk *tegra_clks,
253 struct tegra_clk_pll_params *params)
254{
255 tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
256 &tegra_super_gen_info_gen4);
257}
258
259void __init tegra_super_clk_gen5_init(void __iomem *clk_base,
260 void __iomem *pmc_base,
261 struct tegra_clk *tegra_clks,
262 struct tegra_clk_pll_params *params)
263{
264 tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
265 &tegra_super_gen_info_gen5);
266}
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index b7d03e9add97..4a24aa4bbdea 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -182,40 +182,40 @@ static struct div_nmp pllxc_nmp = {
182 .divp_width = 4, 182 .divp_width = 4,
183}; 183};
184 184
185static struct pdiv_map pllxc_p[] = { 185static const struct pdiv_map pllxc_p[] = {
186 { .pdiv = 1, .hw_val = 0 }, 186 { .pdiv = 1, .hw_val = 0 },
187 { .pdiv = 2, .hw_val = 1 }, 187 { .pdiv = 2, .hw_val = 1 },
188 { .pdiv = 3, .hw_val = 2 }, 188 { .pdiv = 3, .hw_val = 2 },
189 { .pdiv = 4, .hw_val = 3 }, 189 { .pdiv = 4, .hw_val = 3 },
190 { .pdiv = 5, .hw_val = 4 }, 190 { .pdiv = 5, .hw_val = 4 },
191 { .pdiv = 6, .hw_val = 5 }, 191 { .pdiv = 6, .hw_val = 5 },
192 { .pdiv = 8, .hw_val = 6 }, 192 { .pdiv = 8, .hw_val = 6 },
193 { .pdiv = 10, .hw_val = 7 }, 193 { .pdiv = 10, .hw_val = 7 },
194 { .pdiv = 12, .hw_val = 8 }, 194 { .pdiv = 12, .hw_val = 8 },
195 { .pdiv = 16, .hw_val = 9 }, 195 { .pdiv = 16, .hw_val = 9 },
196 { .pdiv = 12, .hw_val = 10 }, 196 { .pdiv = 12, .hw_val = 10 },
197 { .pdiv = 16, .hw_val = 11 }, 197 { .pdiv = 16, .hw_val = 11 },
198 { .pdiv = 20, .hw_val = 12 }, 198 { .pdiv = 20, .hw_val = 12 },
199 { .pdiv = 24, .hw_val = 13 }, 199 { .pdiv = 24, .hw_val = 13 },
200 { .pdiv = 32, .hw_val = 14 }, 200 { .pdiv = 32, .hw_val = 14 },
201 { .pdiv = 0, .hw_val = 0 }, 201 { .pdiv = 0, .hw_val = 0 },
202}; 202};
203 203
204static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 204static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
205 { 12000000, 624000000, 104, 0, 2}, 205 { 12000000, 624000000, 104, 1, 2, 0 },
206 { 12000000, 600000000, 100, 0, 2}, 206 { 12000000, 600000000, 100, 1, 2, 0 },
207 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 207 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
208 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 208 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
209 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 209 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
210 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 210 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
211 { 0, 0, 0, 0, 0, 0 }, 211 { 0, 0, 0, 0, 0, 0 },
212}; 212};
213 213
214static struct tegra_clk_pll_params pll_c_params = { 214static struct tegra_clk_pll_params pll_c_params = {
215 .input_min = 12000000, 215 .input_min = 12000000,
216 .input_max = 800000000, 216 .input_max = 800000000,
217 .cf_min = 12000000, 217 .cf_min = 12000000,
218 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 218 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
219 .vco_min = 600000000, 219 .vco_min = 600000000,
220 .vco_max = 1400000000, 220 .vco_max = 1400000000,
221 .base_reg = PLLC_BASE, 221 .base_reg = PLLC_BASE,
@@ -232,7 +232,7 @@ static struct tegra_clk_pll_params pll_c_params = {
232 .pdiv_tohw = pllxc_p, 232 .pdiv_tohw = pllxc_p,
233 .div_nmp = &pllxc_nmp, 233 .div_nmp = &pllxc_nmp,
234 .freq_table = pll_c_freq_table, 234 .freq_table = pll_c_freq_table,
235 .flags = TEGRA_PLL_USE_LOCK, 235 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
236}; 236};
237 237
238static struct div_nmp pllcx_nmp = { 238static struct div_nmp pllcx_nmp = {
@@ -244,22 +244,22 @@ static struct div_nmp pllcx_nmp = {
244 .divp_width = 3, 244 .divp_width = 3,
245}; 245};
246 246
247static struct pdiv_map pllc_p[] = { 247static const struct pdiv_map pllc_p[] = {
248 { .pdiv = 1, .hw_val = 0 }, 248 { .pdiv = 1, .hw_val = 0 },
249 { .pdiv = 2, .hw_val = 1 }, 249 { .pdiv = 2, .hw_val = 1 },
250 { .pdiv = 4, .hw_val = 3 }, 250 { .pdiv = 4, .hw_val = 3 },
251 { .pdiv = 8, .hw_val = 5 }, 251 { .pdiv = 8, .hw_val = 5 },
252 { .pdiv = 16, .hw_val = 7 }, 252 { .pdiv = 16, .hw_val = 7 },
253 { .pdiv = 0, .hw_val = 0 }, 253 { .pdiv = 0, .hw_val = 0 },
254}; 254};
255 255
256static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 256static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
257 {12000000, 600000000, 100, 0, 2}, 257 { 12000000, 600000000, 100, 1, 2, 0 },
258 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 258 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
259 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 259 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
260 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 260 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
261 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 261 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
262 {0, 0, 0, 0, 0, 0}, 262 { 0, 0, 0, 0, 0, 0 },
263}; 263};
264 264
265static struct tegra_clk_pll_params pll_c2_params = { 265static struct tegra_clk_pll_params pll_c2_params = {
@@ -318,26 +318,26 @@ static struct div_nmp pllm_nmp = {
318 .override_divp_shift = 27, 318 .override_divp_shift = 27,
319}; 319};
320 320
321static struct pdiv_map pllm_p[] = { 321static const struct pdiv_map pllm_p[] = {
322 { .pdiv = 1, .hw_val = 0 }, 322 { .pdiv = 1, .hw_val = 0 },
323 { .pdiv = 2, .hw_val = 1 }, 323 { .pdiv = 2, .hw_val = 1 },
324 { .pdiv = 0, .hw_val = 0 }, 324 { .pdiv = 0, .hw_val = 0 },
325}; 325};
326 326
327static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 327static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
328 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ 328 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
329 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ 329 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
330 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ 330 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
331 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ 331 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
332 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 332 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
333 {0, 0, 0, 0, 0, 0}, 333 { 0, 0, 0, 0, 0, 0 },
334}; 334};
335 335
336static struct tegra_clk_pll_params pll_m_params = { 336static struct tegra_clk_pll_params pll_m_params = {
337 .input_min = 12000000, 337 .input_min = 12000000,
338 .input_max = 500000000, 338 .input_max = 500000000,
339 .cf_min = 12000000, 339 .cf_min = 12000000,
340 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 340 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
341 .vco_min = 400000000, 341 .vco_min = 400000000,
342 .vco_max = 1066000000, 342 .vco_max = 1066000000,
343 .base_reg = PLLM_BASE, 343 .base_reg = PLLM_BASE,
@@ -351,7 +351,8 @@ static struct tegra_clk_pll_params pll_m_params = {
351 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 351 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
352 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 352 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
353 .freq_table = pll_m_freq_table, 353 .freq_table = pll_m_freq_table,
354 .flags = TEGRA_PLL_USE_LOCK, 354 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
355 TEGRA_PLL_FIXED,
355}; 356};
356 357
357static struct div_nmp pllp_nmp = { 358static struct div_nmp pllp_nmp = {
@@ -364,12 +365,12 @@ static struct div_nmp pllp_nmp = {
364}; 365};
365 366
366static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 367static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
367 {12000000, 216000000, 432, 12, 1, 8}, 368 { 12000000, 216000000, 432, 12, 2, 8 },
368 {13000000, 216000000, 432, 13, 1, 8}, 369 { 13000000, 216000000, 432, 13, 2, 8 },
369 {16800000, 216000000, 360, 14, 1, 8}, 370 { 16800000, 216000000, 360, 14, 2, 8 },
370 {19200000, 216000000, 360, 16, 1, 8}, 371 { 19200000, 216000000, 360, 16, 2, 8 },
371 {26000000, 216000000, 432, 26, 1, 8}, 372 { 26000000, 216000000, 432, 26, 2, 8 },
372 {0, 0, 0, 0, 0, 0}, 373 { 0, 0, 0, 0, 0, 0 },
373}; 374};
374 375
375static struct tegra_clk_pll_params pll_p_params = { 376static struct tegra_clk_pll_params pll_p_params = {
@@ -386,19 +387,19 @@ static struct tegra_clk_pll_params pll_p_params = {
386 .lock_delay = 300, 387 .lock_delay = 300,
387 .div_nmp = &pllp_nmp, 388 .div_nmp = &pllp_nmp,
388 .freq_table = pll_p_freq_table, 389 .freq_table = pll_p_freq_table,
389 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 390 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
391 TEGRA_PLL_HAS_LOCK_ENABLE,
390 .fixed_rate = 408000000, 392 .fixed_rate = 408000000,
391}; 393};
392 394
393static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 395static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
394 {9600000, 282240000, 147, 5, 0, 4}, 396 { 9600000, 282240000, 147, 5, 1, 4 },
395 {9600000, 368640000, 192, 5, 0, 4}, 397 { 9600000, 368640000, 192, 5, 1, 4 },
396 {9600000, 240000000, 200, 8, 0, 8}, 398 { 9600000, 240000000, 200, 8, 1, 8 },
397 399 { 28800000, 282240000, 245, 25, 1, 8 },
398 {28800000, 282240000, 245, 25, 0, 8}, 400 { 28800000, 368640000, 320, 25, 1, 8 },
399 {28800000, 368640000, 320, 25, 0, 8}, 401 { 28800000, 240000000, 200, 24, 1, 8 },
400 {28800000, 240000000, 200, 24, 0, 8}, 402 { 0, 0, 0, 0, 0, 0 },
401 {0, 0, 0, 0, 0, 0},
402}; 403};
403 404
404 405
@@ -416,28 +417,26 @@ static struct tegra_clk_pll_params pll_a_params = {
416 .lock_delay = 300, 417 .lock_delay = 300,
417 .div_nmp = &pllp_nmp, 418 .div_nmp = &pllp_nmp,
418 .freq_table = pll_a_freq_table, 419 .freq_table = pll_a_freq_table,
419 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 420 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
421 TEGRA_PLL_HAS_LOCK_ENABLE,
420}; 422};
421 423
422static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 424static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
423 {12000000, 216000000, 864, 12, 2, 12}, 425 { 12000000, 216000000, 864, 12, 4, 12 },
424 {13000000, 216000000, 864, 13, 2, 12}, 426 { 13000000, 216000000, 864, 13, 4, 12 },
425 {16800000, 216000000, 720, 14, 2, 12}, 427 { 16800000, 216000000, 720, 14, 4, 12 },
426 {19200000, 216000000, 720, 16, 2, 12}, 428 { 19200000, 216000000, 720, 16, 4, 12 },
427 {26000000, 216000000, 864, 26, 2, 12}, 429 { 26000000, 216000000, 864, 26, 4, 12 },
428 430 { 12000000, 594000000, 594, 12, 1, 12 },
429 {12000000, 594000000, 594, 12, 0, 12}, 431 { 13000000, 594000000, 594, 13, 1, 12 },
430 {13000000, 594000000, 594, 13, 0, 12}, 432 { 16800000, 594000000, 495, 14, 1, 12 },
431 {16800000, 594000000, 495, 14, 0, 12}, 433 { 19200000, 594000000, 495, 16, 1, 12 },
432 {19200000, 594000000, 495, 16, 0, 12}, 434 { 26000000, 594000000, 594, 26, 1, 12 },
433 {26000000, 594000000, 594, 26, 0, 12}, 435 { 12000000, 1000000000, 1000, 12, 1, 12 },
434 436 { 13000000, 1000000000, 1000, 13, 1, 12 },
435 {12000000, 1000000000, 1000, 12, 0, 12}, 437 { 19200000, 1000000000, 625, 12, 1, 12 },
436 {13000000, 1000000000, 1000, 13, 0, 12}, 438 { 26000000, 1000000000, 1000, 26, 1, 12 },
437 {19200000, 1000000000, 625, 12, 0, 12}, 439 { 0, 0, 0, 0, 0, 0 },
438 {26000000, 1000000000, 1000, 26, 0, 12},
439
440 {0, 0, 0, 0, 0, 0},
441}; 440};
442 441
443static struct tegra_clk_pll_params pll_d_params = { 442static struct tegra_clk_pll_params pll_d_params = {
@@ -455,7 +454,7 @@ static struct tegra_clk_pll_params pll_d_params = {
455 .div_nmp = &pllp_nmp, 454 .div_nmp = &pllp_nmp,
456 .freq_table = pll_d_freq_table, 455 .freq_table = pll_d_freq_table,
457 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 456 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
458 TEGRA_PLL_USE_LOCK, 457 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
459}; 458};
460 459
461static struct tegra_clk_pll_params pll_d2_params = { 460static struct tegra_clk_pll_params pll_d2_params = {
@@ -473,10 +472,10 @@ static struct tegra_clk_pll_params pll_d2_params = {
473 .div_nmp = &pllp_nmp, 472 .div_nmp = &pllp_nmp,
474 .freq_table = pll_d_freq_table, 473 .freq_table = pll_d_freq_table,
475 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 474 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
476 TEGRA_PLL_USE_LOCK, 475 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
477}; 476};
478 477
479static struct pdiv_map pllu_p[] = { 478static const struct pdiv_map pllu_p[] = {
480 { .pdiv = 1, .hw_val = 1 }, 479 { .pdiv = 1, .hw_val = 1 },
481 { .pdiv = 2, .hw_val = 0 }, 480 { .pdiv = 2, .hw_val = 0 },
482 { .pdiv = 0, .hw_val = 0 }, 481 { .pdiv = 0, .hw_val = 0 },
@@ -492,12 +491,12 @@ static struct div_nmp pllu_nmp = {
492}; 491};
493 492
494static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 493static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
495 {12000000, 480000000, 960, 12, 0, 12}, 494 { 12000000, 480000000, 960, 12, 2, 12 },
496 {13000000, 480000000, 960, 13, 0, 12}, 495 { 13000000, 480000000, 960, 13, 2, 12 },
497 {16800000, 480000000, 400, 7, 0, 5}, 496 { 16800000, 480000000, 400, 7, 2, 5 },
498 {19200000, 480000000, 200, 4, 0, 3}, 497 { 19200000, 480000000, 200, 4, 2, 3 },
499 {26000000, 480000000, 960, 26, 0, 12}, 498 { 26000000, 480000000, 960, 26, 2, 12 },
500 {0, 0, 0, 0, 0, 0}, 499 { 0, 0, 0, 0, 0, 0 },
501}; 500};
502 501
503static struct tegra_clk_pll_params pll_u_params = { 502static struct tegra_clk_pll_params pll_u_params = {
@@ -516,25 +515,24 @@ static struct tegra_clk_pll_params pll_u_params = {
516 .div_nmp = &pllu_nmp, 515 .div_nmp = &pllu_nmp,
517 .freq_table = pll_u_freq_table, 516 .freq_table = pll_u_freq_table,
518 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 517 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
519 TEGRA_PLL_USE_LOCK, 518 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
520}; 519};
521 520
522static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 521static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
523 /* 1 GHz */ 522 /* 1 GHz */
524 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 523 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
525 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 524 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
526 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 525 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
527 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 526 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
528 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 527 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
529 528 { 0, 0, 0, 0, 0, 0 },
530 {0, 0, 0, 0, 0, 0},
531}; 529};
532 530
533static struct tegra_clk_pll_params pll_x_params = { 531static struct tegra_clk_pll_params pll_x_params = {
534 .input_min = 12000000, 532 .input_min = 12000000,
535 .input_max = 800000000, 533 .input_max = 800000000,
536 .cf_min = 12000000, 534 .cf_min = 12000000,
537 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 535 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
538 .vco_min = 700000000, 536 .vco_min = 700000000,
539 .vco_max = 2400000000U, 537 .vco_max = 2400000000U,
540 .base_reg = PLLX_BASE, 538 .base_reg = PLLX_BASE,
@@ -551,15 +549,34 @@ static struct tegra_clk_pll_params pll_x_params = {
551 .pdiv_tohw = pllxc_p, 549 .pdiv_tohw = pllxc_p,
552 .div_nmp = &pllxc_nmp, 550 .div_nmp = &pllxc_nmp,
553 .freq_table = pll_x_freq_table, 551 .freq_table = pll_x_freq_table,
554 .flags = TEGRA_PLL_USE_LOCK, 552 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
555}; 553};
556 554
557static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 555static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
558 /* PLLE special case: use cpcon field to store cml divider value */ 556 /* PLLE special case: use cpcon field to store cml divider value */
559 {336000000, 100000000, 100, 21, 16, 11}, 557 { 336000000, 100000000, 100, 21, 16, 11 },
560 {312000000, 100000000, 200, 26, 24, 13}, 558 { 312000000, 100000000, 200, 26, 24, 13 },
561 {12000000, 100000000, 200, 1, 24, 13}, 559 { 12000000, 100000000, 200, 1, 24, 13 },
562 {0, 0, 0, 0, 0, 0}, 560 { 0, 0, 0, 0, 0, 0 },
561};
562
563static const struct pdiv_map plle_p[] = {
564 { .pdiv = 1, .hw_val = 0 },
565 { .pdiv = 2, .hw_val = 1 },
566 { .pdiv = 3, .hw_val = 2 },
567 { .pdiv = 4, .hw_val = 3 },
568 { .pdiv = 5, .hw_val = 4 },
569 { .pdiv = 6, .hw_val = 5 },
570 { .pdiv = 8, .hw_val = 6 },
571 { .pdiv = 10, .hw_val = 7 },
572 { .pdiv = 12, .hw_val = 8 },
573 { .pdiv = 16, .hw_val = 9 },
574 { .pdiv = 12, .hw_val = 10 },
575 { .pdiv = 16, .hw_val = 11 },
576 { .pdiv = 20, .hw_val = 12 },
577 { .pdiv = 24, .hw_val = 13 },
578 { .pdiv = 32, .hw_val = 14 },
579 { .pdiv = 0, .hw_val = 0 }
563}; 580};
564 581
565static struct div_nmp plle_nmp = { 582static struct div_nmp plle_nmp = {
@@ -584,9 +601,10 @@ static struct tegra_clk_pll_params pll_e_params = {
584 .lock_mask = PLLE_MISC_LOCK, 601 .lock_mask = PLLE_MISC_LOCK,
585 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 602 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
586 .lock_delay = 300, 603 .lock_delay = 300,
604 .pdiv_tohw = plle_p,
587 .div_nmp = &plle_nmp, 605 .div_nmp = &plle_nmp,
588 .freq_table = pll_e_freq_table, 606 .freq_table = pll_e_freq_table,
589 .flags = TEGRA_PLL_FIXED, 607 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
590 .fixed_rate = 100000000, 608 .fixed_rate = 100000000,
591}; 609};
592 610
@@ -614,18 +632,19 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
614 .iddq_reg = PLLRE_MISC, 632 .iddq_reg = PLLRE_MISC,
615 .iddq_bit_idx = PLLRE_IDDQ_BIT, 633 .iddq_bit_idx = PLLRE_IDDQ_BIT,
616 .div_nmp = &pllre_nmp, 634 .div_nmp = &pllre_nmp,
617 .flags = TEGRA_PLL_USE_LOCK, 635 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
636 TEGRA_PLL_LOCK_MISC,
618}; 637};
619 638
620/* possible OSC frequencies in Hz */ 639/* possible OSC frequencies in Hz */
621static unsigned long tegra114_input_freq[] = { 640static unsigned long tegra114_input_freq[] = {
622 [0] = 13000000, 641 [ 0] = 13000000,
623 [1] = 16800000, 642 [ 1] = 16800000,
624 [4] = 19200000, 643 [ 4] = 19200000,
625 [5] = 38400000, 644 [ 5] = 38400000,
626 [8] = 12000000, 645 [ 8] = 12000000,
627 [9] = 48000000, 646 [ 9] = 48000000,
628 [12] = 260000000, 647 [12] = 26000000,
629}; 648};
630 649
631#define MASK(x) (BIT(x) - 1) 650#define MASK(x) (BIT(x) - 1)
@@ -644,21 +663,27 @@ struct utmi_clk_param {
644}; 663};
645 664
646static const struct utmi_clk_param utmi_parameters[] = { 665static const struct utmi_clk_param utmi_parameters[] = {
647 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 666 {
648 .stable_count = 0x33, .active_delay_count = 0x05, 667 .osc_frequency = 13000000, .enable_delay_count = 0x02,
649 .xtal_freq_count = 0x7F}, 668 .stable_count = 0x33, .active_delay_count = 0x05,
650 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 669 .xtal_freq_count = 0x7f
651 .stable_count = 0x4B, .active_delay_count = 0x06, 670 }, {
652 .xtal_freq_count = 0xBB}, 671 .osc_frequency = 19200000, .enable_delay_count = 0x03,
653 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 672 .stable_count = 0x4b, .active_delay_count = 0x06,
654 .stable_count = 0x2F, .active_delay_count = 0x04, 673 .xtal_freq_count = 0xbb
655 .xtal_freq_count = 0x76}, 674 }, {
656 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 675 .osc_frequency = 12000000, .enable_delay_count = 0x02,
657 .stable_count = 0x66, .active_delay_count = 0x09, 676 .stable_count = 0x2f, .active_delay_count = 0x04,
658 .xtal_freq_count = 0xFE}, 677 .xtal_freq_count = 0x76
659 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 678 }, {
660 .stable_count = 0x41, .active_delay_count = 0x0A, 679 .osc_frequency = 26000000, .enable_delay_count = 0x04,
661 .xtal_freq_count = 0xA4}, 680 .stable_count = 0x66, .active_delay_count = 0x09,
681 .xtal_freq_count = 0xfe
682 }, {
683 .osc_frequency = 16800000, .enable_delay_count = 0x03,
684 .stable_count = 0x41, .active_delay_count = 0x0a,
685 .xtal_freq_count = 0xa4
686 },
662}; 687};
663 688
664/* peripheral mux definitions */ 689/* peripheral mux definitions */
@@ -965,8 +990,8 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
965 990
966static __init void tegra114_utmi_param_configure(void __iomem *clk_base) 991static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
967{ 992{
993 unsigned int i;
968 u32 reg; 994 u32 reg;
969 int i;
970 995
971 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 996 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
972 if (osc_freq == utmi_parameters[i].osc_frequency) 997 if (osc_freq == utmi_parameters[i].osc_frequency)
@@ -1173,7 +1198,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1173{ 1198{
1174 struct clk *clk; 1199 struct clk *clk;
1175 struct tegra_periph_init_data *data; 1200 struct tegra_periph_init_data *data;
1176 int i; 1201 unsigned int i;
1177 1202
1178 /* xusb_ss_div2 */ 1203 /* xusb_ss_div2 */
1179 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 1204 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
@@ -1278,7 +1303,7 @@ static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1278 1303
1279static const struct of_device_id pmc_match[] __initconst = { 1304static const struct of_device_id pmc_match[] __initconst = {
1280 { .compatible = "nvidia,tegra114-pmc" }, 1305 { .compatible = "nvidia,tegra114-pmc" },
1281 {}, 1306 { },
1282}; 1307};
1283 1308
1284/* 1309/*
@@ -1286,37 +1311,37 @@ static const struct of_device_id pmc_match[] __initconst = {
1286 * breaks 1311 * breaks
1287 */ 1312 */
1288static struct tegra_clk_init_table init_table[] __initdata = { 1313static struct tegra_clk_init_table init_table[] __initdata = {
1289 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0}, 1314 { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
1290 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0}, 1315 { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
1291 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0}, 1316 { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
1292 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0}, 1317 { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
1293 {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1}, 1318 { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
1294 {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1}, 1319 { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
1295 {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1}, 1320 { TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
1296 {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1}, 1321 { TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
1297 {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1}, 1322 { TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
1298 {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 1323 { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1299 {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 1324 { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1300 {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 1325 { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1301 {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 1326 { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1302 {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 1327 { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1303 {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, 1328 { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
1304 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, 1329 { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
1305 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, 1330 { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
1306 {TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0}, 1331 { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
1307 {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0}, 1332 { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
1308 {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, 1333 { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1309 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, 1334 { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1310 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0}, 1335 { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1311 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0}, 1336 { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1312 {TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0}, 1337 { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
1313 {TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0}, 1338 { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
1314 {TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0}, 1339 { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
1315 {TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0}, 1340 { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
1316 {TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0}, 1341 { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1317 {TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0}, 1342 { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1318 /* This MUST be the last entry. */ 1343 /* must be the last entry */
1319 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, 1344 { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1320}; 1345};
1321 1346
1322static void __init tegra114_clock_apply_init_table(void) 1347static void __init tegra114_clock_apply_init_table(void)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 87975f7adddc..1627258292d2 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -150,13 +150,13 @@ static DEFINE_SPINLOCK(emc_lock);
150 150
151/* possible OSC frequencies in Hz */ 151/* possible OSC frequencies in Hz */
152static unsigned long tegra124_input_freq[] = { 152static unsigned long tegra124_input_freq[] = {
153 [0] = 13000000, 153 [ 0] = 13000000,
154 [1] = 16800000, 154 [ 1] = 16800000,
155 [4] = 19200000, 155 [ 4] = 19200000,
156 [5] = 38400000, 156 [ 5] = 38400000,
157 [8] = 12000000, 157 [ 8] = 12000000,
158 [9] = 48000000, 158 [ 9] = 48000000,
159 [12] = 260000000, 159 [12] = 26000000,
160}; 160};
161 161
162static struct div_nmp pllxc_nmp = { 162static struct div_nmp pllxc_nmp = {
@@ -168,33 +168,33 @@ static struct div_nmp pllxc_nmp = {
168 .divp_width = 4, 168 .divp_width = 4,
169}; 169};
170 170
171static struct pdiv_map pllxc_p[] = { 171static const struct pdiv_map pllxc_p[] = {
172 { .pdiv = 1, .hw_val = 0 }, 172 { .pdiv = 1, .hw_val = 0 },
173 { .pdiv = 2, .hw_val = 1 }, 173 { .pdiv = 2, .hw_val = 1 },
174 { .pdiv = 3, .hw_val = 2 }, 174 { .pdiv = 3, .hw_val = 2 },
175 { .pdiv = 4, .hw_val = 3 }, 175 { .pdiv = 4, .hw_val = 3 },
176 { .pdiv = 5, .hw_val = 4 }, 176 { .pdiv = 5, .hw_val = 4 },
177 { .pdiv = 6, .hw_val = 5 }, 177 { .pdiv = 6, .hw_val = 5 },
178 { .pdiv = 8, .hw_val = 6 }, 178 { .pdiv = 8, .hw_val = 6 },
179 { .pdiv = 10, .hw_val = 7 }, 179 { .pdiv = 10, .hw_val = 7 },
180 { .pdiv = 12, .hw_val = 8 }, 180 { .pdiv = 12, .hw_val = 8 },
181 { .pdiv = 16, .hw_val = 9 }, 181 { .pdiv = 16, .hw_val = 9 },
182 { .pdiv = 12, .hw_val = 10 }, 182 { .pdiv = 12, .hw_val = 10 },
183 { .pdiv = 16, .hw_val = 11 }, 183 { .pdiv = 16, .hw_val = 11 },
184 { .pdiv = 20, .hw_val = 12 }, 184 { .pdiv = 20, .hw_val = 12 },
185 { .pdiv = 24, .hw_val = 13 }, 185 { .pdiv = 24, .hw_val = 13 },
186 { .pdiv = 32, .hw_val = 14 }, 186 { .pdiv = 32, .hw_val = 14 },
187 { .pdiv = 0, .hw_val = 0 }, 187 { .pdiv = 0, .hw_val = 0 },
188}; 188};
189 189
190static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 190static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
191 /* 1 GHz */ 191 /* 1 GHz */
192 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 192 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
193 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 193 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
194 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 194 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
195 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 195 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
196 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 196 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
197 {0, 0, 0, 0, 0, 0}, 197 { 0, 0, 0, 0, 0, 0 },
198}; 198};
199 199
200static struct tegra_clk_pll_params pll_x_params = { 200static struct tegra_clk_pll_params pll_x_params = {
@@ -218,24 +218,24 @@ static struct tegra_clk_pll_params pll_x_params = {
218 .pdiv_tohw = pllxc_p, 218 .pdiv_tohw = pllxc_p,
219 .div_nmp = &pllxc_nmp, 219 .div_nmp = &pllxc_nmp,
220 .freq_table = pll_x_freq_table, 220 .freq_table = pll_x_freq_table,
221 .flags = TEGRA_PLL_USE_LOCK, 221 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
222}; 222};
223 223
224static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 224static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
225 { 12000000, 624000000, 104, 1, 2}, 225 { 12000000, 624000000, 104, 1, 2, 0 },
226 { 12000000, 600000000, 100, 1, 2}, 226 { 12000000, 600000000, 100, 1, 2, 0 },
227 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 227 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
228 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ 228 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
229 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ 229 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
230 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ 230 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
231 { 0, 0, 0, 0, 0, 0 }, 231 { 0, 0, 0, 0, 0, 0 },
232}; 232};
233 233
234static struct tegra_clk_pll_params pll_c_params = { 234static struct tegra_clk_pll_params pll_c_params = {
235 .input_min = 12000000, 235 .input_min = 12000000,
236 .input_max = 800000000, 236 .input_max = 800000000,
237 .cf_min = 12000000, 237 .cf_min = 12000000,
238 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 238 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
239 .vco_min = 600000000, 239 .vco_min = 600000000,
240 .vco_max = 1400000000, 240 .vco_max = 1400000000,
241 .base_reg = PLLC_BASE, 241 .base_reg = PLLC_BASE,
@@ -252,7 +252,7 @@ static struct tegra_clk_pll_params pll_c_params = {
252 .pdiv_tohw = pllxc_p, 252 .pdiv_tohw = pllxc_p,
253 .div_nmp = &pllxc_nmp, 253 .div_nmp = &pllxc_nmp,
254 .freq_table = pll_c_freq_table, 254 .freq_table = pll_c_freq_table,
255 .flags = TEGRA_PLL_USE_LOCK, 255 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
256}; 256};
257 257
258static struct div_nmp pllcx_nmp = { 258static struct div_nmp pllcx_nmp = {
@@ -264,25 +264,25 @@ static struct div_nmp pllcx_nmp = {
264 .divp_width = 3, 264 .divp_width = 3,
265}; 265};
266 266
267static struct pdiv_map pllc_p[] = { 267static const struct pdiv_map pllc_p[] = {
268 { .pdiv = 1, .hw_val = 0 }, 268 { .pdiv = 1, .hw_val = 0 },
269 { .pdiv = 2, .hw_val = 1 }, 269 { .pdiv = 2, .hw_val = 1 },
270 { .pdiv = 3, .hw_val = 2 }, 270 { .pdiv = 3, .hw_val = 2 },
271 { .pdiv = 4, .hw_val = 3 }, 271 { .pdiv = 4, .hw_val = 3 },
272 { .pdiv = 6, .hw_val = 4 }, 272 { .pdiv = 6, .hw_val = 4 },
273 { .pdiv = 8, .hw_val = 5 }, 273 { .pdiv = 8, .hw_val = 5 },
274 { .pdiv = 12, .hw_val = 6 }, 274 { .pdiv = 12, .hw_val = 6 },
275 { .pdiv = 16, .hw_val = 7 }, 275 { .pdiv = 16, .hw_val = 7 },
276 { .pdiv = 0, .hw_val = 0 }, 276 { .pdiv = 0, .hw_val = 0 },
277}; 277};
278 278
279static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 279static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
280 {12000000, 600000000, 100, 1, 2}, 280 { 12000000, 600000000, 100, 1, 2, 0 },
281 {13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 281 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
282 {16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ 282 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
283 {19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ 283 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
284 {26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ 284 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
285 {0, 0, 0, 0, 0, 0}, 285 { 0, 0, 0, 0, 0, 0 },
286}; 286};
287 287
288static struct tegra_clk_pll_params pll_c2_params = { 288static struct tegra_clk_pll_params pll_c2_params = {
@@ -338,32 +338,32 @@ static struct div_nmp pllss_nmp = {
338 .divp_width = 4, 338 .divp_width = 4,
339}; 339};
340 340
341static struct pdiv_map pll12g_ssd_esd_p[] = { 341static const struct pdiv_map pll12g_ssd_esd_p[] = {
342 { .pdiv = 1, .hw_val = 0 }, 342 { .pdiv = 1, .hw_val = 0 },
343 { .pdiv = 2, .hw_val = 1 }, 343 { .pdiv = 2, .hw_val = 1 },
344 { .pdiv = 3, .hw_val = 2 }, 344 { .pdiv = 3, .hw_val = 2 },
345 { .pdiv = 4, .hw_val = 3 }, 345 { .pdiv = 4, .hw_val = 3 },
346 { .pdiv = 5, .hw_val = 4 }, 346 { .pdiv = 5, .hw_val = 4 },
347 { .pdiv = 6, .hw_val = 5 }, 347 { .pdiv = 6, .hw_val = 5 },
348 { .pdiv = 8, .hw_val = 6 }, 348 { .pdiv = 8, .hw_val = 6 },
349 { .pdiv = 10, .hw_val = 7 }, 349 { .pdiv = 10, .hw_val = 7 },
350 { .pdiv = 12, .hw_val = 8 }, 350 { .pdiv = 12, .hw_val = 8 },
351 { .pdiv = 16, .hw_val = 9 }, 351 { .pdiv = 16, .hw_val = 9 },
352 { .pdiv = 12, .hw_val = 10 }, 352 { .pdiv = 12, .hw_val = 10 },
353 { .pdiv = 16, .hw_val = 11 }, 353 { .pdiv = 16, .hw_val = 11 },
354 { .pdiv = 20, .hw_val = 12 }, 354 { .pdiv = 20, .hw_val = 12 },
355 { .pdiv = 24, .hw_val = 13 }, 355 { .pdiv = 24, .hw_val = 13 },
356 { .pdiv = 32, .hw_val = 14 }, 356 { .pdiv = 32, .hw_val = 14 },
357 { .pdiv = 0, .hw_val = 0 }, 357 { .pdiv = 0, .hw_val = 0 },
358}; 358};
359 359
360static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = { 360static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
361 { 12000000, 600000000, 100, 1, 1}, 361 { 12000000, 600000000, 100, 1, 2, 0 },
362 { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */ 362 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
363 { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */ 363 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
364 { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */ 364 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
365 { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */ 365 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
366 { 0, 0, 0, 0, 0, 0 }, 366 { 0, 0, 0, 0, 0, 0 },
367}; 367};
368 368
369static struct tegra_clk_pll_params pll_c4_params = { 369static struct tegra_clk_pll_params pll_c4_params = {
@@ -386,21 +386,35 @@ static struct tegra_clk_pll_params pll_c4_params = {
386 .ext_misc_reg[1] = 0x5b0, 386 .ext_misc_reg[1] = 0x5b0,
387 .ext_misc_reg[2] = 0x5b4, 387 .ext_misc_reg[2] = 0x5b4,
388 .freq_table = pll_c4_freq_table, 388 .freq_table = pll_c4_freq_table,
389 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
389}; 390};
390 391
391static struct pdiv_map pllm_p[] = { 392static const struct pdiv_map pllm_p[] = {
392 { .pdiv = 1, .hw_val = 0 }, 393 { .pdiv = 1, .hw_val = 0 },
393 { .pdiv = 2, .hw_val = 1 }, 394 { .pdiv = 2, .hw_val = 1 },
394 { .pdiv = 0, .hw_val = 0 }, 395 { .pdiv = 3, .hw_val = 2 },
396 { .pdiv = 4, .hw_val = 3 },
397 { .pdiv = 5, .hw_val = 4 },
398 { .pdiv = 6, .hw_val = 5 },
399 { .pdiv = 8, .hw_val = 6 },
400 { .pdiv = 10, .hw_val = 7 },
401 { .pdiv = 12, .hw_val = 8 },
402 { .pdiv = 16, .hw_val = 9 },
403 { .pdiv = 12, .hw_val = 10 },
404 { .pdiv = 16, .hw_val = 11 },
405 { .pdiv = 20, .hw_val = 12 },
406 { .pdiv = 24, .hw_val = 13 },
407 { .pdiv = 32, .hw_val = 14 },
408 { .pdiv = 0, .hw_val = 0 },
395}; 409};
396 410
397static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 411static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
398 {12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */ 412 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
399 {13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 413 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
400 {16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */ 414 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
401 {19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */ 415 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
402 {26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */ 416 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
403 {0, 0, 0, 0, 0, 0}, 417 { 0, 0, 0, 0, 0, 0},
404}; 418};
405 419
406static struct div_nmp pllm_nmp = { 420static struct div_nmp pllm_nmp = {
@@ -427,22 +441,41 @@ static struct tegra_clk_pll_params pll_m_params = {
427 .lock_mask = PLL_BASE_LOCK, 441 .lock_mask = PLL_BASE_LOCK,
428 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 442 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
429 .lock_delay = 300, 443 .lock_delay = 300,
430 .max_p = 2, 444 .max_p = 5,
431 .pdiv_tohw = pllm_p, 445 .pdiv_tohw = pllm_p,
432 .div_nmp = &pllm_nmp, 446 .div_nmp = &pllm_nmp,
433 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 447 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
434 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 448 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
435 .freq_table = pll_m_freq_table, 449 .freq_table = pll_m_freq_table,
436 .flags = TEGRA_PLL_USE_LOCK, 450 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
437}; 451};
438 452
439static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 453static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
440 /* PLLE special case: use cpcon field to store cml divider value */ 454 /* PLLE special case: use cpcon field to store cml divider value */
441 {336000000, 100000000, 100, 21, 16, 11}, 455 { 336000000, 100000000, 100, 21, 16, 11 },
442 {312000000, 100000000, 200, 26, 24, 13}, 456 { 312000000, 100000000, 200, 26, 24, 13 },
443 {13000000, 100000000, 200, 1, 26, 13}, 457 { 13000000, 100000000, 200, 1, 26, 13 },
444 {12000000, 100000000, 200, 1, 24, 13}, 458 { 12000000, 100000000, 200, 1, 24, 13 },
445 {0, 0, 0, 0, 0, 0}, 459 { 0, 0, 0, 0, 0, 0 },
460};
461
462static const struct pdiv_map plle_p[] = {
463 { .pdiv = 1, .hw_val = 0 },
464 { .pdiv = 2, .hw_val = 1 },
465 { .pdiv = 3, .hw_val = 2 },
466 { .pdiv = 4, .hw_val = 3 },
467 { .pdiv = 5, .hw_val = 4 },
468 { .pdiv = 6, .hw_val = 5 },
469 { .pdiv = 8, .hw_val = 6 },
470 { .pdiv = 10, .hw_val = 7 },
471 { .pdiv = 12, .hw_val = 8 },
472 { .pdiv = 16, .hw_val = 9 },
473 { .pdiv = 12, .hw_val = 10 },
474 { .pdiv = 16, .hw_val = 11 },
475 { .pdiv = 20, .hw_val = 12 },
476 { .pdiv = 24, .hw_val = 13 },
477 { .pdiv = 32, .hw_val = 14 },
478 { .pdiv = 1, .hw_val = 0 },
446}; 479};
447 480
448static struct div_nmp plle_nmp = { 481static struct div_nmp plle_nmp = {
@@ -467,9 +500,10 @@ static struct tegra_clk_pll_params pll_e_params = {
467 .lock_mask = PLLE_MISC_LOCK, 500 .lock_mask = PLLE_MISC_LOCK,
468 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 501 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
469 .lock_delay = 300, 502 .lock_delay = 300,
503 .pdiv_tohw = plle_p,
470 .div_nmp = &plle_nmp, 504 .div_nmp = &plle_nmp,
471 .freq_table = pll_e_freq_table, 505 .freq_table = pll_e_freq_table,
472 .flags = TEGRA_PLL_FIXED, 506 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
473 .fixed_rate = 100000000, 507 .fixed_rate = 100000000,
474}; 508};
475 509
@@ -507,7 +541,8 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
507 .iddq_reg = PLLRE_MISC, 541 .iddq_reg = PLLRE_MISC,
508 .iddq_bit_idx = PLLRE_IDDQ_BIT, 542 .iddq_bit_idx = PLLRE_IDDQ_BIT,
509 .div_nmp = &pllre_nmp, 543 .div_nmp = &pllre_nmp,
510 .flags = TEGRA_PLL_USE_LOCK, 544 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
545 TEGRA_PLL_LOCK_MISC,
511}; 546};
512 547
513static struct div_nmp pllp_nmp = { 548static struct div_nmp pllp_nmp = {
@@ -520,12 +555,12 @@ static struct div_nmp pllp_nmp = {
520}; 555};
521 556
522static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 557static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
523 {12000000, 408000000, 408, 12, 0, 8}, 558 { 12000000, 408000000, 408, 12, 1, 8 },
524 {13000000, 408000000, 408, 13, 0, 8}, 559 { 13000000, 408000000, 408, 13, 1, 8 },
525 {16800000, 408000000, 340, 14, 0, 8}, 560 { 16800000, 408000000, 340, 14, 1, 8 },
526 {19200000, 408000000, 340, 16, 0, 8}, 561 { 19200000, 408000000, 340, 16, 1, 8 },
527 {26000000, 408000000, 408, 26, 0, 8}, 562 { 26000000, 408000000, 408, 26, 1, 8 },
528 {0, 0, 0, 0, 0, 0}, 563 { 0, 0, 0, 0, 0, 0 },
529}; 564};
530 565
531static struct tegra_clk_pll_params pll_p_params = { 566static struct tegra_clk_pll_params pll_p_params = {
@@ -543,18 +578,18 @@ static struct tegra_clk_pll_params pll_p_params = {
543 .div_nmp = &pllp_nmp, 578 .div_nmp = &pllp_nmp,
544 .freq_table = pll_p_freq_table, 579 .freq_table = pll_p_freq_table,
545 .fixed_rate = 408000000, 580 .fixed_rate = 408000000,
546 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 581 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
582 TEGRA_PLL_HAS_LOCK_ENABLE,
547}; 583};
548 584
549static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 585static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
550 {9600000, 282240000, 147, 5, 0, 4}, 586 { 9600000, 282240000, 147, 5, 1, 4 },
551 {9600000, 368640000, 192, 5, 0, 4}, 587 { 9600000, 368640000, 192, 5, 1, 4 },
552 {9600000, 240000000, 200, 8, 0, 8}, 588 { 9600000, 240000000, 200, 8, 1, 8 },
553 589 { 28800000, 282240000, 245, 25, 1, 8 },
554 {28800000, 282240000, 245, 25, 0, 8}, 590 { 28800000, 368640000, 320, 25, 1, 8 },
555 {28800000, 368640000, 320, 25, 0, 8}, 591 { 28800000, 240000000, 200, 24, 1, 8 },
556 {28800000, 240000000, 200, 24, 0, 8}, 592 { 0, 0, 0, 0, 0, 0 },
557 {0, 0, 0, 0, 0, 0},
558}; 593};
559 594
560static struct tegra_clk_pll_params pll_a_params = { 595static struct tegra_clk_pll_params pll_a_params = {
@@ -571,7 +606,8 @@ static struct tegra_clk_pll_params pll_a_params = {
571 .lock_delay = 300, 606 .lock_delay = 300,
572 .div_nmp = &pllp_nmp, 607 .div_nmp = &pllp_nmp,
573 .freq_table = pll_a_freq_table, 608 .freq_table = pll_a_freq_table,
574 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 609 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
610 TEGRA_PLL_HAS_LOCK_ENABLE,
575}; 611};
576 612
577static struct div_nmp plld_nmp = { 613static struct div_nmp plld_nmp = {
@@ -584,24 +620,21 @@ static struct div_nmp plld_nmp = {
584}; 620};
585 621
586static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 622static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
587 {12000000, 216000000, 864, 12, 4, 12}, 623 { 12000000, 216000000, 864, 12, 4, 12 },
588 {13000000, 216000000, 864, 13, 4, 12}, 624 { 13000000, 216000000, 864, 13, 4, 12 },
589 {16800000, 216000000, 720, 14, 4, 12}, 625 { 16800000, 216000000, 720, 14, 4, 12 },
590 {19200000, 216000000, 720, 16, 4, 12}, 626 { 19200000, 216000000, 720, 16, 4, 12 },
591 {26000000, 216000000, 864, 26, 4, 12}, 627 { 26000000, 216000000, 864, 26, 4, 12 },
592 628 { 12000000, 594000000, 594, 12, 1, 12 },
593 {12000000, 594000000, 594, 12, 1, 12}, 629 { 13000000, 594000000, 594, 13, 1, 12 },
594 {13000000, 594000000, 594, 13, 1, 12}, 630 { 16800000, 594000000, 495, 14, 1, 12 },
595 {16800000, 594000000, 495, 14, 1, 12}, 631 { 19200000, 594000000, 495, 16, 1, 12 },
596 {19200000, 594000000, 495, 16, 1, 12}, 632 { 26000000, 594000000, 594, 26, 1, 12 },
597 {26000000, 594000000, 594, 26, 1, 12}, 633 { 12000000, 1000000000, 1000, 12, 1, 12 },
598 634 { 13000000, 1000000000, 1000, 13, 1, 12 },
599 {12000000, 1000000000, 1000, 12, 1, 12}, 635 { 19200000, 1000000000, 625, 12, 1, 12 },
600 {13000000, 1000000000, 1000, 13, 1, 12}, 636 { 26000000, 1000000000, 1000, 26, 1, 12 },
601 {19200000, 1000000000, 625, 12, 1, 12}, 637 { 0, 0, 0, 0, 0, 0 },
602 {26000000, 1000000000, 1000, 26, 1, 12},
603
604 {0, 0, 0, 0, 0, 0},
605}; 638};
606 639
607static struct tegra_clk_pll_params pll_d_params = { 640static struct tegra_clk_pll_params pll_d_params = {
@@ -619,16 +652,16 @@ static struct tegra_clk_pll_params pll_d_params = {
619 .div_nmp = &plld_nmp, 652 .div_nmp = &plld_nmp,
620 .freq_table = pll_d_freq_table, 653 .freq_table = pll_d_freq_table,
621 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 654 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
622 TEGRA_PLL_USE_LOCK, 655 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
623}; 656};
624 657
625static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = { 658static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
626 { 12000000, 594000000, 99, 1, 2}, 659 { 12000000, 594000000, 99, 1, 2, 0 },
627 { 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */ 660 { 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */
628 { 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */ 661 { 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
629 { 19200000, 594000000, 62, 1, 2}, /* actual: 595.2 MHz */ 662 { 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
630 { 26000000, 594000000, 91, 2, 2}, /* actual: 591.5 MHz */ 663 { 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */
631 { 0, 0, 0, 0, 0, 0 }, 664 { 0, 0, 0, 0, 0, 0 },
632}; 665};
633 666
634static struct tegra_clk_pll_params tegra124_pll_d2_params = { 667static struct tegra_clk_pll_params tegra124_pll_d2_params = {
@@ -652,15 +685,16 @@ static struct tegra_clk_pll_params tegra124_pll_d2_params = {
652 .ext_misc_reg[2] = 0x578, 685 .ext_misc_reg[2] = 0x578,
653 .max_p = 15, 686 .max_p = 15,
654 .freq_table = tegra124_pll_d2_freq_table, 687 .freq_table = tegra124_pll_d2_freq_table,
688 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
655}; 689};
656 690
657static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { 691static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
658 { 12000000, 600000000, 100, 1, 1}, 692 { 12000000, 600000000, 100, 1, 2, 0 },
659 { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */ 693 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
660 { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */ 694 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
661 { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */ 695 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
662 { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */ 696 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
663 { 0, 0, 0, 0, 0, 0 }, 697 { 0, 0, 0, 0, 0, 0 },
664}; 698};
665 699
666static struct tegra_clk_pll_params pll_dp_params = { 700static struct tegra_clk_pll_params pll_dp_params = {
@@ -684,9 +718,10 @@ static struct tegra_clk_pll_params pll_dp_params = {
684 .ext_misc_reg[2] = 0x5a0, 718 .ext_misc_reg[2] = 0x5a0,
685 .max_p = 5, 719 .max_p = 5,
686 .freq_table = pll_dp_freq_table, 720 .freq_table = pll_dp_freq_table,
721 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
687}; 722};
688 723
689static struct pdiv_map pllu_p[] = { 724static const struct pdiv_map pllu_p[] = {
690 { .pdiv = 1, .hw_val = 1 }, 725 { .pdiv = 1, .hw_val = 1 },
691 { .pdiv = 2, .hw_val = 0 }, 726 { .pdiv = 2, .hw_val = 0 },
692 { .pdiv = 0, .hw_val = 0 }, 727 { .pdiv = 0, .hw_val = 0 },
@@ -702,12 +737,12 @@ static struct div_nmp pllu_nmp = {
702}; 737};
703 738
704static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 739static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
705 {12000000, 480000000, 960, 12, 2, 12}, 740 { 12000000, 480000000, 960, 12, 2, 12 },
706 {13000000, 480000000, 960, 13, 2, 12}, 741 { 13000000, 480000000, 960, 13, 2, 12 },
707 {16800000, 480000000, 400, 7, 2, 5}, 742 { 16800000, 480000000, 400, 7, 2, 5 },
708 {19200000, 480000000, 200, 4, 2, 3}, 743 { 19200000, 480000000, 200, 4, 2, 3 },
709 {26000000, 480000000, 960, 26, 2, 12}, 744 { 26000000, 480000000, 960, 26, 2, 12 },
710 {0, 0, 0, 0, 0, 0}, 745 { 0, 0, 0, 0, 0, 0 },
711}; 746};
712 747
713static struct tegra_clk_pll_params pll_u_params = { 748static struct tegra_clk_pll_params pll_u_params = {
@@ -726,7 +761,7 @@ static struct tegra_clk_pll_params pll_u_params = {
726 .div_nmp = &pllu_nmp, 761 .div_nmp = &pllu_nmp,
727 .freq_table = pll_u_freq_table, 762 .freq_table = pll_u_freq_table,
728 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 763 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
729 TEGRA_PLL_USE_LOCK, 764 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
730}; 765};
731 766
732struct utmi_clk_param { 767struct utmi_clk_param {
@@ -743,21 +778,27 @@ struct utmi_clk_param {
743}; 778};
744 779
745static const struct utmi_clk_param utmi_parameters[] = { 780static const struct utmi_clk_param utmi_parameters[] = {
746 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 781 {
747 .stable_count = 0x33, .active_delay_count = 0x05, 782 .osc_frequency = 13000000, .enable_delay_count = 0x02,
748 .xtal_freq_count = 0x7F}, 783 .stable_count = 0x33, .active_delay_count = 0x05,
749 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 784 .xtal_freq_count = 0x7f
750 .stable_count = 0x4B, .active_delay_count = 0x06, 785 }, {
751 .xtal_freq_count = 0xBB}, 786 .osc_frequency = 19200000, .enable_delay_count = 0x03,
752 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 787 .stable_count = 0x4b, .active_delay_count = 0x06,
753 .stable_count = 0x2F, .active_delay_count = 0x04, 788 .xtal_freq_count = 0xbb
754 .xtal_freq_count = 0x76}, 789 }, {
755 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 790 .osc_frequency = 12000000, .enable_delay_count = 0x02,
756 .stable_count = 0x66, .active_delay_count = 0x09, 791 .stable_count = 0x2f, .active_delay_count = 0x04,
757 .xtal_freq_count = 0xFE}, 792 .xtal_freq_count = 0x76
758 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 793 }, {
759 .stable_count = 0x41, .active_delay_count = 0x0A, 794 .osc_frequency = 26000000, .enable_delay_count = 0x04,
760 .xtal_freq_count = 0xA4}, 795 .stable_count = 0x66, .active_delay_count = 0x09,
796 .xtal_freq_count = 0xfe
797 }, {
798 .osc_frequency = 16800000, .enable_delay_count = 0x03,
799 .stable_count = 0x41, .active_delay_count = 0x0a,
800 .xtal_freq_count = 0xa4
801 },
761}; 802};
762 803
763static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 804static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
@@ -1024,8 +1065,8 @@ static struct clk **clks;
1024 1065
1025static void tegra124_utmi_param_configure(void __iomem *clk_base) 1066static void tegra124_utmi_param_configure(void __iomem *clk_base)
1026{ 1067{
1068 unsigned int i;
1027 u32 reg; 1069 u32 reg;
1028 int i;
1029 1070
1030 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1071 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1031 if (osc_freq == utmi_parameters[i].osc_frequency) 1072 if (osc_freq == utmi_parameters[i].osc_frequency)
@@ -1356,65 +1397,65 @@ static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1356 1397
1357static const struct of_device_id pmc_match[] __initconst = { 1398static const struct of_device_id pmc_match[] __initconst = {
1358 { .compatible = "nvidia,tegra124-pmc" }, 1399 { .compatible = "nvidia,tegra124-pmc" },
1359 {}, 1400 { },
1360}; 1401};
1361 1402
1362static struct tegra_clk_init_table common_init_table[] __initdata = { 1403static struct tegra_clk_init_table common_init_table[] __initdata = {
1363 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0}, 1404 { TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 },
1364 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0}, 1405 { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
1365 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0}, 1406 { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
1366 {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0}, 1407 { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
1367 {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1}, 1408 { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
1368 {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1}, 1409 { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
1369 {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1}, 1410 { TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
1370 {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1}, 1411 { TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
1371 {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1}, 1412 { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
1372 {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1413 { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1373 {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1414 { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1374 {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1415 { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1375 {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1416 { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1376 {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1417 { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1377 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0}, 1418 { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0 },
1378 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1}, 1419 { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
1379 {TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0}, 1420 { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
1380 {TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0}, 1421 { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
1381 {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1}, 1422 { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },
1382 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1}, 1423 { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
1383 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1}, 1424 { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
1384 {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0}, 1425 { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
1385 {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0}, 1426 { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },
1386 {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1}, 1427 { TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },
1387 {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0}, 1428 { TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 },
1388 {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0}, 1429 { TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 },
1389 {TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0}, 1430 { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },
1390 {TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0}, 1431 { TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 },
1391 {TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0}, 1432 { TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 },
1392 {TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0}, 1433 { TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 },
1393 {TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0}, 1434 { TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 },
1394 {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0}, 1435 { TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 },
1395 {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0}, 1436 { TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 },
1396 {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0}, 1437 { TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 },
1397 {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1}, 1438 { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
1398 {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1}, 1439 { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
1399 {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0}, 1440 { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
1400 /* This MUST be the last entry. */ 1441 /* must be the last entry */
1401 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1442 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1402}; 1443};
1403 1444
1404static struct tegra_clk_init_table tegra124_init_table[] __initdata = { 1445static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1405 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0}, 1446 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },
1406 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1}, 1447 { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
1407 {TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0}, 1448 { TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },
1408 {TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0}, 1449 { TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },
1409 /* This MUST be the last entry. */ 1450 /* must be the last entry */
1410 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1451 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1411}; 1452};
1412 1453
1413/* Tegra132 requires the SOC_THERM clock to remain active */ 1454/* Tegra132 requires the SOC_THERM clock to remain active */
1414static struct tegra_clk_init_table tegra132_init_table[] __initdata = { 1455static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1415 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1}, 1456 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },
1416 /* This MUST be the last entry. */ 1457 /* must be the last entry */
1417 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1458 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1418}; 1459};
1419 1460
1420static struct tegra_audio_clk_info tegra124_audio_plls[] = { 1461static struct tegra_audio_clk_info tegra124_audio_plls[] = {
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bf004f0e4f65..7a48e986c4c9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -166,126 +166,120 @@ static DEFINE_SPINLOCK(emc_lock);
166static struct clk **clks; 166static struct clk **clks;
167 167
168static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 168static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
169 { 12000000, 600000000, 600, 12, 0, 8 }, 169 { 12000000, 600000000, 600, 12, 1, 8 },
170 { 13000000, 600000000, 600, 13, 0, 8 }, 170 { 13000000, 600000000, 600, 13, 1, 8 },
171 { 19200000, 600000000, 500, 16, 0, 6 }, 171 { 19200000, 600000000, 500, 16, 1, 6 },
172 { 26000000, 600000000, 600, 26, 0, 8 }, 172 { 26000000, 600000000, 600, 26, 1, 8 },
173 { 0, 0, 0, 0, 0, 0 }, 173 { 0, 0, 0, 0, 0, 0 },
174}; 174};
175 175
176static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 176static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
177 { 12000000, 666000000, 666, 12, 0, 8}, 177 { 12000000, 666000000, 666, 12, 1, 8 },
178 { 13000000, 666000000, 666, 13, 0, 8}, 178 { 13000000, 666000000, 666, 13, 1, 8 },
179 { 19200000, 666000000, 555, 16, 0, 8}, 179 { 19200000, 666000000, 555, 16, 1, 8 },
180 { 26000000, 666000000, 666, 26, 0, 8}, 180 { 26000000, 666000000, 666, 26, 1, 8 },
181 { 12000000, 600000000, 600, 12, 0, 8}, 181 { 12000000, 600000000, 600, 12, 1, 8 },
182 { 13000000, 600000000, 600, 13, 0, 8}, 182 { 13000000, 600000000, 600, 13, 1, 8 },
183 { 19200000, 600000000, 375, 12, 0, 6}, 183 { 19200000, 600000000, 375, 12, 1, 6 },
184 { 26000000, 600000000, 600, 26, 0, 8}, 184 { 26000000, 600000000, 600, 26, 1, 8 },
185 { 0, 0, 0, 0, 0, 0 }, 185 { 0, 0, 0, 0, 0, 0 },
186}; 186};
187 187
188static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 188static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
189 { 12000000, 216000000, 432, 12, 1, 8}, 189 { 12000000, 216000000, 432, 12, 2, 8 },
190 { 13000000, 216000000, 432, 13, 1, 8}, 190 { 13000000, 216000000, 432, 13, 2, 8 },
191 { 19200000, 216000000, 90, 4, 1, 1}, 191 { 19200000, 216000000, 90, 4, 2, 1 },
192 { 26000000, 216000000, 432, 26, 1, 8}, 192 { 26000000, 216000000, 432, 26, 2, 8 },
193 { 12000000, 432000000, 432, 12, 0, 8}, 193 { 12000000, 432000000, 432, 12, 1, 8 },
194 { 13000000, 432000000, 432, 13, 0, 8}, 194 { 13000000, 432000000, 432, 13, 1, 8 },
195 { 19200000, 432000000, 90, 4, 0, 1}, 195 { 19200000, 432000000, 90, 4, 1, 1 },
196 { 26000000, 432000000, 432, 26, 0, 8}, 196 { 26000000, 432000000, 432, 26, 1, 8 },
197 { 0, 0, 0, 0, 0, 0 }, 197 { 0, 0, 0, 0, 0, 0 },
198}; 198};
199 199
200static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 200static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
201 { 28800000, 56448000, 49, 25, 0, 1}, 201 { 28800000, 56448000, 49, 25, 1, 1 },
202 { 28800000, 73728000, 64, 25, 0, 1}, 202 { 28800000, 73728000, 64, 25, 1, 1 },
203 { 28800000, 24000000, 5, 6, 0, 1}, 203 { 28800000, 24000000, 5, 6, 1, 1 },
204 { 0, 0, 0, 0, 0, 0 }, 204 { 0, 0, 0, 0, 0, 0 },
205}; 205};
206 206
207static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 207static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
208 { 12000000, 216000000, 216, 12, 0, 4}, 208 { 12000000, 216000000, 216, 12, 1, 4 },
209 { 13000000, 216000000, 216, 13, 0, 4}, 209 { 13000000, 216000000, 216, 13, 1, 4 },
210 { 19200000, 216000000, 135, 12, 0, 3}, 210 { 19200000, 216000000, 135, 12, 1, 3 },
211 { 26000000, 216000000, 216, 26, 0, 4}, 211 { 26000000, 216000000, 216, 26, 1, 4 },
212 212 { 12000000, 594000000, 594, 12, 1, 8 },
213 { 12000000, 594000000, 594, 12, 0, 8}, 213 { 13000000, 594000000, 594, 13, 1, 8 },
214 { 13000000, 594000000, 594, 13, 0, 8}, 214 { 19200000, 594000000, 495, 16, 1, 8 },
215 { 19200000, 594000000, 495, 16, 0, 8}, 215 { 26000000, 594000000, 594, 26, 1, 8 },
216 { 26000000, 594000000, 594, 26, 0, 8}, 216 { 12000000, 1000000000, 1000, 12, 1, 12 },
217 217 { 13000000, 1000000000, 1000, 13, 1, 12 },
218 { 12000000, 1000000000, 1000, 12, 0, 12}, 218 { 19200000, 1000000000, 625, 12, 1, 8 },
219 { 13000000, 1000000000, 1000, 13, 0, 12}, 219 { 26000000, 1000000000, 1000, 26, 1, 12 },
220 { 19200000, 1000000000, 625, 12, 0, 8}, 220 { 0, 0, 0, 0, 0, 0 },
221 { 26000000, 1000000000, 1000, 26, 0, 12},
222
223 { 0, 0, 0, 0, 0, 0 },
224}; 221};
225 222
226static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 223static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
227 { 12000000, 480000000, 960, 12, 0, 0}, 224 { 12000000, 480000000, 960, 12, 1, 0 },
228 { 13000000, 480000000, 960, 13, 0, 0}, 225 { 13000000, 480000000, 960, 13, 1, 0 },
229 { 19200000, 480000000, 200, 4, 0, 0}, 226 { 19200000, 480000000, 200, 4, 1, 0 },
230 { 26000000, 480000000, 960, 26, 0, 0}, 227 { 26000000, 480000000, 960, 26, 1, 0 },
231 { 0, 0, 0, 0, 0, 0 }, 228 { 0, 0, 0, 0, 0, 0 },
232}; 229};
233 230
234static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 231static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
235 /* 1 GHz */ 232 /* 1 GHz */
236 { 12000000, 1000000000, 1000, 12, 0, 12}, 233 { 12000000, 1000000000, 1000, 12, 1, 12 },
237 { 13000000, 1000000000, 1000, 13, 0, 12}, 234 { 13000000, 1000000000, 1000, 13, 1, 12 },
238 { 19200000, 1000000000, 625, 12, 0, 8}, 235 { 19200000, 1000000000, 625, 12, 1, 8 },
239 { 26000000, 1000000000, 1000, 26, 0, 12}, 236 { 26000000, 1000000000, 1000, 26, 1, 12 },
240
241 /* 912 MHz */ 237 /* 912 MHz */
242 { 12000000, 912000000, 912, 12, 0, 12}, 238 { 12000000, 912000000, 912, 12, 1, 12 },
243 { 13000000, 912000000, 912, 13, 0, 12}, 239 { 13000000, 912000000, 912, 13, 1, 12 },
244 { 19200000, 912000000, 760, 16, 0, 8}, 240 { 19200000, 912000000, 760, 16, 1, 8 },
245 { 26000000, 912000000, 912, 26, 0, 12}, 241 { 26000000, 912000000, 912, 26, 1, 12 },
246
247 /* 816 MHz */ 242 /* 816 MHz */
248 { 12000000, 816000000, 816, 12, 0, 12}, 243 { 12000000, 816000000, 816, 12, 1, 12 },
249 { 13000000, 816000000, 816, 13, 0, 12}, 244 { 13000000, 816000000, 816, 13, 1, 12 },
250 { 19200000, 816000000, 680, 16, 0, 8}, 245 { 19200000, 816000000, 680, 16, 1, 8 },
251 { 26000000, 816000000, 816, 26, 0, 12}, 246 { 26000000, 816000000, 816, 26, 1, 12 },
252
253 /* 760 MHz */ 247 /* 760 MHz */
254 { 12000000, 760000000, 760, 12, 0, 12}, 248 { 12000000, 760000000, 760, 12, 1, 12 },
255 { 13000000, 760000000, 760, 13, 0, 12}, 249 { 13000000, 760000000, 760, 13, 1, 12 },
256 { 19200000, 760000000, 950, 24, 0, 8}, 250 { 19200000, 760000000, 950, 24, 1, 8 },
257 { 26000000, 760000000, 760, 26, 0, 12}, 251 { 26000000, 760000000, 760, 26, 1, 12 },
258
259 /* 750 MHz */ 252 /* 750 MHz */
260 { 12000000, 750000000, 750, 12, 0, 12}, 253 { 12000000, 750000000, 750, 12, 1, 12 },
261 { 13000000, 750000000, 750, 13, 0, 12}, 254 { 13000000, 750000000, 750, 13, 1, 12 },
262 { 19200000, 750000000, 625, 16, 0, 8}, 255 { 19200000, 750000000, 625, 16, 1, 8 },
263 { 26000000, 750000000, 750, 26, 0, 12}, 256 { 26000000, 750000000, 750, 26, 1, 12 },
264
265 /* 608 MHz */ 257 /* 608 MHz */
266 { 12000000, 608000000, 608, 12, 0, 12}, 258 { 12000000, 608000000, 608, 12, 1, 12 },
267 { 13000000, 608000000, 608, 13, 0, 12}, 259 { 13000000, 608000000, 608, 13, 1, 12 },
268 { 19200000, 608000000, 380, 12, 0, 8}, 260 { 19200000, 608000000, 380, 12, 1, 8 },
269 { 26000000, 608000000, 608, 26, 0, 12}, 261 { 26000000, 608000000, 608, 26, 1, 12 },
270
271 /* 456 MHz */ 262 /* 456 MHz */
272 { 12000000, 456000000, 456, 12, 0, 12}, 263 { 12000000, 456000000, 456, 12, 1, 12 },
273 { 13000000, 456000000, 456, 13, 0, 12}, 264 { 13000000, 456000000, 456, 13, 1, 12 },
274 { 19200000, 456000000, 380, 16, 0, 8}, 265 { 19200000, 456000000, 380, 16, 1, 8 },
275 { 26000000, 456000000, 456, 26, 0, 12}, 266 { 26000000, 456000000, 456, 26, 1, 12 },
276
277 /* 312 MHz */ 267 /* 312 MHz */
278 { 12000000, 312000000, 312, 12, 0, 12}, 268 { 12000000, 312000000, 312, 12, 1, 12 },
279 { 13000000, 312000000, 312, 13, 0, 12}, 269 { 13000000, 312000000, 312, 13, 1, 12 },
280 { 19200000, 312000000, 260, 16, 0, 8}, 270 { 19200000, 312000000, 260, 16, 1, 8 },
281 { 26000000, 312000000, 312, 26, 0, 12}, 271 { 26000000, 312000000, 312, 26, 1, 12 },
272 { 0, 0, 0, 0, 0, 0 },
273};
282 274
283 { 0, 0, 0, 0, 0, 0 }, 275static const struct pdiv_map plle_p[] = {
276 { .pdiv = 1, .hw_val = 1 },
277 { .pdiv = 0, .hw_val = 0 },
284}; 278};
285 279
286static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 280static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
287 { 12000000, 100000000, 200, 24, 0, 0 }, 281 { 12000000, 100000000, 200, 24, 1, 0 },
288 { 0, 0, 0, 0, 0, 0 }, 282 { 0, 0, 0, 0, 0, 0 },
289}; 283};
290 284
291/* PLL parameters */ 285/* PLL parameters */
@@ -302,7 +296,7 @@ static struct tegra_clk_pll_params pll_c_params = {
302 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 296 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
303 .lock_delay = 300, 297 .lock_delay = 300,
304 .freq_table = pll_c_freq_table, 298 .freq_table = pll_c_freq_table,
305 .flags = TEGRA_PLL_HAS_CPCON, 299 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
306}; 300};
307 301
308static struct tegra_clk_pll_params pll_m_params = { 302static struct tegra_clk_pll_params pll_m_params = {
@@ -318,7 +312,7 @@ static struct tegra_clk_pll_params pll_m_params = {
318 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 312 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
319 .lock_delay = 300, 313 .lock_delay = 300,
320 .freq_table = pll_m_freq_table, 314 .freq_table = pll_m_freq_table,
321 .flags = TEGRA_PLL_HAS_CPCON, 315 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
322}; 316};
323 317
324static struct tegra_clk_pll_params pll_p_params = { 318static struct tegra_clk_pll_params pll_p_params = {
@@ -334,7 +328,8 @@ static struct tegra_clk_pll_params pll_p_params = {
334 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 328 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
335 .lock_delay = 300, 329 .lock_delay = 300,
336 .freq_table = pll_p_freq_table, 330 .freq_table = pll_p_freq_table,
337 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON, 331 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
332 TEGRA_PLL_HAS_LOCK_ENABLE,
338 .fixed_rate = 216000000, 333 .fixed_rate = 216000000,
339}; 334};
340 335
@@ -351,7 +346,7 @@ static struct tegra_clk_pll_params pll_a_params = {
351 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 346 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
352 .lock_delay = 300, 347 .lock_delay = 300,
353 .freq_table = pll_a_freq_table, 348 .freq_table = pll_a_freq_table,
354 .flags = TEGRA_PLL_HAS_CPCON, 349 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
355}; 350};
356 351
357static struct tegra_clk_pll_params pll_d_params = { 352static struct tegra_clk_pll_params pll_d_params = {
@@ -367,10 +362,10 @@ static struct tegra_clk_pll_params pll_d_params = {
367 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 362 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
368 .lock_delay = 1000, 363 .lock_delay = 1000,
369 .freq_table = pll_d_freq_table, 364 .freq_table = pll_d_freq_table,
370 .flags = TEGRA_PLL_HAS_CPCON, 365 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
371}; 366};
372 367
373static struct pdiv_map pllu_p[] = { 368static const struct pdiv_map pllu_p[] = {
374 { .pdiv = 1, .hw_val = 1 }, 369 { .pdiv = 1, .hw_val = 1 },
375 { .pdiv = 2, .hw_val = 0 }, 370 { .pdiv = 2, .hw_val = 0 },
376 { .pdiv = 0, .hw_val = 0 }, 371 { .pdiv = 0, .hw_val = 0 },
@@ -390,7 +385,7 @@ static struct tegra_clk_pll_params pll_u_params = {
390 .lock_delay = 1000, 385 .lock_delay = 1000,
391 .pdiv_tohw = pllu_p, 386 .pdiv_tohw = pllu_p,
392 .freq_table = pll_u_freq_table, 387 .freq_table = pll_u_freq_table,
393 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, 388 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
394}; 389};
395 390
396static struct tegra_clk_pll_params pll_x_params = { 391static struct tegra_clk_pll_params pll_x_params = {
@@ -406,7 +401,7 @@ static struct tegra_clk_pll_params pll_x_params = {
406 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 401 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
407 .lock_delay = 300, 402 .lock_delay = 300,
408 .freq_table = pll_x_freq_table, 403 .freq_table = pll_x_freq_table,
409 .flags = TEGRA_PLL_HAS_CPCON, 404 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
410}; 405};
411 406
412static struct tegra_clk_pll_params pll_e_params = { 407static struct tegra_clk_pll_params pll_e_params = {
@@ -421,8 +416,10 @@ static struct tegra_clk_pll_params pll_e_params = {
421 .lock_mask = PLLE_MISC_LOCK, 416 .lock_mask = PLLE_MISC_LOCK,
422 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 417 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
423 .lock_delay = 0, 418 .lock_delay = 0,
419 .pdiv_tohw = plle_p,
424 .freq_table = pll_e_freq_table, 420 .freq_table = pll_e_freq_table,
425 .flags = TEGRA_PLL_FIXED, 421 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
422 TEGRA_PLL_HAS_LOCK_ENABLE,
426 .fixed_rate = 100000000, 423 .fixed_rate = 100000000,
427}; 424};
428 425
@@ -733,9 +730,9 @@ static void tegra20_super_clk_init(void)
733 clks[TEGRA20_CLK_TWD] = clk; 730 clks[TEGRA20_CLK_TWD] = clk;
734} 731}
735 732
736static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", 733static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",
737 "pll_a_out0", "unused", "unused", 734 "pll_a_out0", "unused", "unused",
738 "unused"}; 735 "unused" };
739 736
740static void __init tegra20_audio_clk_init(void) 737static void __init tegra20_audio_clk_init(void)
741{ 738{
@@ -759,19 +756,18 @@ static void __init tegra20_audio_clk_init(void)
759 CLK_SET_RATE_PARENT, 89, 756 CLK_SET_RATE_PARENT, 89,
760 periph_clk_enb_refcnt); 757 periph_clk_enb_refcnt);
761 clks[TEGRA20_CLK_AUDIO_2X] = clk; 758 clks[TEGRA20_CLK_AUDIO_2X] = clk;
762
763} 759}
764 760
765static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 761static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
766 "clk_m"}; 762 "clk_m" };
767static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 763static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
768 "clk_m"}; 764 "clk_m" };
769static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", 765static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
770 "clk_32k"}; 766 "clk_32k" };
771static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; 767static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
772static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", 768static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
773 "clk_m"}; 769 "clk_m" };
774static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 770static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
775 771
776static struct tegra_periph_init_data tegra_periph_clk_list[] = { 772static struct tegra_periph_init_data tegra_periph_clk_list[] = {
777 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1), 773 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
@@ -802,7 +798,7 @@ static void __init tegra20_periph_clk_init(void)
802{ 798{
803 struct tegra_periph_init_data *data; 799 struct tegra_periph_init_data *data;
804 struct clk *clk; 800 struct clk *clk;
805 int i; 801 unsigned int i;
806 802
807 /* ac97 */ 803 /* ac97 */
808 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 804 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
@@ -1025,44 +1021,45 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1025}; 1021};
1026 1022
1027static struct tegra_clk_init_table init_table[] __initdata = { 1023static struct tegra_clk_init_table init_table[] __initdata = {
1028 {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1}, 1024 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
1029 {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1}, 1025 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
1030 {TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1}, 1026 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
1031 {TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1}, 1027 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
1032 {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1}, 1028 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
1033 {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1}, 1029 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
1034 {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1}, 1030 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 },
1035 {TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1}, 1031 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
1036 {TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1}, 1032 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
1037 {TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1}, 1033 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
1038 {TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1}, 1034 { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
1039 {TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1}, 1035 { TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1 },
1040 {TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1}, 1036 { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
1041 {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0}, 1037 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
1042 {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0}, 1038 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
1043 {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0}, 1039 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
1044 {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0}, 1040 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
1045 {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0}, 1041 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
1046 {TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1}, 1042 { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
1047 {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1}, 1043 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
1048 {TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1}, 1044 { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
1049 {TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1}, 1045 { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
1050 {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0}, 1046 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1051 {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0}, 1047 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1052 {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0}, 1048 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
1053 {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0}, 1049 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
1054 {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0}, 1050 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
1055 {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0}, 1051 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
1056 {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0}, 1052 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
1057 {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0}, 1053 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
1058 {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0}, 1054 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
1059 {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0}, 1055 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
1060 {TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0}, 1056 { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
1061 {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0}, 1057 { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 },
1062 {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0}, 1058 { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
1063 {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0}, 1059 { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1064 {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0}, 1060 { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1065 {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */ 1061 /* must be the last entry */
1062 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
1066}; 1063};
1067 1064
1068static void __init tegra20_clock_apply_init_table(void) 1065static void __init tegra20_clock_apply_init_table(void)
@@ -1076,16 +1073,17 @@ static void __init tegra20_clock_apply_init_table(void)
1076 * table under two names. 1073 * table under two names.
1077 */ 1074 */
1078static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1075static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1079 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL), 1076 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1080 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL), 1077 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1081 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL), 1078 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1082 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"), 1079 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
1083 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */ 1080 /* must be the last entry */
1081 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL),
1084}; 1082};
1085 1083
1086static const struct of_device_id pmc_match[] __initconst = { 1084static const struct of_device_id pmc_match[] __initconst = {
1087 { .compatible = "nvidia,tegra20-pmc" }, 1085 { .compatible = "nvidia,tegra20-pmc" },
1088 {}, 1086 { },
1089}; 1087};
1090 1088
1091static void __init tegra20_clock_init(struct device_node *np) 1089static void __init tegra20_clock_init(struct device_node *np)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
new file mode 100644
index 000000000000..58514c44ea83
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -0,0 +1,2852 @@
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26#include <dt-bindings/clock/tegra210-car.h>
27
28#include "clk.h"
29#include "clk-id.h"
30
31/*
32 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
33 * banks present in the Tegra210 CAR IP block. The banks are
34 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
35 * periph_regs[] in drivers/clk/tegra/clk.c
36 */
37#define TEGRA210_CAR_BANK_COUNT 7
38
39#define CLK_SOURCE_CSITE 0x1d4
40#define CLK_SOURCE_EMC 0x19c
41
42#define PLLC_BASE 0x80
43#define PLLC_OUT 0x84
44#define PLLC_MISC0 0x88
45#define PLLC_MISC1 0x8c
46#define PLLC_MISC2 0x5d0
47#define PLLC_MISC3 0x5d4
48
49#define PLLC2_BASE 0x4e8
50#define PLLC2_MISC0 0x4ec
51#define PLLC2_MISC1 0x4f0
52#define PLLC2_MISC2 0x4f4
53#define PLLC2_MISC3 0x4f8
54
55#define PLLC3_BASE 0x4fc
56#define PLLC3_MISC0 0x500
57#define PLLC3_MISC1 0x504
58#define PLLC3_MISC2 0x508
59#define PLLC3_MISC3 0x50c
60
61#define PLLM_BASE 0x90
62#define PLLM_MISC0 0x9c
63#define PLLM_MISC1 0x98
64#define PLLP_BASE 0xa0
65#define PLLP_MISC0 0xac
66#define PLLP_MISC1 0x680
67#define PLLA_BASE 0xb0
68#define PLLA_MISC0 0xbc
69#define PLLA_MISC1 0xb8
70#define PLLA_MISC2 0x5d8
71#define PLLD_BASE 0xd0
72#define PLLD_MISC0 0xdc
73#define PLLD_MISC1 0xd8
74#define PLLU_BASE 0xc0
75#define PLLU_OUTA 0xc4
76#define PLLU_MISC0 0xcc
77#define PLLU_MISC1 0xc8
78#define PLLX_BASE 0xe0
79#define PLLX_MISC0 0xe4
80#define PLLX_MISC1 0x510
81#define PLLX_MISC2 0x514
82#define PLLX_MISC3 0x518
83#define PLLX_MISC4 0x5f0
84#define PLLX_MISC5 0x5f4
85#define PLLE_BASE 0xe8
86#define PLLE_MISC0 0xec
87#define PLLD2_BASE 0x4b8
88#define PLLD2_MISC0 0x4bc
89#define PLLD2_MISC1 0x570
90#define PLLD2_MISC2 0x574
91#define PLLD2_MISC3 0x578
92#define PLLE_AUX 0x48c
93#define PLLRE_BASE 0x4c4
94#define PLLRE_MISC0 0x4c8
95#define PLLDP_BASE 0x590
96#define PLLDP_MISC 0x594
97
98#define PLLC4_BASE 0x5a4
99#define PLLC4_MISC0 0x5a8
100#define PLLC4_OUT 0x5e4
101#define PLLMB_BASE 0x5e8
102#define PLLMB_MISC0 0x5ec
103#define PLLA1_BASE 0x6a4
104#define PLLA1_MISC0 0x6a8
105#define PLLA1_MISC1 0x6ac
106#define PLLA1_MISC2 0x6b0
107#define PLLA1_MISC3 0x6b4
108
109#define PLLU_IDDQ_BIT 31
110#define PLLCX_IDDQ_BIT 27
111#define PLLRE_IDDQ_BIT 24
112#define PLLA_IDDQ_BIT 25
113#define PLLD_IDDQ_BIT 20
114#define PLLSS_IDDQ_BIT 18
115#define PLLM_IDDQ_BIT 5
116#define PLLMB_IDDQ_BIT 17
117#define PLLXP_IDDQ_BIT 3
118
119#define PLLCX_RESET_BIT 30
120
121#define PLL_BASE_LOCK BIT(27)
122#define PLLCX_BASE_LOCK BIT(26)
123#define PLLE_MISC_LOCK BIT(11)
124#define PLLRE_MISC_LOCK BIT(27)
125
126#define PLL_MISC_LOCK_ENABLE 18
127#define PLLC_MISC_LOCK_ENABLE 24
128#define PLLDU_MISC_LOCK_ENABLE 22
129#define PLLU_MISC_LOCK_ENABLE 29
130#define PLLE_MISC_LOCK_ENABLE 9
131#define PLLRE_MISC_LOCK_ENABLE 30
132#define PLLSS_MISC_LOCK_ENABLE 30
133#define PLLP_MISC_LOCK_ENABLE 18
134#define PLLM_MISC_LOCK_ENABLE 4
135#define PLLMB_MISC_LOCK_ENABLE 16
136#define PLLA_MISC_LOCK_ENABLE 28
137#define PLLU_MISC_LOCK_ENABLE 29
138#define PLLD_MISC_LOCK_ENABLE 18
139
140#define PLLA_SDM_DIN_MASK 0xffff
141#define PLLA_SDM_EN_MASK BIT(26)
142
143#define PLLD_SDM_EN_MASK BIT(16)
144
145#define PLLD2_SDM_EN_MASK BIT(31)
146#define PLLD2_SSC_EN_MASK BIT(30)
147
148#define PLLDP_SS_CFG 0x598
149#define PLLDP_SDM_EN_MASK BIT(31)
150#define PLLDP_SSC_EN_MASK BIT(30)
151#define PLLDP_SS_CTRL1 0x59c
152#define PLLDP_SS_CTRL2 0x5a0
153
154#define PMC_PLLM_WB0_OVERRIDE 0x1dc
155#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
156
157#define UTMIP_PLL_CFG2 0x488
158#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
159#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
160#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
161#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
162#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
163#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
164#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
165#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
166#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
167#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
168
169#define UTMIP_PLL_CFG1 0x484
170#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
171#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
172#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
173#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
174#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
175#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
176#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
177
178#define UTMIPLL_HW_PWRDN_CFG0 0x52c
179#define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
180#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
181#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
182#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
183#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
184#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
185#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
186#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
187#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
188#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
189
190#define PLLU_HW_PWRDN_CFG0 0x530
191#define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
192#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
193#define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
194#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
195#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
196#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
197
198#define XUSB_PLL_CFG0 0x534
199#define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
200#define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
201
202#define SPARE_REG0 0x55c
203#define CLK_M_DIVISOR_SHIFT 2
204#define CLK_M_DIVISOR_MASK 0x3
205
206/*
207 * SDM fractional divisor is 16-bit 2's complement signed number within
208 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
209 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
210 * indicate that SDM is disabled.
211 *
212 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
213 */
214#define PLL_SDM_COEFF BIT(13)
215#define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
216#define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
217
218/* Tegra CPU clock and reset control regs */
219#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
220
221#ifdef CONFIG_PM_SLEEP
222static struct cpu_clk_suspend_context {
223 u32 clk_csite_src;
224} tegra210_cpu_clk_sctx;
225#endif
226
227static void __iomem *clk_base;
228static void __iomem *pmc_base;
229
230static unsigned long osc_freq;
231static unsigned long pll_ref_freq;
232
233static DEFINE_SPINLOCK(pll_d_lock);
234static DEFINE_SPINLOCK(pll_e_lock);
235static DEFINE_SPINLOCK(pll_re_lock);
236static DEFINE_SPINLOCK(pll_u_lock);
237static DEFINE_SPINLOCK(emc_lock);
238
239/* possible OSC frequencies in Hz */
240static unsigned long tegra210_input_freq[] = {
241 [5] = 38400000,
242 [8] = 12000000,
243};
244
245static const char *mux_pllmcp_clkm[] = {
246 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
247};
248#define mux_pllmcp_clkm_idx NULL
249
250#define PLL_ENABLE (1 << 30)
251
252#define PLLCX_MISC1_IDDQ (1 << 27)
253#define PLLCX_MISC0_RESET (1 << 30)
254
255#define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
256#define PLLCX_MISC0_WRITE_MASK 0x400ffffb
257#define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
258#define PLLCX_MISC1_WRITE_MASK 0x08003cff
259#define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
260#define PLLCX_MISC2_WRITE_MASK 0xffffff17
261#define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
262#define PLLCX_MISC3_WRITE_MASK 0x00ffffff
263
264/* PLLA */
265#define PLLA_BASE_IDDQ (1 << 25)
266#define PLLA_BASE_LOCK (1 << 27)
267
268#define PLLA_MISC0_LOCK_ENABLE (1 << 28)
269#define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
270
271#define PLLA_MISC2_EN_SDM (1 << 26)
272#define PLLA_MISC2_EN_DYNRAMP (1 << 25)
273
274#define PLLA_MISC0_DEFAULT_VALUE 0x12000020
275#define PLLA_MISC0_WRITE_MASK 0x7fffffff
276#define PLLA_MISC2_DEFAULT_VALUE 0x0
277#define PLLA_MISC2_WRITE_MASK 0x06ffffff
278
279/* PLLD */
280#define PLLD_MISC0_EN_SDM (1 << 16)
281#define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
282#define PLLD_MISC0_LOCK_ENABLE (1 << 18)
283#define PLLD_MISC0_IDDQ (1 << 20)
284#define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
285
286#define PLLD_MISC0_DEFAULT_VALUE 0x00140000
287#define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
288#define PLLD_MISC1_DEFAULT_VALUE 0x20
289#define PLLD_MISC1_WRITE_MASK 0x00ffffff
290
291/* PLLD2 and PLLDP and PLLC4 */
292#define PLLDSS_BASE_LOCK (1 << 27)
293#define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
294#define PLLDSS_BASE_IDDQ (1 << 18)
295#define PLLDSS_BASE_REF_SEL_SHIFT 25
296#define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
297
298#define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
299
300#define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
301#define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
302
303#define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
304#define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
305#define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
306#define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
307
308#define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
309#define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
310#define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
311#define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
312
313#define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
314#define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
315#define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
316#define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
317
318#define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
319
320/* PLLRE */
321#define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
322#define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
323#define PLLRE_MISC0_LOCK (1 << 27)
324#define PLLRE_MISC0_IDDQ (1 << 24)
325
326#define PLLRE_BASE_DEFAULT_VALUE 0x0
327#define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
328
329#define PLLRE_BASE_DEFAULT_MASK 0x1c000000
330#define PLLRE_MISC0_WRITE_MASK 0x67ffffff
331
332/* PLLX */
333#define PLLX_USE_DYN_RAMP 1
334#define PLLX_BASE_LOCK (1 << 27)
335
336#define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
337#define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
338
339#define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
340#define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
341#define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
342#define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
343#define PLLX_MISC2_NDIV_NEW_SHIFT 8
344#define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
345#define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
346#define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
347#define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
348
349#define PLLX_MISC3_IDDQ (0x1 << 3)
350
351#define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
352#define PLLX_MISC0_WRITE_MASK 0x10c40000
353#define PLLX_MISC1_DEFAULT_VALUE 0x20
354#define PLLX_MISC1_WRITE_MASK 0x00ffffff
355#define PLLX_MISC2_DEFAULT_VALUE 0x0
356#define PLLX_MISC2_WRITE_MASK 0xffffff11
357#define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
358#define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
359#define PLLX_MISC4_DEFAULT_VALUE 0x0
360#define PLLX_MISC4_WRITE_MASK 0x8000ffff
361#define PLLX_MISC5_DEFAULT_VALUE 0x0
362#define PLLX_MISC5_WRITE_MASK 0x0000ffff
363
364#define PLLX_HW_CTRL_CFG 0x548
365#define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
366
367/* PLLMB */
368#define PLLMB_BASE_LOCK (1 << 27)
369
370#define PLLMB_MISC0_LOCK_OVERRIDE (1 << 18)
371#define PLLMB_MISC0_IDDQ (1 << 17)
372#define PLLMB_MISC0_LOCK_ENABLE (1 << 16)
373
374#define PLLMB_MISC0_DEFAULT_VALUE 0x00030000
375#define PLLMB_MISC0_WRITE_MASK 0x0007ffff
376
377/* PLLP */
378#define PLLP_BASE_OVERRIDE (1 << 28)
379#define PLLP_BASE_LOCK (1 << 27)
380
381#define PLLP_MISC0_LOCK_ENABLE (1 << 18)
382#define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
383#define PLLP_MISC0_IDDQ (1 << 3)
384
385#define PLLP_MISC1_HSIO_EN_SHIFT 29
386#define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
387#define PLLP_MISC1_XUSB_EN_SHIFT 28
388#define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
389
390#define PLLP_MISC0_DEFAULT_VALUE 0x00040008
391#define PLLP_MISC1_DEFAULT_VALUE 0x0
392
393#define PLLP_MISC0_WRITE_MASK 0xdc6000f
394#define PLLP_MISC1_WRITE_MASK 0x70ffffff
395
396/* PLLU */
397#define PLLU_BASE_LOCK (1 << 27)
398#define PLLU_BASE_OVERRIDE (1 << 24)
399#define PLLU_BASE_CLKENABLE_USB (1 << 21)
400#define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
401#define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
402#define PLLU_BASE_CLKENABLE_48M (1 << 25)
403#define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
404 PLLU_BASE_CLKENABLE_HSIC |\
405 PLLU_BASE_CLKENABLE_ICUSB |\
406 PLLU_BASE_CLKENABLE_48M)
407
408#define PLLU_MISC0_IDDQ (1 << 31)
409#define PLLU_MISC0_LOCK_ENABLE (1 << 29)
410#define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
411
412#define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
413#define PLLU_MISC1_DEFAULT_VALUE 0x0
414
415#define PLLU_MISC0_WRITE_MASK 0xbfffffff
416#define PLLU_MISC1_WRITE_MASK 0x00000007
417
418static inline void _pll_misc_chk_default(void __iomem *base,
419 struct tegra_clk_pll_params *params,
420 u8 misc_num, u32 default_val, u32 mask)
421{
422 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
423
424 boot_val &= mask;
425 default_val &= mask;
426 if (boot_val != default_val) {
427 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
428 misc_num, boot_val, default_val);
429 pr_warn(" (comparison mask = 0x%x)\n", mask);
430 params->defaults_set = false;
431 }
432}
433
434/*
435 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
436 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
437 * that changes NDIV only, while PLL is already locked.
438 */
439static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
440{
441 u32 default_val;
442
443 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
444 _pll_misc_chk_default(clk_base, params, 0, default_val,
445 PLLCX_MISC0_WRITE_MASK);
446
447 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
448 _pll_misc_chk_default(clk_base, params, 1, default_val,
449 PLLCX_MISC1_WRITE_MASK);
450
451 default_val = PLLCX_MISC2_DEFAULT_VALUE;
452 _pll_misc_chk_default(clk_base, params, 2, default_val,
453 PLLCX_MISC2_WRITE_MASK);
454
455 default_val = PLLCX_MISC3_DEFAULT_VALUE;
456 _pll_misc_chk_default(clk_base, params, 3, default_val,
457 PLLCX_MISC3_WRITE_MASK);
458}
459
460void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx)
461{
462 pllcx->params->defaults_set = true;
463
464 if (readl_relaxed(clk_base + pllcx->params->base_reg) &
465 PLL_ENABLE) {
466 /* PLL is ON: only check if defaults already set */
467 pllcx_check_defaults(pllcx->params);
468 pr_warn("%s already enabled. Postponing set full defaults\n",
469 name);
470 return;
471 }
472
473 /* Defaults assert PLL reset, and set IDDQ */
474 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
475 clk_base + pllcx->params->ext_misc_reg[0]);
476 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
477 clk_base + pllcx->params->ext_misc_reg[1]);
478 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
479 clk_base + pllcx->params->ext_misc_reg[2]);
480 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
481 clk_base + pllcx->params->ext_misc_reg[3]);
482 udelay(1);
483}
484
485void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
486{
487 tegra210_pllcx_set_defaults("PLL_C", pllcx);
488}
489
490void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
491{
492 tegra210_pllcx_set_defaults("PLL_C2", pllcx);
493}
494
495void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
496{
497 tegra210_pllcx_set_defaults("PLL_C3", pllcx);
498}
499
500void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
501{
502 tegra210_pllcx_set_defaults("PLL_A1", pllcx);
503}
504
505/*
506 * PLLA
507 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
508 * Fractional SDM is allowed to provide exact audio rates.
509 */
510void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
511{
512 u32 mask;
513 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
514
515 plla->params->defaults_set = true;
516
517 if (val & PLL_ENABLE) {
518 /*
519 * PLL is ON: check if defaults already set, then set those
520 * that can be updated in flight.
521 */
522 if (val & PLLA_BASE_IDDQ) {
523 pr_warn("PLL_A boot enabled with IDDQ set\n");
524 plla->params->defaults_set = false;
525 }
526
527 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
528
529 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */
530 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
531 _pll_misc_chk_default(clk_base, plla->params, 0, val,
532 ~mask & PLLA_MISC0_WRITE_MASK);
533
534 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */
535 _pll_misc_chk_default(clk_base, plla->params, 2, val,
536 PLLA_MISC2_EN_DYNRAMP);
537
538 /* Enable lock detect */
539 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
540 val &= ~mask;
541 val |= PLLA_MISC0_DEFAULT_VALUE & mask;
542 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
543 udelay(1);
544
545 return;
546 }
547
548 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
549 val |= PLLA_BASE_IDDQ;
550 writel_relaxed(val, clk_base + plla->params->base_reg);
551 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
552 clk_base + plla->params->ext_misc_reg[0]);
553 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
554 clk_base + plla->params->ext_misc_reg[2]);
555 udelay(1);
556}
557
558/*
559 * PLLD
560 * PLL with fractional SDM.
561 */
562void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
563{
564 u32 val;
565 u32 mask = 0xffff;
566
567 plld->params->defaults_set = true;
568
569 if (readl_relaxed(clk_base + plld->params->base_reg) &
570 PLL_ENABLE) {
571 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
572
573 /*
574 * PLL is ON: check if defaults already set, then set those
575 * that can be updated in flight.
576 */
577 val = PLLD_MISC1_DEFAULT_VALUE;
578 _pll_misc_chk_default(clk_base, plld->params, 1,
579 val, PLLD_MISC1_WRITE_MASK);
580
581 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
582 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
583 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
584 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
585 _pll_misc_chk_default(clk_base, plld->params, 0, val,
586 ~mask & PLLD_MISC0_WRITE_MASK);
587
588 /* Enable lock detect */
589 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
590 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
591 val &= ~mask;
592 val |= PLLD_MISC0_DEFAULT_VALUE & mask;
593 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
594 udelay(1);
595
596 return;
597 }
598
599 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
600 val &= PLLD_MISC0_DSI_CLKENABLE;
601 val |= PLLD_MISC0_DEFAULT_VALUE;
602 /* set IDDQ, enable lock detect, disable SDM */
603 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
604 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
605 plld->params->ext_misc_reg[1]);
606 udelay(1);
607}
608
609/*
610 * PLLD2, PLLDP
611 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
612 */
613static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
614 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
615{
616 u32 default_val;
617 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
618
619 plldss->params->defaults_set = true;
620
621 if (val & PLL_ENABLE) {
622 pr_warn("%s already enabled. Postponing set full defaults\n",
623 pll_name);
624
625 /*
626 * PLL is ON: check if defaults already set, then set those
627 * that can be updated in flight.
628 */
629 if (val & PLLDSS_BASE_IDDQ) {
630 pr_warn("plldss boot enabled with IDDQ set\n");
631 plldss->params->defaults_set = false;
632 }
633
634 /* ignore lock enable */
635 default_val = misc0_val;
636 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
637 PLLDSS_MISC0_WRITE_MASK &
638 (~PLLDSS_MISC0_LOCK_ENABLE));
639
640 /*
641 * If SSC is used, check all settings, otherwise just confirm
642 * that SSC is not used on boot as well. Do nothing when using
643 * this function for PLLC4 that has only MISC0.
644 */
645 if (plldss->params->ssc_ctrl_en_mask) {
646 default_val = misc1_val;
647 _pll_misc_chk_default(clk_base, plldss->params, 1,
648 default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
649 default_val = misc2_val;
650 _pll_misc_chk_default(clk_base, plldss->params, 2,
651 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
652 default_val = misc3_val;
653 _pll_misc_chk_default(clk_base, plldss->params, 3,
654 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
655 } else if (plldss->params->ext_misc_reg[1]) {
656 default_val = misc1_val;
657 _pll_misc_chk_default(clk_base, plldss->params, 1,
658 default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
659 (~PLLDSS_MISC1_CFG_EN_SDM));
660 }
661
662 /* Enable lock detect */
663 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
664 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
665 writel_relaxed(val, clk_base +
666 plldss->params->base_reg);
667 }
668
669 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
670 val &= ~PLLDSS_MISC0_LOCK_ENABLE;
671 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
672 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
673 udelay(1);
674
675 return;
676 }
677
678 /* set IDDQ, enable lock detect, configure SDM/SSC */
679 val |= PLLDSS_BASE_IDDQ;
680 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
681 writel_relaxed(val, clk_base + plldss->params->base_reg);
682
683 /* When using this function for PLLC4 exit here */
684 if (!plldss->params->ext_misc_reg[1]) {
685 writel_relaxed(misc0_val, clk_base +
686 plldss->params->ext_misc_reg[0]);
687 udelay(1);
688 return;
689 }
690
691 writel_relaxed(misc0_val, clk_base +
692 plldss->params->ext_misc_reg[0]);
693 /* if SSC used set by 1st enable */
694 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
695 clk_base + plldss->params->ext_misc_reg[1]);
696 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
697 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
698 udelay(1);
699}
700
701void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
702{
703 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
704 PLLD2_MISC1_CFG_DEFAULT_VALUE,
705 PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
706 PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
707}
708
709void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
710{
711 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
712 PLLDP_MISC1_CFG_DEFAULT_VALUE,
713 PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
714 PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
715}
716
717/*
718 * PLLC4
719 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
720 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
721 */
722void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
723{
724 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
725}
726
727/*
728 * PLLRE
729 * VCO is exposed to the clock tree directly along with post-divider output
730 */
731void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
732{
733 u32 mask;
734 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
735
736 pllre->params->defaults_set = true;
737
738 if (val & PLL_ENABLE) {
739 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
740
741 /*
742 * PLL is ON: check if defaults already set, then set those
743 * that can be updated in flight.
744 */
745 val &= PLLRE_BASE_DEFAULT_MASK;
746 if (val != PLLRE_BASE_DEFAULT_VALUE) {
747 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
748 val, PLLRE_BASE_DEFAULT_VALUE);
749 pr_warn("(comparison mask = 0x%x)\n",
750 PLLRE_BASE_DEFAULT_MASK);
751 pllre->params->defaults_set = false;
752 }
753
754 /* Ignore lock enable */
755 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
756 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
757 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
758 ~mask & PLLRE_MISC0_WRITE_MASK);
759
760 /* Enable lock detect */
761 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
762 val &= ~mask;
763 val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
764 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
765 udelay(1);
766
767 return;
768 }
769
770 /* set IDDQ, enable lock detect */
771 val &= ~PLLRE_BASE_DEFAULT_MASK;
772 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
773 writel_relaxed(val, clk_base + pllre->params->base_reg);
774 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
775 clk_base + pllre->params->ext_misc_reg[0]);
776 udelay(1);
777}
778
779static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
780{
781 unsigned long input_rate;
782
783 if (!IS_ERR_OR_NULL(hw->clk)) {
784 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
785 /* cf rate */
786 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
787 } else {
788 input_rate = 38400000;
789 }
790
791 switch (input_rate) {
792 case 12000000:
793 case 12800000:
794 case 13000000:
795 *step_a = 0x2B;
796 *step_b = 0x0B;
797 return;
798 case 19200000:
799 *step_a = 0x12;
800 *step_b = 0x08;
801 return;
802 case 38400000:
803 *step_a = 0x04;
804 *step_b = 0x05;
805 return;
806 default:
807 pr_err("%s: Unexpected reference rate %lu\n",
808 __func__, input_rate);
809 BUG();
810 }
811}
812
813static void pllx_check_defaults(struct tegra_clk_pll *pll)
814{
815 u32 default_val;
816
817 default_val = PLLX_MISC0_DEFAULT_VALUE;
818 /* ignore lock enable */
819 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
820 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
821
822 default_val = PLLX_MISC1_DEFAULT_VALUE;
823 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
824 PLLX_MISC1_WRITE_MASK);
825
826 /* ignore all but control bit */
827 default_val = PLLX_MISC2_DEFAULT_VALUE;
828 _pll_misc_chk_default(clk_base, pll->params, 2,
829 default_val, PLLX_MISC2_EN_DYNRAMP);
830
831 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
832 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
833 PLLX_MISC3_WRITE_MASK);
834
835 default_val = PLLX_MISC4_DEFAULT_VALUE;
836 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
837 PLLX_MISC4_WRITE_MASK);
838
839 default_val = PLLX_MISC5_DEFAULT_VALUE;
840 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
841 PLLX_MISC5_WRITE_MASK);
842}
843
844void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
845{
846 u32 val;
847 u32 step_a, step_b;
848
849 pllx->params->defaults_set = true;
850
851 /* Get ready dyn ramp state machine settings */
852 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
853 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
854 (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
855 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
856 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
857
858 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
859 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
860
861 /*
862 * PLL is ON: check if defaults already set, then set those
863 * that can be updated in flight.
864 */
865 pllx_check_defaults(pllx);
866
867 /* Configure dyn ramp, disable lock override */
868 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
869
870 /* Enable lock detect */
871 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
872 val &= ~PLLX_MISC0_LOCK_ENABLE;
873 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
874 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
875 udelay(1);
876
877 return;
878 }
879
880 /* Enable lock detect and CPU output */
881 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
882 pllx->params->ext_misc_reg[0]);
883
884 /* Setup */
885 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
886 pllx->params->ext_misc_reg[1]);
887
888 /* Configure dyn ramp state machine, disable lock override */
889 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
890
891 /* Set IDDQ */
892 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
893 pllx->params->ext_misc_reg[3]);
894
895 /* Disable SDM */
896 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
897 pllx->params->ext_misc_reg[4]);
898 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
899 pllx->params->ext_misc_reg[5]);
900 udelay(1);
901}
902
903/* PLLMB */
904void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
905{
906 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
907
908 pllmb->params->defaults_set = true;
909
910 if (val & PLL_ENABLE) {
911 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
912
913 /*
914 * PLL is ON: check if defaults already set, then set those
915 * that can be updated in flight.
916 */
917 val = PLLMB_MISC0_DEFAULT_VALUE & (~PLLMB_MISC0_IDDQ);
918 mask = PLLMB_MISC0_LOCK_ENABLE | PLLMB_MISC0_LOCK_OVERRIDE;
919 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
920 ~mask & PLLMB_MISC0_WRITE_MASK);
921
922 /* Enable lock detect */
923 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
924 val &= ~mask;
925 val |= PLLMB_MISC0_DEFAULT_VALUE & mask;
926 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
927 udelay(1);
928
929 return;
930 }
931
932 /* set IDDQ, enable lock detect */
933 writel_relaxed(PLLMB_MISC0_DEFAULT_VALUE,
934 clk_base + pllmb->params->ext_misc_reg[0]);
935 udelay(1);
936}
937
938/*
939 * PLLP
940 * VCO is exposed to the clock tree directly along with post-divider output.
941 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
942 * respectively.
943 */
944static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
945{
946 u32 val, mask;
947
948 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
949 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
950 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
951 if (!enabled)
952 mask |= PLLP_MISC0_IDDQ;
953 _pll_misc_chk_default(clk_base, pll->params, 0, val,
954 ~mask & PLLP_MISC0_WRITE_MASK);
955
956 /* Ignore branch controls */
957 val = PLLP_MISC1_DEFAULT_VALUE;
958 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
959 _pll_misc_chk_default(clk_base, pll->params, 1, val,
960 ~mask & PLLP_MISC1_WRITE_MASK);
961}
962
963void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
964{
965 u32 mask;
966 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
967
968 pllp->params->defaults_set = true;
969
970 if (val & PLL_ENABLE) {
971 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
972
973 /*
974 * PLL is ON: check if defaults already set, then set those
975 * that can be updated in flight.
976 */
977 pllp_check_defaults(pllp, true);
978
979 /* Enable lock detect */
980 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
981 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
982 val &= ~mask;
983 val |= PLLP_MISC0_DEFAULT_VALUE & mask;
984 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
985 udelay(1);
986
987 return;
988 }
989
990 /* set IDDQ, enable lock detect */
991 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
992 clk_base + pllp->params->ext_misc_reg[0]);
993
994 /* Preserve branch control */
995 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
996 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
997 val &= mask;
998 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
999 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1000 udelay(1);
1001}
1002
1003/*
1004 * PLLU
1005 * VCO is exposed to the clock tree directly along with post-divider output.
1006 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1007 * respectively.
1008 */
1009static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control)
1010{
1011 u32 val, mask;
1012
1013 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1014 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1015 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1016 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1017 ~mask & PLLU_MISC0_WRITE_MASK);
1018
1019 val = PLLU_MISC1_DEFAULT_VALUE;
1020 mask = PLLU_MISC1_LOCK_OVERRIDE;
1021 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1022 ~mask & PLLU_MISC1_WRITE_MASK);
1023}
1024
1025void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
1026{
1027 u32 val = readl_relaxed(clk_base + pllu->params->base_reg);
1028
1029 pllu->params->defaults_set = true;
1030
1031 if (val & PLL_ENABLE) {
1032 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1033
1034 /*
1035 * PLL is ON: check if defaults already set, then set those
1036 * that can be updated in flight.
1037 */
1038 pllu_check_defaults(pllu, false);
1039
1040 /* Enable lock detect */
1041 val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]);
1042 val &= ~PLLU_MISC0_LOCK_ENABLE;
1043 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1044 writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[0]);
1045
1046 val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[1]);
1047 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1048 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1049 writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[1]);
1050 udelay(1);
1051
1052 return;
1053 }
1054
1055 /* set IDDQ, enable lock detect */
1056 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1057 clk_base + pllu->params->ext_misc_reg[0]);
1058 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1059 clk_base + pllu->params->ext_misc_reg[1]);
1060 udelay(1);
1061}
1062
1063#define mask(w) ((1 << (w)) - 1)
1064#define divm_mask(p) mask(p->params->div_nmp->divm_width)
1065#define divn_mask(p) mask(p->params->div_nmp->divn_width)
1066#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1067 mask(p->params->div_nmp->divp_width))
1068
1069#define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1070#define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1071#define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1072
1073#define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1074#define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1075#define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1076
1077#define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
1078static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
1079 u32 reg, u32 mask)
1080{
1081 int i;
1082 u32 val = 0;
1083
1084 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1085 udelay(PLL_LOCKDET_DELAY);
1086 val = readl_relaxed(clk_base + reg);
1087 if ((val & mask) == mask) {
1088 udelay(PLL_LOCKDET_DELAY);
1089 return 0;
1090 }
1091 }
1092 return -ETIMEDOUT;
1093}
1094
1095static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
1096 struct tegra_clk_pll_freq_table *cfg)
1097{
1098 u32 val, base, ndiv_new_mask;
1099
1100 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1101 << PLLX_MISC2_NDIV_NEW_SHIFT;
1102
1103 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1104 val &= (~ndiv_new_mask);
1105 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1106 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1107 udelay(1);
1108
1109 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1110 val |= PLLX_MISC2_EN_DYNRAMP;
1111 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1112 udelay(1);
1113
1114 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1115 PLLX_MISC2_DYNRAMP_DONE);
1116
1117 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1118 (~divn_mask_shifted(pllx));
1119 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1120 writel_relaxed(base, clk_base + pllx->params->base_reg);
1121 udelay(1);
1122
1123 val &= ~PLLX_MISC2_EN_DYNRAMP;
1124 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1125 udelay(1);
1126
1127 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1128 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1129 cfg->input_rate / cfg->m * cfg->n /
1130 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1131
1132 return 0;
1133}
1134
1135/*
1136 * Common configuration for PLLs with fixed input divider policy:
1137 * - always set fixed M-value based on the reference rate
1138 * - always set P-value value 1:1 for output rates above VCO minimum, and
1139 * choose minimum necessary P-value for output rates below VCO maximum
1140 * - calculate N-value based on selected M and P
1141 * - calculate SDM_DIN fractional part
1142 */
1143static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1144 struct tegra_clk_pll_freq_table *cfg,
1145 unsigned long rate, unsigned long input_rate)
1146{
1147 struct tegra_clk_pll *pll = to_clk_pll(hw);
1148 struct tegra_clk_pll_params *params = pll->params;
1149 int p;
1150 unsigned long cf, p_rate;
1151 u32 pdiv;
1152
1153 if (!rate)
1154 return -EINVAL;
1155
1156 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1157 p = DIV_ROUND_UP(params->vco_min, rate);
1158 p = params->round_p_to_pdiv(p, &pdiv);
1159 } else {
1160 p = rate >= params->vco_min ? 1 : -EINVAL;
1161 }
1162
1163 if (IS_ERR_VALUE(p))
1164 return -EINVAL;
1165
1166 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1167 cfg->p = p;
1168
1169 /* Store P as HW value, as that is what is expected */
1170 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1171
1172 p_rate = rate * p;
1173 if (p_rate > params->vco_max)
1174 p_rate = params->vco_max;
1175 cf = input_rate / cfg->m;
1176 cfg->n = p_rate / cf;
1177
1178 cfg->sdm_data = 0;
1179 if (params->sdm_ctrl_reg) {
1180 unsigned long rem = p_rate - cf * cfg->n;
1181 /* If ssc is enabled SDM enabled as well, even for integer n */
1182 if (rem || params->ssc_ctrl_reg) {
1183 u64 s = rem * PLL_SDM_COEFF;
1184
1185 do_div(s, cf);
1186 s -= PLL_SDM_COEFF / 2;
1187 cfg->sdm_data = sdin_din_to_data(s);
1188 }
1189 }
1190
1191 cfg->input_rate = input_rate;
1192 cfg->output_rate = rate;
1193
1194 return 0;
1195}
1196
1197/*
1198 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
1199 *
1200 * @cfg: struct tegra_clk_pll_freq_table * cfg
1201 *
1202 * For Normal mode:
1203 * Fvco = Fref * NDIV / MDIV
1204 *
1205 * For fractional mode:
1206 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
1207 */
1208static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1209{
1210 cfg->n = cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 +
1211 sdin_data_to_din(cfg->sdm_data);
1212 cfg->m *= PLL_SDM_COEFF;
1213}
1214
1215unsigned long tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1216 unsigned long parent_rate)
1217{
1218 unsigned long vco_min = params->vco_min;
1219
1220 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1221 vco_min = min(vco_min, params->vco_min);
1222
1223 return vco_min;
1224}
1225
1226static struct div_nmp pllx_nmp = {
1227 .divm_shift = 0,
1228 .divm_width = 8,
1229 .divn_shift = 8,
1230 .divn_width = 8,
1231 .divp_shift = 20,
1232 .divp_width = 5,
1233};
1234/*
1235 * PLL post divider maps - two types: quasi-linear and exponential
1236 * post divider.
1237 */
1238#define PLL_QLIN_PDIV_MAX 16
1239static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
1240 { .pdiv = 1, .hw_val = 0 },
1241 { .pdiv = 2, .hw_val = 1 },
1242 { .pdiv = 3, .hw_val = 2 },
1243 { .pdiv = 4, .hw_val = 3 },
1244 { .pdiv = 5, .hw_val = 4 },
1245 { .pdiv = 6, .hw_val = 5 },
1246 { .pdiv = 8, .hw_val = 6 },
1247 { .pdiv = 9, .hw_val = 7 },
1248 { .pdiv = 10, .hw_val = 8 },
1249 { .pdiv = 12, .hw_val = 9 },
1250 { .pdiv = 15, .hw_val = 10 },
1251 { .pdiv = 16, .hw_val = 11 },
1252 { .pdiv = 18, .hw_val = 12 },
1253 { .pdiv = 20, .hw_val = 13 },
1254 { .pdiv = 24, .hw_val = 14 },
1255 { .pdiv = 30, .hw_val = 15 },
1256 { .pdiv = 32, .hw_val = 16 },
1257};
1258
1259static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
1260{
1261 int i;
1262
1263 if (p) {
1264 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
1265 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
1266 if (pdiv)
1267 *pdiv = i;
1268 return pll_qlin_pdiv_to_hw[i].pdiv;
1269 }
1270 }
1271 }
1272
1273 return -EINVAL;
1274}
1275
1276#define PLL_EXPO_PDIV_MAX 7
1277static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
1278 { .pdiv = 1, .hw_val = 0 },
1279 { .pdiv = 2, .hw_val = 1 },
1280 { .pdiv = 4, .hw_val = 2 },
1281 { .pdiv = 8, .hw_val = 3 },
1282 { .pdiv = 16, .hw_val = 4 },
1283 { .pdiv = 32, .hw_val = 5 },
1284 { .pdiv = 64, .hw_val = 6 },
1285 { .pdiv = 128, .hw_val = 7 },
1286};
1287
1288static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1289{
1290 if (p) {
1291 u32 i = fls(p);
1292
1293 if (i == ffs(p))
1294 i--;
1295
1296 if (i <= PLL_EXPO_PDIV_MAX) {
1297 if (pdiv)
1298 *pdiv = i;
1299 return 1 << i;
1300 }
1301 }
1302 return -EINVAL;
1303}
1304
1305static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1306 /* 1 GHz */
1307 { 12000000, 1000000000, 166, 1, 1, 0 }, /* actual: 996.0 MHz */
1308 { 13000000, 1000000000, 153, 1, 1, 0 }, /* actual: 994.0 MHz */
1309 { 38400000, 1000000000, 156, 3, 1, 0 }, /* actual: 998.4 MHz */
1310 { 0, 0, 0, 0, 0, 0 },
1311};
1312
1313static struct tegra_clk_pll_params pll_x_params = {
1314 .input_min = 12000000,
1315 .input_max = 800000000,
1316 .cf_min = 12000000,
1317 .cf_max = 38400000,
1318 .vco_min = 1350000000,
1319 .vco_max = 3000000000UL,
1320 .base_reg = PLLX_BASE,
1321 .misc_reg = PLLX_MISC0,
1322 .lock_mask = PLL_BASE_LOCK,
1323 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
1324 .lock_delay = 300,
1325 .ext_misc_reg[0] = PLLX_MISC0,
1326 .ext_misc_reg[1] = PLLX_MISC1,
1327 .ext_misc_reg[2] = PLLX_MISC2,
1328 .ext_misc_reg[3] = PLLX_MISC3,
1329 .ext_misc_reg[4] = PLLX_MISC4,
1330 .ext_misc_reg[5] = PLLX_MISC5,
1331 .iddq_reg = PLLX_MISC3,
1332 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1333 .max_p = PLL_QLIN_PDIV_MAX,
1334 .mdiv_default = 2,
1335 .dyn_ramp_reg = PLLX_MISC2,
1336 .stepa_shift = 16,
1337 .stepb_shift = 24,
1338 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1339 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1340 .div_nmp = &pllx_nmp,
1341 .freq_table = pll_x_freq_table,
1342 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1343 .dyn_ramp = tegra210_pllx_dyn_ramp,
1344 .set_defaults = tegra210_pllx_set_defaults,
1345 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1346};
1347
1348static struct div_nmp pllc_nmp = {
1349 .divm_shift = 0,
1350 .divm_width = 8,
1351 .divn_shift = 10,
1352 .divn_width = 8,
1353 .divp_shift = 20,
1354 .divp_width = 5,
1355};
1356
1357static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1358 { 12000000, 510000000, 85, 1, 1, 0 },
1359 { 13000000, 510000000, 78, 1, 1, 0 }, /* actual: 507.0 MHz */
1360 { 38400000, 510000000, 79, 3, 1, 0 }, /* actual: 505.6 MHz */
1361 { 0, 0, 0, 0, 0, 0 },
1362};
1363
1364static struct tegra_clk_pll_params pll_c_params = {
1365 .input_min = 12000000,
1366 .input_max = 700000000,
1367 .cf_min = 12000000,
1368 .cf_max = 50000000,
1369 .vco_min = 600000000,
1370 .vco_max = 1200000000,
1371 .base_reg = PLLC_BASE,
1372 .misc_reg = PLLC_MISC0,
1373 .lock_mask = PLL_BASE_LOCK,
1374 .lock_delay = 300,
1375 .iddq_reg = PLLC_MISC1,
1376 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1377 .reset_reg = PLLC_MISC0,
1378 .reset_bit_idx = PLLCX_RESET_BIT,
1379 .max_p = PLL_QLIN_PDIV_MAX,
1380 .ext_misc_reg[0] = PLLC_MISC0,
1381 .ext_misc_reg[1] = PLLC_MISC1,
1382 .ext_misc_reg[2] = PLLC_MISC2,
1383 .ext_misc_reg[3] = PLLC_MISC3,
1384 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1385 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1386 .mdiv_default = 3,
1387 .div_nmp = &pllc_nmp,
1388 .freq_table = pll_cx_freq_table,
1389 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1390 .set_defaults = _pllc_set_defaults,
1391 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1392};
1393
1394static struct div_nmp pllcx_nmp = {
1395 .divm_shift = 0,
1396 .divm_width = 8,
1397 .divn_shift = 10,
1398 .divn_width = 8,
1399 .divp_shift = 20,
1400 .divp_width = 5,
1401};
1402
1403static struct tegra_clk_pll_params pll_c2_params = {
1404 .input_min = 12000000,
1405 .input_max = 700000000,
1406 .cf_min = 12000000,
1407 .cf_max = 50000000,
1408 .vco_min = 600000000,
1409 .vco_max = 1200000000,
1410 .base_reg = PLLC2_BASE,
1411 .misc_reg = PLLC2_MISC0,
1412 .iddq_reg = PLLC2_MISC1,
1413 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1414 .reset_reg = PLLC2_MISC0,
1415 .reset_bit_idx = PLLCX_RESET_BIT,
1416 .lock_mask = PLLCX_BASE_LOCK,
1417 .lock_delay = 300,
1418 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1419 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1420 .mdiv_default = 3,
1421 .div_nmp = &pllcx_nmp,
1422 .max_p = PLL_QLIN_PDIV_MAX,
1423 .ext_misc_reg[0] = PLLC2_MISC0,
1424 .ext_misc_reg[1] = PLLC2_MISC1,
1425 .ext_misc_reg[2] = PLLC2_MISC2,
1426 .ext_misc_reg[3] = PLLC2_MISC3,
1427 .freq_table = pll_cx_freq_table,
1428 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1429 .set_defaults = _pllc2_set_defaults,
1430 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1431};
1432
1433static struct tegra_clk_pll_params pll_c3_params = {
1434 .input_min = 12000000,
1435 .input_max = 700000000,
1436 .cf_min = 12000000,
1437 .cf_max = 50000000,
1438 .vco_min = 600000000,
1439 .vco_max = 1200000000,
1440 .base_reg = PLLC3_BASE,
1441 .misc_reg = PLLC3_MISC0,
1442 .lock_mask = PLLCX_BASE_LOCK,
1443 .lock_delay = 300,
1444 .iddq_reg = PLLC3_MISC1,
1445 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1446 .reset_reg = PLLC3_MISC0,
1447 .reset_bit_idx = PLLCX_RESET_BIT,
1448 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1449 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1450 .mdiv_default = 3,
1451 .div_nmp = &pllcx_nmp,
1452 .max_p = PLL_QLIN_PDIV_MAX,
1453 .ext_misc_reg[0] = PLLC3_MISC0,
1454 .ext_misc_reg[1] = PLLC3_MISC1,
1455 .ext_misc_reg[2] = PLLC3_MISC2,
1456 .ext_misc_reg[3] = PLLC3_MISC3,
1457 .freq_table = pll_cx_freq_table,
1458 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1459 .set_defaults = _pllc3_set_defaults,
1460 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1461};
1462
1463static struct div_nmp pllss_nmp = {
1464 .divm_shift = 0,
1465 .divm_width = 8,
1466 .divn_shift = 8,
1467 .divn_width = 8,
1468 .divp_shift = 19,
1469 .divp_width = 5,
1470};
1471
1472static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1473 { 12000000, 600000000, 50, 1, 0, 0 },
1474 { 13000000, 600000000, 46, 1, 0, 0 }, /* actual: 598.0 MHz */
1475 { 38400000, 600000000, 62, 4, 0, 0 }, /* actual: 595.2 MHz */
1476 { 0, 0, 0, 0, 0, 0 },
1477};
1478
1479static const struct clk_div_table pll_vco_post_div_table[] = {
1480 { .val = 0, .div = 1 },
1481 { .val = 1, .div = 2 },
1482 { .val = 2, .div = 3 },
1483 { .val = 3, .div = 4 },
1484 { .val = 4, .div = 5 },
1485 { .val = 5, .div = 6 },
1486 { .val = 6, .div = 8 },
1487 { .val = 7, .div = 10 },
1488 { .val = 8, .div = 12 },
1489 { .val = 9, .div = 16 },
1490 { .val = 10, .div = 12 },
1491 { .val = 11, .div = 16 },
1492 { .val = 12, .div = 20 },
1493 { .val = 13, .div = 24 },
1494 { .val = 14, .div = 32 },
1495 { .val = 0, .div = 0 },
1496};
1497
1498static struct tegra_clk_pll_params pll_c4_vco_params = {
1499 .input_min = 9600000,
1500 .input_max = 800000000,
1501 .cf_min = 9600000,
1502 .cf_max = 19200000,
1503 .vco_min = 500000000,
1504 .vco_max = 1080000000,
1505 .base_reg = PLLC4_BASE,
1506 .misc_reg = PLLC4_MISC0,
1507 .lock_mask = PLL_BASE_LOCK,
1508 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
1509 .lock_delay = 300,
1510 .max_p = PLL_QLIN_PDIV_MAX,
1511 .ext_misc_reg[0] = PLLC4_MISC0,
1512 .iddq_reg = PLLC4_BASE,
1513 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1514 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1515 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1516 .mdiv_default = 3,
1517 .div_nmp = &pllss_nmp,
1518 .freq_table = pll_c4_vco_freq_table,
1519 .set_defaults = tegra210_pllc4_set_defaults,
1520 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
1521 TEGRA_PLL_VCO_OUT,
1522 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1523};
1524
1525static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1526 { 12000000, 800000000, 66, 1, 0, 0 }, /* actual: 792.0 MHz */
1527 { 13000000, 800000000, 61, 1, 0, 0 }, /* actual: 793.0 MHz */
1528 { 38400000, 297600000, 93, 4, 2, 0 },
1529 { 38400000, 400000000, 125, 4, 2, 0 },
1530 { 38400000, 532800000, 111, 4, 1, 0 },
1531 { 38400000, 665600000, 104, 3, 1, 0 },
1532 { 38400000, 800000000, 125, 3, 1, 0 },
1533 { 38400000, 931200000, 97, 4, 0, 0 },
1534 { 38400000, 1065600000, 111, 4, 0, 0 },
1535 { 38400000, 1200000000, 125, 4, 0, 0 },
1536 { 38400000, 1331200000, 104, 3, 0, 0 },
1537 { 38400000, 1459200000, 76, 2, 0, 0 },
1538 { 38400000, 1600000000, 125, 3, 0, 0 },
1539 { 0, 0, 0, 0, 0, 0 },
1540};
1541
1542static struct div_nmp pllm_nmp = {
1543 .divm_shift = 0,
1544 .divm_width = 8,
1545 .override_divm_shift = 0,
1546 .divn_shift = 8,
1547 .divn_width = 8,
1548 .override_divn_shift = 8,
1549 .divp_shift = 20,
1550 .divp_width = 5,
1551 .override_divp_shift = 27,
1552};
1553
1554static struct tegra_clk_pll_params pll_m_params = {
1555 .input_min = 9600000,
1556 .input_max = 500000000,
1557 .cf_min = 9600000,
1558 .cf_max = 19200000,
1559 .vco_min = 800000000,
1560 .vco_max = 1866000000,
1561 .base_reg = PLLM_BASE,
1562 .misc_reg = PLLM_MISC1,
1563 .lock_mask = PLL_BASE_LOCK,
1564 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
1565 .lock_delay = 300,
1566 .iddq_reg = PLLM_MISC0,
1567 .iddq_bit_idx = PLLM_IDDQ_BIT,
1568 .max_p = PLL_QLIN_PDIV_MAX,
1569 .ext_misc_reg[0] = PLLM_MISC0,
1570 .ext_misc_reg[0] = PLLM_MISC1,
1571 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1572 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1573 .div_nmp = &pllm_nmp,
1574 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
1575 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
1576 .freq_table = pll_m_freq_table,
1577 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1578 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1579};
1580
1581static struct tegra_clk_pll_params pll_mb_params = {
1582 .input_min = 9600000,
1583 .input_max = 500000000,
1584 .cf_min = 9600000,
1585 .cf_max = 19200000,
1586 .vco_min = 800000000,
1587 .vco_max = 1866000000,
1588 .base_reg = PLLMB_BASE,
1589 .misc_reg = PLLMB_MISC0,
1590 .lock_mask = PLL_BASE_LOCK,
1591 .lock_enable_bit_idx = PLLMB_MISC_LOCK_ENABLE,
1592 .lock_delay = 300,
1593 .iddq_reg = PLLMB_MISC0,
1594 .iddq_bit_idx = PLLMB_IDDQ_BIT,
1595 .max_p = PLL_QLIN_PDIV_MAX,
1596 .ext_misc_reg[0] = PLLMB_MISC0,
1597 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1598 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1599 .div_nmp = &pllm_nmp,
1600 .freq_table = pll_m_freq_table,
1601 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1602 .set_defaults = tegra210_pllmb_set_defaults,
1603 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1604};
1605
1606
1607static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
1608 /* PLLE special case: use cpcon field to store cml divider value */
1609 { 672000000, 100000000, 125, 42, 0, 13 },
1610 { 624000000, 100000000, 125, 39, 0, 13 },
1611 { 336000000, 100000000, 125, 21, 0, 13 },
1612 { 312000000, 100000000, 200, 26, 0, 14 },
1613 { 38400000, 100000000, 125, 2, 0, 14 },
1614 { 12000000, 100000000, 200, 1, 0, 14 },
1615 { 0, 0, 0, 0, 0, 0 },
1616};
1617
1618static struct div_nmp plle_nmp = {
1619 .divm_shift = 0,
1620 .divm_width = 8,
1621 .divn_shift = 8,
1622 .divn_width = 8,
1623 .divp_shift = 24,
1624 .divp_width = 5,
1625};
1626
1627static struct tegra_clk_pll_params pll_e_params = {
1628 .input_min = 12000000,
1629 .input_max = 800000000,
1630 .cf_min = 12000000,
1631 .cf_max = 38400000,
1632 .vco_min = 1600000000,
1633 .vco_max = 2500000000U,
1634 .base_reg = PLLE_BASE,
1635 .misc_reg = PLLE_MISC0,
1636 .aux_reg = PLLE_AUX,
1637 .lock_mask = PLLE_MISC_LOCK,
1638 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
1639 .lock_delay = 300,
1640 .div_nmp = &plle_nmp,
1641 .freq_table = pll_e_freq_table,
1642 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1643 TEGRA_PLL_HAS_LOCK_ENABLE,
1644 .fixed_rate = 100000000,
1645 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1646};
1647
1648static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1649 { 12000000, 672000000, 56, 1, 0, 0 },
1650 { 13000000, 672000000, 51, 1, 0, 0 }, /* actual: 663.0 MHz */
1651 { 38400000, 672000000, 70, 4, 0, 0 },
1652 { 0, 0, 0, 0, 0, 0 },
1653};
1654
1655static struct div_nmp pllre_nmp = {
1656 .divm_shift = 0,
1657 .divm_width = 8,
1658 .divn_shift = 8,
1659 .divn_width = 8,
1660 .divp_shift = 16,
1661 .divp_width = 5,
1662};
1663
1664static struct tegra_clk_pll_params pll_re_vco_params = {
1665 .input_min = 9600000,
1666 .input_max = 800000000,
1667 .cf_min = 9600000,
1668 .cf_max = 19200000,
1669 .vco_min = 350000000,
1670 .vco_max = 700000000,
1671 .base_reg = PLLRE_BASE,
1672 .misc_reg = PLLRE_MISC0,
1673 .lock_mask = PLLRE_MISC_LOCK,
1674 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
1675 .lock_delay = 300,
1676 .max_p = PLL_QLIN_PDIV_MAX,
1677 .ext_misc_reg[0] = PLLRE_MISC0,
1678 .iddq_reg = PLLRE_MISC0,
1679 .iddq_bit_idx = PLLRE_IDDQ_BIT,
1680 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1681 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1682 .div_nmp = &pllre_nmp,
1683 .freq_table = pll_re_vco_freq_table,
1684 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC |
1685 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT,
1686 .set_defaults = tegra210_pllre_set_defaults,
1687 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1688};
1689
1690static struct div_nmp pllp_nmp = {
1691 .divm_shift = 0,
1692 .divm_width = 8,
1693 .divn_shift = 10,
1694 .divn_width = 8,
1695 .divp_shift = 20,
1696 .divp_width = 5,
1697};
1698
1699static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1700 { 12000000, 408000000, 34, 1, 0, 0 },
1701 { 38400000, 408000000, 85, 8, 0, 0 }, /* cf = 4.8MHz, allowed exception */
1702 { 0, 0, 0, 0, 0, 0 },
1703};
1704
1705static struct tegra_clk_pll_params pll_p_params = {
1706 .input_min = 9600000,
1707 .input_max = 800000000,
1708 .cf_min = 9600000,
1709 .cf_max = 19200000,
1710 .vco_min = 350000000,
1711 .vco_max = 700000000,
1712 .base_reg = PLLP_BASE,
1713 .misc_reg = PLLP_MISC0,
1714 .lock_mask = PLL_BASE_LOCK,
1715 .lock_enable_bit_idx = PLLP_MISC_LOCK_ENABLE,
1716 .lock_delay = 300,
1717 .iddq_reg = PLLP_MISC0,
1718 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1719 .ext_misc_reg[0] = PLLP_MISC0,
1720 .ext_misc_reg[1] = PLLP_MISC1,
1721 .div_nmp = &pllp_nmp,
1722 .freq_table = pll_p_freq_table,
1723 .fixed_rate = 408000000,
1724 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
1725 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT,
1726 .set_defaults = tegra210_pllp_set_defaults,
1727 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1728};
1729
1730static struct tegra_clk_pll_params pll_a1_params = {
1731 .input_min = 12000000,
1732 .input_max = 700000000,
1733 .cf_min = 12000000,
1734 .cf_max = 50000000,
1735 .vco_min = 600000000,
1736 .vco_max = 1200000000,
1737 .base_reg = PLLA1_BASE,
1738 .misc_reg = PLLA1_MISC0,
1739 .lock_mask = PLLCX_BASE_LOCK,
1740 .lock_delay = 300,
1741 .iddq_reg = PLLA1_MISC0,
1742 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1743 .reset_reg = PLLA1_MISC0,
1744 .reset_bit_idx = PLLCX_RESET_BIT,
1745 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1746 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1747 .div_nmp = &pllc_nmp,
1748 .ext_misc_reg[0] = PLLA1_MISC0,
1749 .ext_misc_reg[1] = PLLA1_MISC1,
1750 .ext_misc_reg[2] = PLLA1_MISC2,
1751 .ext_misc_reg[3] = PLLA1_MISC3,
1752 .freq_table = pll_cx_freq_table,
1753 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1754 .set_defaults = _plla1_set_defaults,
1755 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1756};
1757
1758static struct div_nmp plla_nmp = {
1759 .divm_shift = 0,
1760 .divm_width = 8,
1761 .divn_shift = 8,
1762 .divn_width = 8,
1763 .divp_shift = 20,
1764 .divp_width = 5,
1765};
1766
1767static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
1768 { 12000000, 282240000, 47, 1, 1, 1, 0xf148 }, /* actual: 282240234 */
1769 { 12000000, 368640000, 61, 1, 1, 1, 0xfe15 }, /* actual: 368640381 */
1770 { 12000000, 240000000, 60, 1, 2, 1, 0 },
1771 { 13000000, 282240000, 43, 1, 1, 1, 0xfd7d }, /* actual: 282239807 */
1772 { 13000000, 368640000, 56, 1, 1, 1, 0x06d8 }, /* actual: 368640137 */
1773 { 13000000, 240000000, 55, 1, 2, 1, 0 }, /* actual: 238.3 MHz */
1774 { 38400000, 282240000, 44, 3, 1, 1, 0xf333 }, /* actual: 282239844 */
1775 { 38400000, 368640000, 57, 3, 1, 1, 0x0333 }, /* actual: 368639844 */
1776 { 38400000, 240000000, 75, 3, 3, 1, 0 },
1777 { 0, 0, 0, 0, 0, 0, 0 },
1778};
1779
1780static struct tegra_clk_pll_params pll_a_params = {
1781 .input_min = 12000000,
1782 .input_max = 800000000,
1783 .cf_min = 12000000,
1784 .cf_max = 19200000,
1785 .vco_min = 500000000,
1786 .vco_max = 1000000000,
1787 .base_reg = PLLA_BASE,
1788 .misc_reg = PLLA_MISC0,
1789 .lock_mask = PLL_BASE_LOCK,
1790 .lock_enable_bit_idx = PLLA_MISC_LOCK_ENABLE,
1791 .lock_delay = 300,
1792 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1793 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1794 .iddq_reg = PLLA_BASE,
1795 .iddq_bit_idx = PLLA_IDDQ_BIT,
1796 .div_nmp = &plla_nmp,
1797 .sdm_din_reg = PLLA_MISC1,
1798 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1799 .sdm_ctrl_reg = PLLA_MISC2,
1800 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
1801 .ext_misc_reg[0] = PLLA_MISC0,
1802 .ext_misc_reg[1] = PLLA_MISC1,
1803 .ext_misc_reg[2] = PLLA_MISC2,
1804 .freq_table = pll_a_freq_table,
1805 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW |
1806 TEGRA_PLL_HAS_LOCK_ENABLE,
1807 .set_defaults = tegra210_plla_set_defaults,
1808 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1809 .set_gain = tegra210_clk_pll_set_gain,
1810 .adjust_vco = tegra210_clk_adjust_vco_min,
1811};
1812
1813static struct div_nmp plld_nmp = {
1814 .divm_shift = 0,
1815 .divm_width = 8,
1816 .divn_shift = 11,
1817 .divn_width = 8,
1818 .divp_shift = 20,
1819 .divp_width = 3,
1820};
1821
1822static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
1823 { 12000000, 594000000, 99, 1, 1, 0, 0 },
1824 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1825 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1826 { 0, 0, 0, 0, 0, 0, 0 },
1827};
1828
1829static struct tegra_clk_pll_params pll_d_params = {
1830 .input_min = 12000000,
1831 .input_max = 800000000,
1832 .cf_min = 12000000,
1833 .cf_max = 38400000,
1834 .vco_min = 750000000,
1835 .vco_max = 1500000000,
1836 .base_reg = PLLD_BASE,
1837 .misc_reg = PLLD_MISC0,
1838 .lock_mask = PLL_BASE_LOCK,
1839 .lock_enable_bit_idx = PLLD_MISC_LOCK_ENABLE,
1840 .lock_delay = 1000,
1841 .iddq_reg = PLLD_MISC0,
1842 .iddq_bit_idx = PLLD_IDDQ_BIT,
1843 .round_p_to_pdiv = pll_expo_p_to_pdiv,
1844 .pdiv_tohw = pll_expo_pdiv_to_hw,
1845 .div_nmp = &plld_nmp,
1846 .sdm_din_reg = PLLD_MISC0,
1847 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1848 .sdm_ctrl_reg = PLLD_MISC0,
1849 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
1850 .ext_misc_reg[0] = PLLD_MISC0,
1851 .ext_misc_reg[1] = PLLD_MISC1,
1852 .freq_table = pll_d_freq_table,
1853 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1854 .mdiv_default = 1,
1855 .set_defaults = tegra210_plld_set_defaults,
1856 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1857 .set_gain = tegra210_clk_pll_set_gain,
1858 .adjust_vco = tegra210_clk_adjust_vco_min,
1859};
1860
1861static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
1862 { 12000000, 594000000, 99, 1, 1, 0, 0xf000 },
1863 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1864 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1865 { 0, 0, 0, 0, 0, 0, 0 },
1866};
1867
1868/* s/w policy, always tegra_pll_ref */
1869static struct tegra_clk_pll_params pll_d2_params = {
1870 .input_min = 12000000,
1871 .input_max = 800000000,
1872 .cf_min = 12000000,
1873 .cf_max = 38400000,
1874 .vco_min = 750000000,
1875 .vco_max = 1500000000,
1876 .base_reg = PLLD2_BASE,
1877 .misc_reg = PLLD2_MISC0,
1878 .lock_mask = PLL_BASE_LOCK,
1879 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
1880 .lock_delay = 300,
1881 .iddq_reg = PLLD2_BASE,
1882 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1883 .sdm_din_reg = PLLD2_MISC3,
1884 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1885 .sdm_ctrl_reg = PLLD2_MISC1,
1886 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
1887 .ssc_ctrl_reg = PLLD2_MISC1,
1888 .ssc_ctrl_en_mask = PLLD2_SSC_EN_MASK,
1889 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1890 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1891 .div_nmp = &pllss_nmp,
1892 .ext_misc_reg[0] = PLLD2_MISC0,
1893 .ext_misc_reg[1] = PLLD2_MISC1,
1894 .ext_misc_reg[2] = PLLD2_MISC2,
1895 .ext_misc_reg[3] = PLLD2_MISC3,
1896 .max_p = PLL_QLIN_PDIV_MAX,
1897 .mdiv_default = 1,
1898 .freq_table = tegra210_pll_d2_freq_table,
1899 .set_defaults = tegra210_plld2_set_defaults,
1900 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1901 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1902 .set_gain = tegra210_clk_pll_set_gain,
1903 .adjust_vco = tegra210_clk_adjust_vco_min,
1904};
1905
1906static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
1907 { 12000000, 270000000, 90, 1, 3, 0, 0xf000 },
1908 { 13000000, 270000000, 83, 1, 3, 0, 0xf000 }, /* actual: 269.8 MHz */
1909 { 38400000, 270000000, 28, 1, 3, 0, 0xf400 },
1910 { 0, 0, 0, 0, 0, 0, 0 },
1911};
1912
1913static struct tegra_clk_pll_params pll_dp_params = {
1914 .input_min = 12000000,
1915 .input_max = 800000000,
1916 .cf_min = 12000000,
1917 .cf_max = 38400000,
1918 .vco_min = 750000000,
1919 .vco_max = 1500000000,
1920 .base_reg = PLLDP_BASE,
1921 .misc_reg = PLLDP_MISC,
1922 .lock_mask = PLL_BASE_LOCK,
1923 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
1924 .lock_delay = 300,
1925 .iddq_reg = PLLDP_BASE,
1926 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1927 .sdm_din_reg = PLLDP_SS_CTRL2,
1928 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1929 .sdm_ctrl_reg = PLLDP_SS_CFG,
1930 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
1931 .ssc_ctrl_reg = PLLDP_SS_CFG,
1932 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
1933 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1934 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1935 .div_nmp = &pllss_nmp,
1936 .ext_misc_reg[0] = PLLDP_MISC,
1937 .ext_misc_reg[1] = PLLDP_SS_CFG,
1938 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
1939 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
1940 .max_p = PLL_QLIN_PDIV_MAX,
1941 .mdiv_default = 1,
1942 .freq_table = pll_dp_freq_table,
1943 .set_defaults = tegra210_plldp_set_defaults,
1944 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1945 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1946 .set_gain = tegra210_clk_pll_set_gain,
1947 .adjust_vco = tegra210_clk_adjust_vco_min,
1948};
1949
1950static struct div_nmp pllu_nmp = {
1951 .divm_shift = 0,
1952 .divm_width = 8,
1953 .divn_shift = 8,
1954 .divn_width = 8,
1955 .divp_shift = 16,
1956 .divp_width = 5,
1957};
1958
1959static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
1960 { 12000000, 480000000, 40, 1, 0, 0 },
1961 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
1962 { 38400000, 480000000, 25, 2, 0, 0 },
1963 { 0, 0, 0, 0, 0, 0 },
1964};
1965
1966static struct tegra_clk_pll_params pll_u_vco_params = {
1967 .input_min = 9600000,
1968 .input_max = 800000000,
1969 .cf_min = 9600000,
1970 .cf_max = 19200000,
1971 .vco_min = 350000000,
1972 .vco_max = 700000000,
1973 .base_reg = PLLU_BASE,
1974 .misc_reg = PLLU_MISC0,
1975 .lock_mask = PLL_BASE_LOCK,
1976 .lock_enable_bit_idx = PLLU_MISC_LOCK_ENABLE,
1977 .lock_delay = 1000,
1978 .iddq_reg = PLLU_MISC0,
1979 .iddq_bit_idx = PLLU_IDDQ_BIT,
1980 .ext_misc_reg[0] = PLLU_MISC0,
1981 .ext_misc_reg[1] = PLLU_MISC1,
1982 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1983 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1984 .div_nmp = &pllu_nmp,
1985 .freq_table = pll_u_freq_table,
1986 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
1987 TEGRA_PLL_VCO_OUT,
1988 .set_defaults = tegra210_pllu_set_defaults,
1989 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1990};
1991
1992struct utmi_clk_param {
1993 /* Oscillator Frequency in KHz */
1994 u32 osc_frequency;
1995 /* UTMIP PLL Enable Delay Count */
1996 u8 enable_delay_count;
1997 /* UTMIP PLL Stable count */
1998 u16 stable_count;
1999 /* UTMIP PLL Active delay count */
2000 u8 active_delay_count;
2001 /* UTMIP PLL Xtal frequency count */
2002 u16 xtal_freq_count;
2003};
2004
2005static const struct utmi_clk_param utmi_parameters[] = {
2006 {
2007 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2008 .stable_count = 0x0, .active_delay_count = 0x6,
2009 .xtal_freq_count = 0x80
2010 }, {
2011 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2012 .stable_count = 0x33, .active_delay_count = 0x05,
2013 .xtal_freq_count = 0x7f
2014 }, {
2015 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2016 .stable_count = 0x4b, .active_delay_count = 0x06,
2017 .xtal_freq_count = 0xbb
2018 }, {
2019 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2020 .stable_count = 0x2f, .active_delay_count = 0x08,
2021 .xtal_freq_count = 0x76
2022 }, {
2023 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2024 .stable_count = 0x66, .active_delay_count = 0x09,
2025 .xtal_freq_count = 0xfe
2026 }, {
2027 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2028 .stable_count = 0x41, .active_delay_count = 0x0a,
2029 .xtal_freq_count = 0xa4
2030 },
2031};
2032
2033static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2034 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2035 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
2036 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
2037 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
2038 [tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true },
2039 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
2040 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
2041 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
2042 [tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true },
2043 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
2044 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
2045 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
2046 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
2047 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
2048 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
2049 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
2050 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
2051 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
2052 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
2053 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
2054 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
2055 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
2056 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
2057 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
2058 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
2059 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
2060 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
2061 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true },
2062 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
2063 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
2064 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
2065 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
2066 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
2067 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
2068 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
2069 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
2070 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
2071 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
2072 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
2073 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
2074 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
2075 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
2076 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
2077 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
2078 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
2079 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
2080 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
2081 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
2082 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
2083 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
2084 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
2085 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
2086 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
2087 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
2088 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
2089 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
2090 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
2091 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
2092 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
2093 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
2094 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
2095 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
2096 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
2097 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
2098 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
2099 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
2100 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
2101 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2102 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2103 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2104 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2105 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2106 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2107 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2108 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2109 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2110 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2111 [tegra_clk_vfir] = { .dt_id = TEGRA210_CLK_VFIR, .present = true },
2112 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2113 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2114 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2115 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
2116 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
2117 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
2118 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
2119 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2120 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
2121 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
2122 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
2123 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
2124 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
2125 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2126 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2127 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2128 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true },
2129 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2130 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2131 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
2132 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
2133 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
2134 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
2135 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
2136 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
2137 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
2138 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2139 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
2140 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
2141 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
2142 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
2143 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
2144 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
2145 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
2146 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
2147 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
2148 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
2149 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
2150 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
2151 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
2152 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
2153 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
2154 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
2155 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
2156 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
2157 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
2158 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
2159 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
2160 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
2161 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
2162 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
2163 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
2164 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
2165 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
2166 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2167 [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
2168 [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
2169 [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
2170 [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
2171 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
2172 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
2173 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
2174 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
2175 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
2176 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
2177 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
2178 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
2179 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
2180 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
2181 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
2182 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
2183 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
2184 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
2185 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
2186 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
2187 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
2188 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
2189 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
2190 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
2191 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
2192 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
2193 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
2194 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
2195 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
2196 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
2197 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
2198 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
2199 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
2200 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
2201 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2202 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
2203 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
2204 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
2205 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
2206 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
2207 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
2208 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
2209 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
2210 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
2211 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
2212 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
2213 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
2214 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
2215 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
2216 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
2217 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2218 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
2219 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2220 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2221};
2222
2223static struct tegra_devclk devclks[] __initdata = {
2224 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2225 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2226 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2227 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2228 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
2229 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2230 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2231 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2232 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2233 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2234 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2235 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2236 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2237 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2238 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2239 { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 },
2240 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2241 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2242 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2243 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2244 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2245 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2246 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2247 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2248 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2249 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2250 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2251 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2252 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2253 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2254 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2255 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2256 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2257 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2258 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2259 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2260 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2261 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2262 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2263 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2264 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2265 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2266 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2267 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2268 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2269 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2270 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2271 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
2272 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
2273 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
2274 { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
2275 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2276 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2277 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2278 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2279 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2280 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2281 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
2282 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
2283 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2284 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2285 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2286 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2287 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
2288 { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 },
2289};
2290
2291static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2292 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2293 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
2294};
2295
2296static struct clk **clks;
2297
2298static void tegra210_utmi_param_configure(void __iomem *clk_base)
2299{
2300 u32 reg;
2301 int i;
2302
2303 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2304 if (osc_freq == utmi_parameters[i].osc_frequency)
2305 break;
2306 }
2307
2308 if (i >= ARRAY_SIZE(utmi_parameters)) {
2309 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2310 osc_freq);
2311 return;
2312 }
2313
2314 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2315 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2316 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2317 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2318 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2319 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2320 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2321
2322 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2323 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2324 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2325 udelay(1);
2326
2327 reg = readl_relaxed(clk_base + PLLU_BASE);
2328 reg &= ~PLLU_BASE_CLKENABLE_USB;
2329 writel_relaxed(reg, clk_base + PLLU_BASE);
2330
2331 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2332 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2333 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2334
2335 udelay(10);
2336
2337 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2338
2339 /* Program UTMIP PLL stable and active counts */
2340 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2341 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2342 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2343
2344 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2345
2346 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
2347 active_delay_count);
2348 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2349
2350 /* Program UTMIP PLL delay and oscillator frequency counts */
2351 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2352 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2353
2354 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
2355 enable_delay_count);
2356
2357 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2358 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
2359 xtal_freq_count);
2360
2361 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2362 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2363
2364 /* Remove power downs from UTMIP PLL control bits */
2365 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2366 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2367 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2368 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2369 udelay(1);
2370
2371 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2372 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2373 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2374 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2375 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2376 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2377 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2378 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2379 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2380
2381 /* Setup HW control of UTMIPLL */
2382 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2383 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2384 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2385 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2386
2387 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2388 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2389 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2390 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2391
2392 udelay(1);
2393
2394 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2395 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2396 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2397
2398 udelay(1);
2399
2400 /* Enable HW control UTMIPLL */
2401 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2402 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2403 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2404}
2405
2406static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2407 void __iomem *pmc_base)
2408{
2409 struct clk *clk;
2410
2411 /* xusb_ss_div2 */
2412 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
2413 1, 2);
2414 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2415
2416 /* pll_d_dsi_out */
2417 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
2418 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
2419 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
2420
2421 /* dsia */
2422 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
2423 clk_base, 0, 48,
2424 periph_clk_enb_refcnt);
2425 clks[TEGRA210_CLK_DSIA] = clk;
2426
2427 /* dsib */
2428 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
2429 clk_base, 0, 82,
2430 periph_clk_enb_refcnt);
2431 clks[TEGRA210_CLK_DSIB] = clk;
2432
2433 /* emc mux */
2434 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2435 ARRAY_SIZE(mux_pllmcp_clkm), 0,
2436 clk_base + CLK_SOURCE_EMC,
2437 29, 3, 0, &emc_lock);
2438
2439 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
2440 &emc_lock);
2441 clks[TEGRA210_CLK_MC] = clk;
2442
2443 /* cml0 */
2444 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
2445 0, 0, &pll_e_lock);
2446 clk_register_clkdev(clk, "cml0", NULL);
2447 clks[TEGRA210_CLK_CML0] = clk;
2448
2449 /* cml1 */
2450 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
2451 1, 0, &pll_e_lock);
2452 clk_register_clkdev(clk, "cml1", NULL);
2453 clks[TEGRA210_CLK_CML1] = clk;
2454
2455 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
2456}
2457
2458static void __init tegra210_pll_init(void __iomem *clk_base,
2459 void __iomem *pmc)
2460{
2461 u32 val;
2462 struct clk *clk;
2463
2464 /* PLLC */
2465 clk = tegra_clk_register_pllxc_tegra210("pll_c", "pll_ref", clk_base,
2466 pmc, 0, &pll_c_params, NULL);
2467 if (!WARN_ON(IS_ERR(clk)))
2468 clk_register_clkdev(clk, "pll_c", NULL);
2469 clks[TEGRA210_CLK_PLL_C] = clk;
2470
2471 /* PLLC_OUT1 */
2472 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
2473 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
2474 8, 8, 1, NULL);
2475 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
2476 clk_base + PLLC_OUT, 1, 0,
2477 CLK_SET_RATE_PARENT, 0, NULL);
2478 clk_register_clkdev(clk, "pll_c_out1", NULL);
2479 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
2480
2481 /* PLLC_UD */
2482 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
2483 CLK_SET_RATE_PARENT, 1, 1);
2484 clk_register_clkdev(clk, "pll_c_ud", NULL);
2485 clks[TEGRA210_CLK_PLL_C_UD] = clk;
2486
2487 /* PLLC2 */
2488 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
2489 pmc, 0, &pll_c2_params, NULL);
2490 clk_register_clkdev(clk, "pll_c2", NULL);
2491 clks[TEGRA210_CLK_PLL_C2] = clk;
2492
2493 /* PLLC3 */
2494 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
2495 pmc, 0, &pll_c3_params, NULL);
2496 clk_register_clkdev(clk, "pll_c3", NULL);
2497 clks[TEGRA210_CLK_PLL_C3] = clk;
2498
2499 /* PLLM */
2500 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
2501 CLK_SET_RATE_GATE, &pll_m_params, NULL);
2502 clk_register_clkdev(clk, "pll_m", NULL);
2503 clks[TEGRA210_CLK_PLL_M] = clk;
2504
2505 /* PLLMB */
2506 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
2507 CLK_SET_RATE_GATE, &pll_mb_params, NULL);
2508 clk_register_clkdev(clk, "pll_mb", NULL);
2509 clks[TEGRA210_CLK_PLL_MB] = clk;
2510
2511 clk_register_clkdev(clk, "pll_m_out1", NULL);
2512 clks[TEGRA210_CLK_PLL_M_OUT1] = clk;
2513
2514 /* PLLM_UD */
2515 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
2516 CLK_SET_RATE_PARENT, 1, 1);
2517 clk_register_clkdev(clk, "pll_m_ud", NULL);
2518 clks[TEGRA210_CLK_PLL_M_UD] = clk;
2519
2520 /* PLLU_VCO */
2521 val = readl(clk_base + pll_u_vco_params.base_reg);
2522 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
2523 writel(val, clk_base + pll_u_vco_params.base_reg);
2524
2525 clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
2526 0, &pll_u_vco_params, &pll_u_lock, pll_ref_freq);
2527 clk_register_clkdev(clk, "pll_u_vco", NULL);
2528 clks[TEGRA210_CLK_PLL_U] = clk;
2529
2530 /* PLLU_OUT */
2531 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
2532 clk_base + PLLU_BASE, 16, 4, 0,
2533 pll_vco_post_div_table, NULL);
2534 clk_register_clkdev(clk, "pll_u_out", NULL);
2535 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
2536
2537 /* PLLU_OUT1 */
2538 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
2539 clk_base + PLLU_OUTA, 0,
2540 TEGRA_DIVIDER_ROUND_UP,
2541 8, 8, 1, &pll_u_lock);
2542 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
2543 clk_base + PLLU_OUTA, 1, 0,
2544 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
2545 clk_register_clkdev(clk, "pll_u_out1", NULL);
2546 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
2547
2548 /* PLLU_OUT2 */
2549 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
2550 clk_base + PLLU_OUTA, 0,
2551 TEGRA_DIVIDER_ROUND_UP,
2552 24, 8, 1, &pll_u_lock);
2553 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
2554 clk_base + PLLU_OUTA, 17, 16,
2555 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
2556 clk_register_clkdev(clk, "pll_u_out2", NULL);
2557 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
2558
2559 tegra210_utmi_param_configure(clk_base);
2560
2561 /* PLLU_480M */
2562 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
2563 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
2564 22, 0, &pll_u_lock);
2565 clk_register_clkdev(clk, "pll_u_480M", NULL);
2566 clks[TEGRA210_CLK_PLL_U_480M] = clk;
2567
2568 /* PLLU_60M */
2569 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
2570 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
2571 23, 0, NULL);
2572 clk_register_clkdev(clk, "pll_u_60M", NULL);
2573 clks[TEGRA210_CLK_PLL_U_60M] = clk;
2574
2575 /* PLLU_48M */
2576 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
2577 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
2578 25, 0, NULL);
2579 clk_register_clkdev(clk, "pll_u_48M", NULL);
2580 clks[TEGRA210_CLK_PLL_U_48M] = clk;
2581
2582 /* PLLD */
2583 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
2584 &pll_d_params, &pll_d_lock);
2585 clk_register_clkdev(clk, "pll_d", NULL);
2586 clks[TEGRA210_CLK_PLL_D] = clk;
2587
2588 /* PLLD_OUT0 */
2589 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
2590 CLK_SET_RATE_PARENT, 1, 2);
2591 clk_register_clkdev(clk, "pll_d_out0", NULL);
2592 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
2593
2594 /* PLLRE */
2595 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
2596 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
2597 clk_register_clkdev(clk, "pll_re_vco", NULL);
2598 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
2599
2600 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
2601 clk_base + PLLRE_BASE, 16, 5, 0,
2602 pll_vco_post_div_table, &pll_re_lock);
2603 clk_register_clkdev(clk, "pll_re_out", NULL);
2604 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
2605
2606 /* PLLE */
2607 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
2608 clk_base, 0, &pll_e_params, NULL);
2609 clk_register_clkdev(clk, "pll_e", NULL);
2610 clks[TEGRA210_CLK_PLL_E] = clk;
2611
2612 /* PLLC4 */
2613 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
2614 0, &pll_c4_vco_params, NULL, pll_ref_freq);
2615 clk_register_clkdev(clk, "pll_c4_vco", NULL);
2616 clks[TEGRA210_CLK_PLL_C4] = clk;
2617
2618 /* PLLC4_OUT0 */
2619 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
2620 clk_base + PLLC4_BASE, 19, 4, 0,
2621 pll_vco_post_div_table, NULL);
2622 clk_register_clkdev(clk, "pll_c4_out0", NULL);
2623 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
2624
2625 /* PLLC4_OUT1 */
2626 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
2627 CLK_SET_RATE_PARENT, 1, 3);
2628 clk_register_clkdev(clk, "pll_c4_out1", NULL);
2629 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
2630
2631 /* PLLC4_OUT2 */
2632 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
2633 CLK_SET_RATE_PARENT, 1, 5);
2634 clk_register_clkdev(clk, "pll_c4_out2", NULL);
2635 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
2636
2637 /* PLLC4_OUT3 */
2638 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
2639 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
2640 8, 8, 1, NULL);
2641 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
2642 clk_base + PLLC4_OUT, 1, 0,
2643 CLK_SET_RATE_PARENT, 0, NULL);
2644 clk_register_clkdev(clk, "pll_c4_out3", NULL);
2645 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
2646
2647 /* PLLDP */
2648 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
2649 0, &pll_dp_params, NULL);
2650 clk_register_clkdev(clk, "pll_dp", NULL);
2651 clks[TEGRA210_CLK_PLL_DP] = clk;
2652
2653 /* PLLD2 */
2654 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
2655 0, &pll_d2_params, NULL);
2656 clk_register_clkdev(clk, "pll_d2", NULL);
2657 clks[TEGRA210_CLK_PLL_D2] = clk;
2658
2659 /* PLLD2_OUT0 */
2660 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
2661 CLK_SET_RATE_PARENT, 1, 1);
2662 clk_register_clkdev(clk, "pll_d2_out0", NULL);
2663 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
2664
2665 /* PLLP_OUT2 */
2666 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
2667 CLK_SET_RATE_PARENT, 1, 2);
2668 clk_register_clkdev(clk, "pll_p_out2", NULL);
2669 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
2670
2671}
2672
2673/* Tegra210 CPU clock and reset control functions */
2674static void tegra210_wait_cpu_in_reset(u32 cpu)
2675{
2676 unsigned int reg;
2677
2678 do {
2679 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2680 cpu_relax();
2681 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
2682}
2683
2684static void tegra210_disable_cpu_clock(u32 cpu)
2685{
2686 /* flow controller would take care in the power sequence. */
2687}
2688
2689#ifdef CONFIG_PM_SLEEP
2690static void tegra210_cpu_clock_suspend(void)
2691{
2692 /* switch coresite to clk_m, save off original source */
2693 tegra210_cpu_clk_sctx.clk_csite_src =
2694 readl(clk_base + CLK_SOURCE_CSITE);
2695 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
2696}
2697
2698static void tegra210_cpu_clock_resume(void)
2699{
2700 writel(tegra210_cpu_clk_sctx.clk_csite_src,
2701 clk_base + CLK_SOURCE_CSITE);
2702}
2703#endif
2704
2705static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
2706 .wait_for_reset = tegra210_wait_cpu_in_reset,
2707 .disable_clock = tegra210_disable_cpu_clock,
2708#ifdef CONFIG_PM_SLEEP
2709 .suspend = tegra210_cpu_clock_suspend,
2710 .resume = tegra210_cpu_clock_resume,
2711#endif
2712};
2713
2714static const struct of_device_id pmc_match[] __initconst = {
2715 { .compatible = "nvidia,tegra210-pmc" },
2716 { },
2717};
2718
2719static struct tegra_clk_init_table init_table[] __initdata = {
2720 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
2721 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
2722 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
2723 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
2724 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
2725 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
2726 { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
2727 { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
2728 { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
2729 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2730 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2731 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2732 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2733 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2734 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
2735 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
2736 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 1 },
2737 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
2738 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
2739 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
2740 { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
2741 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
2742 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
2743 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
2744 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
2745 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
2746 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
2747 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
2748 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
2749 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
2750 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
2751 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
2752 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
2753 { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
2754 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
2755 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
2756 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
2757 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
2758 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
2759 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
2760 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
2761 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
2762 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
2763 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
2764 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
2765 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
2766 /* This MUST be the last entry. */
2767 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
2768};
2769
2770/**
2771 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
2772 *
2773 * Program an initial clock rate and enable or disable clocks needed
2774 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
2775 * called by assigning a pointer to it to tegra_clk_apply_init_table -
2776 * this will be called as an arch_initcall. No return value.
2777 */
2778static void __init tegra210_clock_apply_init_table(void)
2779{
2780 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
2781}
2782
2783/**
2784 * tegra210_clock_init - Tegra210-specific clock initialization
2785 * @np: struct device_node * of the DT node for the SoC CAR IP block
2786 *
2787 * Register most SoC clocks for the Tegra210 system-on-chip. Intended
2788 * to be called by the OF init code when a DT node with the
2789 * "nvidia,tegra210-car" string is encountered, and declared with
2790 * CLK_OF_DECLARE. No return value.
2791 */
2792static void __init tegra210_clock_init(struct device_node *np)
2793{
2794 struct device_node *node;
2795 u32 value, clk_m_div;
2796
2797 clk_base = of_iomap(np, 0);
2798 if (!clk_base) {
2799 pr_err("ioremap tegra210 CAR failed\n");
2800 return;
2801 }
2802
2803 node = of_find_matching_node(NULL, pmc_match);
2804 if (!node) {
2805 pr_err("Failed to find pmc node\n");
2806 WARN_ON(1);
2807 return;
2808 }
2809
2810 pmc_base = of_iomap(node, 0);
2811 if (!pmc_base) {
2812 pr_err("Can't map pmc registers\n");
2813 WARN_ON(1);
2814 return;
2815 }
2816
2817 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
2818 TEGRA210_CAR_BANK_COUNT);
2819 if (!clks)
2820 return;
2821
2822 value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
2823 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
2824
2825 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
2826 ARRAY_SIZE(tegra210_input_freq), clk_m_div,
2827 &osc_freq, &pll_ref_freq) < 0)
2828 return;
2829
2830 tegra_fixed_clk_init(tegra210_clks);
2831 tegra210_pll_init(clk_base, pmc_base);
2832 tegra210_periph_clk_init(clk_base, pmc_base);
2833 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
2834 tegra210_audio_plls,
2835 ARRAY_SIZE(tegra210_audio_plls));
2836 tegra_pmc_clk_init(pmc_base, tegra210_clks);
2837
2838 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
2839 value = clk_readl(clk_base + PLLD_BASE);
2840 value &= ~BIT(25);
2841 clk_writel(value, clk_base + PLLD_BASE);
2842
2843 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
2844
2845 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
2846 &pll_x_params);
2847 tegra_add_of_provider(np);
2848 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2849
2850 tegra_cpu_car_ops = &tegra210_cpu_car_ops;
2851}
2852CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index b90db615c29e..0478565cf292 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -224,188 +224,192 @@ struct utmi_clk_param {
224}; 224};
225 225
226static const struct utmi_clk_param utmi_parameters[] = { 226static const struct utmi_clk_param utmi_parameters[] = {
227/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ 227 {
228 {13000000, 0x02, 0x33, 0x05, 0x7F}, 228 .osc_frequency = 13000000, .enable_delay_count = 0x02,
229 {19200000, 0x03, 0x4B, 0x06, 0xBB}, 229 .stable_count = 0x33, .active_delay_count = 0x05,
230 {12000000, 0x02, 0x2F, 0x04, 0x76}, 230 .xtal_freq_count = 0x7f
231 {26000000, 0x04, 0x66, 0x09, 0xFE}, 231 }, {
232 {16800000, 0x03, 0x41, 0x0A, 0xA4}, 232 .osc_frequency = 19200000, .enable_delay_count = 0x03,
233 .stable_count = 0x4b, .active_delay_count = 0x06,
234 .xtal_freq_count = 0xbb
235 }, {
236 .osc_frequency = 12000000, .enable_delay_count = 0x02,
237 .stable_count = 0x2f, .active_delay_count = 0x04,
238 .xtal_freq_count = 0x76
239 }, {
240 .osc_frequency = 26000000, .enable_delay_count = 0x04,
241 .stable_count = 0x66, .active_delay_count = 0x09,
242 .xtal_freq_count = 0xfe
243 }, {
244 .osc_frequency = 16800000, .enable_delay_count = 0x03,
245 .stable_count = 0x41, .active_delay_count = 0x0a,
246 .xtal_freq_count = 0xa4
247 },
233}; 248};
234 249
235static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
236 { 12000000, 1040000000, 520, 6, 0, 8}, 251 { 12000000, 1040000000, 520, 6, 1, 8 },
237 { 13000000, 1040000000, 480, 6, 0, 8}, 252 { 13000000, 1040000000, 480, 6, 1, 8 },
238 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */ 253 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
239 { 19200000, 1040000000, 325, 6, 0, 6}, 254 { 19200000, 1040000000, 325, 6, 1, 6 },
240 { 26000000, 1040000000, 520, 13, 0, 8}, 255 { 26000000, 1040000000, 520, 13, 1, 8 },
241 256 { 12000000, 832000000, 416, 6, 1, 8 },
242 { 12000000, 832000000, 416, 6, 0, 8}, 257 { 13000000, 832000000, 832, 13, 1, 8 },
243 { 13000000, 832000000, 832, 13, 0, 8}, 258 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
244 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */ 259 { 19200000, 832000000, 260, 6, 1, 8 },
245 { 19200000, 832000000, 260, 6, 0, 8}, 260 { 26000000, 832000000, 416, 13, 1, 8 },
246 { 26000000, 832000000, 416, 13, 0, 8}, 261 { 12000000, 624000000, 624, 12, 1, 8 },
247 262 { 13000000, 624000000, 624, 13, 1, 8 },
248 { 12000000, 624000000, 624, 12, 0, 8}, 263 { 16800000, 600000000, 520, 14, 1, 8 },
249 { 13000000, 624000000, 624, 13, 0, 8}, 264 { 19200000, 624000000, 520, 16, 1, 8 },
250 { 16800000, 600000000, 520, 14, 0, 8}, 265 { 26000000, 624000000, 624, 26, 1, 8 },
251 { 19200000, 624000000, 520, 16, 0, 8}, 266 { 12000000, 600000000, 600, 12, 1, 8 },
252 { 26000000, 624000000, 624, 26, 0, 8}, 267 { 13000000, 600000000, 600, 13, 1, 8 },
253 268 { 16800000, 600000000, 500, 14, 1, 8 },
254 { 12000000, 600000000, 600, 12, 0, 8}, 269 { 19200000, 600000000, 375, 12, 1, 6 },
255 { 13000000, 600000000, 600, 13, 0, 8}, 270 { 26000000, 600000000, 600, 26, 1, 8 },
256 { 16800000, 600000000, 500, 14, 0, 8}, 271 { 12000000, 520000000, 520, 12, 1, 8 },
257 { 19200000, 600000000, 375, 12, 0, 6}, 272 { 13000000, 520000000, 520, 13, 1, 8 },
258 { 26000000, 600000000, 600, 26, 0, 8}, 273 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
259 274 { 19200000, 520000000, 325, 12, 1, 6 },
260 { 12000000, 520000000, 520, 12, 0, 8}, 275 { 26000000, 520000000, 520, 26, 1, 8 },
261 { 13000000, 520000000, 520, 13, 0, 8}, 276 { 12000000, 416000000, 416, 12, 1, 8 },
262 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */ 277 { 13000000, 416000000, 416, 13, 1, 8 },
263 { 19200000, 520000000, 325, 12, 0, 6}, 278 { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */
264 { 26000000, 520000000, 520, 26, 0, 8}, 279 { 19200000, 416000000, 260, 12, 1, 6 },
265 280 { 26000000, 416000000, 416, 26, 1, 8 },
266 { 12000000, 416000000, 416, 12, 0, 8}, 281 { 0, 0, 0, 0, 0, 0 },
267 { 13000000, 416000000, 416, 13, 0, 8},
268 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
269 { 19200000, 416000000, 260, 12, 0, 6},
270 { 26000000, 416000000, 416, 26, 0, 8},
271 { 0, 0, 0, 0, 0, 0 },
272}; 282};
273 283
274static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 284static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
275 { 12000000, 666000000, 666, 12, 0, 8}, 285 { 12000000, 666000000, 666, 12, 1, 8 },
276 { 13000000, 666000000, 666, 13, 0, 8}, 286 { 13000000, 666000000, 666, 13, 1, 8 },
277 { 16800000, 666000000, 555, 14, 0, 8}, 287 { 16800000, 666000000, 555, 14, 1, 8 },
278 { 19200000, 666000000, 555, 16, 0, 8}, 288 { 19200000, 666000000, 555, 16, 1, 8 },
279 { 26000000, 666000000, 666, 26, 0, 8}, 289 { 26000000, 666000000, 666, 26, 1, 8 },
280 { 12000000, 600000000, 600, 12, 0, 8}, 290 { 12000000, 600000000, 600, 12, 1, 8 },
281 { 13000000, 600000000, 600, 13, 0, 8}, 291 { 13000000, 600000000, 600, 13, 1, 8 },
282 { 16800000, 600000000, 500, 14, 0, 8}, 292 { 16800000, 600000000, 500, 14, 1, 8 },
283 { 19200000, 600000000, 375, 12, 0, 6}, 293 { 19200000, 600000000, 375, 12, 1, 6 },
284 { 26000000, 600000000, 600, 26, 0, 8}, 294 { 26000000, 600000000, 600, 26, 1, 8 },
285 { 0, 0, 0, 0, 0, 0 }, 295 { 0, 0, 0, 0, 0, 0 },
286}; 296};
287 297
288static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 298static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
289 { 12000000, 216000000, 432, 12, 1, 8}, 299 { 12000000, 216000000, 432, 12, 2, 8 },
290 { 13000000, 216000000, 432, 13, 1, 8}, 300 { 13000000, 216000000, 432, 13, 2, 8 },
291 { 16800000, 216000000, 360, 14, 1, 8}, 301 { 16800000, 216000000, 360, 14, 2, 8 },
292 { 19200000, 216000000, 360, 16, 1, 8}, 302 { 19200000, 216000000, 360, 16, 2, 8 },
293 { 26000000, 216000000, 432, 26, 1, 8}, 303 { 26000000, 216000000, 432, 26, 2, 8 },
294 { 0, 0, 0, 0, 0, 0 }, 304 { 0, 0, 0, 0, 0, 0 },
295}; 305};
296 306
297static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 307static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
298 { 9600000, 564480000, 294, 5, 0, 4}, 308 { 9600000, 564480000, 294, 5, 1, 4 },
299 { 9600000, 552960000, 288, 5, 0, 4}, 309 { 9600000, 552960000, 288, 5, 1, 4 },
300 { 9600000, 24000000, 5, 2, 0, 1}, 310 { 9600000, 24000000, 5, 2, 1, 1 },
301 311 { 28800000, 56448000, 49, 25, 1, 1 },
302 { 28800000, 56448000, 49, 25, 0, 1}, 312 { 28800000, 73728000, 64, 25, 1, 1 },
303 { 28800000, 73728000, 64, 25, 0, 1}, 313 { 28800000, 24000000, 5, 6, 1, 1 },
304 { 28800000, 24000000, 5, 6, 0, 1}, 314 { 0, 0, 0, 0, 0, 0 },
305 { 0, 0, 0, 0, 0, 0 },
306}; 315};
307 316
308static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 317static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
309 { 12000000, 216000000, 216, 12, 0, 4}, 318 { 12000000, 216000000, 216, 12, 1, 4 },
310 { 13000000, 216000000, 216, 13, 0, 4}, 319 { 13000000, 216000000, 216, 13, 1, 4 },
311 { 16800000, 216000000, 180, 14, 0, 4}, 320 { 16800000, 216000000, 180, 14, 1, 4 },
312 { 19200000, 216000000, 180, 16, 0, 4}, 321 { 19200000, 216000000, 180, 16, 1, 4 },
313 { 26000000, 216000000, 216, 26, 0, 4}, 322 { 26000000, 216000000, 216, 26, 1, 4 },
314 323 { 12000000, 594000000, 594, 12, 1, 8 },
315 { 12000000, 594000000, 594, 12, 0, 8}, 324 { 13000000, 594000000, 594, 13, 1, 8 },
316 { 13000000, 594000000, 594, 13, 0, 8}, 325 { 16800000, 594000000, 495, 14, 1, 8 },
317 { 16800000, 594000000, 495, 14, 0, 8}, 326 { 19200000, 594000000, 495, 16, 1, 8 },
318 { 19200000, 594000000, 495, 16, 0, 8}, 327 { 26000000, 594000000, 594, 26, 1, 8 },
319 { 26000000, 594000000, 594, 26, 0, 8}, 328 { 12000000, 1000000000, 1000, 12, 1, 12 },
320 329 { 13000000, 1000000000, 1000, 13, 1, 12 },
321 { 12000000, 1000000000, 1000, 12, 0, 12}, 330 { 19200000, 1000000000, 625, 12, 1, 8 },
322 { 13000000, 1000000000, 1000, 13, 0, 12}, 331 { 26000000, 1000000000, 1000, 26, 1, 12 },
323 { 19200000, 1000000000, 625, 12, 0, 8}, 332 { 0, 0, 0, 0, 0, 0 },
324 { 26000000, 1000000000, 1000, 26, 0, 12},
325
326 { 0, 0, 0, 0, 0, 0 },
327}; 333};
328 334
329static struct pdiv_map pllu_p[] = { 335static const struct pdiv_map pllu_p[] = {
330 { .pdiv = 1, .hw_val = 1 }, 336 { .pdiv = 1, .hw_val = 1 },
331 { .pdiv = 2, .hw_val = 0 }, 337 { .pdiv = 2, .hw_val = 0 },
332 { .pdiv = 0, .hw_val = 0 }, 338 { .pdiv = 0, .hw_val = 0 },
333}; 339};
334 340
335static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 341static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
336 { 12000000, 480000000, 960, 12, 0, 12}, 342 { 12000000, 480000000, 960, 12, 1, 12 },
337 { 13000000, 480000000, 960, 13, 0, 12}, 343 { 13000000, 480000000, 960, 13, 1, 12 },
338 { 16800000, 480000000, 400, 7, 0, 5}, 344 { 16800000, 480000000, 400, 7, 1, 5 },
339 { 19200000, 480000000, 200, 4, 0, 3}, 345 { 19200000, 480000000, 200, 4, 1, 3 },
340 { 26000000, 480000000, 960, 26, 0, 12}, 346 { 26000000, 480000000, 960, 26, 1, 12 },
341 { 0, 0, 0, 0, 0, 0 }, 347 { 0, 0, 0, 0, 0, 0 },
342}; 348};
343 349
344static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 350static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
345 /* 1.7 GHz */ 351 /* 1.7 GHz */
346 { 12000000, 1700000000, 850, 6, 0, 8}, 352 { 12000000, 1700000000, 850, 6, 1, 8 },
347 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */ 353 { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */
348 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */ 354 { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */
349 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */ 355 { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */
350 { 26000000, 1700000000, 850, 13, 0, 8}, 356 { 26000000, 1700000000, 850, 13, 1, 8 },
351
352 /* 1.6 GHz */ 357 /* 1.6 GHz */
353 { 12000000, 1600000000, 800, 6, 0, 8}, 358 { 12000000, 1600000000, 800, 6, 1, 8 },
354 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */ 359 { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */
355 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */ 360 { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */
356 { 19200000, 1600000000, 500, 6, 0, 8}, 361 { 19200000, 1600000000, 500, 6, 1, 8 },
357 { 26000000, 1600000000, 800, 13, 0, 8}, 362 { 26000000, 1600000000, 800, 13, 1, 8 },
358
359 /* 1.5 GHz */ 363 /* 1.5 GHz */
360 { 12000000, 1500000000, 750, 6, 0, 8}, 364 { 12000000, 1500000000, 750, 6, 1, 8 },
361 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */ 365 { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */
362 { 16800000, 1500000000, 625, 7, 0, 8}, 366 { 16800000, 1500000000, 625, 7, 1, 8 },
363 { 19200000, 1500000000, 625, 8, 0, 8}, 367 { 19200000, 1500000000, 625, 8, 1, 8 },
364 { 26000000, 1500000000, 750, 13, 0, 8}, 368 { 26000000, 1500000000, 750, 13, 1, 8 },
365
366 /* 1.4 GHz */ 369 /* 1.4 GHz */
367 { 12000000, 1400000000, 700, 6, 0, 8}, 370 { 12000000, 1400000000, 700, 6, 1, 8 },
368 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */ 371 { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */
369 { 16800000, 1400000000, 1000, 12, 0, 8}, 372 { 16800000, 1400000000, 1000, 12, 1, 8 },
370 { 19200000, 1400000000, 875, 12, 0, 8}, 373 { 19200000, 1400000000, 875, 12, 1, 8 },
371 { 26000000, 1400000000, 700, 13, 0, 8}, 374 { 26000000, 1400000000, 700, 13, 1, 8 },
372
373 /* 1.3 GHz */ 375 /* 1.3 GHz */
374 { 12000000, 1300000000, 975, 9, 0, 8}, 376 { 12000000, 1300000000, 975, 9, 1, 8 },
375 { 13000000, 1300000000, 1000, 10, 0, 8}, 377 { 13000000, 1300000000, 1000, 10, 1, 8 },
376 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */ 378 { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */
377 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */ 379 { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */
378 { 26000000, 1300000000, 650, 13, 0, 8}, 380 { 26000000, 1300000000, 650, 13, 1, 8 },
379
380 /* 1.2 GHz */ 381 /* 1.2 GHz */
381 { 12000000, 1200000000, 1000, 10, 0, 8}, 382 { 12000000, 1200000000, 1000, 10, 1, 8 },
382 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */ 383 { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */
383 { 16800000, 1200000000, 1000, 14, 0, 8}, 384 { 16800000, 1200000000, 1000, 14, 1, 8 },
384 { 19200000, 1200000000, 1000, 16, 0, 8}, 385 { 19200000, 1200000000, 1000, 16, 1, 8 },
385 { 26000000, 1200000000, 600, 13, 0, 8}, 386 { 26000000, 1200000000, 600, 13, 1, 8 },
386
387 /* 1.1 GHz */ 387 /* 1.1 GHz */
388 { 12000000, 1100000000, 825, 9, 0, 8}, 388 { 12000000, 1100000000, 825, 9, 1, 8 },
389 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */ 389 { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */
390 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */ 390 { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */
391 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */ 391 { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */
392 { 26000000, 1100000000, 550, 13, 0, 8}, 392 { 26000000, 1100000000, 550, 13, 1, 8 },
393
394 /* 1 GHz */ 393 /* 1 GHz */
395 { 12000000, 1000000000, 1000, 12, 0, 8}, 394 { 12000000, 1000000000, 1000, 12, 1, 8 },
396 { 13000000, 1000000000, 1000, 13, 0, 8}, 395 { 13000000, 1000000000, 1000, 13, 1, 8 },
397 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */ 396 { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */
398 { 19200000, 1000000000, 625, 12, 0, 8}, 397 { 19200000, 1000000000, 625, 12, 1, 8 },
399 { 26000000, 1000000000, 1000, 26, 0, 8}, 398 { 26000000, 1000000000, 1000, 26, 1, 8 },
399 { 0, 0, 0, 0, 0, 0 },
400};
400 401
401 { 0, 0, 0, 0, 0, 0 }, 402static const struct pdiv_map plle_p[] = {
403 { .pdiv = 18, .hw_val = 18 },
404 { .pdiv = 24, .hw_val = 24 },
405 { .pdiv = 0, .hw_val = 0 },
402}; 406};
403 407
404static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 408static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
405 /* PLLE special case: use cpcon field to store cml divider value */ 409 /* PLLE special case: use cpcon field to store cml divider value */
406 { 12000000, 100000000, 150, 1, 18, 11}, 410 { 12000000, 100000000, 150, 1, 18, 11 },
407 { 216000000, 100000000, 200, 18, 24, 13}, 411 { 216000000, 100000000, 200, 18, 24, 13 },
408 { 0, 0, 0, 0, 0, 0 }, 412 { 0, 0, 0, 0, 0, 0 },
409}; 413};
410 414
411/* PLL parameters */ 415/* PLL parameters */
@@ -422,7 +426,8 @@ static struct tegra_clk_pll_params pll_c_params = {
422 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
423 .lock_delay = 300, 427 .lock_delay = 300,
424 .freq_table = pll_c_freq_table, 428 .freq_table = pll_c_freq_table,
425 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 429 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
430 TEGRA_PLL_HAS_LOCK_ENABLE,
426}; 431};
427 432
428static struct div_nmp pllm_nmp = { 433static struct div_nmp pllm_nmp = {
@@ -454,7 +459,8 @@ static struct tegra_clk_pll_params pll_m_params = {
454 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 459 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
455 .freq_table = pll_m_freq_table, 460 .freq_table = pll_m_freq_table,
456 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 461 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
457 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 462 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |
463 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,
458}; 464};
459 465
460static struct tegra_clk_pll_params pll_p_params = { 466static struct tegra_clk_pll_params pll_p_params = {
@@ -470,7 +476,8 @@ static struct tegra_clk_pll_params pll_p_params = {
470 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 476 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
471 .lock_delay = 300, 477 .lock_delay = 300,
472 .freq_table = pll_p_freq_table, 478 .freq_table = pll_p_freq_table,
473 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 479 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
480 TEGRA_PLL_HAS_LOCK_ENABLE,
474 .fixed_rate = 408000000, 481 .fixed_rate = 408000000,
475}; 482};
476 483
@@ -487,7 +494,8 @@ static struct tegra_clk_pll_params pll_a_params = {
487 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 494 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
488 .lock_delay = 300, 495 .lock_delay = 300,
489 .freq_table = pll_a_freq_table, 496 .freq_table = pll_a_freq_table,
490 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 497 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
498 TEGRA_PLL_HAS_LOCK_ENABLE,
491}; 499};
492 500
493static struct tegra_clk_pll_params pll_d_params = { 501static struct tegra_clk_pll_params pll_d_params = {
@@ -504,8 +512,7 @@ static struct tegra_clk_pll_params pll_d_params = {
504 .lock_delay = 1000, 512 .lock_delay = 1000,
505 .freq_table = pll_d_freq_table, 513 .freq_table = pll_d_freq_table,
506 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 514 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
507 TEGRA_PLL_USE_LOCK, 515 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
508
509}; 516};
510 517
511static struct tegra_clk_pll_params pll_d2_params = { 518static struct tegra_clk_pll_params pll_d2_params = {
@@ -522,7 +529,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
522 .lock_delay = 1000, 529 .lock_delay = 1000,
523 .freq_table = pll_d_freq_table, 530 .freq_table = pll_d_freq_table,
524 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 531 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
525 TEGRA_PLL_USE_LOCK, 532 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
526}; 533};
527 534
528static struct tegra_clk_pll_params pll_u_params = { 535static struct tegra_clk_pll_params pll_u_params = {
@@ -539,7 +546,8 @@ static struct tegra_clk_pll_params pll_u_params = {
539 .lock_delay = 1000, 546 .lock_delay = 1000,
540 .pdiv_tohw = pllu_p, 547 .pdiv_tohw = pllu_p,
541 .freq_table = pll_u_freq_table, 548 .freq_table = pll_u_freq_table,
542 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON, 549 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
550 TEGRA_PLL_HAS_LOCK_ENABLE,
543}; 551};
544 552
545static struct tegra_clk_pll_params pll_x_params = { 553static struct tegra_clk_pll_params pll_x_params = {
@@ -556,7 +564,7 @@ static struct tegra_clk_pll_params pll_x_params = {
556 .lock_delay = 300, 564 .lock_delay = 300,
557 .freq_table = pll_x_freq_table, 565 .freq_table = pll_x_freq_table,
558 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | 566 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
559 TEGRA_PLL_USE_LOCK, 567 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
560}; 568};
561 569
562static struct tegra_clk_pll_params pll_e_params = { 570static struct tegra_clk_pll_params pll_e_params = {
@@ -571,19 +579,21 @@ static struct tegra_clk_pll_params pll_e_params = {
571 .lock_mask = PLLE_MISC_LOCK, 579 .lock_mask = PLLE_MISC_LOCK,
572 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 580 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
573 .lock_delay = 300, 581 .lock_delay = 300,
582 .pdiv_tohw = plle_p,
574 .freq_table = pll_e_freq_table, 583 .freq_table = pll_e_freq_table,
575 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED, 584 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
585 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,
576 .fixed_rate = 100000000, 586 .fixed_rate = 100000000,
577}; 587};
578 588
579static unsigned long tegra30_input_freq[] = { 589static unsigned long tegra30_input_freq[] = {
580 [0] = 13000000, 590 [ 0] = 13000000,
581 [1] = 16800000, 591 [ 1] = 16800000,
582 [4] = 19200000, 592 [ 4] = 19200000,
583 [5] = 38400000, 593 [ 5] = 38400000,
584 [8] = 12000000, 594 [ 8] = 12000000,
585 [9] = 48000000, 595 [ 9] = 48000000,
586 [12] = 260000000, 596 [12] = 26000000,
587}; 597};
588 598
589static struct tegra_devclk devclks[] __initdata = { 599static struct tegra_devclk devclks[] __initdata = {
@@ -861,13 +871,12 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
861 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true }, 871 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
862 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true }, 872 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
863 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true }, 873 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
864
865}; 874};
866 875
867static void tegra30_utmi_param_configure(void) 876static void tegra30_utmi_param_configure(void)
868{ 877{
878 unsigned int i;
869 u32 reg; 879 u32 reg;
870 int i;
871 880
872 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 881 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
873 if (input_freq == utmi_parameters[i].osc_frequency) 882 if (input_freq == utmi_parameters[i].osc_frequency)
@@ -917,7 +926,7 @@ static void tegra30_utmi_param_configure(void)
917 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 926 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
918} 927}
919 928
920static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; 929static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
921 930
922static void __init tegra30_pll_init(void) 931static void __init tegra30_pll_init(void)
923{ 932{
@@ -925,7 +934,7 @@ static void __init tegra30_pll_init(void)
925 934
926 /* PLLC */ 935 /* PLLC */
927 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 936 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
928 &pll_c_params, NULL); 937 &pll_c_params, NULL);
929 clks[TEGRA30_CLK_PLL_C] = clk; 938 clks[TEGRA30_CLK_PLL_C] = clk;
930 939
931 /* PLLC_OUT1 */ 940 /* PLLC_OUT1 */
@@ -1135,7 +1144,7 @@ static void __init tegra30_periph_clk_init(void)
1135{ 1144{
1136 struct tegra_periph_init_data *data; 1145 struct tegra_periph_init_data *data;
1137 struct clk *clk; 1146 struct clk *clk;
1138 int i; 1147 unsigned int i;
1139 1148
1140 /* dsia */ 1149 /* dsia */
1141 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1150 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
@@ -1224,7 +1233,6 @@ static void tegra30_cpu_out_of_reset(u32 cpu)
1224 wmb(); 1233 wmb();
1225} 1234}
1226 1235
1227
1228static void tegra30_enable_cpu_clock(u32 cpu) 1236static void tegra30_enable_cpu_clock(u32 cpu)
1229{ 1237{
1230 unsigned int reg; 1238 unsigned int reg;
@@ -1237,7 +1245,6 @@ static void tegra30_enable_cpu_clock(u32 cpu)
1237 1245
1238static void tegra30_disable_cpu_clock(u32 cpu) 1246static void tegra30_disable_cpu_clock(u32 cpu)
1239{ 1247{
1240
1241 unsigned int reg; 1248 unsigned int reg;
1242 1249
1243 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1250 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
@@ -1268,7 +1275,7 @@ static void tegra30_cpu_clock_suspend(void)
1268 /* switch coresite to clk_m, save off original source */ 1275 /* switch coresite to clk_m, save off original source */
1269 tegra30_cpu_clk_sctx.clk_csite_src = 1276 tegra30_cpu_clk_sctx.clk_csite_src =
1270 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1277 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1271 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE); 1278 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
1272 1279
1273 tegra30_cpu_clk_sctx.cpu_burst = 1280 tegra30_cpu_clk_sctx.cpu_burst =
1274 readl(clk_base + CLK_RESET_CCLK_BURST); 1281 readl(clk_base + CLK_RESET_CCLK_BURST);
@@ -1335,44 +1342,45 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1335}; 1342};
1336 1343
1337static struct tegra_clk_init_table init_table[] __initdata = { 1344static struct tegra_clk_init_table init_table[] __initdata = {
1338 {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0}, 1345 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1339 {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0}, 1346 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1340 {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0}, 1347 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1341 {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0}, 1348 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1342 {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0}, 1349 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1343 {TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1}, 1350 { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
1344 {TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1}, 1351 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
1345 {TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1}, 1352 { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
1346 {TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0}, 1353 { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
1347 {TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1}, 1354 { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
1348 {TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1}, 1355 { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
1349 {TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0}, 1356 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1350 {TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0}, 1357 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1351 {TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0}, 1358 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1352 {TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0}, 1359 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1353 {TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0}, 1360 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1354 {TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0}, 1361 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1355 {TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0}, 1362 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1356 {TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0}, 1363 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
1357 {TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1}, 1364 { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
1358 {TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1}, 1365 { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
1359 {TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1}, 1366 { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
1360 {TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1}, 1367 { TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
1361 {TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1}, 1368 { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
1362 {TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0}, 1369 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
1363 {TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0}, 1370 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
1364 {TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0}, 1371 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
1365 {TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0}, 1372 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
1366 {TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0}, 1373 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
1367 {TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0}, 1374 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
1368 {TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0}, 1375 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
1369 {TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0}, 1376 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
1370 {TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0}, 1377 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
1371 {TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1}, 1378 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
1372 {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0}, 1379 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1373 {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0}, 1380 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1374 {TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0}, 1381 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
1375 {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */ 1382 /* must be the last entry */
1383 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
1376}; 1384};
1377 1385
1378static void __init tegra30_clock_apply_init_table(void) 1386static void __init tegra30_clock_apply_init_table(void)
@@ -1397,12 +1405,13 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1397 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL), 1405 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1398 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"), 1406 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1399 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"), 1407 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1400 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */ 1408 /* must be the last entry */
1409 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
1401}; 1410};
1402 1411
1403static const struct of_device_id pmc_match[] __initconst = { 1412static const struct of_device_id pmc_match[] __initconst = {
1404 { .compatible = "nvidia,tegra30-pmc" }, 1413 { .compatible = "nvidia,tegra30-pmc" },
1405 {}, 1414 { },
1406}; 1415};
1407 1416
1408static struct tegra_audio_clk_info tegra30_audio_plls[] = { 1417static struct tegra_audio_clk_info tegra30_audio_plls[] = {
@@ -1441,7 +1450,6 @@ static void __init tegra30_clock_init(struct device_node *np)
1441 NULL) < 0) 1450 NULL) < 0)
1442 return; 1451 return;
1443 1452
1444
1445 tegra_fixed_clk_init(tegra30_clks); 1453 tegra_fixed_clk_init(tegra30_clks);
1446 tegra30_pll_init(); 1454 tegra30_pll_init();
1447 tegra30_super_clk_init(); 1455 tegra30_super_clk_init();
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 5d2678914160..4dbcfaec576a 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -110,14 +110,16 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
110 * @m: input divider 110 * @m: input divider
111 * @p: post divider 111 * @p: post divider
112 * @cpcon: charge pump current 112 * @cpcon: charge pump current
113 * @sdm_data: fraction divider setting (0 = disabled)
113 */ 114 */
114struct tegra_clk_pll_freq_table { 115struct tegra_clk_pll_freq_table {
115 unsigned long input_rate; 116 unsigned long input_rate;
116 unsigned long output_rate; 117 unsigned long output_rate;
117 u16 n; 118 u32 n;
118 u16 m; 119 u16 m;
119 u8 p; 120 u8 p;
120 u8 cpcon; 121 u8 cpcon;
122 u16 sdm_data;
121}; 123};
122 124
123/** 125/**
@@ -156,6 +158,10 @@ struct div_nmp {
156 u8 override_divp_shift; 158 u8 override_divp_shift;
157}; 159};
158 160
161#define MAX_PLL_MISC_REG_COUNT 6
162
163struct tegra_clk_pll;
164
159/** 165/**
160 * struct tegra_clk_pll_params - PLL parameters 166 * struct tegra_clk_pll_params - PLL parameters
161 * 167 *
@@ -172,6 +178,14 @@ struct div_nmp {
172 * @lock_enable_bit_idx: Bit index to enable PLL lock 178 * @lock_enable_bit_idx: Bit index to enable PLL lock
173 * @iddq_reg: PLL IDDQ register offset 179 * @iddq_reg: PLL IDDQ register offset
174 * @iddq_bit_idx: Bit index to enable PLL IDDQ 180 * @iddq_bit_idx: Bit index to enable PLL IDDQ
181 * @reset_reg: Register offset of where RESET bit is
182 * @reset_bit_idx: Shift of reset bit in reset_reg
183 * @sdm_din_reg: Register offset where SDM settings are
184 * @sdm_din_mask: Mask of SDM divider bits
185 * @sdm_ctrl_reg: Register offset where SDM enable is
186 * @sdm_ctrl_en_mask: Mask of SDM enable bit
187 * @ssc_ctrl_reg: Register offset where SSC settings are
188 * @ssc_ctrl_en_mask: Mask of SSC enable bit
175 * @aux_reg: AUX register offset 189 * @aux_reg: AUX register offset
176 * @dyn_ramp_reg: Dynamic ramp control register offset 190 * @dyn_ramp_reg: Dynamic ramp control register offset
177 * @ext_misc_reg: Miscellaneous control register offsets 191 * @ext_misc_reg: Miscellaneous control register offsets
@@ -182,10 +196,27 @@ struct div_nmp {
182 * @stepb_shift: Dynamic ramp step B field shift 196 * @stepb_shift: Dynamic ramp step B field shift
183 * @lock_delay: Delay in us if PLL lock is not used 197 * @lock_delay: Delay in us if PLL lock is not used
184 * @max_p: maximum value for the p divider 198 * @max_p: maximum value for the p divider
199 * @defaults_set: Boolean signaling all reg defaults for PLL set.
185 * @pdiv_tohw: mapping of p divider to register values 200 * @pdiv_tohw: mapping of p divider to register values
186 * @div_nmp: offsets and widths on n, m and p fields 201 * @div_nmp: offsets and widths on n, m and p fields
187 * @freq_table: array of frequencies supported by PLL 202 * @freq_table: array of frequencies supported by PLL
188 * @fixed_rate: PLL rate if it is fixed 203 * @fixed_rate: PLL rate if it is fixed
204 * @mdiv_default: Default value for fixed mdiv for this PLL
205 * @round_p_to_pdiv: Callback used to round p to the closed pdiv
206 * @set_gain: Callback to adjust N div for SDM enabled
207 * PLL's based on fractional divider value.
208 * @calc_rate: Callback used to change how out of table
209 * rates (dividers and multipler) are calculated.
210 * @adjust_vco: Callback to adjust the programming range of the
211 * divider range (if SDM is present)
212 * @set_defaults: Callback which will try to initialize PLL
213 * registers to sane default values. This is first
214 * tried during PLL registration, but if the PLL
215 * is already enabled, it will be done the first
216 * time the rate is changed while the PLL is
217 * disabled.
218 * @dyn_ramp: Callback which can be used to define a custom
219 * dynamic ramp function for a given PLL.
189 * 220 *
190 * Flags: 221 * Flags:
191 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 222 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
@@ -207,6 +238,11 @@ struct div_nmp {
207 * base register. 238 * base register.
208 * TEGRA_PLL_BYPASS - PLL has bypass bit 239 * TEGRA_PLL_BYPASS - PLL has bypass bit
209 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 240 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
241 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
242 * it may be more accurate (especially if SDM present)
243 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
244 * flag indicated that it is PLLMB.
245 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
210 */ 246 */
211struct tegra_clk_pll_params { 247struct tegra_clk_pll_params {
212 unsigned long input_min; 248 unsigned long input_min;
@@ -223,9 +259,17 @@ struct tegra_clk_pll_params {
223 u32 lock_enable_bit_idx; 259 u32 lock_enable_bit_idx;
224 u32 iddq_reg; 260 u32 iddq_reg;
225 u32 iddq_bit_idx; 261 u32 iddq_bit_idx;
262 u32 reset_reg;
263 u32 reset_bit_idx;
264 u32 sdm_din_reg;
265 u32 sdm_din_mask;
266 u32 sdm_ctrl_reg;
267 u32 sdm_ctrl_en_mask;
268 u32 ssc_ctrl_reg;
269 u32 ssc_ctrl_en_mask;
226 u32 aux_reg; 270 u32 aux_reg;
227 u32 dyn_ramp_reg; 271 u32 dyn_ramp_reg;
228 u32 ext_misc_reg[3]; 272 u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
229 u32 pmc_divnm_reg; 273 u32 pmc_divnm_reg;
230 u32 pmc_divp_reg; 274 u32 pmc_divp_reg;
231 u32 flags; 275 u32 flags;
@@ -233,10 +277,22 @@ struct tegra_clk_pll_params {
233 int stepb_shift; 277 int stepb_shift;
234 int lock_delay; 278 int lock_delay;
235 int max_p; 279 int max_p;
236 struct pdiv_map *pdiv_tohw; 280 bool defaults_set;
281 const struct pdiv_map *pdiv_tohw;
237 struct div_nmp *div_nmp; 282 struct div_nmp *div_nmp;
238 struct tegra_clk_pll_freq_table *freq_table; 283 struct tegra_clk_pll_freq_table *freq_table;
239 unsigned long fixed_rate; 284 unsigned long fixed_rate;
285 u16 mdiv_default;
286 u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
287 void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
288 int (*calc_rate)(struct clk_hw *hw,
289 struct tegra_clk_pll_freq_table *cfg,
290 unsigned long rate, unsigned long parent_rate);
291 unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
292 unsigned long parent_rate);
293 void (*set_defaults)(struct tegra_clk_pll *pll);
294 int (*dyn_ramp)(struct tegra_clk_pll *pll,
295 struct tegra_clk_pll_freq_table *cfg);
240}; 296};
241 297
242#define TEGRA_PLL_USE_LOCK BIT(0) 298#define TEGRA_PLL_USE_LOCK BIT(0)
@@ -250,6 +306,9 @@ struct tegra_clk_pll_params {
250#define TEGRA_PLL_LOCK_MISC BIT(8) 306#define TEGRA_PLL_LOCK_MISC BIT(8)
251#define TEGRA_PLL_BYPASS BIT(9) 307#define TEGRA_PLL_BYPASS BIT(9)
252#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 308#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
309#define TEGRA_MDIV_NEW BIT(11)
310#define TEGRA_PLLMB BIT(12)
311#define TEGRA_PLL_VCO_OUT BIT(13)
253 312
254/** 313/**
255 * struct tegra_clk_pll - Tegra PLL clock 314 * struct tegra_clk_pll - Tegra PLL clock
@@ -303,6 +362,12 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
303 struct tegra_clk_pll_params *pll_params, 362 struct tegra_clk_pll_params *pll_params,
304 spinlock_t *lock); 363 spinlock_t *lock);
305 364
365struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
366 const char *parent_name, void __iomem *clk_base,
367 void __iomem *pmc, unsigned long flags,
368 struct tegra_clk_pll_params *pll_params,
369 spinlock_t *lock);
370
306struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 371struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
307 void __iomem *clk_base, void __iomem *pmc, 372 void __iomem *clk_base, void __iomem *pmc,
308 unsigned long flags, 373 unsigned long flags,
@@ -327,11 +392,35 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
327 struct tegra_clk_pll_params *pll_params, 392 struct tegra_clk_pll_params *pll_params,
328 spinlock_t *lock); 393 spinlock_t *lock);
329 394
395struct clk *tegra_clk_register_plle_tegra210(const char *name,
396 const char *parent_name,
397 void __iomem *clk_base, unsigned long flags,
398 struct tegra_clk_pll_params *pll_params,
399 spinlock_t *lock);
400
401struct clk *tegra_clk_register_pllc_tegra210(const char *name,
402 const char *parent_name, void __iomem *clk_base,
403 void __iomem *pmc, unsigned long flags,
404 struct tegra_clk_pll_params *pll_params,
405 spinlock_t *lock);
406
407struct clk *tegra_clk_register_pllss_tegra210(const char *name,
408 const char *parent_name, void __iomem *clk_base,
409 unsigned long flags,
410 struct tegra_clk_pll_params *pll_params,
411 spinlock_t *lock);
412
330struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 413struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
331 void __iomem *clk_base, unsigned long flags, 414 void __iomem *clk_base, unsigned long flags,
332 struct tegra_clk_pll_params *pll_params, 415 struct tegra_clk_pll_params *pll_params,
333 spinlock_t *lock); 416 spinlock_t *lock);
334 417
418struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
419 void __iomem *clk_base, void __iomem *pmc,
420 unsigned long flags,
421 struct tegra_clk_pll_params *pll_params,
422 spinlock_t *lock);
423
335/** 424/**
336 * struct tegra_clk_pll_out - PLL divider down clock 425 * struct tegra_clk_pll_out - PLL divider down clock
337 * 426 *
@@ -653,6 +742,9 @@ int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
653void tegra_super_clk_gen4_init(void __iomem *clk_base, 742void tegra_super_clk_gen4_init(void __iomem *clk_base,
654 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 743 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
655 struct tegra_clk_pll_params *pll_params); 744 struct tegra_clk_pll_params *pll_params);
745void tegra_super_clk_gen5_init(void __iomem *clk_base,
746 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
747 struct tegra_clk_pll_params *pll_params);
656 748
657#ifdef CONFIG_TEGRA_CLK_EMC 749#ifdef CONFIG_TEGRA_CLK_EMC
658struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, 750struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
@@ -674,5 +766,8 @@ void tegra114_clock_deassert_dfll_dvco_reset(void);
674 766
675typedef void (*tegra_clk_apply_init_table_func)(void); 767typedef void (*tegra_clk_apply_init_table_func)(void);
676extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 768extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
769int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
770u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
771int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
677 772
678#endif /* TEGRA_CLK_H */ 773#endif /* TEGRA_CLK_H */
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
new file mode 100644
index 000000000000..6f45aea49e4f
--- /dev/null
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -0,0 +1,401 @@
1/*
2 * This header provides constants for binding nvidia,tegra210-car.
3 *
4 * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
5 * registers. These IDs often match those in the CAR's RST_DEVICES registers,
6 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
7 * this case, those clocks are assigned IDs above 224 in order to highlight
8 * this issue. Implementations that interpret these clock IDs as bit values
9 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
10 * explicitly handle these special cases.
11 *
12 * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
13 * above.
14 */
15
16#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
17#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
18
19/* 0 */
20/* 1 */
21/* 2 */
22#define TEGRA210_CLK_ISPB 3
23#define TEGRA210_CLK_RTC 4
24#define TEGRA210_CLK_TIMER 5
25#define TEGRA210_CLK_UARTA 6
26/* 7 (register bit affects uartb and vfir) */
27#define TEGRA210_CLK_GPIO 8
28#define TEGRA210_CLK_SDMMC2 9
29/* 10 (register bit affects spdif_in and spdif_out) */
30#define TEGRA210_CLK_I2S1 11
31#define TEGRA210_CLK_I2C1 12
32/* 13 */
33#define TEGRA210_CLK_SDMMC1 14
34#define TEGRA210_CLK_SDMMC4 15
35/* 16 */
36#define TEGRA210_CLK_PWM 17
37#define TEGRA210_CLK_I2S2 18
38/* 19 */
39/* 20 (register bit affects vi and vi_sensor) */
40/* 21 */
41#define TEGRA210_CLK_USBD 22
42#define TEGRA210_CLK_ISP 23
43/* 24 */
44/* 25 */
45#define TEGRA210_CLK_DISP2 26
46#define TEGRA210_CLK_DISP1 27
47#define TEGRA210_CLK_HOST1X 28
48/* 29 */
49#define TEGRA210_CLK_I2S0 30
50/* 31 */
51
52#define TEGRA210_CLK_MC 32
53#define TEGRA210_CLK_AHBDMA 33
54#define TEGRA210_CLK_APBDMA 34
55/* 35 */
56/* 36 */
57/* 37 */
58#define TEGRA210_CLK_PMC 38
59/* 39 (register bit affects fuse and fuse_burn) */
60#define TEGRA210_CLK_KFUSE 40
61#define TEGRA210_CLK_SBC1 41
62/* 42 */
63/* 43 */
64#define TEGRA210_CLK_SBC2 44
65/* 45 */
66#define TEGRA210_CLK_SBC3 46
67#define TEGRA210_CLK_I2C5 47
68#define TEGRA210_CLK_DSIA 48
69/* 49 */
70/* 50 */
71/* 51 */
72#define TEGRA210_CLK_CSI 52
73/* 53 */
74#define TEGRA210_CLK_I2C2 54
75#define TEGRA210_CLK_UARTC 55
76#define TEGRA210_CLK_MIPI_CAL 56
77#define TEGRA210_CLK_EMC 57
78#define TEGRA210_CLK_USB2 58
79/* 59 */
80/* 60 */
81/* 61 */
82/* 62 */
83#define TEGRA210_CLK_BSEV 63
84
85/* 64 */
86#define TEGRA210_CLK_UARTD 65
87/* 66 */
88#define TEGRA210_CLK_I2C3 67
89#define TEGRA210_CLK_SBC4 68
90#define TEGRA210_CLK_SDMMC3 69
91#define TEGRA210_CLK_PCIE 70
92#define TEGRA210_CLK_OWR 71
93#define TEGRA210_CLK_AFI 72
94#define TEGRA210_CLK_CSITE 73
95/* 74 */
96/* 75 */
97/* 76 */
98/* 77 */
99#define TEGRA210_CLK_SOC_THERM 78
100#define TEGRA210_CLK_DTV 79
101/* 80 */
102#define TEGRA210_CLK_I2CSLOW 81
103#define TEGRA210_CLK_DSIB 82
104#define TEGRA210_CLK_TSEC 83
105/* 84 */
106/* 85 */
107/* 86 */
108/* 87 */
109/* 88 */
110#define TEGRA210_CLK_XUSB_HOST 89
111/* 90 */
112/* 91 */
113#define TEGRA210_CLK_CSUS 92
114/* 93 */
115/* 94 */
116/* 95 (bit affects xusb_dev and xusb_dev_src) */
117
118/* 96 */
119/* 97 */
120/* 98 */
121#define TEGRA210_CLK_MSELECT 99
122#define TEGRA210_CLK_TSENSOR 100
123#define TEGRA210_CLK_I2S3 101
124#define TEGRA210_CLK_I2S4 102
125#define TEGRA210_CLK_I2C4 103
126/* 104 */
127/* 105 */
128#define TEGRA210_CLK_D_AUDIO 106
129/* 107 ( affects abp -> ape) */
130/* 108 */
131/* 109 */
132/* 110 */
133#define TEGRA210_CLK_HDA2CODEC_2X 111
134/* 112 */
135/* 113 */
136/* 114 */
137/* 115 */
138/* 116 */
139/* 117 */
140#define TEGRA210_CLK_SPDIF_2X 118
141#define TEGRA210_CLK_ACTMON 119
142#define TEGRA210_CLK_EXTERN1 120
143#define TEGRA210_CLK_EXTERN2 121
144#define TEGRA210_CLK_EXTERN3 122
145#define TEGRA210_CLK_SATA_OOB 123
146#define TEGRA210_CLK_SATA 124
147#define TEGRA210_CLK_HDA 125
148/* 126 */
149/* 127 */
150
151#define TEGRA210_CLK_HDA2HDMI 128
152/* 129 */
153/* 130 */
154/* 131 */
155/* 132 */
156/* 133 */
157/* 134 */
158/* 135 */
159/* 136 */
160/* 137 */
161/* 138 */
162/* 139 */
163/* 140 */
164/* 141 */
165/* 142 */
166/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
167#define TEGRA210_CLK_XUSB_GATE 143
168#define TEGRA210_CLK_CILAB 144
169#define TEGRA210_CLK_CILCD 145
170#define TEGRA210_CLK_CILE 146
171#define TEGRA210_CLK_DSIALP 147
172#define TEGRA210_CLK_DSIBLP 148
173#define TEGRA210_CLK_ENTROPY 149
174/* 150 */
175/* 151 */
176/* 152 */
177/* 153 */
178/* 154 */
179/* 155 (bit affects dfll_ref and dfll_soc) */
180#define TEGRA210_CLK_XUSB_SS 156
181/* 157 */
182/* 158 */
183/* 159 */
184
185/* 160 */
186#define TEGRA210_CLK_DMIC1 161
187#define TEGRA210_CLK_DMIC2 162
188/* 163 */
189/* 164 */
190/* 165 */
191#define TEGRA210_CLK_I2C6 166
192/* 167 */
193/* 168 */
194/* 169 */
195/* 170 */
196#define TEGRA210_CLK_VIM2_CLK 171
197/* 172 */
198#define TEGRA210_CLK_MIPIBIF 173
199/* 174 */
200/* 175 */
201/* 176 */
202#define TEGRA210_CLK_CLK72MHZ 177
203#define TEGRA210_CLK_VIC03 178
204/* 179 */
205/* 180 */
206#define TEGRA210_CLK_DPAUX 181
207#define TEGRA210_CLK_SOR0 182
208#define TEGRA210_CLK_SOR1 183
209#define TEGRA210_CLK_GPU 184
210#define TEGRA210_CLK_DBGAPB 185
211/* 186 */
212#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
213/* 188 */
214#define TEGRA210_CLK_PLL_G_REF 189
215/* 190 */
216/* 191 */
217
218/* 192 */
219#define TEGRA210_CLK_SDMMC_LEGACY 193
220#define TEGRA210_CLK_NVDEC 194
221#define TEGRA210_CLK_NVJPG 195
222/* 196 */
223#define TEGRA210_CLK_DMIC3 197
224#define TEGRA210_CLK_APE 198
225/* 199 */
226/* 200 */
227/* 201 */
228#define TEGRA210_CLK_MAUD 202
229/* 203 */
230/* 204 */
231/* 205 */
232#define TEGRA210_CLK_TSECB 206
233#define TEGRA210_CLK_DPAUX1 207
234#define TEGRA210_CLK_VI_I2C 208
235#define TEGRA210_CLK_HSIC_TRK 209
236#define TEGRA210_CLK_USB2_TRK 210
237#define TEGRA210_CLK_QSPI 211
238#define TEGRA210_CLK_UARTAPE 212
239/* 213 */
240/* 214 */
241/* 215 */
242/* 216 */
243/* 217 */
244/* 218 */
245#define TEGRA210_CLK_NVENC 219
246/* 220 */
247/* 221 */
248#define TEGRA210_CLK_SOR_SAFE 222
249#define TEGRA210_CLK_PLL_P_OUT_CPU 223
250
251
252#define TEGRA210_CLK_UARTB 224
253#define TEGRA210_CLK_VFIR 225
254#define TEGRA210_CLK_SPDIF_IN 226
255#define TEGRA210_CLK_SPDIF_OUT 227
256#define TEGRA210_CLK_VI 228
257#define TEGRA210_CLK_VI_SENSOR 229
258#define TEGRA210_CLK_FUSE 230
259#define TEGRA210_CLK_FUSE_BURN 231
260#define TEGRA210_CLK_CLK_32K 232
261#define TEGRA210_CLK_CLK_M 233
262#define TEGRA210_CLK_CLK_M_DIV2 234
263#define TEGRA210_CLK_CLK_M_DIV4 235
264#define TEGRA210_CLK_PLL_REF 236
265#define TEGRA210_CLK_PLL_C 237
266#define TEGRA210_CLK_PLL_C_OUT1 238
267#define TEGRA210_CLK_PLL_C2 239
268#define TEGRA210_CLK_PLL_C3 240
269#define TEGRA210_CLK_PLL_M 241
270#define TEGRA210_CLK_PLL_M_OUT1 242
271#define TEGRA210_CLK_PLL_P 243
272#define TEGRA210_CLK_PLL_P_OUT1 244
273#define TEGRA210_CLK_PLL_P_OUT2 245
274#define TEGRA210_CLK_PLL_P_OUT3 246
275#define TEGRA210_CLK_PLL_P_OUT4 247
276#define TEGRA210_CLK_PLL_A 248
277#define TEGRA210_CLK_PLL_A_OUT0 249
278#define TEGRA210_CLK_PLL_D 250
279#define TEGRA210_CLK_PLL_D_OUT0 251
280#define TEGRA210_CLK_PLL_D2 252
281#define TEGRA210_CLK_PLL_D2_OUT0 253
282#define TEGRA210_CLK_PLL_U 254
283#define TEGRA210_CLK_PLL_U_480M 255
284
285#define TEGRA210_CLK_PLL_U_60M 256
286#define TEGRA210_CLK_PLL_U_48M 257
287/* 258 */
288#define TEGRA210_CLK_PLL_X 259
289#define TEGRA210_CLK_PLL_X_OUT0 260
290#define TEGRA210_CLK_PLL_RE_VCO 261
291#define TEGRA210_CLK_PLL_RE_OUT 262
292#define TEGRA210_CLK_PLL_E 263
293#define TEGRA210_CLK_SPDIF_IN_SYNC 264
294#define TEGRA210_CLK_I2S0_SYNC 265
295#define TEGRA210_CLK_I2S1_SYNC 266
296#define TEGRA210_CLK_I2S2_SYNC 267
297#define TEGRA210_CLK_I2S3_SYNC 268
298#define TEGRA210_CLK_I2S4_SYNC 269
299#define TEGRA210_CLK_VIMCLK_SYNC 270
300#define TEGRA210_CLK_AUDIO0 271
301#define TEGRA210_CLK_AUDIO1 272
302#define TEGRA210_CLK_AUDIO2 273
303#define TEGRA210_CLK_AUDIO3 274
304#define TEGRA210_CLK_AUDIO4 275
305#define TEGRA210_CLK_SPDIF 276
306#define TEGRA210_CLK_CLK_OUT_1 277
307#define TEGRA210_CLK_CLK_OUT_2 278
308#define TEGRA210_CLK_CLK_OUT_3 279
309#define TEGRA210_CLK_BLINK 280
310/* 281 */
311/* 282 */
312/* 283 */
313#define TEGRA210_CLK_XUSB_HOST_SRC 284
314#define TEGRA210_CLK_XUSB_FALCON_SRC 285
315#define TEGRA210_CLK_XUSB_FS_SRC 286
316#define TEGRA210_CLK_XUSB_SS_SRC 287
317
318#define TEGRA210_CLK_XUSB_DEV_SRC 288
319#define TEGRA210_CLK_XUSB_DEV 289
320#define TEGRA210_CLK_XUSB_HS_SRC 290
321#define TEGRA210_CLK_SCLK 291
322#define TEGRA210_CLK_HCLK 292
323#define TEGRA210_CLK_PCLK 293
324#define TEGRA210_CLK_CCLK_G 294
325#define TEGRA210_CLK_CCLK_LP 295
326#define TEGRA210_CLK_DFLL_REF 296
327#define TEGRA210_CLK_DFLL_SOC 297
328#define TEGRA210_CLK_VI_SENSOR2 298
329#define TEGRA210_CLK_PLL_P_OUT5 299
330#define TEGRA210_CLK_CML0 300
331#define TEGRA210_CLK_CML1 301
332#define TEGRA210_CLK_PLL_C4 302
333#define TEGRA210_CLK_PLL_DP 303
334#define TEGRA210_CLK_PLL_E_MUX 304
335#define TEGRA210_CLK_PLL_MB 305
336#define TEGRA210_CLK_PLL_A1 306
337#define TEGRA210_CLK_PLL_D_DSI_OUT 307
338#define TEGRA210_CLK_PLL_C4_OUT0 308
339#define TEGRA210_CLK_PLL_C4_OUT1 309
340#define TEGRA210_CLK_PLL_C4_OUT2 310
341#define TEGRA210_CLK_PLL_C4_OUT3 311
342#define TEGRA210_CLK_PLL_U_OUT 312
343#define TEGRA210_CLK_PLL_U_OUT1 313
344#define TEGRA210_CLK_PLL_U_OUT2 314
345#define TEGRA210_CLK_USB2_HSIC_TRK 315
346#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
347#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
348#define TEGRA210_CLK_XUSB_SSP_SRC 318
349/* 319 */
350/* 320 */
351/* 321 */
352/* 322 */
353/* 323 */
354/* 324 */
355/* 325 */
356/* 326 */
357/* 327 */
358/* 328 */
359/* 329 */
360/* 330 */
361/* 331 */
362/* 332 */
363/* 333 */
364/* 334 */
365/* 335 */
366/* 336 */
367/* 337 */
368/* 338 */
369/* 339 */
370/* 340 */
371/* 341 */
372/* 342 */
373/* 343 */
374/* 344 */
375/* 345 */
376/* 346 */
377/* 347 */
378/* 348 */
379/* 349 */
380
381#define TEGRA210_CLK_AUDIO0_MUX 350
382#define TEGRA210_CLK_AUDIO1_MUX 351
383#define TEGRA210_CLK_AUDIO2_MUX 352
384#define TEGRA210_CLK_AUDIO3_MUX 353
385#define TEGRA210_CLK_AUDIO4_MUX 354
386#define TEGRA210_CLK_SPDIF_MUX 355
387#define TEGRA210_CLK_CLK_OUT_1_MUX 356
388#define TEGRA210_CLK_CLK_OUT_2_MUX 357
389#define TEGRA210_CLK_CLK_OUT_3_MUX 358
390#define TEGRA210_CLK_DSIA_MUX 359
391#define TEGRA210_CLK_DSIB_MUX 360
392#define TEGRA210_CLK_SOR0_LVDS 361
393#define TEGRA210_CLK_XUSB_SS_DIV2 362
394
395#define TEGRA210_CLK_PLL_M_UD 363
396#define TEGRA210_CLK_PLL_C_UD 364
397#define TEGRA210_CLK_SCLK_MUX 365
398
399#define TEGRA210_CLK_CLK_MAX 366
400
401#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 01:53:00 -0400