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authorAlex Deucher <alexander.deucher@amd.com>2013-08-20 19:08:22 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-30 16:31:22 -0400
commitb309ed98672705729bce271efb60f530290bbffd (patch)
treea98190562600ac8c3dab8d3cc16b23419b2961c7
parent53f3b25287d8eed5a274d85fe7192c5812045fa3 (diff)
drm/radeon: gcc fixes for ci dpm
Newer versions of gcc seem to wander off into the weeds when dealing with variable sizes arrays in structs. Rather than indexing the arrays, use pointer arithmetic. See bugs: https://bugs.freedesktop.org/show_bug.cgi?id=66932 https://bugs.freedesktop.org/show_bug.cgi?id=66972 https://bugs.freedesktop.org/show_bug.cgi?id=66945 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/ci_dpm.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 7a6068968b70..dd2a07c44c3a 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -4931,6 +4931,7 @@ static int ci_parse_power_table(struct radeon_device *rdev)
4931 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 4931 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
4932 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 4932 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
4933 for (i = 0; i < state_array->ucNumEntries; i++) { 4933 for (i = 0; i < state_array->ucNumEntries; i++) {
4934 u8 *idx;
4934 power_state = (union pplib_power_state *)power_state_offset; 4935 power_state = (union pplib_power_state *)power_state_offset;
4935 non_clock_array_index = power_state->v2.nonClockInfoIndex; 4936 non_clock_array_index = power_state->v2.nonClockInfoIndex;
4936 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 4937 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
@@ -4947,14 +4948,16 @@ static int ci_parse_power_table(struct radeon_device *rdev)
4947 non_clock_info, 4948 non_clock_info,
4948 non_clock_info_array->ucEntrySize); 4949 non_clock_info_array->ucEntrySize);
4949 k = 0; 4950 k = 0;
4951 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
4950 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 4952 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
4951 clock_array_index = power_state->v2.clockInfoIndex[j]; 4953 clock_array_index = idx[j];
4952 if (clock_array_index >= clock_info_array->ucNumEntries) 4954 if (clock_array_index >= clock_info_array->ucNumEntries)
4953 continue; 4955 continue;
4954 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) 4956 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
4955 break; 4957 break;
4956 clock_info = (union pplib_clock_info *) 4958 clock_info = (union pplib_clock_info *)
4957 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 4959 ((u8 *)&clock_info_array->clockInfo[0] +
4960 (clock_array_index * clock_info_array->ucEntrySize));
4958 ci_parse_pplib_clock_info(rdev, 4961 ci_parse_pplib_clock_info(rdev,
4959 &rdev->pm.dpm.ps[i], k, 4962 &rdev->pm.dpm.ps[i], k,
4960 clock_info); 4963 clock_info);