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authorJörg Krause <joerg.krause@embedded.rocks>2017-01-13 15:44:28 -0500
committerMark Brown <broonie@kernel.org>2017-01-17 13:19:36 -0500
commitb25658ed7d24cd8b1f9a72148e80e216b6a0c17a (patch)
tree83e19bcd6583ce3aa7bb945105bdda94fd85db84
parenta5de5b74a50113564a1e0850e2da96c37c35e55d (diff)
ASoC: mxs-saif: fix setting SAIF1 register
If SAIF0 is used in master and SAIF1 in slave mode setting the SAIF1 register in mxs_saif_set_dai_fmt() does not have any effect on the interface as the clk gate needs to be cleared before the register can be written. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/mxs/mxs-saif.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index a002ab892772..9012a2036131 100644
--- a/sound/soc/mxs/mxs-saif.c
+++ b/sound/soc/mxs/mxs-saif.c
@@ -299,6 +299,16 @@ static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
299 return -EBUSY; 299 return -EBUSY;
300 } 300 }
301 301
302 /* If SAIF1 is configured as slave, the clk gate needs to be cleared
303 * before the register can be written.
304 */
305 if (saif->id != saif->master_id) {
306 __raw_writel(BM_SAIF_CTRL_SFTRST,
307 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
308 __raw_writel(BM_SAIF_CTRL_CLKGATE,
309 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
310 }
311
302 scr0 = __raw_readl(saif->base + SAIF_CTRL); 312 scr0 = __raw_readl(saif->base + SAIF_CTRL);
303 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 313 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
304 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 314 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;