aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJerome Brunet <jbrunet@baylibre.com>2018-12-21 11:02:38 -0500
committerNeil Armstrong <narmstrong@baylibre.com>2019-01-07 09:21:22 -0500
commitb249623fd1472225232e8784864af55aec1fd81b (patch)
treec9c33648993d7c5ee2d4f6a26825f423ba410fa4
parenta8d552a63857c73c6f0ea28dc8a70df10764b820 (diff)
clk: meson: gxbb-ao: replace cec-32k with the dual divider
Replace the cec-32k clock of gxbb-ao with the simpler dual divider driver. The dual divider implements only the dividing part. All the other bits are now exposed using simple elements, such as gates and muxes Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181221160239.26265-5-jbrunet@baylibre.com
Diffstat
-rw-r--r--drivers/clk/meson/Makefile2
-rw-r--r--drivers/clk/meson/gxbb-aoclk-32k.c193
-rw-r--r--drivers/clk/meson/gxbb-aoclk.c251
-rw-r--r--drivers/clk/meson/gxbb-aoclk.h20
4 files changed, 204 insertions, 262 deletions
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index f1fcafc046d5..8234e92eea38 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o clk-dualdiv.o
7obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o 7obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
8obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o 8obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
9obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o 9obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
10obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o 10obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
11obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o 11obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
12obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o 12obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
13obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o 13obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/gxbb-aoclk-32k.c b/drivers/clk/meson/gxbb-aoclk-32k.c
deleted file mode 100644
index 680467141a1d..000000000000
--- a/drivers/clk/meson/gxbb-aoclk-32k.c
+++ /dev/null
@@ -1,193 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2017 BayLibre, SAS.
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/bitfield.h>
9#include <linux/regmap.h>
10#include "gxbb-aoclk.h"
11
12/*
13 * The AO Domain embeds a dual/divider to generate a more precise
14 * 32,768KHz clock for low-power suspend mode and CEC.
15 * ______ ______
16 * | | | |
17 * ______ | Div1 |-| Cnt1 | ______
18 * | | /|______| |______|\ | |
19 * Xtal-->| Gate |---| ______ ______ X-X--| Gate |-->
20 * |______| | \| | | |/ | |______|
21 * | | Div2 |-| Cnt2 | |
22 * | |______| |______| |
23 * |_______________________|
24 *
25 * The dividing can be switched to single or dual, with a counter
26 * for each divider to set when the switching is done.
27 * The entire dividing mechanism can be also bypassed.
28 */
29
30#define CLK_CNTL0_N1_MASK GENMASK(11, 0)
31#define CLK_CNTL0_N2_MASK GENMASK(23, 12)
32#define CLK_CNTL0_DUALDIV_EN BIT(28)
33#define CLK_CNTL0_OUT_GATE_EN BIT(30)
34#define CLK_CNTL0_IN_GATE_EN BIT(31)
35
36#define CLK_CNTL1_M1_MASK GENMASK(11, 0)
37#define CLK_CNTL1_M2_MASK GENMASK(23, 12)
38#define CLK_CNTL1_BYPASS_EN BIT(24)
39#define CLK_CNTL1_SELECT_OSC BIT(27)
40
41#define PWR_CNTL_ALT_32K_SEL GENMASK(13, 10)
42
43struct cec_32k_freq_table {
44 unsigned long parent_rate;
45 unsigned long target_rate;
46 bool dualdiv;
47 unsigned int n1;
48 unsigned int n2;
49 unsigned int m1;
50 unsigned int m2;
51};
52
53static const struct cec_32k_freq_table aoclk_cec_32k_table[] = {
54 [0] = {
55 .parent_rate = 24000000,
56 .target_rate = 32768,
57 .dualdiv = true,
58 .n1 = 733,
59 .n2 = 732,
60 .m1 = 8,
61 .m2 = 11,
62 },
63};
64
65/*
66 * If CLK_CNTL0_DUALDIV_EN == 0
67 * - will use N1 divider only
68 * If CLK_CNTL0_DUALDIV_EN == 1
69 * - hold M1 cycles of N1 divider then changes to N2
70 * - hold M2 cycles of N2 divider then changes to N1
71 * Then we can get more accurate division.
72 */
73static unsigned long aoclk_cec_32k_recalc_rate(struct clk_hw *hw,
74 unsigned long parent_rate)
75{
76 struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
77 unsigned long n1;
78 u32 reg0, reg1;
79
80 regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, &reg0);
81 regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, &reg1);
82
83 if (reg1 & CLK_CNTL1_BYPASS_EN)
84 return parent_rate;
85
86 if (reg0 & CLK_CNTL0_DUALDIV_EN) {
87 unsigned long n2, m1, m2, f1, f2, p1, p2;
88
89 n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
90 n2 = FIELD_GET(CLK_CNTL0_N2_MASK, reg0) + 1;
91
92 m1 = FIELD_GET(CLK_CNTL1_M1_MASK, reg1) + 1;
93 m2 = FIELD_GET(CLK_CNTL1_M2_MASK, reg1) + 1;
94
95 f1 = DIV_ROUND_CLOSEST(parent_rate, n1);
96 f2 = DIV_ROUND_CLOSEST(parent_rate, n2);
97
98 p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2));
99 p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2));
100
101 return DIV_ROUND_UP(100000000, p1 + p2);
102 }
103
104 n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
105
106 return DIV_ROUND_CLOSEST(parent_rate, n1);
107}
108
109static const struct cec_32k_freq_table *find_cec_32k_freq(unsigned long rate,
110 unsigned long prate)
111{
112 int i;
113
114 for (i = 0 ; i < ARRAY_SIZE(aoclk_cec_32k_table) ; ++i)
115 if (aoclk_cec_32k_table[i].parent_rate == prate &&
116 aoclk_cec_32k_table[i].target_rate == rate)
117 return &aoclk_cec_32k_table[i];
118
119 return NULL;
120}
121
122static long aoclk_cec_32k_round_rate(struct clk_hw *hw, unsigned long rate,
123 unsigned long *prate)
124{
125 const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
126 *prate);
127
128 /* If invalid return first one */
129 if (!freq)
130 return aoclk_cec_32k_table[0].target_rate;
131
132 return freq->target_rate;
133}
134
135/*
136 * From the Amlogic init procedure, the IN and OUT gates needs to be handled
137 * in the init procedure to avoid any glitches.
138 */
139
140static int aoclk_cec_32k_set_rate(struct clk_hw *hw, unsigned long rate,
141 unsigned long parent_rate)
142{
143 const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
144 parent_rate);
145 struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
146 u32 reg = 0;
147
148 if (!freq)
149 return -EINVAL;
150
151 /* Disable clock */
152 regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
153 CLK_CNTL0_IN_GATE_EN | CLK_CNTL0_OUT_GATE_EN, 0);
154
155 reg = FIELD_PREP(CLK_CNTL0_N1_MASK, freq->n1 - 1);
156 if (freq->dualdiv)
157 reg |= CLK_CNTL0_DUALDIV_EN |
158 FIELD_PREP(CLK_CNTL0_N2_MASK, freq->n2 - 1);
159
160 regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, reg);
161
162 reg = FIELD_PREP(CLK_CNTL1_M1_MASK, freq->m1 - 1);
163 if (freq->dualdiv)
164 reg |= FIELD_PREP(CLK_CNTL1_M2_MASK, freq->m2 - 1);
165
166 regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, reg);
167
168 /* Enable clock */
169 regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
170 CLK_CNTL0_IN_GATE_EN, CLK_CNTL0_IN_GATE_EN);
171
172 udelay(200);
173
174 regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
175 CLK_CNTL0_OUT_GATE_EN, CLK_CNTL0_OUT_GATE_EN);
176
177 regmap_update_bits(cec_32k->regmap, AO_CRT_CLK_CNTL1,
178 CLK_CNTL1_SELECT_OSC, CLK_CNTL1_SELECT_OSC);
179
180 /* Select 32k from XTAL */
181 regmap_update_bits(cec_32k->regmap,
182 AO_RTI_PWR_CNTL_REG0,
183 PWR_CNTL_ALT_32K_SEL,
184 FIELD_PREP(PWR_CNTL_ALT_32K_SEL, 4));
185
186 return 0;
187}
188
189const struct clk_ops meson_aoclk_cec_32k_ops = {
190 .recalc_rate = aoclk_cec_32k_recalc_rate,
191 .round_rate = aoclk_cec_32k_round_rate,
192 .set_rate = aoclk_cec_32k_set_rate,
193};
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 42ed61d3c3fb..5fa57b623b8f 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -5,10 +5,19 @@
5 */ 5 */
6#include <linux/platform_device.h> 6#include <linux/platform_device.h>
7#include <linux/mfd/syscon.h> 7#include <linux/mfd/syscon.h>
8#include "clk-regmap.h" 8#include "clkc.h"
9#include "meson-aoclk.h" 9#include "meson-aoclk.h"
10#include "gxbb-aoclk.h" 10#include "gxbb-aoclk.h"
11 11
12/* AO Configuration Clock registers offsets */
13#define AO_RTI_PWR_CNTL_REG1 0x0c
14#define AO_RTI_PWR_CNTL_REG0 0x10
15#define AO_RTI_GEN_CNTL_REG0 0x40
16#define AO_OSCIN_CNTL 0x58
17#define AO_CRT_CLK_CNTL1 0x68
18#define AO_RTC_ALT_CLK_CNTL0 0x94
19#define AO_RTC_ALT_CLK_CNTL1 0x98
20
12#define GXBB_AO_GATE(_name, _bit) \ 21#define GXBB_AO_GATE(_name, _bit) \
13static struct clk_regmap _name##_ao = { \ 22static struct clk_regmap _name##_ao = { \
14 .data = &(struct clk_regmap_gate_data) { \ 23 .data = &(struct clk_regmap_gate_data) { \
@@ -31,13 +40,174 @@ GXBB_AO_GATE(uart1, 3);
31GXBB_AO_GATE(uart2, 5); 40GXBB_AO_GATE(uart2, 5);
32GXBB_AO_GATE(ir_blaster, 6); 41GXBB_AO_GATE(ir_blaster, 6);
33 42
34static struct aoclk_cec_32k cec_32k_ao = { 43static struct clk_regmap ao_cts_oscin = {
35 .hw.init = &(struct clk_init_data) { 44 .data = &(struct clk_regmap_gate_data){
36 .name = "cec_32k_ao", 45 .offset = AO_RTI_PWR_CNTL_REG0,
37 .ops = &meson_aoclk_cec_32k_ops, 46 .bit_idx = 6,
47 },
48 .hw.init = &(struct clk_init_data){
49 .name = "ao_cts_oscin",
50 .ops = &clk_regmap_gate_ro_ops,
38 .parent_names = (const char *[]){ "xtal" }, 51 .parent_names = (const char *[]){ "xtal" },
39 .num_parents = 1, 52 .num_parents = 1,
40 .flags = CLK_IGNORE_UNUSED, 53 },
54};
55
56static struct clk_regmap ao_32k_pre = {
57 .data = &(struct clk_regmap_gate_data){
58 .offset = AO_RTC_ALT_CLK_CNTL0,
59 .bit_idx = 31,
60 },
61 .hw.init = &(struct clk_init_data){
62 .name = "ao_32k_pre",
63 .ops = &clk_regmap_gate_ops,
64 .parent_names = (const char *[]){ "ao_cts_oscin" },
65 .num_parents = 1,
66 },
67};
68
69static const struct meson_clk_dualdiv_param gxbb_32k_div_table[] = {
70 {
71 .dual = 1,
72 .n1 = 733,
73 .m1 = 8,
74 .n2 = 732,
75 .m2 = 11,
76 }, {}
77};
78
79static struct clk_regmap ao_32k_div = {
80 .data = &(struct meson_clk_dualdiv_data){
81 .n1 = {
82 .reg_off = AO_RTC_ALT_CLK_CNTL0,
83 .shift = 0,
84 .width = 12,
85 },
86 .n2 = {
87 .reg_off = AO_RTC_ALT_CLK_CNTL0,
88 .shift = 12,
89 .width = 12,
90 },
91 .m1 = {
92 .reg_off = AO_RTC_ALT_CLK_CNTL1,
93 .shift = 0,
94 .width = 12,
95 },
96 .m2 = {
97 .reg_off = AO_RTC_ALT_CLK_CNTL1,
98 .shift = 12,
99 .width = 12,
100 },
101 .dual = {
102 .reg_off = AO_RTC_ALT_CLK_CNTL0,
103 .shift = 28,
104 .width = 1,
105 },
106 .table = gxbb_32k_div_table,
107 },
108 .hw.init = &(struct clk_init_data){
109 .name = "ao_32k_div",
110 .ops = &meson_clk_dualdiv_ops,
111 .parent_names = (const char *[]){ "ao_32k_pre" },
112 .num_parents = 1,
113 },
114};
115
116static struct clk_regmap ao_32k_sel = {
117 .data = &(struct clk_regmap_mux_data) {
118 .offset = AO_RTC_ALT_CLK_CNTL1,
119 .mask = 0x1,
120 .shift = 24,
121 .flags = CLK_MUX_ROUND_CLOSEST,
122 },
123 .hw.init = &(struct clk_init_data){
124 .name = "ao_32k_sel",
125 .ops = &clk_regmap_mux_ops,
126 .parent_names = (const char *[]){ "ao_32k_div",
127 "ao_32k_pre" },
128 .num_parents = 2,
129 .flags = CLK_SET_RATE_PARENT,
130 },
131};
132
133static struct clk_regmap ao_32k = {
134 .data = &(struct clk_regmap_gate_data){
135 .offset = AO_RTC_ALT_CLK_CNTL0,
136 .bit_idx = 30,
137 },
138 .hw.init = &(struct clk_init_data){
139 .name = "ao_32k",
140 .ops = &clk_regmap_gate_ops,
141 .parent_names = (const char *[]){ "ao_32k_sel" },
142 .num_parents = 1,
143 .flags = CLK_SET_RATE_PARENT,
144 },
145};
146
147static struct clk_regmap ao_cts_rtc_oscin = {
148 .data = &(struct clk_regmap_mux_data) {
149 .offset = AO_RTI_PWR_CNTL_REG0,
150 .mask = 0x7,
151 .shift = 10,
152 .table = (u32[]){ 1, 2, 3, 4 },
153 .flags = CLK_MUX_ROUND_CLOSEST,
154 },
155 .hw.init = &(struct clk_init_data){
156 .name = "ao_cts_rtc_oscin",
157 .ops = &clk_regmap_mux_ops,
158 .parent_names = (const char *[]){ "ext_32k_0",
159 "ext_32k_1",
160 "ext_32k_2",
161 "ao_32k" },
162 .num_parents = 4,
163 .flags = CLK_SET_RATE_PARENT,
164 },
165};
166
167static struct clk_regmap ao_clk81 = {
168 .data = &(struct clk_regmap_mux_data) {
169 .offset = AO_RTI_PWR_CNTL_REG0,
170 .mask = 0x1,
171 .shift = 0,
172 .flags = CLK_MUX_ROUND_CLOSEST,
173 },
174 .hw.init = &(struct clk_init_data){
175 .name = "ao_clk81",
176 .ops = &clk_regmap_mux_ro_ops,
177 .parent_names = (const char *[]){ "clk81",
178 "ao_cts_rtc_oscin" },
179 .num_parents = 2,
180 .flags = CLK_SET_RATE_PARENT,
181 },
182};
183
184static struct clk_regmap ao_cts_cec = {
185 .data = &(struct clk_regmap_mux_data) {
186 .offset = AO_CRT_CLK_CNTL1,
187 .mask = 0x1,
188 .shift = 27,
189 .flags = CLK_MUX_ROUND_CLOSEST,
190 },
191 .hw.init = &(struct clk_init_data){
192 .name = "ao_cts_cec",
193 .ops = &clk_regmap_mux_ops,
194 /*
195 * FIXME: The 'fixme' parent obviously does not exist.
196 *
197 * ATM, CCF won't call get_parent() if num_parents is 1. It
198 * does not allow NULL as a parent name either.
199 *
200 * On this particular mux, we only know the input #1 parent
201 * but, on boot, unknown input #0 is set, so it is critical
202 * to call .get_parent() on it
203 *
204 * Until CCF gets fixed, adding this fake parent that won't
205 * ever be registered should work around the problem
206 */
207 .parent_names = (const char *[]){ "fixme",
208 "ao_cts_rtc_oscin" },
209 .num_parents = 2,
210 .flags = CLK_SET_RATE_PARENT,
41 }, 211 },
42}; 212};
43 213
@@ -50,13 +220,21 @@ static const unsigned int gxbb_aoclk_reset[] = {
50 [RESET_AO_IR_BLASTER] = 23, 220 [RESET_AO_IR_BLASTER] = 23,
51}; 221};
52 222
53static struct clk_regmap *gxbb_aoclk_gate[] = { 223static struct clk_regmap *gxbb_aoclk[] = {
54 [CLKID_AO_REMOTE] = &remote_ao, 224 &remote_ao,
55 [CLKID_AO_I2C_MASTER] = &i2c_master_ao, 225 &i2c_master_ao,
56 [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao, 226 &i2c_slave_ao,
57 [CLKID_AO_UART1] = &uart1_ao, 227 &uart1_ao,
58 [CLKID_AO_UART2] = &uart2_ao, 228 &uart2_ao,
59 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao, 229 &ir_blaster_ao,
230 &ao_cts_oscin,
231 &ao_32k_pre,
232 &ao_32k_div,
233 &ao_32k_sel,
234 &ao_32k,
235 &ao_cts_rtc_oscin,
236 &ao_clk81,
237 &ao_cts_cec,
60}; 238};
61 239
62static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = { 240static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
@@ -67,52 +245,27 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
67 [CLKID_AO_UART1] = &uart1_ao.hw, 245 [CLKID_AO_UART1] = &uart1_ao.hw,
68 [CLKID_AO_UART2] = &uart2_ao.hw, 246 [CLKID_AO_UART2] = &uart2_ao.hw,
69 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw, 247 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
70 [CLKID_AO_CEC_32K] = &cec_32k_ao.hw, 248 [CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
249 [CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
250 [CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
251 [CLKID_AO_32K_DIV] = &ao_32k_div.hw,
252 [CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
253 [CLKID_AO_32K] = &ao_32k.hw,
254 [CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
255 [CLKID_AO_CLK81] = &ao_clk81.hw,
71 }, 256 },
72 .num = NR_CLKS, 257 .num = NR_CLKS,
73}; 258};
74 259
75static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
76{
77 struct device *dev = &pdev->dev;
78 struct regmap *regmap;
79 int ret;
80
81 regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
82 if (IS_ERR(regmap)) {
83 dev_err(dev, "failed to get regmap\n");
84 return PTR_ERR(regmap);
85 }
86
87 /* Specific clocks */
88 cec_32k_ao.regmap = regmap;
89 ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
90 if (ret) {
91 dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
92 return ret;
93 }
94
95 return 0;
96}
97
98static const struct meson_aoclk_data gxbb_aoclkc_data = { 260static const struct meson_aoclk_data gxbb_aoclkc_data = {
99 .reset_reg = AO_RTI_GEN_CNTL_REG0, 261 .reset_reg = AO_RTI_GEN_CNTL_REG0,
100 .num_reset = ARRAY_SIZE(gxbb_aoclk_reset), 262 .num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
101 .reset = gxbb_aoclk_reset, 263 .reset = gxbb_aoclk_reset,
102 .num_clks = ARRAY_SIZE(gxbb_aoclk_gate), 264 .num_clks = ARRAY_SIZE(gxbb_aoclk),
103 .clks = gxbb_aoclk_gate, 265 .clks = gxbb_aoclk,
104 .hw_data = &gxbb_aoclk_onecell_data, 266 .hw_data = &gxbb_aoclk_onecell_data,
105}; 267};
106 268
107static int gxbb_aoclkc_probe(struct platform_device *pdev)
108{
109 int ret = gxbb_register_cec_ao_32k(pdev);
110 if (ret)
111 return ret;
112
113 return meson_aoclkc_probe(pdev);
114}
115
116static const struct of_device_id gxbb_aoclkc_match_table[] = { 269static const struct of_device_id gxbb_aoclkc_match_table[] = {
117 { 270 {
118 .compatible = "amlogic,meson-gx-aoclkc", 271 .compatible = "amlogic,meson-gx-aoclkc",
@@ -122,7 +275,7 @@ static const struct of_device_id gxbb_aoclkc_match_table[] = {
122}; 275};
123 276
124static struct platform_driver gxbb_aoclkc_driver = { 277static struct platform_driver gxbb_aoclkc_driver = {
125 .probe = gxbb_aoclkc_probe, 278 .probe = meson_aoclkc_probe,
126 .driver = { 279 .driver = {
127 .name = "gxbb-aoclkc", 280 .name = "gxbb-aoclkc",
128 .of_match_table = gxbb_aoclkc_match_table, 281 .of_match_table = gxbb_aoclkc_match_table,
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index c514493d989a..1db16f9b37d4 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -7,25 +7,7 @@
7#ifndef __GXBB_AOCLKC_H 7#ifndef __GXBB_AOCLKC_H
8#define __GXBB_AOCLKC_H 8#define __GXBB_AOCLKC_H
9 9
10#define NR_CLKS 7 10#define NR_CLKS 14
11
12/* AO Configuration Clock registers offsets */
13#define AO_RTI_PWR_CNTL_REG1 0x0c
14#define AO_RTI_PWR_CNTL_REG0 0x10
15#define AO_RTI_GEN_CNTL_REG0 0x40
16#define AO_OSCIN_CNTL 0x58
17#define AO_CRT_CLK_CNTL1 0x68
18#define AO_RTC_ALT_CLK_CNTL0 0x94
19#define AO_RTC_ALT_CLK_CNTL1 0x98
20
21struct aoclk_cec_32k {
22 struct clk_hw hw;
23 struct regmap *regmap;
24};
25
26#define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
27
28extern const struct clk_ops meson_aoclk_cec_32k_ops;
29 11
30#include <dt-bindings/clock/gxbb-aoclkc.h> 12#include <dt-bindings/clock/gxbb-aoclkc.h>
31#include <dt-bindings/reset/gxbb-aoclkc.h> 13#include <dt-bindings/reset/gxbb-aoclkc.h>
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 00:37:59 -0400