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authorThomas Garnier <thgarnie@google.com>2016-06-21 20:47:01 -0400
committerIngo Molnar <mingo@kernel.org>2016-07-08 11:33:46 -0400
commitb234e8a09003af108d3573f0369e25c080676b14 (patch)
tree43aa87bc7daf673d658d77d0ad50cd23cea1f8ea
parentfaa379332f3cb3375db1849e27386f8bc9b97da4 (diff)
x86/mm: Separate variable for trampoline PGD
Use a separate global variable to define the trampoline PGD used to start other processors. This change will allow KALSR memory randomization to change the trampoline PGD to be correctly aligned with physical memory. Signed-off-by: Thomas Garnier <thgarnie@google.com> Signed-off-by: Kees Cook <keescook@chromium.org> Cc: Alexander Kuleshov <kuleshovmail@gmail.com> Cc: Alexander Popov <alpopov@ptsecurity.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Cc: Baoquan He <bhe@redhat.com> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Borislav Petkov <bp@suse.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Dave Young <dyoung@redhat.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jan Beulich <JBeulich@suse.com> Cc: Joerg Roedel <jroedel@suse.de> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Juergen Gross <jgross@suse.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Lv Zheng <lv.zheng@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Matt Fleming <matt@codeblueprint.co.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephen Smalley <sds@tycho.nsa.gov> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Toshi Kani <toshi.kani@hpe.com> Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: kernel-hardening@lists.openwall.com Cc: linux-doc@vger.kernel.org Link: http://lkml.kernel.org/r/1466556426-32664-5-git-send-email-keescook@chromium.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/include/asm/pgtable.h12
-rw-r--r--arch/x86/mm/init.c3
-rw-r--r--arch/x86/realmode/init.c5
3 files changed, 19 insertions, 1 deletions
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 1a27396b6ea0..d455bef39e9c 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -729,6 +729,18 @@ extern int direct_gbpages;
729void init_mem_mapping(void); 729void init_mem_mapping(void);
730void early_alloc_pgt_buf(void); 730void early_alloc_pgt_buf(void);
731 731
732#ifdef CONFIG_X86_64
733/* Realmode trampoline initialization. */
734extern pgd_t trampoline_pgd_entry;
735static inline void __meminit init_trampoline(void)
736{
737 /* Default trampoline pgd value */
738 trampoline_pgd_entry = init_level4_pgt[pgd_index(__PAGE_OFFSET)];
739}
740#else
741static inline void init_trampoline(void) { }
742#endif
743
732/* local pte updates need not use xchg for locking */ 744/* local pte updates need not use xchg for locking */
733static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) 745static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep)
734{ 746{
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 372aad2b3291..4252acdfcbbd 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -590,6 +590,9 @@ void __init init_mem_mapping(void)
590 /* the ISA range is always mapped regardless of memory holes */ 590 /* the ISA range is always mapped regardless of memory holes */
591 init_memory_mapping(0, ISA_END_ADDRESS); 591 init_memory_mapping(0, ISA_END_ADDRESS);
592 592
593 /* Init the trampoline, possibly with KASLR memory offset */
594 init_trampoline();
595
593 /* 596 /*
594 * If the allocation is in bottom-up direction, we setup direct mapping 597 * If the allocation is in bottom-up direction, we setup direct mapping
595 * in bottom-up, otherwise we setup direct mapping in top-down. 598 * in bottom-up, otherwise we setup direct mapping in top-down.
diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c
index 0b7a63d98440..705e3fffb4a1 100644
--- a/arch/x86/realmode/init.c
+++ b/arch/x86/realmode/init.c
@@ -8,6 +8,9 @@
8struct real_mode_header *real_mode_header; 8struct real_mode_header *real_mode_header;
9u32 *trampoline_cr4_features; 9u32 *trampoline_cr4_features;
10 10
11/* Hold the pgd entry used on booting additional CPUs */
12pgd_t trampoline_pgd_entry;
13
11void __init reserve_real_mode(void) 14void __init reserve_real_mode(void)
12{ 15{
13 phys_addr_t mem; 16 phys_addr_t mem;
@@ -84,7 +87,7 @@ void __init setup_real_mode(void)
84 *trampoline_cr4_features = __read_cr4(); 87 *trampoline_cr4_features = __read_cr4();
85 88
86 trampoline_pgd = (u64 *) __va(real_mode_header->trampoline_pgd); 89 trampoline_pgd = (u64 *) __va(real_mode_header->trampoline_pgd);
87 trampoline_pgd[0] = init_level4_pgt[pgd_index(__PAGE_OFFSET)].pgd; 90 trampoline_pgd[0] = trampoline_pgd_entry.pgd;
88 trampoline_pgd[511] = init_level4_pgt[511].pgd; 91 trampoline_pgd[511] = init_level4_pgt[511].pgd;
89#endif 92#endif
90} 93}