diff options
author | David S. Miller <davem@davemloft.net> | 2017-05-08 15:15:03 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2017-05-08 15:15:03 -0400 |
commit | b210aeaedfc47ab8a86fbdcad46caf1e49cc0e37 (patch) | |
tree | fdbb5d9c32b7b7ffc3fa8cdc0e1a01c2fd6c286c | |
parent | 8ed508fd4b84a38db63ddeee8ab6905f06cfa589 (diff) | |
parent | 70fe4432bb360207fba04b4137f330a7a109f7a6 (diff) |
Merge branch 'stmmac-pci-fix-crash-on-Intel-Galileo-Gen2'
Andy Shevchenko says:
====================
stmmac: pci: Fix crash on Intel Galileo Gen2
Due to misconfiguration of PCI driver for Intel Quark the user will get
a kernel crash:
udhcpc: started, v1.26.2
stmmaceth 0000:00:14.6 eth0: device MAC address 98:4f:ee:05:ac:47
Generic PHY stmmac-a6:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-a6:01, irq=-1)
stmmaceth 0000:00:14.6 eth0: IEEE 1588-2008 Advanced Timestamp supported
stmmaceth 0000:00:14.6 eth0: registered PTP clock
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc: sending discover
stmmaceth 0000:00:14.6 eth0: Link is Up - 100Mbps/Full - flow control off
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
BUG: unable to handle kernel NULL pointer dereference at (null)
IP: stmmac_xmit+0xf1/0x1080
Fix this by adding necessary settings.
P.S. I split fix to three patches according to what each of them adds.
====================
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 41 |
1 files changed, 18 insertions, 23 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c index 39be96779145..22f910795be4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | |||
@@ -70,11 +70,8 @@ static int stmmac_pci_find_phy_addr(struct stmmac_pci_info *info) | |||
70 | return -ENODEV; | 70 | return -ENODEV; |
71 | } | 71 | } |
72 | 72 | ||
73 | static void stmmac_default_data(struct plat_stmmacenet_data *plat) | 73 | static void common_default_data(struct plat_stmmacenet_data *plat) |
74 | { | 74 | { |
75 | plat->bus_id = 1; | ||
76 | plat->phy_addr = 0; | ||
77 | plat->interface = PHY_INTERFACE_MODE_GMII; | ||
78 | plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ | 75 | plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ |
79 | plat->has_gmac = 1; | 76 | plat->has_gmac = 1; |
80 | plat->force_sf_dma_mode = 1; | 77 | plat->force_sf_dma_mode = 1; |
@@ -82,10 +79,6 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat) | |||
82 | plat->mdio_bus_data->phy_reset = NULL; | 79 | plat->mdio_bus_data->phy_reset = NULL; |
83 | plat->mdio_bus_data->phy_mask = 0; | 80 | plat->mdio_bus_data->phy_mask = 0; |
84 | 81 | ||
85 | plat->dma_cfg->pbl = 32; | ||
86 | plat->dma_cfg->pblx8 = true; | ||
87 | /* TODO: AXI */ | ||
88 | |||
89 | /* Set default value for multicast hash bins */ | 82 | /* Set default value for multicast hash bins */ |
90 | plat->multicast_filter_bins = HASH_TABLE_SIZE; | 83 | plat->multicast_filter_bins = HASH_TABLE_SIZE; |
91 | 84 | ||
@@ -107,12 +100,29 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat) | |||
107 | plat->rx_queues_cfg[0].pkt_route = 0x0; | 100 | plat->rx_queues_cfg[0].pkt_route = 0x0; |
108 | } | 101 | } |
109 | 102 | ||
103 | static void stmmac_default_data(struct plat_stmmacenet_data *plat) | ||
104 | { | ||
105 | /* Set common default data first */ | ||
106 | common_default_data(plat); | ||
107 | |||
108 | plat->bus_id = 1; | ||
109 | plat->phy_addr = 0; | ||
110 | plat->interface = PHY_INTERFACE_MODE_GMII; | ||
111 | |||
112 | plat->dma_cfg->pbl = 32; | ||
113 | plat->dma_cfg->pblx8 = true; | ||
114 | /* TODO: AXI */ | ||
115 | } | ||
116 | |||
110 | static int quark_default_data(struct plat_stmmacenet_data *plat, | 117 | static int quark_default_data(struct plat_stmmacenet_data *plat, |
111 | struct stmmac_pci_info *info) | 118 | struct stmmac_pci_info *info) |
112 | { | 119 | { |
113 | struct pci_dev *pdev = info->pdev; | 120 | struct pci_dev *pdev = info->pdev; |
114 | int ret; | 121 | int ret; |
115 | 122 | ||
123 | /* Set common default data first */ | ||
124 | common_default_data(plat); | ||
125 | |||
116 | /* | 126 | /* |
117 | * Refuse to load the driver and register net device if MAC controller | 127 | * Refuse to load the driver and register net device if MAC controller |
118 | * does not connect to any PHY interface. | 128 | * does not connect to any PHY interface. |
@@ -124,27 +134,12 @@ static int quark_default_data(struct plat_stmmacenet_data *plat, | |||
124 | plat->bus_id = PCI_DEVID(pdev->bus->number, pdev->devfn); | 134 | plat->bus_id = PCI_DEVID(pdev->bus->number, pdev->devfn); |
125 | plat->phy_addr = ret; | 135 | plat->phy_addr = ret; |
126 | plat->interface = PHY_INTERFACE_MODE_RMII; | 136 | plat->interface = PHY_INTERFACE_MODE_RMII; |
127 | plat->clk_csr = 2; | ||
128 | plat->has_gmac = 1; | ||
129 | plat->force_sf_dma_mode = 1; | ||
130 | |||
131 | plat->mdio_bus_data->phy_reset = NULL; | ||
132 | plat->mdio_bus_data->phy_mask = 0; | ||
133 | 137 | ||
134 | plat->dma_cfg->pbl = 16; | 138 | plat->dma_cfg->pbl = 16; |
135 | plat->dma_cfg->pblx8 = true; | 139 | plat->dma_cfg->pblx8 = true; |
136 | plat->dma_cfg->fixed_burst = 1; | 140 | plat->dma_cfg->fixed_burst = 1; |
137 | /* AXI (TODO) */ | 141 | /* AXI (TODO) */ |
138 | 142 | ||
139 | /* Set default value for multicast hash bins */ | ||
140 | plat->multicast_filter_bins = HASH_TABLE_SIZE; | ||
141 | |||
142 | /* Set default value for unicast filter entries */ | ||
143 | plat->unicast_filter_entries = 1; | ||
144 | |||
145 | /* Set the maxmtu to a default of JUMBO_LEN */ | ||
146 | plat->maxmtu = JUMBO_LEN; | ||
147 | |||
148 | return 0; | 143 | return 0; |
149 | } | 144 | } |
150 | 145 | ||