diff options
author | Jani Nikula <jani.nikula@intel.com> | 2018-05-14 04:18:06 -0400 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2018-05-14 04:18:06 -0400 |
commit | b1705f729dc7c7cdeeef712272b13886b2904ad0 (patch) | |
tree | c55a0cf612788297d3518ffddfc7aef09a9063c9 | |
parent | 0c79f9cb77eae28d48a4f9fc1b3341aacbbd260c (diff) | |
parent | 41e403d04e7050c8d88682939febcdbe117d4c82 (diff) |
Merge tag 'gvt-next-2018-05-14' of https://github.com/intel/gvt-linux into drm-intel-next-queued
- Improve the emulation of virtual non-priv register. (Yan)
- Reverse the hack of host of preeption of GVT-g. (Weinan)
- Improve untracked warning message.(Changbin)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ebae7cf1-6550-bb44-74a2-d3a014051804@intel.com
-rw-r--r-- | drivers/gpu/drm/i915/gvt/cmd_parser.c | 26 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gvt/gvt.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 35 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gvt/mmio.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gvt/scheduler.c | 3 |
5 files changed, 39 insertions, 28 deletions
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index a294427088d8..718ca08f9575 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c | |||
@@ -813,15 +813,31 @@ static inline bool is_force_nonpriv_mmio(unsigned int offset) | |||
813 | } | 813 | } |
814 | 814 | ||
815 | static int force_nonpriv_reg_handler(struct parser_exec_state *s, | 815 | static int force_nonpriv_reg_handler(struct parser_exec_state *s, |
816 | unsigned int offset, unsigned int index) | 816 | unsigned int offset, unsigned int index, char *cmd) |
817 | { | 817 | { |
818 | struct intel_gvt *gvt = s->vgpu->gvt; | 818 | struct intel_gvt *gvt = s->vgpu->gvt; |
819 | unsigned int data = cmd_val(s, index + 1); | 819 | unsigned int data; |
820 | u32 ring_base; | ||
821 | u32 nopid; | ||
822 | struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; | ||
823 | |||
824 | if (!strcmp(cmd, "lri")) | ||
825 | data = cmd_val(s, index + 1); | ||
826 | else { | ||
827 | gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n", | ||
828 | offset, cmd); | ||
829 | return -EINVAL; | ||
830 | } | ||
820 | 831 | ||
821 | if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) { | 832 | ring_base = dev_priv->engine[s->ring_id]->mmio_base; |
833 | nopid = i915_mmio_reg_offset(RING_NOPID(ring_base)); | ||
834 | |||
835 | if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) && | ||
836 | data != nopid) { | ||
822 | gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n", | 837 | gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n", |
823 | offset, data); | 838 | offset, data); |
824 | return -EPERM; | 839 | patch_value(s, cmd_ptr(s, index), nopid); |
840 | return 0; | ||
825 | } | 841 | } |
826 | return 0; | 842 | return 0; |
827 | } | 843 | } |
@@ -869,7 +885,7 @@ static int cmd_reg_handler(struct parser_exec_state *s, | |||
869 | return -EINVAL; | 885 | return -EINVAL; |
870 | 886 | ||
871 | if (is_force_nonpriv_mmio(offset) && | 887 | if (is_force_nonpriv_mmio(offset) && |
872 | force_nonpriv_reg_handler(s, offset, index)) | 888 | force_nonpriv_reg_handler(s, offset, index, cmd)) |
873 | return -EPERM; | 889 | return -EPERM; |
874 | 890 | ||
875 | if (offset == i915_mmio_reg_offset(DERRMR) || | 891 | if (offset == i915_mmio_reg_offset(DERRMR) || |
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 6ec888822a0f..05d15a095310 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h | |||
@@ -99,7 +99,6 @@ struct intel_vgpu_fence { | |||
99 | struct intel_vgpu_mmio { | 99 | struct intel_vgpu_mmio { |
100 | void *vreg; | 100 | void *vreg; |
101 | void *sreg; | 101 | void *sreg; |
102 | bool disable_warn_untrack; | ||
103 | }; | 102 | }; |
104 | 103 | ||
105 | #define INTEL_GVT_MAX_BAR_NUM 4 | 104 | #define INTEL_GVT_MAX_BAR_NUM 4 |
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index a33c1c3e4a21..4b6532fb789a 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c | |||
@@ -191,6 +191,8 @@ static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, | |||
191 | unsigned int max_fence = vgpu_fence_sz(vgpu); | 191 | unsigned int max_fence = vgpu_fence_sz(vgpu); |
192 | 192 | ||
193 | if (fence_num >= max_fence) { | 193 | if (fence_num >= max_fence) { |
194 | gvt_vgpu_err("access oob fence reg %d/%d\n", | ||
195 | fence_num, max_fence); | ||
194 | 196 | ||
195 | /* When guest access oob fence regs without access | 197 | /* When guest access oob fence regs without access |
196 | * pv_info first, we treat guest not supporting GVT, | 198 | * pv_info first, we treat guest not supporting GVT, |
@@ -200,11 +202,6 @@ static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, | |||
200 | enter_failsafe_mode(vgpu, | 202 | enter_failsafe_mode(vgpu, |
201 | GVT_FAILSAFE_UNSUPPORTED_GUEST); | 203 | GVT_FAILSAFE_UNSUPPORTED_GUEST); |
202 | 204 | ||
203 | if (!vgpu->mmio.disable_warn_untrack) { | ||
204 | gvt_vgpu_err("found oob fence register access\n"); | ||
205 | gvt_vgpu_err("total fence %d, access fence %d\n", | ||
206 | max_fence, fence_num); | ||
207 | } | ||
208 | memset(p_data, 0, bytes); | 205 | memset(p_data, 0, bytes); |
209 | return -EINVAL; | 206 | return -EINVAL; |
210 | } | 207 | } |
@@ -477,22 +474,28 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu, | |||
477 | unsigned int offset, void *p_data, unsigned int bytes) | 474 | unsigned int offset, void *p_data, unsigned int bytes) |
478 | { | 475 | { |
479 | u32 reg_nonpriv = *(u32 *)p_data; | 476 | u32 reg_nonpriv = *(u32 *)p_data; |
477 | int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); | ||
478 | u32 ring_base; | ||
479 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | ||
480 | int ret = -EINVAL; | 480 | int ret = -EINVAL; |
481 | 481 | ||
482 | if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) { | 482 | if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) { |
483 | gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", | 483 | gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n", |
484 | vgpu->id, offset, bytes); | 484 | vgpu->id, ring_id, offset, bytes); |
485 | return ret; | 485 | return ret; |
486 | } | 486 | } |
487 | 487 | ||
488 | if (in_whitelist(reg_nonpriv)) { | 488 | ring_base = dev_priv->engine[ring_id]->mmio_base; |
489 | |||
490 | if (in_whitelist(reg_nonpriv) || | ||
491 | reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { | ||
489 | ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, | 492 | ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, |
490 | bytes); | 493 | bytes); |
491 | } else { | 494 | } else |
492 | gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n", | 495 | gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", |
493 | vgpu->id, reg_nonpriv); | 496 | vgpu->id, reg_nonpriv, offset); |
494 | } | 497 | |
495 | return ret; | 498 | return 0; |
496 | } | 499 | } |
497 | 500 | ||
498 | static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | 501 | static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, |
@@ -3092,9 +3095,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, | |||
3092 | */ | 3095 | */ |
3093 | mmio_info = find_mmio_info(gvt, offset); | 3096 | mmio_info = find_mmio_info(gvt, offset); |
3094 | if (!mmio_info) { | 3097 | if (!mmio_info) { |
3095 | if (!vgpu->mmio.disable_warn_untrack) | 3098 | gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); |
3096 | gvt_vgpu_err("untracked MMIO %08x len %d\n", | ||
3097 | offset, bytes); | ||
3098 | goto default_rw; | 3099 | goto default_rw; |
3099 | } | 3100 | } |
3100 | 3101 | ||
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c index 11b71b33f1c0..e4960aff68bd 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.c +++ b/drivers/gpu/drm/i915/gvt/mmio.c | |||
@@ -244,8 +244,6 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr) | |||
244 | 244 | ||
245 | /* set the bit 0:2(Core C-State ) to C0 */ | 245 | /* set the bit 0:2(Core C-State ) to C0 */ |
246 | vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; | 246 | vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; |
247 | |||
248 | vgpu->mmio.disable_warn_untrack = false; | ||
249 | } else { | 247 | } else { |
250 | #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200) | 248 | #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200) |
251 | /* only reset the engine related, so starting with 0x44200 | 249 | /* only reset the engine related, so starting with 0x44200 |
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index ffb45a9ee228..c2d183b91500 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c | |||
@@ -1156,9 +1156,6 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) | |||
1156 | if (IS_ERR(s->shadow_ctx)) | 1156 | if (IS_ERR(s->shadow_ctx)) |
1157 | return PTR_ERR(s->shadow_ctx); | 1157 | return PTR_ERR(s->shadow_ctx); |
1158 | 1158 | ||
1159 | if (HAS_LOGICAL_RING_PREEMPTION(vgpu->gvt->dev_priv)) | ||
1160 | s->shadow_ctx->sched.priority = INT_MAX; | ||
1161 | |||
1162 | bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); | 1159 | bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); |
1163 | 1160 | ||
1164 | s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload", | 1161 | s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload", |