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authorSteve Twiss <stwiss.opensource@diasemi.com>2018-03-28 07:03:09 -0400
committerLee Jones <lee.jones@linaro.org>2018-05-16 04:21:48 -0400
commitb16d23931b7ee5acf17432c3a6b5c6edb204aa35 (patch)
tree112e1d2cb4c8de4305b617ae25eb4655182c59e6
parentc18604660ad02324dfc21de5dfd0c8d15e9070a5 (diff)
mfd: da9062: Use core helper regmap_reg_range macros
Replace multi-line entries in the regmap_range arrays with single line macros: regmap_reg_range(). This will leave the static structure array entries for regmap_range unaltered. It will significantly reduce the line count in the DA9062/61 core file. Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat
-rw-r--r--drivers/mfd/da9062-core.c462
1 files changed, 114 insertions, 348 deletions
diff --git a/drivers/mfd/da9062-core.c b/drivers/mfd/da9062-core.c
index fe1811523e4a..9f6105906c09 100644
--- a/drivers/mfd/da9062-core.c
+++ b/drivers/mfd/da9062-core.c
@@ -365,186 +365,69 @@ static int da9062_get_device_type(struct da9062 *chip)
365} 365}
366 366
367static const struct regmap_range da9061_aa_readable_ranges[] = { 367static const struct regmap_range da9061_aa_readable_ranges[] = {
368 { 368 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
369 .range_min = DA9062AA_PAGE_CON, 369 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
370 .range_max = DA9062AA_STATUS_B, 370 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
371 }, { 371 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
372 .range_min = DA9062AA_STATUS_D, 372 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
373 .range_max = DA9062AA_EVENT_C, 373 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
374 }, { 374 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
375 .range_min = DA9062AA_IRQ_MASK_A, 375 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
376 .range_max = DA9062AA_IRQ_MASK_C, 376 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
377 }, { 377 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
378 .range_min = DA9062AA_CONTROL_A, 378 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
379 .range_max = DA9062AA_GPIO_4, 379 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
380 }, { 380 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
381 .range_min = DA9062AA_GPIO_WKUP_MODE, 381 regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
382 .range_max = DA9062AA_GPIO_OUT3_4, 382 regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
383 }, { 383 regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
384 .range_min = DA9062AA_BUCK1_CONT, 384 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
385 .range_max = DA9062AA_BUCK4_CONT, 385 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
386 }, { 386 regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
387 .range_min = DA9062AA_BUCK3_CONT, 387 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
388 .range_max = DA9062AA_BUCK3_CONT, 388 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
389 }, { 389 regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
390 .range_min = DA9062AA_LDO1_CONT, 390 regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
391 .range_max = DA9062AA_LDO4_CONT, 391 regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
392 }, { 392 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
393 .range_min = DA9062AA_DVC_1, 393 regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
394 .range_max = DA9062AA_DVC_1,
395 }, {
396 .range_min = DA9062AA_SEQ,
397 .range_max = DA9062AA_ID_4_3,
398 }, {
399 .range_min = DA9062AA_ID_12_11,
400 .range_max = DA9062AA_ID_16_15,
401 }, {
402 .range_min = DA9062AA_ID_22_21,
403 .range_max = DA9062AA_ID_32_31,
404 }, {
405 .range_min = DA9062AA_SEQ_A,
406 .range_max = DA9062AA_WAIT,
407 }, {
408 .range_min = DA9062AA_RESET,
409 .range_max = DA9062AA_BUCK_ILIM_C,
410 }, {
411 .range_min = DA9062AA_BUCK1_CFG,
412 .range_max = DA9062AA_BUCK3_CFG,
413 }, {
414 .range_min = DA9062AA_VBUCK1_A,
415 .range_max = DA9062AA_VBUCK4_A,
416 }, {
417 .range_min = DA9062AA_VBUCK3_A,
418 .range_max = DA9062AA_VBUCK3_A,
419 }, {
420 .range_min = DA9062AA_VLDO1_A,
421 .range_max = DA9062AA_VLDO4_A,
422 }, {
423 .range_min = DA9062AA_VBUCK1_B,
424 .range_max = DA9062AA_VBUCK4_B,
425 }, {
426 .range_min = DA9062AA_VBUCK3_B,
427 .range_max = DA9062AA_VBUCK3_B,
428 }, {
429 .range_min = DA9062AA_VLDO1_B,
430 .range_max = DA9062AA_VLDO4_B,
431 }, {
432 .range_min = DA9062AA_INTERFACE,
433 .range_max = DA9062AA_CONFIG_E,
434 }, {
435 .range_min = DA9062AA_CONFIG_G,
436 .range_max = DA9062AA_CONFIG_K,
437 }, {
438 .range_min = DA9062AA_CONFIG_M,
439 .range_max = DA9062AA_CONFIG_M,
440 }, {
441 .range_min = DA9062AA_GP_ID_0,
442 .range_max = DA9062AA_GP_ID_19,
443 }, {
444 .range_min = DA9062AA_DEVICE_ID,
445 .range_max = DA9062AA_CONFIG_ID,
446 },
447}; 394};
448 395
449static const struct regmap_range da9061_aa_writeable_ranges[] = { 396static const struct regmap_range da9061_aa_writeable_ranges[] = {
450 { 397 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
451 .range_min = DA9062AA_PAGE_CON, 398 regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
452 .range_max = DA9062AA_PAGE_CON, 399 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
453 }, { 400 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
454 .range_min = DA9062AA_FAULT_LOG, 401 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
455 .range_max = DA9062AA_EVENT_C, 402 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
456 }, { 403 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
457 .range_min = DA9062AA_IRQ_MASK_A, 404 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
458 .range_max = DA9062AA_IRQ_MASK_C, 405 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
459 }, { 406 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
460 .range_min = DA9062AA_CONTROL_A, 407 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
461 .range_max = DA9062AA_GPIO_4, 408 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
462 }, { 409 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
463 .range_min = DA9062AA_GPIO_WKUP_MODE, 410 regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
464 .range_max = DA9062AA_GPIO_OUT3_4, 411 regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
465 }, { 412 regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
466 .range_min = DA9062AA_BUCK1_CONT, 413 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
467 .range_max = DA9062AA_BUCK4_CONT, 414 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
468 }, { 415 regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
469 .range_min = DA9062AA_BUCK3_CONT, 416 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
470 .range_max = DA9062AA_BUCK3_CONT, 417 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
471 }, { 418 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
472 .range_min = DA9062AA_LDO1_CONT,
473 .range_max = DA9062AA_LDO4_CONT,
474 }, {
475 .range_min = DA9062AA_DVC_1,
476 .range_max = DA9062AA_DVC_1,
477 }, {
478 .range_min = DA9062AA_SEQ,
479 .range_max = DA9062AA_ID_4_3,
480 }, {
481 .range_min = DA9062AA_ID_12_11,
482 .range_max = DA9062AA_ID_16_15,
483 }, {
484 .range_min = DA9062AA_ID_22_21,
485 .range_max = DA9062AA_ID_32_31,
486 }, {
487 .range_min = DA9062AA_SEQ_A,
488 .range_max = DA9062AA_WAIT,
489 }, {
490 .range_min = DA9062AA_RESET,
491 .range_max = DA9062AA_BUCK_ILIM_C,
492 }, {
493 .range_min = DA9062AA_BUCK1_CFG,
494 .range_max = DA9062AA_BUCK3_CFG,
495 }, {
496 .range_min = DA9062AA_VBUCK1_A,
497 .range_max = DA9062AA_VBUCK4_A,
498 }, {
499 .range_min = DA9062AA_VBUCK3_A,
500 .range_max = DA9062AA_VBUCK3_A,
501 }, {
502 .range_min = DA9062AA_VLDO1_A,
503 .range_max = DA9062AA_VLDO4_A,
504 }, {
505 .range_min = DA9062AA_VBUCK1_B,
506 .range_max = DA9062AA_VBUCK4_B,
507 }, {
508 .range_min = DA9062AA_VBUCK3_B,
509 .range_max = DA9062AA_VBUCK3_B,
510 }, {
511 .range_min = DA9062AA_VLDO1_B,
512 .range_max = DA9062AA_VLDO4_B,
513 }, {
514 .range_min = DA9062AA_GP_ID_0,
515 .range_max = DA9062AA_GP_ID_19,
516 },
517}; 419};
518 420
519static const struct regmap_range da9061_aa_volatile_ranges[] = { 421static const struct regmap_range da9061_aa_volatile_ranges[] = {
520 { 422 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
521 .range_min = DA9062AA_PAGE_CON, 423 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
522 .range_max = DA9062AA_STATUS_B, 424 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
523 }, { 425 regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
524 .range_min = DA9062AA_STATUS_D, 426 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
525 .range_max = DA9062AA_EVENT_C, 427 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
526 }, { 428 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
527 .range_min = DA9062AA_CONTROL_A, 429 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
528 .range_max = DA9062AA_CONTROL_B, 430 regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
529 }, {
530 .range_min = DA9062AA_CONTROL_E,
531 .range_max = DA9062AA_CONTROL_F,
532 }, {
533 .range_min = DA9062AA_BUCK1_CONT,
534 .range_max = DA9062AA_BUCK4_CONT,
535 }, {
536 .range_min = DA9062AA_BUCK3_CONT,
537 .range_max = DA9062AA_BUCK3_CONT,
538 }, {
539 .range_min = DA9062AA_LDO1_CONT,
540 .range_max = DA9062AA_LDO4_CONT,
541 }, {
542 .range_min = DA9062AA_DVC_1,
543 .range_max = DA9062AA_DVC_1,
544 }, {
545 .range_min = DA9062AA_SEQ,
546 .range_max = DA9062AA_SEQ,
547 },
548}; 431};
549 432
550static const struct regmap_access_table da9061_aa_readable_table = { 433static const struct regmap_access_table da9061_aa_readable_table = {
@@ -587,186 +470,69 @@ static struct regmap_config da9061_regmap_config = {
587}; 470};
588 471
589static const struct regmap_range da9062_aa_readable_ranges[] = { 472static const struct regmap_range da9062_aa_readable_ranges[] = {
590 { 473 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
591 .range_min = DA9062AA_PAGE_CON, 474 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
592 .range_max = DA9062AA_STATUS_B, 475 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
593 }, { 476 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
594 .range_min = DA9062AA_STATUS_D, 477 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
595 .range_max = DA9062AA_EVENT_C, 478 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
596 }, { 479 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
597 .range_min = DA9062AA_IRQ_MASK_A, 480 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
598 .range_max = DA9062AA_IRQ_MASK_C, 481 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
599 }, { 482 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
600 .range_min = DA9062AA_CONTROL_A, 483 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
601 .range_max = DA9062AA_GPIO_4, 484 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
602 }, { 485 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
603 .range_min = DA9062AA_GPIO_WKUP_MODE, 486 regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
604 .range_max = DA9062AA_BUCK4_CONT, 487 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
605 }, { 488 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
606 .range_min = DA9062AA_BUCK3_CONT, 489 regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
607 .range_max = DA9062AA_BUCK3_CONT, 490 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
608 }, { 491 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
609 .range_min = DA9062AA_LDO1_CONT, 492 regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
610 .range_max = DA9062AA_LDO4_CONT, 493 regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
611 }, { 494 regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
612 .range_min = DA9062AA_DVC_1, 495 regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
613 .range_max = DA9062AA_DVC_1, 496 regmap_reg_range(DA9062AA_TRIM_CLDR, DA9062AA_GP_ID_19),
614 }, { 497 regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
615 .range_min = DA9062AA_COUNT_S,
616 .range_max = DA9062AA_SECOND_D,
617 }, {
618 .range_min = DA9062AA_SEQ,
619 .range_max = DA9062AA_ID_4_3,
620 }, {
621 .range_min = DA9062AA_ID_12_11,
622 .range_max = DA9062AA_ID_16_15,
623 }, {
624 .range_min = DA9062AA_ID_22_21,
625 .range_max = DA9062AA_ID_32_31,
626 }, {
627 .range_min = DA9062AA_SEQ_A,
628 .range_max = DA9062AA_BUCK3_CFG,
629 }, {
630 .range_min = DA9062AA_VBUCK2_A,
631 .range_max = DA9062AA_VBUCK4_A,
632 }, {
633 .range_min = DA9062AA_VBUCK3_A,
634 .range_max = DA9062AA_VBUCK3_A,
635 }, {
636 .range_min = DA9062AA_VLDO1_A,
637 .range_max = DA9062AA_VLDO4_A,
638 }, {
639 .range_min = DA9062AA_VBUCK2_B,
640 .range_max = DA9062AA_VBUCK4_B,
641 }, {
642 .range_min = DA9062AA_VBUCK3_B,
643 .range_max = DA9062AA_VBUCK3_B,
644 }, {
645 .range_min = DA9062AA_VLDO1_B,
646 .range_max = DA9062AA_VLDO4_B,
647 }, {
648 .range_min = DA9062AA_BBAT_CONT,
649 .range_max = DA9062AA_BBAT_CONT,
650 }, {
651 .range_min = DA9062AA_INTERFACE,
652 .range_max = DA9062AA_CONFIG_E,
653 }, {
654 .range_min = DA9062AA_CONFIG_G,
655 .range_max = DA9062AA_CONFIG_K,
656 }, {
657 .range_min = DA9062AA_CONFIG_M,
658 .range_max = DA9062AA_CONFIG_M,
659 }, {
660 .range_min = DA9062AA_TRIM_CLDR,
661 .range_max = DA9062AA_GP_ID_19,
662 }, {
663 .range_min = DA9062AA_DEVICE_ID,
664 .range_max = DA9062AA_CONFIG_ID,
665 },
666}; 498};
667 499
668static const struct regmap_range da9062_aa_writeable_ranges[] = { 500static const struct regmap_range da9062_aa_writeable_ranges[] = {
669 { 501 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
670 .range_min = DA9062AA_PAGE_CON, 502 regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
671 .range_max = DA9062AA_PAGE_CON, 503 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
672 }, { 504 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
673 .range_min = DA9062AA_FAULT_LOG, 505 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
674 .range_max = DA9062AA_EVENT_C, 506 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
675 }, { 507 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
676 .range_min = DA9062AA_IRQ_MASK_A, 508 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
677 .range_max = DA9062AA_IRQ_MASK_C, 509 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_ALARM_Y),
678 }, { 510 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
679 .range_min = DA9062AA_CONTROL_A, 511 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
680 .range_max = DA9062AA_GPIO_4, 512 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
681 }, { 513 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
682 .range_min = DA9062AA_GPIO_WKUP_MODE, 514 regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
683 .range_max = DA9062AA_BUCK4_CONT, 515 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
684 }, { 516 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
685 .range_min = DA9062AA_BUCK3_CONT, 517 regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
686 .range_max = DA9062AA_BUCK3_CONT, 518 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
687 }, { 519 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
688 .range_min = DA9062AA_LDO1_CONT, 520 regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
689 .range_max = DA9062AA_LDO4_CONT, 521 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
690 }, {
691 .range_min = DA9062AA_DVC_1,
692 .range_max = DA9062AA_DVC_1,
693 }, {
694 .range_min = DA9062AA_COUNT_S,
695 .range_max = DA9062AA_ALARM_Y,
696 }, {
697 .range_min = DA9062AA_SEQ,
698 .range_max = DA9062AA_ID_4_3,
699 }, {
700 .range_min = DA9062AA_ID_12_11,
701 .range_max = DA9062AA_ID_16_15,
702 }, {
703 .range_min = DA9062AA_ID_22_21,
704 .range_max = DA9062AA_ID_32_31,
705 }, {
706 .range_min = DA9062AA_SEQ_A,
707 .range_max = DA9062AA_BUCK3_CFG,
708 }, {
709 .range_min = DA9062AA_VBUCK2_A,
710 .range_max = DA9062AA_VBUCK4_A,
711 }, {
712 .range_min = DA9062AA_VBUCK3_A,
713 .range_max = DA9062AA_VBUCK3_A,
714 }, {
715 .range_min = DA9062AA_VLDO1_A,
716 .range_max = DA9062AA_VLDO4_A,
717 }, {
718 .range_min = DA9062AA_VBUCK2_B,
719 .range_max = DA9062AA_VBUCK4_B,
720 }, {
721 .range_min = DA9062AA_VBUCK3_B,
722 .range_max = DA9062AA_VBUCK3_B,
723 }, {
724 .range_min = DA9062AA_VLDO1_B,
725 .range_max = DA9062AA_VLDO4_B,
726 }, {
727 .range_min = DA9062AA_BBAT_CONT,
728 .range_max = DA9062AA_BBAT_CONT,
729 }, {
730 .range_min = DA9062AA_GP_ID_0,
731 .range_max = DA9062AA_GP_ID_19,
732 },
733}; 522};
734 523
735static const struct regmap_range da9062_aa_volatile_ranges[] = { 524static const struct regmap_range da9062_aa_volatile_ranges[] = {
736 { 525 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
737 .range_min = DA9062AA_PAGE_CON, 526 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
738 .range_max = DA9062AA_STATUS_B, 527 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
739 }, { 528 regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
740 .range_min = DA9062AA_STATUS_D, 529 regmap_reg_range(DA9062AA_BUCK2_CONT, DA9062AA_BUCK4_CONT),
741 .range_max = DA9062AA_EVENT_C, 530 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
742 }, { 531 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
743 .range_min = DA9062AA_CONTROL_A, 532 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
744 .range_max = DA9062AA_CONTROL_B, 533 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
745 }, { 534 regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
746 .range_min = DA9062AA_CONTROL_E, 535 regmap_reg_range(DA9062AA_EN_32K, DA9062AA_EN_32K),
747 .range_max = DA9062AA_CONTROL_F,
748 }, {
749 .range_min = DA9062AA_BUCK2_CONT,
750 .range_max = DA9062AA_BUCK4_CONT,
751 }, {
752 .range_min = DA9062AA_BUCK3_CONT,
753 .range_max = DA9062AA_BUCK3_CONT,
754 }, {
755 .range_min = DA9062AA_LDO1_CONT,
756 .range_max = DA9062AA_LDO4_CONT,
757 }, {
758 .range_min = DA9062AA_DVC_1,
759 .range_max = DA9062AA_DVC_1,
760 }, {
761 .range_min = DA9062AA_COUNT_S,
762 .range_max = DA9062AA_SECOND_D,
763 }, {
764 .range_min = DA9062AA_SEQ,
765 .range_max = DA9062AA_SEQ,
766 }, {
767 .range_min = DA9062AA_EN_32K,
768 .range_max = DA9062AA_EN_32K,
769 },
770}; 536};
771 537
772static const struct regmap_access_table da9062_aa_readable_table = { 538static const struct regmap_access_table da9062_aa_readable_table = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 00:36:22 -0400