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authorOlof Johansson <olof@lixom.net>2015-08-18 16:14:39 -0400
committerOlof Johansson <olof@lixom.net>2015-08-18 16:14:39 -0400
commitb12c0820868f8f65289dda974c54eff2b0290fa7 (patch)
tree5fbdc76140bff2895edf705e55f0648c67baa92b
parente7895461593506e2e86404a255208876340d4bca (diff)
parent360325755336893869c419013ec0e33757432cbb (diff)
Merge tag 'imx-dt-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
The i.MX device tree updates for 4.3: - Add audio and eTSEC device support and update dspi node for LS1021A. - Add initial i.MX6UL and imx6ul-14x14-evk board support, and enable a bunch of device support for i.MX6UL, including RTC, power key, USB, QSPI, and dual FEC. - Enable HDMI and LVDS dual display support for a few imx6qdl boards. - Support of imx6sl-warp board rev1.12, the version which will be publicly available for the customers. - A few i.MX7D device additions, watchdog, cortex-a7 coresight components, RTC, power key, power off. - Some Vybrid updates: add device support for I2C, QSPI, eSDHC etc., update ADC node, and define stdout-path property. - A few random updates for i.MX27 and i.MX53 devices. * tag 'imx-dt-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits) ARM: dts: imx6ul: add snvs power key support ARM: dts: imx6ul: add RTC support ARM: dts: imx6ul: enable GPC as extended interrupt controller ARM: dts: imx6sx: correct property name for wakeup source ARM: dts: add property for maximum ADC clock frequencies ARM: dts: imx7d: enable snvs rtc, onoffkey and power off ARM: dts: imx6ul-14x14-evk: add fec1 and fec2 support ARM: dts: imx: add fec1 and fec2 nodes for SOC i.MX6UL ARM: dts: imx27: add support of internal rtc ARM: dts: vf-colibri: define stdout-path property ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR ARM: dts: ls1021a: Add the eTSEC controller nodes ARM: dts: imx6ul: add qspi support ARM: dts: imx6ul: fix low case define in imx6ul-pinfunc.h ARM: dts: imx6ul: add usb host and function support ARM: dts: vfxxx: Add io-channel-cells property for ADC node ARM: dts: ls1021a: Add dts nodes for audio on LS1021A ARM: imx6qdl-sabreauto.dtsi: enable USB support ARM: dts: imx: update snvs to use syscon access register ARM: dts: imx: add imx6ul and imx6ul evk board support ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx6ul-clock.txt13
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt36
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/imx27.dtsi9
-rw-r--r--arch/arm/boot/dts/imx53-qsb-common.dtsi5
-rw-r--r--arch/arm/boot/dts/imx53-qsrb.dts14
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi35
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi35
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi34
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw551x.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw552x.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi39
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi137
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabrelite.dtsi39
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi7
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi52
-rw-r--r--arch/arm/boot/dts/imx6sl-warp.dts32
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi21
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi28
-rw-r--r--arch/arm/boot/dts/imx6ul-14x14-evk.dts343
-rw-r--r--arch/arm/boot/dts/imx6ul-pinfunc.h938
-rw-r--r--arch/arm/boot/dts/imx6ul.dtsi707
-rw-r--r--arch/arm/boot/dts/imx7d.dtsi260
-rw-r--r--arch/arm/boot/dts/ls1021a-qds.dts89
-rw-r--r--arch/arm/boot/dts/ls1021a-twr.dts81
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi106
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi2
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi85
-rw-r--r--drivers/clk/imx/Makefile1
-rw-r--r--drivers/clk/imx/clk-imx6q.c4
-rw-r--r--drivers/clk/imx/clk-imx6ul.c432
-rw-r--r--include/dt-bindings/clock/imx6ul-clock.h240
33 files changed, 3739 insertions, 90 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.txt b/Documentation/devicetree/bindings/clock/imx6ul-clock.txt
new file mode 100644
index 000000000000..571d5039f663
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6ul-clock.txt
@@ -0,0 +1,13 @@
1* Clock bindings for Freescale i.MX6 UltraLite
2
3Required properties:
4- compatible: Should be "fsl,imx6ul-ccm"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7- clocks: list of clock specifiers, must contain an entry for each required
8 entry in clock-names
9- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
10
11The clock consumer should specify the desired clock by having the clock
12ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h
13for the full list of i.MX6 UltraLite clock IDs.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
new file mode 100644
index 000000000000..a81bbf37ed66
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
@@ -0,0 +1,36 @@
1* Freescale i.MX6 UltraLite IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx6ul-iomuxc"
8- fsl,pins: each entry consists of 6 integers and represents the mux and config
9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
10 input_val> are specified using a PIN_FUNC_ID macro, which can be found in
11 imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
12 the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
13 Reference Manual for detailed CONFIG settings.
14
15CONFIG bits definition:
16PAD_CTL_HYS (1 << 16)
17PAD_CTL_PUS_100K_DOWN (0 << 14)
18PAD_CTL_PUS_47K_UP (1 << 14)
19PAD_CTL_PUS_100K_UP (2 << 14)
20PAD_CTL_PUS_22K_UP (3 << 14)
21PAD_CTL_PUE (1 << 13)
22PAD_CTL_PKE (1 << 12)
23PAD_CTL_ODE (1 << 11)
24PAD_CTL_SPEED_LOW (0 << 6)
25PAD_CTL_SPEED_MED (1 << 6)
26PAD_CTL_SPEED_HIGH (3 << 6)
27PAD_CTL_DSE_DISABLE (0 << 3)
28PAD_CTL_DSE_260ohm (1 << 3)
29PAD_CTL_DSE_130ohm (2 << 3)
30PAD_CTL_DSE_87ohm (3 << 3)
31PAD_CTL_DSE_65ohm (4 << 3)
32PAD_CTL_DSE_52ohm (5 << 3)
33PAD_CTL_DSE_43ohm (6 << 3)
34PAD_CTL_DSE_37ohm (7 << 3)
35PAD_CTL_SRE_FAST (1 << 0)
36PAD_CTL_SRE_SLOW (0 << 0)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9960316e4c3..685b4881abe7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -335,6 +335,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
335 imx6sx-sabreauto.dtb \ 335 imx6sx-sabreauto.dtb \
336 imx6sx-sdb-reva.dtb \ 336 imx6sx-sdb-reva.dtb \
337 imx6sx-sdb.dtb 337 imx6sx-sdb.dtb
338dtb-$(CONFIG_SOC_IMX6UL) += \
339 imx6ul-14x14-evk.dtb
338dtb-$(CONFIG_SOC_IMX7D) += \ 340dtb-$(CONFIG_SOC_IMX7D) += \
339 imx7d-sdb.dtb 341 imx7d-sdb.dtb
340dtb-$(CONFIG_SOC_LS1021A) += \ 342dtb-$(CONFIG_SOC_LS1021A) += \
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index bc215e4b75fd..d0e000b21d38 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -144,6 +144,15 @@
144 clock-names = "ipg", "per"; 144 clock-names = "ipg", "per";
145 }; 145 };
146 146
147 rtc: rtc@10007000 {
148 compatible = "fsl,imx21-rtc";
149 reg = <0x10007000 0x1000>;
150 interrupts = <22>;
151 clocks = <&clks IMX27_CLK_CKIL>,
152 <&clks IMX27_CLK_RTC_IPG_GATE>;
153 clock-names = "ref", "ipg";
154 };
155
147 kpp: kpp@10008000 { 156 kpp: kpp@10008000 {
148 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; 157 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
149 reg = <0x10008000 0x1000>; 158 reg = <0x10008000 0x1000>;
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index 181ae5ebf23f..43932bb7b691 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -228,10 +228,11 @@
228 >; 228 >;
229 }; 229 };
230 230
231 /* open drain */
231 pinctrl_i2c1: i2c1grp { 232 pinctrl_i2c1: i2c1grp {
232 fsl,pins = < 233 fsl,pins = <
233 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 234 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
234 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 235 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
235 >; 236 >;
236 }; 237 };
237 238
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
index 82d623d05915..66e47de5e826 100644
--- a/arch/arm/boot/dts/imx53-qsrb.dts
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -20,15 +20,7 @@
20}; 20};
21 21
22&iomuxc { 22&iomuxc {
23 i2c1 { 23 imx53-qsrb {
24 /* open drain */
25 pinctrl_i2c1_qsrb: i2c1grp-1 {
26 fsl,pins = <
27 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
28 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
29 >;
30 };
31
32 pinctrl_pmic: pmicgrp { 24 pinctrl_pmic: pmicgrp {
33 fsl,pins = < 25 fsl,pins = <
34 MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */ 26 MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */
@@ -38,10 +30,6 @@
38}; 30};
39 31
40&i2c1 { 32&i2c1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_i2c1_qsrb>;
43 status = "okay";
44
45 pmic: mc34708@8 { 33 pmic: mc34708@8 {
46 compatible = "fsl,mc34708"; 34 compatible = "fsl,mc34708";
47 pinctrl-names = "default"; 35 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index f2867c4b34a8..7b31fdb79ced 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -248,7 +248,6 @@
248 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 248 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
249 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 249 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
250 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 250 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
251 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
252 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 251 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
253 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 252 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
254 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 253 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index b5756c21ea1d..b8e35513aed2 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -316,10 +316,13 @@
316}; 316};
317 317
318&usdhc3 { 318&usdhc3 {
319 pinctrl-names = "default"; 319 pinctrl-names = "default", "state_100mhz", "state_200mhz";
320 pinctrl-0 = <&pinctrl_usdhc3>; 320 pinctrl-0 = <&pinctrl_usdhc3>;
321 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
322 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
321 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 323 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
322 vmmc-supply = <&reg_3p3v>; 324 vmmc-supply = <&reg_3p3v>;
325 no-1-8-v; /* firmware will remove if board revision supports */
323 status = "okay"; 326 status = "okay";
324}; 327};
325 328
@@ -380,7 +383,6 @@
380 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 383 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
381 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 384 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
382 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 385 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
383 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
384 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 386 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
385 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 387 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
386 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 388 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
@@ -469,7 +471,34 @@
469 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 471 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
470 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 472 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
471 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 473 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
472 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ 474 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
475 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
476 >;
477 };
478
479 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
480 fsl,pins = <
481 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
482 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
483 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
484 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
485 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
486 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
487 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
488 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
489 >;
490 };
491
492 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
493 fsl,pins = <
494 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
495 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
496 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
497 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
498 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
499 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
500 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
501 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
473 >; 502 >;
474 }; 503 };
475 }; 504 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 86f03c1b147c..765c3a758ae0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -322,10 +322,13 @@
322}; 322};
323 323
324&usdhc3 { 324&usdhc3 {
325 pinctrl-names = "default"; 325 pinctrl-names = "default", "state_100mhz", "state_200mhz";
326 pinctrl-0 = <&pinctrl_usdhc3>; 326 pinctrl-0 = <&pinctrl_usdhc3>;
327 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
328 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
327 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 329 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
328 vmmc-supply = <&reg_3p3v>; 330 vmmc-supply = <&reg_3p3v>;
331 no-1-8-v; /* firmware will remove if board revision supports */
329 status = "okay"; 332 status = "okay";
330}; 333};
331 334
@@ -385,7 +388,6 @@
385 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 388 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
386 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 389 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
387 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 390 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
388 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
389 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 391 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
390 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 392 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
391 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 393 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
@@ -476,7 +478,34 @@
476 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 478 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
477 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 479 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
478 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 480 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
479 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ 481 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
482 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
483 >;
484 };
485
486 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
487 fsl,pins = <
488 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
489 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
490 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
491 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
492 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
493 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
494 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
495 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
496 >;
497 };
498
499 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
500 fsl,pins = <
501 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
502 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
503 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
504 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
505 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
506 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
507 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
508 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
480 >; 509 >;
481 }; 510 };
482 }; 511 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 4a8d97f47759..1100aab4be54 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -415,10 +415,13 @@
415}; 415};
416 416
417&usdhc3 { 417&usdhc3 {
418 pinctrl-names = "default"; 418 pinctrl-names = "default", "state_100mhz", "state_200mhz";
419 pinctrl-0 = <&pinctrl_usdhc3>; 419 pinctrl-0 = <&pinctrl_usdhc3>;
420 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
421 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
420 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 422 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
421 vmmc-supply = <&reg_3p3v>; 423 vmmc-supply = <&reg_3p3v>;
424 no-1-8-v; /* firmware will remove if board revision supports */
422 status = "okay"; 425 status = "okay";
423}; 426};
424 427
@@ -478,7 +481,6 @@
478 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 481 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
479 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 482 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
480 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 483 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
481 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
482 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 484 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
483 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 485 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
484 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 486 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
@@ -568,6 +570,34 @@
568 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 570 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
569 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 571 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
570 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 572 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
573 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
574 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
575 >;
576 };
577
578 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
579 fsl,pins = <
580 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
581 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
582 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
583 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
584 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
585 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
586 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
587 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
588 >;
589 };
590
591 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
592 fsl,pins = <
593 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
594 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
595 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
596 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
597 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
598 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
599 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
600 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
571 >; 601 >;
572 }; 602 };
573 }; 603 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index d1866a0a2f13..741f3d529e3e 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -250,7 +250,6 @@
250 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 250 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
251 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 251 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
252 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 252 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
253 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
254 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 253 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
255 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 254 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
256 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 255 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index 5c6587f6c420..d1e5048b00b5 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -202,7 +202,6 @@
202 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 202 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
203 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 203 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
204 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 204 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
205 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
206 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 205 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
207 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 206 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
208 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 207 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 3af16dfe417b..5bb9aef415f5 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -54,6 +54,17 @@
54 gpio = <&gpio3 22 0>; 54 gpio = <&gpio3 22 0>;
55 enable-active-high; 55 enable-active-high;
56 }; 56 };
57
58 reg_can_xcvr: regulator@3 {
59 compatible = "regulator-fixed";
60 reg = <3>;
61 regulator-name = "CAN XCVR";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_can_xcvr>;
66 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
67 };
57 }; 68 };
58 69
59 gpio-keys { 70 gpio-keys {
@@ -149,6 +160,20 @@
149 status = "okay"; 160 status = "okay";
150}; 161};
151 162
163&can1 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_can1>;
166 xceiver-supply = <&reg_can_xcvr>;
167 status = "okay";
168};
169
170&clks {
171 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
172 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
173 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
174 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
175};
176
152&ecspi1 { 177&ecspi1 {
153 fsl,spi-num-chipselects = <1>; 178 fsl,spi-num-chipselects = <1>;
154 cs-gpios = <&gpio3 19 0>; 179 cs-gpios = <&gpio3 19 0>;
@@ -245,6 +270,20 @@
245 >; 270 >;
246 }; 271 };
247 272
273 pinctrl_can1: can1grp {
274 fsl,pins = <
275 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
276 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
277 >;
278 };
279
280 pinctrl_can_xcvr: can-xcvrgrp {
281 fsl,pins = <
282 /* Flexcan XCVR enable */
283 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
284 >;
285 };
286
248 pinctrl_ecspi1: ecspi1grp { 287 pinctrl_ecspi1: ecspi1grp {
249 fsl,pins = < 288 fsl,pins = <
250 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 289 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 3b24b12651b2..a6a310bef4b9 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -28,6 +28,71 @@
28 }; 28 };
29 }; 29 };
30 30
31 clocks {
32 codec_osc: anaclk2 {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <24576000>;
36 };
37 };
38
39 regulators {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 reg_audio: regulator@0 {
45 compatible = "regulator-fixed";
46 reg = <0>;
47 regulator-name = "cs42888_supply";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 regulator-always-on;
51 };
52
53 reg_usb_h1_vbus: regulator@1 {
54 compatible = "regulator-fixed";
55 reg = <1>;
56 regulator-name = "usb_h1_vbus";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
60 enable-active-high;
61 };
62
63 reg_usb_otg_vbus: regulator@2 {
64 compatible = "regulator-fixed";
65 reg = <2>;
66 regulator-name = "usb_otg_vbus";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
69 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
70 enable-active-high;
71 };
72 };
73
74 sound-cs42888 {
75 compatible = "fsl,imx6-sabreauto-cs42888",
76 "fsl,imx-audio-cs42888";
77 model = "imx-cs42888";
78 audio-cpu = <&esai>;
79 audio-asrc = <&asrc>;
80 audio-codec = <&codec>;
81 audio-routing =
82 "Line Out Jack", "AOUT1L",
83 "Line Out Jack", "AOUT1R",
84 "Line Out Jack", "AOUT2L",
85 "Line Out Jack", "AOUT2R",
86 "Line Out Jack", "AOUT3L",
87 "Line Out Jack", "AOUT3R",
88 "Line Out Jack", "AOUT4L",
89 "Line Out Jack", "AOUT4R",
90 "AIN1L", "Line In Jack",
91 "AIN1R", "Line In Jack",
92 "AIN2L", "Line In Jack",
93 "AIN2R", "Line In Jack";
94 };
95
31 sound-spdif { 96 sound-spdif {
32 compatible = "fsl,imx-audio-spdif", 97 compatible = "fsl,imx-audio-spdif",
33 "fsl,imx-sabreauto-spdif"; 98 "fsl,imx-sabreauto-spdif";
@@ -45,6 +110,19 @@
45 }; 110 };
46}; 111};
47 112
113&clks {
114 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
115 <&clks IMX6QDL_PLL4_BYPASS>,
116 <&clks IMX6QDL_CLK_PLL4_POST_DIV>,
117 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
118 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
119 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
120 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
121 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
122 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
123 assigned-clock-rates = <0>, <0>, <24576000>;
124};
125
48&ecspi1 { 126&ecspi1 {
49 fsl,spi-num-chipselects = <1>; 127 fsl,spi-num-chipselects = <1>;
50 cs-gpios = <&gpio3 19 0>; 128 cs-gpios = <&gpio3 19 0>;
@@ -61,6 +139,16 @@
61 }; 139 };
62}; 140};
63 141
142&esai {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_esai>;
145 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
146 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
148 assigned-clock-rates = <0>, <24576000>;
149 status = "okay";
150};
151
64&fec { 152&fec {
65 pinctrl-names = "default"; 153 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_enet>; 154 pinctrl-0 = <&pinctrl_enet>;
@@ -76,6 +164,10 @@
76 status = "okay"; 164 status = "okay";
77}; 165};
78 166
167&hdmi {
168 status = "okay";
169};
170
79&i2c2 { 171&i2c2 {
80 clock-frequency = <100000>; 172 clock-frequency = <100000>;
81 pinctrl-names = "default"; 173 pinctrl-names = "default";
@@ -180,6 +272,18 @@
180 }; 272 };
181 }; 273 };
182 }; 274 };
275
276 codec: cs42888@48 {
277 compatible = "cirrus,cs42888";
278 reg = <0x48>;
279 clocks = <&codec_osc>;
280 clock-names = "mclk";
281 VA-supply = <&reg_audio>;
282 VD-supply = <&reg_audio>;
283 VLS-supply = <&reg_audio>;
284 VLC-supply = <&reg_audio>;
285 };
286
183}; 287};
184 288
185&i2c3 { 289&i2c3 {
@@ -257,6 +361,21 @@
257 >; 361 >;
258 }; 362 };
259 363
364 pinctrl_esai: esaigrp {
365 fsl,pins = <
366 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
367 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
368 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
369 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
370 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
371 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
372 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
373 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
374 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
375 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
376 >;
377 };
378
260 pinctrl_gpio_leds: gpioledsgrp { 379 pinctrl_gpio_leds: gpioledsgrp {
261 fsl,pins = < 380 fsl,pins = <
262 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 381 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
@@ -318,6 +437,12 @@
318 >; 437 >;
319 }; 438 };
320 439
440 pinctrl_usbotg: usbotggrp {
441 fsl,pins = <
442 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
443 >;
444 };
445
321 pinctrl_usdhc3: usdhc3grp { 446 pinctrl_usdhc3: usdhc3grp {
322 fsl,pins = < 447 fsl,pins = <
323 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 448 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@@ -462,6 +587,18 @@
462 status = "okay"; 587 status = "okay";
463}; 588};
464 589
590&usbh1 {
591 vbus-supply = <&reg_usb_h1_vbus>;
592 status = "okay";
593};
594
595&usbotg {
596 vbus-supply = <&reg_usb_otg_vbus>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&pinctrl_usbotg>;
599 status = "okay";
600};
601
465&usdhc3 { 602&usdhc3 {
466 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 603 pinctrl-names = "default", "state_100mhz", "state_200mhz";
467 pinctrl-0 = <&pinctrl_usdhc3>; 604 pinctrl-0 = <&pinctrl_usdhc3>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index e00c44f6a0df..2a39806b5aa2 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -53,6 +53,17 @@
53 gpio = <&gpio3 22 0>; 53 gpio = <&gpio3 22 0>;
54 enable-active-high; 54 enable-active-high;
55 }; 55 };
56
57 reg_can_xcvr: regulator@3 {
58 compatible = "regulator-fixed";
59 reg = <3>;
60 regulator-name = "CAN XCVR";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_can_xcvr>;
65 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
66 };
56 }; 67 };
57 68
58 gpio-keys { 69 gpio-keys {
@@ -148,6 +159,20 @@
148 status = "okay"; 159 status = "okay";
149}; 160};
150 161
162&can1 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_can1>;
165 xceiver-supply = <&reg_can_xcvr>;
166 status = "okay";
167};
168
169&clks {
170 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
171 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
172 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
173 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
174};
175
151&ecspi1 { 176&ecspi1 {
152 fsl,spi-num-chipselects = <1>; 177 fsl,spi-num-chipselects = <1>;
153 cs-gpios = <&gpio3 19 0>; 178 cs-gpios = <&gpio3 19 0>;
@@ -239,6 +264,20 @@
239 >; 264 >;
240 }; 265 };
241 266
267 pinctrl_can1: can1grp {
268 fsl,pins = <
269 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
270 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
271 >;
272 };
273
274 pinctrl_can_xcvr: can-xcvrgrp {
275 fsl,pins = <
276 /* Flexcan XCVR enable */
277 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
278 >;
279 };
280
242 pinctrl_ecspi1: ecspi1grp { 281 pinctrl_ecspi1: ecspi1grp {
243 fsl,pins = < 282 fsl,pins = <
244 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 283 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index a626e6dd8022..cca847e448a0 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -141,6 +141,13 @@
141 status = "okay"; 141 status = "okay";
142}; 142};
143 143
144&clks {
145 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
146 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
148 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
149};
150
144&ecspi1 { 151&ecspi1 {
145 fsl,spi-num-chipselects = <1>; 152 fsl,spi-num-chipselects = <1>;
146 cs-gpios = <&gpio4 9 0>; 153 cs-gpios = <&gpio4 9 0>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e6d13592080d..03858d7d4064 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -300,8 +300,19 @@
300 }; 300 };
301 301
302 esai: esai@02024000 { 302 esai: esai@02024000 {
303 #sound-dai-cells = <0>;
304 compatible = "fsl,imx35-esai";
303 reg = <0x02024000 0x4000>; 305 reg = <0x02024000 0x4000>;
304 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 306 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
308 <&clks IMX6QDL_CLK_ESAI_MEM>,
309 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
310 <&clks IMX6QDL_CLK_ESAI_IPG>,
311 <&clks IMX6QDL_CLK_SPBA>;
312 clock-names = "core", "mem", "extal", "fsys", "dma";
313 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
314 dma-names = "rx", "tx";
315 status = "disabled";
305 }; 316 };
306 317
307 ssi1: ssi@02028000 { 318 ssi1: ssi@02028000 {
@@ -353,8 +364,28 @@
353 }; 364 };
354 365
355 asrc: asrc@02034000 { 366 asrc: asrc@02034000 {
367 compatible = "fsl,imx53-asrc";
356 reg = <0x02034000 0x4000>; 368 reg = <0x02034000 0x4000>;
357 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 369 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
371 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
372 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
373 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
374 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
375 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
376 <&clks IMX6QDL_CLK_SPBA>;
377 clock-names = "mem", "ipg", "asrck_0",
378 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
379 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
380 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
381 "asrck_d", "asrck_e", "asrck_f", "dma";
382 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
383 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
384 dma-names = "rxa", "rxb", "rxc",
385 "txa", "txb", "txc";
386 fsl,asrc-rate = <48000>;
387 fsl,asrc-width = <16>;
388 status = "okay";
358 }; 389 };
359 390
360 spba@0203c000 { 391 spba@0203c000 {
@@ -687,22 +718,23 @@
687 fsl,anatop = <&anatop>; 718 fsl,anatop = <&anatop>;
688 }; 719 };
689 720
690 snvs@020cc000 { 721 snvs: snvs@020cc000 {
691 compatible = "fsl,sec-v4.0-mon", "simple-bus"; 722 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
692 #address-cells = <1>; 723 reg = <0x020cc000 0x4000>;
693 #size-cells = <1>;
694 ranges = <0 0x020cc000 0x4000>;
695 724
696 snvs_rtc: snvs-rtc-lp@34 { 725 snvs_rtc: snvs-rtc-lp {
697 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 726 compatible = "fsl,sec-v4.0-mon-rtc-lp";
698 reg = <0x34 0x58>; 727 regmap = <&snvs>;
728 offset = <0x34>;
699 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 729 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
700 <0 20 IRQ_TYPE_LEVEL_HIGH>; 730 <0 20 IRQ_TYPE_LEVEL_HIGH>;
701 }; 731 };
702 732
703 snvs_poweroff: snvs-poweroff@38 { 733 snvs_poweroff: snvs-poweroff {
704 compatible = "fsl,sec-v4.0-poweroff"; 734 compatible = "syscon-poweroff";
705 reg = <0x38 0x4>; 735 regmap = <&snvs>;
736 offset = <0x38>;
737 mask = <0x60>;
706 status = "disabled"; 738 status = "disabled";
707 }; 739 };
708 }; 740 };
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
index 0da906bd8df2..10c69963100f 100644
--- a/arch/arm/boot/dts/imx6sl-warp.dts
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -61,7 +61,9 @@
61 usdhc3_pwrseq: usdhc3_pwrseq { 61 usdhc3_pwrseq: usdhc3_pwrseq {
62 compatible = "mmc-pwrseq-simple"; 62 compatible = "mmc-pwrseq-simple";
63 reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ 63 reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
64 <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */
64 <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ 65 <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
66 <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */
65 <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ 67 <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
66 <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ 68 <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
67 }; 69 };
@@ -73,16 +75,16 @@
73 status = "okay"; 75 status = "okay";
74}; 76};
75 77
76&uart2 { 78&uart3 {
77 pinctrl-names = "default"; 79 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_uart2>; 80 pinctrl-0 = <&pinctrl_uart3>;
79 fsl,uart-has-rtscts;
80 status = "okay"; 81 status = "okay";
81}; 82};
82 83
83&uart3 { 84&uart5 {
84 pinctrl-names = "default"; 85 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_uart3>; 86 pinctrl-0 = <&pinctrl_uart5>;
87 fsl,uart-has-rtscts;
86 status = "okay"; 88 status = "okay";
87}; 89};
88 90
@@ -130,14 +132,6 @@
130 >; 132 >;
131 }; 133 };
132 134
133 pinctrl_uart2: uart2grp {
134 fsl,pins = <
135 MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
136 MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
137 MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
138 MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
139 >;
140 };
141 135
142 pinctrl_uart3: uart3grp { 136 pinctrl_uart3: uart3grp {
143 fsl,pins = < 137 fsl,pins = <
@@ -146,6 +140,15 @@
146 >; 140 >;
147 }; 141 };
148 142
143 pinctrl_uart5: uart5grp {
144 fsl,pins = <
145 MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1
146 MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1
147 MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1
148 MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1
149 >;
150 };
151
149 pinctrl_usdhc2: usdhc2grp { 152 pinctrl_usdhc2: usdhc2grp {
150 fsl,pins = < 153 fsl,pins = <
151 MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 154 MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
@@ -158,6 +161,7 @@
158 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 161 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059
159 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 162 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059
160 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 163 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059
164 MX6SL_PAD_SD2_RST__SD2_RESET 0x417059
161 >; 165 >;
162 }; 166 };
163 167
@@ -173,6 +177,7 @@
173 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 177 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9
174 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 178 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9
175 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 179 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9
180 MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9
176 >; 181 >;
177 }; 182 };
178 183
@@ -188,6 +193,7 @@
188 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 193 MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9
189 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 194 MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9
190 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 195 MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9
196 MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9
191 >; 197 >;
192 }; 198 };
193 199
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index a78e715e3982..320a27f8889e 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -563,22 +563,23 @@
563 fsl,anatop = <&anatop>; 563 fsl,anatop = <&anatop>;
564 }; 564 };
565 565
566 snvs@020cc000 { 566 snvs: snvs@020cc000 {
567 compatible = "fsl,sec-v4.0-mon", "simple-bus"; 567 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
568 #address-cells = <1>; 568 reg = <0x020cc000 0x4000>;
569 #size-cells = <1>;
570 ranges = <0 0x020cc000 0x4000>;
571 569
572 snvs_rtc: snvs-rtc-lp@34 { 570 snvs_rtc: snvs-rtc-lp {
573 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 571 compatible = "fsl,sec-v4.0-mon-rtc-lp";
574 reg = <0x34 0x58>; 572 regmap = <&snvs>;
573 offset = <0x34>;
575 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
576 <0 20 IRQ_TYPE_LEVEL_HIGH>; 575 <0 20 IRQ_TYPE_LEVEL_HIGH>;
577 }; 576 };
578 577
579 snvs_poweroff: snvs-poweroff@38 { 578 snvs_poweroff: snvs-poweroff {
580 compatible = "fsl,sec-v4.0-poweroff"; 579 compatible = "syscon-poweroff";
581 reg = <0x38 0x4>; 580 regmap = <&snvs>;
581 offset = <0x38>;
582 mask = <0x60>;
582 status = "disabled"; 583 status = "disabled";
583 }; 584 };
584 }; 585 };
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 708175d59b9c..dc7eaaefe01a 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -8,6 +8,7 @@
8 8
9#include <dt-bindings/clock/imx6sx-clock.h> 9#include <dt-bindings/clock/imx6sx-clock.h>
10#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "imx6sx-pinfunc.h" 13#include "imx6sx-pinfunc.h"
13#include "skeleton.dtsi" 14#include "skeleton.dtsi"
@@ -662,22 +663,31 @@
662 }; 663 };
663 664
664 snvs: snvs@020cc000 { 665 snvs: snvs@020cc000 {
665 compatible = "fsl,sec-v4.0-mon", "simple-bus"; 666 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
666 #address-cells = <1>; 667 reg = <0x020cc000 0x4000>;
667 #size-cells = <1>;
668 ranges = <0 0x020cc000 0x4000>;
669 668
670 snvs_rtc: snvs-rtc-lp@34 { 669 snvs_rtc: snvs-rtc-lp {
671 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 670 compatible = "fsl,sec-v4.0-mon-rtc-lp";
672 reg = <0x34 0x58>; 671 regmap = <&snvs>;
672 offset = <0x34>;
673 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 673 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
674 }; 674 };
675 675
676 snvs_poweroff: snvs-poweroff@38 { 676 snvs_poweroff: snvs-poweroff {
677 compatible = "fsl,sec-v4.0-poweroff"; 677 compatible = "syscon-poweroff";
678 reg = <0x38 0x4>; 678 regmap = <&snvs>;
679 offset = <0x38>;
680 mask = <0x60>;
679 status = "disabled"; 681 status = "disabled";
680 }; 682 };
683
684 snvs_pwrkey: snvs-powerkey {
685 compatible = "fsl,sec-v4.0-pwrkey";
686 regmap = <&snvs>;
687 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
688 linux,keycode = <KEY_POWER>;
689 wakeup-source;
690 };
681 }; 691 };
682 692
683 epit1: epit@020d0000 { 693 epit1: epit@020d0000 {
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
new file mode 100644
index 000000000000..25746b122ea6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -0,0 +1,343 @@
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/input/input.h>
12#include "imx6ul.dtsi"
13
14/ {
15 model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
16 compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
17
18 chosen {
19 stdout-path = &uart1;
20 };
21
22 memory {
23 reg = <0x80000000 0x20000000>;
24 };
25
26 regulators {
27 compatible = "simple-bus";
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 reg_sd1_vmmc: sd1_regulator {
32 compatible = "regulator-fixed";
33 regulator-name = "VSD_3V3";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
37 enable-active-high;
38 };
39 };
40};
41
42&cpu0 {
43 arm-supply = <&reg_arm>;
44 soc-supply = <&reg_soc>;
45};
46
47&fec1 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_enet1>;
50 phy-mode = "rmii";
51 phy-handle = <&ethphy0>;
52 status = "okay";
53};
54
55&fec2 {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_enet2>;
58 phy-mode = "rmii";
59 phy-handle = <&ethphy1>;
60 status = "okay";
61
62 mdio {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 ethphy0: ethernet-phy@2 {
67 reg = <2>;
68 };
69
70 ethphy1: ethernet-phy@1 {
71 reg = <1>;
72 };
73 };
74};
75
76&qspi {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_qspi>;
79 status = "okay";
80
81 flash0: n25q256a@0 {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "micron,n25q256a";
85 spi-max-frequency = <29000000>;
86 reg = <0>;
87 };
88};
89
90&uart1 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_uart1>;
93 status = "okay";
94};
95
96&uart2 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_uart2>;
99 fsl,uart-has-rtscts;
100 status = "okay";
101};
102
103&usbotg1 {
104 dr_mode = "peripheral";
105 status = "okay";
106};
107
108&usbotg2 {
109 dr_mode = "host";
110 disable-over-current;
111 status = "okay";
112};
113
114&usdhc1 {
115 pinctrl-names = "default", "state_100mhz", "state_200mhz";
116 pinctrl-0 = <&pinctrl_usdhc1>;
117 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
118 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
119 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
120 keep-power-in-suspend;
121 enable-sdio-wakeup;
122 vmmc-supply = <&reg_sd1_vmmc>;
123 status = "okay";
124};
125
126&usdhc2 {
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_usdhc2>;
129 no-1-8-v;
130 keep-power-in-suspend;
131 enable-sdio-wakeup;
132 status = "okay";
133};
134
135&iomuxc {
136 pinctrl-names = "default";
137
138 pinctrl_csi1: csi1grp {
139 fsl,pins = <
140 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
141 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
142 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
143 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
144 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
145 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
146 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
147 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
148 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
149 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
150 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
151 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
152 >;
153 };
154
155 pinctrl_enet1: enet1grp {
156 fsl,pins = <
157 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
158 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
159 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
160 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
161 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
162 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
163 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
164 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
165 >;
166 };
167
168 pinctrl_enet2: enet2grp {
169 fsl,pins = <
170 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
171 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
172 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
173 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
174 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
175 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
176 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
177 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
178 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
179 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
180 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
181 >;
182 };
183
184 pinctrl_flexcan1: flexcan1grp{
185 fsl,pins = <
186 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
187 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
188 >;
189 };
190
191 pinctrl_flexcan2: flexcan2grp{
192 fsl,pins = <
193 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
194 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
195 >;
196 };
197
198 pinctrl_i2c1: i2c1grp {
199 fsl,pins = <
200 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
201 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
202 >;
203 };
204
205 pinctrl_i2c2: i2c2grp {
206 fsl,pins = <
207 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
208 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
209 >;
210 };
211
212 pinctrl_lcdif_dat: lcdifdatgrp {
213 fsl,pins = <
214 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
215 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
216 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
217 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
218 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
219 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
220 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
221 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
222 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
223 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
224 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
225 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
226 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
227 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
228 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
229 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
230 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
231 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
232 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
233 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
234 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
235 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
236 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
237 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
238 >;
239 };
240
241 pinctrl_lcdif_ctrl: lcdifctrlgrp {
242 fsl,pins = <
243 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
244 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
245 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
246 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
247 /* used for lcd reset */
248 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
249 >;
250 };
251
252 pinctrl_qspi: qspigrp {
253 fsl,pins = <
254 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
255 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
256 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
257 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
258 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
259 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
260 >;
261 };
262
263 pinctrl_pwm1: pwm1grp {
264 fsl,pins = <
265 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
266 >;
267 };
268
269 pinctrl_sim2: sim2grp {
270 fsl,pins = <
271 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
272 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
273 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
274 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
275 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
276 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
277 >;
278 };
279
280 pinctrl_uart1: uart1grp {
281 fsl,pins = <
282 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
283 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
284 >;
285 };
286
287 pinctrl_uart2: uart2grp {
288 fsl,pins = <
289 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
290 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
291 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
292 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
293 >;
294 };
295
296 pinctrl_usdhc1: usdhc1grp {
297 fsl,pins = <
298 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
299 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
300 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
301 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
302 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
303 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
304 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
305 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
306 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
307 >;
308 };
309
310 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
311 fsl,pins = <
312 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
313 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
314 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
315 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
316 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
317 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
318
319 >;
320 };
321
322 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
323 fsl,pins = <
324 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
325 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
326 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
327 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
328 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
329 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
330 >;
331 };
332
333 pinctrl_usdhc2: usdhc2grp {
334 fsl,pins = <
335 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
336 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
337 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
338 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
339 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
340 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
341 >;
342 };
343};
diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h
new file mode 100644
index 000000000000..20c7da1affce
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-pinfunc.h
@@ -0,0 +1,938 @@
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX6UL_PINFUNC_H
11#define __DTS_IMX6UL_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
18#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
19
20#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
21#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
22#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
23#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
24#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
25#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
26#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
27#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
28#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0
29#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0
30
31#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0
32#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0
33#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0
34#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0
35#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0
36#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0
37#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0
38#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0
39#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0
40#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0
41#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0
42#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0
43#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0
44#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0
45#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0
46#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0
47#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0
48#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0
49#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0
50#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0
51#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0
52#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0
53#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0
54#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0
55#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0
56#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0
57#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0
58#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0
59#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0
60#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0
61#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0
62#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0
63#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x0000 2 0
64#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0
65#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0
66#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0
67#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0
68#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0
69#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0
70#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0
71#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0
72#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0
73#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1
74#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0
75#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0
76#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0
77#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0
78#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0
79#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0
80#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0
81#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0
82#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1
83#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0
84#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0
85#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0
86#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0
87#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0
88#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0
89#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0
90#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0
91#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0
92#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0
93#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0
94#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0
95#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0
96#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0
97#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0
98#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0
99#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0
100#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0
101#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1
102#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0
103#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0
104#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0
105#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0
106#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0
107#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0
108#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0
109#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1
110#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1
111#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0
112#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0
113#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0
114#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0
115#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0
116#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0
117#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2
118#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1
119#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0
120#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0
121#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0
122#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0
123#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0
124#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0
125#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3
126#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0
127#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0
128#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0
129#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0
130#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0
131#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0
132#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0
133#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0
134#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0
135#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0
136#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0
137#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0
138#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0
139#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0
140#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0
141#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1
142#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0
143#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0
144#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1
145#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0
146#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0
147#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0
148#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0
149#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1
150#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0
151#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0
152#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1
153#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1
154#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0
155#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0
156#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0
157#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0
158#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1
159#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0
160#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0
161#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0
162#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0
163#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2
164#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0
165#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2
166#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0
167#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0
168#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x0000 3 0
169#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0
170#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0
171#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0
172#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3
173#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0
174#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0
175#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0
176#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x0000 3 0
177#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0
178#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0
179#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0000 8 0
180#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0
181#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2
182#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0
183#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1
184#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x0000 3 0
185#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0
186#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0
187#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x0000 8 0
188#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3
189#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0
190#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0
191#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1
192#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x0000 3 0
193#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0
194#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0
195#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0000 8 0
196#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0
197#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0
198#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0
199#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0
200#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x0000 3 0
201#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1
202#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0
203#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0
204#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1
205#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0
206#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0
207#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0
208#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x0000 3 0
209#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0
210#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0
211#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0
212#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0000 8 0
213#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0
214#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0
215#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0
216#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0
217#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x0000 3 0
218#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0
219#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0
220#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0
221#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x0000 8 0
222#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1
223#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0
224#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0
225#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0
226#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x0000 3 0
227#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0
228#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0
229#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0
230#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0000 8 0
231#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0
232#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0
233#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0
234#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0
235#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0
236#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0
237#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2
238#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0
239#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0
240#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x0000 8 0
241#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1
242#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0
243#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0
244#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0
245#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0
246#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3
247#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0
248#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0
249#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0
250#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0
251#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0
252#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0
253#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0
254#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0
255#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0
256#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0
257#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0
258#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1
259#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0
260#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0
261#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0
262#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0
263#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0
264#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0
265#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0
266#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0
267#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0
268#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0
269#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1
270#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0
271#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0
272#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0
273#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0000 8 0
274#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1
275#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0
276#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0
277#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2
278#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0
279#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0
280#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0
281#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0
282#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0
283#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x0000 8 0
284#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0
285#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4
286#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0
287#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2
288#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0
289#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0
290#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5
291#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0
292#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0
293#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2
294#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0
295#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0
296#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0
297#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0000 8 0
298#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0
299#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0
300#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0
301#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0
302#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0
303#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0
304#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0
305#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0
306#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0
307#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0
308#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0
309#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1
310#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0
311#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0
312#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1
313#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0
314#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0
315#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0
316#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0
317#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3
318#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0
319#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0
320#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0
321#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0
322#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0
323#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0
324#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0
325#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0
326#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4
327#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0
328#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1
329#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0
330#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0
331#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0
332#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0
333#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0
334#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2
335#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0
336#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0
337#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1
338#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0
339#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0
340#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0
341#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0
342#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3
343#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0
344#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0
345#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0
346#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0
347#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0
348#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0
349#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0
350#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0
351#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0
352#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0
353#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0
354#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0
355#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2
356#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0
357#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0
358#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0000 8 0
359#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0
360#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1
361#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0
362#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0
363#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0
364#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0
365#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0
366#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0
367#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0000 8 0
368#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0
369#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0
370#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1
371#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0
372#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1
373#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1
374#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0
375#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0
376#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0
377#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0
378#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2
379#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0
380#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0
381#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1
382#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0
383#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0
384#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0
385#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0000 8 0
386#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0
387#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0
388#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0
389#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0
390#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1
391#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0
392#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0
393#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0
394#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0
395#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0
396#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1
397#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0
398#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0
399#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1
400#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0
401#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0
402#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0
403#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0
404#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0
405#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0
406#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0
407#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0
408#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0
409#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0
410#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0
411#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0
412#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0
413#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1
414#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0
415#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0
416#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0
417#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0
418#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0
419#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0
420#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0000 8 0
421#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0
422#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0
423#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0
424#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0
425#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0
426#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2
427#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0
428#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0
429#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x0000 8 0
430#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0
431#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1
432#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0
433#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0
434#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0
435#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0
436#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0
437#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0
438#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0
439#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0
440#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0
441#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0
442#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2
443#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0
444#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0
445#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0
446#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0
447#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0
448#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0
449#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3
450#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0
451#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0
452#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0
453#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0
454#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0
455#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0
456#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0
457#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0
458#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2
459#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0
460#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0
461#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0
462#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0
463#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0
464#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1
465#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3
466#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0
467#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0
468#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0
469#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0
470#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0
471#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0
472#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0
473#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0
474#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0
475#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0
476#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0
477#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0
478#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0
479#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0
480#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0
481#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2
482#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0
483#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0
484#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0
485#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0
486#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0
487#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0
488#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2
489#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0
490#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0
491#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x0000 8 0
492#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0
493#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0
494#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0
495#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2
496#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0
497#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0
498#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x0000 8 0
499#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0
500#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0
501#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0
502#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2
503#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0
504#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0
505#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0
506#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0
507#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0
508#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2
509#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0
510#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0
511#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0
512#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0
513#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0
514#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0
515#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3
516#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0
517#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0
518#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0
519#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0
520#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0
521#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0
522#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0
523#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0
524#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2
525#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0
526#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0
527#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0
528#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0
529#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0
530#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0
531#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3
532#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0
533#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0
534#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0
535#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0
536#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0
537#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0
538#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0
539#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2
540#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0
541#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0
542#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0
543#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0
544#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0
545#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0
546#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0
547#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0
548#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0
549#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0
550#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0
551#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0000 8 0
552#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0
553#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0
554#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0
555#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0
556#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0
557#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0
558#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0
559#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0
560#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0
561#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0
562#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0
563#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0
564#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0
565#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0000 8 0
566#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0
567#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1
568#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0
569#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0
570#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0
571#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0
572#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0
573#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0
574#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1
575#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0
576#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0
577#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0
578#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0
579#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0
580#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0
581#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0
582#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0
583#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0
584#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0
585#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0
586#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x0000 8 0
587#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0
588#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0
589#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0
590#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0
591#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0
592#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0
593#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0000 8 0
594#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0
595#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0
596#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2
597#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0
598#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0
599#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0
600#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0
601#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0000 8 0
602#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0
603#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3
604#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0
605#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0
606#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0
607#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0
608#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0
609#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0000 8 0
610#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0
611#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0
612#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0
613#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0
614#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0
615#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0
616#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0
617#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0000 8 0
618#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0
619#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0
620#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0
621#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0000 8 0
622#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0
623#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0
624#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0
625#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0
626#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0
627#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0
628#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0
629#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x0000 8 0
630#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0
631#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0
632#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2
633#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0
634#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0
635#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0
636#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3
637#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0
638#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0
639#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0
640#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0
641#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0
642#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0
643#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0000 8 0
644#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0
645#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0
646#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0
647#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0
648#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0
649#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0
650#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0
651#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0000 8 0
652#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0
653#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0
654#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0
655#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0
656#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0
657#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0
658#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0
659#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0000 8 0
660#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0
661#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2
662#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0
663#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0
664#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0
665#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0
666#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0
667#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0
668#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2
669#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0
670#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0
671#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0
672#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0
673#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0
674#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0
675#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2
676#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0
677#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0
678#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0
679#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0
680#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0
681#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0
682#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2
683#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0
684#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0
685#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0
686#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0
687#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0
688#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0
689#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1
690#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0
691#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0
692#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0
693#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0
694#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0
695#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0
696#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2
697#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0
698#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0
699#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0
700#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0
701#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0
702#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0
703#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1
704#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0
705#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1
706#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0
707#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0
708#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0
709#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2
710#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0
711#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1
712#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0
713#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1
714#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0
715#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0
716#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3
717#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0
718#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0
719#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1
720#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0
721#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1
722#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0
723#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0
724#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0
725#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4
726#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0
727#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1
728#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0
729#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0
730#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0
731#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0
732#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5
733#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0
734#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0
735#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0
736#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0
737#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0
738#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0
739#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0
740#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0
741#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0
742#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0
743#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0
744#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0
745#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0
746#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0
747#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0
748#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0
749#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0
750#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0
751#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0
752#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0
753#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0
754#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0
755#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2
756#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0
757#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0
758#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0
759#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1
760#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0
761#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0
762#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3
763#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0
764#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0
765#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0
766#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0
767#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1
768#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0
769#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0
770#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0
771#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2
772#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0
773#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0
774#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0
775#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1
776#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0
777#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0
778#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3
779#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0
780#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0
781#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1
782#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0
783#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0
784#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0
785#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0
786#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0
787#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x0000 8 0
788#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0
789#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0
790#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0
791#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0
792#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0
793#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0
794#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0
795#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0
796#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0
797#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0
798#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0
799#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3
800#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0
801#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0
802#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0000 8 0
803#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0
804#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0
805#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1
806#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0
807#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0
808#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0
809#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x0000 8 0
810#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0
811#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1
812#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1
813#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3
814#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0
815#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0
816#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0
817#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0
818#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1
819#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1
820#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0
821#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0
822#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0
823#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0
824#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0000 8 0
825#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0
826#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1
827#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0
828#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3
829#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0
830#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0
831#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0
832#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x0000 8 0
833#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0
834#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0
835#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0
836#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0
837#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0
838#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0
839#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0
840#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0
841#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0
842#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1
843#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2
844#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0
845#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2
846#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0
847#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0
848#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0
849#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3
850#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0
851#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0
852#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0
853#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0
854#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0
855#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0
856#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0
857#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0
858#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0
859#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0
860#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0
861#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0
862#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0
863#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0
864#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0
865#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0
866#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0
867#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0
868#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1
869#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0
870#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0
871#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0
872#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0
873#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0
874#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0
875#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0
876#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0
877#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0
878#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0
879#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0
880#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0
881#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0
882#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0
883#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0
884#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0
885#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1
886#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0
887#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1
888#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2
889#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0
890#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1
891#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0
892#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0
893#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0
894#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5
895#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0
896#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0
897#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0
898#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0
899#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0
900#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0
901#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0
902#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0
903#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0
904#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0
905#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1
906#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2
907#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0
908#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1
909#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0
910#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0
911#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1
912#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x0000 8 0
913#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1
914#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2
915#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0
916#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0
917#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0
918#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0
919#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1
920#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0000 8 0
921#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1
922#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2
923#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0
924#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1
925#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0
926#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0
927#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0
928#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0
929#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1
930#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2
931#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0
932#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1
933#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0
934#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0
935#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0
936#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0
937
938#endif /* __DTS_IMX6UL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
new file mode 100644
index 000000000000..09edbedfd908
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -0,0 +1,707 @@
1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "imx6ul-pinfunc.h"
13#include "skeleton.dtsi"
14
15/ {
16 aliases {
17 ethernet0 = &fec1;
18 ethernet1 = &fec2;
19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 mmc0 = &usdhc1;
29 mmc1 = &usdhc2;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 spi0 = &ecspi1;
39 spi1 = &ecspi2;
40 spi2 = &ecspi3;
41 spi3 = &ecspi4;
42 usbphy0 = &usbphy1;
43 usbphy1 = &usbphy2;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 compatible = "arm,cortex-a7";
52 device_type = "cpu";
53 reg = <0>;
54 clock-latency = <61036>; /* two CLK32 periods */
55 operating-points = <
56 /* kHz uV */
57 528000 1250000
58 396000 1150000
59 198000 1150000
60 >;
61 fsl,soc-operating-points = <
62 /* KHz uV */
63 528000 1250000
64 396000 1150000
65 198000 1150000
66 >;
67 clocks = <&clks IMX6UL_CLK_ARM>,
68 <&clks IMX6UL_CLK_PLL2_BUS>,
69 <&clks IMX6UL_CLK_PLL2_PFD2>,
70 <&clks IMX6UL_CA7_SECONDARY_SEL>,
71 <&clks IMX6UL_CLK_STEP>,
72 <&clks IMX6UL_CLK_PLL1_SW>,
73 <&clks IMX6UL_CLK_PLL1_SYS>,
74 <&clks IMX6UL_PLL1_BYPASS>,
75 <&clks IMX6UL_CLK_PLL1>,
76 <&clks IMX6UL_PLL1_BYPASS_SRC>,
77 <&clks IMX6UL_CLK_OSC>;
78 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
79 "secondary_sel", "step", "pll1_sw",
80 "pll1_sys", "pll1_bypass", "pll1",
81 "pll1_bypass_src", "osc";
82 arm-supply = <&reg_arm>;
83 soc-supply = <&reg_soc>;
84 };
85 };
86
87 intc: interrupt-controller@00a01000 {
88 compatible = "arm,cortex-a7-gic";
89 #interrupt-cells = <3>;
90 interrupt-controller;
91 reg = <0x00a01000 0x1000>,
92 <0x00a02000 0x1000>,
93 <0x00a04000 0x2000>,
94 <0x00a06000 0x2000>;
95 };
96
97 ckil: clock-cli {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <32768>;
101 clock-output-names = "ckil";
102 };
103
104 osc: clock-osc {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <24000000>;
108 clock-output-names = "osc";
109 };
110
111 ipp_di0: clock-di0 {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <0>;
115 clock-output-names = "ipp_di0";
116 };
117
118 ipp_di1: clock-di1 {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <0>;
122 clock-output-names = "ipp_di1";
123 };
124
125 soc {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
129 interrupt-parent = <&gpc>;
130 ranges;
131
132 pmu {
133 compatible = "arm,cortex-a7-pmu";
134 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
135 status = "disabled";
136 };
137
138 aips1: aips-bus@02000000 {
139 compatible = "fsl,aips-bus", "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 reg = <0x02000000 0x100000>;
143 ranges;
144
145 spba-bus@02000000 {
146 compatible = "fsl,spba-bus", "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 reg = <0x02000000 0x40000>;
150 ranges;
151
152 ecspi1: ecspi@02008000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02008000 0x4000>;
157 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks IMX6UL_CLK_ECSPI1>,
159 <&clks IMX6UL_CLK_ECSPI1>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162 };
163
164 ecspi2: ecspi@0200c000 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
168 reg = <0x0200c000 0x4000>;
169 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&clks IMX6UL_CLK_ECSPI2>,
171 <&clks IMX6UL_CLK_ECSPI2>;
172 clock-names = "ipg", "per";
173 status = "disabled";
174 };
175
176 ecspi3: ecspi@02010000 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
180 reg = <0x02010000 0x4000>;
181 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&clks IMX6UL_CLK_ECSPI3>,
183 <&clks IMX6UL_CLK_ECSPI3>;
184 clock-names = "ipg", "per";
185 status = "disabled";
186 };
187
188 ecspi4: ecspi@02014000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
192 reg = <0x02014000 0x4000>;
193 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clks IMX6UL_CLK_ECSPI4>,
195 <&clks IMX6UL_CLK_ECSPI4>;
196 clock-names = "ipg", "per";
197 status = "disabled";
198 };
199
200 uart7: serial@02018000 {
201 compatible = "fsl,imx6ul-uart",
202 "fsl,imx6q-uart";
203 reg = <0x02018000 0x4000>;
204 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
206 <&clks IMX6UL_CLK_UART7_SERIAL>;
207 clock-names = "ipg", "per";
208 status = "disabled";
209 };
210
211 uart1: serial@02020000 {
212 compatible = "fsl,imx6ul-uart",
213 "fsl,imx6q-uart";
214 reg = <0x02020000 0x4000>;
215 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
217 <&clks IMX6UL_CLK_UART1_SERIAL>;
218 clock-names = "ipg", "per";
219 status = "disabled";
220 };
221
222 uart8: serial@02024000 {
223 compatible = "fsl,imx6ul-uart",
224 "fsl,imx6q-uart";
225 reg = <0x02024000 0x4000>;
226 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
228 <&clks IMX6UL_CLK_UART8_SERIAL>;
229 clock-names = "ipg", "per";
230 status = "disabled";
231 };
232 };
233
234 gpt1: gpt@02098000 {
235 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
236 reg = <0x02098000 0x4000>;
237 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
239 <&clks IMX6UL_CLK_GPT1_SERIAL>;
240 clock-names = "ipg", "per";
241 };
242
243 gpio1: gpio@0209c000 {
244 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
245 reg = <0x0209c000 0x4000>;
246 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 };
253
254 gpio2: gpio@020a0000 {
255 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
256 reg = <0x020a0000 0x4000>;
257 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 };
264
265 gpio3: gpio@020a4000 {
266 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
267 reg = <0x020a4000 0x4000>;
268 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
270 gpio-controller;
271 #gpio-cells = <2>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 };
275
276 gpio4: gpio@020a8000 {
277 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
278 reg = <0x020a8000 0x4000>;
279 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
286
287 gpio5: gpio@020ac000 {
288 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
289 reg = <0x020ac000 0x4000>;
290 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 };
297
298 fec2: ethernet@020b4000 {
299 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
300 reg = <0x020b4000 0x4000>;
301 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clks IMX6UL_CLK_ENET>,
304 <&clks IMX6UL_CLK_ENET_AHB>,
305 <&clks IMX6UL_CLK_ENET_PTP>,
306 <&clks IMX6UL_CLK_ENET2_REF_125M>,
307 <&clks IMX6UL_CLK_ENET2_REF_125M>;
308 clock-names = "ipg", "ahb", "ptp",
309 "enet_clk_ref", "enet_out";
310 fsl,num-tx-queues=<1>;
311 fsl,num-rx-queues=<1>;
312 status = "disabled";
313 };
314
315 wdog1: wdog@020bc000 {
316 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
317 reg = <0x020bc000 0x4000>;
318 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks IMX6UL_CLK_WDOG1>;
320 };
321
322 wdog2: wdog@020c0000 {
323 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
324 reg = <0x020c0000 0x4000>;
325 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clks IMX6UL_CLK_WDOG2>;
327 status = "disabled";
328 };
329
330 clks: ccm@020c4000 {
331 compatible = "fsl,imx6ul-ccm";
332 reg = <0x020c4000 0x4000>;
333 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
335 #clock-cells = <1>;
336 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
337 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
338 };
339
340 anatop: anatop@020c8000 {
341 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
342 "syscon", "simple-bus";
343 reg = <0x020c8000 0x1000>;
344 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
347
348 reg_3p0: regulator-3p0@120 {
349 compatible = "fsl,anatop-regulator";
350 regulator-name = "vdd3p0";
351 regulator-min-microvolt = <2625000>;
352 regulator-max-microvolt = <3400000>;
353 anatop-reg-offset = <0x120>;
354 anatop-vol-bit-shift = <8>;
355 anatop-vol-bit-width = <5>;
356 anatop-min-bit-val = <0>;
357 anatop-min-voltage = <2625000>;
358 anatop-max-voltage = <3400000>;
359 anatop-enable-bit = <0>;
360 };
361
362 reg_arm: regulator-vddcore@140 {
363 compatible = "fsl,anatop-regulator";
364 regulator-name = "cpu";
365 regulator-min-microvolt = <725000>;
366 regulator-max-microvolt = <1450000>;
367 regulator-always-on;
368 anatop-reg-offset = <0x140>;
369 anatop-vol-bit-shift = <0>;
370 anatop-vol-bit-width = <5>;
371 anatop-delay-reg-offset = <0x170>;
372 anatop-delay-bit-shift = <24>;
373 anatop-delay-bit-width = <2>;
374 anatop-min-bit-val = <1>;
375 anatop-min-voltage = <725000>;
376 anatop-max-voltage = <1450000>;
377 };
378
379 reg_soc: regulator-vddsoc@140 {
380 compatible = "fsl,anatop-regulator";
381 regulator-name = "vddsoc";
382 regulator-min-microvolt = <725000>;
383 regulator-max-microvolt = <1450000>;
384 regulator-always-on;
385 anatop-reg-offset = <0x140>;
386 anatop-vol-bit-shift = <18>;
387 anatop-vol-bit-width = <5>;
388 anatop-delay-reg-offset = <0x170>;
389 anatop-delay-bit-shift = <28>;
390 anatop-delay-bit-width = <2>;
391 anatop-min-bit-val = <1>;
392 anatop-min-voltage = <725000>;
393 anatop-max-voltage = <1450000>;
394 };
395 };
396
397 usbphy1: usbphy@020c9000 {
398 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
399 reg = <0x020c9000 0x1000>;
400 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clks IMX6UL_CLK_USBPHY1>;
402 phy-3p0-supply = <&reg_3p0>;
403 fsl,anatop = <&anatop>;
404 };
405
406 usbphy2: usbphy@020ca000 {
407 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
408 reg = <0x020ca000 0x1000>;
409 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6UL_CLK_USBPHY2>;
411 phy-3p0-supply = <&reg_3p0>;
412 fsl,anatop = <&anatop>;
413 };
414
415 snvs: snvs@020cc000 {
416 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
417 reg = <0x020cc000 0x4000>;
418
419 snvs_rtc: snvs-rtc-lp {
420 compatible = "fsl,sec-v4.0-mon-rtc-lp";
421 regmap = <&snvs>;
422 offset = <0x34>;
423 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
425 };
426
427 snvs_pwrkey: snvs-powerkey {
428 compatible = "fsl,sec-v4.0-pwrkey";
429 regmap = <&snvs>;
430 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
431 linux,keycode = <KEY_POWER>;
432 wakeup-source;
433 };
434 };
435
436 epit1: epit@020d0000 {
437 reg = <0x020d0000 0x4000>;
438 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
439 };
440
441 epit2: epit@020d4000 {
442 reg = <0x020d4000 0x4000>;
443 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
444 };
445
446 src: src@020d8000 {
447 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
448 reg = <0x020d8000 0x4000>;
449 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
451 #reset-cells = <1>;
452 };
453
454 gpc: gpc@020dc000 {
455 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
456 reg = <0x020dc000 0x4000>;
457 interrupt-controller;
458 #interrupt-cells = <3>;
459 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-parent = <&intc>;
461 };
462
463 iomuxc: iomuxc@020e0000 {
464 compatible = "fsl,imx6ul-iomuxc";
465 reg = <0x020e0000 0x4000>;
466 };
467
468 gpr: iomuxc-gpr@020e4000 {
469 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
470 reg = <0x020e4000 0x4000>;
471 };
472
473 gpt2: gpt@020e8000 {
474 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
475 reg = <0x020e8000 0x4000>;
476 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clks IMX6UL_CLK_DUMMY>,
478 <&clks IMX6UL_CLK_DUMMY>;
479 clock-names = "ipg", "per";
480 };
481
482 pwm5: pwm@020f0000 {
483 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
484 reg = <0x020f0000 0x4000>;
485 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clks IMX6UL_CLK_DUMMY>,
487 <&clks IMX6UL_CLK_DUMMY>;
488 clock-names = "ipg", "per";
489 #pwm-cells = <2>;
490 };
491
492 pwm6: pwm@020f4000 {
493 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
494 reg = <0x020f4000 0x4000>;
495 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX6UL_CLK_DUMMY>,
497 <&clks IMX6UL_CLK_DUMMY>;
498 clock-names = "ipg", "per";
499 #pwm-cells = <2>;
500 };
501
502 pwm7: pwm@020f8000 {
503 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
504 reg = <0x020f8000 0x4000>;
505 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6UL_CLK_DUMMY>,
507 <&clks IMX6UL_CLK_DUMMY>;
508 clock-names = "ipg", "per";
509 #pwm-cells = <2>;
510 };
511
512 pwm8: pwm@020fc000 {
513 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
514 reg = <0x020fc000 0x4000>;
515 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clks IMX6UL_CLK_DUMMY>,
517 <&clks IMX6UL_CLK_DUMMY>;
518 clock-names = "ipg", "per";
519 #pwm-cells = <2>;
520 };
521 };
522
523 aips2: aips-bus@02100000 {
524 compatible = "fsl,aips-bus", "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <1>;
527 reg = <0x02100000 0x100000>;
528 ranges;
529
530 usbotg1: usb@02184000 {
531 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
532 reg = <0x02184000 0x200>;
533 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clks IMX6UL_CLK_USBOH3>;
535 fsl,usbphy = <&usbphy1>;
536 fsl,usbmisc = <&usbmisc 0>;
537 fsl,anatop = <&anatop>;
538 status = "disabled";
539 };
540
541 usbotg2: usb@02184200 {
542 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
543 reg = <0x02184200 0x200>;
544 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clks IMX6UL_CLK_USBOH3>;
546 fsl,usbphy = <&usbphy2>;
547 fsl,usbmisc = <&usbmisc 1>;
548 status = "disabled";
549 };
550
551 usbmisc: usbmisc@02184800 {
552 #index-cells = <1>;
553 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
554 reg = <0x02184800 0x200>;
555 };
556
557 fec1: ethernet@02188000 {
558 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
559 reg = <0x02188000 0x4000>;
560 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&clks IMX6UL_CLK_ENET>,
563 <&clks IMX6UL_CLK_ENET_AHB>,
564 <&clks IMX6UL_CLK_ENET_PTP>,
565 <&clks IMX6UL_CLK_ENET_REF>,
566 <&clks IMX6UL_CLK_ENET_REF>;
567 clock-names = "ipg", "ahb", "ptp",
568 "enet_clk_ref", "enet_out";
569 fsl,num-tx-queues=<1>;
570 fsl,num-rx-queues=<1>;
571 status = "disabled";
572 };
573
574 usdhc1: usdhc@02190000 {
575 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
576 reg = <0x02190000 0x4000>;
577 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clks IMX6UL_CLK_USDHC1>,
579 <&clks IMX6UL_CLK_USDHC1>,
580 <&clks IMX6UL_CLK_USDHC1>;
581 clock-names = "ipg", "ahb", "per";
582 bus-width = <4>;
583 status = "disabled";
584 };
585
586 usdhc2: usdhc@02194000 {
587 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
588 reg = <0x02194000 0x4000>;
589 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clks IMX6UL_CLK_USDHC2>,
591 <&clks IMX6UL_CLK_USDHC2>,
592 <&clks IMX6UL_CLK_USDHC2>;
593 clock-names = "ipg", "ahb", "per";
594 bus-width = <4>;
595 status = "disabled";
596 };
597
598 i2c1: i2c@021a0000 {
599 #address-cells = <1>;
600 #size-cells = <0>;
601 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
602 reg = <0x021a0000 0x4000>;
603 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&clks IMX6UL_CLK_I2C1>;
605 status = "disabled";
606 };
607
608 i2c2: i2c@021a4000 {
609 #address-cells = <1>;
610 #size-cells = <0>;
611 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
612 reg = <0x021a4000 0x4000>;
613 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clks IMX6UL_CLK_I2C2>;
615 status = "disabled";
616 };
617
618 i2c3: i2c@021a8000 {
619 #address-cells = <1>;
620 #size-cells = <0>;
621 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
622 reg = <0x021a8000 0x4000>;
623 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&clks IMX6UL_CLK_I2C3>;
625 status = "disabled";
626 };
627
628 qspi: qspi@021e0000 {
629 #address-cells = <1>;
630 #size-cells = <0>;
631 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
632 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
633 reg-names = "QuadSPI", "QuadSPI-memory";
634 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&clks IMX6UL_CLK_QSPI>,
636 <&clks IMX6UL_CLK_QSPI>;
637 clock-names = "qspi_en", "qspi";
638 status = "disabled";
639 };
640
641 uart2: serial@021e8000 {
642 compatible = "fsl,imx6ul-uart",
643 "fsl,imx6q-uart";
644 reg = <0x021e8000 0x4000>;
645 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
647 <&clks IMX6UL_CLK_UART2_SERIAL>;
648 clock-names = "ipg", "per";
649 status = "disabled";
650 };
651
652 uart3: serial@021ec000 {
653 compatible = "fsl,imx6ul-uart",
654 "fsl,imx6q-uart";
655 reg = <0x021ec000 0x4000>;
656 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
658 <&clks IMX6UL_CLK_UART3_SERIAL>;
659 clock-names = "ipg", "per";
660 status = "disabled";
661 };
662
663 uart4: serial@021f0000 {
664 compatible = "fsl,imx6ul-uart",
665 "fsl,imx6q-uart";
666 reg = <0x021f0000 0x4000>;
667 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
669 <&clks IMX6UL_CLK_UART4_SERIAL>;
670 clock-names = "ipg", "per";
671 status = "disabled";
672 };
673
674 uart5: serial@021f4000 {
675 compatible = "fsl,imx6ul-uart",
676 "fsl,imx6q-uart";
677 reg = <0x021f4000 0x4000>;
678 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
680 <&clks IMX6UL_CLK_UART5_SERIAL>;
681 clock-names = "ipg", "per";
682 status = "disabled";
683 };
684
685 i2c4: i2c@021f8000 {
686 #address-cells = <1>;
687 #size-cells = <0>;
688 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
689 reg = <0x021f8000 0x4000>;
690 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clks IMX6UL_CLK_I2C4>;
692 status = "disabled";
693 };
694
695 uart6: serial@021fc000 {
696 compatible = "fsl,imx6ul-uart",
697 "fsl,imx6q-uart";
698 reg = <0x021fc000 0x4000>;
699 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
701 <&clks IMX6UL_CLK_UART6_SERIAL>;
702 clock-names = "ipg", "per";
703 status = "disabled";
704 };
705 };
706 };
707};
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index c42cf8db0451..b738ce0f9d9b 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -121,6 +121,209 @@
121 clock-output-names = "osc"; 121 clock-output-names = "osc";
122 }; 122 };
123 123
124 etr@30086000 {
125 compatible = "arm,coresight-tmc", "arm,primecell";
126 reg = <0x30086000 0x1000>;
127 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
128 clock-names = "apb_pclk";
129
130 port {
131 etr_in_port: endpoint {
132 slave-mode;
133 remote-endpoint = <&replicator_out_port1>;
134 };
135 };
136 };
137
138 tpiu@30087000 {
139 compatible = "arm,coresight-tpiu", "arm,primecell";
140 reg = <0x30087000 0x1000>;
141 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
142 clock-names = "apb_pclk";
143
144 port {
145 tpiu_in_port: endpoint {
146 slave-mode;
147 remote-endpoint = <&replicator_out_port1>;
148 };
149 };
150 };
151
152 replicator {
153 /*
154 * non-configurable replicators don't show up on the
155 * AMBA bus. As such no need to add "arm,primecell"
156 */
157 compatible = "arm,coresight-replicator";
158
159 ports {
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 /* replicator output ports */
164 port@0 {
165 reg = <0>;
166 replicator_out_port0: endpoint {
167 remote-endpoint = <&tpiu_in_port>;
168 };
169 };
170
171 port@1 {
172 reg = <1>;
173 replicator_out_port1: endpoint {
174 remote-endpoint = <&etr_in_port>;
175 };
176 };
177
178 /* replicator input port */
179 port@2 {
180 reg = <0>;
181 replicator_in_port0: endpoint {
182 slave-mode;
183 remote-endpoint = <&etf_out_port>;
184 };
185 };
186 };
187 };
188
189 etf@30084000 {
190 compatible = "arm,coresight-tmc", "arm,primecell";
191 reg = <0x30084000 0x1000>;
192 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
193 clock-names = "apb_pclk";
194
195 ports {
196 #address-cells = <1>;
197 #size-cells = <0>;
198
199 port@0 {
200 reg = <0>;
201 etf_in_port: endpoint {
202 slave-mode;
203 remote-endpoint = <&hugo_funnel_out_port0>;
204 };
205 };
206
207 port@1 {
208 reg = <0>;
209 etf_out_port: endpoint {
210 remote-endpoint = <&replicator_in_port0>;
211 };
212 };
213 };
214 };
215
216 funnel@30083000 {
217 compatible = "arm,coresight-funnel", "arm,primecell";
218 reg = <0x30083000 0x1000>;
219 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
220 clock-names = "apb_pclk";
221
222 ports {
223 #address-cells = <1>;
224 #size-cells = <0>;
225
226 /* funnel input ports */
227 port@0 {
228 reg = <0>;
229 hugo_funnel_in_port0: endpoint {
230 slave-mode;
231 remote-endpoint = <&ca_funnel_out_port0>;
232 };
233 };
234
235 port@1 {
236 reg = <1>;
237 hugo_funnel_in_port1: endpoint {
238 slave-mode; /* M4 input */
239 };
240 };
241
242 port@2 {
243 reg = <0>;
244 hugo_funnel_out_port0: endpoint {
245 remote-endpoint = <&etf_in_port>;
246 };
247 };
248
249 /* the other input ports are not connect to anything */
250 };
251 };
252
253 funnel@30041000 {
254 compatible = "arm,coresight-funnel", "arm,primecell";
255 reg = <0x30041000 0x1000>;
256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
257 clock-names = "apb_pclk";
258
259 ports {
260 #address-cells = <1>;
261 #size-cells = <0>;
262
263 /* funnel input ports */
264 port@0 {
265 reg = <0>;
266 ca_funnel_in_port0: endpoint {
267 slave-mode;
268 remote-endpoint = <&etm0_out_port>;
269 };
270 };
271
272 port@1 {
273 reg = <1>;
274 ca_funnel_in_port1: endpoint {
275 slave-mode;
276 remote-endpoint = <&etm1_out_port>;
277 };
278 };
279
280 /* funnel output port */
281 port@2 {
282 reg = <0>;
283 ca_funnel_out_port0: endpoint {
284 remote-endpoint = <&hugo_funnel_in_port0>;
285 };
286 };
287
288 /* the other input ports are not connect to anything */
289 };
290 };
291
292 etm@3007c000 {
293 compatible = "arm,coresight-etm3x", "arm,primecell";
294 reg = <0x3007c000 0x1000>;
295 cpu = <&cpu0>;
296 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
297 clock-names = "apb_pclk";
298
299 port {
300 etm0_out_port: endpoint {
301 remote-endpoint = <&ca_funnel_in_port0>;
302 };
303 };
304 };
305
306 etm@3007d000 {
307 compatible = "arm,coresight-etm3x", "arm,primecell";
308 reg = <0x3007d000 0x1000>;
309
310 /*
311 * System will hang if added nosmp in kernel command line
312 * without arm,primecell-periphid because amba bus try to
313 * read id and core1 power off at this time.
314 */
315 arm,primecell-periphid = <0xbb956>;
316 cpu = <&cpu1>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
318 clock-names = "apb_pclk";
319
320 port {
321 etm1_out_port: endpoint {
322 remote-endpoint = <&ca_funnel_in_port1>;
323 };
324 };
325 };
326
124 soc { 327 soc {
125 #address-cells = <1>; 328 #address-cells = <1>;
126 #size-cells = <1>; 329 #size-cells = <1>;
@@ -212,6 +415,37 @@
212 #interrupt-cells = <2>; 415 #interrupt-cells = <2>;
213 }; 416 };
214 417
418 wdog1: wdog@30280000 {
419 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
420 reg = <0x30280000 0x10000>;
421 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
423 };
424
425 wdog2: wdog@30290000 {
426 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
427 reg = <0x30290000 0x10000>;
428 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
430 status = "disabled";
431 };
432
433 wdog3: wdog@302a0000 {
434 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
435 reg = <0x302a0000 0x10000>;
436 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
438 status = "disabled";
439 };
440
441 wdog4: wdog@302b0000 {
442 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
443 reg = <0x302b0000 0x10000>;
444 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
446 status = "disabled";
447 };
448
215 gpt1: gpt@302d0000 { 449 gpt1: gpt@302d0000 {
216 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 450 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
217 reg = <0x302d0000 0x10000>; 451 reg = <0x302d0000 0x10000>;
@@ -291,17 +525,31 @@
291 }; 525 };
292 526
293 snvs: snvs@30370000 { 527 snvs: snvs@30370000 {
294 compatible = "fsl,sec-v4.0-mon", "simple-bus"; 528 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
295 #address-cells = <1>; 529 reg = <0x30370000 0x10000>;
296 #size-cells = <1>;
297 ranges = <0 0x30370000 0x10000>;
298 530
299 snvs-rtc-lp@34 { 531 snvs_rtc: snvs-rtc-lp {
300 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 532 compatible = "fsl,sec-v4.0-mon-rtc-lp";
301 reg = <0x34 0x58>; 533 regmap = <&snvs>;
534 offset = <0x34>;
302 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 535 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 536 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
304 }; 537 };
538
539 snvs_poweroff: snvs-poweroff {
540 compatible = "syscon-poweroff";
541 regmap = <&snvs>;
542 offset = <0x38>;
543 mask = <0x60>;
544 };
545
546 snvs_pwrkey: snvs-powerkey {
547 compatible = "fsl,sec-v4.0-pwrkey";
548 regmap = <&snvs>;
549 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
550 linux,keycode = <KEY_POWER>;
551 wakeup-source;
552 };
305 }; 553 };
306 554
307 clks: ccm@30380000 { 555 clks: ccm@30380000 {
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16ba8c95..0521e6864cb7 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -58,6 +58,55 @@
58 enet0_sgmii_phy = &sgmii_phy1c; 58 enet0_sgmii_phy = &sgmii_phy1c;
59 enet1_sgmii_phy = &sgmii_phy1d; 59 enet1_sgmii_phy = &sgmii_phy1d;
60 }; 60 };
61
62 sys_mclk: clock-mclk {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <24576000>;
66 };
67
68 regulators {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 reg_3p3v: regulator@0 {
74 compatible = "regulator-fixed";
75 reg = <0>;
76 regulator-name = "3P3V";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 regulator-always-on;
80 };
81 };
82
83 sound {
84 compatible = "simple-audio-card";
85 simple-audio-card,format = "i2s";
86 simple-audio-card,widgets =
87 "Microphone", "Microphone Jack",
88 "Headphone", "Headphone Jack",
89 "Speaker", "Speaker Ext",
90 "Line", "Line In Jack";
91 simple-audio-card,routing =
92 "MIC_IN", "Microphone Jack",
93 "Microphone Jack", "Mic Bias",
94 "LINE_IN", "Line In Jack",
95 "Headphone Jack", "HP_OUT",
96 "Speaker Ext", "LINE_OUT";
97
98 simple-audio-card,cpu {
99 sound-dai = <&sai2>;
100 frame-master;
101 bitclock-master;
102 };
103
104 simple-audio-card,codec {
105 sound-dai = <&codec>;
106 frame-master;
107 bitclock-master;
108 };
109 };
61}; 110};
62 111
63&dspi0 { 112&dspi0 {
@@ -75,10 +124,31 @@
75 }; 124 };
76}; 125};
77 126
127&enet0 {
128 tbi-handle = <&tbi0>;
129 phy-handle = <&sgmii_phy1c>;
130 phy-connection-type = "sgmii";
131 status = "okay";
132};
133
134&enet1 {
135 tbi-handle = <&tbi0>;
136 phy-handle = <&sgmii_phy1d>;
137 phy-connection-type = "sgmii";
138 status = "okay";
139};
140
141&enet2 {
142 phy-handle = <&rgmii_phy3>;
143 phy-connection-type = "rgmii-id";
144 status = "okay";
145};
146
78&i2c0 { 147&i2c0 {
79 status = "okay"; 148 status = "okay";
80 149
81 pca9547: mux@77 { 150 pca9547: mux@77 {
151 compatible = "nxp,pca9547";
82 reg = <0x77>; 152 reg = <0x77>;
83 #address-cells = <1>; 153 #address-cells = <1>;
84 #size-cells = <0>; 154 #size-cells = <0>;
@@ -133,6 +203,21 @@
133 reg = <0x4c>; 203 reg = <0x4c>;
134 }; 204 };
135 }; 205 };
206
207 i2c@4 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 reg = <0x4>;
211
212 codec: sgtl5000@2a {
213 #sound-dai-cells = <0>;
214 compatible = "fsl,sgtl5000";
215 reg = <0x2a>;
216 VDDA-supply = <&reg_3p3v>;
217 VDDIO-supply = <&reg_3p3v>;
218 clocks = <&sys_mclk 1>;
219 };
220 };
136 }; 221 };
137}; 222};
138 223
@@ -231,6 +316,10 @@
231 }; 316 };
232}; 317};
233 318
319&sai2 {
320 status = "okay";
321};
322
234&uart0 { 323&uart0 {
235 status = "okay"; 324 status = "okay";
236}; 325};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e2d918..e008f9367510 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -56,6 +56,55 @@
56 enet0_sgmii_phy = &sgmii_phy2; 56 enet0_sgmii_phy = &sgmii_phy2;
57 enet1_sgmii_phy = &sgmii_phy0; 57 enet1_sgmii_phy = &sgmii_phy0;
58 }; 58 };
59
60 sys_mclk: clock-mclk {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <24576000>;
64 };
65
66 regulators {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 reg_3p3v: regulator@0 {
72 compatible = "regulator-fixed";
73 reg = <0>;
74 regulator-name = "3P3V";
75 regulator-min-microvolt = <3300000>;
76 regulator-max-microvolt = <3300000>;
77 regulator-always-on;
78 };
79 };
80
81 sound {
82 compatible = "simple-audio-card";
83 simple-audio-card,format = "i2s";
84 simple-audio-card,widgets =
85 "Microphone", "Microphone Jack",
86 "Headphone", "Headphone Jack",
87 "Speaker", "Speaker Ext",
88 "Line", "Line In Jack";
89 simple-audio-card,routing =
90 "MIC_IN", "Microphone Jack",
91 "Microphone Jack", "Mic Bias",
92 "LINE_IN", "Line In Jack",
93 "Headphone Jack", "HP_OUT",
94 "Speaker Ext", "LINE_OUT";
95
96 simple-audio-card,cpu {
97 sound-dai = <&sai1>;
98 frame-master;
99 bitclock-master;
100 };
101
102 simple-audio-card,codec {
103 sound-dai = <&codec>;
104 frame-master;
105 bitclock-master;
106 };
107 };
59}; 108};
60 109
61&dspi1 { 110&dspi1 {
@@ -73,12 +122,40 @@
73 }; 122 };
74}; 123};
75 124
125&enet0 {
126 tbi-handle = <&tbi1>;
127 phy-handle = <&sgmii_phy2>;
128 phy-connection-type = "sgmii";
129 status = "okay";
130};
131
132&enet1 {
133 tbi-handle = <&tbi1>;
134 phy-handle = <&sgmii_phy0>;
135 phy-connection-type = "sgmii";
136 status = "okay";
137};
138
139&enet2 {
140 phy-handle = <&rgmii_phy1>;
141 phy-connection-type = "rgmii-id";
142 status = "okay";
143};
144
76&i2c0 { 145&i2c0 {
77 status = "okay"; 146 status = "okay";
78}; 147};
79 148
80&i2c1 { 149&i2c1 {
81 status = "okay"; 150 status = "okay";
151 codec: sgtl5000@a {
152 #sound-dai-cells = <0>;
153 compatible = "fsl,sgtl5000";
154 reg = <0x0a>;
155 VDDA-supply = <&reg_3p3v>;
156 VDDIO-supply = <&reg_3p3v>;
157 clocks = <&sys_mclk 1>;
158 };
82}; 159};
83 160
84&ifc { 161&ifc {
@@ -118,6 +195,10 @@
118 }; 195 };
119}; 196};
120 197
198&sai1 {
199 status = "okay";
200};
201
121&uart0 { 202&uart0 {
122 status = "okay"; 203 status = "okay";
123}; 204};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27ac65a..973a496207fc 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -53,6 +53,9 @@
53 interrupt-parent = <&gic>; 53 interrupt-parent = <&gic>;
54 54
55 aliases { 55 aliases {
56 ethernet0 = &enet0;
57 ethernet1 = &enet1;
58 ethernet2 = &enet2;
56 serial0 = &lpuart0; 59 serial0 = &lpuart0;
57 serial1 = &lpuart1; 60 serial1 = &lpuart1;
58 serial2 = &lpuart2; 61 serial2 = &lpuart2;
@@ -184,7 +187,7 @@
184 }; 187 };
185 188
186 dspi0: dspi@2100000 { 189 dspi0: dspi@2100000 {
187 compatible = "fsl,vf610-dspi"; 190 compatible = "fsl,ls1021a-v1.0-dspi";
188 #address-cells = <1>; 191 #address-cells = <1>;
189 #size-cells = <0>; 192 #size-cells = <0>;
190 reg = <0x0 0x2100000 0x0 0x10000>; 193 reg = <0x0 0x2100000 0x0 0x10000>;
@@ -197,7 +200,7 @@
197 }; 200 };
198 201
199 dspi1: dspi@2110000 { 202 dspi1: dspi@2110000 {
200 compatible = "fsl,vf610-dspi"; 203 compatible = "fsl,ls1021a-v1.0-dspi";
201 #address-cells = <1>; 204 #address-cells = <1>;
202 #size-cells = <0>; 205 #size-cells = <0>;
203 reg = <0x0 0x2110000 0x0 0x10000>; 206 reg = <0x0 0x2110000 0x0 0x10000>;
@@ -342,28 +345,30 @@
342 }; 345 };
343 346
344 sai1: sai@2b50000 { 347 sai1: sai@2b50000 {
348 #sound-dai-cells = <0>;
345 compatible = "fsl,vf610-sai"; 349 compatible = "fsl,vf610-sai";
346 reg = <0x0 0x2b50000 0x0 0x10000>; 350 reg = <0x0 0x2b50000 0x0 0x10000>;
347 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 351 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&platform_clk 1>; 352 clocks = <&platform_clk 1>, <&platform_clk 1>,
349 clock-names = "sai"; 353 <&platform_clk 1>, <&platform_clk 1>;
354 clock-names = "bus", "mclk1", "mclk2", "mclk3";
350 dma-names = "tx", "rx"; 355 dma-names = "tx", "rx";
351 dmas = <&edma0 1 47>, 356 dmas = <&edma0 1 47>,
352 <&edma0 1 46>; 357 <&edma0 1 46>;
353 big-endian;
354 status = "disabled"; 358 status = "disabled";
355 }; 359 };
356 360
357 sai2: sai@2b60000 { 361 sai2: sai@2b60000 {
362 #sound-dai-cells = <0>;
358 compatible = "fsl,vf610-sai"; 363 compatible = "fsl,vf610-sai";
359 reg = <0x0 0x2b60000 0x0 0x10000>; 364 reg = <0x0 0x2b60000 0x0 0x10000>;
360 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 365 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&platform_clk 1>; 366 clocks = <&platform_clk 1>, <&platform_clk 1>,
362 clock-names = "sai"; 367 <&platform_clk 1>, <&platform_clk 1>;
368 clock-names = "bus", "mclk1", "mclk2", "mclk3";
363 dma-names = "tx", "rx"; 369 dma-names = "tx", "rx";
364 dmas = <&edma0 1 45>, 370 dmas = <&edma0 1 45>,
365 <&edma0 1 44>; 371 <&edma0 1 44>;
366 big-endian;
367 status = "disabled"; 372 status = "disabled";
368 }; 373 };
369 374
@@ -391,6 +396,91 @@
391 reg = <0x0 0x2d24000 0x0 0x4000>; 396 reg = <0x0 0x2d24000 0x0 0x4000>;
392 }; 397 };
393 398
399 enet0: ethernet@2d10000 {
400 compatible = "fsl,etsec2";
401 device_type = "network";
402 #address-cells = <2>;
403 #size-cells = <2>;
404 interrupt-parent = <&gic>;
405 model = "eTSEC";
406 fsl,magic-packet;
407 ranges;
408
409 queue-group@2d10000 {
410 #address-cells = <2>;
411 #size-cells = <2>;
412 reg = <0x0 0x2d10000 0x0 0x1000>;
413 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
416 };
417
418 queue-group@2d14000 {
419 #address-cells = <2>;
420 #size-cells = <2>;
421 reg = <0x0 0x2d14000 0x0 0x1000>;
422 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
425 };
426 };
427
428 enet1: ethernet@2d50000 {
429 compatible = "fsl,etsec2";
430 device_type = "network";
431 #address-cells = <2>;
432 #size-cells = <2>;
433 interrupt-parent = <&gic>;
434 model = "eTSEC";
435 ranges;
436
437 queue-group@2d50000 {
438 #address-cells = <2>;
439 #size-cells = <2>;
440 reg = <0x0 0x2d50000 0x0 0x1000>;
441 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
444 };
445
446 queue-group@2d54000 {
447 #address-cells = <2>;
448 #size-cells = <2>;
449 reg = <0x0 0x2d54000 0x0 0x1000>;
450 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
453 };
454 };
455
456 enet2: ethernet@2d90000 {
457 compatible = "fsl,etsec2";
458 device_type = "network";
459 #address-cells = <2>;
460 #size-cells = <2>;
461 interrupt-parent = <&gic>;
462 model = "eTSEC";
463 ranges;
464
465 queue-group@2d90000 {
466 #address-cells = <2>;
467 #size-cells = <2>;
468 reg = <0x0 0x2d90000 0x0 0x1000>;
469 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
472 };
473
474 queue-group@2d94000 {
475 #address-cells = <2>;
476 #size-cells = <2>;
477 reg = <0x0 0x2d94000 0x0 0x1000>;
478 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
481 };
482 };
483
394 usb@8600000 { 484 usb@8600000 {
395 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 485 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
396 reg = <0x0 0x8600000 0x0 0x1000>; 486 reg = <0x0 0x8600000 0x0 0x1000>;
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 606753eb72c8..ed65e0f7dfc0 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -9,7 +9,7 @@
9 9
10/ { 10/ {
11 chosen { 11 chosen {
12 bootargs = "console=ttyLP0,115200"; 12 stdout-path = "serial0:115200n8";
13 }; 13 };
14 14
15 clk16m: clk16m { 15 clk16m: clk16m {
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 4aa335166be7..6865137fd114 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -226,7 +226,10 @@
226 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 226 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks VF610_CLK_ADC0>; 227 clocks = <&clks VF610_CLK_ADC0>;
228 clock-names = "adc"; 228 clock-names = "adc";
229 #io-channel-cells = <1>;
229 status = "disabled"; 230 status = "disabled";
231 fsl,adck-max-frequency = <30000000>, <40000000>,
232 <20000000>;
230 }; 233 };
231 234
232 wdoga5: wdog@4003e000 { 235 wdoga5: wdog@4003e000 {
@@ -242,7 +245,8 @@
242 #address-cells = <1>; 245 #address-cells = <1>;
243 #size-cells = <0>; 246 #size-cells = <0>;
244 compatible = "fsl,vf610-qspi"; 247 compatible = "fsl,vf610-qspi";
245 reg = <0x40044000 0x1000>; 248 reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
249 reg-names = "QuadSPI", "QuadSPI-memory";
246 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 250 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clks VF610_CLK_QSPI0_EN>, 251 clocks = <&clks VF610_CLK_QSPI0_EN>,
248 <&clks VF610_CLK_QSPI0>; 252 <&clks VF610_CLK_QSPI0>;
@@ -347,6 +351,20 @@
347 status = "disabled"; 351 status = "disabled";
348 }; 352 };
349 353
354 i2c1: i2c@40067000 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "fsl,vf610-i2c";
358 reg = <0x40067000 0x1000>;
359 interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks VF610_CLK_I2C1>;
361 clock-names = "ipg";
362 dmas = <&edma0 0 52>,
363 <&edma0 0 53>;
364 dma-names = "rx","tx";
365 status = "disabled";
366 };
367
350 clks: ccm@4006b000 { 368 clks: ccm@4006b000 {
351 compatible = "fsl,vf610-ccm"; 369 compatible = "fsl,vf610-ccm";
352 reg = <0x4006b000 0x1000>; 370 reg = <0x4006b000 0x1000>;
@@ -404,14 +422,13 @@
404 }; 422 };
405 423
406 snvs0: snvs@400a7000 { 424 snvs0: snvs@400a7000 {
407 compatible = "fsl,sec-v4.0-mon", "simple-bus"; 425 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
408 #address-cells = <1>; 426 reg = <0x400a7000 0x2000>;
409 #size-cells = <1>;
410 ranges = <0 0x400a7000 0x2000>;
411 427
412 snvsrtc: snvs-rtc-lp@34 { 428 snvsrtc: snvs-rtc-lp {
413 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 429 compatible = "fsl,sec-v4.0-mon-rtc-lp";
414 reg = <0x34 0x58>; 430 regmap = <&snvs0>;
431 offset = <0x34>;
415 interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; 432 interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clks VF610_CLK_SNVS>; 433 clocks = <&clks VF610_CLK_SNVS>;
417 clock-names = "snvs-rtc"; 434 clock-names = "snvs-rtc";
@@ -442,9 +459,23 @@
442 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 459 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks VF610_CLK_ADC1>; 460 clocks = <&clks VF610_CLK_ADC1>;
444 clock-names = "adc"; 461 clock-names = "adc";
462 #io-channel-cells = <1>;
445 status = "disabled"; 463 status = "disabled";
446 }; 464 };
447 465
466 esdhc0: esdhc@400b1000 {
467 compatible = "fsl,imx53-esdhc";
468 reg = <0x400b1000 0x1000>;
469 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&clks VF610_CLK_IPG_BUS>,
471 <&clks VF610_CLK_PLATFORM_BUS>,
472 <&clks VF610_CLK_ESDHC0>;
473 clock-names = "ipg", "ahb", "per";
474 status = "disabled";
475 fsl,adck-max-frequency = <30000000>, <40000000>,
476 <20000000>;
477 };
478
448 esdhc1: esdhc@400b2000 { 479 esdhc1: esdhc@400b2000 {
449 compatible = "fsl,imx53-esdhc"; 480 compatible = "fsl,imx53-esdhc";
450 reg = <0x400b2000 0x1000>; 481 reg = <0x400b2000 0x1000>;
@@ -488,6 +519,19 @@
488 status = "disabled"; 519 status = "disabled";
489 }; 520 };
490 521
522 qspi1: quadspi@400c4000 {
523 #address-cells = <1>;
524 #size-cells = <0>;
525 compatible = "fsl,vf610-qspi";
526 reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>;
527 reg-names = "QuadSPI", "QuadSPI-memory";
528 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&clks VF610_CLK_QSPI1_EN>,
530 <&clks VF610_CLK_QSPI1>;
531 clock-names = "qspi_en", "qspi";
532 status = "disabled";
533 };
534
491 fec0: ethernet@400d0000 { 535 fec0: ethernet@400d0000 {
492 compatible = "fsl,mvf600-fec"; 536 compatible = "fsl,mvf600-fec";
493 reg = <0x400d0000 0x1000>; 537 reg = <0x400d0000 0x1000>;
@@ -520,6 +564,33 @@
520 status = "disabled"; 564 status = "disabled";
521 }; 565 };
522 566
567 i2c2: i2c@400e6000 {
568 #address-cells = <1>;
569 #size-cells = <0>;
570 compatible = "fsl,vf610-i2c";
571 reg = <0x400e6000 0x1000>;
572 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clks VF610_CLK_I2C2>;
574 clock-names = "ipg";
575 dmas = <&edma0 1 36>,
576 <&edma0 1 37>;
577 dma-names = "rx","tx";
578 status = "disabled";
579 };
580
581 i2c3: i2c@400e7000 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "fsl,vf610-i2c";
585 reg = <0x400e7000 0x1000>;
586 interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&clks VF610_CLK_I2C3>;
588 clock-names = "ipg";
589 dmas = <&edma0 1 38>,
590 <&edma0 1 39>;
591 dma-names = "rx","tx";
592 status = "disabled";
593 };
523 }; 594 };
524 }; 595 };
525}; 596};
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 75fae169ce8f..1ada68abb158 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -22,5 +22,6 @@ obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o
22obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o 22obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o
23obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o 23obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
24obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o 24obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
25obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
25obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o 26obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
26obj-$(CONFIG_SOC_VF610) += clk-vf610.o 27obj-$(CONFIG_SOC_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index d046f8e43de8..c507bcad2c37 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -494,6 +494,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
494 clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); 494 clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
495 } 495 }
496 496
497 clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
498 if (clk_on_imx6dl())
499 clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
500
497 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); 501 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
498 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); 502 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
499 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); 503 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
new file mode 100644
index 000000000000..aaa36650695f
--- /dev/null
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -0,0 +1,432 @@
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/clock/imx6ul-clock.h>
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/types.h>
22
23#include "clk.h"
24
25#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
26#define CCDR 0x4
27
28static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
29static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
30static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
31static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
32static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
33static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
34static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
35static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
36static const char *ca7_secondary_sels[] = { "pll2_pfd2_396m", "pll2_bus", };
37static const char *step_sels[] = { "osc", "ca7_secondary_sel", };
38static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
39static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
40static const char *axi_sels[] = {"periph", "axi_alt_sel", };
41static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
42static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
43static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
44static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
45static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
46static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
47static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
48static const char *bch_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
49static const char *gpmi_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
50static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", };
51static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
52static const char *sai_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
53static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
54static const char *sim_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
55static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
56static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
57static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
58static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
59static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
60static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
61static const char *ecspi_sels[] = { "pll3_60m", "osc", };
62static const char *uart_sels[] = { "pll3_80m", "osc", };
63static const char *perclk_sels[] = { "ipg", "osc", };
64static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
65static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
66static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
67
68static struct clk *clks[IMX6UL_CLK_END];
69static struct clk_onecell_data clk_data;
70
71static int const clks_init_on[] __initconst = {
72 IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3,
73 IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
74 IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
75};
76
77static struct clk_div_table clk_enet_ref_table[] = {
78 { .val = 0, .div = 20, },
79 { .val = 1, .div = 10, },
80 { .val = 2, .div = 5, },
81 { .val = 3, .div = 4, },
82 { }
83};
84
85static struct clk_div_table post_div_table[] = {
86 { .val = 2, .div = 1, },
87 { .val = 1, .div = 2, },
88 { .val = 0, .div = 4, },
89 { }
90};
91
92static struct clk_div_table video_div_table[] = {
93 { .val = 0, .div = 1, },
94 { .val = 1, .div = 2, },
95 { .val = 2, .div = 1, },
96 { .val = 3, .div = 4, },
97 { }
98};
99
100static u32 share_count_asrc;
101static u32 share_count_audio;
102static u32 share_count_sai1;
103static u32 share_count_sai2;
104static u32 share_count_sai3;
105
106static void __init imx6ul_clocks_init(struct device_node *ccm_node)
107{
108 struct device_node *np;
109 void __iomem *base;
110 int i;
111
112 clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
113
114 clks[IMX6UL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
115 clks[IMX6UL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
116
117 /* ipp_di clock is external input */
118 clks[IMX6UL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
119 clks[IMX6UL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
120
121 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");
122 base = of_iomap(np, 0);
123 WARN_ON(!base);
124
125 clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
126 clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
127 clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
128 clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
129 clks[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
130 clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
131 clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
132
133 clks[IMX6UL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
134 clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
135 clks[IMX6UL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
136 clks[IMX6UL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
137 clks[IMX6UL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
138 clks[IMX6UL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
139 clks[IMX6UL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
140
141 clks[IMX6UL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
142 clks[IMX6UL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
143 clks[IMX6UL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
144 clks[IMX6UL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
145 clks[IMX6UL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
146 clks[IMX6UL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
147 clks[IMX6UL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
148 clks[IMX6UL_CLK_CSI_SEL] = imx_clk_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT);
149
150 /* Do not bypass PLLs initially */
151 clk_set_parent(clks[IMX6UL_PLL1_BYPASS], clks[IMX6UL_CLK_PLL1]);
152 clk_set_parent(clks[IMX6UL_PLL2_BYPASS], clks[IMX6UL_CLK_PLL2]);
153 clk_set_parent(clks[IMX6UL_PLL3_BYPASS], clks[IMX6UL_CLK_PLL3]);
154 clk_set_parent(clks[IMX6UL_PLL4_BYPASS], clks[IMX6UL_CLK_PLL4]);
155 clk_set_parent(clks[IMX6UL_PLL5_BYPASS], clks[IMX6UL_CLK_PLL5]);
156 clk_set_parent(clks[IMX6UL_PLL6_BYPASS], clks[IMX6UL_CLK_PLL6]);
157 clk_set_parent(clks[IMX6UL_PLL7_BYPASS], clks[IMX6UL_CLK_PLL7]);
158
159 clks[IMX6UL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
160 clks[IMX6UL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
161 clks[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
162 clks[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
163 clks[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
164 clks[IMX6UL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
165 clks[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
166
167 /*
168 * Bit 20 is the reserved and read-only bit, we do this only for:
169 * - Do nothing for usbphy clk_enable/disable
170 * - Keep refcount when do usbphy clk_enable/disable, in that case,
171 * the clk framework many need to enable/disable usbphy's parent
172 */
173 clks[IMX6UL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
174 clks[IMX6UL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
175
176 /*
177 * usbphy*_gate needs to be on after system boots up, and software
178 * never needs to control it anymore.
179 */
180 clks[IMX6UL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
181 clks[IMX6UL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
182
183 /* name parent_name reg idx */
184 clks[IMX6UL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
185 clks[IMX6UL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
186 clks[IMX6UL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
187 clks[IMX6UL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
188 clks[IMX6UL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
189 clks[IMX6UL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
190 clks[IMX6UL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
191 clks[IMX6UL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
192
193 clks[IMX6UL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
194 base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
195 clks[IMX6UL_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
196 base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
197
198 clks[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20);
199 clks[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
200 clks[IMX6UL_CLK_ENET_PTP] = imx_clk_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21);
201
202 clks[IMX6UL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
203 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
204 clks[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
205 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
206 clks[IMX6UL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
207 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
208 clks[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
209 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
210
211 /* name parent_name mult div */
212 clks[IMX6UL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
213 clks[IMX6UL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
214 clks[IMX6UL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
215 clks[IMX6UL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
216
217 np = ccm_node;
218 base = of_iomap(np, 0);
219 WARN_ON(!base);
220
221 clks[IMX6UL_CA7_SECONDARY_SEL] = imx_clk_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels));
222 clks[IMX6UL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
223 clks[IMX6UL_CLK_PLL1_SW] = imx_clk_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
224 clks[IMX6UL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
225 clks[IMX6UL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0);
226 clks[IMX6UL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
227 clks[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
228 clks[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
229 clks[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
230 clks[IMX6UL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
231 clks[IMX6UL_CLK_GPMI_SEL] = imx_clk_mux("gpmi_sel", base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels));
232 clks[IMX6UL_CLK_BCH_SEL] = imx_clk_mux("bch_sel", base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels));
233 clks[IMX6UL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
234 clks[IMX6UL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
235 clks[IMX6UL_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels));
236 clks[IMX6UL_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels));
237 clks[IMX6UL_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels));
238 clks[IMX6UL_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
239 clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
240 clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
241 clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
242 clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels));
243 clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
244 clks[IMX6UL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
245 clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
246 clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
247 clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
248 clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
249 clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
250
251 clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
252 clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
253
254 clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
255 clks[IMX6UL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
256 clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7);
257 clks[IMX6UL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "qspi1_sel", 1, 7);
258
259 clks[IMX6UL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
260 clks[IMX6UL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
261
262 clks[IMX6UL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
263 clks[IMX6UL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
264 clks[IMX6UL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
265 clks[IMX6UL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3);
266 clks[IMX6UL_CLK_QSPI1_PDOF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3);
267 clks[IMX6UL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
268 clks[IMX6UL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
269 clks[IMX6UL_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6);
270 clks[IMX6UL_CLK_GPMI_PODF] = imx_clk_divider("gpmi_podf", "gpmi_sel", base + 0x24, 22, 3);
271 clks[IMX6UL_CLK_BCH_PODF] = imx_clk_divider("bch_podf", "bch_sel", base + 0x24, 19, 3);
272 clks[IMX6UL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
273 clks[IMX6UL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
274 clks[IMX6UL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
275 clks[IMX6UL_CLK_SAI3_PRED] = imx_clk_divider("sai3_pred", "sai3_sel", base + 0x28, 22, 3);
276 clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6);
277 clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3);
278 clks[IMX6UL_CLK_SAI1_PODF] = imx_clk_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6);
279 clks[IMX6UL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
280 clks[IMX6UL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
281 clks[IMX6UL_CLK_SAI2_PRED] = imx_clk_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3);
282 clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6);
283 clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
284 clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
285 clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3);
286 clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
287 clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
288 clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
289
290 clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
291 clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
292 clks[IMX6UL_CLK_AXI_PODF] = imx_clk_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
293 clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
294
295 /* CCGR0 */
296 clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
297 clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
298 clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4);
299 clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
300 clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
301 clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
302 clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
303 clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
304 clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
305 clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16);
306 clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
307 clks[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20);
308 clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x68, 24);
309 clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x68, 26);
310 clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
311 clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
312 clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
313
314 /* CCGR1 */
315 clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
316 clks[IMX6UL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
317 clks[IMX6UL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
318 clks[IMX6UL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
319 clks[IMX6UL_CLK_ADC2] = imx_clk_gate2("adc2", "ipg", base + 0x6c, 8);
320 clks[IMX6UL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10);
321 clks[IMX6UL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10);
322 clks[IMX6UL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
323 clks[IMX6UL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
324 clks[IMX6UL_CLK_ADC1] = imx_clk_gate2("adc1", "ipg", base + 0x6c, 16);
325 clks[IMX6UL_CLK_GPT1_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20);
326 clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
327 clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
328 clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
329
330 /* CCGR2 */
331 clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2);
332 clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
333 clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
334 clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
335 clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
336 clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14);
337 clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
338 clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
339
340 /* CCGR3 */
341 clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2);
342 clks[IMX6UL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2);
343 clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4);
344 clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4);
345 clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6);
346 clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6);
347 clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
348 clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
349 clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
350 clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
351 clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24);
352 clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28);
353
354 /* CCGR4 */
355 clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12);
356 clks[IMX6UL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
357 clks[IMX6UL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
358 clks[IMX6UL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
359 clks[IMX6UL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
360 clks[IMX6UL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "bch_podf", base + 0x78, 24);
361 clks[IMX6UL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "gpmi_podf", base + 0x78, 26);
362 clks[IMX6UL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc_podf", base + 0x78, 28);
363 clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30);
364
365 /* CCGR5 */
366 clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
367 clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
368 clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10);
369 clks[IMX6UL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
370 clks[IMX6UL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
371 clks[IMX6UL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
372 clks[IMX6UL_CLK_SAI3] = imx_clk_gate2_shared("sai3", "sai3_podf", base + 0x7c, 22, &share_count_sai3);
373 clks[IMX6UL_CLK_SAI3_IPG] = imx_clk_gate2_shared("sai3_ipg", "ipg", base + 0x7c, 22, &share_count_sai3);
374 clks[IMX6UL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24);
375 clks[IMX6UL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24);
376 clks[IMX6UL_CLK_UART7_IPG] = imx_clk_gate2("uart7_ipg", "ipg", base + 0x7c, 26);
377 clks[IMX6UL_CLK_UART7_SERIAL] = imx_clk_gate2("uart7_serial", "uart_podf", base + 0x7c, 26);
378 clks[IMX6UL_CLK_SAI1] = imx_clk_gate2_shared("sai1", "sai1_podf", base + 0x7c, 28, &share_count_sai1);
379 clks[IMX6UL_CLK_SAI1_IPG] = imx_clk_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1);
380 clks[IMX6UL_CLK_SAI2] = imx_clk_gate2_shared("sai2", "sai2_podf", base + 0x7c, 30, &share_count_sai2);
381 clks[IMX6UL_CLK_SAI2_IPG] = imx_clk_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2);
382
383 /* CCGR6 */
384 clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
385 clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
386 clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
387 clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6);
388 clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8);
389 clks[IMX6UL_CLK_EIM] = imx_clk_gate2("eim", "eim_slow_podf", base + 0x80, 10);
390 clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16);
391 clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14);
392 clks[IMX6UL_CLK_UART8_SERIAL] = imx_clk_gate2("uart8_serial", "uart_podf", base + 0x80, 14);
393 clks[IMX6UL_CLK_WDOG3] = imx_clk_gate2("wdog3", "ipg", base + 0x80, 20);
394 clks[IMX6UL_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24);
395 clks[IMX6UL_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26);
396 clks[IMX6UL_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28);
397 clks[IMX6UL_CLK_PWM7] = imx_clk_gate2("Pwm7", "perclk", base + 0x80, 30);
398
399 /* mask handshake of mmdc */
400 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
401
402 for (i = 0; i < ARRAY_SIZE(clks); i++)
403 if (IS_ERR(clks[i]))
404 pr_err("i.MX6UL clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
405
406 clk_data.clks = clks;
407 clk_data.clk_num = ARRAY_SIZE(clks);
408 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
409
410 /* set perclk to from OSC */
411 clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]);
412
413 clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000);
414 clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);
415 clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000);
416
417 /* keep all the clks on just for bringup */
418 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
419 clk_prepare_enable(clks[clks_init_on[i]]);
420
421 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
422 clk_prepare_enable(clks[IMX6UL_CLK_USBPHY1_GATE]);
423 clk_prepare_enable(clks[IMX6UL_CLK_USBPHY2_GATE]);
424 }
425
426 clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]);
427 clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
428
429 clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]);
430}
431
432CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init);
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
new file mode 100644
index 000000000000..c343894ce603
--- /dev/null
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -0,0 +1,240 @@
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
11#define __DT_BINDINGS_CLOCK_IMX6UL_H
12
13#define IMX6UL_CLK_DUMMY 0
14#define IMX6UL_CLK_CKIL 1
15#define IMX6UL_CLK_CKIH 2
16#define IMX6UL_CLK_OSC 3
17#define IMX6UL_PLL1_BYPASS_SRC 4
18#define IMX6UL_PLL2_BYPASS_SRC 5
19#define IMX6UL_PLL3_BYPASS_SRC 6
20#define IMX6UL_PLL4_BYPASS_SRC 7
21#define IMX6UL_PLL5_BYPASS_SRC 8
22#define IMX6UL_PLL6_BYPASS_SRC 9
23#define IMX6UL_PLL7_BYPASS_SRC 10
24#define IMX6UL_CLK_PLL1 11
25#define IMX6UL_CLK_PLL2 12
26#define IMX6UL_CLK_PLL3 13
27#define IMX6UL_CLK_PLL4 14
28#define IMX6UL_CLK_PLL5 15
29#define IMX6UL_CLK_PLL6 16
30#define IMX6UL_CLK_PLL7 17
31#define IMX6UL_PLL1_BYPASS 18
32#define IMX6UL_PLL2_BYPASS 19
33#define IMX6UL_PLL3_BYPASS 20
34#define IMX6UL_PLL4_BYPASS 21
35#define IMX6UL_PLL5_BYPASS 22
36#define IMX6UL_PLL6_BYPASS 23
37#define IMX6UL_PLL7_BYPASS 24
38#define IMX6UL_CLK_PLL1_SYS 25
39#define IMX6UL_CLK_PLL2_BUS 26
40#define IMX6UL_CLK_PLL3_USB_OTG 27
41#define IMX6UL_CLK_PLL4_AUDIO 28
42#define IMX6UL_CLK_PLL5_VIDEO 29
43#define IMX6UL_CLK_PLL6_ENET 30
44#define IMX6UL_CLK_PLL7_USB_HOST 31
45#define IMX6UL_CLK_USBPHY1 32
46#define IMX6UL_CLK_USBPHY2 33
47#define IMX6UL_CLK_USBPHY1_GATE 34
48#define IMX6UL_CLK_USBPHY2_GATE 35
49#define IMX6UL_CLK_PLL2_PFD0 36
50#define IMX6UL_CLK_PLL2_PFD1 37
51#define IMX6UL_CLK_PLL2_PFD2 38
52#define IMX6UL_CLK_PLL2_PFD3 39
53#define IMX6UL_CLK_PLL3_PFD0 40
54#define IMX6UL_CLK_PLL3_PFD1 41
55#define IMX6UL_CLK_PLL3_PFD2 42
56#define IMX6UL_CLK_PLL3_PFD3 43
57#define IMX6UL_CLK_ENET_REF 44
58#define IMX6UL_CLK_ENET2_REF 45
59#define IMX6UL_CLK_ENET2_REF_125M 46
60#define IMX6UL_CLK_ENET_PTP_REF 47
61#define IMX6UL_CLK_ENET_PTP 48
62#define IMX6UL_CLK_PLL4_POST_DIV 49
63#define IMX6UL_CLK_PLL4_AUDIO_DIV 50
64#define IMX6UL_CLK_PLL5_POST_DIV 51
65#define IMX6UL_CLK_PLL5_VIDEO_DIV 52
66#define IMX6UL_CLK_PLL2_198M 53
67#define IMX6UL_CLK_PLL3_80M 54
68#define IMX6UL_CLK_PLL3_60M 55
69#define IMX6UL_CLK_STEP 56
70#define IMX6UL_CLK_PLL1_SW 57
71#define IMX6UL_CLK_AXI_ALT_SEL 58
72#define IMX6UL_CLK_AXI_SEL 59
73#define IMX6UL_CLK_PERIPH_PRE 60
74#define IMX6UL_CLK_PERIPH2_PRE 61
75#define IMX6UL_CLK_PERIPH_CLK2_SEL 62
76#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63
77#define IMX6UL_CLK_USDHC1_SEL 64
78#define IMX6UL_CLK_USDHC2_SEL 65
79#define IMX6UL_CLK_BCH_SEL 66
80#define IMX6UL_CLK_GPMI_SEL 67
81#define IMX6UL_CLK_EIM_SLOW_SEL 68
82#define IMX6UL_CLK_SPDIF_SEL 69
83#define IMX6UL_CLK_SAI1_SEL 70
84#define IMX6UL_CLK_SAI2_SEL 71
85#define IMX6UL_CLK_SAI3_SEL 72
86#define IMX6UL_CLK_LCDIF_PRE_SEL 73
87#define IMX6UL_CLK_SIM_PRE_SEL 74
88#define IMX6UL_CLK_LDB_DI0_SEL 75
89#define IMX6UL_CLK_LDB_DI1_SEL 76
90#define IMX6UL_CLK_ENFC_SEL 77
91#define IMX6UL_CLK_CAN_SEL 78
92#define IMX6UL_CLK_ECSPI_SEL 79
93#define IMX6UL_CLK_UART_SEL 80
94#define IMX6UL_CLK_QSPI1_SEL 81
95#define IMX6UL_CLK_PERCLK_SEL 82
96#define IMX6UL_CLK_LCDIF_SEL 83
97#define IMX6UL_CLK_SIM_SEL 84
98#define IMX6UL_CLK_PERIPH 85
99#define IMX6UL_CLK_PERIPH2 86
100#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87
101#define IMX6UL_CLK_LDB_DI0_DIV_7 88
102#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89
103#define IMX6UL_CLK_LDB_DI1_DIV_7 90
104#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91
105#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
106#define IMX6UL_CLK_ARM 93
107#define IMX6UL_CLK_PERIPH_CLK2 94
108#define IMX6UL_CLK_PERIPH2_CLK2 95
109#define IMX6UL_CLK_AHB 96
110#define IMX6UL_CLK_MMDC_PODF 97
111#define IMX6UL_CLK_AXI_PODF 98
112#define IMX6UL_CLK_PERCLK 99
113#define IMX6UL_CLK_IPG 100
114#define IMX6UL_CLK_USDHC1_PODF 101
115#define IMX6UL_CLK_USDHC2_PODF 102
116#define IMX6UL_CLK_BCH_PODF 103
117#define IMX6UL_CLK_GPMI_PODF 104
118#define IMX6UL_CLK_EIM_SLOW_PODF 105
119#define IMX6UL_CLK_SPDIF_PRED 106
120#define IMX6UL_CLK_SPDIF_PODF 107
121#define IMX6UL_CLK_SAI1_PRED 108
122#define IMX6UL_CLK_SAI1_PODF 109
123#define IMX6UL_CLK_SAI2_PRED 110
124#define IMX6UL_CLK_SAI2_PODF 111
125#define IMX6UL_CLK_SAI3_PRED 112
126#define IMX6UL_CLK_SAI3_PODF 113
127#define IMX6UL_CLK_LCDIF_PRED 114
128#define IMX6UL_CLK_LCDIF_PODF 115
129#define IMX6UL_CLK_SIM_PODF 116
130#define IMX6UL_CLK_QSPI1_PDOF 117
131#define IMX6UL_CLK_ENFC_PRED 118
132#define IMX6UL_CLK_ENFC_PODF 119
133#define IMX6UL_CLK_CAN_PODF 120
134#define IMX6UL_CLK_ECSPI_PODF 121
135#define IMX6UL_CLK_UART_PODF 122
136#define IMX6UL_CLK_ADC1 123
137#define IMX6UL_CLK_ADC2 124
138#define IMX6UL_CLK_AIPSTZ1 125
139#define IMX6UL_CLK_AIPSTZ2 126
140#define IMX6UL_CLK_AIPSTZ3 127
141#define IMX6UL_CLK_APBHDMA 128
142#define IMX6UL_CLK_ASRC_IPG 129
143#define IMX6UL_CLK_ASRC_MEM 130
144#define IMX6UL_CLK_GPMI_BCH_APB 131
145#define IMX6UL_CLK_GPMI_BCH 132
146#define IMX6UL_CLK_GPMI_IO 133
147#define IMX6UL_CLK_GPMI_APB 134
148#define IMX6UL_CLK_CAAM_MEM 135
149#define IMX6UL_CLK_CAAM_ACLK 136
150#define IMX6UL_CLK_CAAM_IPG 137
151#define IMX6UL_CLK_CSI 138
152#define IMX6UL_CLK_ECSPI1 139
153#define IMX6UL_CLK_ECSPI2 140
154#define IMX6UL_CLK_ECSPI3 141
155#define IMX6UL_CLK_ECSPI4 142
156#define IMX6UL_CLK_EIM 143
157#define IMX6UL_CLK_ENET 144
158#define IMX6UL_CLK_ENET_AHB 145
159#define IMX6UL_CLK_EPIT1 146
160#define IMX6UL_CLK_EPIT2 147
161#define IMX6UL_CLK_CAN1_IPG 148
162#define IMX6UL_CLK_CAN1_SERIAL 149
163#define IMX6UL_CLK_CAN2_IPG 150
164#define IMX6UL_CLK_CAN2_SERIAL 151
165#define IMX6UL_CLK_GPT1_BUS 152
166#define IMX6UL_CLK_GPT1_SERIAL 153
167#define IMX6UL_CLK_GPT2_BUS 154
168#define IMX6UL_CLK_GPT2_SERIAL 155
169#define IMX6UL_CLK_I2C1 156
170#define IMX6UL_CLK_I2C2 157
171#define IMX6UL_CLK_I2C3 158
172#define IMX6UL_CLK_I2C4 159
173#define IMX6UL_CLK_IOMUXC 160
174#define IMX6UL_CLK_LCDIF_APB 161
175#define IMX6UL_CLK_LCDIF_PIX 162
176#define IMX6UL_CLK_MMDC_P0_FAST 163
177#define IMX6UL_CLK_MMDC_P0_IPG 164
178#define IMX6UL_CLK_OCOTP 165
179#define IMX6UL_CLK_OCRAM 166
180#define IMX6UL_CLK_PWM1 167
181#define IMX6UL_CLK_PWM2 168
182#define IMX6UL_CLK_PWM3 169
183#define IMX6UL_CLK_PWM4 170
184#define IMX6UL_CLK_PWM5 171
185#define IMX6UL_CLK_PWM6 172
186#define IMX6UL_CLK_PWM7 173
187#define IMX6UL_CLK_PWM8 174
188#define IMX6UL_CLK_PXP 175
189#define IMX6UL_CLK_QSPI 176
190#define IMX6UL_CLK_ROM 177
191#define IMX6UL_CLK_SAI1 178
192#define IMX6UL_CLK_SAI1_IPG 179
193#define IMX6UL_CLK_SAI2 180
194#define IMX6UL_CLK_SAI2_IPG 181
195#define IMX6UL_CLK_SAI3 182
196#define IMX6UL_CLK_SAI3_IPG 183
197#define IMX6UL_CLK_SDMA 184
198#define IMX6UL_CLK_SIM 185
199#define IMX6UL_CLK_SIM_S 186
200#define IMX6UL_CLK_SPBA 187
201#define IMX6UL_CLK_SPDIF 188
202#define IMX6UL_CLK_UART1_IPG 189
203#define IMX6UL_CLK_UART1_SERIAL 190
204#define IMX6UL_CLK_UART2_IPG 191
205#define IMX6UL_CLK_UART2_SERIAL 192
206#define IMX6UL_CLK_UART3_IPG 193
207#define IMX6UL_CLK_UART3_SERIAL 194
208#define IMX6UL_CLK_UART4_IPG 195
209#define IMX6UL_CLK_UART4_SERIAL 196
210#define IMX6UL_CLK_UART5_IPG 197
211#define IMX6UL_CLK_UART5_SERIAL 198
212#define IMX6UL_CLK_UART6_IPG 199
213#define IMX6UL_CLK_UART6_SERIAL 200
214#define IMX6UL_CLK_UART7_IPG 201
215#define IMX6UL_CLK_UART7_SERIAL 202
216#define IMX6UL_CLK_UART8_IPG 203
217#define IMX6UL_CLK_UART8_SERIAL 204
218#define IMX6UL_CLK_USBOH3 205
219#define IMX6UL_CLK_USDHC1 206
220#define IMX6UL_CLK_USDHC2 207
221#define IMX6UL_CLK_WDOG1 208
222#define IMX6UL_CLK_WDOG2 209
223#define IMX6UL_CLK_WDOG3 210
224#define IMX6UL_CLK_LDB_DI0 211
225#define IMX6UL_CLK_AXI 212
226#define IMX6UL_CLK_SPDIF_GCLK 213
227#define IMX6UL_CLK_GPT_3M 214
228#define IMX6UL_CLK_SIM2 215
229#define IMX6UL_CLK_SIM1 216
230#define IMX6UL_CLK_IPP_DI0 217
231#define IMX6UL_CLK_IPP_DI1 218
232#define IMX6UL_CA7_SECONDARY_SEL 219
233#define IMX6UL_CLK_PER_BCH 220
234#define IMX6UL_CLK_CSI_SEL 221
235#define IMX6UL_CLK_CSI_PODF 222
236#define IMX6UL_CLK_PLL3_120M 223
237
238#define IMX6UL_CLK_END 224
239
240#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 17:14:24 -0400