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authorChristian König <christian.koenig@amd.com>2015-11-30 07:26:07 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-02-10 14:17:04 -0500
commitb07c9d2a73f4b956ee141005e7dfbada4e51c52c (patch)
tree862dad43a0ae4ed8a39149430894fdf6eb2071ef
parent599f434817c5cdf1af9fd9e7d4bef69bd0c02796 (diff)
drm/amdgpu: move more logic into amdgpu_vm_map_gart v3
No need to duplicate that code over and over again. Also stop using the flags to determine if we need to map the addresses. v2: constify the pages_addr v3: rebased, fix typo in commit message Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c36
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c11
5 files changed, 33 insertions, 42 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 532e0a17dd9a..1529e0aecb83 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -283,7 +283,7 @@ struct amdgpu_vm_pte_funcs {
283 unsigned count); 283 unsigned count);
284 /* write pte one entry at a time with addr mapping */ 284 /* write pte one entry at a time with addr mapping */
285 void (*write_pte)(struct amdgpu_ib *ib, 285 void (*write_pte)(struct amdgpu_ib *ib,
286 uint64_t pe, 286 const dma_addr_t *pages_addr, uint64_t pe,
287 uint64_t addr, unsigned count, 287 uint64_t addr, unsigned count,
288 uint32_t incr, uint32_t flags); 288 uint32_t incr, uint32_t flags);
289 /* for linear pte/pde updates without addr mapping */ 289 /* for linear pte/pde updates without addr mapping */
@@ -962,7 +962,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
962void amdgpu_vm_flush(struct amdgpu_ring *ring, 962void amdgpu_vm_flush(struct amdgpu_ring *ring,
963 struct amdgpu_vm *vm, 963 struct amdgpu_vm *vm,
964 struct fence *updates); 964 struct fence *updates);
965uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 965uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
966int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 966int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
967 struct amdgpu_vm *vm); 967 struct amdgpu_vm *vm);
968int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 968int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
@@ -2198,7 +2198,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2198#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2198#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2199#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2199#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2200#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2200#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2201#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2201#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
2202#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2202#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2203#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2203#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2204#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2204#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dfbcc64ef9fa..ae3b275f2a38 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -299,9 +299,14 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
299 uint64_t src = adev->gart.table_addr + (addr >> 12) * 8; 299 uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
300 amdgpu_vm_copy_pte(adev, ib, pe, src, count); 300 amdgpu_vm_copy_pte(adev, ib, pe, src, count);
301 301
302 } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) { 302 } else if (flags & AMDGPU_PTE_SYSTEM) {
303 amdgpu_vm_write_pte(adev, ib, pe, addr, 303 dma_addr_t *pages_addr = adev->gart.pages_addr;
304 count, incr, flags); 304 amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr,
305 count, incr, flags);
306
307 } else if (count < 3) {
308 amdgpu_vm_write_pte(adev, ib, NULL, pe, addr,
309 count, incr, flags);
305 310
306 } else { 311 } else {
307 amdgpu_vm_set_pte_pde(adev, ib, pe, addr, 312 amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
@@ -378,24 +383,31 @@ error:
378} 383}
379 384
380/** 385/**
381 * amdgpu_vm_map_gart - get the physical address of a gart page 386 * amdgpu_vm_map_gart - Resolve gart mapping of addr
382 * 387 *
383 * @adev: amdgpu_device pointer 388 * @pages_addr: optional DMA address to use for lookup
384 * @addr: the unmapped addr 389 * @addr: the unmapped addr
385 * 390 *
386 * Look up the physical address of the page that the pte resolves 391 * Look up the physical address of the page that the pte resolves
387 * to (cayman+). 392 * to and return the pointer for the page table entry.
388 * Returns the physical address of the page.
389 */ 393 */
390uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr) 394uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
391{ 395{
392 uint64_t result; 396 uint64_t result;
393 397
394 /* page table offset */ 398 if (pages_addr) {
395 result = adev->gart.pages_addr[addr >> PAGE_SHIFT]; 399 /* page table offset */
400 result = pages_addr[addr >> PAGE_SHIFT];
401
402 /* in case cpu page size != gpu page size*/
403 result |= addr & (~PAGE_MASK);
404
405 } else {
406 /* No mapping required */
407 result = addr;
408 }
396 409
397 /* in case cpu page size != gpu page size*/ 410 result &= 0xFFFFFFFFFFFFF000ULL;
398 result |= addr & (~PAGE_MASK);
399 411
400 return result; 412 return result;
401} 413}
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index e8a48ae8d360..abfa3f2f15fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -714,7 +714,7 @@ static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
714 * Update PTEs by writing them manually using sDMA (CIK). 714 * Update PTEs by writing them manually using sDMA (CIK).
715 */ 715 */
716static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, 716static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
717 uint64_t pe, 717 const dma_addr_t *pages_addr, uint64_t pe,
718 uint64_t addr, unsigned count, 718 uint64_t addr, unsigned count,
719 uint32_t incr, uint32_t flags) 719 uint32_t incr, uint32_t flags)
720{ 720{
@@ -733,14 +733,7 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
733 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 733 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
734 ib->ptr[ib->length_dw++] = ndw; 734 ib->ptr[ib->length_dw++] = ndw;
735 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 735 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
736 if (flags & AMDGPU_PTE_SYSTEM) { 736 value = amdgpu_vm_map_gart(pages_addr, addr);
737 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
738 value &= 0xFFFFFFFFFFFFF000ULL;
739 } else if (flags & AMDGPU_PTE_VALID) {
740 value = addr;
741 } else {
742 value = 0;
743 }
744 addr += incr; 737 addr += incr;
745 value |= flags; 738 value |= flags;
746 ib->ptr[ib->length_dw++] = value; 739 ib->ptr[ib->length_dw++] = value;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 9fae4bf1a6c6..750231d06aa0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -772,7 +772,7 @@ static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
772 * Update PTEs by writing them manually using sDMA (CIK). 772 * Update PTEs by writing them manually using sDMA (CIK).
773 */ 773 */
774static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, 774static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
775 uint64_t pe, 775 const dma_addr_t *pages_addr, uint64_t pe,
776 uint64_t addr, unsigned count, 776 uint64_t addr, unsigned count,
777 uint32_t incr, uint32_t flags) 777 uint32_t incr, uint32_t flags)
778{ 778{
@@ -791,14 +791,7 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
791 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 791 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
792 ib->ptr[ib->length_dw++] = ndw; 792 ib->ptr[ib->length_dw++] = ndw;
793 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 793 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
794 if (flags & AMDGPU_PTE_SYSTEM) { 794 value = amdgpu_vm_map_gart(pages_addr, addr);
795 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
796 value &= 0xFFFFFFFFFFFFF000ULL;
797 } else if (flags & AMDGPU_PTE_VALID) {
798 value = addr;
799 } else {
800 value = 0;
801 }
802 addr += incr; 795 addr += incr;
803 value |= flags; 796 value |= flags;
804 ib->ptr[ib->length_dw++] = value; 797 ib->ptr[ib->length_dw++] = value;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index b2fbf96dad7a..7af4b57ad3d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -922,7 +922,7 @@ static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
922 * Update PTEs by writing them manually using sDMA (CIK). 922 * Update PTEs by writing them manually using sDMA (CIK).
923 */ 923 */
924static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, 924static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
925 uint64_t pe, 925 const dma_addr_t *pages_addr, uint64_t pe,
926 uint64_t addr, unsigned count, 926 uint64_t addr, unsigned count,
927 uint32_t incr, uint32_t flags) 927 uint32_t incr, uint32_t flags)
928{ 928{
@@ -941,14 +941,7 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
941 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 941 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
942 ib->ptr[ib->length_dw++] = ndw; 942 ib->ptr[ib->length_dw++] = ndw;
943 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 943 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
944 if (flags & AMDGPU_PTE_SYSTEM) { 944 value = amdgpu_vm_map_gart(pages_addr, addr);
945 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
946 value &= 0xFFFFFFFFFFFFF000ULL;
947 } else if (flags & AMDGPU_PTE_VALID) {
948 value = addr;
949 } else {
950 value = 0;
951 }
952 addr += incr; 945 addr += incr;
953 value |= flags; 946 value |= flags;
954 ib->ptr[ib->length_dw++] = value; 947 ib->ptr[ib->length_dw++] = value;