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authorTony Lindgren <tony@atomide.com>2013-11-25 18:17:12 -0500
committerTony Lindgren <tony@atomide.com>2013-11-25 18:31:18 -0500
commitb05ef2159dd373034332151ff7341d0231fae799 (patch)
tree1c3e26e6de18df2d1ece400428b8dda543d193b6
parentd6db0e7fa1de9559e09c141367740ecd97eb2fe6 (diff)
ARM: OMAP2+: Remove legacy hwmod entries for omap2
These now come from device tree except for DSS and DMA that still uses hwmod to initialize. That will get fixed when we DSS gets device tree bindings and we move completely to the dmaengine API. Cc: Paul Walmsley <paul@pwsan.com> [tony@atomide.com: updated to add trailing commas to structs] Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c137
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c266
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c165
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c72
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h5
5 files changed, 7 insertions, 638 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index d8b9d60f854f..2f15979c2e9c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -108,8 +108,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
108/* I2C1 */ 108/* I2C1 */
109static struct omap_hwmod omap2420_i2c1_hwmod = { 109static struct omap_hwmod omap2420_i2c1_hwmod = {
110 .name = "i2c1", 110 .name = "i2c1",
111 .mpu_irqs = omap2_i2c1_mpu_irqs,
112 .sdma_reqs = omap2_i2c1_sdma_reqs,
113 .main_clk = "i2c1_fck", 111 .main_clk = "i2c1_fck",
114 .prcm = { 112 .prcm = {
115 .omap2 = { 113 .omap2 = {
@@ -133,8 +131,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
133/* I2C2 */ 131/* I2C2 */
134static struct omap_hwmod omap2420_i2c2_hwmod = { 132static struct omap_hwmod omap2420_i2c2_hwmod = {
135 .name = "i2c2", 133 .name = "i2c2",
136 .mpu_irqs = omap2_i2c2_mpu_irqs,
137 .sdma_reqs = omap2_i2c2_sdma_reqs,
138 .main_clk = "i2c2_fck", 134 .main_clk = "i2c2_fck",
139 .prcm = { 135 .prcm = {
140 .omap2 = { 136 .omap2 = {
@@ -179,16 +175,9 @@ static struct omap_mbox_pdata omap2420_mailbox_attrs = {
179 .info = omap2420_mailbox_info, 175 .info = omap2420_mailbox_info,
180}; 176};
181 177
182static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
183 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
184 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
185 { .irq = -1 },
186};
187
188static struct omap_hwmod omap2420_mailbox_hwmod = { 178static struct omap_hwmod omap2420_mailbox_hwmod = {
189 .name = "mailbox", 179 .name = "mailbox",
190 .class = &omap2xxx_mailbox_hwmod_class, 180 .class = &omap2xxx_mailbox_hwmod_class,
191 .mpu_irqs = omap2420_mailbox_irqs,
192 .main_clk = "mailboxes_ick", 181 .main_clk = "mailboxes_ick",
193 .prcm = { 182 .prcm = {
194 .omap2 = { 183 .omap2 = {
@@ -217,17 +206,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
217}; 206};
218 207
219/* mcbsp1 */ 208/* mcbsp1 */
220static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
221 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
222 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
223 { .irq = -1 },
224};
225
226static struct omap_hwmod omap2420_mcbsp1_hwmod = { 209static struct omap_hwmod omap2420_mcbsp1_hwmod = {
227 .name = "mcbsp1", 210 .name = "mcbsp1",
228 .class = &omap2420_mcbsp_hwmod_class, 211 .class = &omap2420_mcbsp_hwmod_class,
229 .mpu_irqs = omap2420_mcbsp1_irqs,
230 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
231 .main_clk = "mcbsp1_fck", 212 .main_clk = "mcbsp1_fck",
232 .prcm = { 213 .prcm = {
233 .omap2 = { 214 .omap2 = {
@@ -243,17 +224,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
243}; 224};
244 225
245/* mcbsp2 */ 226/* mcbsp2 */
246static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
247 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
248 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
249 { .irq = -1 },
250};
251
252static struct omap_hwmod omap2420_mcbsp2_hwmod = { 227static struct omap_hwmod omap2420_mcbsp2_hwmod = {
253 .name = "mcbsp2", 228 .name = "mcbsp2",
254 .class = &omap2420_mcbsp_hwmod_class, 229 .class = &omap2420_mcbsp_hwmod_class,
255 .mpu_irqs = omap2420_mcbsp2_irqs,
256 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
257 .main_clk = "mcbsp2_fck", 230 .main_clk = "mcbsp2_fck",
258 .prcm = { 231 .prcm = {
259 .omap2 = { 232 .omap2 = {
@@ -283,22 +256,9 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
283}; 256};
284 257
285/* msdi1 */ 258/* msdi1 */
286static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
287 { .irq = 83 + OMAP_INTC_START, },
288 { .irq = -1 },
289};
290
291static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
292 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
293 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
294 { .dma_req = -1 }
295};
296
297static struct omap_hwmod omap2420_msdi1_hwmod = { 259static struct omap_hwmod omap2420_msdi1_hwmod = {
298 .name = "msdi1", 260 .name = "msdi1",
299 .class = &omap2420_msdi_hwmod_class, 261 .class = &omap2420_msdi_hwmod_class,
300 .mpu_irqs = omap2420_msdi1_irqs,
301 .sdma_reqs = omap2420_msdi1_sdma_reqs,
302 .main_clk = "mmc_fck", 262 .main_clk = "mmc_fck",
303 .prcm = { 263 .prcm = {
304 .omap2 = { 264 .omap2 = {
@@ -315,7 +275,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = {
315/* HDQ1W/1-wire */ 275/* HDQ1W/1-wire */
316static struct omap_hwmod omap2420_hdq1w_hwmod = { 276static struct omap_hwmod omap2420_hdq1w_hwmod = {
317 .name = "hdq1w", 277 .name = "hdq1w",
318 .mpu_irqs = omap2_hdq1w_mpu_irqs,
319 .main_clk = "hdq_fck", 278 .main_clk = "hdq_fck",
320 .prcm = { 279 .prcm = {
321 .omap2 = { 280 .omap2 = {
@@ -338,7 +297,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
338 .master = &omap2xxx_l4_core_hwmod, 297 .master = &omap2xxx_l4_core_hwmod,
339 .slave = &omap2420_i2c1_hwmod, 298 .slave = &omap2420_i2c1_hwmod,
340 .clk = "i2c1_ick", 299 .clk = "i2c1_ick",
341 .addr = omap2_i2c1_addr_space,
342 .user = OCP_USER_MPU | OCP_USER_SDMA, 300 .user = OCP_USER_MPU | OCP_USER_SDMA,
343}; 301};
344 302
@@ -347,7 +305,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
347 .master = &omap2xxx_l4_core_hwmod, 305 .master = &omap2xxx_l4_core_hwmod,
348 .slave = &omap2420_i2c2_hwmod, 306 .slave = &omap2420_i2c2_hwmod,
349 .clk = "i2c2_ick", 307 .clk = "i2c2_ick",
350 .addr = omap2_i2c2_addr_space,
351 .user = OCP_USER_MPU | OCP_USER_SDMA, 308 .user = OCP_USER_MPU | OCP_USER_SDMA,
352}; 309};
353 310
@@ -367,111 +324,51 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
367 .user = OCP_USER_MPU | OCP_USER_SDMA, 324 .user = OCP_USER_MPU | OCP_USER_SDMA,
368}; 325};
369 326
370static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
371 {
372 .pa_start = 0x48028000,
373 .pa_end = 0x48028000 + SZ_1K - 1,
374 .flags = ADDR_TYPE_RT
375 },
376 { }
377};
378
379/* l4_wkup -> timer1 */ 327/* l4_wkup -> timer1 */
380static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 328static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
381 .master = &omap2xxx_l4_wkup_hwmod, 329 .master = &omap2xxx_l4_wkup_hwmod,
382 .slave = &omap2xxx_timer1_hwmod, 330 .slave = &omap2xxx_timer1_hwmod,
383 .clk = "gpt1_ick", 331 .clk = "gpt1_ick",
384 .addr = omap2420_timer1_addrs,
385 .user = OCP_USER_MPU | OCP_USER_SDMA, 332 .user = OCP_USER_MPU | OCP_USER_SDMA,
386}; 333};
387 334
388/* l4_wkup -> wd_timer2 */ 335/* l4_wkup -> wd_timer2 */
389static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
390 {
391 .pa_start = 0x48022000,
392 .pa_end = 0x4802207f,
393 .flags = ADDR_TYPE_RT
394 },
395 { }
396};
397
398static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 336static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
399 .master = &omap2xxx_l4_wkup_hwmod, 337 .master = &omap2xxx_l4_wkup_hwmod,
400 .slave = &omap2xxx_wd_timer2_hwmod, 338 .slave = &omap2xxx_wd_timer2_hwmod,
401 .clk = "mpu_wdt_ick", 339 .clk = "mpu_wdt_ick",
402 .addr = omap2420_wd_timer2_addrs,
403 .user = OCP_USER_MPU | OCP_USER_SDMA, 340 .user = OCP_USER_MPU | OCP_USER_SDMA,
404}; 341};
405 342
406/* l4_wkup -> gpio1 */ 343/* l4_wkup -> gpio1 */
407static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
408 {
409 .pa_start = 0x48018000,
410 .pa_end = 0x480181ff,
411 .flags = ADDR_TYPE_RT
412 },
413 { }
414};
415
416static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 344static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
417 .master = &omap2xxx_l4_wkup_hwmod, 345 .master = &omap2xxx_l4_wkup_hwmod,
418 .slave = &omap2xxx_gpio1_hwmod, 346 .slave = &omap2xxx_gpio1_hwmod,
419 .clk = "gpios_ick", 347 .clk = "gpios_ick",
420 .addr = omap2420_gpio1_addr_space,
421 .user = OCP_USER_MPU | OCP_USER_SDMA, 348 .user = OCP_USER_MPU | OCP_USER_SDMA,
422}; 349};
423 350
424/* l4_wkup -> gpio2 */ 351/* l4_wkup -> gpio2 */
425static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
426 {
427 .pa_start = 0x4801a000,
428 .pa_end = 0x4801a1ff,
429 .flags = ADDR_TYPE_RT
430 },
431 { }
432};
433
434static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 352static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
435 .master = &omap2xxx_l4_wkup_hwmod, 353 .master = &omap2xxx_l4_wkup_hwmod,
436 .slave = &omap2xxx_gpio2_hwmod, 354 .slave = &omap2xxx_gpio2_hwmod,
437 .clk = "gpios_ick", 355 .clk = "gpios_ick",
438 .addr = omap2420_gpio2_addr_space,
439 .user = OCP_USER_MPU | OCP_USER_SDMA, 356 .user = OCP_USER_MPU | OCP_USER_SDMA,
440}; 357};
441 358
442/* l4_wkup -> gpio3 */ 359/* l4_wkup -> gpio3 */
443static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
444 {
445 .pa_start = 0x4801c000,
446 .pa_end = 0x4801c1ff,
447 .flags = ADDR_TYPE_RT
448 },
449 { }
450};
451
452static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 360static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
453 .master = &omap2xxx_l4_wkup_hwmod, 361 .master = &omap2xxx_l4_wkup_hwmod,
454 .slave = &omap2xxx_gpio3_hwmod, 362 .slave = &omap2xxx_gpio3_hwmod,
455 .clk = "gpios_ick", 363 .clk = "gpios_ick",
456 .addr = omap2420_gpio3_addr_space,
457 .user = OCP_USER_MPU | OCP_USER_SDMA, 364 .user = OCP_USER_MPU | OCP_USER_SDMA,
458}; 365};
459 366
460/* l4_wkup -> gpio4 */ 367/* l4_wkup -> gpio4 */
461static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
462 {
463 .pa_start = 0x4801e000,
464 .pa_end = 0x4801e1ff,
465 .flags = ADDR_TYPE_RT
466 },
467 { }
468};
469
470static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 368static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
471 .master = &omap2xxx_l4_wkup_hwmod, 369 .master = &omap2xxx_l4_wkup_hwmod,
472 .slave = &omap2xxx_gpio4_hwmod, 370 .slave = &omap2xxx_gpio4_hwmod,
473 .clk = "gpios_ick", 371 .clk = "gpios_ick",
474 .addr = omap2420_gpio4_addr_space,
475 .user = OCP_USER_MPU | OCP_USER_SDMA, 372 .user = OCP_USER_MPU | OCP_USER_SDMA,
476}; 373};
477 374
@@ -496,7 +393,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
496static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 393static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
497 .master = &omap2xxx_l4_core_hwmod, 394 .master = &omap2xxx_l4_core_hwmod,
498 .slave = &omap2420_mailbox_hwmod, 395 .slave = &omap2420_mailbox_hwmod,
499 .addr = omap2_mailbox_addrs,
500 .user = OCP_USER_MPU | OCP_USER_SDMA, 396 .user = OCP_USER_MPU | OCP_USER_SDMA,
501}; 397};
502 398
@@ -505,7 +401,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
505 .master = &omap2xxx_l4_core_hwmod, 401 .master = &omap2xxx_l4_core_hwmod,
506 .slave = &omap2420_mcbsp1_hwmod, 402 .slave = &omap2420_mcbsp1_hwmod,
507 .clk = "mcbsp1_ick", 403 .clk = "mcbsp1_ick",
508 .addr = omap2_mcbsp1_addrs,
509 .user = OCP_USER_MPU | OCP_USER_SDMA, 404 .user = OCP_USER_MPU | OCP_USER_SDMA,
510}; 405};
511 406
@@ -514,25 +409,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
514 .master = &omap2xxx_l4_core_hwmod, 409 .master = &omap2xxx_l4_core_hwmod,
515 .slave = &omap2420_mcbsp2_hwmod, 410 .slave = &omap2420_mcbsp2_hwmod,
516 .clk = "mcbsp2_ick", 411 .clk = "mcbsp2_ick",
517 .addr = omap2xxx_mcbsp2_addrs,
518 .user = OCP_USER_MPU | OCP_USER_SDMA, 412 .user = OCP_USER_MPU | OCP_USER_SDMA,
519}; 413};
520 414
521static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
522 {
523 .pa_start = 0x4809c000,
524 .pa_end = 0x4809c000 + SZ_128 - 1,
525 .flags = ADDR_TYPE_RT,
526 },
527 { }
528};
529
530/* l4_core -> msdi1 */ 415/* l4_core -> msdi1 */
531static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { 416static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
532 .master = &omap2xxx_l4_core_hwmod, 417 .master = &omap2xxx_l4_core_hwmod,
533 .slave = &omap2420_msdi1_hwmod, 418 .slave = &omap2420_msdi1_hwmod,
534 .clk = "mmc_ick", 419 .clk = "mmc_ick",
535 .addr = omap2420_msdi1_addrs,
536 .user = OCP_USER_MPU | OCP_USER_SDMA, 420 .user = OCP_USER_MPU | OCP_USER_SDMA,
537}; 421};
538 422
@@ -541,36 +425,16 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
541 .master = &omap2xxx_l4_core_hwmod, 425 .master = &omap2xxx_l4_core_hwmod,
542 .slave = &omap2420_hdq1w_hwmod, 426 .slave = &omap2420_hdq1w_hwmod,
543 .clk = "hdq_ick", 427 .clk = "hdq_ick",
544 .addr = omap2_hdq1w_addr_space,
545 .user = OCP_USER_MPU | OCP_USER_SDMA, 428 .user = OCP_USER_MPU | OCP_USER_SDMA,
546 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 429 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
547}; 430};
548 431
549 432
550/* l4_wkup -> 32ksync_counter */ 433/* l4_wkup -> 32ksync_counter */
551static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
552 {
553 .pa_start = 0x48004000,
554 .pa_end = 0x4800401f,
555 .flags = ADDR_TYPE_RT
556 },
557 { }
558};
559
560static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
561 {
562 .pa_start = 0x6800a000,
563 .pa_end = 0x6800afff,
564 .flags = ADDR_TYPE_RT
565 },
566 { }
567};
568
569static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { 434static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
570 .master = &omap2xxx_l4_wkup_hwmod, 435 .master = &omap2xxx_l4_wkup_hwmod,
571 .slave = &omap2xxx_counter_32k_hwmod, 436 .slave = &omap2xxx_counter_32k_hwmod,
572 .clk = "sync_32k_ick", 437 .clk = "sync_32k_ick",
573 .addr = omap2420_counter_32k_addrs,
574 .user = OCP_USER_MPU | OCP_USER_SDMA, 438 .user = OCP_USER_MPU | OCP_USER_SDMA,
575}; 439};
576 440
@@ -578,7 +442,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
578 .master = &omap2xxx_l3_main_hwmod, 442 .master = &omap2xxx_l3_main_hwmod,
579 .slave = &omap2xxx_gpmc_hwmod, 443 .slave = &omap2xxx_gpmc_hwmod,
580 .clk = "core_l3_ck", 444 .clk = "core_l3_ck",
581 .addr = omap2420_gpmc_addrs,
582 .user = OCP_USER_MPU | OCP_USER_SDMA, 445 .user = OCP_USER_MPU | OCP_USER_SDMA,
583}; 446};
584 447
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 5b9083461dc5..6d1b60902179 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -86,8 +86,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
86static struct omap_hwmod omap2430_i2c1_hwmod = { 86static struct omap_hwmod omap2430_i2c1_hwmod = {
87 .name = "i2c1", 87 .name = "i2c1",
88 .flags = HWMOD_16BIT_REG, 88 .flags = HWMOD_16BIT_REG,
89 .mpu_irqs = omap2_i2c1_mpu_irqs,
90 .sdma_reqs = omap2_i2c1_sdma_reqs,
91 .main_clk = "i2chs1_fck", 89 .main_clk = "i2chs1_fck",
92 .prcm = { 90 .prcm = {
93 .omap2 = { 91 .omap2 = {
@@ -114,8 +112,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
114static struct omap_hwmod omap2430_i2c2_hwmod = { 112static struct omap_hwmod omap2430_i2c2_hwmod = {
115 .name = "i2c2", 113 .name = "i2c2",
116 .flags = HWMOD_16BIT_REG, 114 .flags = HWMOD_16BIT_REG,
117 .mpu_irqs = omap2_i2c2_mpu_irqs,
118 .sdma_reqs = omap2_i2c2_sdma_reqs,
119 .main_clk = "i2chs2_fck", 115 .main_clk = "i2chs2_fck",
120 .prcm = { 116 .prcm = {
121 .omap2 = { 117 .omap2 = {
@@ -131,15 +127,9 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
131}; 127};
132 128
133/* gpio5 */ 129/* gpio5 */
134static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
135 { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
136 { .irq = -1 },
137};
138
139static struct omap_hwmod omap2430_gpio5_hwmod = { 130static struct omap_hwmod omap2430_gpio5_hwmod = {
140 .name = "gpio5", 131 .name = "gpio5",
141 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 132 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
142 .mpu_irqs = omap243x_gpio5_irqs,
143 .main_clk = "gpio5_fck", 133 .main_clk = "gpio5_fck",
144 .prcm = { 134 .prcm = {
145 .omap2 = { 135 .omap2 = {
@@ -182,15 +172,9 @@ static struct omap_mbox_pdata omap2430_mailbox_attrs = {
182 .info = omap2430_mailbox_info, 172 .info = omap2430_mailbox_info,
183}; 173};
184 174
185static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
186 { .irq = 26 + OMAP_INTC_START, },
187 { .irq = -1 },
188};
189
190static struct omap_hwmod omap2430_mailbox_hwmod = { 175static struct omap_hwmod omap2430_mailbox_hwmod = {
191 .name = "mailbox", 176 .name = "mailbox",
192 .class = &omap2xxx_mailbox_hwmod_class, 177 .class = &omap2xxx_mailbox_hwmod_class,
193 .mpu_irqs = omap2430_mailbox_irqs,
194 .main_clk = "mailboxes_ick", 178 .main_clk = "mailboxes_ick",
195 .prcm = { 179 .prcm = {
196 .omap2 = { 180 .omap2 = {
@@ -205,27 +189,12 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
205}; 189};
206 190
207/* mcspi3 */ 191/* mcspi3 */
208static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
209 { .irq = 91 + OMAP_INTC_START, },
210 { .irq = -1 },
211};
212
213static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
214 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
215 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
216 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
217 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
218 { .dma_req = -1 }
219};
220
221static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 192static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
222 .num_chipselect = 2, 193 .num_chipselect = 2,
223}; 194};
224 195
225static struct omap_hwmod omap2430_mcspi3_hwmod = { 196static struct omap_hwmod omap2430_mcspi3_hwmod = {
226 .name = "mcspi3", 197 .name = "mcspi3",
227 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
228 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
229 .main_clk = "mcspi3_fck", 198 .main_clk = "mcspi3_fck",
230 .prcm = { 199 .prcm = {
231 .omap2 = { 200 .omap2 = {
@@ -259,16 +228,8 @@ static struct omap_hwmod_class usbotg_class = {
259}; 228};
260 229
261/* usb_otg_hs */ 230/* usb_otg_hs */
262static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
263
264 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
265 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
266 { .irq = -1 },
267};
268
269static struct omap_hwmod omap2430_usbhsotg_hwmod = { 231static struct omap_hwmod omap2430_usbhsotg_hwmod = {
270 .name = "usb_otg_hs", 232 .name = "usb_otg_hs",
271 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
272 .main_clk = "usbhs_ick", 233 .main_clk = "usbhs_ick",
273 .prcm = { 234 .prcm = {
274 .omap2 = { 235 .omap2 = {
@@ -313,19 +274,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
313}; 274};
314 275
315/* mcbsp1 */ 276/* mcbsp1 */
316static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
317 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
318 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
319 { .name = "ovr", .irq = 61 + OMAP_INTC_START, },
320 { .name = "common", .irq = 64 + OMAP_INTC_START, },
321 { .irq = -1 },
322};
323
324static struct omap_hwmod omap2430_mcbsp1_hwmod = { 277static struct omap_hwmod omap2430_mcbsp1_hwmod = {
325 .name = "mcbsp1", 278 .name = "mcbsp1",
326 .class = &omap2430_mcbsp_hwmod_class, 279 .class = &omap2430_mcbsp_hwmod_class,
327 .mpu_irqs = omap2430_mcbsp1_irqs,
328 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
329 .main_clk = "mcbsp1_fck", 280 .main_clk = "mcbsp1_fck",
330 .prcm = { 281 .prcm = {
331 .omap2 = { 282 .omap2 = {
@@ -341,18 +292,9 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
341}; 292};
342 293
343/* mcbsp2 */ 294/* mcbsp2 */
344static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
345 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
346 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
347 { .name = "common", .irq = 16 + OMAP_INTC_START, },
348 { .irq = -1 },
349};
350
351static struct omap_hwmod omap2430_mcbsp2_hwmod = { 295static struct omap_hwmod omap2430_mcbsp2_hwmod = {
352 .name = "mcbsp2", 296 .name = "mcbsp2",
353 .class = &omap2430_mcbsp_hwmod_class, 297 .class = &omap2430_mcbsp_hwmod_class,
354 .mpu_irqs = omap2430_mcbsp2_irqs,
355 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
356 .main_clk = "mcbsp2_fck", 298 .main_clk = "mcbsp2_fck",
357 .prcm = { 299 .prcm = {
358 .omap2 = { 300 .omap2 = {
@@ -368,18 +310,9 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
368}; 310};
369 311
370/* mcbsp3 */ 312/* mcbsp3 */
371static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
372 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
373 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
374 { .name = "common", .irq = 17 + OMAP_INTC_START, },
375 { .irq = -1 },
376};
377
378static struct omap_hwmod omap2430_mcbsp3_hwmod = { 313static struct omap_hwmod omap2430_mcbsp3_hwmod = {
379 .name = "mcbsp3", 314 .name = "mcbsp3",
380 .class = &omap2430_mcbsp_hwmod_class, 315 .class = &omap2430_mcbsp_hwmod_class,
381 .mpu_irqs = omap2430_mcbsp3_irqs,
382 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
383 .main_clk = "mcbsp3_fck", 316 .main_clk = "mcbsp3_fck",
384 .prcm = { 317 .prcm = {
385 .omap2 = { 318 .omap2 = {
@@ -395,24 +328,9 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
395}; 328};
396 329
397/* mcbsp4 */ 330/* mcbsp4 */
398static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
399 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
400 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
401 { .name = "common", .irq = 18 + OMAP_INTC_START, },
402 { .irq = -1 },
403};
404
405static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
406 { .name = "rx", .dma_req = 20 },
407 { .name = "tx", .dma_req = 19 },
408 { .dma_req = -1 }
409};
410
411static struct omap_hwmod omap2430_mcbsp4_hwmod = { 331static struct omap_hwmod omap2430_mcbsp4_hwmod = {
412 .name = "mcbsp4", 332 .name = "mcbsp4",
413 .class = &omap2430_mcbsp_hwmod_class, 333 .class = &omap2430_mcbsp_hwmod_class,
414 .mpu_irqs = omap2430_mcbsp4_irqs,
415 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
416 .main_clk = "mcbsp4_fck", 334 .main_clk = "mcbsp4_fck",
417 .prcm = { 335 .prcm = {
418 .omap2 = { 336 .omap2 = {
@@ -428,24 +346,9 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
428}; 346};
429 347
430/* mcbsp5 */ 348/* mcbsp5 */
431static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
432 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
433 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
434 { .name = "common", .irq = 19 + OMAP_INTC_START, },
435 { .irq = -1 },
436};
437
438static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
439 { .name = "rx", .dma_req = 22 },
440 { .name = "tx", .dma_req = 21 },
441 { .dma_req = -1 }
442};
443
444static struct omap_hwmod omap2430_mcbsp5_hwmod = { 349static struct omap_hwmod omap2430_mcbsp5_hwmod = {
445 .name = "mcbsp5", 350 .name = "mcbsp5",
446 .class = &omap2430_mcbsp_hwmod_class, 351 .class = &omap2430_mcbsp_hwmod_class,
447 .mpu_irqs = omap2430_mcbsp5_irqs,
448 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
449 .main_clk = "mcbsp5_fck", 352 .main_clk = "mcbsp5_fck",
450 .prcm = { 353 .prcm = {
451 .omap2 = { 354 .omap2 = {
@@ -478,17 +381,6 @@ static struct omap_hwmod_class omap2430_mmc_class = {
478}; 381};
479 382
480/* MMC/SD/SDIO1 */ 383/* MMC/SD/SDIO1 */
481static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
482 { .irq = 83 + OMAP_INTC_START, },
483 { .irq = -1 },
484};
485
486static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
487 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
488 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
489 { .dma_req = -1 }
490};
491
492static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 384static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
493 { .role = "dbck", .clk = "mmchsdb1_fck" }, 385 { .role = "dbck", .clk = "mmchsdb1_fck" },
494}; 386};
@@ -500,8 +392,6 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
500static struct omap_hwmod omap2430_mmc1_hwmod = { 392static struct omap_hwmod omap2430_mmc1_hwmod = {
501 .name = "mmc1", 393 .name = "mmc1",
502 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 394 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
503 .mpu_irqs = omap2430_mmc1_mpu_irqs,
504 .sdma_reqs = omap2430_mmc1_sdma_reqs,
505 .opt_clks = omap2430_mmc1_opt_clks, 395 .opt_clks = omap2430_mmc1_opt_clks,
506 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 396 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
507 .main_clk = "mmchs1_fck", 397 .main_clk = "mmchs1_fck",
@@ -519,17 +409,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
519}; 409};
520 410
521/* MMC/SD/SDIO2 */ 411/* MMC/SD/SDIO2 */
522static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
523 { .irq = 86 + OMAP_INTC_START, },
524 { .irq = -1 },
525};
526
527static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
528 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
529 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
530 { .dma_req = -1 }
531};
532
533static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 412static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
534 { .role = "dbck", .clk = "mmchsdb2_fck" }, 413 { .role = "dbck", .clk = "mmchsdb2_fck" },
535}; 414};
@@ -537,8 +416,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
537static struct omap_hwmod omap2430_mmc2_hwmod = { 416static struct omap_hwmod omap2430_mmc2_hwmod = {
538 .name = "mmc2", 417 .name = "mmc2",
539 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 418 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
540 .mpu_irqs = omap2430_mmc2_mpu_irqs,
541 .sdma_reqs = omap2430_mmc2_sdma_reqs,
542 .opt_clks = omap2430_mmc2_opt_clks, 419 .opt_clks = omap2430_mmc2_opt_clks,
543 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 420 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
544 .main_clk = "mmchs2_fck", 421 .main_clk = "mmchs2_fck",
@@ -557,7 +434,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
557/* HDQ1W/1-wire */ 434/* HDQ1W/1-wire */
558static struct omap_hwmod omap2430_hdq1w_hwmod = { 435static struct omap_hwmod omap2430_hdq1w_hwmod = {
559 .name = "hdq1w", 436 .name = "hdq1w",
560 .mpu_irqs = omap2_hdq1w_mpu_irqs,
561 .main_clk = "hdq_fck", 437 .main_clk = "hdq_fck",
562 .prcm = { 438 .prcm = {
563 .omap2 = { 439 .omap2 = {
@@ -589,7 +465,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
589 .master = &omap2xxx_l4_core_hwmod, 465 .master = &omap2xxx_l4_core_hwmod,
590 .slave = &omap2430_i2c1_hwmod, 466 .slave = &omap2430_i2c1_hwmod,
591 .clk = "i2c1_ick", 467 .clk = "i2c1_ick",
592 .addr = omap2_i2c1_addr_space,
593 .user = OCP_USER_MPU | OCP_USER_SDMA, 468 .user = OCP_USER_MPU | OCP_USER_SDMA,
594}; 469};
595 470
@@ -598,25 +473,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
598 .master = &omap2xxx_l4_core_hwmod, 473 .master = &omap2xxx_l4_core_hwmod,
599 .slave = &omap2430_i2c2_hwmod, 474 .slave = &omap2430_i2c2_hwmod,
600 .clk = "i2c2_ick", 475 .clk = "i2c2_ick",
601 .addr = omap2_i2c2_addr_space,
602 .user = OCP_USER_MPU | OCP_USER_SDMA, 476 .user = OCP_USER_MPU | OCP_USER_SDMA,
603}; 477};
604 478
605static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
606 {
607 .pa_start = OMAP243X_HS_BASE,
608 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
609 .flags = ADDR_TYPE_RT
610 },
611 { }
612};
613
614/* l4_core ->usbhsotg interface */ 479/* l4_core ->usbhsotg interface */
615static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 480static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
616 .master = &omap2xxx_l4_core_hwmod, 481 .master = &omap2xxx_l4_core_hwmod,
617 .slave = &omap2430_usbhsotg_hwmod, 482 .slave = &omap2430_usbhsotg_hwmod,
618 .clk = "usb_l4_ick", 483 .clk = "usb_l4_ick",
619 .addr = omap2430_usbhsotg_addrs,
620 .user = OCP_USER_MPU, 484 .user = OCP_USER_MPU,
621}; 485};
622 486
@@ -625,7 +489,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
625 .master = &omap2xxx_l4_core_hwmod, 489 .master = &omap2xxx_l4_core_hwmod,
626 .slave = &omap2430_mmc1_hwmod, 490 .slave = &omap2430_mmc1_hwmod,
627 .clk = "mmchs1_ick", 491 .clk = "mmchs1_ick",
628 .addr = omap2430_mmc1_addr_space,
629 .user = OCP_USER_MPU | OCP_USER_SDMA, 492 .user = OCP_USER_MPU | OCP_USER_SDMA,
630}; 493};
631 494
@@ -634,7 +497,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
634 .master = &omap2xxx_l4_core_hwmod, 497 .master = &omap2xxx_l4_core_hwmod,
635 .slave = &omap2430_mmc2_hwmod, 498 .slave = &omap2430_mmc2_hwmod,
636 .clk = "mmchs2_ick", 499 .clk = "mmchs2_ick",
637 .addr = omap2430_mmc2_addr_space,
638 .user = OCP_USER_MPU | OCP_USER_SDMA, 500 .user = OCP_USER_MPU | OCP_USER_SDMA,
639}; 501};
640 502
@@ -643,7 +505,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
643 .master = &omap2xxx_l4_core_hwmod, 505 .master = &omap2xxx_l4_core_hwmod,
644 .slave = &omap2430_mcspi3_hwmod, 506 .slave = &omap2430_mcspi3_hwmod,
645 .clk = "mcspi3_ick", 507 .clk = "mcspi3_ick",
646 .addr = omap2430_mcspi3_addr_space,
647 .user = OCP_USER_MPU | OCP_USER_SDMA, 508 .user = OCP_USER_MPU | OCP_USER_SDMA,
648}; 509};
649 510
@@ -655,129 +516,59 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = {
655 .user = OCP_USER_MPU | OCP_USER_SDMA, 516 .user = OCP_USER_MPU | OCP_USER_SDMA,
656}; 517};
657 518
658static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
659 {
660 .pa_start = 0x49018000,
661 .pa_end = 0x49018000 + SZ_1K - 1,
662 .flags = ADDR_TYPE_RT
663 },
664 { }
665};
666
667/* l4_wkup -> timer1 */ 519/* l4_wkup -> timer1 */
668static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 520static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
669 .master = &omap2xxx_l4_wkup_hwmod, 521 .master = &omap2xxx_l4_wkup_hwmod,
670 .slave = &omap2xxx_timer1_hwmod, 522 .slave = &omap2xxx_timer1_hwmod,
671 .clk = "gpt1_ick", 523 .clk = "gpt1_ick",
672 .addr = omap2430_timer1_addrs,
673 .user = OCP_USER_MPU | OCP_USER_SDMA, 524 .user = OCP_USER_MPU | OCP_USER_SDMA,
674}; 525};
675 526
676/* l4_wkup -> wd_timer2 */ 527/* l4_wkup -> wd_timer2 */
677static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
678 {
679 .pa_start = 0x49016000,
680 .pa_end = 0x4901607f,
681 .flags = ADDR_TYPE_RT
682 },
683 { }
684};
685
686static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 528static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
687 .master = &omap2xxx_l4_wkup_hwmod, 529 .master = &omap2xxx_l4_wkup_hwmod,
688 .slave = &omap2xxx_wd_timer2_hwmod, 530 .slave = &omap2xxx_wd_timer2_hwmod,
689 .clk = "mpu_wdt_ick", 531 .clk = "mpu_wdt_ick",
690 .addr = omap2430_wd_timer2_addrs,
691 .user = OCP_USER_MPU | OCP_USER_SDMA, 532 .user = OCP_USER_MPU | OCP_USER_SDMA,
692}; 533};
693 534
694/* l4_wkup -> gpio1 */ 535/* l4_wkup -> gpio1 */
695static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
696 {
697 .pa_start = 0x4900C000,
698 .pa_end = 0x4900C1ff,
699 .flags = ADDR_TYPE_RT
700 },
701 { }
702};
703
704static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 536static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
705 .master = &omap2xxx_l4_wkup_hwmod, 537 .master = &omap2xxx_l4_wkup_hwmod,
706 .slave = &omap2xxx_gpio1_hwmod, 538 .slave = &omap2xxx_gpio1_hwmod,
707 .clk = "gpios_ick", 539 .clk = "gpios_ick",
708 .addr = omap2430_gpio1_addr_space,
709 .user = OCP_USER_MPU | OCP_USER_SDMA, 540 .user = OCP_USER_MPU | OCP_USER_SDMA,
710}; 541};
711 542
712/* l4_wkup -> gpio2 */ 543/* l4_wkup -> gpio2 */
713static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
714 {
715 .pa_start = 0x4900E000,
716 .pa_end = 0x4900E1ff,
717 .flags = ADDR_TYPE_RT
718 },
719 { }
720};
721
722static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 544static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
723 .master = &omap2xxx_l4_wkup_hwmod, 545 .master = &omap2xxx_l4_wkup_hwmod,
724 .slave = &omap2xxx_gpio2_hwmod, 546 .slave = &omap2xxx_gpio2_hwmod,
725 .clk = "gpios_ick", 547 .clk = "gpios_ick",
726 .addr = omap2430_gpio2_addr_space,
727 .user = OCP_USER_MPU | OCP_USER_SDMA, 548 .user = OCP_USER_MPU | OCP_USER_SDMA,
728}; 549};
729 550
730/* l4_wkup -> gpio3 */ 551/* l4_wkup -> gpio3 */
731static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
732 {
733 .pa_start = 0x49010000,
734 .pa_end = 0x490101ff,
735 .flags = ADDR_TYPE_RT
736 },
737 { }
738};
739
740static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 552static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
741 .master = &omap2xxx_l4_wkup_hwmod, 553 .master = &omap2xxx_l4_wkup_hwmod,
742 .slave = &omap2xxx_gpio3_hwmod, 554 .slave = &omap2xxx_gpio3_hwmod,
743 .clk = "gpios_ick", 555 .clk = "gpios_ick",
744 .addr = omap2430_gpio3_addr_space,
745 .user = OCP_USER_MPU | OCP_USER_SDMA, 556 .user = OCP_USER_MPU | OCP_USER_SDMA,
746}; 557};
747 558
748/* l4_wkup -> gpio4 */ 559/* l4_wkup -> gpio4 */
749static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
750 {
751 .pa_start = 0x49012000,
752 .pa_end = 0x490121ff,
753 .flags = ADDR_TYPE_RT
754 },
755 { }
756};
757
758static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 560static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
759 .master = &omap2xxx_l4_wkup_hwmod, 561 .master = &omap2xxx_l4_wkup_hwmod,
760 .slave = &omap2xxx_gpio4_hwmod, 562 .slave = &omap2xxx_gpio4_hwmod,
761 .clk = "gpios_ick", 563 .clk = "gpios_ick",
762 .addr = omap2430_gpio4_addr_space,
763 .user = OCP_USER_MPU | OCP_USER_SDMA, 564 .user = OCP_USER_MPU | OCP_USER_SDMA,
764}; 565};
765 566
766/* l4_core -> gpio5 */ 567/* l4_core -> gpio5 */
767static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
768 {
769 .pa_start = 0x480B6000,
770 .pa_end = 0x480B61ff,
771 .flags = ADDR_TYPE_RT
772 },
773 { }
774};
775
776static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 568static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
777 .master = &omap2xxx_l4_core_hwmod, 569 .master = &omap2xxx_l4_core_hwmod,
778 .slave = &omap2430_gpio5_hwmod, 570 .slave = &omap2430_gpio5_hwmod,
779 .clk = "gpio5_ick", 571 .clk = "gpio5_ick",
780 .addr = omap2430_gpio5_addr_space,
781 .user = OCP_USER_MPU | OCP_USER_SDMA, 572 .user = OCP_USER_MPU | OCP_USER_SDMA,
782}; 573};
783 574
@@ -802,7 +593,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
802static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 593static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
803 .master = &omap2xxx_l4_core_hwmod, 594 .master = &omap2xxx_l4_core_hwmod,
804 .slave = &omap2430_mailbox_hwmod, 595 .slave = &omap2430_mailbox_hwmod,
805 .addr = omap2_mailbox_addrs,
806 .user = OCP_USER_MPU | OCP_USER_SDMA, 596 .user = OCP_USER_MPU | OCP_USER_SDMA,
807}; 597};
808 598
@@ -811,7 +601,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
811 .master = &omap2xxx_l4_core_hwmod, 601 .master = &omap2xxx_l4_core_hwmod,
812 .slave = &omap2430_mcbsp1_hwmod, 602 .slave = &omap2430_mcbsp1_hwmod,
813 .clk = "mcbsp1_ick", 603 .clk = "mcbsp1_ick",
814 .addr = omap2_mcbsp1_addrs,
815 .user = OCP_USER_MPU | OCP_USER_SDMA, 604 .user = OCP_USER_MPU | OCP_USER_SDMA,
816}; 605};
817 606
@@ -820,64 +609,30 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
820 .master = &omap2xxx_l4_core_hwmod, 609 .master = &omap2xxx_l4_core_hwmod,
821 .slave = &omap2430_mcbsp2_hwmod, 610 .slave = &omap2430_mcbsp2_hwmod,
822 .clk = "mcbsp2_ick", 611 .clk = "mcbsp2_ick",
823 .addr = omap2xxx_mcbsp2_addrs,
824 .user = OCP_USER_MPU | OCP_USER_SDMA, 612 .user = OCP_USER_MPU | OCP_USER_SDMA,
825}; 613};
826 614
827static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
828 {
829 .name = "mpu",
830 .pa_start = 0x4808C000,
831 .pa_end = 0x4808C0ff,
832 .flags = ADDR_TYPE_RT
833 },
834 { }
835};
836
837/* l4_core -> mcbsp3 */ 615/* l4_core -> mcbsp3 */
838static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { 616static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
839 .master = &omap2xxx_l4_core_hwmod, 617 .master = &omap2xxx_l4_core_hwmod,
840 .slave = &omap2430_mcbsp3_hwmod, 618 .slave = &omap2430_mcbsp3_hwmod,
841 .clk = "mcbsp3_ick", 619 .clk = "mcbsp3_ick",
842 .addr = omap2430_mcbsp3_addrs,
843 .user = OCP_USER_MPU | OCP_USER_SDMA, 620 .user = OCP_USER_MPU | OCP_USER_SDMA,
844}; 621};
845 622
846static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
847 {
848 .name = "mpu",
849 .pa_start = 0x4808E000,
850 .pa_end = 0x4808E0ff,
851 .flags = ADDR_TYPE_RT
852 },
853 { }
854};
855
856/* l4_core -> mcbsp4 */ 623/* l4_core -> mcbsp4 */
857static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { 624static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
858 .master = &omap2xxx_l4_core_hwmod, 625 .master = &omap2xxx_l4_core_hwmod,
859 .slave = &omap2430_mcbsp4_hwmod, 626 .slave = &omap2430_mcbsp4_hwmod,
860 .clk = "mcbsp4_ick", 627 .clk = "mcbsp4_ick",
861 .addr = omap2430_mcbsp4_addrs,
862 .user = OCP_USER_MPU | OCP_USER_SDMA, 628 .user = OCP_USER_MPU | OCP_USER_SDMA,
863}; 629};
864 630
865static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
866 {
867 .name = "mpu",
868 .pa_start = 0x48096000,
869 .pa_end = 0x480960ff,
870 .flags = ADDR_TYPE_RT
871 },
872 { }
873};
874
875/* l4_core -> mcbsp5 */ 631/* l4_core -> mcbsp5 */
876static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { 632static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
877 .master = &omap2xxx_l4_core_hwmod, 633 .master = &omap2xxx_l4_core_hwmod,
878 .slave = &omap2430_mcbsp5_hwmod, 634 .slave = &omap2430_mcbsp5_hwmod,
879 .clk = "mcbsp5_ick", 635 .clk = "mcbsp5_ick",
880 .addr = omap2430_mcbsp5_addrs,
881 .user = OCP_USER_MPU | OCP_USER_SDMA, 636 .user = OCP_USER_MPU | OCP_USER_SDMA,
882}; 637};
883 638
@@ -886,35 +641,15 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
886 .master = &omap2xxx_l4_core_hwmod, 641 .master = &omap2xxx_l4_core_hwmod,
887 .slave = &omap2430_hdq1w_hwmod, 642 .slave = &omap2430_hdq1w_hwmod,
888 .clk = "hdq_ick", 643 .clk = "hdq_ick",
889 .addr = omap2_hdq1w_addr_space,
890 .user = OCP_USER_MPU | OCP_USER_SDMA, 644 .user = OCP_USER_MPU | OCP_USER_SDMA,
891 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 645 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
892}; 646};
893 647
894/* l4_wkup -> 32ksync_counter */ 648/* l4_wkup -> 32ksync_counter */
895static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
896 {
897 .pa_start = 0x49020000,
898 .pa_end = 0x4902001f,
899 .flags = ADDR_TYPE_RT
900 },
901 { }
902};
903
904static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
905 {
906 .pa_start = 0x6e000000,
907 .pa_end = 0x6e000fff,
908 .flags = ADDR_TYPE_RT
909 },
910 { }
911};
912
913static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { 649static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
914 .master = &omap2xxx_l4_wkup_hwmod, 650 .master = &omap2xxx_l4_wkup_hwmod,
915 .slave = &omap2xxx_counter_32k_hwmod, 651 .slave = &omap2xxx_counter_32k_hwmod,
916 .clk = "sync_32k_ick", 652 .clk = "sync_32k_ick",
917 .addr = omap2430_counter_32k_addrs,
918 .user = OCP_USER_MPU | OCP_USER_SDMA, 653 .user = OCP_USER_MPU | OCP_USER_SDMA,
919}; 654};
920 655
@@ -922,7 +657,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
922 .master = &omap2xxx_l3_main_hwmod, 657 .master = &omap2xxx_l3_main_hwmod,
923 .slave = &omap2xxx_gpmc_hwmod, 658 .slave = &omap2xxx_gpmc_hwmod,
924 .clk = "core_l3_ck", 659 .clk = "core_l3_ck",
925 .addr = omap2430_gpmc_addrs,
926 .user = OCP_USER_MPU | OCP_USER_SDMA, 660 .user = OCP_USER_MPU | OCP_USER_SDMA,
927}; 661};
928 662
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 5fd40d4a989e..656861c29d5c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -20,142 +20,6 @@
20 20
21#include "omap_hwmod_common_data.h" 21#include "omap_hwmod_common_data.h"
22 22
23static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
24 {
25 .pa_start = OMAP2_UART1_BASE,
26 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
27 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
28 },
29 { }
30};
31
32static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
33 {
34 .pa_start = OMAP2_UART2_BASE,
35 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
36 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
37 },
38 { }
39};
40
41static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
42 {
43 .pa_start = OMAP2_UART3_BASE,
44 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
45 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
46 },
47 { }
48};
49
50static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
51 {
52 .pa_start = 0x4802a000,
53 .pa_end = 0x4802a000 + SZ_1K - 1,
54 .flags = ADDR_TYPE_RT
55 },
56 { }
57};
58
59static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
60 {
61 .pa_start = 0x48078000,
62 .pa_end = 0x48078000 + SZ_1K - 1,
63 .flags = ADDR_TYPE_RT
64 },
65 { }
66};
67
68static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
69 {
70 .pa_start = 0x4807a000,
71 .pa_end = 0x4807a000 + SZ_1K - 1,
72 .flags = ADDR_TYPE_RT
73 },
74 { }
75};
76
77static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
78 {
79 .pa_start = 0x4807c000,
80 .pa_end = 0x4807c000 + SZ_1K - 1,
81 .flags = ADDR_TYPE_RT
82 },
83 { }
84};
85
86static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
87 {
88 .pa_start = 0x4807e000,
89 .pa_end = 0x4807e000 + SZ_1K - 1,
90 .flags = ADDR_TYPE_RT
91 },
92 { }
93};
94
95static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
96 {
97 .pa_start = 0x48080000,
98 .pa_end = 0x48080000 + SZ_1K - 1,
99 .flags = ADDR_TYPE_RT
100 },
101 { }
102};
103
104static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
105 {
106 .pa_start = 0x48082000,
107 .pa_end = 0x48082000 + SZ_1K - 1,
108 .flags = ADDR_TYPE_RT
109 },
110 { }
111};
112
113static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
114 {
115 .pa_start = 0x48084000,
116 .pa_end = 0x48084000 + SZ_1K - 1,
117 .flags = ADDR_TYPE_RT
118 },
119 { }
120};
121
122struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
123 {
124 .name = "mpu",
125 .pa_start = 0x48076000,
126 .pa_end = 0x480760ff,
127 .flags = ADDR_TYPE_RT
128 },
129 { }
130};
131
132static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
133 {
134 .pa_start = 0x480a0000,
135 .pa_end = 0x480a004f,
136 .flags = ADDR_TYPE_RT
137 },
138 { }
139};
140
141static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
142 {
143 .pa_start = 0x480a4000,
144 .pa_end = 0x480a4000 + 0x64 - 1,
145 .flags = ADDR_TYPE_RT
146 },
147 { }
148};
149
150static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
151 {
152 .pa_start = 0x480a6000,
153 .pa_end = 0x480a6000 + 0x50 - 1,
154 .flags = ADDR_TYPE_RT
155 },
156 { }
157};
158
159/* 23/*
160 * Common interconnect data 24 * Common interconnect data
161 */ 25 */
@@ -182,7 +46,7 @@ struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
182 .omap2 = { 46 .omap2 = {
183 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, 47 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
184 .flags = OMAP_FIREWALL_L3, 48 .flags = OMAP_FIREWALL_L3,
185 } 49 },
186 }, 50 },
187 .user = OCP_USER_MPU | OCP_USER_SDMA, 51 .user = OCP_USER_MPU | OCP_USER_SDMA,
188}; 52};
@@ -199,7 +63,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
199 .master = &omap2xxx_l4_core_hwmod, 63 .master = &omap2xxx_l4_core_hwmod,
200 .slave = &omap2xxx_uart1_hwmod, 64 .slave = &omap2xxx_uart1_hwmod,
201 .clk = "uart1_ick", 65 .clk = "uart1_ick",
202 .addr = omap2xxx_uart1_addr_space,
203 .user = OCP_USER_MPU | OCP_USER_SDMA, 66 .user = OCP_USER_MPU | OCP_USER_SDMA,
204}; 67};
205 68
@@ -208,7 +71,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
208 .master = &omap2xxx_l4_core_hwmod, 71 .master = &omap2xxx_l4_core_hwmod,
209 .slave = &omap2xxx_uart2_hwmod, 72 .slave = &omap2xxx_uart2_hwmod,
210 .clk = "uart2_ick", 73 .clk = "uart2_ick",
211 .addr = omap2xxx_uart2_addr_space,
212 .user = OCP_USER_MPU | OCP_USER_SDMA, 74 .user = OCP_USER_MPU | OCP_USER_SDMA,
213}; 75};
214 76
@@ -217,7 +79,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
217 .master = &omap2xxx_l4_core_hwmod, 79 .master = &omap2xxx_l4_core_hwmod,
218 .slave = &omap2xxx_uart3_hwmod, 80 .slave = &omap2xxx_uart3_hwmod,
219 .clk = "uart3_ick", 81 .clk = "uart3_ick",
220 .addr = omap2xxx_uart3_addr_space,
221 .user = OCP_USER_MPU | OCP_USER_SDMA, 82 .user = OCP_USER_MPU | OCP_USER_SDMA,
222}; 83};
223 84
@@ -226,7 +87,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
226 .master = &omap2xxx_l4_core_hwmod, 87 .master = &omap2xxx_l4_core_hwmod,
227 .slave = &omap2xxx_mcspi1_hwmod, 88 .slave = &omap2xxx_mcspi1_hwmod,
228 .clk = "mcspi1_ick", 89 .clk = "mcspi1_ick",
229 .addr = omap2_mcspi1_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA, 90 .user = OCP_USER_MPU | OCP_USER_SDMA,
231}; 91};
232 92
@@ -235,7 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
235 .master = &omap2xxx_l4_core_hwmod, 95 .master = &omap2xxx_l4_core_hwmod,
236 .slave = &omap2xxx_mcspi2_hwmod, 96 .slave = &omap2xxx_mcspi2_hwmod,
237 .clk = "mcspi2_ick", 97 .clk = "mcspi2_ick",
238 .addr = omap2_mcspi2_addr_space,
239 .user = OCP_USER_MPU | OCP_USER_SDMA, 98 .user = OCP_USER_MPU | OCP_USER_SDMA,
240}; 99};
241 100
@@ -244,7 +103,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
244 .master = &omap2xxx_l4_core_hwmod, 103 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2xxx_timer2_hwmod, 104 .slave = &omap2xxx_timer2_hwmod,
246 .clk = "gpt2_ick", 105 .clk = "gpt2_ick",
247 .addr = omap2xxx_timer2_addrs,
248 .user = OCP_USER_MPU | OCP_USER_SDMA, 106 .user = OCP_USER_MPU | OCP_USER_SDMA,
249}; 107};
250 108
@@ -253,7 +111,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
253 .master = &omap2xxx_l4_core_hwmod, 111 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2xxx_timer3_hwmod, 112 .slave = &omap2xxx_timer3_hwmod,
255 .clk = "gpt3_ick", 113 .clk = "gpt3_ick",
256 .addr = omap2xxx_timer3_addrs,
257 .user = OCP_USER_MPU | OCP_USER_SDMA, 114 .user = OCP_USER_MPU | OCP_USER_SDMA,
258}; 115};
259 116
@@ -262,7 +119,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
262 .master = &omap2xxx_l4_core_hwmod, 119 .master = &omap2xxx_l4_core_hwmod,
263 .slave = &omap2xxx_timer4_hwmod, 120 .slave = &omap2xxx_timer4_hwmod,
264 .clk = "gpt4_ick", 121 .clk = "gpt4_ick",
265 .addr = omap2xxx_timer4_addrs,
266 .user = OCP_USER_MPU | OCP_USER_SDMA, 122 .user = OCP_USER_MPU | OCP_USER_SDMA,
267}; 123};
268 124
@@ -271,7 +127,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
271 .master = &omap2xxx_l4_core_hwmod, 127 .master = &omap2xxx_l4_core_hwmod,
272 .slave = &omap2xxx_timer5_hwmod, 128 .slave = &omap2xxx_timer5_hwmod,
273 .clk = "gpt5_ick", 129 .clk = "gpt5_ick",
274 .addr = omap2xxx_timer5_addrs,
275 .user = OCP_USER_MPU | OCP_USER_SDMA, 130 .user = OCP_USER_MPU | OCP_USER_SDMA,
276}; 131};
277 132
@@ -280,7 +135,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
280 .master = &omap2xxx_l4_core_hwmod, 135 .master = &omap2xxx_l4_core_hwmod,
281 .slave = &omap2xxx_timer6_hwmod, 136 .slave = &omap2xxx_timer6_hwmod,
282 .clk = "gpt6_ick", 137 .clk = "gpt6_ick",
283 .addr = omap2xxx_timer6_addrs,
284 .user = OCP_USER_MPU | OCP_USER_SDMA, 138 .user = OCP_USER_MPU | OCP_USER_SDMA,
285}; 139};
286 140
@@ -289,7 +143,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
289 .master = &omap2xxx_l4_core_hwmod, 143 .master = &omap2xxx_l4_core_hwmod,
290 .slave = &omap2xxx_timer7_hwmod, 144 .slave = &omap2xxx_timer7_hwmod,
291 .clk = "gpt7_ick", 145 .clk = "gpt7_ick",
292 .addr = omap2xxx_timer7_addrs,
293 .user = OCP_USER_MPU | OCP_USER_SDMA, 146 .user = OCP_USER_MPU | OCP_USER_SDMA,
294}; 147};
295 148
@@ -298,7 +151,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
298 .master = &omap2xxx_l4_core_hwmod, 151 .master = &omap2xxx_l4_core_hwmod,
299 .slave = &omap2xxx_timer8_hwmod, 152 .slave = &omap2xxx_timer8_hwmod,
300 .clk = "gpt8_ick", 153 .clk = "gpt8_ick",
301 .addr = omap2xxx_timer8_addrs,
302 .user = OCP_USER_MPU | OCP_USER_SDMA, 154 .user = OCP_USER_MPU | OCP_USER_SDMA,
303}; 155};
304 156
@@ -307,7 +159,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
307 .master = &omap2xxx_l4_core_hwmod, 159 .master = &omap2xxx_l4_core_hwmod,
308 .slave = &omap2xxx_timer9_hwmod, 160 .slave = &omap2xxx_timer9_hwmod,
309 .clk = "gpt9_ick", 161 .clk = "gpt9_ick",
310 .addr = omap2xxx_timer9_addrs,
311 .user = OCP_USER_MPU | OCP_USER_SDMA, 162 .user = OCP_USER_MPU | OCP_USER_SDMA,
312}; 163};
313 164
@@ -316,7 +167,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
316 .master = &omap2xxx_l4_core_hwmod, 167 .master = &omap2xxx_l4_core_hwmod,
317 .slave = &omap2xxx_timer10_hwmod, 168 .slave = &omap2xxx_timer10_hwmod,
318 .clk = "gpt10_ick", 169 .clk = "gpt10_ick",
319 .addr = omap2_timer10_addrs,
320 .user = OCP_USER_MPU | OCP_USER_SDMA, 170 .user = OCP_USER_MPU | OCP_USER_SDMA,
321}; 171};
322 172
@@ -325,7 +175,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
325 .master = &omap2xxx_l4_core_hwmod, 175 .master = &omap2xxx_l4_core_hwmod,
326 .slave = &omap2xxx_timer11_hwmod, 176 .slave = &omap2xxx_timer11_hwmod,
327 .clk = "gpt11_ick", 177 .clk = "gpt11_ick",
328 .addr = omap2_timer11_addrs,
329 .user = OCP_USER_MPU | OCP_USER_SDMA, 178 .user = OCP_USER_MPU | OCP_USER_SDMA,
330}; 179};
331 180
@@ -334,7 +183,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
334 .master = &omap2xxx_l4_core_hwmod, 183 .master = &omap2xxx_l4_core_hwmod,
335 .slave = &omap2xxx_timer12_hwmod, 184 .slave = &omap2xxx_timer12_hwmod,
336 .clk = "gpt12_ick", 185 .clk = "gpt12_ick",
337 .addr = omap2xxx_timer12_addrs,
338 .user = OCP_USER_MPU | OCP_USER_SDMA, 186 .user = OCP_USER_MPU | OCP_USER_SDMA,
339}; 187};
340 188
@@ -348,7 +196,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
348 .omap2 = { 196 .omap2 = {
349 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 197 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
350 .flags = OMAP_FIREWALL_L4, 198 .flags = OMAP_FIREWALL_L4,
351 } 199 },
352 }, 200 },
353 .user = OCP_USER_MPU | OCP_USER_SDMA, 201 .user = OCP_USER_MPU | OCP_USER_SDMA,
354}; 202};
@@ -363,7 +211,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
363 .omap2 = { 211 .omap2 = {
364 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 212 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
365 .flags = OMAP_FIREWALL_L4, 213 .flags = OMAP_FIREWALL_L4,
366 } 214 },
367 }, 215 },
368 .user = OCP_USER_MPU | OCP_USER_SDMA, 216 .user = OCP_USER_MPU | OCP_USER_SDMA,
369}; 217};
@@ -378,7 +226,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
378 .omap2 = { 226 .omap2 = {
379 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 227 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
380 .flags = OMAP_FIREWALL_L4, 228 .flags = OMAP_FIREWALL_L4,
381 } 229 },
382 }, 230 },
383 .user = OCP_USER_MPU | OCP_USER_SDMA, 231 .user = OCP_USER_MPU | OCP_USER_SDMA,
384}; 232};
@@ -393,7 +241,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
393 .omap2 = { 241 .omap2 = {
394 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 242 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
395 .flags = OMAP_FIREWALL_L4, 243 .flags = OMAP_FIREWALL_L4,
396 } 244 },
397 }, 245 },
398 .flags = OCPIF_SWSUP_IDLE, 246 .flags = OCPIF_SWSUP_IDLE,
399 .user = OCP_USER_MPU | OCP_USER_SDMA, 247 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -404,7 +252,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
404 .master = &omap2xxx_l4_core_hwmod, 252 .master = &omap2xxx_l4_core_hwmod,
405 .slave = &omap2xxx_rng_hwmod, 253 .slave = &omap2xxx_rng_hwmod,
406 .clk = "rng_ick", 254 .clk = "rng_ick",
407 .addr = omap2_rng_addr_space,
408 .user = OCP_USER_MPU | OCP_USER_SDMA, 255 .user = OCP_USER_MPU | OCP_USER_SDMA,
409}; 256};
410 257
@@ -413,7 +260,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
413 .master = &omap2xxx_l4_core_hwmod, 260 .master = &omap2xxx_l4_core_hwmod,
414 .slave = &omap2xxx_sham_hwmod, 261 .slave = &omap2xxx_sham_hwmod,
415 .clk = "sha_ick", 262 .clk = "sha_ick",
416 .addr = omap2xxx_sham_addrs,
417 .user = OCP_USER_MPU | OCP_USER_SDMA, 263 .user = OCP_USER_MPU | OCP_USER_SDMA,
418}; 264};
419 265
@@ -422,6 +268,5 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
422 .master = &omap2xxx_l4_core_hwmod, 268 .master = &omap2xxx_l4_core_hwmod,
423 .slave = &omap2xxx_aes_hwmod, 269 .slave = &omap2xxx_aes_hwmod,
424 .clk = "aes_ick", 270 .clk = "aes_ick",
425 .addr = omap2xxx_aes_addrs,
426 .user = OCP_USER_MPU | OCP_USER_SDMA, 271 .user = OCP_USER_MPU | OCP_USER_SDMA,
427}; 272};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 56cebb05509e..8821b9d6bae4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -20,14 +20,9 @@
20#include "prm-regbits-24xx.h" 20#include "prm-regbits-24xx.h"
21#include "wd_timer.h" 21#include "wd_timer.h"
22 22
23struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
24 { .irq = 48 + OMAP_INTC_START, },
25 { .irq = -1 },
26};
27
28struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { 23struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
29 { .name = "dispc", .dma_req = 5 }, 24 { .name = "dispc", .dma_req = 5 },
30 { .dma_req = -1 } 25 { .dma_req = -1, },
31}; 26};
32 27
33/* 28/*
@@ -219,14 +214,8 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
219}; 214};
220 215
221/* MPU */ 216/* MPU */
222static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
223 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
224 { .irq = -1 }
225};
226
227struct omap_hwmod omap2xxx_mpu_hwmod = { 217struct omap_hwmod omap2xxx_mpu_hwmod = {
228 .name = "mpu", 218 .name = "mpu",
229 .mpu_irqs = omap2xxx_mpu_irqs,
230 .class = &mpu_hwmod_class, 219 .class = &mpu_hwmod_class,
231 .main_clk = "mpu_ck", 220 .main_clk = "mpu_ck",
232}; 221};
@@ -256,7 +245,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
256 245
257struct omap_hwmod omap2xxx_timer1_hwmod = { 246struct omap_hwmod omap2xxx_timer1_hwmod = {
258 .name = "timer1", 247 .name = "timer1",
259 .mpu_irqs = omap2_timer1_mpu_irqs,
260 .main_clk = "gpt1_fck", 248 .main_clk = "gpt1_fck",
261 .prcm = { 249 .prcm = {
262 .omap2 = { 250 .omap2 = {
@@ -276,7 +264,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
276 264
277struct omap_hwmod omap2xxx_timer2_hwmod = { 265struct omap_hwmod omap2xxx_timer2_hwmod = {
278 .name = "timer2", 266 .name = "timer2",
279 .mpu_irqs = omap2_timer2_mpu_irqs,
280 .main_clk = "gpt2_fck", 267 .main_clk = "gpt2_fck",
281 .prcm = { 268 .prcm = {
282 .omap2 = { 269 .omap2 = {
@@ -295,7 +282,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
295 282
296struct omap_hwmod omap2xxx_timer3_hwmod = { 283struct omap_hwmod omap2xxx_timer3_hwmod = {
297 .name = "timer3", 284 .name = "timer3",
298 .mpu_irqs = omap2_timer3_mpu_irqs,
299 .main_clk = "gpt3_fck", 285 .main_clk = "gpt3_fck",
300 .prcm = { 286 .prcm = {
301 .omap2 = { 287 .omap2 = {
@@ -314,7 +300,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
314 300
315struct omap_hwmod omap2xxx_timer4_hwmod = { 301struct omap_hwmod omap2xxx_timer4_hwmod = {
316 .name = "timer4", 302 .name = "timer4",
317 .mpu_irqs = omap2_timer4_mpu_irqs,
318 .main_clk = "gpt4_fck", 303 .main_clk = "gpt4_fck",
319 .prcm = { 304 .prcm = {
320 .omap2 = { 305 .omap2 = {
@@ -333,7 +318,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
333 318
334struct omap_hwmod omap2xxx_timer5_hwmod = { 319struct omap_hwmod omap2xxx_timer5_hwmod = {
335 .name = "timer5", 320 .name = "timer5",
336 .mpu_irqs = omap2_timer5_mpu_irqs,
337 .main_clk = "gpt5_fck", 321 .main_clk = "gpt5_fck",
338 .prcm = { 322 .prcm = {
339 .omap2 = { 323 .omap2 = {
@@ -353,7 +337,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
353 337
354struct omap_hwmod omap2xxx_timer6_hwmod = { 338struct omap_hwmod omap2xxx_timer6_hwmod = {
355 .name = "timer6", 339 .name = "timer6",
356 .mpu_irqs = omap2_timer6_mpu_irqs,
357 .main_clk = "gpt6_fck", 340 .main_clk = "gpt6_fck",
358 .prcm = { 341 .prcm = {
359 .omap2 = { 342 .omap2 = {
@@ -373,7 +356,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
373 356
374struct omap_hwmod omap2xxx_timer7_hwmod = { 357struct omap_hwmod omap2xxx_timer7_hwmod = {
375 .name = "timer7", 358 .name = "timer7",
376 .mpu_irqs = omap2_timer7_mpu_irqs,
377 .main_clk = "gpt7_fck", 359 .main_clk = "gpt7_fck",
378 .prcm = { 360 .prcm = {
379 .omap2 = { 361 .omap2 = {
@@ -393,7 +375,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
393 375
394struct omap_hwmod omap2xxx_timer8_hwmod = { 376struct omap_hwmod omap2xxx_timer8_hwmod = {
395 .name = "timer8", 377 .name = "timer8",
396 .mpu_irqs = omap2_timer8_mpu_irqs,
397 .main_clk = "gpt8_fck", 378 .main_clk = "gpt8_fck",
398 .prcm = { 379 .prcm = {
399 .omap2 = { 380 .omap2 = {
@@ -413,7 +394,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
413 394
414struct omap_hwmod omap2xxx_timer9_hwmod = { 395struct omap_hwmod omap2xxx_timer9_hwmod = {
415 .name = "timer9", 396 .name = "timer9",
416 .mpu_irqs = omap2_timer9_mpu_irqs,
417 .main_clk = "gpt9_fck", 397 .main_clk = "gpt9_fck",
418 .prcm = { 398 .prcm = {
419 .omap2 = { 399 .omap2 = {
@@ -433,7 +413,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
433 413
434struct omap_hwmod omap2xxx_timer10_hwmod = { 414struct omap_hwmod omap2xxx_timer10_hwmod = {
435 .name = "timer10", 415 .name = "timer10",
436 .mpu_irqs = omap2_timer10_mpu_irqs,
437 .main_clk = "gpt10_fck", 416 .main_clk = "gpt10_fck",
438 .prcm = { 417 .prcm = {
439 .omap2 = { 418 .omap2 = {
@@ -453,7 +432,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
453 432
454struct omap_hwmod omap2xxx_timer11_hwmod = { 433struct omap_hwmod omap2xxx_timer11_hwmod = {
455 .name = "timer11", 434 .name = "timer11",
456 .mpu_irqs = omap2_timer11_mpu_irqs,
457 .main_clk = "gpt11_fck", 435 .main_clk = "gpt11_fck",
458 .prcm = { 436 .prcm = {
459 .omap2 = { 437 .omap2 = {
@@ -473,7 +451,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
473 451
474struct omap_hwmod omap2xxx_timer12_hwmod = { 452struct omap_hwmod omap2xxx_timer12_hwmod = {
475 .name = "timer12", 453 .name = "timer12",
476 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
477 .main_clk = "gpt12_fck", 454 .main_clk = "gpt12_fck",
478 .prcm = { 455 .prcm = {
479 .omap2 = { 456 .omap2 = {
@@ -509,8 +486,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
509 486
510struct omap_hwmod omap2xxx_uart1_hwmod = { 487struct omap_hwmod omap2xxx_uart1_hwmod = {
511 .name = "uart1", 488 .name = "uart1",
512 .mpu_irqs = omap2_uart1_mpu_irqs,
513 .sdma_reqs = omap2_uart1_sdma_reqs,
514 .main_clk = "uart1_fck", 489 .main_clk = "uart1_fck",
515 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 490 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
516 .prcm = { 491 .prcm = {
@@ -529,8 +504,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
529 504
530struct omap_hwmod omap2xxx_uart2_hwmod = { 505struct omap_hwmod omap2xxx_uart2_hwmod = {
531 .name = "uart2", 506 .name = "uart2",
532 .mpu_irqs = omap2_uart2_mpu_irqs,
533 .sdma_reqs = omap2_uart2_sdma_reqs,
534 .main_clk = "uart2_fck", 507 .main_clk = "uart2_fck",
535 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 508 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
536 .prcm = { 509 .prcm = {
@@ -549,8 +522,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
549 522
550struct omap_hwmod omap2xxx_uart3_hwmod = { 523struct omap_hwmod omap2xxx_uart3_hwmod = {
551 .name = "uart3", 524 .name = "uart3",
552 .mpu_irqs = omap2_uart3_mpu_irqs,
553 .sdma_reqs = omap2_uart3_sdma_reqs,
554 .main_clk = "uart3_fck", 525 .main_clk = "uart3_fck",
555 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 526 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
556 .prcm = { 527 .prcm = {
@@ -610,7 +581,7 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
610 }, 581 },
611 }, 582 },
612 .flags = HWMOD_NO_IDLEST, 583 .flags = HWMOD_NO_IDLEST,
613 .dev_attr = &omap2_3_dss_dispc_dev_attr 584 .dev_attr = &omap2_3_dss_dispc_dev_attr,
614}; 585};
615 586
616static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 587static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
@@ -657,7 +628,6 @@ struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
657struct omap_hwmod omap2xxx_gpio1_hwmod = { 628struct omap_hwmod omap2xxx_gpio1_hwmod = {
658 .name = "gpio1", 629 .name = "gpio1",
659 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 630 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
660 .mpu_irqs = omap2_gpio1_irqs,
661 .main_clk = "gpios_fck", 631 .main_clk = "gpios_fck",
662 .prcm = { 632 .prcm = {
663 .omap2 = { 633 .omap2 = {
@@ -676,7 +646,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = {
676struct omap_hwmod omap2xxx_gpio2_hwmod = { 646struct omap_hwmod omap2xxx_gpio2_hwmod = {
677 .name = "gpio2", 647 .name = "gpio2",
678 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
679 .mpu_irqs = omap2_gpio2_irqs,
680 .main_clk = "gpios_fck", 649 .main_clk = "gpios_fck",
681 .prcm = { 650 .prcm = {
682 .omap2 = { 651 .omap2 = {
@@ -695,7 +664,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = {
695struct omap_hwmod omap2xxx_gpio3_hwmod = { 664struct omap_hwmod omap2xxx_gpio3_hwmod = {
696 .name = "gpio3", 665 .name = "gpio3",
697 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
698 .mpu_irqs = omap2_gpio3_irqs,
699 .main_clk = "gpios_fck", 667 .main_clk = "gpios_fck",
700 .prcm = { 668 .prcm = {
701 .omap2 = { 669 .omap2 = {
@@ -714,7 +682,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = {
714struct omap_hwmod omap2xxx_gpio4_hwmod = { 682struct omap_hwmod omap2xxx_gpio4_hwmod = {
715 .name = "gpio4", 683 .name = "gpio4",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 684 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .mpu_irqs = omap2_gpio4_irqs,
718 .main_clk = "gpios_fck", 685 .main_clk = "gpios_fck",
719 .prcm = { 686 .prcm = {
720 .omap2 = { 687 .omap2 = {
@@ -736,8 +703,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
736 703
737struct omap_hwmod omap2xxx_mcspi1_hwmod = { 704struct omap_hwmod omap2xxx_mcspi1_hwmod = {
738 .name = "mcspi1", 705 .name = "mcspi1",
739 .mpu_irqs = omap2_mcspi1_mpu_irqs,
740 .sdma_reqs = omap2_mcspi1_sdma_reqs,
741 .main_clk = "mcspi1_fck", 706 .main_clk = "mcspi1_fck",
742 .prcm = { 707 .prcm = {
743 .omap2 = { 708 .omap2 = {
@@ -759,8 +724,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
759 724
760struct omap_hwmod omap2xxx_mcspi2_hwmod = { 725struct omap_hwmod omap2xxx_mcspi2_hwmod = {
761 .name = "mcspi2", 726 .name = "mcspi2",
762 .mpu_irqs = omap2_mcspi2_mpu_irqs,
763 .sdma_reqs = omap2_mcspi2_sdma_reqs,
764 .main_clk = "mcspi2_fck", 727 .main_clk = "mcspi2_fck",
765 .prcm = { 728 .prcm = {
766 .omap2 = { 729 .omap2 = {
@@ -795,15 +758,9 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
795}; 758};
796 759
797/* gpmc */ 760/* gpmc */
798static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
799 { .irq = 20 },
800 { .irq = -1 }
801};
802
803struct omap_hwmod omap2xxx_gpmc_hwmod = { 761struct omap_hwmod omap2xxx_gpmc_hwmod = {
804 .name = "gpmc", 762 .name = "gpmc",
805 .class = &omap2xxx_gpmc_hwmod_class, 763 .class = &omap2xxx_gpmc_hwmod_class,
806 .mpu_irqs = omap2xxx_gpmc_irqs,
807 .main_clk = "gpmc_fck", 764 .main_clk = "gpmc_fck",
808 /* 765 /*
809 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP 766 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
@@ -840,14 +797,8 @@ static struct omap_hwmod_class omap2_rng_hwmod_class = {
840 .sysc = &omap2_rng_sysc, 797 .sysc = &omap2_rng_sysc,
841}; 798};
842 799
843static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
844 { .irq = 52 },
845 { .irq = -1 }
846};
847
848struct omap_hwmod omap2xxx_rng_hwmod = { 800struct omap_hwmod omap2xxx_rng_hwmod = {
849 .name = "rng", 801 .name = "rng",
850 .mpu_irqs = omap2_rng_mpu_irqs,
851 .main_clk = "l4_ck", 802 .main_clk = "l4_ck",
852 .prcm = { 803 .prcm = {
853 .omap2 = { 804 .omap2 = {
@@ -884,20 +835,8 @@ static struct omap_hwmod_class omap2xxx_sham_class = {
884 .sysc = &omap2_sham_sysc, 835 .sysc = &omap2_sham_sysc,
885}; 836};
886 837
887static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
888 { .irq = 51 + OMAP_INTC_START, },
889 { .irq = -1 }
890};
891
892static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
893 { .name = "rx", .dma_req = 13 },
894 { .dma_req = -1 }
895};
896
897struct omap_hwmod omap2xxx_sham_hwmod = { 838struct omap_hwmod omap2xxx_sham_hwmod = {
898 .name = "sham", 839 .name = "sham",
899 .mpu_irqs = omap2_sham_mpu_irqs,
900 .sdma_reqs = omap2_sham_sdma_chs,
901 .main_clk = "l4_ck", 840 .main_clk = "l4_ck",
902 .prcm = { 841 .prcm = {
903 .omap2 = { 842 .omap2 = {
@@ -927,15 +866,8 @@ static struct omap_hwmod_class omap2xxx_aes_class = {
927 .sysc = &omap2_aes_sysc, 866 .sysc = &omap2_aes_sysc,
928}; 867};
929 868
930static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
931 { .name = "tx", .dma_req = 9 },
932 { .name = "rx", .dma_req = 10 },
933 { .dma_req = -1 }
934};
935
936struct omap_hwmod omap2xxx_aes_hwmod = { 869struct omap_hwmod omap2xxx_aes_hwmod = {
937 .name = "aes", 870 .name = "aes",
938 .sdma_reqs = omap2_aes_sdma_chs,
939 .main_clk = "l4_ck", 871 .main_clk = "l4_ck",
940 .prcm = { 872 .prcm = {
941 .omap2 = { 873 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 6e04ff7065e1..2c38c6b0ee03 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -18,9 +18,6 @@
18#include "common.h" 18#include "common.h"
19#include "display.h" 19#include "display.h"
20 20
21/* Common address space across OMAP2xxx */
22extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
23
24/* Common address space across OMAP2xxx/3xxx */ 21/* Common address space across OMAP2xxx/3xxx */
25extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[]; 22extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
26extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[]; 23extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
@@ -41,8 +38,6 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
41extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; 38extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
42 39
43/* Common IP block data across OMAP2xxx */ 40/* Common IP block data across OMAP2xxx */
44extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
45extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
46extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; 41extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
47extern struct omap_hwmod omap2xxx_l3_main_hwmod; 42extern struct omap_hwmod omap2xxx_l3_main_hwmod;
48extern struct omap_hwmod omap2xxx_l4_core_hwmod; 43extern struct omap_hwmod omap2xxx_l4_core_hwmod;
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 04:31:33 -0500