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authorBen Skeggs <bskeggs@redhat.com>2013-07-03 21:01:34 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-07-04 23:43:40 -0400
commitb054aadfb0030b9717bb22f4283bfe5aec13440b (patch)
tree80f2afc5909932262d77590d599de4122996d37c
parent9ec2dbba9fedbd1788849fb00d659ebdf549a4f8 (diff)
drm/nvf0/gr: magic sequence that makes PGRAPH come out of hiding
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c50
2 files changed, 48 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 90779120d9e9..7aca1877add4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -164,10 +164,8 @@ nve0_identify(struct nouveau_device *device)
164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 164 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; 165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
166 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; 166 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
167#if 0
168 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; 167 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
169 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; 168 device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
170#endif
171 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; 169 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
172 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; 170 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
173 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; 171 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
index 1d6ebd05216e..d7dff11c1883 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
@@ -25,6 +25,15 @@
25#include "nvc0.h" 25#include "nvc0.h"
26 26
27/******************************************************************************* 27/*******************************************************************************
28 * Graphics object classes
29 ******************************************************************************/
30
31static struct nouveau_oclass
32nvf0_graph_sclass[] = {
33 {}
34};
35
36/*******************************************************************************
28 * PGRAPH engine/subdev functions 37 * PGRAPH engine/subdev functions
29 ******************************************************************************/ 38 ******************************************************************************/
30 39
@@ -142,6 +151,43 @@ nvf0_graph_init_tpc[] = {
142 {} 151 {}
143}; 152};
144 153
154static int
155nvf0_graph_fini(struct nouveau_object *object, bool suspend)
156{
157 struct nvc0_graph_priv *priv = (void *)object;
158 static const struct {
159 u32 addr;
160 u32 data;
161 } magic[] = {
162 { 0x020520, 0xfffffffc },
163 { 0x020524, 0xfffffffe },
164 { 0x020524, 0xfffffffc },
165 { 0x020524, 0xfffffff8 },
166 { 0x020524, 0xffffffe0 },
167 { 0x020530, 0xfffffffe },
168 { 0x02052c, 0xfffffffa },
169 { 0x02052c, 0xfffffff0 },
170 { 0x02052c, 0xffffffc0 },
171 { 0x02052c, 0xffffff00 },
172 { 0x02052c, 0xfffffc00 },
173 { 0x02052c, 0xfffcfc00 },
174 { 0x02052c, 0xfff0fc00 },
175 { 0x02052c, 0xff80fc00 },
176 { 0x020528, 0xfffffffe },
177 { 0x020528, 0xfffffffc },
178 };
179 int i;
180
181 nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
182 nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
183 for (i = 0; i < ARRAY_SIZE(magic); i++) {
184 nv_wr32(priv, magic[i].addr, magic[i].data);
185 nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
186 }
187
188 return nouveau_graph_fini(&priv->base, suspend);
189}
190
145static struct nvc0_graph_init * 191static struct nvc0_graph_init *
146nvf0_graph_init_mmio[] = { 192nvf0_graph_init_mmio[] = {
147 nve4_graph_init_regs, 193 nve4_graph_init_regs,
@@ -168,9 +214,9 @@ nvf0_graph_oclass = &(struct nvc0_graph_oclass) {
168 .ctor = nvc0_graph_ctor, 214 .ctor = nvc0_graph_ctor,
169 .dtor = nvc0_graph_dtor, 215 .dtor = nvc0_graph_dtor,
170 .init = nve4_graph_init, 216 .init = nve4_graph_init,
171 .fini = _nouveau_graph_fini, 217 .fini = nvf0_graph_fini,
172 }, 218 },
173 .cclass = &nvf0_grctx_oclass, 219 .cclass = &nvf0_grctx_oclass,
174 .sclass = NULL, 220 .sclass = nvf0_graph_sclass,
175 .mmio = nvf0_graph_init_mmio, 221 .mmio = nvf0_graph_init_mmio,
176}.base; 222}.base;