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authorLinus Torvalds <torvalds@linux-foundation.org>2019-03-06 13:22:26 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2019-03-06 13:22:26 -0500
commitafe6fe7036c6efdcb46cabc64bec9b6e4a005210 (patch)
tree0f5aaa66028806b8ab45fc46a7f7e0c4bc58cc36
parent64b1b217f1a20f15dbedf47e49a25a0b5ee3d53b (diff)
parent2547635054af399303f8b91292ea121e13b84bb1 (diff)
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC late updates from Arnd Bergmann: "Here are two branches that came relatively late during the linux-5.0 development cycle and have dependencies on the other branches: - On the TI OMAP platform, the CPSW Ethernet PHY mode selection driver is being replaced, this puts the final pieces in place - On the DaVinci platform, the interrupt handling code in arch/arm gets moved into a regular device driver in drivers/irqchip. Since they both had some time in linux-next after the 5.0-rc8 release, I'm sending them along with the other updates" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) net: ethernet: ti: cpsw: deprecate cpsw-phy-sel driver ARM: davinci: remove intc related fields from davinci_soc_info irqchip: davinci-cp-intc: move the driver to drivers/irqchip ARM: davinci: cp-intc: remove redundant comments ARM: davinci: cp-intc: drop GPL license boilerplate ARM: davinci: cp-intc: use readl/writel_relaxed() ARM: davinci: cp-intc: unify error handling ARM: davinci: cp-intc: improve coding style ARM: davinci: cp-intc: request the memory region before remapping it ARM: davinci: cp-intc: use the new-style config structure ARM: davinci: cp-intc: convert all hex numbers to lowercase ARM: davinci: cp-intc: use a common prefix for all symbols ARM: davinci: cp-intc: add the new config structures for da8xx SoCs irqchip: davinci-cp-intc: add a new config structure ARM: davinci: cp-intc: add a wrapper around cp_intc_init() ARM: davinci: cp-intc: remove cp_intc.h irqchip: davinci-aintc: move the driver to drivers/irqchip ARM: davinci: aintc: remove unnecessary includes ARM: davinci: aintc: remove the timer-specific irq_set_handler() ARM: davinci: aintc: request memory region before remapping it ...
Diffstat
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/mach-davinci/Kconfig19
-rw-r--r--arch/arm/mach-davinci/Makefile3
-rw-r--r--arch/arm/mach-davinci/asp.h8
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c5
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c5
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c2
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c8
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c6
-rw-r--r--arch/arm/mach-davinci/board-mityomapl138.c3
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c2
-rw-r--r--arch/arm/mach-davinci/board-omapl138-hawk.c3
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c2
-rw-r--r--arch/arm/mach-davinci/common.c3
-rw-r--r--arch/arm/mach-davinci/cp_intc.c215
-rw-r--r--arch/arm/mach-davinci/cp_intc.h57
-rw-r--r--arch/arm/mach-davinci/da830.c128
-rw-r--r--arch/arm/mach-davinci/da850.c154
-rw-r--r--arch/arm/mach-davinci/davinci.h4
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c147
-rw-r--r--arch/arm/mach-davinci/devices.c40
-rw-r--r--arch/arm/mach-davinci/dm355.c78
-rw-r--r--arch/arm/mach-davinci/dm365.c102
-rw-r--r--arch/arm/mach-davinci/dm644x.c68
-rw-r--r--arch/arm/mach-davinci/dm646x.c82
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h14
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/entry-macro.S39
-rw-r--r--arch/arm/mach-davinci/irq.c117
-rw-r--r--arch/arm/mach-davinci/irqs.h (renamed from arch/arm/mach-davinci/include/mach/irqs.h)4
-rw-r--r--arch/arm/mach-davinci/usb-da8xx.c9
-rw-r--r--arch/arm/mach-davinci/usb.c15
-rw-r--r--drivers/input/keyboard/davinci_keyscan.c4
-rw-r--r--drivers/irqchip/Kconfig10
-rw-r--r--drivers/irqchip/Makefile2
-rw-r--r--drivers/irqchip/irq-davinci-aintc.c163
-rw-r--r--drivers/irqchip/irq-davinci-cp-intc.c260
-rw-r--r--drivers/net/ethernet/ti/Kconfig6
-rw-r--r--drivers/net/ethernet/ti/cpsw.h6
-rw-r--r--include/linux/irqchip/irq-davinci-aintc.h27
-rw-r--r--include/linux/irqchip/irq-davinci-cp-intc.h25
43 files changed, 889 insertions, 964 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 83f724e5a056..e8a4d3ffb6eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -590,11 +590,13 @@ config ARCH_DAVINCI
590 select GENERIC_ALLOCATOR 590 select GENERIC_ALLOCATOR
591 select GENERIC_CLOCKEVENTS 591 select GENERIC_CLOCKEVENTS
592 select GENERIC_IRQ_CHIP 592 select GENERIC_IRQ_CHIP
593 select GENERIC_IRQ_MULTI_HANDLER
593 select GPIOLIB 594 select GPIOLIB
594 select HAVE_IDE 595 select HAVE_IDE
595 select PM_GENERIC_DOMAINS if PM 596 select PM_GENERIC_DOMAINS if PM
596 select PM_GENERIC_DOMAINS_OF if PM && OF 597 select PM_GENERIC_DOMAINS_OF if PM && OF
597 select RESET_CONTROLLER 598 select RESET_CONTROLLER
599 select SPARSE_IRQ
598 select USE_OF 600 select USE_OF
599 select ZONE_DMA 601 select ZONE_DMA
600 help 602 help
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index da8a039d65f9..5a59cebc7d0a 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -1,13 +1,6 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2if ARCH_DAVINCI 2if ARCH_DAVINCI
3 3
4config AINTC
5 bool
6
7config CP_INTC
8 bool
9 select IRQ_DOMAIN
10
11config ARCH_DAVINCI_DMx 4config ARCH_DAVINCI_DMx
12 bool 5 bool
13 6
@@ -17,17 +10,17 @@ comment "DaVinci Core Type"
17 10
18config ARCH_DAVINCI_DM644x 11config ARCH_DAVINCI_DM644x
19 bool "DaVinci 644x based system" 12 bool "DaVinci 644x based system"
20 select AINTC 13 select DAVINCI_AINTC
21 select ARCH_DAVINCI_DMx 14 select ARCH_DAVINCI_DMx
22 15
23config ARCH_DAVINCI_DM355 16config ARCH_DAVINCI_DM355
24 bool "DaVinci 355 based system" 17 bool "DaVinci 355 based system"
25 select AINTC 18 select DAVINCI_AINTC
26 select ARCH_DAVINCI_DMx 19 select ARCH_DAVINCI_DMx
27 20
28config ARCH_DAVINCI_DM646x 21config ARCH_DAVINCI_DM646x
29 bool "DaVinci 646x based system" 22 bool "DaVinci 646x based system"
30 select AINTC 23 select DAVINCI_AINTC
31 select ARCH_DAVINCI_DMx 24 select ARCH_DAVINCI_DMx
32 25
33config ARCH_DAVINCI_DA830 26config ARCH_DAVINCI_DA830
@@ -36,20 +29,20 @@ config ARCH_DAVINCI_DA830
36 select ARCH_DAVINCI_DA8XX 29 select ARCH_DAVINCI_DA8XX
37 # needed on silicon revs 1.0, 1.1: 30 # needed on silicon revs 1.0, 1.1:
38 select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE 31 select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
39 select CP_INTC 32 select DAVINCI_CP_INTC
40 33
41config ARCH_DAVINCI_DA850 34config ARCH_DAVINCI_DA850
42 bool "DA850/OMAP-L138/AM18x based system" 35 bool "DA850/OMAP-L138/AM18x based system"
43 depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT) 36 depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
44 select ARCH_DAVINCI_DA8XX 37 select ARCH_DAVINCI_DA8XX
45 select CP_INTC 38 select DAVINCI_CP_INTC
46 39
47config ARCH_DAVINCI_DA8XX 40config ARCH_DAVINCI_DA8XX
48 bool 41 bool
49 42
50config ARCH_DAVINCI_DM365 43config ARCH_DAVINCI_DM365
51 bool "DaVinci 365 based system" 44 bool "DaVinci 365 based system"
52 select AINTC 45 select DAVINCI_AINTC
53 select ARCH_DAVINCI_DMx 46 select ARCH_DAVINCI_DMx
54 47
55comment "DaVinci Board Type" 48comment "DaVinci Board Type"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 93d271b4d84b..f76a8482784f 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -18,9 +18,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
18obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o 18obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o
19obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o 19obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o
20 20
21obj-$(CONFIG_AINTC) += irq.o
22obj-$(CONFIG_CP_INTC) += cp_intc.o
23
24# Board specific 21# Board specific
25obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o 22obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o
26obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o 23obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
index 495aa6907cbc..d0ecd1d0f084 100644
--- a/arch/arm/mach-davinci/asp.h
+++ b/arch/arm/mach-davinci/asp.h
@@ -49,9 +49,9 @@
49#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5 49#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5
50 50
51/* Interrupts */ 51/* Interrupts */
52#define DAVINCI_ASP0_RX_INT IRQ_MBRINT 52#define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
53#define DAVINCI_ASP0_TX_INT IRQ_MBXINT 53#define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
54#define DAVINCI_ASP1_RX_INT IRQ_MBRINT 54#define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
55#define DAVINCI_ASP1_TX_INT IRQ_MBXINT 55#define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
56 56
57#endif /* __ASM_ARCH_DAVINCI_ASP_H */ 57#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 3a2124212a7f..ff097ecfa451 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -36,10 +36,11 @@
36#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
37 37
38#include <mach/common.h> 38#include <mach/common.h>
39#include "cp_intc.h"
40#include <mach/mux.h> 39#include <mach/mux.h>
41#include <mach/da8xx.h> 40#include <mach/da8xx.h>
42 41
42#include "irqs.h"
43
43#define DA830_EVM_PHY_ID "" 44#define DA830_EVM_PHY_ID ""
44/* 45/*
45 * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. 46 * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
@@ -633,7 +634,7 @@ static void __init da830_evm_map_io(void)
633MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") 634MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
634 .atag_offset = 0x100, 635 .atag_offset = 0x100,
635 .map_io = da830_evm_map_io, 636 .map_io = da830_evm_map_io,
636 .init_irq = cp_intc_init, 637 .init_irq = da830_init_irq,
637 .init_time = da830_init_time, 638 .init_time = da830_init_time,
638 .init_machine = da830_evm_init, 639 .init_machine = da830_evm_init,
639 .init_late = davinci_init_late, 640 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 56d0e0257048..1fdc9283a8c5 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -43,9 +43,10 @@
43#include <linux/spi/flash.h> 43#include <linux/spi/flash.h>
44 44
45#include <mach/common.h> 45#include <mach/common.h>
46#include "cp_intc.h"
47#include <mach/da8xx.h> 46#include <mach/da8xx.h>
48#include <mach/mux.h> 47#include <mach/mux.h>
48
49#include "irqs.h"
49#include "sram.h" 50#include "sram.h"
50 51
51#include <asm/mach-types.h> 52#include <asm/mach-types.h>
@@ -1499,7 +1500,7 @@ static void __init da850_evm_map_io(void)
1499MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") 1500MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
1500 .atag_offset = 0x100, 1501 .atag_offset = 0x100,
1501 .map_io = da850_evm_map_io, 1502 .map_io = da850_evm_map_io,
1502 .init_irq = cp_intc_init, 1503 .init_irq = da850_init_irq,
1503 .init_time = da850_init_time, 1504 .init_time = da850_init_time,
1504 .init_machine = da850_evm_init, 1505 .init_machine = da850_evm_init,
1505 .init_late = davinci_init_late, 1506 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index f7fa960c23e3..64d81fc86f14 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -438,7 +438,7 @@ static __init void dm355_evm_init(void)
438MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") 438MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
439 .atag_offset = 0x100, 439 .atag_offset = 0x100,
440 .map_io = dm355_evm_map_io, 440 .map_io = dm355_evm_map_io,
441 .init_irq = davinci_irq_init, 441 .init_irq = dm355_init_irq,
442 .init_time = dm355_init_time, 442 .init_time = dm355_init_time,
443 .init_machine = dm355_evm_init, 443 .init_machine = dm355_evm_init,
444 .init_late = davinci_init_late, 444 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 0fdf1d03eb11..b9e9950dd300 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -273,7 +273,7 @@ static __init void dm355_leopard_init(void)
273MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") 273MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
274 .atag_offset = 0x100, 274 .atag_offset = 0x100,
275 .map_io = dm355_leopard_map_io, 275 .map_io = dm355_leopard_map_io,
276 .init_irq = davinci_irq_init, 276 .init_irq = dm355_init_irq,
277 .init_time = dm355_init_time, 277 .init_time = dm355_init_time,
278 .init_machine = dm355_leopard_init, 278 .init_machine = dm355_leopard_init,
279 .init_late = davinci_init_late, 279 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index f21dc8d3b28c..150a36f333df 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -831,7 +831,7 @@ static __init void dm365_evm_init(void)
831MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") 831MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
832 .atag_offset = 0x100, 832 .atag_offset = 0x100,
833 .map_io = dm365_evm_map_io, 833 .map_io = dm365_evm_map_io,
834 .init_irq = davinci_irq_init, 834 .init_irq = dm365_init_irq,
835 .init_time = dm365_init_time, 835 .init_time = dm365_init_time,
836 .init_machine = dm365_evm_init, 836 .init_machine = dm365_evm_init,
837 .init_late = davinci_init_late, 837 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index ecd30643c2c4..de15f782816e 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -36,9 +36,10 @@
36#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
37 37
38#include <mach/common.h> 38#include <mach/common.h>
39#include <linux/platform_data/i2c-davinci.h>
40#include <mach/serial.h>
41#include <mach/mux.h> 39#include <mach/mux.h>
40#include <mach/serial.h>
41
42#include <linux/platform_data/i2c-davinci.h>
42#include <linux/platform_data/mtd-davinci.h> 43#include <linux/platform_data/mtd-davinci.h>
43#include <linux/platform_data/mmc-davinci.h> 44#include <linux/platform_data/mmc-davinci.h>
44#include <linux/platform_data/usb-davinci.h> 45#include <linux/platform_data/usb-davinci.h>
@@ -46,6 +47,7 @@
46#include <linux/platform_data/ti-aemif.h> 47#include <linux/platform_data/ti-aemif.h>
47 48
48#include "davinci.h" 49#include "davinci.h"
50#include "irqs.h"
49 51
50#define DM644X_EVM_PHY_ID "davinci_mdio-0:01" 52#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
51#define LXT971_PHY_ID (0x001378e2) 53#define LXT971_PHY_ID (0x001378e2)
@@ -886,7 +888,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
886 /* Maintainer: MontaVista Software <source@mvista.com> */ 888 /* Maintainer: MontaVista Software <source@mvista.com> */
887 .atag_offset = 0x100, 889 .atag_offset = 0x100,
888 .map_io = davinci_evm_map_io, 890 .map_io = davinci_evm_map_io,
889 .init_irq = davinci_irq_init, 891 .init_irq = dm644x_init_irq,
890 .init_time = dm644x_init_time, 892 .init_time = dm644x_init_time,
891 .init_machine = davinci_evm_init, 893 .init_machine = davinci_evm_init,
892 .init_late = davinci_init_late, 894 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 02b57face113..4600b617f9b4 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -44,10 +44,10 @@
44#include <asm/mach/arch.h> 44#include <asm/mach/arch.h>
45 45
46#include <mach/common.h> 46#include <mach/common.h>
47#include <mach/irqs.h>
48#include <mach/serial.h> 47#include <mach/serial.h>
49 48
50#include "davinci.h" 49#include "davinci.h"
50#include "irqs.h"
51 51
52#define NAND_BLOCK_SIZE SZ_128K 52#define NAND_BLOCK_SIZE SZ_128K
53 53
@@ -860,7 +860,7 @@ static __init void evm_init(void)
860MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") 860MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
861 .atag_offset = 0x100, 861 .atag_offset = 0x100,
862 .map_io = davinci_map_io, 862 .map_io = davinci_map_io,
863 .init_irq = davinci_irq_init, 863 .init_irq = dm646x_init_irq,
864 .init_time = dm646x_evm_init_time, 864 .init_time = dm646x_evm_init_time,
865 .init_machine = evm_init, 865 .init_machine = evm_init,
866 .init_late = davinci_init_late, 866 .init_late = davinci_init_late,
@@ -870,7 +870,7 @@ MACHINE_END
870MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") 870MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
871 .atag_offset = 0x100, 871 .atag_offset = 0x100,
872 .map_io = davinci_map_io, 872 .map_io = davinci_map_io,
873 .init_irq = davinci_irq_init, 873 .init_irq = dm646x_init_irq,
874 .init_time = dm6467t_evm_init_time, 874 .init_time = dm6467t_evm_init_time,
875 .init_machine = evm_init, 875 .init_machine = evm_init,
876 .init_late = davinci_init_late, 876 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index a381b26328d8..dfce421c0579 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -29,7 +29,6 @@
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
31#include <mach/common.h> 31#include <mach/common.h>
32#include "cp_intc.h"
33#include <mach/da8xx.h> 32#include <mach/da8xx.h>
34#include <linux/platform_data/mtd-davinci.h> 33#include <linux/platform_data/mtd-davinci.h>
35#include <linux/platform_data/mtd-davinci-aemif.h> 34#include <linux/platform_data/mtd-davinci-aemif.h>
@@ -628,7 +627,7 @@ static void __init mityomapl138_map_io(void)
628MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") 627MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
629 .atag_offset = 0x100, 628 .atag_offset = 0x100,
630 .map_io = mityomapl138_map_io, 629 .map_io = mityomapl138_map_io,
631 .init_irq = cp_intc_init, 630 .init_irq = da850_init_irq,
632 .init_time = da850_init_time, 631 .init_time = da850_init_time,
633 .init_machine = mityomapl138_init, 632 .init_machine = mityomapl138_init,
634 .init_late = davinci_init_late, 633 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index efdaa27241c5..ce99f782811a 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -231,7 +231,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
231 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */ 231 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
232 .atag_offset = 0x100, 232 .atag_offset = 0x100,
233 .map_io = davinci_ntosd2_map_io, 233 .map_io = davinci_ntosd2_map_io,
234 .init_irq = davinci_irq_init, 234 .init_irq = dm644x_init_irq,
235 .init_time = dm644x_init_time, 235 .init_time = dm644x_init_time,
236 .init_machine = davinci_ntosd2_init, 236 .init_machine = davinci_ntosd2_init,
237 .init_late = davinci_init_late, 237 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 88a0c62eee86..0896af2bed24 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -27,7 +27,6 @@
27#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
28 28
29#include <mach/common.h> 29#include <mach/common.h>
30#include "cp_intc.h"
31#include <mach/da8xx.h> 30#include <mach/da8xx.h>
32#include <mach/mux.h> 31#include <mach/mux.h>
33 32
@@ -399,7 +398,7 @@ static void __init omapl138_hawk_map_io(void)
399MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") 398MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
400 .atag_offset = 0x100, 399 .atag_offset = 0x100,
401 .map_io = omapl138_hawk_map_io, 400 .map_io = omapl138_hawk_map_io,
402 .init_irq = cp_intc_init, 401 .init_irq = da850_init_irq,
403 .init_time = da850_init_time, 402 .init_time = da850_init_time,
404 .init_machine = omapl138_hawk_init, 403 .init_machine = omapl138_hawk_init,
405 .init_late = davinci_init_late, 404 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index ff14de1396c8..bcdefde2f401 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -152,7 +152,7 @@ static __init void davinci_sffsdr_init(void)
152MACHINE_START(SFFSDR, "Lyrtech SFFSDR") 152MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
153 .atag_offset = 0x100, 153 .atag_offset = 0x100,
154 .map_io = davinci_sffsdr_map_io, 154 .map_io = davinci_sffsdr_map_io,
155 .init_irq = davinci_irq_init, 155 .init_irq = dm644x_init_irq,
156 .init_time = dm644x_init_time, 156 .init_time = dm644x_init_time,
157 .init_machine = davinci_sffsdr_init, 157 .init_machine = davinci_sffsdr_init,
158 .init_late = davinci_init_late, 158 .init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 0c638fe15dcb..ae61d19f9b3a 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -23,9 +23,6 @@
23struct davinci_soc_info davinci_soc_info; 23struct davinci_soc_info davinci_soc_info;
24EXPORT_SYMBOL(davinci_soc_info); 24EXPORT_SYMBOL(davinci_soc_info);
25 25
26void __iomem *davinci_intc_base;
27int davinci_intc_type;
28
29static int __init davinci_init_id(struct davinci_soc_info *soc_info) 26static int __init davinci_init_id(struct davinci_soc_info *soc_info)
30{ 27{
31 int i; 28 int i;
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
deleted file mode 100644
index 94085d21018e..000000000000
--- a/arch/arm/mach-davinci/cp_intc.c
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * TI Common Platform Interrupt Controller (cp_intc) driver
3 *
4 * Author: Steve Chen <schen@mvista.com>
5 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/irq.h>
15#include <linux/irqchip.h>
16#include <linux/irqdomain.h>
17#include <linux/io.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21
22#include <mach/common.h>
23#include "cp_intc.h"
24
25static inline unsigned int cp_intc_read(unsigned offset)
26{
27 return __raw_readl(davinci_intc_base + offset);
28}
29
30static inline void cp_intc_write(unsigned long value, unsigned offset)
31{
32 __raw_writel(value, davinci_intc_base + offset);
33}
34
35static void cp_intc_ack_irq(struct irq_data *d)
36{
37 cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
38}
39
40/* Disable interrupt */
41static void cp_intc_mask_irq(struct irq_data *d)
42{
43 /* XXX don't know why we need to disable nIRQ here... */
44 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
45 cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
46 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
47}
48
49/* Enable interrupt */
50static void cp_intc_unmask_irq(struct irq_data *d)
51{
52 cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
53}
54
55static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
56{
57 unsigned reg = BIT_WORD(d->hwirq);
58 unsigned mask = BIT_MASK(d->hwirq);
59 unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
60 unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
61
62 switch (flow_type) {
63 case IRQ_TYPE_EDGE_RISING:
64 polarity |= mask;
65 type |= mask;
66 break;
67 case IRQ_TYPE_EDGE_FALLING:
68 polarity &= ~mask;
69 type |= mask;
70 break;
71 case IRQ_TYPE_LEVEL_HIGH:
72 polarity |= mask;
73 type &= ~mask;
74 break;
75 case IRQ_TYPE_LEVEL_LOW:
76 polarity &= ~mask;
77 type &= ~mask;
78 break;
79 default:
80 return -EINVAL;
81 }
82
83 cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
84 cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
85
86 return 0;
87}
88
89static struct irq_chip cp_intc_irq_chip = {
90 .name = "cp_intc",
91 .irq_ack = cp_intc_ack_irq,
92 .irq_mask = cp_intc_mask_irq,
93 .irq_unmask = cp_intc_unmask_irq,
94 .irq_set_type = cp_intc_set_irq_type,
95 .flags = IRQCHIP_SKIP_SET_WAKE,
96};
97
98static struct irq_domain *cp_intc_domain;
99
100static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
101 irq_hw_number_t hw)
102{
103 pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
104
105 irq_set_chip(virq, &cp_intc_irq_chip);
106 irq_set_probe(virq);
107 irq_set_handler(virq, handle_edge_irq);
108 return 0;
109}
110
111static const struct irq_domain_ops cp_intc_host_ops = {
112 .map = cp_intc_host_map,
113 .xlate = irq_domain_xlate_onetwocell,
114};
115
116int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
117{
118 u32 num_irq = davinci_soc_info.intc_irq_num;
119 u8 *irq_prio = davinci_soc_info.intc_irq_prios;
120 u32 *host_map = davinci_soc_info.intc_host_map;
121 unsigned num_reg = BITS_TO_LONGS(num_irq);
122 int i, irq_base;
123
124 davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
125 if (node) {
126 davinci_intc_base = of_iomap(node, 0);
127 if (of_property_read_u32(node, "ti,intc-size", &num_irq))
128 pr_warn("unable to get intc-size, default to %d\n",
129 num_irq);
130 } else {
131 davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
132 }
133 if (WARN_ON(!davinci_intc_base))
134 return -EINVAL;
135
136 cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
137
138 /* Disable all host interrupts */
139 cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
140
141 /* Disable system interrupts */
142 for (i = 0; i < num_reg; i++)
143 cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
144
145 /* Set to normal mode, no nesting, no priority hold */
146 cp_intc_write(0, CP_INTC_CTRL);
147 cp_intc_write(0, CP_INTC_HOST_CTRL);
148
149 /* Clear system interrupt status */
150 for (i = 0; i < num_reg; i++)
151 cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
152
153 /* Enable nIRQ (what about nFIQ?) */
154 cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
155
156 /*
157 * Priority is determined by host channel: lower channel number has
158 * higher priority i.e. channel 0 has highest priority and channel 31
159 * had the lowest priority.
160 */
161 num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
162 if (irq_prio) {
163 unsigned j, k;
164 u32 val;
165
166 for (k = i = 0; i < num_reg; i++) {
167 for (val = j = 0; j < 4; j++, k++) {
168 val >>= 8;
169 if (k < num_irq)
170 val |= irq_prio[k] << 24;
171 }
172
173 cp_intc_write(val, CP_INTC_CHAN_MAP(i));
174 }
175 } else {
176 /*
177 * Default everything to channel 15 if priority not specified.
178 * Note that channel 0-1 are mapped to nFIQ and channels 2-31
179 * are mapped to nIRQ.
180 */
181 for (i = 0; i < num_reg; i++)
182 cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
183 }
184
185 if (host_map)
186 for (i = 0; host_map[i] != -1; i++)
187 cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
188
189 irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
190 if (irq_base < 0) {
191 pr_warn("Couldn't allocate IRQ numbers\n");
192 irq_base = 0;
193 }
194
195 /* create a legacy host */
196 cp_intc_domain = irq_domain_add_legacy(node, num_irq,
197 irq_base, 0, &cp_intc_host_ops, NULL);
198
199 if (!cp_intc_domain) {
200 pr_err("cp_intc: failed to allocate irq host!\n");
201 return -EINVAL;
202 }
203
204 /* Enable global interrupt */
205 cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
206
207 return 0;
208}
209
210void __init cp_intc_init(void)
211{
212 cp_intc_of_init(NULL, NULL);
213}
214
215IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", cp_intc_of_init);
diff --git a/arch/arm/mach-davinci/cp_intc.h b/arch/arm/mach-davinci/cp_intc.h
deleted file mode 100644
index 827bbe9baed4..000000000000
--- a/arch/arm/mach-davinci/cp_intc.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * TI Common Platform Interrupt Controller (cp_intc) definitions
3 *
4 * Author: Steve Chen <schen@mvista.com>
5 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11#ifndef __ASM_HARDWARE_CP_INTC_H
12#define __ASM_HARDWARE_CP_INTC_H
13
14#define CP_INTC_REV 0x00
15#define CP_INTC_CTRL 0x04
16#define CP_INTC_HOST_CTRL 0x0C
17#define CP_INTC_GLOBAL_ENABLE 0x10
18#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C
19#define CP_INTC_SYS_STAT_IDX_SET 0x20
20#define CP_INTC_SYS_STAT_IDX_CLR 0x24
21#define CP_INTC_SYS_ENABLE_IDX_SET 0x28
22#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
23#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30
24#define CP_INTC_HOST_ENABLE_IDX_SET 0x34
25#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38
26#define CP_INTC_PACING_PRESCALE 0x40
27#define CP_INTC_VECTOR_BASE 0x50
28#define CP_INTC_VECTOR_SIZE 0x54
29#define CP_INTC_VECTOR_NULL 0x58
30#define CP_INTC_PRIO_IDX 0x80
31#define CP_INTC_PRIO_VECTOR 0x84
32#define CP_INTC_SECURE_ENABLE 0x90
33#define CP_INTC_SECURE_PRIO_IDX 0x94
34#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4))
35#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4))
36#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4))
37#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2))
38#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
39#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2))
40#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
41#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
42#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2))
43#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2))
44#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
45#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
46#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2))
47#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2))
48#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2))
49#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2))
50#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
51#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
53
54void cp_intc_init(void);
55int cp_intc_of_init(struct device_node *, struct device_node *);
56
57#endif /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 2cc9fe4c3a91..63511f638ce4 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -12,6 +12,7 @@
12#include <linux/clk/davinci.h> 12#include <linux/clk/davinci.h>
13#include <linux/gpio.h> 13#include <linux/gpio.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/irqchip/irq-davinci-cp-intc.h>
15#include <linux/platform_data/gpio-davinci.h> 16#include <linux/platform_data/gpio-davinci.h>
16 17
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
@@ -19,9 +20,9 @@
19#include <mach/common.h> 20#include <mach/common.h>
20#include <mach/cputype.h> 21#include <mach/cputype.h>
21#include <mach/da8xx.h> 22#include <mach/da8xx.h>
22#include <mach/irqs.h>
23#include <mach/time.h> 23#include <mach/time.h>
24 24
25#include "irqs.h"
25#include "mux.h" 26#include "mux.h"
26 27
27/* Offsets of the 8 compare registers on the da830 */ 28/* Offsets of the 8 compare registers on the da830 */
@@ -623,101 +624,6 @@ const short da830_eqep1_pins[] __initconst = {
623 -1 624 -1
624}; 625};
625 626
626/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
627static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
628 [IRQ_DA8XX_COMMTX] = 7,
629 [IRQ_DA8XX_COMMRX] = 7,
630 [IRQ_DA8XX_NINT] = 7,
631 [IRQ_DA8XX_EVTOUT0] = 7,
632 [IRQ_DA8XX_EVTOUT1] = 7,
633 [IRQ_DA8XX_EVTOUT2] = 7,
634 [IRQ_DA8XX_EVTOUT3] = 7,
635 [IRQ_DA8XX_EVTOUT4] = 7,
636 [IRQ_DA8XX_EVTOUT5] = 7,
637 [IRQ_DA8XX_EVTOUT6] = 7,
638 [IRQ_DA8XX_EVTOUT7] = 7,
639 [IRQ_DA8XX_CCINT0] = 7,
640 [IRQ_DA8XX_CCERRINT] = 7,
641 [IRQ_DA8XX_TCERRINT0] = 7,
642 [IRQ_DA8XX_AEMIFINT] = 7,
643 [IRQ_DA8XX_I2CINT0] = 7,
644 [IRQ_DA8XX_MMCSDINT0] = 7,
645 [IRQ_DA8XX_MMCSDINT1] = 7,
646 [IRQ_DA8XX_ALLINT0] = 7,
647 [IRQ_DA8XX_RTC] = 7,
648 [IRQ_DA8XX_SPINT0] = 7,
649 [IRQ_DA8XX_TINT12_0] = 7,
650 [IRQ_DA8XX_TINT34_0] = 7,
651 [IRQ_DA8XX_TINT12_1] = 7,
652 [IRQ_DA8XX_TINT34_1] = 7,
653 [IRQ_DA8XX_UARTINT0] = 7,
654 [IRQ_DA8XX_KEYMGRINT] = 7,
655 [IRQ_DA830_MPUERR] = 7,
656 [IRQ_DA8XX_CHIPINT0] = 7,
657 [IRQ_DA8XX_CHIPINT1] = 7,
658 [IRQ_DA8XX_CHIPINT2] = 7,
659 [IRQ_DA8XX_CHIPINT3] = 7,
660 [IRQ_DA8XX_TCERRINT1] = 7,
661 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
662 [IRQ_DA8XX_C0_RX_PULSE] = 7,
663 [IRQ_DA8XX_C0_TX_PULSE] = 7,
664 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
665 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
666 [IRQ_DA8XX_C1_RX_PULSE] = 7,
667 [IRQ_DA8XX_C1_TX_PULSE] = 7,
668 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
669 [IRQ_DA8XX_MEMERR] = 7,
670 [IRQ_DA8XX_GPIO0] = 7,
671 [IRQ_DA8XX_GPIO1] = 7,
672 [IRQ_DA8XX_GPIO2] = 7,
673 [IRQ_DA8XX_GPIO3] = 7,
674 [IRQ_DA8XX_GPIO4] = 7,
675 [IRQ_DA8XX_GPIO5] = 7,
676 [IRQ_DA8XX_GPIO6] = 7,
677 [IRQ_DA8XX_GPIO7] = 7,
678 [IRQ_DA8XX_GPIO8] = 7,
679 [IRQ_DA8XX_I2CINT1] = 7,
680 [IRQ_DA8XX_LCDINT] = 7,
681 [IRQ_DA8XX_UARTINT1] = 7,
682 [IRQ_DA8XX_MCASPINT] = 7,
683 [IRQ_DA8XX_ALLINT1] = 7,
684 [IRQ_DA8XX_SPINT1] = 7,
685 [IRQ_DA8XX_UHPI_INT1] = 7,
686 [IRQ_DA8XX_USB_INT] = 7,
687 [IRQ_DA8XX_IRQN] = 7,
688 [IRQ_DA8XX_RWAKEUP] = 7,
689 [IRQ_DA8XX_UARTINT2] = 7,
690 [IRQ_DA8XX_DFTSSINT] = 7,
691 [IRQ_DA8XX_EHRPWM0] = 7,
692 [IRQ_DA8XX_EHRPWM0TZ] = 7,
693 [IRQ_DA8XX_EHRPWM1] = 7,
694 [IRQ_DA8XX_EHRPWM1TZ] = 7,
695 [IRQ_DA830_EHRPWM2] = 7,
696 [IRQ_DA830_EHRPWM2TZ] = 7,
697 [IRQ_DA8XX_ECAP0] = 7,
698 [IRQ_DA8XX_ECAP1] = 7,
699 [IRQ_DA8XX_ECAP2] = 7,
700 [IRQ_DA830_EQEP0] = 7,
701 [IRQ_DA830_EQEP1] = 7,
702 [IRQ_DA830_T12CMPINT0_0] = 7,
703 [IRQ_DA830_T12CMPINT1_0] = 7,
704 [IRQ_DA830_T12CMPINT2_0] = 7,
705 [IRQ_DA830_T12CMPINT3_0] = 7,
706 [IRQ_DA830_T12CMPINT4_0] = 7,
707 [IRQ_DA830_T12CMPINT5_0] = 7,
708 [IRQ_DA830_T12CMPINT6_0] = 7,
709 [IRQ_DA830_T12CMPINT7_0] = 7,
710 [IRQ_DA830_T12CMPINT0_1] = 7,
711 [IRQ_DA830_T12CMPINT1_1] = 7,
712 [IRQ_DA830_T12CMPINT2_1] = 7,
713 [IRQ_DA830_T12CMPINT3_1] = 7,
714 [IRQ_DA830_T12CMPINT4_1] = 7,
715 [IRQ_DA830_T12CMPINT5_1] = 7,
716 [IRQ_DA830_T12CMPINT6_1] = 7,
717 [IRQ_DA830_T12CMPINT7_1] = 7,
718 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
719};
720
721static struct map_desc da830_io_desc[] = { 627static struct map_desc da830_io_desc[] = {
722 { 628 {
723 .virtual = IO_VIRT, 629 .virtual = IO_VIRT,
@@ -772,17 +678,17 @@ int __init da830_register_gpio(void)
772static struct davinci_timer_instance da830_timer_instance[2] = { 678static struct davinci_timer_instance da830_timer_instance[2] = {
773 { 679 {
774 .base = DA8XX_TIMER64P0_BASE, 680 .base = DA8XX_TIMER64P0_BASE,
775 .bottom_irq = IRQ_DA8XX_TINT12_0, 681 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
776 .top_irq = IRQ_DA8XX_TINT34_0, 682 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
777 .cmp_off = DA830_CMP12_0, 683 .cmp_off = DA830_CMP12_0,
778 .cmp_irq = IRQ_DA830_T12CMPINT0_0, 684 .cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0),
779 }, 685 },
780 { 686 {
781 .base = DA8XX_TIMER64P1_BASE, 687 .base = DA8XX_TIMER64P1_BASE,
782 .bottom_irq = IRQ_DA8XX_TINT12_1, 688 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
783 .top_irq = IRQ_DA8XX_TINT34_1, 689 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
784 .cmp_off = DA830_CMP12_0, 690 .cmp_off = DA830_CMP12_0,
785 .cmp_irq = IRQ_DA830_T12CMPINT0_1, 691 .cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_1),
786 }, 692 },
787}; 693};
788 694
@@ -806,10 +712,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
806 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, 712 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
807 .pinmux_pins = da830_pins, 713 .pinmux_pins = da830_pins,
808 .pinmux_pins_num = ARRAY_SIZE(da830_pins), 714 .pinmux_pins_num = ARRAY_SIZE(da830_pins),
809 .intc_base = DA8XX_CP_INTC_BASE,
810 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
811 .intc_irq_prios = da830_default_priorities,
812 .intc_irq_num = DA830_N_CP_INTC_IRQ,
813 .timer_info = &da830_timer_info, 715 .timer_info = &da830_timer_info,
814 .emac_pdata = &da8xx_emac_pdata, 716 .emac_pdata = &da8xx_emac_pdata,
815}; 717};
@@ -822,6 +724,20 @@ void __init da830_init(void)
822 WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); 724 WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
823} 725}
824 726
727static const struct davinci_cp_intc_config da830_cp_intc_config = {
728 .reg = {
729 .start = DA8XX_CP_INTC_BASE,
730 .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
731 .flags = IORESOURCE_MEM,
732 },
733 .num_irqs = DA830_N_CP_INTC_IRQ,
734};
735
736void __init da830_init_irq(void)
737{
738 davinci_cp_intc_init(&da830_cp_intc_config);
739}
740
825void __init da830_init_time(void) 741void __init da830_init_time(void)
826{ 742{
827 void __iomem *pll; 743 void __iomem *pll;
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index e7b78df2bfef..8a50956a9181 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -18,6 +18,7 @@
18#include <linux/cpufreq.h> 18#include <linux/cpufreq.h>
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/irqchip/irq-davinci-cp-intc.h>
21#include <linux/mfd/da8xx-cfgchip.h> 22#include <linux/mfd/da8xx-cfgchip.h>
22#include <linux/platform_data/clk-da8xx-cfgchip.h> 23#include <linux/platform_data/clk-da8xx-cfgchip.h>
23#include <linux/platform_data/clk-davinci-pll.h> 24#include <linux/platform_data/clk-davinci-pll.h>
@@ -32,10 +33,10 @@
32#include <mach/cpufreq.h> 33#include <mach/cpufreq.h>
33#include <mach/cputype.h> 34#include <mach/cputype.h>
34#include <mach/da8xx.h> 35#include <mach/da8xx.h>
35#include <mach/irqs.h>
36#include <mach/pm.h> 36#include <mach/pm.h>
37#include <mach/time.h> 37#include <mach/time.h>
38 38
39#include "irqs.h"
39#include "mux.h" 40#include "mux.h"
40 41
41#define DA850_PLL1_BASE 0x01e1a000 42#define DA850_PLL1_BASE 0x01e1a000
@@ -298,111 +299,6 @@ const short da850_vpif_display_pins[] __initconst = {
298 -1 299 -1
299}; 300};
300 301
301/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
302static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
303 [IRQ_DA8XX_COMMTX] = 7,
304 [IRQ_DA8XX_COMMRX] = 7,
305 [IRQ_DA8XX_NINT] = 7,
306 [IRQ_DA8XX_EVTOUT0] = 7,
307 [IRQ_DA8XX_EVTOUT1] = 7,
308 [IRQ_DA8XX_EVTOUT2] = 7,
309 [IRQ_DA8XX_EVTOUT3] = 7,
310 [IRQ_DA8XX_EVTOUT4] = 7,
311 [IRQ_DA8XX_EVTOUT5] = 7,
312 [IRQ_DA8XX_EVTOUT6] = 7,
313 [IRQ_DA8XX_EVTOUT7] = 7,
314 [IRQ_DA8XX_CCINT0] = 7,
315 [IRQ_DA8XX_CCERRINT] = 7,
316 [IRQ_DA8XX_TCERRINT0] = 7,
317 [IRQ_DA8XX_AEMIFINT] = 7,
318 [IRQ_DA8XX_I2CINT0] = 7,
319 [IRQ_DA8XX_MMCSDINT0] = 7,
320 [IRQ_DA8XX_MMCSDINT1] = 7,
321 [IRQ_DA8XX_ALLINT0] = 7,
322 [IRQ_DA8XX_RTC] = 7,
323 [IRQ_DA8XX_SPINT0] = 7,
324 [IRQ_DA8XX_TINT12_0] = 7,
325 [IRQ_DA8XX_TINT34_0] = 7,
326 [IRQ_DA8XX_TINT12_1] = 7,
327 [IRQ_DA8XX_TINT34_1] = 7,
328 [IRQ_DA8XX_UARTINT0] = 7,
329 [IRQ_DA8XX_KEYMGRINT] = 7,
330 [IRQ_DA850_MPUADDRERR0] = 7,
331 [IRQ_DA8XX_CHIPINT0] = 7,
332 [IRQ_DA8XX_CHIPINT1] = 7,
333 [IRQ_DA8XX_CHIPINT2] = 7,
334 [IRQ_DA8XX_CHIPINT3] = 7,
335 [IRQ_DA8XX_TCERRINT1] = 7,
336 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
337 [IRQ_DA8XX_C0_RX_PULSE] = 7,
338 [IRQ_DA8XX_C0_TX_PULSE] = 7,
339 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
340 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
341 [IRQ_DA8XX_C1_RX_PULSE] = 7,
342 [IRQ_DA8XX_C1_TX_PULSE] = 7,
343 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
344 [IRQ_DA8XX_MEMERR] = 7,
345 [IRQ_DA8XX_GPIO0] = 7,
346 [IRQ_DA8XX_GPIO1] = 7,
347 [IRQ_DA8XX_GPIO2] = 7,
348 [IRQ_DA8XX_GPIO3] = 7,
349 [IRQ_DA8XX_GPIO4] = 7,
350 [IRQ_DA8XX_GPIO5] = 7,
351 [IRQ_DA8XX_GPIO6] = 7,
352 [IRQ_DA8XX_GPIO7] = 7,
353 [IRQ_DA8XX_GPIO8] = 7,
354 [IRQ_DA8XX_I2CINT1] = 7,
355 [IRQ_DA8XX_LCDINT] = 7,
356 [IRQ_DA8XX_UARTINT1] = 7,
357 [IRQ_DA8XX_MCASPINT] = 7,
358 [IRQ_DA8XX_ALLINT1] = 7,
359 [IRQ_DA8XX_SPINT1] = 7,
360 [IRQ_DA8XX_UHPI_INT1] = 7,
361 [IRQ_DA8XX_USB_INT] = 7,
362 [IRQ_DA8XX_IRQN] = 7,
363 [IRQ_DA8XX_RWAKEUP] = 7,
364 [IRQ_DA8XX_UARTINT2] = 7,
365 [IRQ_DA8XX_DFTSSINT] = 7,
366 [IRQ_DA8XX_EHRPWM0] = 7,
367 [IRQ_DA8XX_EHRPWM0TZ] = 7,
368 [IRQ_DA8XX_EHRPWM1] = 7,
369 [IRQ_DA8XX_EHRPWM1TZ] = 7,
370 [IRQ_DA850_SATAINT] = 7,
371 [IRQ_DA850_TINTALL_2] = 7,
372 [IRQ_DA8XX_ECAP0] = 7,
373 [IRQ_DA8XX_ECAP1] = 7,
374 [IRQ_DA8XX_ECAP2] = 7,
375 [IRQ_DA850_MMCSDINT0_1] = 7,
376 [IRQ_DA850_MMCSDINT1_1] = 7,
377 [IRQ_DA850_T12CMPINT0_2] = 7,
378 [IRQ_DA850_T12CMPINT1_2] = 7,
379 [IRQ_DA850_T12CMPINT2_2] = 7,
380 [IRQ_DA850_T12CMPINT3_2] = 7,
381 [IRQ_DA850_T12CMPINT4_2] = 7,
382 [IRQ_DA850_T12CMPINT5_2] = 7,
383 [IRQ_DA850_T12CMPINT6_2] = 7,
384 [IRQ_DA850_T12CMPINT7_2] = 7,
385 [IRQ_DA850_T12CMPINT0_3] = 7,
386 [IRQ_DA850_T12CMPINT1_3] = 7,
387 [IRQ_DA850_T12CMPINT2_3] = 7,
388 [IRQ_DA850_T12CMPINT3_3] = 7,
389 [IRQ_DA850_T12CMPINT4_3] = 7,
390 [IRQ_DA850_T12CMPINT5_3] = 7,
391 [IRQ_DA850_T12CMPINT6_3] = 7,
392 [IRQ_DA850_T12CMPINT7_3] = 7,
393 [IRQ_DA850_RPIINT] = 7,
394 [IRQ_DA850_VPIFINT] = 7,
395 [IRQ_DA850_CCINT1] = 7,
396 [IRQ_DA850_CCERRINT1] = 7,
397 [IRQ_DA850_TCERRINT2] = 7,
398 [IRQ_DA850_TINTALL_3] = 7,
399 [IRQ_DA850_MCBSP0RINT] = 7,
400 [IRQ_DA850_MCBSP0XINT] = 7,
401 [IRQ_DA850_MCBSP1RINT] = 7,
402 [IRQ_DA850_MCBSP1XINT] = 7,
403 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
404};
405
406static struct map_desc da850_io_desc[] = { 302static struct map_desc da850_io_desc[] = {
407 { 303 {
408 .virtual = IO_VIRT, 304 .virtual = IO_VIRT,
@@ -439,23 +335,23 @@ static struct davinci_id da850_ids[] = {
439static struct davinci_timer_instance da850_timer_instance[4] = { 335static struct davinci_timer_instance da850_timer_instance[4] = {
440 { 336 {
441 .base = DA8XX_TIMER64P0_BASE, 337 .base = DA8XX_TIMER64P0_BASE,
442 .bottom_irq = IRQ_DA8XX_TINT12_0, 338 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
443 .top_irq = IRQ_DA8XX_TINT34_0, 339 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
444 }, 340 },
445 { 341 {
446 .base = DA8XX_TIMER64P1_BASE, 342 .base = DA8XX_TIMER64P1_BASE,
447 .bottom_irq = IRQ_DA8XX_TINT12_1, 343 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
448 .top_irq = IRQ_DA8XX_TINT34_1, 344 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
449 }, 345 },
450 { 346 {
451 .base = DA850_TIMER64P2_BASE, 347 .base = DA850_TIMER64P2_BASE,
452 .bottom_irq = IRQ_DA850_TINT12_2, 348 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2),
453 .top_irq = IRQ_DA850_TINT34_2, 349 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2),
454 }, 350 },
455 { 351 {
456 .base = DA850_TIMER64P3_BASE, 352 .base = DA850_TIMER64P3_BASE,
457 .bottom_irq = IRQ_DA850_TINT12_3, 353 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3),
458 .top_irq = IRQ_DA850_TINT34_3, 354 .top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3),
459 }, 355 },
460}; 356};
461 357
@@ -658,8 +554,8 @@ static struct platform_device da850_vpif_dev = {
658 554
659static struct resource da850_vpif_display_resource[] = { 555static struct resource da850_vpif_display_resource[] = {
660 { 556 {
661 .start = IRQ_DA850_VPIFINT, 557 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
662 .end = IRQ_DA850_VPIFINT, 558 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
663 .flags = IORESOURCE_IRQ, 559 .flags = IORESOURCE_IRQ,
664 }, 560 },
665}; 561};
@@ -677,13 +573,13 @@ static struct platform_device da850_vpif_display_dev = {
677 573
678static struct resource da850_vpif_capture_resource[] = { 574static struct resource da850_vpif_capture_resource[] = {
679 { 575 {
680 .start = IRQ_DA850_VPIFINT, 576 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
681 .end = IRQ_DA850_VPIFINT, 577 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
682 .flags = IORESOURCE_IRQ, 578 .flags = IORESOURCE_IRQ,
683 }, 579 },
684 { 580 {
685 .start = IRQ_DA850_VPIFINT, 581 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
686 .end = IRQ_DA850_VPIFINT, 582 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
687 .flags = IORESOURCE_IRQ, 583 .flags = IORESOURCE_IRQ,
688 }, 584 },
689}; 585};
@@ -738,10 +634,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
738 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, 634 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
739 .pinmux_pins = da850_pins, 635 .pinmux_pins = da850_pins,
740 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 636 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
741 .intc_base = DA8XX_CP_INTC_BASE,
742 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
743 .intc_irq_prios = da850_default_priorities,
744 .intc_irq_num = DA850_N_CP_INTC_IRQ,
745 .timer_info = &da850_timer_info, 637 .timer_info = &da850_timer_info,
746 .emac_pdata = &da8xx_emac_pdata, 638 .emac_pdata = &da8xx_emac_pdata,
747 .sram_dma = DA8XX_SHARED_RAM_BASE, 639 .sram_dma = DA8XX_SHARED_RAM_BASE,
@@ -760,6 +652,20 @@ void __init da850_init(void)
760 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); 652 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
761} 653}
762 654
655static const struct davinci_cp_intc_config da850_cp_intc_config = {
656 .reg = {
657 .start = DA8XX_CP_INTC_BASE,
658 .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
659 .flags = IORESOURCE_MEM,
660 },
661 .num_irqs = DA850_N_CP_INTC_IRQ,
662};
663
664void __init da850_init_irq(void)
665{
666 davinci_cp_intc_init(&da850_cp_intc_config);
667}
668
763void __init da850_init_time(void) 669void __init da850_init_time(void)
764{ 670{
765 void __iomem *pll0; 671 void __iomem *pll0;
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index db4c95ef4d5c..56c1835c42e5 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -88,6 +88,7 @@ int davinci_init_wdt(void);
88/* DM355 function declarations */ 88/* DM355 function declarations */
89void dm355_init(void); 89void dm355_init(void);
90void dm355_init_time(void); 90void dm355_init_time(void);
91void dm355_init_irq(void);
91void dm355_register_clocks(void); 92void dm355_register_clocks(void);
92void dm355_init_spi0(unsigned chipselect_mask, 93void dm355_init_spi0(unsigned chipselect_mask,
93 const struct spi_board_info *info, unsigned len); 94 const struct spi_board_info *info, unsigned len);
@@ -97,6 +98,7 @@ int dm355_gpio_register(void);
97 98
98/* DM365 function declarations */ 99/* DM365 function declarations */
99void dm365_init(void); 100void dm365_init(void);
101void dm365_init_irq(void);
100void dm365_init_time(void); 102void dm365_init_time(void);
101void dm365_register_clocks(void); 103void dm365_register_clocks(void);
102void dm365_init_asp(void); 104void dm365_init_asp(void);
@@ -110,6 +112,7 @@ int dm365_gpio_register(void);
110 112
111/* DM644x function declarations */ 113/* DM644x function declarations */
112void dm644x_init(void); 114void dm644x_init(void);
115void dm644x_init_irq(void);
113void dm644x_init_devices(void); 116void dm644x_init_devices(void);
114void dm644x_init_time(void); 117void dm644x_init_time(void);
115void dm644x_register_clocks(void); 118void dm644x_register_clocks(void);
@@ -119,6 +122,7 @@ int dm644x_gpio_register(void);
119 122
120/* DM646x function declarations */ 123/* DM646x function declarations */
121void dm646x_init(void); 124void dm646x_init(void);
125void dm646x_init_irq(void);
122void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate); 126void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
123void dm646x_register_clocks(void); 127void dm646x_register_clocks(void);
124void dm646x_init_mcasp0(struct snd_platform_data *pdata); 128void dm646x_init_mcasp0(struct snd_platform_data *pdata);
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index cf78da5ab054..b8dc674e06bc 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -28,6 +28,7 @@
28 28
29#include "asp.h" 29#include "asp.h"
30#include "cpuidle.h" 30#include "cpuidle.h"
31#include "irqs.h"
31#include "sram.h" 32#include "sram.h"
32 33
33#define DA8XX_TPCC_BASE 0x01c00000 34#define DA8XX_TPCC_BASE 0x01c00000
@@ -64,7 +65,7 @@ void __iomem *da8xx_syscfg1_base;
64static struct plat_serial8250_port da8xx_serial0_pdata[] = { 65static struct plat_serial8250_port da8xx_serial0_pdata[] = {
65 { 66 {
66 .mapbase = DA8XX_UART0_BASE, 67 .mapbase = DA8XX_UART0_BASE,
67 .irq = IRQ_DA8XX_UARTINT0, 68 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 69 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
69 UPF_IOREMAP, 70 UPF_IOREMAP,
70 .iotype = UPIO_MEM, 71 .iotype = UPIO_MEM,
@@ -77,7 +78,7 @@ static struct plat_serial8250_port da8xx_serial0_pdata[] = {
77static struct plat_serial8250_port da8xx_serial1_pdata[] = { 78static struct plat_serial8250_port da8xx_serial1_pdata[] = {
78 { 79 {
79 .mapbase = DA8XX_UART1_BASE, 80 .mapbase = DA8XX_UART1_BASE,
80 .irq = IRQ_DA8XX_UARTINT1, 81 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
81 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 82 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
82 UPF_IOREMAP, 83 UPF_IOREMAP,
83 .iotype = UPIO_MEM, 84 .iotype = UPIO_MEM,
@@ -90,7 +91,7 @@ static struct plat_serial8250_port da8xx_serial1_pdata[] = {
90static struct plat_serial8250_port da8xx_serial2_pdata[] = { 91static struct plat_serial8250_port da8xx_serial2_pdata[] = {
91 { 92 {
92 .mapbase = DA8XX_UART2_BASE, 93 .mapbase = DA8XX_UART2_BASE,
93 .irq = IRQ_DA8XX_UARTINT2, 94 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
94 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 95 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
95 UPF_IOREMAP, 96 UPF_IOREMAP,
96 .iotype = UPIO_MEM, 97 .iotype = UPIO_MEM,
@@ -171,12 +172,12 @@ static struct resource da8xx_edma0_resources[] = {
171 }, 172 },
172 { 173 {
173 .name = "edma3_ccint", 174 .name = "edma3_ccint",
174 .start = IRQ_DA8XX_CCINT0, 175 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
175 .flags = IORESOURCE_IRQ, 176 .flags = IORESOURCE_IRQ,
176 }, 177 },
177 { 178 {
178 .name = "edma3_ccerrint", 179 .name = "edma3_ccerrint",
179 .start = IRQ_DA8XX_CCERRINT, 180 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
180 .flags = IORESOURCE_IRQ, 181 .flags = IORESOURCE_IRQ,
181 }, 182 },
182}; 183};
@@ -196,12 +197,12 @@ static struct resource da850_edma1_resources[] = {
196 }, 197 },
197 { 198 {
198 .name = "edma3_ccint", 199 .name = "edma3_ccint",
199 .start = IRQ_DA850_CCINT1, 200 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
200 .flags = IORESOURCE_IRQ, 201 .flags = IORESOURCE_IRQ,
201 }, 202 },
202 { 203 {
203 .name = "edma3_ccerrint", 204 .name = "edma3_ccerrint",
204 .start = IRQ_DA850_CCERRINT1, 205 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
205 .flags = IORESOURCE_IRQ, 206 .flags = IORESOURCE_IRQ,
206 }, 207 },
207}; 208};
@@ -306,8 +307,8 @@ static struct resource da8xx_i2c_resources0[] = {
306 .flags = IORESOURCE_MEM, 307 .flags = IORESOURCE_MEM,
307 }, 308 },
308 { 309 {
309 .start = IRQ_DA8XX_I2CINT0, 310 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
310 .end = IRQ_DA8XX_I2CINT0, 311 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
311 .flags = IORESOURCE_IRQ, 312 .flags = IORESOURCE_IRQ,
312 }, 313 },
313}; 314};
@@ -326,8 +327,8 @@ static struct resource da8xx_i2c_resources1[] = {
326 .flags = IORESOURCE_MEM, 327 .flags = IORESOURCE_MEM,
327 }, 328 },
328 { 329 {
329 .start = IRQ_DA8XX_I2CINT1, 330 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
330 .end = IRQ_DA8XX_I2CINT1, 331 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
331 .flags = IORESOURCE_IRQ, 332 .flags = IORESOURCE_IRQ,
332 }, 333 },
333}; 334};
@@ -382,23 +383,23 @@ static struct resource da8xx_emac_resources[] = {
382 .flags = IORESOURCE_MEM, 383 .flags = IORESOURCE_MEM,
383 }, 384 },
384 { 385 {
385 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, 386 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
386 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, 387 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
387 .flags = IORESOURCE_IRQ, 388 .flags = IORESOURCE_IRQ,
388 }, 389 },
389 { 390 {
390 .start = IRQ_DA8XX_C0_RX_PULSE, 391 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
391 .end = IRQ_DA8XX_C0_RX_PULSE, 392 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
392 .flags = IORESOURCE_IRQ, 393 .flags = IORESOURCE_IRQ,
393 }, 394 },
394 { 395 {
395 .start = IRQ_DA8XX_C0_TX_PULSE, 396 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
396 .end = IRQ_DA8XX_C0_TX_PULSE, 397 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
397 .flags = IORESOURCE_IRQ, 398 .flags = IORESOURCE_IRQ,
398 }, 399 },
399 { 400 {
400 .start = IRQ_DA8XX_C0_MISC_PULSE, 401 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
401 .end = IRQ_DA8XX_C0_MISC_PULSE, 402 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
402 .flags = IORESOURCE_IRQ, 403 .flags = IORESOURCE_IRQ,
403 }, 404 },
404}; 405};
@@ -470,7 +471,7 @@ static struct resource da830_mcasp1_resources[] = {
470 }, 471 },
471 { 472 {
472 .name = "common", 473 .name = "common",
473 .start = IRQ_DA8XX_MCASPINT, 474 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
474 .flags = IORESOURCE_IRQ, 475 .flags = IORESOURCE_IRQ,
475 }, 476 },
476}; 477};
@@ -505,7 +506,7 @@ static struct resource da830_mcasp2_resources[] = {
505 }, 506 },
506 { 507 {
507 .name = "common", 508 .name = "common",
508 .start = IRQ_DA8XX_MCASPINT, 509 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
509 .flags = IORESOURCE_IRQ, 510 .flags = IORESOURCE_IRQ,
510 }, 511 },
511}; 512};
@@ -540,7 +541,7 @@ static struct resource da850_mcasp_resources[] = {
540 }, 541 },
541 { 542 {
542 .name = "common", 543 .name = "common",
543 .start = IRQ_DA8XX_MCASPINT, 544 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
544 .flags = IORESOURCE_IRQ, 545 .flags = IORESOURCE_IRQ,
545 }, 546 },
546}; 547};
@@ -588,43 +589,43 @@ static struct resource da8xx_pruss_resources[] = {
588 .flags = IORESOURCE_MEM, 589 .flags = IORESOURCE_MEM,
589 }, 590 },
590 { 591 {
591 .start = IRQ_DA8XX_EVTOUT0, 592 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
592 .end = IRQ_DA8XX_EVTOUT0, 593 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
593 .flags = IORESOURCE_IRQ, 594 .flags = IORESOURCE_IRQ,
594 }, 595 },
595 { 596 {
596 .start = IRQ_DA8XX_EVTOUT1, 597 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
597 .end = IRQ_DA8XX_EVTOUT1, 598 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
598 .flags = IORESOURCE_IRQ, 599 .flags = IORESOURCE_IRQ,
599 }, 600 },
600 { 601 {
601 .start = IRQ_DA8XX_EVTOUT2, 602 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
602 .end = IRQ_DA8XX_EVTOUT2, 603 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
603 .flags = IORESOURCE_IRQ, 604 .flags = IORESOURCE_IRQ,
604 }, 605 },
605 { 606 {
606 .start = IRQ_DA8XX_EVTOUT3, 607 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
607 .end = IRQ_DA8XX_EVTOUT3, 608 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
608 .flags = IORESOURCE_IRQ, 609 .flags = IORESOURCE_IRQ,
609 }, 610 },
610 { 611 {
611 .start = IRQ_DA8XX_EVTOUT4, 612 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
612 .end = IRQ_DA8XX_EVTOUT4, 613 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
613 .flags = IORESOURCE_IRQ, 614 .flags = IORESOURCE_IRQ,
614 }, 615 },
615 { 616 {
616 .start = IRQ_DA8XX_EVTOUT5, 617 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
617 .end = IRQ_DA8XX_EVTOUT5, 618 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
618 .flags = IORESOURCE_IRQ, 619 .flags = IORESOURCE_IRQ,
619 }, 620 },
620 { 621 {
621 .start = IRQ_DA8XX_EVTOUT6, 622 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
622 .end = IRQ_DA8XX_EVTOUT6, 623 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
623 .flags = IORESOURCE_IRQ, 624 .flags = IORESOURCE_IRQ,
624 }, 625 },
625 { 626 {
626 .start = IRQ_DA8XX_EVTOUT7, 627 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
627 .end = IRQ_DA8XX_EVTOUT7, 628 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
628 .flags = IORESOURCE_IRQ, 629 .flags = IORESOURCE_IRQ,
629 }, 630 },
630}; 631};
@@ -674,8 +675,8 @@ static struct resource da8xx_lcdc_resources[] = {
674 .flags = IORESOURCE_MEM, 675 .flags = IORESOURCE_MEM,
675 }, 676 },
676 [1] = { /* interrupt */ 677 [1] = { /* interrupt */
677 .start = IRQ_DA8XX_LCDINT, 678 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
678 .end = IRQ_DA8XX_LCDINT, 679 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
679 .flags = IORESOURCE_IRQ, 680 .flags = IORESOURCE_IRQ,
680 }, 681 },
681}; 682};
@@ -700,48 +701,48 @@ static struct resource da8xx_gpio_resources[] = {
700 .flags = IORESOURCE_MEM, 701 .flags = IORESOURCE_MEM,
701 }, 702 },
702 { /* interrupt */ 703 { /* interrupt */
703 .start = IRQ_DA8XX_GPIO0, 704 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
704 .end = IRQ_DA8XX_GPIO0, 705 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
705 .flags = IORESOURCE_IRQ, 706 .flags = IORESOURCE_IRQ,
706 }, 707 },
707 { 708 {
708 .start = IRQ_DA8XX_GPIO1, 709 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
709 .end = IRQ_DA8XX_GPIO1, 710 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
710 .flags = IORESOURCE_IRQ, 711 .flags = IORESOURCE_IRQ,
711 }, 712 },
712 { 713 {
713 .start = IRQ_DA8XX_GPIO2, 714 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
714 .end = IRQ_DA8XX_GPIO2, 715 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
715 .flags = IORESOURCE_IRQ, 716 .flags = IORESOURCE_IRQ,
716 }, 717 },
717 { 718 {
718 .start = IRQ_DA8XX_GPIO3, 719 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
719 .end = IRQ_DA8XX_GPIO3, 720 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
720 .flags = IORESOURCE_IRQ, 721 .flags = IORESOURCE_IRQ,
721 }, 722 },
722 { 723 {
723 .start = IRQ_DA8XX_GPIO4, 724 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
724 .end = IRQ_DA8XX_GPIO4, 725 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
725 .flags = IORESOURCE_IRQ, 726 .flags = IORESOURCE_IRQ,
726 }, 727 },
727 { 728 {
728 .start = IRQ_DA8XX_GPIO5, 729 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
729 .end = IRQ_DA8XX_GPIO5, 730 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
730 .flags = IORESOURCE_IRQ, 731 .flags = IORESOURCE_IRQ,
731 }, 732 },
732 { 733 {
733 .start = IRQ_DA8XX_GPIO6, 734 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
734 .end = IRQ_DA8XX_GPIO6, 735 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
735 .flags = IORESOURCE_IRQ, 736 .flags = IORESOURCE_IRQ,
736 }, 737 },
737 { 738 {
738 .start = IRQ_DA8XX_GPIO7, 739 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
739 .end = IRQ_DA8XX_GPIO7, 740 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
740 .flags = IORESOURCE_IRQ, 741 .flags = IORESOURCE_IRQ,
741 }, 742 },
742 { 743 {
743 .start = IRQ_DA8XX_GPIO8, 744 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
744 .end = IRQ_DA8XX_GPIO8, 745 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
745 .flags = IORESOURCE_IRQ, 746 .flags = IORESOURCE_IRQ,
746 }, 747 },
747}; 748};
@@ -766,8 +767,8 @@ static struct resource da8xx_mmcsd0_resources[] = {
766 .flags = IORESOURCE_MEM, 767 .flags = IORESOURCE_MEM,
767 }, 768 },
768 { /* interrupt */ 769 { /* interrupt */
769 .start = IRQ_DA8XX_MMCSDINT0, 770 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
770 .end = IRQ_DA8XX_MMCSDINT0, 771 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
771 .flags = IORESOURCE_IRQ, 772 .flags = IORESOURCE_IRQ,
772 }, 773 },
773}; 774};
@@ -793,8 +794,8 @@ static struct resource da850_mmcsd1_resources[] = {
793 .flags = IORESOURCE_MEM, 794 .flags = IORESOURCE_MEM,
794 }, 795 },
795 { /* interrupt */ 796 { /* interrupt */
796 .start = IRQ_DA850_MMCSDINT0_1, 797 .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
797 .end = IRQ_DA850_MMCSDINT0_1, 798 .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
798 .flags = IORESOURCE_IRQ, 799 .flags = IORESOURCE_IRQ,
799 }, 800 },
800}; 801};
@@ -845,8 +846,8 @@ static struct resource da8xx_rproc_resources[] = {
845 .flags = IORESOURCE_MEM, 846 .flags = IORESOURCE_MEM,
846 }, 847 },
847 { /* dsp irq */ 848 { /* dsp irq */
848 .start = IRQ_DA8XX_CHIPINT0, 849 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
849 .end = IRQ_DA8XX_CHIPINT0, 850 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
850 .flags = IORESOURCE_IRQ, 851 .flags = IORESOURCE_IRQ,
851 }, 852 },
852}; 853};
@@ -936,13 +937,13 @@ static struct resource da8xx_rtc_resources[] = {
936 .flags = IORESOURCE_MEM, 937 .flags = IORESOURCE_MEM,
937 }, 938 },
938 { /* timer irq */ 939 { /* timer irq */
939 .start = IRQ_DA8XX_RTC, 940 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
940 .end = IRQ_DA8XX_RTC, 941 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
941 .flags = IORESOURCE_IRQ, 942 .flags = IORESOURCE_IRQ,
942 }, 943 },
943 { /* alarm irq */ 944 { /* alarm irq */
944 .start = IRQ_DA8XX_RTC, 945 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
945 .end = IRQ_DA8XX_RTC, 946 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
946 .flags = IORESOURCE_IRQ, 947 .flags = IORESOURCE_IRQ,
947 }, 948 },
948}; 949};
@@ -1009,8 +1010,8 @@ static struct resource da8xx_spi0_resources[] = {
1009 .flags = IORESOURCE_MEM, 1010 .flags = IORESOURCE_MEM,
1010 }, 1011 },
1011 [1] = { 1012 [1] = {
1012 .start = IRQ_DA8XX_SPINT0, 1013 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1013 .end = IRQ_DA8XX_SPINT0, 1014 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1014 .flags = IORESOURCE_IRQ, 1015 .flags = IORESOURCE_IRQ,
1015 }, 1016 },
1016}; 1017};
@@ -1022,8 +1023,8 @@ static struct resource da8xx_spi1_resources[] = {
1022 .flags = IORESOURCE_MEM, 1023 .flags = IORESOURCE_MEM,
1023 }, 1024 },
1024 [1] = { 1025 [1] = {
1025 .start = IRQ_DA8XX_SPINT1, 1026 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1026 .end = IRQ_DA8XX_SPINT1, 1027 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1027 .flags = IORESOURCE_IRQ, 1028 .flags = IORESOURCE_IRQ,
1028 }, 1029 },
1029}; 1030};
@@ -1103,7 +1104,7 @@ static struct resource da850_sata_resources[] = {
1103 .flags = IORESOURCE_MEM, 1104 .flags = IORESOURCE_MEM,
1104 }, 1105 },
1105 { 1106 {
1106 .start = IRQ_DA850_SATAINT, 1107 .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
1107 .flags = IORESOURCE_IRQ, 1108 .flags = IORESOURCE_IRQ,
1108 }, 1109 },
1109}; 1110};
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index e8dbbb7479ab..40bd8029e457 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -11,21 +11,20 @@
11 11
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/platform_data/i2c-davinci.h>
15#include <linux/platform_data/mmc-davinci.h>
16#include <linux/platform_data/edma.h>
14#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
15#include <linux/io.h> 18#include <linux/io.h>
16#include <linux/reboot.h> 19#include <linux/reboot.h>
17 20
18#include <mach/hardware.h> 21#include <mach/hardware.h>
19#include <linux/platform_data/i2c-davinci.h>
20#include <mach/irqs.h>
21#include <mach/cputype.h> 22#include <mach/cputype.h>
22#include <mach/mux.h> 23#include <mach/mux.h>
23#include <linux/platform_data/mmc-davinci.h>
24#include <mach/time.h> 24#include <mach/time.h>
25#include <linux/platform_data/edma.h>
26
27 25
28#include "davinci.h" 26#include "davinci.h"
27#include "irqs.h"
29 28
30#define DAVINCI_I2C_BASE 0x01C21000 29#define DAVINCI_I2C_BASE 0x01C21000
31#define DAVINCI_ATA_BASE 0x01C66000 30#define DAVINCI_ATA_BASE 0x01C66000
@@ -56,7 +55,7 @@ static struct resource i2c_resources[] = {
56 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
57 }, 56 },
58 { 57 {
59 .start = IRQ_I2C, 58 .start = DAVINCI_INTC_IRQ(IRQ_I2C),
60 .flags = IORESOURCE_IRQ, 59 .flags = IORESOURCE_IRQ,
61 }, 60 },
62}; 61};
@@ -84,8 +83,8 @@ static struct resource ide_resources[] = {
84 .flags = IORESOURCE_MEM, 83 .flags = IORESOURCE_MEM,
85 }, 84 },
86 { 85 {
87 .start = IRQ_IDE, 86 .start = DAVINCI_INTC_IRQ(IRQ_IDE),
88 .end = IRQ_IDE, 87 .end = DAVINCI_INTC_IRQ(IRQ_IDE),
89 .flags = IORESOURCE_IRQ, 88 .flags = IORESOURCE_IRQ,
90 }, 89 },
91}; 90};
@@ -133,11 +132,11 @@ static struct resource mmcsd0_resources[] = {
133 }, 132 },
134 /* IRQs: MMC/SD, then SDIO */ 133 /* IRQs: MMC/SD, then SDIO */
135 { 134 {
136 .start = IRQ_MMCINT, 135 .start = DAVINCI_INTC_IRQ(IRQ_MMCINT),
137 .flags = IORESOURCE_IRQ, 136 .flags = IORESOURCE_IRQ,
138 }, { 137 }, {
139 /* different on dm355 */ 138 /* different on dm355 */
140 .start = IRQ_SDIOINT, 139 .start = DAVINCI_INTC_IRQ(IRQ_SDIOINT),
141 .flags = IORESOURCE_IRQ, 140 .flags = IORESOURCE_IRQ,
142 }, 141 },
143}; 142};
@@ -163,10 +162,10 @@ static struct resource mmcsd1_resources[] = {
163 }, 162 },
164 /* IRQs: MMC/SD, then SDIO */ 163 /* IRQs: MMC/SD, then SDIO */
165 { 164 {
166 .start = IRQ_DM355_MMCINT1, 165 .start = DAVINCI_INTC_IRQ(IRQ_DM355_MMCINT1),
167 .flags = IORESOURCE_IRQ, 166 .flags = IORESOURCE_IRQ,
168 }, { 167 }, {
169 .start = IRQ_DM355_SDIOINT1, 168 .start = DAVINCI_INTC_IRQ(IRQ_DM355_SDIOINT1),
170 .flags = IORESOURCE_IRQ, 169 .flags = IORESOURCE_IRQ,
171 }, 170 },
172}; 171};
@@ -219,7 +218,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
219 mmcsd1_resources[0].start = DM365_MMCSD1_BASE; 218 mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
220 mmcsd1_resources[0].end = DM365_MMCSD1_BASE + 219 mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
221 SZ_4K - 1; 220 SZ_4K - 1;
222 mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1; 221 mmcsd1_resources[2].start = DAVINCI_INTC_IRQ(
222 IRQ_DM365_SDIOINT1);
223 davinci_mmcsd1_device.name = "da830-mmc"; 223 davinci_mmcsd1_device.name = "da830-mmc";
224 } else 224 } else
225 break; 225 break;
@@ -230,7 +230,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
230 if (cpu_is_davinci_dm355()) { 230 if (cpu_is_davinci_dm355()) {
231 mmcsd0_resources[0].start = DM355_MMCSD0_BASE; 231 mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
232 mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; 232 mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
233 mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0; 233 mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
234 IRQ_DM355_SDIOINT0);
234 235
235 /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ 236 /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
236 davinci_cfg_reg(DM355_MMCSD0); 237 davinci_cfg_reg(DM355_MMCSD0);
@@ -241,7 +242,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
241 mmcsd0_resources[0].start = DM365_MMCSD0_BASE; 242 mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
242 mmcsd0_resources[0].end = DM365_MMCSD0_BASE + 243 mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
243 SZ_4K - 1; 244 SZ_4K - 1;
244 mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; 245 mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
246 IRQ_DM365_SDIOINT0);
245 davinci_mmcsd0_device.name = "da830-mmc"; 247 davinci_mmcsd0_device.name = "da830-mmc";
246 } else if (cpu_is_davinci_dm644x()) { 248 } else if (cpu_is_davinci_dm644x()) {
247 /* REVISIT: should this be in board-init code? */ 249 /* REVISIT: should this be in board-init code? */
@@ -313,13 +315,13 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata)
313struct davinci_timer_instance davinci_timer_instance[2] = { 315struct davinci_timer_instance davinci_timer_instance[2] = {
314 { 316 {
315 .base = DAVINCI_TIMER0_BASE, 317 .base = DAVINCI_TIMER0_BASE,
316 .bottom_irq = IRQ_TINT0_TINT12, 318 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12),
317 .top_irq = IRQ_TINT0_TINT34, 319 .top_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34),
318 }, 320 },
319 { 321 {
320 .base = DAVINCI_TIMER1_BASE, 322 .base = DAVINCI_TIMER1_BASE,
321 .bottom_irq = IRQ_TINT1_TINT12, 323 .bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT12),
322 .top_irq = IRQ_TINT1_TINT34, 324 .top_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34),
323 }, 325 },
324}; 326};
325 327
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 4c6e0bef4509..4a482445b9a2 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -15,6 +15,7 @@
15#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h> 16#include <linux/dmaengine.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/irqchip/irq-davinci-aintc.h>
18#include <linux/platform_data/edma.h> 19#include <linux/platform_data/edma.h>
19#include <linux/platform_data/gpio-davinci.h> 20#include <linux/platform_data/gpio-davinci.h>
20#include <linux/platform_data/spi-davinci.h> 21#include <linux/platform_data/spi-davinci.h>
@@ -26,13 +27,13 @@
26 27
27#include <mach/common.h> 28#include <mach/common.h>
28#include <mach/cputype.h> 29#include <mach/cputype.h>
29#include <mach/irqs.h>
30#include <mach/mux.h> 30#include <mach/mux.h>
31#include <mach/serial.h> 31#include <mach/serial.h>
32#include <mach/time.h> 32#include <mach/time.h>
33 33
34#include "asp.h" 34#include "asp.h"
35#include "davinci.h" 35#include "davinci.h"
36#include "irqs.h"
36#include "mux.h" 37#include "mux.h"
37 38
38#define DM355_UART2_BASE (IO_PHYS + 0x206000) 39#define DM355_UART2_BASE (IO_PHYS + 0x206000)
@@ -53,7 +54,7 @@ static struct resource dm355_spi0_resources[] = {
53 .flags = IORESOURCE_MEM, 54 .flags = IORESOURCE_MEM,
54 }, 55 },
55 { 56 {
56 .start = IRQ_DM355_SPINT0_0, 57 .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
57 .flags = IORESOURCE_IRQ, 58 .flags = IORESOURCE_IRQ,
58 }, 59 },
59}; 60};
@@ -273,12 +274,12 @@ static struct resource edma_resources[] = {
273 }, 274 },
274 { 275 {
275 .name = "edma3_ccint", 276 .name = "edma3_ccint",
276 .start = IRQ_CCINT0, 277 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
277 .flags = IORESOURCE_IRQ, 278 .flags = IORESOURCE_IRQ,
278 }, 279 },
279 { 280 {
280 .name = "edma3_ccerrint", 281 .name = "edma3_ccerrint",
281 .start = IRQ_CCERRINT, 282 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
282 .flags = IORESOURCE_IRQ, 283 .flags = IORESOURCE_IRQ,
283 }, 284 },
284 /* not using (or muxing) TC*_ERR */ 285 /* not using (or muxing) TC*_ERR */
@@ -358,13 +359,13 @@ static struct platform_device dm355_vpss_device = {
358 359
359static struct resource vpfe_resources[] = { 360static struct resource vpfe_resources[] = {
360 { 361 {
361 .start = IRQ_VDINT0, 362 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
362 .end = IRQ_VDINT0, 363 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
363 .flags = IORESOURCE_IRQ, 364 .flags = IORESOURCE_IRQ,
364 }, 365 },
365 { 366 {
366 .start = IRQ_VDINT1, 367 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
367 .end = IRQ_VDINT1, 368 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
368 .flags = IORESOURCE_IRQ, 369 .flags = IORESOURCE_IRQ,
369 }, 370 },
370}; 371};
@@ -422,8 +423,8 @@ static struct platform_device dm355_osd_dev = {
422 423
423static struct resource dm355_venc_resources[] = { 424static struct resource dm355_venc_resources[] = {
424 { 425 {
425 .start = IRQ_VENCINT, 426 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
426 .end = IRQ_VENCINT, 427 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
427 .flags = IORESOURCE_IRQ, 428 .flags = IORESOURCE_IRQ,
428 }, 429 },
429 /* venc registers io space */ 430 /* venc registers io space */
@@ -442,8 +443,8 @@ static struct resource dm355_venc_resources[] = {
442 443
443static struct resource dm355_v4l2_disp_resources[] = { 444static struct resource dm355_v4l2_disp_resources[] = {
444 { 445 {
445 .start = IRQ_VENCINT, 446 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
446 .end = IRQ_VENCINT, 447 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
447 .flags = IORESOURCE_IRQ, 448 .flags = IORESOURCE_IRQ,
448 }, 449 },
449 /* venc registers io space */ 450 /* venc registers io space */
@@ -547,38 +548,38 @@ static struct resource dm355_gpio_resources[] = {
547 .flags = IORESOURCE_MEM, 548 .flags = IORESOURCE_MEM,
548 }, 549 },
549 { /* interrupt */ 550 { /* interrupt */
550 .start = IRQ_DM355_GPIOBNK0, 551 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
551 .end = IRQ_DM355_GPIOBNK0, 552 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
552 .flags = IORESOURCE_IRQ, 553 .flags = IORESOURCE_IRQ,
553 }, 554 },
554 { 555 {
555 .start = IRQ_DM355_GPIOBNK1, 556 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
556 .end = IRQ_DM355_GPIOBNK1, 557 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
557 .flags = IORESOURCE_IRQ, 558 .flags = IORESOURCE_IRQ,
558 }, 559 },
559 { 560 {
560 .start = IRQ_DM355_GPIOBNK2, 561 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
561 .end = IRQ_DM355_GPIOBNK2, 562 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
562 .flags = IORESOURCE_IRQ, 563 .flags = IORESOURCE_IRQ,
563 }, 564 },
564 { 565 {
565 .start = IRQ_DM355_GPIOBNK3, 566 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
566 .end = IRQ_DM355_GPIOBNK3, 567 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
567 .flags = IORESOURCE_IRQ, 568 .flags = IORESOURCE_IRQ,
568 }, 569 },
569 { 570 {
570 .start = IRQ_DM355_GPIOBNK4, 571 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
571 .end = IRQ_DM355_GPIOBNK4, 572 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
572 .flags = IORESOURCE_IRQ, 573 .flags = IORESOURCE_IRQ,
573 }, 574 },
574 { 575 {
575 .start = IRQ_DM355_GPIOBNK5, 576 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
576 .end = IRQ_DM355_GPIOBNK5, 577 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
577 .flags = IORESOURCE_IRQ, 578 .flags = IORESOURCE_IRQ,
578 }, 579 },
579 { 580 {
580 .start = IRQ_DM355_GPIOBNK6, 581 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
581 .end = IRQ_DM355_GPIOBNK6, 582 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
582 .flags = IORESOURCE_IRQ, 583 .flags = IORESOURCE_IRQ,
583 }, 584 },
584}; 585};
@@ -632,7 +633,7 @@ static struct davinci_timer_info dm355_timer_info = {
632static struct plat_serial8250_port dm355_serial0_platform_data[] = { 633static struct plat_serial8250_port dm355_serial0_platform_data[] = {
633 { 634 {
634 .mapbase = DAVINCI_UART0_BASE, 635 .mapbase = DAVINCI_UART0_BASE,
635 .irq = IRQ_UARTINT0, 636 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
636 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 637 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
637 UPF_IOREMAP, 638 UPF_IOREMAP,
638 .iotype = UPIO_MEM, 639 .iotype = UPIO_MEM,
@@ -645,7 +646,7 @@ static struct plat_serial8250_port dm355_serial0_platform_data[] = {
645static struct plat_serial8250_port dm355_serial1_platform_data[] = { 646static struct plat_serial8250_port dm355_serial1_platform_data[] = {
646 { 647 {
647 .mapbase = DAVINCI_UART1_BASE, 648 .mapbase = DAVINCI_UART1_BASE,
648 .irq = IRQ_UARTINT1, 649 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
649 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 650 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
650 UPF_IOREMAP, 651 UPF_IOREMAP,
651 .iotype = UPIO_MEM, 652 .iotype = UPIO_MEM,
@@ -658,7 +659,7 @@ static struct plat_serial8250_port dm355_serial1_platform_data[] = {
658static struct plat_serial8250_port dm355_serial2_platform_data[] = { 659static struct plat_serial8250_port dm355_serial2_platform_data[] = {
659 { 660 {
660 .mapbase = DM355_UART2_BASE, 661 .mapbase = DM355_UART2_BASE,
661 .irq = IRQ_DM355_UARTINT2, 662 .irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
662 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 663 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
663 UPF_IOREMAP, 664 UPF_IOREMAP,
664 .iotype = UPIO_MEM, 665 .iotype = UPIO_MEM,
@@ -704,10 +705,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
704 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 705 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
705 .pinmux_pins = dm355_pins, 706 .pinmux_pins = dm355_pins,
706 .pinmux_pins_num = ARRAY_SIZE(dm355_pins), 707 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
707 .intc_base = DAVINCI_ARM_INTC_BASE,
708 .intc_type = DAVINCI_INTC_TYPE_AINTC,
709 .intc_irq_prios = dm355_default_priorities,
710 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
711 .timer_info = &dm355_timer_info, 708 .timer_info = &dm355_timer_info,
712 .sram_dma = 0x00010000, 709 .sram_dma = 0x00010000,
713 .sram_len = SZ_32K, 710 .sram_len = SZ_32K,
@@ -793,6 +790,21 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
793 return 0; 790 return 0;
794} 791}
795 792
793static const struct davinci_aintc_config dm355_aintc_config = {
794 .reg = {
795 .start = DAVINCI_ARM_INTC_BASE,
796 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
797 .flags = IORESOURCE_MEM,
798 },
799 .num_irqs = 64,
800 .prios = dm355_default_priorities,
801};
802
803void __init dm355_init_irq(void)
804{
805 davinci_aintc_init(&dm355_aintc_config);
806}
807
796static int __init dm355_init_devices(void) 808static int __init dm355_init_devices(void)
797{ 809{
798 struct platform_device *edma_pdev; 810 struct platform_device *edma_pdev;
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 01fb2b0c82de..8e0a77315add 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -19,6 +19,7 @@
19#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h> 20#include <linux/dmaengine.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/irqchip/irq-davinci-aintc.h>
22#include <linux/platform_data/edma.h> 23#include <linux/platform_data/edma.h>
23#include <linux/platform_data/gpio-davinci.h> 24#include <linux/platform_data/gpio-davinci.h>
24#include <linux/platform_data/keyscan-davinci.h> 25#include <linux/platform_data/keyscan-davinci.h>
@@ -31,13 +32,13 @@
31 32
32#include <mach/common.h> 33#include <mach/common.h>
33#include <mach/cputype.h> 34#include <mach/cputype.h>
34#include <mach/irqs.h>
35#include <mach/mux.h> 35#include <mach/mux.h>
36#include <mach/serial.h> 36#include <mach/serial.h>
37#include <mach/time.h> 37#include <mach/time.h>
38 38
39#include "asp.h" 39#include "asp.h"
40#include "davinci.h" 40#include "davinci.h"
41#include "irqs.h"
41#include "mux.h" 42#include "mux.h"
42 43
43#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ 44#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
@@ -224,7 +225,7 @@ static struct resource dm365_spi0_resources[] = {
224 .flags = IORESOURCE_MEM, 225 .flags = IORESOURCE_MEM,
225 }, 226 },
226 { 227 {
227 .start = IRQ_DM365_SPIINT0_0, 228 .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
228 .flags = IORESOURCE_IRQ, 229 .flags = IORESOURCE_IRQ,
229 }, 230 },
230}; 231};
@@ -266,43 +267,43 @@ static struct resource dm365_gpio_resources[] = {
266 .flags = IORESOURCE_MEM, 267 .flags = IORESOURCE_MEM,
267 }, 268 },
268 { /* interrupt */ 269 { /* interrupt */
269 .start = IRQ_DM365_GPIO0, 270 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
270 .end = IRQ_DM365_GPIO0, 271 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
271 .flags = IORESOURCE_IRQ, 272 .flags = IORESOURCE_IRQ,
272 }, 273 },
273 { 274 {
274 .start = IRQ_DM365_GPIO1, 275 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
275 .end = IRQ_DM365_GPIO1, 276 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
276 .flags = IORESOURCE_IRQ, 277 .flags = IORESOURCE_IRQ,
277 }, 278 },
278 { 279 {
279 .start = IRQ_DM365_GPIO2, 280 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
280 .end = IRQ_DM365_GPIO2, 281 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
281 .flags = IORESOURCE_IRQ, 282 .flags = IORESOURCE_IRQ,
282 }, 283 },
283 { 284 {
284 .start = IRQ_DM365_GPIO3, 285 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
285 .end = IRQ_DM365_GPIO3, 286 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
286 .flags = IORESOURCE_IRQ, 287 .flags = IORESOURCE_IRQ,
287 }, 288 },
288 { 289 {
289 .start = IRQ_DM365_GPIO4, 290 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
290 .end = IRQ_DM365_GPIO4, 291 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
291 .flags = IORESOURCE_IRQ, 292 .flags = IORESOURCE_IRQ,
292 }, 293 },
293 { 294 {
294 .start = IRQ_DM365_GPIO5, 295 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
295 .end = IRQ_DM365_GPIO5, 296 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
296 .flags = IORESOURCE_IRQ, 297 .flags = IORESOURCE_IRQ,
297 }, 298 },
298 { 299 {
299 .start = IRQ_DM365_GPIO6, 300 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
300 .end = IRQ_DM365_GPIO6, 301 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
301 .flags = IORESOURCE_IRQ, 302 .flags = IORESOURCE_IRQ,
302 }, 303 },
303 { 304 {
304 .start = IRQ_DM365_GPIO7, 305 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
305 .end = IRQ_DM365_GPIO7, 306 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
306 .flags = IORESOURCE_IRQ, 307 .flags = IORESOURCE_IRQ,
307 }, 308 },
308}; 309};
@@ -336,23 +337,23 @@ static struct resource dm365_emac_resources[] = {
336 .flags = IORESOURCE_MEM, 337 .flags = IORESOURCE_MEM,
337 }, 338 },
338 { 339 {
339 .start = IRQ_DM365_EMAC_RXTHRESH, 340 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
340 .end = IRQ_DM365_EMAC_RXTHRESH, 341 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
341 .flags = IORESOURCE_IRQ, 342 .flags = IORESOURCE_IRQ,
342 }, 343 },
343 { 344 {
344 .start = IRQ_DM365_EMAC_RXPULSE, 345 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
345 .end = IRQ_DM365_EMAC_RXPULSE, 346 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
346 .flags = IORESOURCE_IRQ, 347 .flags = IORESOURCE_IRQ,
347 }, 348 },
348 { 349 {
349 .start = IRQ_DM365_EMAC_TXPULSE, 350 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
350 .end = IRQ_DM365_EMAC_TXPULSE, 351 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
351 .flags = IORESOURCE_IRQ, 352 .flags = IORESOURCE_IRQ,
352 }, 353 },
353 { 354 {
354 .start = IRQ_DM365_EMAC_MISCPULSE, 355 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
355 .end = IRQ_DM365_EMAC_MISCPULSE, 356 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
356 .flags = IORESOURCE_IRQ, 357 .flags = IORESOURCE_IRQ,
357 }, 358 },
358}; 359};
@@ -518,12 +519,12 @@ static struct resource edma_resources[] = {
518 }, 519 },
519 { 520 {
520 .name = "edma3_ccint", 521 .name = "edma3_ccint",
521 .start = IRQ_CCINT0, 522 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
522 .flags = IORESOURCE_IRQ, 523 .flags = IORESOURCE_IRQ,
523 }, 524 },
524 { 525 {
525 .name = "edma3_ccerrint", 526 .name = "edma3_ccerrint",
526 .start = IRQ_CCERRINT, 527 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
527 .flags = IORESOURCE_IRQ, 528 .flags = IORESOURCE_IRQ,
528 }, 529 },
529 /* not using TC*_ERR */ 530 /* not using TC*_ERR */
@@ -597,7 +598,7 @@ static struct resource dm365_rtc_resources[] = {
597 .flags = IORESOURCE_MEM, 598 .flags = IORESOURCE_MEM,
598 }, 599 },
599 { 600 {
600 .start = IRQ_DM365_RTCINT, 601 .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
601 .flags = IORESOURCE_IRQ, 602 .flags = IORESOURCE_IRQ,
602 }, 603 },
603}; 604};
@@ -627,8 +628,8 @@ static struct resource dm365_ks_resources[] = {
627 }, 628 },
628 { 629 {
629 /* interrupt */ 630 /* interrupt */
630 .start = IRQ_DM365_KEYINT, 631 .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
631 .end = IRQ_DM365_KEYINT, 632 .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
632 .flags = IORESOURCE_IRQ, 633 .flags = IORESOURCE_IRQ,
633 }, 634 },
634}; 635};
@@ -669,7 +670,7 @@ static struct davinci_timer_info dm365_timer_info = {
669static struct plat_serial8250_port dm365_serial0_platform_data[] = { 670static struct plat_serial8250_port dm365_serial0_platform_data[] = {
670 { 671 {
671 .mapbase = DAVINCI_UART0_BASE, 672 .mapbase = DAVINCI_UART0_BASE,
672 .irq = IRQ_UARTINT0, 673 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
673 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 674 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
674 UPF_IOREMAP, 675 UPF_IOREMAP,
675 .iotype = UPIO_MEM, 676 .iotype = UPIO_MEM,
@@ -682,7 +683,7 @@ static struct plat_serial8250_port dm365_serial0_platform_data[] = {
682static struct plat_serial8250_port dm365_serial1_platform_data[] = { 683static struct plat_serial8250_port dm365_serial1_platform_data[] = {
683 { 684 {
684 .mapbase = DM365_UART1_BASE, 685 .mapbase = DM365_UART1_BASE,
685 .irq = IRQ_UARTINT1, 686 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
686 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 687 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
687 UPF_IOREMAP, 688 UPF_IOREMAP,
688 .iotype = UPIO_MEM, 689 .iotype = UPIO_MEM,
@@ -721,10 +722,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
721 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 722 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
722 .pinmux_pins = dm365_pins, 723 .pinmux_pins = dm365_pins,
723 .pinmux_pins_num = ARRAY_SIZE(dm365_pins), 724 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
724 .intc_base = DAVINCI_ARM_INTC_BASE,
725 .intc_type = DAVINCI_INTC_TYPE_AINTC,
726 .intc_irq_prios = dm365_default_priorities,
727 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
728 .timer_info = &dm365_timer_info, 725 .timer_info = &dm365_timer_info,
729 .emac_pdata = &dm365_emac_pdata, 726 .emac_pdata = &dm365_emac_pdata,
730 .sram_dma = 0x00010000, 727 .sram_dma = 0x00010000,
@@ -822,13 +819,13 @@ static struct platform_device dm365_vpss_device = {
822 819
823static struct resource vpfe_resources[] = { 820static struct resource vpfe_resources[] = {
824 { 821 {
825 .start = IRQ_VDINT0, 822 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
826 .end = IRQ_VDINT0, 823 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
827 .flags = IORESOURCE_IRQ, 824 .flags = IORESOURCE_IRQ,
828 }, 825 },
829 { 826 {
830 .start = IRQ_VDINT1, 827 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
831 .end = IRQ_VDINT1, 828 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
832 .flags = IORESOURCE_IRQ, 829 .flags = IORESOURCE_IRQ,
833 }, 830 },
834}; 831};
@@ -909,8 +906,8 @@ static struct platform_device dm365_osd_dev = {
909 906
910static struct resource dm365_venc_resources[] = { 907static struct resource dm365_venc_resources[] = {
911 { 908 {
912 .start = IRQ_VENCINT, 909 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
913 .end = IRQ_VENCINT, 910 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
914 .flags = IORESOURCE_IRQ, 911 .flags = IORESOURCE_IRQ,
915 }, 912 },
916 /* venc registers io space */ 913 /* venc registers io space */
@@ -929,8 +926,8 @@ static struct resource dm365_venc_resources[] = {
929 926
930static struct resource dm365_v4l2_disp_resources[] = { 927static struct resource dm365_v4l2_disp_resources[] = {
931 { 928 {
932 .start = IRQ_VENCINT, 929 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
933 .end = IRQ_VENCINT, 930 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
934 .flags = IORESOURCE_IRQ, 931 .flags = IORESOURCE_IRQ,
935 }, 932 },
936 /* venc registers io space */ 933 /* venc registers io space */
@@ -1052,6 +1049,21 @@ int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1052 return 0; 1049 return 0;
1053} 1050}
1054 1051
1052static const struct davinci_aintc_config dm365_aintc_config = {
1053 .reg = {
1054 .start = DAVINCI_ARM_INTC_BASE,
1055 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
1056 .flags = IORESOURCE_MEM,
1057 },
1058 .num_irqs = 64,
1059 .prios = dm365_default_priorities,
1060};
1061
1062void __init dm365_init_irq(void)
1063{
1064 davinci_aintc_init(&dm365_aintc_config);
1065}
1066
1055static int __init dm365_init_devices(void) 1067static int __init dm365_init_devices(void)
1056{ 1068{
1057 struct platform_device *edma_pdev; 1069 struct platform_device *edma_pdev;
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 38f92b7d413e..cecc7ceb8d34 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -14,6 +14,7 @@
14#include <linux/clkdev.h> 14#include <linux/clkdev.h>
15#include <linux/dmaengine.h> 15#include <linux/dmaengine.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/irqchip/irq-davinci-aintc.h>
17#include <linux/platform_data/edma.h> 18#include <linux/platform_data/edma.h>
18#include <linux/platform_data/gpio-davinci.h> 19#include <linux/platform_data/gpio-davinci.h>
19#include <linux/platform_device.h> 20#include <linux/platform_device.h>
@@ -23,13 +24,13 @@
23 24
24#include <mach/common.h> 25#include <mach/common.h>
25#include <mach/cputype.h> 26#include <mach/cputype.h>
26#include <mach/irqs.h>
27#include <mach/mux.h> 27#include <mach/mux.h>
28#include <mach/serial.h> 28#include <mach/serial.h>
29#include <mach/time.h> 29#include <mach/time.h>
30 30
31#include "asp.h" 31#include "asp.h"
32#include "davinci.h" 32#include "davinci.h"
33#include "irqs.h"
33#include "mux.h" 34#include "mux.h"
34 35
35/* 36/*
@@ -59,8 +60,8 @@ static struct resource dm644x_emac_resources[] = {
59 .flags = IORESOURCE_MEM, 60 .flags = IORESOURCE_MEM,
60 }, 61 },
61 { 62 {
62 .start = IRQ_EMACINT, 63 .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
63 .end = IRQ_EMACINT, 64 .end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
64 .flags = IORESOURCE_IRQ, 65 .flags = IORESOURCE_IRQ,
65 }, 66 },
66}; 67};
@@ -260,12 +261,12 @@ static struct resource edma_resources[] = {
260 }, 261 },
261 { 262 {
262 .name = "edma3_ccint", 263 .name = "edma3_ccint",
263 .start = IRQ_CCINT0, 264 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
264 .flags = IORESOURCE_IRQ, 265 .flags = IORESOURCE_IRQ,
265 }, 266 },
266 { 267 {
267 .name = "edma3_ccerrint", 268 .name = "edma3_ccerrint",
268 .start = IRQ_CCERRINT, 269 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
269 .flags = IORESOURCE_IRQ, 270 .flags = IORESOURCE_IRQ,
270 }, 271 },
271 /* not using TC*_ERR */ 272 /* not using TC*_ERR */
@@ -330,13 +331,13 @@ static struct platform_device dm644x_vpss_device = {
330 331
331static struct resource dm644x_vpfe_resources[] = { 332static struct resource dm644x_vpfe_resources[] = {
332 { 333 {
333 .start = IRQ_VDINT0, 334 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
334 .end = IRQ_VDINT0, 335 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
335 .flags = IORESOURCE_IRQ, 336 .flags = IORESOURCE_IRQ,
336 }, 337 },
337 { 338 {
338 .start = IRQ_VDINT1, 339 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
339 .end = IRQ_VDINT1, 340 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
340 .flags = IORESOURCE_IRQ, 341 .flags = IORESOURCE_IRQ,
341 }, 342 },
342}; 343};
@@ -442,8 +443,8 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
442 443
443static struct resource dm644x_v4l2_disp_resources[] = { 444static struct resource dm644x_v4l2_disp_resources[] = {
444 { 445 {
445 .start = IRQ_VENCINT, 446 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
446 .end = IRQ_VENCINT, 447 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
447 .flags = IORESOURCE_IRQ, 448 .flags = IORESOURCE_IRQ,
448 }, 449 },
449}; 450};
@@ -491,28 +492,28 @@ static struct resource dm644_gpio_resources[] = {
491 .flags = IORESOURCE_MEM, 492 .flags = IORESOURCE_MEM,
492 }, 493 },
493 { /* interrupt */ 494 { /* interrupt */
494 .start = IRQ_GPIOBNK0, 495 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
495 .end = IRQ_GPIOBNK0, 496 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
496 .flags = IORESOURCE_IRQ, 497 .flags = IORESOURCE_IRQ,
497 }, 498 },
498 { 499 {
499 .start = IRQ_GPIOBNK1, 500 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
500 .end = IRQ_GPIOBNK1, 501 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
501 .flags = IORESOURCE_IRQ, 502 .flags = IORESOURCE_IRQ,
502 }, 503 },
503 { 504 {
504 .start = IRQ_GPIOBNK2, 505 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
505 .end = IRQ_GPIOBNK2, 506 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
506 .flags = IORESOURCE_IRQ, 507 .flags = IORESOURCE_IRQ,
507 }, 508 },
508 { 509 {
509 .start = IRQ_GPIOBNK3, 510 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
510 .end = IRQ_GPIOBNK3, 511 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
511 .flags = IORESOURCE_IRQ, 512 .flags = IORESOURCE_IRQ,
512 }, 513 },
513 { 514 {
514 .start = IRQ_GPIOBNK4, 515 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
515 .end = IRQ_GPIOBNK4, 516 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
516 .flags = IORESOURCE_IRQ, 517 .flags = IORESOURCE_IRQ,
517 }, 518 },
518}; 519};
@@ -573,7 +574,7 @@ static struct davinci_timer_info dm644x_timer_info = {
573static struct plat_serial8250_port dm644x_serial0_platform_data[] = { 574static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
574 { 575 {
575 .mapbase = DAVINCI_UART0_BASE, 576 .mapbase = DAVINCI_UART0_BASE,
576 .irq = IRQ_UARTINT0, 577 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
577 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 578 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
578 UPF_IOREMAP, 579 UPF_IOREMAP,
579 .iotype = UPIO_MEM, 580 .iotype = UPIO_MEM,
@@ -586,7 +587,7 @@ static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
586static struct plat_serial8250_port dm644x_serial1_platform_data[] = { 587static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
587 { 588 {
588 .mapbase = DAVINCI_UART1_BASE, 589 .mapbase = DAVINCI_UART1_BASE,
589 .irq = IRQ_UARTINT1, 590 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
590 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 591 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
591 UPF_IOREMAP, 592 UPF_IOREMAP,
592 .iotype = UPIO_MEM, 593 .iotype = UPIO_MEM,
@@ -599,7 +600,7 @@ static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
599static struct plat_serial8250_port dm644x_serial2_platform_data[] = { 600static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
600 { 601 {
601 .mapbase = DAVINCI_UART2_BASE, 602 .mapbase = DAVINCI_UART2_BASE,
602 .irq = IRQ_UARTINT2, 603 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
603 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 604 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
604 UPF_IOREMAP, 605 UPF_IOREMAP,
605 .iotype = UPIO_MEM, 606 .iotype = UPIO_MEM,
@@ -645,10 +646,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
645 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 646 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
646 .pinmux_pins = dm644x_pins, 647 .pinmux_pins = dm644x_pins,
647 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), 648 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
648 .intc_base = DAVINCI_ARM_INTC_BASE,
649 .intc_type = DAVINCI_INTC_TYPE_AINTC,
650 .intc_irq_prios = dm644x_default_priorities,
651 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
652 .timer_info = &dm644x_timer_info, 649 .timer_info = &dm644x_timer_info,
653 .emac_pdata = &dm644x_emac_pdata, 650 .emac_pdata = &dm644x_emac_pdata,
654 .sram_dma = 0x00008000, 651 .sram_dma = 0x00008000,
@@ -729,6 +726,21 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
729 return 0; 726 return 0;
730} 727}
731 728
729static const struct davinci_aintc_config dm644x_aintc_config = {
730 .reg = {
731 .start = DAVINCI_ARM_INTC_BASE,
732 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
733 .flags = IORESOURCE_MEM,
734 },
735 .num_irqs = 64,
736 .prios = dm644x_default_priorities,
737};
738
739void __init dm644x_init_irq(void)
740{
741 davinci_aintc_init(&dm644x_aintc_config);
742}
743
732void __init dm644x_init_devices(void) 744void __init dm644x_init_devices(void)
733{ 745{
734 struct platform_device *edma_pdev; 746 struct platform_device *edma_pdev;
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 7dc54b2a610f..f33392f77a03 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -15,6 +15,7 @@
15#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h> 16#include <linux/dmaengine.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/irqchip/irq-davinci-aintc.h>
18#include <linux/platform_data/edma.h> 19#include <linux/platform_data/edma.h>
19#include <linux/platform_data/gpio-davinci.h> 20#include <linux/platform_data/gpio-davinci.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
@@ -24,13 +25,13 @@
24 25
25#include <mach/common.h> 26#include <mach/common.h>
26#include <mach/cputype.h> 27#include <mach/cputype.h>
27#include <mach/irqs.h>
28#include <mach/mux.h> 28#include <mach/mux.h>
29#include <mach/serial.h> 29#include <mach/serial.h>
30#include <mach/time.h> 30#include <mach/time.h>
31 31
32#include "asp.h" 32#include "asp.h"
33#include "davinci.h" 33#include "davinci.h"
34#include "irqs.h"
34#include "mux.h" 35#include "mux.h"
35 36
36#define DAVINCI_VPIF_BASE (0x01C12000) 37#define DAVINCI_VPIF_BASE (0x01C12000)
@@ -62,23 +63,23 @@ static struct resource dm646x_emac_resources[] = {
62 .flags = IORESOURCE_MEM, 63 .flags = IORESOURCE_MEM,
63 }, 64 },
64 { 65 {
65 .start = IRQ_DM646X_EMACRXTHINT, 66 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
66 .end = IRQ_DM646X_EMACRXTHINT, 67 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
67 .flags = IORESOURCE_IRQ, 68 .flags = IORESOURCE_IRQ,
68 }, 69 },
69 { 70 {
70 .start = IRQ_DM646X_EMACRXINT, 71 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
71 .end = IRQ_DM646X_EMACRXINT, 72 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
72 .flags = IORESOURCE_IRQ, 73 .flags = IORESOURCE_IRQ,
73 }, 74 },
74 { 75 {
75 .start = IRQ_DM646X_EMACTXINT, 76 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
76 .end = IRQ_DM646X_EMACTXINT, 77 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
77 .flags = IORESOURCE_IRQ, 78 .flags = IORESOURCE_IRQ,
78 }, 79 },
79 { 80 {
80 .start = IRQ_DM646X_EMACMISCINT, 81 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
81 .end = IRQ_DM646X_EMACMISCINT, 82 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
82 .flags = IORESOURCE_IRQ, 83 .flags = IORESOURCE_IRQ,
83 }, 84 },
84}; 85};
@@ -273,12 +274,12 @@ static struct resource edma_resources[] = {
273 }, 274 },
274 { 275 {
275 .name = "edma3_ccint", 276 .name = "edma3_ccint",
276 .start = IRQ_CCINT0, 277 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
277 .flags = IORESOURCE_IRQ, 278 .flags = IORESOURCE_IRQ,
278 }, 279 },
279 { 280 {
280 .name = "edma3_ccerrint", 281 .name = "edma3_ccerrint",
281 .start = IRQ_CCERRINT, 282 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
282 .flags = IORESOURCE_IRQ, 283 .flags = IORESOURCE_IRQ,
283 }, 284 },
284 /* not using TC*_ERR */ 285 /* not using TC*_ERR */
@@ -315,12 +316,12 @@ static struct resource dm646x_mcasp0_resources[] = {
315 }, 316 },
316 { 317 {
317 .name = "tx", 318 .name = "tx",
318 .start = IRQ_DM646X_MCASP0TXINT, 319 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
319 .flags = IORESOURCE_IRQ, 320 .flags = IORESOURCE_IRQ,
320 }, 321 },
321 { 322 {
322 .name = "rx", 323 .name = "rx",
323 .start = IRQ_DM646X_MCASP0RXINT, 324 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
324 .flags = IORESOURCE_IRQ, 325 .flags = IORESOURCE_IRQ,
325 }, 326 },
326}; 327};
@@ -341,7 +342,7 @@ static struct resource dm646x_mcasp1_resources[] = {
341 }, 342 },
342 { 343 {
343 .name = "tx", 344 .name = "tx",
344 .start = IRQ_DM646X_MCASP1TXINT, 345 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
345 .flags = IORESOURCE_IRQ, 346 .flags = IORESOURCE_IRQ,
346 }, 347 },
347}; 348};
@@ -388,13 +389,13 @@ static struct platform_device vpif_dev = {
388 389
389static struct resource vpif_display_resource[] = { 390static struct resource vpif_display_resource[] = {
390 { 391 {
391 .start = IRQ_DM646X_VP_VERTINT2, 392 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
392 .end = IRQ_DM646X_VP_VERTINT2, 393 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
393 .flags = IORESOURCE_IRQ, 394 .flags = IORESOURCE_IRQ,
394 }, 395 },
395 { 396 {
396 .start = IRQ_DM646X_VP_VERTINT3, 397 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
397 .end = IRQ_DM646X_VP_VERTINT3, 398 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
398 .flags = IORESOURCE_IRQ, 399 .flags = IORESOURCE_IRQ,
399 }, 400 },
400}; 401};
@@ -412,13 +413,13 @@ static struct platform_device vpif_display_dev = {
412 413
413static struct resource vpif_capture_resource[] = { 414static struct resource vpif_capture_resource[] = {
414 { 415 {
415 .start = IRQ_DM646X_VP_VERTINT0, 416 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
416 .end = IRQ_DM646X_VP_VERTINT0, 417 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
417 .flags = IORESOURCE_IRQ, 418 .flags = IORESOURCE_IRQ,
418 }, 419 },
419 { 420 {
420 .start = IRQ_DM646X_VP_VERTINT1, 421 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
421 .end = IRQ_DM646X_VP_VERTINT1, 422 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
422 .flags = IORESOURCE_IRQ, 423 .flags = IORESOURCE_IRQ,
423 }, 424 },
424}; 425};
@@ -441,18 +442,18 @@ static struct resource dm646x_gpio_resources[] = {
441 .flags = IORESOURCE_MEM, 442 .flags = IORESOURCE_MEM,
442 }, 443 },
443 { /* interrupt */ 444 { /* interrupt */
444 .start = IRQ_DM646X_GPIOBNK0, 445 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
445 .end = IRQ_DM646X_GPIOBNK0, 446 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
446 .flags = IORESOURCE_IRQ, 447 .flags = IORESOURCE_IRQ,
447 }, 448 },
448 { 449 {
449 .start = IRQ_DM646X_GPIOBNK1, 450 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
450 .end = IRQ_DM646X_GPIOBNK1, 451 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
451 .flags = IORESOURCE_IRQ, 452 .flags = IORESOURCE_IRQ,
452 }, 453 },
453 { 454 {
454 .start = IRQ_DM646X_GPIOBNK2, 455 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
455 .end = IRQ_DM646X_GPIOBNK2, 456 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
456 .flags = IORESOURCE_IRQ, 457 .flags = IORESOURCE_IRQ,
457 }, 458 },
458}; 459};
@@ -513,7 +514,7 @@ static struct davinci_timer_info dm646x_timer_info = {
513static struct plat_serial8250_port dm646x_serial0_platform_data[] = { 514static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
514 { 515 {
515 .mapbase = DAVINCI_UART0_BASE, 516 .mapbase = DAVINCI_UART0_BASE,
516 .irq = IRQ_UARTINT0, 517 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
517 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 518 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
518 UPF_IOREMAP, 519 UPF_IOREMAP,
519 .iotype = UPIO_MEM32, 520 .iotype = UPIO_MEM32,
@@ -526,7 +527,7 @@ static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
526static struct plat_serial8250_port dm646x_serial1_platform_data[] = { 527static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
527 { 528 {
528 .mapbase = DAVINCI_UART1_BASE, 529 .mapbase = DAVINCI_UART1_BASE,
529 .irq = IRQ_UARTINT1, 530 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
530 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 531 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
531 UPF_IOREMAP, 532 UPF_IOREMAP,
532 .iotype = UPIO_MEM32, 533 .iotype = UPIO_MEM32,
@@ -539,7 +540,7 @@ static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
539static struct plat_serial8250_port dm646x_serial2_platform_data[] = { 540static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
540 { 541 {
541 .mapbase = DAVINCI_UART2_BASE, 542 .mapbase = DAVINCI_UART2_BASE,
542 .irq = IRQ_DM646X_UARTINT2, 543 .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
543 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 544 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
544 UPF_IOREMAP, 545 UPF_IOREMAP,
545 .iotype = UPIO_MEM32, 546 .iotype = UPIO_MEM32,
@@ -585,10 +586,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
585 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 586 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
586 .pinmux_pins = dm646x_pins, 587 .pinmux_pins = dm646x_pins,
587 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), 588 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
588 .intc_base = DAVINCI_ARM_INTC_BASE,
589 .intc_type = DAVINCI_INTC_TYPE_AINTC,
590 .intc_irq_prios = dm646x_default_priorities,
591 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
592 .timer_info = &dm646x_timer_info, 589 .timer_info = &dm646x_timer_info,
593 .emac_pdata = &dm646x_emac_pdata, 590 .emac_pdata = &dm646x_emac_pdata,
594 .sram_dma = 0x10010000, 591 .sram_dma = 0x10010000,
@@ -690,6 +687,21 @@ void __init dm646x_register_clocks(void)
690 platform_device_register(&dm646x_pll2_device); 687 platform_device_register(&dm646x_pll2_device);
691} 688}
692 689
690static const struct davinci_aintc_config dm646x_aintc_config = {
691 .reg = {
692 .start = DAVINCI_ARM_INTC_BASE,
693 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
694 .flags = IORESOURCE_MEM,
695 },
696 .num_irqs = 64,
697 .prios = dm646x_default_priorities,
698};
699
700void __init dm646x_init_irq(void)
701{
702 davinci_aintc_init(&dm646x_aintc_config);
703}
704
693static int __init dm646x_init_devices(void) 705static int __init dm646x_init_devices(void)
694{ 706{
695 int ret = 0; 707 int ret = 0;
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b577e13a9c23..9526e5da0d33 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -17,11 +17,12 @@
17#include <linux/types.h> 17#include <linux/types.h>
18#include <linux/reboot.h> 18#include <linux/reboot.h>
19 19
20void davinci_timer_init(struct clk *clk); 20#include <asm/irq.h>
21
22#define DAVINCI_INTC_START NR_IRQS
23#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
21 24
22extern void davinci_irq_init(void); 25void davinci_timer_init(struct clk *clk);
23extern void __iomem *davinci_intc_base;
24extern int davinci_intc_type;
25 26
26struct davinci_timer_instance { 27struct davinci_timer_instance {
27 u32 base; 28 u32 base;
@@ -57,11 +58,6 @@ struct davinci_soc_info {
57 u32 pinmux_base; 58 u32 pinmux_base;
58 const struct mux_config *pinmux_pins; 59 const struct mux_config *pinmux_pins;
59 unsigned long pinmux_pins_num; 60 unsigned long pinmux_pins_num;
60 u32 intc_base;
61 int intc_type;
62 u8 *intc_irq_prios;
63 unsigned long intc_irq_num;
64 u32 *intc_host_map;
65 struct davinci_timer_info *timer_info; 61 struct davinci_timer_info *timer_info;
66 int gpio_type; 62 int gpio_type;
67 u32 gpio_base; 63 u32 gpio_base;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index ab4a57f433f4..1618b30661a9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -88,10 +88,12 @@ extern unsigned int da850_max_speed;
88#define DA8XX_ARM_RAM_BASE 0xffff0000 88#define DA8XX_ARM_RAM_BASE 0xffff0000
89 89
90void da830_init(void); 90void da830_init(void);
91void da830_init_irq(void);
91void da830_init_time(void); 92void da830_init_time(void);
92void da830_register_clocks(void); 93void da830_register_clocks(void);
93 94
94void da850_init(void); 95void da850_init(void);
96void da850_init_irq(void);
95void da850_init_time(void); 97void da850_init_time(void);
96void da850_register_clocks(void); 98void da850_register_clocks(void);
97 99
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
deleted file mode 100644
index cf5f573eb5fd..000000000000
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Low-level IRQ helper macros for TI DaVinci-based platforms
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <mach/irqs.h>
12
13 .macro get_irqnr_preamble, base, tmp
14 ldr \base, =davinci_intc_base
15 ldr \base, [\base]
16 .endm
17
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
20 ldr \tmp, =davinci_intc_type
21 ldr \tmp, [\tmp]
22 cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
23 beq 1001f
24#endif
25#if defined(CONFIG_AINTC)
26 ldr \tmp, [\base, #0x14]
27 movs \tmp, \tmp, lsr #2
28 sub \irqnr, \tmp, #1
29 b 1002f
30#endif
31#if defined(CONFIG_CP_INTC)
321001: ldr \irqnr, [\base, #0x80] /* get irq number */
33 mov \tmp, \irqnr, lsr #31
34 and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */
35 and \tmp, \tmp, #0x1
36 cmp \tmp, #0x1
37#endif
381002:
39 .endm
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
deleted file mode 100644
index 952dc126c390..000000000000
--- a/arch/arm/mach-davinci/irq.c
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * Interrupt handler for DaVinci boards.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26
27#include <mach/hardware.h>
28#include <mach/cputype.h>
29#include <mach/common.h>
30#include <asm/mach/irq.h>
31
32#define FIQ_REG0_OFFSET 0x0000
33#define FIQ_REG1_OFFSET 0x0004
34#define IRQ_REG0_OFFSET 0x0008
35#define IRQ_REG1_OFFSET 0x000C
36#define IRQ_ENT_REG0_OFFSET 0x0018
37#define IRQ_ENT_REG1_OFFSET 0x001C
38#define IRQ_INCTL_REG_OFFSET 0x0020
39#define IRQ_EABASE_REG_OFFSET 0x0024
40#define IRQ_INTPRI0_REG_OFFSET 0x0030
41#define IRQ_INTPRI7_REG_OFFSET 0x004C
42
43static inline void davinci_irq_writel(unsigned long value, int offset)
44{
45 __raw_writel(value, davinci_intc_base + offset);
46}
47
48static __init void
49davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
50{
51 struct irq_chip_generic *gc;
52 struct irq_chip_type *ct;
53
54 gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
55 if (!gc) {
56 pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
57 __func__, irq_start);
58 return;
59 }
60
61 ct = gc->chip_types;
62 ct->chip.irq_ack = irq_gc_ack_set_bit;
63 ct->chip.irq_mask = irq_gc_mask_clr_bit;
64 ct->chip.irq_unmask = irq_gc_mask_set_bit;
65
66 ct->regs.ack = IRQ_REG0_OFFSET;
67 ct->regs.mask = IRQ_ENT_REG0_OFFSET;
68 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
69 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
70}
71
72/* ARM Interrupt Controller Initialization */
73void __init davinci_irq_init(void)
74{
75 unsigned i, j;
76 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
77
78 davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
79 davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
80 if (WARN_ON(!davinci_intc_base))
81 return;
82
83 /* Clear all interrupt requests */
84 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
85 davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
86 davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
87 davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
88
89 /* Disable all interrupts */
90 davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
91 davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
92
93 /* Interrupts disabled immediately, IRQ entry reflects all */
94 davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
95
96 /* we don't use the hardware vector table, just its entry addresses */
97 davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
98
99 /* Clear all interrupt requests */
100 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
101 davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
102 davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
103 davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
104
105 for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
106 u32 pri;
107
108 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
109 pri |= (*davinci_def_priorities & 0x07) << j;
110 davinci_irq_writel(pri, i);
111 }
112
113 for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
114 davinci_alloc_gc(davinci_intc_base + j, i, 32);
115
116 irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
117}
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/irqs.h
index edb2ca62321a..8f9fc7a56ce8 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/irqs.h
@@ -30,9 +30,6 @@
30/* Base address */ 30/* Base address */
31#define DAVINCI_ARM_INTC_BASE 0x01C48000 31#define DAVINCI_ARM_INTC_BASE 0x01C48000
32 32
33#define DAVINCI_INTC_TYPE_AINTC 0
34#define DAVINCI_INTC_TYPE_CP_INTC 1
35
36/* Interrupt lines */ 33/* Interrupt lines */
37#define IRQ_VDINT0 0 34#define IRQ_VDINT0 0
38#define IRQ_VDINT1 1 35#define IRQ_VDINT1 1
@@ -404,6 +401,5 @@
404/* da850 currently has the most gpio pins (144) */ 401/* da850 currently has the most gpio pins (144) */
405#define DAVINCI_N_GPIO 144 402#define DAVINCI_N_GPIO 144
406/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ 403/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
407#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
408 404
409#endif /* __ASM_ARCH_IRQS_H */ 405#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
index c17ce66a3d95..25f21ee86f1a 100644
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ b/arch/arm/mach-davinci/usb-da8xx.c
@@ -18,7 +18,8 @@
18#include <mach/common.h> 18#include <mach/common.h>
19#include <mach/cputype.h> 19#include <mach/cputype.h>
20#include <mach/da8xx.h> 20#include <mach/da8xx.h>
21#include <mach/irqs.h> 21
22#include "irqs.h"
22 23
23#define DA8XX_USB0_BASE 0x01e00000 24#define DA8XX_USB0_BASE 0x01e00000
24#define DA8XX_USB1_BASE 0x01e25000 25#define DA8XX_USB1_BASE 0x01e25000
@@ -70,7 +71,7 @@ static struct resource da8xx_usb20_resources[] = {
70 .flags = IORESOURCE_MEM, 71 .flags = IORESOURCE_MEM,
71 }, 72 },
72 { 73 {
73 .start = IRQ_DA8XX_USB_INT, 74 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_USB_INT),
74 .flags = IORESOURCE_IRQ, 75 .flags = IORESOURCE_IRQ,
75 .name = "mc", 76 .name = "mc",
76 }, 77 },
@@ -105,8 +106,8 @@ static struct resource da8xx_usb11_resources[] = {
105 .flags = IORESOURCE_MEM, 106 .flags = IORESOURCE_MEM,
106 }, 107 },
107 [1] = { 108 [1] = {
108 .start = IRQ_DA8XX_IRQN, 109 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
109 .end = IRQ_DA8XX_IRQN, 110 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
110 .flags = IORESOURCE_IRQ, 111 .flags = IORESOURCE_IRQ,
111 }, 112 },
112}; 113};
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 31ed7aa47227..dd8db61cdd1c 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -2,16 +2,16 @@
2/* 2/*
3 * USB 3 * USB
4 */ 4 */
5#include <linux/dma-mapping.h>
5#include <linux/init.h> 6#include <linux/init.h>
6#include <linux/platform_device.h> 7#include <linux/platform_device.h>
7#include <linux/dma-mapping.h> 8#include <linux/platform_data/usb-davinci.h>
8
9#include <linux/usb/musb.h> 9#include <linux/usb/musb.h>
10 10
11#include <mach/common.h> 11#include <mach/common.h>
12#include <mach/irqs.h>
13#include <mach/cputype.h> 12#include <mach/cputype.h>
14#include <linux/platform_data/usb-davinci.h> 13
14#include "irqs.h"
15 15
16#define DAVINCI_USB_OTG_BASE 0x01c64000 16#define DAVINCI_USB_OTG_BASE 0x01c64000
17 17
@@ -38,7 +38,7 @@ static struct resource usb_resources[] = {
38 .flags = IORESOURCE_MEM, 38 .flags = IORESOURCE_MEM,
39 }, 39 },
40 { 40 {
41 .start = IRQ_USBINT, 41 .start = DAVINCI_INTC_IRQ(IRQ_USBINT),
42 .flags = IORESOURCE_IRQ, 42 .flags = IORESOURCE_IRQ,
43 .name = "mc" 43 .name = "mc"
44 }, 44 },
@@ -70,8 +70,9 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
70 70
71 if (cpu_is_davinci_dm646x()) { 71 if (cpu_is_davinci_dm646x()) {
72 /* Override the defaults as DM6467 uses different IRQs. */ 72 /* Override the defaults as DM6467 uses different IRQs. */
73 usb_dev.resource[1].start = IRQ_DM646X_USBINT; 73 usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT);
74 usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT; 74 usb_dev.resource[2].start = DAVINCI_INTC_IRQ(
75 IRQ_DM646X_USBDMAINT);
75 } else /* other devices don't have dedicated CPPI IRQ */ 76 } else /* other devices don't have dedicated CPPI IRQ */
76 usb_dev.num_resources = 2; 77 usb_dev.num_resources = 2;
77 78
diff --git a/drivers/input/keyboard/davinci_keyscan.c b/drivers/input/keyboard/davinci_keyscan.c
index b20a5d044caa..b4db72f833ca 100644
--- a/drivers/input/keyboard/davinci_keyscan.c
+++ b/drivers/input/keyboard/davinci_keyscan.c
@@ -32,10 +32,6 @@
32#include <linux/errno.h> 32#include <linux/errno.h>
33#include <linux/slab.h> 33#include <linux/slab.h>
34 34
35#include <asm/irq.h>
36
37#include <mach/hardware.h>
38#include <mach/irqs.h>
39#include <linux/platform_data/keyscan-davinci.h> 35#include <linux/platform_data/keyscan-davinci.h>
40 36
41/* Key scan registers */ 37/* Key scan registers */
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 5dcb5456cd14..5438abb1baba 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -129,6 +129,16 @@ config BRCMSTB_L2_IRQ
129 select GENERIC_IRQ_CHIP 129 select GENERIC_IRQ_CHIP
130 select IRQ_DOMAIN 130 select IRQ_DOMAIN
131 131
132config DAVINCI_AINTC
133 bool
134 select GENERIC_IRQ_CHIP
135 select IRQ_DOMAIN
136
137config DAVINCI_CP_INTC
138 bool
139 select GENERIC_IRQ_CHIP
140 select IRQ_DOMAIN
141
132config DW_APB_ICTL 142config DW_APB_ICTL
133 bool 143 bool
134 select GENERIC_IRQ_CHIP 144 select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 7acd0e36d0b4..85972ae1bd7f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,8 @@ obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
6obj-$(CONFIG_ATH79) += irq-ath79-misc.o 6obj-$(CONFIG_ATH79) += irq-ath79-misc.o
7obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 7obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
8obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o 8obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
9obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
10obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
9obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o 11obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
10obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o 12obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
11obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o 13obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
diff --git a/drivers/irqchip/irq-davinci-aintc.c b/drivers/irqchip/irq-davinci-aintc.c
new file mode 100644
index 000000000000..810ccc4fe476
--- /dev/null
+++ b/drivers/irqchip/irq-davinci-aintc.c
@@ -0,0 +1,163 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2//
3// Copyright (C) 2006, 2019 Texas Instruments.
4//
5// Interrupt handler for DaVinci boards.
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/irq.h>
11#include <linux/irqchip/irq-davinci-aintc.h>
12#include <linux/io.h>
13#include <linux/irqdomain.h>
14
15#include <asm/exception.h>
16
17#define DAVINCI_AINTC_FIQ_REG0 0x00
18#define DAVINCI_AINTC_FIQ_REG1 0x04
19#define DAVINCI_AINTC_IRQ_REG0 0x08
20#define DAVINCI_AINTC_IRQ_REG1 0x0c
21#define DAVINCI_AINTC_IRQ_IRQENTRY 0x14
22#define DAVINCI_AINTC_IRQ_ENT_REG0 0x18
23#define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c
24#define DAVINCI_AINTC_IRQ_INCTL_REG 0x20
25#define DAVINCI_AINTC_IRQ_EABASE_REG 0x24
26#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30
27#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c
28
29static void __iomem *davinci_aintc_base;
30static struct irq_domain *davinci_aintc_irq_domain;
31
32static inline void davinci_aintc_writel(unsigned long value, int offset)
33{
34 writel_relaxed(value, davinci_aintc_base + offset);
35}
36
37static inline unsigned long davinci_aintc_readl(int offset)
38{
39 return readl_relaxed(davinci_aintc_base + offset);
40}
41
42static __init void
43davinci_aintc_setup_gc(void __iomem *base,
44 unsigned int irq_start, unsigned int num)
45{
46 struct irq_chip_generic *gc;
47 struct irq_chip_type *ct;
48
49 gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start);
50 gc->reg_base = base;
51 gc->irq_base = irq_start;
52
53 ct = gc->chip_types;
54 ct->chip.irq_ack = irq_gc_ack_set_bit;
55 ct->chip.irq_mask = irq_gc_mask_clr_bit;
56 ct->chip.irq_unmask = irq_gc_mask_set_bit;
57
58 ct->regs.ack = DAVINCI_AINTC_IRQ_REG0;
59 ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0;
60 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
61 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
62}
63
64static asmlinkage void __exception_irq_entry
65davinci_aintc_handle_irq(struct pt_regs *regs)
66{
67 int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY);
68
69 /*
70 * Use the formula for entry vector index generation from section
71 * 8.3.3 of the manual.
72 */
73 irqnr >>= 2;
74 irqnr -= 1;
75
76 handle_domain_irq(davinci_aintc_irq_domain, irqnr, regs);
77}
78
79/* ARM Interrupt Controller Initialization */
80void __init davinci_aintc_init(const struct davinci_aintc_config *config)
81{
82 unsigned int irq_off, reg_off, prio, shift;
83 void __iomem *req;
84 int ret, irq_base;
85 const u8 *prios;
86
87 req = request_mem_region(config->reg.start,
88 resource_size(&config->reg),
89 "davinci-cp-intc");
90 if (!req) {
91 pr_err("%s: register range busy\n", __func__);
92 return;
93 }
94
95 davinci_aintc_base = ioremap(config->reg.start,
96 resource_size(&config->reg));
97 if (!davinci_aintc_base) {
98 pr_err("%s: unable to ioremap register range\n", __func__);
99 return;
100 }
101
102 /* Clear all interrupt requests */
103 davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
104 davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
105 davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
106 davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
107
108 /* Disable all interrupts */
109 davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0);
110 davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1);
111
112 /* Interrupts disabled immediately, IRQ entry reflects all */
113 davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG);
114
115 /* we don't use the hardware vector table, just its entry addresses */
116 davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG);
117
118 /* Clear all interrupt requests */
119 davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
120 davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
121 davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
122 davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
123
124 prios = config->prios;
125 for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG;
126 reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) {
127 for (shift = 0, prio = 0; shift < 32; shift += 4, prios++)
128 prio |= (*prios & 0x07) << shift;
129 davinci_aintc_writel(prio, reg_off);
130 }
131
132 irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
133 if (irq_base < 0) {
134 pr_err("%s: unable to allocate interrupt descriptors: %d\n",
135 __func__, irq_base);
136 return;
137 }
138
139 davinci_aintc_irq_domain = irq_domain_add_legacy(NULL,
140 config->num_irqs, irq_base, 0,
141 &irq_domain_simple_ops, NULL);
142 if (!davinci_aintc_irq_domain) {
143 pr_err("%s: unable to create interrupt domain\n", __func__);
144 return;
145 }
146
147 ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1,
148 "AINTC", handle_edge_irq,
149 IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0);
150 if (ret) {
151 pr_err("%s: unable to allocate generic irq chips for domain\n",
152 __func__);
153 return;
154 }
155
156 for (irq_off = 0, reg_off = 0;
157 irq_off < config->num_irqs;
158 irq_off += 32, reg_off += 0x04)
159 davinci_aintc_setup_gc(davinci_aintc_base + reg_off,
160 irq_base + irq_off, 32);
161
162 set_handle_irq(davinci_aintc_handle_irq);
163}
diff --git a/drivers/irqchip/irq-davinci-cp-intc.c b/drivers/irqchip/irq-davinci-cp-intc.c
new file mode 100644
index 000000000000..276da2772e7f
--- /dev/null
+++ b/drivers/irqchip/irq-davinci-cp-intc.c
@@ -0,0 +1,260 @@
1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Author: Steve Chen <schen@mvista.com>
4// Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
5// Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
6// Copyright (C) 2019, Texas Instruments
7//
8// TI Common Platform Interrupt Controller (cp_intc) driver
9
10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/irq.h>
13#include <linux/irqchip.h>
14#include <linux/irqchip/irq-davinci-cp-intc.h>
15#include <linux/irqdomain.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20
21#include <asm/exception.h>
22
23#define DAVINCI_CP_INTC_CTRL 0x04
24#define DAVINCI_CP_INTC_HOST_CTRL 0x0c
25#define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10
26#define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24
27#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28
28#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2c
29#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
30#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
31#define DAVINCI_CP_INTC_PRIO_IDX 0x80
32#define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
33#define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
34#define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
35#define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0d00 + (n << 2))
36#define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0d80 + (n << 2))
37#define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
38#define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0)
39#define DAVINCI_CP_INTC_GPIR_NONE BIT(31)
40
41static void __iomem *davinci_cp_intc_base;
42static struct irq_domain *davinci_cp_intc_irq_domain;
43
44static inline unsigned int davinci_cp_intc_read(unsigned int offset)
45{
46 return readl_relaxed(davinci_cp_intc_base + offset);
47}
48
49static inline void davinci_cp_intc_write(unsigned long value,
50 unsigned int offset)
51{
52 writel_relaxed(value, davinci_cp_intc_base + offset);
53}
54
55static void davinci_cp_intc_ack_irq(struct irq_data *d)
56{
57 davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR);
58}
59
60static void davinci_cp_intc_mask_irq(struct irq_data *d)
61{
62 /* XXX don't know why we need to disable nIRQ here... */
63 davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR);
64 davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR);
65 davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
66}
67
68static void davinci_cp_intc_unmask_irq(struct irq_data *d)
69{
70 davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET);
71}
72
73static int davinci_cp_intc_set_irq_type(struct irq_data *d,
74 unsigned int flow_type)
75{
76 unsigned int reg, mask, polarity, type;
77
78 reg = BIT_WORD(d->hwirq);
79 mask = BIT_MASK(d->hwirq);
80 polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg));
81 type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg));
82
83 switch (flow_type) {
84 case IRQ_TYPE_EDGE_RISING:
85 polarity |= mask;
86 type |= mask;
87 break;
88 case IRQ_TYPE_EDGE_FALLING:
89 polarity &= ~mask;
90 type |= mask;
91 break;
92 case IRQ_TYPE_LEVEL_HIGH:
93 polarity |= mask;
94 type &= ~mask;
95 break;
96 case IRQ_TYPE_LEVEL_LOW:
97 polarity &= ~mask;
98 type &= ~mask;
99 break;
100 default:
101 return -EINVAL;
102 }
103
104 davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg));
105 davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg));
106
107 return 0;
108}
109
110static struct irq_chip davinci_cp_intc_irq_chip = {
111 .name = "cp_intc",
112 .irq_ack = davinci_cp_intc_ack_irq,
113 .irq_mask = davinci_cp_intc_mask_irq,
114 .irq_unmask = davinci_cp_intc_unmask_irq,
115 .irq_set_type = davinci_cp_intc_set_irq_type,
116 .flags = IRQCHIP_SKIP_SET_WAKE,
117};
118
119static asmlinkage void __exception_irq_entry
120davinci_cp_intc_handle_irq(struct pt_regs *regs)
121{
122 int gpir, irqnr, none;
123
124 /*
125 * The interrupt number is in first ten bits. The NONE field set to 1
126 * indicates a spurious irq.
127 */
128
129 gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX);
130 irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK;
131 none = gpir & DAVINCI_CP_INTC_GPIR_NONE;
132
133 if (unlikely(none)) {
134 pr_err_once("%s: spurious irq!\n", __func__);
135 return;
136 }
137
138 handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs);
139}
140
141static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq,
142 irq_hw_number_t hw)
143{
144 pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
145
146 irq_set_chip(virq, &davinci_cp_intc_irq_chip);
147 irq_set_probe(virq);
148 irq_set_handler(virq, handle_edge_irq);
149
150 return 0;
151}
152
153static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
154 .map = davinci_cp_intc_host_map,
155 .xlate = irq_domain_xlate_onetwocell,
156};
157
158static int __init
159davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
160 struct device_node *node)
161{
162 unsigned int num_regs = BITS_TO_LONGS(config->num_irqs);
163 int offset, irq_base;
164 void __iomem *req;
165
166 req = request_mem_region(config->reg.start,
167 resource_size(&config->reg),
168 "davinci-cp-intc");
169 if (!req) {
170 pr_err("%s: register range busy\n", __func__);
171 return -EBUSY;
172 }
173
174 davinci_cp_intc_base = ioremap(config->reg.start,
175 resource_size(&config->reg));
176 if (!davinci_cp_intc_base) {
177 pr_err("%s: unable to ioremap register range\n", __func__);
178 return -EINVAL;
179 }
180
181 davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE);
182
183 /* Disable all host interrupts */
184 davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
185
186 /* Disable system interrupts */
187 for (offset = 0; offset < num_regs; offset++)
188 davinci_cp_intc_write(~0,
189 DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset));
190
191 /* Set to normal mode, no nesting, no priority hold */
192 davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
193 davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
194
195 /* Clear system interrupt status */
196 for (offset = 0; offset < num_regs; offset++)
197 davinci_cp_intc_write(~0,
198 DAVINCI_CP_INTC_SYS_STAT_CLR(offset));
199
200 /* Enable nIRQ (what about nFIQ?) */
201 davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
202
203 /* Default all priorities to channel 7. */
204 num_regs = (config->num_irqs + 3) >> 2; /* 4 channels per register */
205 for (offset = 0; offset < num_regs; offset++)
206 davinci_cp_intc_write(0x07070707,
207 DAVINCI_CP_INTC_CHAN_MAP(offset));
208
209 irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
210 if (irq_base < 0) {
211 pr_err("%s: unable to allocate interrupt descriptors: %d\n",
212 __func__, irq_base);
213 return irq_base;
214 }
215
216 davinci_cp_intc_irq_domain = irq_domain_add_legacy(
217 node, config->num_irqs, irq_base, 0,
218 &davinci_cp_intc_irq_domain_ops, NULL);
219
220 if (!davinci_cp_intc_irq_domain) {
221 pr_err("%s: unable to create an interrupt domain\n", __func__);
222 return -EINVAL;
223 }
224
225 set_handle_irq(davinci_cp_intc_handle_irq);
226
227 /* Enable global interrupt */
228 davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE);
229
230 return 0;
231}
232
233int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config)
234{
235 return davinci_cp_intc_do_init(config, NULL);
236}
237
238static int __init davinci_cp_intc_of_init(struct device_node *node,
239 struct device_node *parent)
240{
241 struct davinci_cp_intc_config config = { };
242 int ret;
243
244 ret = of_address_to_resource(node, 0, &config.reg);
245 if (ret) {
246 pr_err("%s: unable to get the register range from device-tree\n",
247 __func__);
248 return ret;
249 }
250
251 ret = of_property_read_u32(node, "ti,intc-size", &config.num_irqs);
252 if (ret) {
253 pr_err("%s: unable to read the 'ti,intc-size' property\n",
254 __func__);
255 return ret;
256 }
257
258 return davinci_cp_intc_do_init(&config, node);
259}
260IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);
diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig
index bb126be1eb72..8b21b40a9fe5 100644
--- a/drivers/net/ethernet/ti/Kconfig
+++ b/drivers/net/ethernet/ti/Kconfig
@@ -49,10 +49,11 @@ config TI_DAVINCI_CPDMA
49 will be called davinci_cpdma. This is recommended. 49 will be called davinci_cpdma. This is recommended.
50 50
51config TI_CPSW_PHY_SEL 51config TI_CPSW_PHY_SEL
52 bool 52 bool "TI CPSW Phy mode Selection (DEPRECATED)"
53 default n
53 ---help--- 54 ---help---
54 This driver supports configuring of the phy mode connected to 55 This driver supports configuring of the phy mode connected to
55 the CPSW. 56 the CPSW. DEPRECATED: use PHY_TI_GMII_SEL.
56 57
57config TI_CPSW_ALE 58config TI_CPSW_ALE
58 tristate "TI CPSW ALE Support" 59 tristate "TI CPSW ALE Support"
@@ -64,7 +65,6 @@ config TI_CPSW
64 depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST 65 depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST
65 select TI_DAVINCI_CPDMA 66 select TI_DAVINCI_CPDMA
66 select TI_DAVINCI_MDIO 67 select TI_DAVINCI_MDIO
67 select TI_CPSW_PHY_SEL
68 select TI_CPSW_ALE 68 select TI_CPSW_ALE
69 select MFD_SYSCON 69 select MFD_SYSCON
70 select REGMAP 70 select REGMAP
diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h
index cf111db3dc27..907e05fc22e4 100644
--- a/drivers/net/ethernet/ti/cpsw.h
+++ b/drivers/net/ethernet/ti/cpsw.h
@@ -21,7 +21,13 @@
21 ((mac)[2] << 16) | ((mac)[3] << 24)) 21 ((mac)[2] << 16) | ((mac)[3] << 24))
22#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 22#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
23 23
24#if IS_ENABLED(CONFIG_TI_CPSW_PHY_SEL)
24void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave); 25void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave);
26#else
27static inline
28void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
29{}
30#endif
25int ti_cm_get_macid(struct device *dev, int slave, u8 *mac_addr); 31int ti_cm_get_macid(struct device *dev, int slave, u8 *mac_addr);
26 32
27#endif /* __CPSW_H__ */ 33#endif /* __CPSW_H__ */
diff --git a/include/linux/irqchip/irq-davinci-aintc.h b/include/linux/irqchip/irq-davinci-aintc.h
new file mode 100644
index 000000000000..ea4e087fac98
--- /dev/null
+++ b/include/linux/irqchip/irq-davinci-aintc.h
@@ -0,0 +1,27 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2019 Texas Instruments
4 */
5
6#ifndef _LINUX_IRQ_DAVINCI_AINTC_
7#define _LINUX_IRQ_DAVINCI_AINTC_
8
9#include <linux/ioport.h>
10
11/**
12 * struct davinci_aintc_config - configuration data for davinci-aintc driver.
13 *
14 * @reg: register range to map
15 * @num_irqs: number of HW interrupts supported by the controller
16 * @prios: an array of size num_irqs containing priority settings for
17 * each interrupt
18 */
19struct davinci_aintc_config {
20 struct resource reg;
21 unsigned int num_irqs;
22 u8 *prios;
23};
24
25void davinci_aintc_init(const struct davinci_aintc_config *config);
26
27#endif /* _LINUX_IRQ_DAVINCI_AINTC_ */
diff --git a/include/linux/irqchip/irq-davinci-cp-intc.h b/include/linux/irqchip/irq-davinci-cp-intc.h
new file mode 100644
index 000000000000..8d71ed5b5a61
--- /dev/null
+++ b/include/linux/irqchip/irq-davinci-cp-intc.h
@@ -0,0 +1,25 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2019 Texas Instruments
4 */
5
6#ifndef _LINUX_IRQ_DAVINCI_CP_INTC_
7#define _LINUX_IRQ_DAVINCI_CP_INTC_
8
9#include <linux/ioport.h>
10
11/**
12 * struct davinci_cp_intc_config - configuration data for davinci-cp-intc
13 * driver.
14 *
15 * @reg: register range to map
16 * @num_irqs: number of HW interrupts supported by the controller
17 */
18struct davinci_cp_intc_config {
19 struct resource reg;
20 unsigned int num_irqs;
21};
22
23int davinci_cp_intc_init(const struct davinci_cp_intc_config *config);
24
25#endif /* _LINUX_IRQ_DAVINCI_CP_INTC_ */
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