arm64: dts: h3ulcb: enable SCIF clk and pins

This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

1 files changed, 13 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index ecb9e1102266..67ce368ff9ee 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -37,10 +37,18 @@
 };
 
 &pfc {
+        pinctrl-0 = <&scif_clk_pins>;
+        pinctrl-names = "default";
+
         scif2_pins: scif2 {
                 groups = "scif2_data_a";
                 function = "scif2";
         };
+
+        scif_clk_pins: scif_clk {
+                groups = "scif_clk_a";
+                function = "scif_clk";
+        };
 };
 
 &scif2 {
@@ -49,3 +57,8 @@
 
         status = "okay";
 };
+
+&scif_clk {
+        clock-frequency = <14745600>;
+        status = "okay";
+};