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authorJosé Roberto de Souza <jose.souza@intel.com>2018-03-28 18:30:40 -0400
committerRodrigo Vivi <rodrigo.vivi@intel.com>2018-03-30 13:17:55 -0400
commitaee3bac0a3a89ea12644533142ba69eebb602e4c (patch)
tree460cbcfdc59eac8c953de0924ae6e988dd75a054
parent6ce9b78a7388c37b33293666aa6fc61c177046e6 (diff)
drm/i915/psr: Tie PSR2 support to Y coordinate requirement
Although i915 don't implement aux sync frame through tests was findout that pannels can do selective update when the y-coordinate is also included in SDP, that is why it is required to run PSR2 in i915. So moving to only one place the sink requirements that the actual driver needs to enable PSR2. Also intel_psr2_config_valid() is called every time the crtc config is computed, wasting some time every time it was checking for Y coordinate requirement. This allow us to nuke y_cord_support and some of VSC setup code that was handling a scenario that would never happen(PSR2 without Y coordinate). Also here renaming intel_dp_get_y_cord_status() to intel_dp_get_y_coord_required() as it more accurate to the name and function of bit according to eDP spec. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-4-jose.souza@intel.com
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c46
2 files changed, 19 insertions, 28 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fade9029b6f5..92cf6f4e9e00 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -604,7 +604,6 @@ struct i915_psr {
604 unsigned busy_frontbuffer_bits; 604 unsigned busy_frontbuffer_bits;
605 bool psr2_support; 605 bool psr2_support;
606 bool link_standby; 606 bool link_standby;
607 bool y_cord_support;
608 bool colorimetry_support; 607 bool colorimetry_support;
609 bool alpm; 608 bool alpm;
610 bool has_hw_tracking; 609 bool has_hw_tracking;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c0a6f63b586f..fb2d0fe7106b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -93,7 +93,7 @@ static void psr_aux_io_power_put(struct intel_dp *intel_dp)
93 intel_display_power_put(dev_priv, psr_aux_domain(intel_dp)); 93 intel_display_power_put(dev_priv, psr_aux_domain(intel_dp));
94} 94}
95 95
96static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) 96static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
97{ 97{
98 uint8_t psr_caps = 0; 98 uint8_t psr_caps = 0;
99 99
@@ -130,22 +130,29 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
130 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 130 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
131 sizeof(intel_dp->psr_dpcd)); 131 sizeof(intel_dp->psr_dpcd));
132 132
133 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 133 if (intel_dp->psr_dpcd[0]) {
134 dev_priv->psr.sink_support = true; 134 dev_priv->psr.sink_support = true;
135 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 135 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
136 } 136 }
137 137
138 if (INTEL_GEN(dev_priv) >= 9 && 138 if (INTEL_GEN(dev_priv) >= 9 &&
139 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { 139 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
140 140 /*
141 dev_priv->psr.sink_support = true; 141 * All panels that supports PSR version 03h (PSR2 +
142 dev_priv->psr.psr2_support = true; 142 * Y-coordinate) can handle Y-coordinates in VSC but we are
143 * only sure that it is going to be used when required by the
144 * panel. This way panel is capable to do selective update
145 * without a aux frame sync.
146 *
147 * To support PSR version 02h and PSR version 03h without
148 * Y-coordinate requirement panels we would need to enable
149 * GTC first.
150 */
151 dev_priv->psr.psr2_support = intel_dp_get_y_coord_required(intel_dp);
143 DRM_DEBUG_KMS("PSR2 %s on sink", 152 DRM_DEBUG_KMS("PSR2 %s on sink",
144 dev_priv->psr.psr2_support ? "supported" : "not supported"); 153 dev_priv->psr.psr2_support ? "supported" : "not supported");
145 154
146 if (dev_priv->psr.psr2_support) { 155 if (dev_priv->psr.psr2_support) {
147 dev_priv->psr.y_cord_support =
148 intel_dp_get_y_cord_status(intel_dp);
149 dev_priv->psr.colorimetry_support = 156 dev_priv->psr.colorimetry_support =
150 intel_dp_get_colorimetry_status(intel_dp); 157 intel_dp_get_colorimetry_status(intel_dp);
151 dev_priv->psr.alpm = 158 dev_priv->psr.alpm =
@@ -191,16 +198,12 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
191 memset(&psr_vsc, 0, sizeof(psr_vsc)); 198 memset(&psr_vsc, 0, sizeof(psr_vsc));
192 psr_vsc.sdp_header.HB0 = 0; 199 psr_vsc.sdp_header.HB0 = 0;
193 psr_vsc.sdp_header.HB1 = 0x7; 200 psr_vsc.sdp_header.HB1 = 0x7;
194 if (dev_priv->psr.colorimetry_support && 201 if (dev_priv->psr.colorimetry_support) {
195 dev_priv->psr.y_cord_support) {
196 psr_vsc.sdp_header.HB2 = 0x5; 202 psr_vsc.sdp_header.HB2 = 0x5;
197 psr_vsc.sdp_header.HB3 = 0x13; 203 psr_vsc.sdp_header.HB3 = 0x13;
198 } else if (dev_priv->psr.y_cord_support) { 204 } else {
199 psr_vsc.sdp_header.HB2 = 0x4; 205 psr_vsc.sdp_header.HB2 = 0x4;
200 psr_vsc.sdp_header.HB3 = 0xe; 206 psr_vsc.sdp_header.HB3 = 0xe;
201 } else {
202 psr_vsc.sdp_header.HB2 = 0x3;
203 psr_vsc.sdp_header.HB3 = 0xc;
204 } 207 }
205 } else { 208 } else {
206 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 209 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
@@ -457,15 +460,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
457 return false; 460 return false;
458 } 461 }
459 462
460 /*
461 * FIXME:enable psr2 only for y-cordinate psr2 panels
462 * After gtc implementation , remove this restriction.
463 */
464 if (!dev_priv->psr.y_cord_support) {
465 DRM_DEBUG_KMS("PSR2 not enabled, panel does not support Y coordinate\n");
466 return false;
467 }
468
469 return true; 463 return true;
470} 464}
471 465
@@ -565,7 +559,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
565 struct drm_device *dev = dig_port->base.base.dev; 559 struct drm_device *dev = dig_port->base.base.dev;
566 struct drm_i915_private *dev_priv = to_i915(dev); 560 struct drm_i915_private *dev_priv = to_i915(dev);
567 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 561 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
568 u32 chicken;
569 562
570 psr_aux_io_power_get(intel_dp); 563 psr_aux_io_power_get(intel_dp);
571 564
@@ -576,9 +569,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
576 hsw_psr_setup_aux(intel_dp); 569 hsw_psr_setup_aux(intel_dp);
577 570
578 if (dev_priv->psr.psr2_support) { 571 if (dev_priv->psr.psr2_support) {
579 chicken = PSR2_VSC_ENABLE_PROG_HEADER; 572 u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
580 if (dev_priv->psr.y_cord_support) 573 | PSR2_ADD_VERTICAL_LINE_COUNT;
581 chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
582 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); 574 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
583 575
584 I915_WRITE(EDP_PSR_DEBUG, 576 I915_WRITE(EDP_PSR_DEBUG,