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authorDavid S. Miller <davem@davemloft.net>2015-09-24 18:39:09 -0400
committerDavid S. Miller <davem@davemloft.net>2015-09-24 18:39:09 -0400
commitaee2f545f0a12399cc6bbe134d69b8994582b694 (patch)
tree8f2276564581309652fc00b63cc492ecb8f04f5b
parentd8ed625044cdede8661324074aaad7459a1e3c7a (diff)
parent21dd560162d4bbf98cc81b303bfa19740ae5b964 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
Jeff Kirsher says: ==================== Intel Wired LAN Driver Updates 2015-09-23 This series contains updates to ixgbe only. Mark provides all the changes in this series, first clears the destination location for I2C data initially so that the received data will not be corrupted by previous attempts. Then reduced the pauses/delays in the PHY detection when no SFP is present by reducing the number of retires, once an SFP is detected, the "normal" number of retries in PHY detection will be used. Added support for X55EM_x SFP+ dual-speed, and fixed 1G and 10G link stability for X550EM_x by configuring the CS4227 correctly by moving code to ixgbe_setup_mac_link_sfp_x550em(). Added functionality to reset CS4227, since on some platforms the CS4227 does not initialize properly. Next reduces the SFP polling rate, due to when an SFP is not present, the I2C timeouts that result are very costly. So prevent the SFP polling from being done more than once every two seconds. Added support for I2C bus MUX. Fixed the setting of RDRXCTL register which should fall through X540 and 82599, not 82598. In addition, added small packet padding support in X550 by setting RDRXCTL.PSP when the driver is in SRIOV mode. Fixed a known hardware issue where the PCI transactions pending bit sticks high when there are pending transactions, so workaround the issue by wait and then continue with our reset flow. Added a new device ID for X550EM device with SFPs. Provided a fix with the DCA setup, which was suggested by Alex Duyck <aduyck@mirantis.com>, by making it so that we always set the relaxed ordering bits related to the DCA registers even if DCA is not enbaled. Then moves the configuration out of the ixgbe_down() and into ixgbe_configure() before enabling the transmit and receive rings. This ensures that DCA is configured correctly before starting the processing of packets. Fixed VM-to-VM loopback mode which requires that FCRTH be set, but the datasheets did not specify what the value should be. It has now been determined that the correct value should be RXPBSIZE - (24*1024). ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe.h2
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c192
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_common.c226
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_common.h5
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c8
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_main.c61
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c21
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h27
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_type.h4
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c102
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c485
11 files changed, 855 insertions, 278 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
index a699c991ad2c..dda0f678339a 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
@@ -594,6 +594,7 @@ struct ixgbe_mac_addr {
594 594
595/* default to trying for four seconds */ 595/* default to trying for four seconds */
596#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 596#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
597#define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
597 598
598/* board specific private data structure */ 599/* board specific private data structure */
599struct ixgbe_adapter { 600struct ixgbe_adapter {
@@ -707,6 +708,7 @@ struct ixgbe_adapter {
707 708
708 u32 link_speed; 709 u32 link_speed;
709 bool link_up; 710 bool link_up;
711 unsigned long sfp_poll_time;
710 unsigned long link_check_timeout; 712 unsigned long link_check_timeout;
711 713
712 struct timer_list service_timer; 714 struct timer_list service_timer;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
index 85156fb53b62..a39afcf03e2c 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
@@ -44,9 +44,8 @@
44static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 44static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 45static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
47static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 47static void
48 ixgbe_link_speed speed, 48ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *, ixgbe_link_speed);
49 bool autoneg_wait_to_complete);
50static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed, 50 ixgbe_link_speed speed,
52 bool autoneg_wait_to_complete); 51 bool autoneg_wait_to_complete);
@@ -109,6 +108,9 @@ static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
109 if (hw->phy.multispeed_fiber) { 108 if (hw->phy.multispeed_fiber) {
110 /* Set up dual speed SFP+ support */ 109 /* Set up dual speed SFP+ support */
111 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 110 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
111 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
112 mac->ops.set_rate_select_speed =
113 ixgbe_set_hard_rate_select_speed;
112 } else { 114 } else {
113 if ((mac->ops.get_media_type(hw) == 115 if ((mac->ops.get_media_type(hw) ==
114 ixgbe_media_type_backplane) && 116 ixgbe_media_type_backplane) &&
@@ -646,176 +648,32 @@ static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
646} 648}
647 649
648/** 650/**
649 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 651 * ixgbe_set_hard_rate_select_speed - Set module link speed
650 * @hw: pointer to hardware structure 652 * @hw: pointer to hardware structure
651 * @speed: new link speed 653 * @speed: link speed to set
652 * @autoneg_wait_to_complete: true when waiting for completion is needed
653 * 654 *
654 * Set the link speed in the AUTOC register and restarts link. 655 * Set module link speed via RS0/RS1 rate select pins.
655 **/ 656 */
656static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 657static void
657 ixgbe_link_speed speed, 658ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
658 bool autoneg_wait_to_complete)
659{ 659{
660 s32 status = 0;
661 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
662 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
663 u32 speedcnt = 0;
664 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 660 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
665 u32 i = 0;
666 bool link_up = false;
667 bool autoneg = false;
668 661
669 /* Mask off requested but non-supported speeds */ 662 switch (speed) {
670 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, 663 case IXGBE_LINK_SPEED_10GB_FULL:
671 &autoneg); 664 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
672 if (status != 0) 665 break;
673 return status; 666 case IXGBE_LINK_SPEED_1GB_FULL:
674 667 esdp_reg &= ~IXGBE_ESDP_SDP5;
675 speed &= link_speed; 668 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
676 669 break;
677 /* 670 default:
678 * Try each speed one by one, highest priority first. We do this in 671 hw_dbg(hw, "Invalid fixed module speed\n");
679 * software because 10gb fiber doesn't support speed autonegotiation. 672 return;
680 */
681 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
682 speedcnt++;
683 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
684
685 /* If we already have link at this speed, just jump out */
686 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
687 false);
688 if (status != 0)
689 return status;
690
691 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
692 goto out;
693
694 /* Set the module link speed */
695 switch (hw->phy.media_type) {
696 case ixgbe_media_type_fiber:
697 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
698 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
699 IXGBE_WRITE_FLUSH(hw);
700 break;
701 case ixgbe_media_type_fiber_qsfp:
702 /* QSFP module automatically detects MAC link speed */
703 break;
704 default:
705 hw_dbg(hw, "Unexpected media type.\n");
706 break;
707 }
708
709 /* Allow module to change analog characteristics (1G->10G) */
710 msleep(40);
711
712 status = ixgbe_setup_mac_link_82599(hw,
713 IXGBE_LINK_SPEED_10GB_FULL,
714 autoneg_wait_to_complete);
715 if (status != 0)
716 return status;
717
718 /* Flap the tx laser if it has not already been done */
719 if (hw->mac.ops.flap_tx_laser)
720 hw->mac.ops.flap_tx_laser(hw);
721
722 /*
723 * Wait for the controller to acquire link. Per IEEE 802.3ap,
724 * Section 73.10.2, we may have to wait up to 500ms if KR is
725 * attempted. 82599 uses the same timing for 10g SFI.
726 */
727 for (i = 0; i < 5; i++) {
728 /* Wait for the link partner to also set speed */
729 msleep(100);
730
731 /* If we have link, just jump out */
732 status = hw->mac.ops.check_link(hw, &link_speed,
733 &link_up, false);
734 if (status != 0)
735 return status;
736
737 if (link_up)
738 goto out;
739 }
740 }
741
742 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
743 speedcnt++;
744 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
745 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
746
747 /* If we already have link at this speed, just jump out */
748 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
749 false);
750 if (status != 0)
751 return status;
752
753 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
754 goto out;
755
756 /* Set the module link speed */
757 switch (hw->phy.media_type) {
758 case ixgbe_media_type_fiber:
759 esdp_reg &= ~IXGBE_ESDP_SDP5;
760 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
761 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
762 IXGBE_WRITE_FLUSH(hw);
763 break;
764 case ixgbe_media_type_fiber_qsfp:
765 /* QSFP module automatically detects MAC link speed */
766 break;
767 default:
768 hw_dbg(hw, "Unexpected media type.\n");
769 break;
770 }
771
772 /* Allow module to change analog characteristics (10G->1G) */
773 msleep(40);
774
775 status = ixgbe_setup_mac_link_82599(hw,
776 IXGBE_LINK_SPEED_1GB_FULL,
777 autoneg_wait_to_complete);
778 if (status != 0)
779 return status;
780
781 /* Flap the tx laser if it has not already been done */
782 if (hw->mac.ops.flap_tx_laser)
783 hw->mac.ops.flap_tx_laser(hw);
784
785 /* Wait for the link partner to also set speed */
786 msleep(100);
787
788 /* If we have link, just jump out */
789 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
790 false);
791 if (status != 0)
792 return status;
793
794 if (link_up)
795 goto out;
796 } 673 }
797 674
798 /* 675 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
799 * We didn't get link. Configure back to the highest speed we tried, 676 IXGBE_WRITE_FLUSH(hw);
800 * (if there was more than one). We call ourselves back with just the
801 * single highest speed that the user requested.
802 */
803 if (speedcnt > 1)
804 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
805 highest_link_speed,
806 autoneg_wait_to_complete);
807
808out:
809 /* Set autoneg_advertised value based on input link speed */
810 hw->phy.autoneg_advertised = 0;
811
812 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
813 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
814
815 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
816 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
817
818 return status;
819} 677}
820 678
821/** 679/**
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
index 3f56a8080118..ce61b36b94f1 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
@@ -297,13 +297,13 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
297 297
298 /* Setup flow control */ 298 /* Setup flow control */
299 ret_val = ixgbe_setup_fc(hw); 299 ret_val = ixgbe_setup_fc(hw);
300 if (!ret_val) 300 if (ret_val)
301 return 0; 301 return ret_val;
302 302
303 /* Clear adapter stopped flag */ 303 /* Clear adapter stopped flag */
304 hw->adapter_stopped = false; 304 hw->adapter_stopped = false;
305 305
306 return ret_val; 306 return 0;
307} 307}
308 308
309/** 309/**
@@ -2164,10 +2164,11 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2164 /* 2164 /*
2165 * In order to prevent Tx hangs when the internal Tx 2165 * In order to prevent Tx hangs when the internal Tx
2166 * switch is enabled we must set the high water mark 2166 * switch is enabled we must set the high water mark
2167 * to the maximum FCRTH value. This allows the Tx 2167 * to the Rx packet buffer size - 24KB. This allows
2168 * switch to function even under heavy Rx workloads. 2168 * the Tx switch to function even under heavy Rx
2169 * workloads.
2169 */ 2170 */
2170 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 2171 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2171 } 2172 }
2172 2173
2173 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2174 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
@@ -2476,6 +2477,9 @@ static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2476 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2477 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2477 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2478 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2478 2479
2480 if (hw->mac.type >= ixgbe_mac_X550)
2481 return 0;
2482
2479 /* 2483 /*
2480 * Before proceeding, make sure that the PCIe block does not have 2484 * Before proceeding, make sure that the PCIe block does not have
2481 * transactions pending. 2485 * transactions pending.
@@ -3920,3 +3924,213 @@ bool ixgbe_mng_present(struct ixgbe_hw *hw)
3920 fwsm &= IXGBE_FWSM_MODE_MASK; 3924 fwsm &= IXGBE_FWSM_MODE_MASK;
3921 return fwsm == IXGBE_FWSM_FW_MODE_PT; 3925 return fwsm == IXGBE_FWSM_FW_MODE_PT;
3922} 3926}
3927
3928/**
3929 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
3930 * @hw: pointer to hardware structure
3931 * @speed: new link speed
3932 * @autoneg_wait_to_complete: true when waiting for completion is needed
3933 *
3934 * Set the link speed in the MAC and/or PHY register and restarts link.
3935 */
3936s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
3937 ixgbe_link_speed speed,
3938 bool autoneg_wait_to_complete)
3939{
3940 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3941 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3942 s32 status = 0;
3943 u32 speedcnt = 0;
3944 u32 i = 0;
3945 bool autoneg, link_up = false;
3946
3947 /* Mask off requested but non-supported speeds */
3948 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg);
3949 if (status)
3950 return status;
3951
3952 speed &= link_speed;
3953
3954 /* Try each speed one by one, highest priority first. We do this in
3955 * software because 10Gb fiber doesn't support speed autonegotiation.
3956 */
3957 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
3958 speedcnt++;
3959 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
3960
3961 /* If we already have link at this speed, just jump out */
3962 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
3963 false);
3964 if (status)
3965 return status;
3966
3967 if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up)
3968 goto out;
3969
3970 /* Set the module link speed */
3971 switch (hw->phy.media_type) {
3972 case ixgbe_media_type_fiber:
3973 hw->mac.ops.set_rate_select_speed(hw,
3974 IXGBE_LINK_SPEED_10GB_FULL);
3975 break;
3976 case ixgbe_media_type_fiber_qsfp:
3977 /* QSFP module automatically detects MAC link speed */
3978 break;
3979 default:
3980 hw_dbg(hw, "Unexpected media type\n");
3981 break;
3982 }
3983
3984 /* Allow module to change analog characteristics (1G->10G) */
3985 msleep(40);
3986
3987 status = hw->mac.ops.setup_mac_link(hw,
3988 IXGBE_LINK_SPEED_10GB_FULL,
3989 autoneg_wait_to_complete);
3990 if (status)
3991 return status;
3992
3993 /* Flap the Tx laser if it has not already been done */
3994 if (hw->mac.ops.flap_tx_laser)
3995 hw->mac.ops.flap_tx_laser(hw);
3996
3997 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
3998 * Section 73.10.2, we may have to wait up to 500ms if KR is
3999 * attempted. 82599 uses the same timing for 10g SFI.
4000 */
4001 for (i = 0; i < 5; i++) {
4002 /* Wait for the link partner to also set speed */
4003 msleep(100);
4004
4005 /* If we have link, just jump out */
4006 status = hw->mac.ops.check_link(hw, &link_speed,
4007 &link_up, false);
4008 if (status)
4009 return status;
4010
4011 if (link_up)
4012 goto out;
4013 }
4014 }
4015
4016 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4017 speedcnt++;
4018 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4019 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4020
4021 /* If we already have link at this speed, just jump out */
4022 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4023 false);
4024 if (status)
4025 return status;
4026
4027 if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up)
4028 goto out;
4029
4030 /* Set the module link speed */
4031 switch (hw->phy.media_type) {
4032 case ixgbe_media_type_fiber:
4033 hw->mac.ops.set_rate_select_speed(hw,
4034 IXGBE_LINK_SPEED_1GB_FULL);
4035 break;
4036 case ixgbe_media_type_fiber_qsfp:
4037 /* QSFP module automatically detects link speed */
4038 break;
4039 default:
4040 hw_dbg(hw, "Unexpected media type\n");
4041 break;
4042 }
4043
4044 /* Allow module to change analog characteristics (10G->1G) */
4045 msleep(40);
4046
4047 status = hw->mac.ops.setup_mac_link(hw,
4048 IXGBE_LINK_SPEED_1GB_FULL,
4049 autoneg_wait_to_complete);
4050 if (status)
4051 return status;
4052
4053 /* Flap the Tx laser if it has not already been done */
4054 if (hw->mac.ops.flap_tx_laser)
4055 hw->mac.ops.flap_tx_laser(hw);
4056
4057 /* Wait for the link partner to also set speed */
4058 msleep(100);
4059
4060 /* If we have link, just jump out */
4061 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4062 false);
4063 if (status)
4064 return status;
4065
4066 if (link_up)
4067 goto out;
4068 }
4069
4070 /* We didn't get link. Configure back to the highest speed we tried,
4071 * (if there was more than one). We call ourselves back with just the
4072 * single highest speed that the user requested.
4073 */
4074 if (speedcnt > 1)
4075 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4076 highest_link_speed,
4077 autoneg_wait_to_complete);
4078
4079out:
4080 /* Set autoneg_advertised value based on input link speed */
4081 hw->phy.autoneg_advertised = 0;
4082
4083 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4084 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4085
4086 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4087 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4088
4089 return status;
4090}
4091
4092/**
4093 * ixgbe_set_soft_rate_select_speed - Set module link speed
4094 * @hw: pointer to hardware structure
4095 * @speed: link speed to set
4096 *
4097 * Set module link speed via the soft rate select.
4098 */
4099void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4100 ixgbe_link_speed speed)
4101{
4102 s32 status;
4103 u8 rs, eeprom_data;
4104
4105 switch (speed) {
4106 case IXGBE_LINK_SPEED_10GB_FULL:
4107 /* one bit mask same as setting on */
4108 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4109 break;
4110 case IXGBE_LINK_SPEED_1GB_FULL:
4111 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4112 break;
4113 default:
4114 hw_dbg(hw, "Invalid fixed module speed\n");
4115 return;
4116 }
4117
4118 /* Set RS0 */
4119 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4120 IXGBE_I2C_EEPROM_DEV_ADDR2,
4121 &eeprom_data);
4122 if (status) {
4123 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
4124 return;
4125 }
4126
4127 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4128
4129 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4130 IXGBE_I2C_EEPROM_DEV_ADDR2,
4131 eeprom_data);
4132 if (status) {
4133 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
4134 return;
4135 }
4136}
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
index 2f779f35dc4f..a0044e4a8b90 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
@@ -135,6 +135,11 @@ s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);
135s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw); 135s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);
136void ixgbe_disable_rx_generic(struct ixgbe_hw *hw); 136void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);
137void ixgbe_enable_rx_generic(struct ixgbe_hw *hw); 137void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);
138s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
139 ixgbe_link_speed speed,
140 bool autoneg_wait_to_complete);
141void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
142 ixgbe_link_speed speed);
138 143
139#define IXGBE_FAILED_READ_REG 0xffffffffU 144#define IXGBE_FAILED_READ_REG 0xffffffffU
140#define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU 145#define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
index 3b932fe64ab6..23277ab153b6 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
@@ -259,7 +259,13 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
259 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 259 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
260 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 260 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
261 } else { 261 } else {
262 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 262 /* In order to prevent Tx hangs when the internal Tx
263 * switch is enabled we must set the high water mark
264 * to the Rx packet buffer size - 24KB. This allows
265 * the Tx switch to function even under heavy Rx
266 * workloads.
267 */
268 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
263 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 269 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
264 } 270 }
265 271
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 369204c18832..191003901adb 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -79,7 +79,7 @@ char ixgbe_default_device_descr[] =
79static char ixgbe_default_device_descr[] = 79static char ixgbe_default_device_descr[] =
80 "Intel(R) 10 Gigabit Network Connection"; 80 "Intel(R) 10 Gigabit Network Connection";
81#endif 81#endif
82#define DRV_VERSION "4.0.1-k" 82#define DRV_VERSION "4.2.1-k"
83const char ixgbe_driver_version[] = DRV_VERSION; 83const char ixgbe_driver_version[] = DRV_VERSION;
84static const char ixgbe_copyright[] = 84static const char ixgbe_copyright[] =
85 "Copyright (c) 1999-2015 Intel Corporation."; 85 "Copyright (c) 1999-2015 Intel Corporation.";
@@ -137,6 +137,7 @@ static const struct pci_device_id ixgbe_pci_tbl[] = {
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
140 /* required last entry */ 141 /* required last entry */
141 {0, } 142 {0, }
142}; 143};
@@ -1244,9 +1245,12 @@ static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1244 int cpu) 1245 int cpu)
1245{ 1246{
1246 struct ixgbe_hw *hw = &adapter->hw; 1247 struct ixgbe_hw *hw = &adapter->hw;
1247 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1248 u32 txctrl = 0;
1248 u16 reg_offset; 1249 u16 reg_offset;
1249 1250
1251 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1252 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1253
1250 switch (hw->mac.type) { 1254 switch (hw->mac.type) {
1251 case ixgbe_mac_82598EB: 1255 case ixgbe_mac_82598EB:
1252 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1256 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
@@ -1278,9 +1282,11 @@ static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1278 int cpu) 1282 int cpu)
1279{ 1283{
1280 struct ixgbe_hw *hw = &adapter->hw; 1284 struct ixgbe_hw *hw = &adapter->hw;
1281 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1285 u32 rxctrl = 0;
1282 u8 reg_idx = rx_ring->reg_idx; 1286 u8 reg_idx = rx_ring->reg_idx;
1283 1287
1288 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1289 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1284 1290
1285 switch (hw->mac.type) { 1291 switch (hw->mac.type) {
1286 case ixgbe_mac_82599EB: 1292 case ixgbe_mac_82599EB:
@@ -1297,6 +1303,7 @@ static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1297 * which will cause the DCA tag to be cleared. 1303 * which will cause the DCA tag to be cleared.
1298 */ 1304 */
1299 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1305 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1306 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1300 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1307 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1301 1308
1302 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1309 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
@@ -1326,11 +1333,13 @@ static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1326{ 1333{
1327 int i; 1334 int i;
1328 1335
1329 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1330 return;
1331
1332 /* always use CB2 mode, difference is masked in the CB driver */ 1336 /* always use CB2 mode, difference is masked in the CB driver */
1333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); 1337 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1339 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1340 else
1341 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1342 IXGBE_DCA_CTRL_DCA_DISABLE);
1334 1343
1335 for (i = 0; i < adapter->num_q_vectors; i++) { 1344 for (i = 0; i < adapter->num_q_vectors; i++) {
1336 adapter->q_vector[i]->cpu = -1; 1345 adapter->q_vector[i]->cpu = -1;
@@ -1353,7 +1362,8 @@ static int __ixgbe_notify_dca(struct device *dev, void *data)
1353 break; 1362 break;
1354 if (dca_add_requester(dev) == 0) { 1363 if (dca_add_requester(dev) == 0) {
1355 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1364 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1356 ixgbe_setup_dca(adapter); 1365 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1366 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1357 break; 1367 break;
1358 } 1368 }
1359 /* Fall Through since DCA is disabled. */ 1369 /* Fall Through since DCA is disabled. */
@@ -1361,7 +1371,8 @@ static int __ixgbe_notify_dca(struct device *dev, void *data)
1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1371 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1362 dca_remove_requester(dev); 1372 dca_remove_requester(dev);
1363 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1373 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 1374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1375 IXGBE_DCA_CTRL_DCA_DISABLE);
1365 } 1376 }
1366 break; 1377 break;
1367 } 1378 }
@@ -2509,6 +2520,7 @@ static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2509 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2510 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2511 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2522 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2523 adapter->sfp_poll_time = 0;
2512 ixgbe_service_event_schedule(adapter); 2524 ixgbe_service_event_schedule(adapter);
2513 } 2525 }
2514 } 2526 }
@@ -3788,8 +3800,6 @@ static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3788 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3800 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3789 3801
3790 switch (hw->mac.type) { 3802 switch (hw->mac.type) {
3791 case ixgbe_mac_X550:
3792 case ixgbe_mac_X550EM_x:
3793 case ixgbe_mac_82598EB: 3803 case ixgbe_mac_82598EB:
3794 /* 3804 /*
3795 * For VMDq support of different descriptor types or 3805 * For VMDq support of different descriptor types or
@@ -3803,6 +3813,11 @@ static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3803 */ 3813 */
3804 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3814 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3805 break; 3815 break;
3816 case ixgbe_mac_X550:
3817 case ixgbe_mac_X550EM_x:
3818 if (adapter->num_vfs)
3819 rdrxctl |= IXGBE_RDRXCTL_PSP;
3820 /* fall through for older HW */
3806 case ixgbe_mac_82599EB: 3821 case ixgbe_mac_82599EB:
3807 case ixgbe_mac_X540: 3822 case ixgbe_mac_X540:
3808 /* Disable RSC for ACK packets */ 3823 /* Disable RSC for ACK packets */
@@ -4778,6 +4793,12 @@ static void ixgbe_configure(struct ixgbe_adapter *adapter)
4778 break; 4793 break;
4779 } 4794 }
4780 4795
4796#ifdef CONFIG_IXGBE_DCA
4797 /* configure DCA */
4798 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
4799 ixgbe_setup_dca(adapter);
4800#endif /* CONFIG_IXGBE_DCA */
4801
4781#ifdef IXGBE_FCOE 4802#ifdef IXGBE_FCOE
4782 /* configure FCoE L2 filters, redirection table, and Rx control */ 4803 /* configure FCoE L2 filters, redirection table, and Rx control */
4783 ixgbe_configure_fcoe(adapter); 4804 ixgbe_configure_fcoe(adapter);
@@ -4804,6 +4825,7 @@ static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4804 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 4825 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4805 4826
4806 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 4827 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4828 adapter->sfp_poll_time = 0;
4807} 4829}
4808 4830
4809/** 4831/**
@@ -4894,9 +4916,6 @@ static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4894 case ixgbe_mac_82599EB: 4916 case ixgbe_mac_82599EB:
4895 gpie |= IXGBE_SDP0_GPIEN_8259X; 4917 gpie |= IXGBE_SDP0_GPIEN_8259X;
4896 break; 4918 break;
4897 case ixgbe_mac_X540:
4898 gpie |= IXGBE_EIMS_TS;
4899 break;
4900 default: 4919 default:
4901 break; 4920 break;
4902 } 4921 }
@@ -5237,11 +5256,6 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
5237 5256
5238 ixgbe_clean_all_tx_rings(adapter); 5257 ixgbe_clean_all_tx_rings(adapter);
5239 ixgbe_clean_all_rx_rings(adapter); 5258 ixgbe_clean_all_rx_rings(adapter);
5240
5241#ifdef CONFIG_IXGBE_DCA
5242 /* since we reset the hardware DCA settings were cleared */
5243 ixgbe_setup_dca(adapter);
5244#endif
5245} 5259}
5246 5260
5247/** 5261/**
@@ -6709,10 +6723,16 @@ static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6709 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6723 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6710 return; 6724 return;
6711 6725
6726 if (adapter->sfp_poll_time &&
6727 time_after(adapter->sfp_poll_time, jiffies))
6728 return; /* If not yet time to poll for SFP */
6729
6712 /* someone else is in init, wait until next service event */ 6730 /* someone else is in init, wait until next service event */
6713 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6731 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6714 return; 6732 return;
6715 6733
6734 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6735
6716 err = hw->phy.ops.identify_sfp(hw); 6736 err = hw->phy.ops.identify_sfp(hw);
6717 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6737 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6718 goto sfp_out; 6738 goto sfp_out;
@@ -9024,7 +9044,8 @@ static void ixgbe_remove(struct pci_dev *pdev)
9024 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 9044 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9025 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 9045 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9026 dca_remove_requester(&pdev->dev); 9046 dca_remove_requester(&pdev->dev);
9027 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 9047 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9048 IXGBE_DCA_CTRL_DCA_DISABLE);
9028 } 9049 }
9029 9050
9030#endif 9051#endif
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
index 315f0597fbc0..fb8673d63806 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
@@ -1230,7 +1230,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1230 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1230 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1231 else 1231 else
1232 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1232 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1233 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1233 } else {
1234 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1234 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1235 if (hw->bus.lan_id == 0) 1235 if (hw->bus.lan_id == 0)
1236 hw->phy.sfp_type = 1236 hw->phy.sfp_type =
@@ -1731,6 +1731,21 @@ s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1731} 1731}
1732 1732
1733/** 1733/**
1734 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1735 * @hw: pointer to hardware structure
1736 * @offset: eeprom offset to be read
1737 * @addr: I2C address to be read
1738 */
1739static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1740{
1741 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1742 offset == IXGBE_SFF_IDENTIFIER &&
1743 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1744 return true;
1745 return false;
1746}
1747
1748/**
1734 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1749 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1735 * @hw: pointer to hardware structure 1750 * @hw: pointer to hardware structure
1736 * @byte_offset: byte offset to read 1751 * @byte_offset: byte offset to read
@@ -1749,6 +1764,9 @@ static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1749 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1764 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1750 bool nack = true; 1765 bool nack = true;
1751 1766
1767 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1768 max_retry = IXGBE_SFP_DETECT_RETRIES;
1769
1752 *data = 0; 1770 *data = 0;
1753 1771
1754 do { 1772 do {
@@ -2026,6 +2044,7 @@ static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2026 s32 i; 2044 s32 i;
2027 bool bit = false; 2045 bool bit = false;
2028 2046
2047 *data = 0;
2029 for (i = 7; i >= 0; i--) { 2048 for (i = 7; i >= 0; i--) {
2030 ixgbe_clock_in_i2c_bit(hw, &bit); 2049 ixgbe_clock_in_i2c_bit(hw, &bit);
2031 *data |= bit << i; 2050 *data |= bit << i;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
index 4c06484fdebc..5abd66c84d00 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
@@ -66,6 +66,9 @@
66#define IXGBE_SFF_1GBASET_CAPABLE 0x8 66#define IXGBE_SFF_1GBASET_CAPABLE 0x8
67#define IXGBE_SFF_10GBASESR_CAPABLE 0x10 67#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
68#define IXGBE_SFF_10GBASELR_CAPABLE 0x20 68#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
69#define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
70#define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8
71#define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0
69#define IXGBE_SFF_ADDRESSING_MODE 0x4 72#define IXGBE_SFF_ADDRESSING_MODE 0x4
70#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 73#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
71#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 74#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
@@ -78,9 +81,29 @@
78#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 81#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
79#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 82#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
80#define IXGBE_CS4227 0xBE /* CS4227 address */ 83#define IXGBE_CS4227 0xBE /* CS4227 address */
81#define IXGBE_CS4227_SPARE24_LSB 0x12B0 /* Reg to program EDC */ 84#define IXGBE_CS4227_SCRATCH 2
85#define IXGBE_CS4227_RESET_PENDING 0x1357
86#define IXGBE_CS4227_RESET_COMPLETE 0x5AA5
87#define IXGBE_CS4227_RETRIES 15
88#define IXGBE_CS4227_EFUSE_STATUS 0x0181
89#define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to set speed */
90#define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to set EDC */
91#define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to set speed */
92#define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */
93#define IXGBE_CS4227_EEPROM_STATUS 0x5001
94#define IXGBE_CS4227_EEPROM_LOAD_OK 0x0001
95#define IXGBE_CS4227_SPEED_1G 0x8000
96#define IXGBE_CS4227_SPEED_10G 0
82#define IXGBE_CS4227_EDC_MODE_CX1 0x0002 97#define IXGBE_CS4227_EDC_MODE_CX1 0x0002
83#define IXGBE_CS4227_EDC_MODE_SR 0x0004 98#define IXGBE_CS4227_EDC_MODE_SR 0x0004
99#define IXGBE_CS4227_EDC_MODE_DIAG 0x0008
100#define IXGBE_CS4227_RESET_HOLD 500 /* microseconds */
101#define IXGBE_CS4227_RESET_DELAY 500 /* milliseconds */
102#define IXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */
103#define IXGBE_PE 0xE0 /* Port expander addr */
104#define IXGBE_PE_OUTPUT 1 /* Output reg offset */
105#define IXGBE_PE_CONFIG 3 /* Config reg offset */
106#define IXGBE_PE_BIT1 (1 << 1)
84 107
85/* Flow control defines */ 108/* Flow control defines */
86#define IXGBE_TAF_SYM_PAUSE 0x400 109#define IXGBE_TAF_SYM_PAUSE 0x400
@@ -109,6 +132,8 @@
109#define IXGBE_I2C_T_SU_STO 4 132#define IXGBE_I2C_T_SU_STO 4
110#define IXGBE_I2C_T_BUF 5 133#define IXGBE_I2C_T_BUF 5
111 134
135#define IXGBE_SFP_DETECT_RETRIES 2
136
112#define IXGBE_TN_LASI_STATUS_REG 0x9005 137#define IXGBE_TN_LASI_STATUS_REG 0x9005
113#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 138#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
114 139
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
index 3be743b4f6ba..939c90c4ff39 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -1193,6 +1193,7 @@ struct ixgbe_thermal_sensor_data {
1193/* RDRXCTL Bit Masks */ 1193/* RDRXCTL Bit Masks */
1194#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ 1194#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
1195#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1195#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
1196#define IXGBE_RDRXCTL_PSP 0x00000004 /* Pad small packet */
1196#define IXGBE_RDRXCTL_MVMEN 0x00000020 1197#define IXGBE_RDRXCTL_MVMEN 0x00000020
1197#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1198#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
1198#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 1199#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
@@ -1949,6 +1950,7 @@ enum {
1949#define IXGBE_GSSR_SW_MNG_SM 0x0400 1950#define IXGBE_GSSR_SW_MNG_SM 0x0400
1950#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */ 1951#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */
1951#define IXGBE_GSSR_I2C_MASK 0x1800 1952#define IXGBE_GSSR_I2C_MASK 0x1800
1953#define IXGBE_GSSR_NVM_PHY_MASK 0xF
1952 1954
1953/* FW Status register bitmask */ 1955/* FW Status register bitmask */
1954#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 1956#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
@@ -3256,9 +3258,11 @@ struct ixgbe_mac_operations {
3256 void (*flap_tx_laser)(struct ixgbe_hw *); 3258 void (*flap_tx_laser)(struct ixgbe_hw *);
3257 void (*stop_link_on_d3)(struct ixgbe_hw *); 3259 void (*stop_link_on_d3)(struct ixgbe_hw *);
3258 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3260 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3261 s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3259 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 3262 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3260 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 3263 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3261 bool *); 3264 bool *);
3265 void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3262 3266
3263 /* Packet Buffer Manipulation */ 3267 /* Packet Buffer Manipulation */
3264 void (*set_rxpba)(struct ixgbe_hw *, int, u32, int); 3268 void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
index 4e758435ece8..c1d4584f6469 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
@@ -567,19 +567,25 @@ static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
567 **/ 567 **/
568s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 568s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
569{ 569{
570 u32 swfw_sync; 570 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
571 u32 swmask = mask; 571 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
572 u32 fwmask = mask << 5; 572 u32 fwmask = swmask << 5;
573 u32 hwmask = 0;
574 u32 timeout = 200; 573 u32 timeout = 200;
574 u32 hwmask = 0;
575 u32 swfw_sync;
575 u32 i; 576 u32 i;
576 577
577 if (swmask == IXGBE_GSSR_EEP_SM) 578 if (swmask & IXGBE_GSSR_EEP_SM)
578 hwmask = IXGBE_GSSR_FLASH_SM; 579 hwmask = IXGBE_GSSR_FLASH_SM;
579 580
581 /* SW only mask does not have FW bit pair */
582 if (mask & IXGBE_GSSR_SW_MNG_SM)
583 swmask |= IXGBE_GSSR_SW_MNG_SM;
584
585 swmask |= swi2c_mask;
586 fwmask |= swi2c_mask << 2;
580 for (i = 0; i < timeout; i++) { 587 for (i = 0; i < timeout; i++) {
581 /* 588 /* SW NVM semaphore bit is used for access to all
582 * SW NVM semaphore bit is used for access to all
583 * SW_FW_SYNC bits (not just NVM) 589 * SW_FW_SYNC bits (not just NVM)
584 */ 590 */
585 if (ixgbe_get_swfw_sync_semaphore(hw)) 591 if (ixgbe_get_swfw_sync_semaphore(hw))
@@ -590,39 +596,56 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
590 swfw_sync |= swmask; 596 swfw_sync |= swmask;
591 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); 597 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
592 ixgbe_release_swfw_sync_semaphore(hw); 598 ixgbe_release_swfw_sync_semaphore(hw);
593 break; 599 usleep_range(5000, 6000);
594 } else { 600 return 0;
595 /*
596 * Firmware currently using resource (fwmask),
597 * hardware currently using resource (hwmask),
598 * or other software thread currently using
599 * resource (swmask)
600 */
601 ixgbe_release_swfw_sync_semaphore(hw);
602 usleep_range(5000, 10000);
603 } 601 }
602 /* Firmware currently using resource (fwmask), hardware
603 * currently using resource (hwmask), or other software
604 * thread currently using resource (swmask)
605 */
606 ixgbe_release_swfw_sync_semaphore(hw);
607 usleep_range(5000, 10000);
604 } 608 }
605 609
606 /* 610 /* Failed to get SW only semaphore */
607 * If the resource is not released by the FW/HW the SW can assume that 611 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
608 * the FW/HW malfunctions. In that case the SW should sets the 612 hw_dbg(hw, "Failed to get SW only semaphore\n");
609 * SW bit(s) of the requested resource(s) while ignoring the 613 return IXGBE_ERR_SWFW_SYNC;
610 * corresponding FW/HW bits in the SW_FW_SYNC register. 614 }
611 */
612 if (i >= timeout) {
613 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
614 if (swfw_sync & (fwmask | hwmask)) {
615 if (ixgbe_get_swfw_sync_semaphore(hw))
616 return IXGBE_ERR_SWFW_SYNC;
617 615
618 swfw_sync |= swmask; 616 /* If the resource is not released by the FW/HW the SW can assume that
619 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); 617 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
620 ixgbe_release_swfw_sync_semaphore(hw); 618 * of the requested resource(s) while ignoring the corresponding FW/HW
621 } 619 * bits in the SW_FW_SYNC register.
620 */
621 if (ixgbe_get_swfw_sync_semaphore(hw))
622 return IXGBE_ERR_SWFW_SYNC;
623 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
624 if (swfw_sync & (fwmask | hwmask)) {
625 swfw_sync |= swmask;
626 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
627 ixgbe_release_swfw_sync_semaphore(hw);
628 usleep_range(5000, 6000);
629 return 0;
622 } 630 }
631 /* If the resource is not released by other SW the SW can assume that
632 * the other SW malfunctions. In that case the SW should clear all SW
633 * flags that it does not own and then repeat the whole process once
634 * again.
635 */
636 if (swfw_sync & swmask) {
637 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
638 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
639
640 if (swi2c_mask)
641 rmask |= IXGBE_GSSR_I2C_MASK;
642 ixgbe_release_swfw_sync_X540(hw, rmask);
643 ixgbe_release_swfw_sync_semaphore(hw);
644 return IXGBE_ERR_SWFW_SYNC;
645 }
646 ixgbe_release_swfw_sync_semaphore(hw);
623 647
624 usleep_range(5000, 10000); 648 return IXGBE_ERR_SWFW_SYNC;
625 return 0;
626} 649}
627 650
628/** 651/**
@@ -635,9 +658,11 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
635 **/ 658 **/
636void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 659void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
637{ 660{
661 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
638 u32 swfw_sync; 662 u32 swfw_sync;
639 u32 swmask = mask;
640 663
664 if (mask & IXGBE_GSSR_I2C_MASK)
665 swmask |= mask & IXGBE_GSSR_I2C_MASK;
641 ixgbe_get_swfw_sync_semaphore(hw); 666 ixgbe_get_swfw_sync_semaphore(hw);
642 667
643 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); 668 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
@@ -645,7 +670,7 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
645 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); 670 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
646 671
647 ixgbe_release_swfw_sync_semaphore(hw); 672 ixgbe_release_swfw_sync_semaphore(hw);
648 usleep_range(5000, 10000); 673 usleep_range(5000, 6000);
649} 674}
650 675
651/** 676/**
@@ -686,6 +711,11 @@ static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
686 usleep_range(50, 100); 711 usleep_range(50, 100);
687 } 712 }
688 713
714 /* Release semaphores and return error if SW NVM semaphore
715 * was not granted because we do not have access to the EEPROM
716 */
717 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
718 ixgbe_release_swfw_sync_semaphore(hw);
689 return IXGBE_ERR_EEPROM; 719 return IXGBE_ERR_EEPROM;
690} 720}
691 721
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
index 2a1dca6e8d44..ed7b2899affe 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
@@ -56,6 +56,283 @@ static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
56 IXGBE_WRITE_FLUSH(hw); 56 IXGBE_WRITE_FLUSH(hw);
57} 57}
58 58
59/**
60 * ixgbe_read_cs4227 - Read CS4227 register
61 * @hw: pointer to hardware structure
62 * @reg: register number to write
63 * @value: pointer to receive value read
64 *
65 * Returns status code
66 */
67static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
68{
69 return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
70 value);
71}
72
73/**
74 * ixgbe_write_cs4227 - Write CS4227 register
75 * @hw: pointer to hardware structure
76 * @reg: register number to write
77 * @value: value to write to register
78 *
79 * Returns status code
80 */
81static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
82{
83 return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
84 value);
85}
86
87/**
88 * ixgbe_check_cs4227_reg - Perform diag on a CS4227 register
89 * @hw: pointer to hardware structure
90 * @reg: the register to check
91 *
92 * Performs a diagnostic on a register in the CS4227 chip. Returns an error
93 * if it is not operating correctly.
94 * This function assumes that the caller has acquired the proper semaphore.
95 */
96static s32 ixgbe_check_cs4227_reg(struct ixgbe_hw *hw, u16 reg)
97{
98 s32 status;
99 u32 retry;
100 u16 reg_val;
101
102 reg_val = (IXGBE_CS4227_EDC_MODE_DIAG << 1) | 1;
103 status = ixgbe_write_cs4227(hw, reg, reg_val);
104 if (status)
105 return status;
106 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
107 msleep(IXGBE_CS4227_CHECK_DELAY);
108 reg_val = 0xFFFF;
109 ixgbe_read_cs4227(hw, reg, &reg_val);
110 if (!reg_val)
111 break;
112 }
113 if (reg_val) {
114 hw_err(hw, "CS4227 reg 0x%04X failed diagnostic\n", reg);
115 return status;
116 }
117
118 return 0;
119}
120
121/**
122 * ixgbe_get_cs4227_status - Return CS4227 status
123 * @hw: pointer to hardware structure
124 *
125 * Performs a diagnostic on the CS4227 chip. Returns an error if it is
126 * not operating correctly.
127 * This function assumes that the caller has acquired the proper semaphore.
128 */
129static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
130{
131 s32 status;
132 u16 value = 0;
133
134 /* Exit if the diagnostic has already been performed. */
135 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
136 if (status)
137 return status;
138 if (value == IXGBE_CS4227_RESET_COMPLETE)
139 return 0;
140
141 /* Check port 0. */
142 status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB);
143 if (status)
144 return status;
145
146 status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB);
147 if (status)
148 return status;
149
150 /* Check port 1. */
151 status = ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_LINE_SPARE24_LSB +
152 (1 << 12));
153 if (status)
154 return status;
155
156 return ixgbe_check_cs4227_reg(hw, IXGBE_CS4227_HOST_SPARE24_LSB +
157 (1 << 12));
158}
159
160/**
161 * ixgbe_read_pe - Read register from port expander
162 * @hw: pointer to hardware structure
163 * @reg: register number to read
164 * @value: pointer to receive read value
165 *
166 * Returns status code
167 */
168static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
169{
170 s32 status;
171
172 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
173 if (status)
174 hw_err(hw, "port expander access failed with %d\n", status);
175 return status;
176}
177
178/**
179 * ixgbe_write_pe - Write register to port expander
180 * @hw: pointer to hardware structure
181 * @reg: register number to write
182 * @value: value to write
183 *
184 * Returns status code
185 */
186static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
187{
188 s32 status;
189
190 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
191 value);
192 if (status)
193 hw_err(hw, "port expander access failed with %d\n", status);
194 return status;
195}
196
197/**
198 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
199 * @hw: pointer to hardware structure
200 *
201 * Returns error code
202 */
203static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
204{
205 s32 status;
206 u32 retry;
207 u16 value;
208 u8 reg;
209
210 /* Trigger hard reset. */
211 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
212 if (status)
213 return status;
214 reg |= IXGBE_PE_BIT1;
215 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
216 if (status)
217 return status;
218
219 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
220 if (status)
221 return status;
222 reg &= ~IXGBE_PE_BIT1;
223 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
224 if (status)
225 return status;
226
227 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
228 if (status)
229 return status;
230 reg &= ~IXGBE_PE_BIT1;
231 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
232 if (status)
233 return status;
234
235 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
236
237 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
238 if (status)
239 return status;
240 reg |= IXGBE_PE_BIT1;
241 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
242 if (status)
243 return status;
244
245 /* Wait for the reset to complete. */
246 msleep(IXGBE_CS4227_RESET_DELAY);
247 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
248 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
249 &value);
250 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
251 break;
252 msleep(IXGBE_CS4227_CHECK_DELAY);
253 }
254 if (retry == IXGBE_CS4227_RETRIES) {
255 hw_err(hw, "CS4227 reset did not complete\n");
256 return IXGBE_ERR_PHY;
257 }
258
259 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
260 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
261 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
262 return IXGBE_ERR_PHY;
263 }
264
265 return 0;
266}
267
268/**
269 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
270 * @hw: pointer to hardware structure
271 */
272static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
273{
274 u32 swfw_mask = hw->phy.phy_semaphore_mask;
275 s32 status;
276 u16 value;
277 u8 retry;
278
279 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
280 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
281 if (status) {
282 hw_err(hw, "semaphore failed with %d\n", status);
283 msleep(IXGBE_CS4227_CHECK_DELAY);
284 continue;
285 }
286
287 /* Get status of reset flow. */
288 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
289 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
290 goto out;
291
292 if (status || value != IXGBE_CS4227_RESET_PENDING)
293 break;
294
295 /* Reset is pending. Wait and check again. */
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
297 msleep(IXGBE_CS4227_CHECK_DELAY);
298 }
299
300 /* Reset the CS4227. */
301 status = ixgbe_reset_cs4227(hw);
302 if (status) {
303 hw_err(hw, "CS4227 reset failed: %d", status);
304 goto out;
305 }
306
307 /* Reset takes so long, temporarily release semaphore in case the
308 * other driver instance is waiting for the reset indication.
309 */
310 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
311 IXGBE_CS4227_RESET_PENDING);
312 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
313 usleep_range(10000, 12000);
314 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
315 if (status) {
316 hw_err(hw, "semaphore failed with %d", status);
317 return;
318 }
319
320 /* Is the CS4227 working correctly? */
321 status = ixgbe_get_cs4227_status(hw);
322 if (status) {
323 hw_err(hw, "CS4227 status failed: %d", status);
324 goto out;
325 }
326
327 /* Record completion for next time. */
328 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
329 IXGBE_CS4227_RESET_COMPLETE);
330
331out:
332 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
333 msleep(hw->eeprom.semaphore_delay);
334}
335
59/** ixgbe_identify_phy_x550em - Get PHY type based on device id 336/** ixgbe_identify_phy_x550em - Get PHY type based on device id
60 * @hw: pointer to hardware structure 337 * @hw: pointer to hardware structure
61 * 338 *
@@ -68,7 +345,7 @@ static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
68 /* set up for CS4227 usage */ 345 /* set up for CS4227 usage */
69 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 346 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
70 ixgbe_setup_mux_ctl(hw); 347 ixgbe_setup_mux_ctl(hw);
71 348 ixgbe_check_cs4227(hw);
72 return ixgbe_identify_module_generic(hw); 349 return ixgbe_identify_module_generic(hw);
73 case IXGBE_DEV_ID_X550EM_X_KX4: 350 case IXGBE_DEV_ID_X550EM_X_KX4:
74 hw->phy.type = ixgbe_phy_x550em_kx4; 351 hw->phy.type = ixgbe_phy_x550em_kx4;
@@ -910,6 +1187,96 @@ static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
910} 1187}
911 1188
912/** 1189/**
1190 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1191 * @hw: pointer to hardware structure
1192 * @linear: true if SFP module is linear
1193 */
1194static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1195{
1196 switch (hw->phy.sfp_type) {
1197 case ixgbe_sfp_type_not_present:
1198 return IXGBE_ERR_SFP_NOT_PRESENT;
1199 case ixgbe_sfp_type_da_cu_core0:
1200 case ixgbe_sfp_type_da_cu_core1:
1201 *linear = true;
1202 break;
1203 case ixgbe_sfp_type_srlr_core0:
1204 case ixgbe_sfp_type_srlr_core1:
1205 case ixgbe_sfp_type_da_act_lmt_core0:
1206 case ixgbe_sfp_type_da_act_lmt_core1:
1207 case ixgbe_sfp_type_1g_sx_core0:
1208 case ixgbe_sfp_type_1g_sx_core1:
1209 case ixgbe_sfp_type_1g_lx_core0:
1210 case ixgbe_sfp_type_1g_lx_core1:
1211 *linear = false;
1212 break;
1213 case ixgbe_sfp_type_unknown:
1214 case ixgbe_sfp_type_1g_cu_core0:
1215 case ixgbe_sfp_type_1g_cu_core1:
1216 default:
1217 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1218 }
1219
1220 return 0;
1221}
1222
1223/**
1224 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1225 * @hw: pointer to hardware structure
1226 *
1227 * Configures the extern PHY and the integrated KR PHY for SFP support.
1228 */
1229static s32
1230ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1231 ixgbe_link_speed speed,
1232 __always_unused bool autoneg_wait_to_complete)
1233{
1234 s32 status;
1235 u16 slice, value;
1236 bool setup_linear = false;
1237
1238 /* Check if SFP module is supported and linear */
1239 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1240
1241 /* If no SFP module present, then return success. Return success since
1242 * there is no reason to configure CS4227 and SFP not present error is
1243 * not accepted in the setup MAC link flow.
1244 */
1245 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1246 return 0;
1247
1248 if (status)
1249 return status;
1250
1251 /* Configure CS4227 LINE side to 10G SR. */
1252 slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1253 value = IXGBE_CS4227_SPEED_10G;
1254 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1255 value);
1256
1257 /* Configure CS4227 for HOST connection rate then type. */
1258 slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1259 value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1260 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1261 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1262 value);
1263
1264 slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1265 if (setup_linear)
1266 value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1267 else
1268 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1269 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227, slice,
1270 value);
1271
1272 /* If internal link mode is XFI, then setup XFI internal link. */
1273 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1274 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1275
1276 return status;
1277}
1278
1279/**
913 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1280 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
914 * @hw: pointer to hardware structure 1281 * @hw: pointer to hardware structure
915 * @speed: new link speed 1282 * @speed: new link speed
@@ -1003,6 +1370,10 @@ static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1003 mac->ops.disable_tx_laser = NULL; 1370 mac->ops.disable_tx_laser = NULL;
1004 mac->ops.enable_tx_laser = NULL; 1371 mac->ops.enable_tx_laser = NULL;
1005 mac->ops.flap_tx_laser = NULL; 1372 mac->ops.flap_tx_laser = NULL;
1373 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1374 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1375 mac->ops.set_rate_select_speed =
1376 ixgbe_set_soft_rate_select_speed;
1006 break; 1377 break;
1007 case ixgbe_media_type_copper: 1378 case ixgbe_media_type_copper:
1008 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 1379 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
@@ -1018,53 +1389,18 @@ static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1018 */ 1389 */
1019static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1390static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1020{ 1391{
1021 bool setup_linear; 1392 s32 status;
1022 u16 reg_slice, edc_mode; 1393 bool linear;
1023 s32 ret_val;
1024 1394
1025 switch (hw->phy.sfp_type) { 1395 /* Check if SFP module is supported */
1026 case ixgbe_sfp_type_unknown: 1396 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1027 return 0; 1397 if (status)
1028 case ixgbe_sfp_type_not_present: 1398 return status;
1029 return IXGBE_ERR_SFP_NOT_PRESENT;
1030 case ixgbe_sfp_type_da_cu_core0:
1031 case ixgbe_sfp_type_da_cu_core1:
1032 setup_linear = true;
1033 break;
1034 case ixgbe_sfp_type_srlr_core0:
1035 case ixgbe_sfp_type_srlr_core1:
1036 case ixgbe_sfp_type_da_act_lmt_core0:
1037 case ixgbe_sfp_type_da_act_lmt_core1:
1038 case ixgbe_sfp_type_1g_sx_core0:
1039 case ixgbe_sfp_type_1g_sx_core1:
1040 setup_linear = false;
1041 break;
1042 default:
1043 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1044 }
1045 1399
1046 ixgbe_init_mac_link_ops_X550em(hw); 1400 ixgbe_init_mac_link_ops_X550em(hw);
1047 hw->phy.ops.reset = NULL; 1401 hw->phy.ops.reset = NULL;
1048 1402
1049 /* The CS4227 slice address is the base address + the port-pair reg 1403 return 0;
1050 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1051 */
1052 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
1053
1054 if (setup_linear)
1055 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1056 else
1057 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1058
1059 /* Configure CS4227 for connection type. */
1060 ret_val = hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1061 edc_mode);
1062
1063 if (ret_val)
1064 ret_val = hw->phy.ops.write_i2c_combined(hw, 0x80, reg_slice,
1065 edc_mode);
1066
1067 return ret_val;
1068} 1404}
1069 1405
1070/** ixgbe_get_link_capabilities_x550em - Determines link capabilities 1406/** ixgbe_get_link_capabilities_x550em - Determines link capabilities
@@ -1927,6 +2263,62 @@ static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
1927 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 2263 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1928} 2264}
1929 2265
2266/**
2267 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2268 * @hw: pointer to hardware structure
2269 * @state: set mux if 1, clear if 0
2270 */
2271static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2272{
2273 u32 esdp;
2274
2275 if (!hw->bus.lan_id)
2276 return;
2277 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2278 if (state)
2279 esdp |= IXGBE_ESDP_SDP1;
2280 else
2281 esdp &= ~IXGBE_ESDP_SDP1;
2282 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2283 IXGBE_WRITE_FLUSH(hw);
2284}
2285
2286/**
2287 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2288 * @hw: pointer to hardware structure
2289 * @mask: Mask to specify which semaphore to acquire
2290 *
2291 * Acquires the SWFW semaphore and sets the I2C MUX
2292 */
2293static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2294{
2295 s32 status;
2296
2297 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2298 if (status)
2299 return status;
2300
2301 if (mask & IXGBE_GSSR_I2C_MASK)
2302 ixgbe_set_mux(hw, 1);
2303
2304 return 0;
2305}
2306
2307/**
2308 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2309 * @hw: pointer to hardware structure
2310 * @mask: Mask to specify which semaphore to release
2311 *
2312 * Releases the SWFW semaphore and sets the I2C MUX
2313 */
2314static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2315{
2316 if (mask & IXGBE_GSSR_I2C_MASK)
2317 ixgbe_set_mux(hw, 0);
2318
2319 ixgbe_release_swfw_sync_X540(hw, mask);
2320}
2321
1930#define X550_COMMON_MAC \ 2322#define X550_COMMON_MAC \
1931 .init_hw = &ixgbe_init_hw_generic, \ 2323 .init_hw = &ixgbe_init_hw_generic, \
1932 .start_hw = &ixgbe_start_hw_X540, \ 2324 .start_hw = &ixgbe_start_hw_X540, \
@@ -1964,8 +2356,6 @@ static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
1964 &ixgbe_set_source_address_pruning_X550, \ 2356 &ixgbe_set_source_address_pruning_X550, \
1965 .set_ethertype_anti_spoofing = \ 2357 .set_ethertype_anti_spoofing = \
1966 &ixgbe_set_ethertype_anti_spoofing_X550, \ 2358 &ixgbe_set_ethertype_anti_spoofing_X550, \
1967 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, \
1968 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, \
1969 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 2359 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
1970 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 2360 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
1971 .get_thermal_sensor_data = NULL, \ 2361 .get_thermal_sensor_data = NULL, \
@@ -1985,6 +2375,8 @@ static struct ixgbe_mac_operations mac_ops_X550 = {
1985 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 2375 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
1986 .get_bus_info = &ixgbe_get_bus_info_generic, 2376 .get_bus_info = &ixgbe_get_bus_info_generic,
1987 .setup_sfp = NULL, 2377 .setup_sfp = NULL,
2378 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
2379 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
1988}; 2380};
1989 2381
1990static struct ixgbe_mac_operations mac_ops_X550EM_x = { 2382static struct ixgbe_mac_operations mac_ops_X550EM_x = {
@@ -1997,7 +2389,8 @@ static struct ixgbe_mac_operations mac_ops_X550EM_x = {
1997 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 2389 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
1998 .get_bus_info = &ixgbe_get_bus_info_X550em, 2390 .get_bus_info = &ixgbe_get_bus_info_X550em,
1999 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 2391 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
2000 2392 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
2393 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
2001}; 2394};
2002 2395
2003#define X550_COMMON_EEP \ 2396#define X550_COMMON_EEP \
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 19:51:37 -0500