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authorOlof Johansson <olof@lixom.net>2016-11-17 20:53:42 -0500
committerOlof Johansson <olof@lixom.net>2016-11-17 20:53:42 -0500
commitaeb961bec7a0226099ec138f8cbe99b7d390484b (patch)
tree2ad8c7e2289a3bee56ed7d06bebdafcd57210370
parent62c2f3f67d9d855fdaf442be1e38a0016d123bf0 (diff)
parent8ac46fc57df82efbc19194dddd335b6c7a960c31 (diff)
Merge tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Finally, I am really pleased to announce adding support for Exynos5433 ARMv8 SoC along with two boards. A lot of Samsung people contributed into this but the final work and commits were done by Chanwoo Choi. This means that for v4.10 we got: 1. Exynos5433 DTSI. 2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones. * tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt2
-rw-r--r--arch/arm64/boot/dts/exynos/Makefile5
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi794
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2.dts974
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts41
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi23
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi22
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi296
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433.dtsi1356
9 files changed, 3512 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index 0ea7f14ef294..c64c7b515777 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -15,6 +15,8 @@ Required root node properties:
15 - "samsung,xyref5260" - for Exynos5260-based Samsung board. 15 - "samsung,xyref5260" - for Exynos5260-based Samsung board.
16 - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. 16 - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
17 - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. 17 - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
18 - "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
19 - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
18 - "samsung,sd5v1" - for Exynos5440-based Samsung board. 20 - "samsung,sd5v1" - for Exynos5440-based Samsung board.
19 - "samsung,ssdk5440" - for Exynos5440-based Samsung board. 21 - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
20 22
diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index 50c9b9383cfa..7ddea53769a7 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -1,4 +1,7 @@
1dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb 1dtb-$(CONFIG_ARCH_EXYNOS) += \
2 exynos5433-tm2.dtb \
3 exynos5433-tm2e.dtb \
4 exynos7-espresso.dtb
2 5
3always := $(dtb-y) 6always := $(dtb-y)
4subdir-y := $(dts-dirs) 7subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
new file mode 100644
index 000000000000..796881310bf6
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -0,0 +1,794 @@
1/*
2 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 *
7 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
8 * tree nodes are listed in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define PIN_PULL_NONE 0
16#define PIN_PULL_DOWN 1
17#define PIN_PULL_UP 3
18
19#define PIN_DRV_LV1 0
20#define PIN_DRV_LV2 2
21#define PIN_DRV_LV3 1
22#define PIN_DRV_LV4 3
23
24#define PIN_IN 0
25#define PIN_OUT 1
26#define PIN_FUNC1 2
27
28#define PIN(_func, _pin, _pull, _drv) \
29 _pin { \
30 samsung,pins = #_pin; \
31 samsung,pin-function = <PIN_ ##_func>; \
32 samsung,pin-pud = <PIN_PULL_ ##_pull>; \
33 samsung,pin-drv = <PIN_DRV_ ##_drv>; \
34 }
35
36&pinctrl_alive {
37 gpa0: gpa0 {
38 gpio-controller;
39 #gpio-cells = <2>;
40
41 interrupt-controller;
42 interrupt-parent = <&gic>;
43 interrupts = <GIC_SPI 0 0>, <GIC_SPI 1 0>, <GIC_SPI 2 0>,
44 <GIC_SPI 3 0>, <GIC_SPI 4 0>, <GIC_SPI 5 0>,
45 <GIC_SPI 6 0>, <GIC_SPI 7 0>;
46 #interrupt-cells = <2>;
47 };
48
49 gpa1: gpa1 {
50 gpio-controller;
51 #gpio-cells = <2>;
52
53 interrupt-controller;
54 interrupt-parent = <&gic>;
55 interrupts = <GIC_SPI 8 0>, <GIC_SPI 9 0>, <GIC_SPI 10 0>,
56 <GIC_SPI 11 0>, <GIC_SPI 12 0>, <GIC_SPI 13 0>,
57 <GIC_SPI 14 0>, <GIC_SPI 15 0>;
58 #interrupt-cells = <2>;
59 };
60
61 gpa2: gpa2 {
62 gpio-controller;
63 #gpio-cells = <2>;
64
65 interrupt-controller;
66 #interrupt-cells = <2>;
67 };
68
69 gpa3: gpa3 {
70 gpio-controller;
71 #gpio-cells = <2>;
72
73 interrupt-controller;
74 #interrupt-cells = <2>;
75 };
76
77 gpf1: gpf1 {
78 gpio-controller;
79 #gpio-cells = <2>;
80
81 interrupt-controller;
82 #interrupt-cells = <2>;
83 };
84
85 gpf2: gpf2 {
86 gpio-controller;
87 #gpio-cells = <2>;
88
89 interrupt-controller;
90 #interrupt-cells = <2>;
91 };
92
93 gpf3: gpf3 {
94 gpio-controller;
95 #gpio-cells = <2>;
96
97 interrupt-controller;
98 #interrupt-cells = <2>;
99 };
100
101 gpf4: gpf4 {
102 gpio-controller;
103 #gpio-cells = <2>;
104
105 interrupt-controller;
106 #interrupt-cells = <2>;
107 };
108
109 gpf5: gpf5 {
110 gpio-controller;
111 #gpio-cells = <2>;
112
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 };
116};
117
118&pinctrl_aud {
119 gpz0: gpz0 {
120 gpio-controller;
121 #gpio-cells = <2>;
122
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 };
126
127 gpz1: gpz1 {
128 gpio-controller;
129 #gpio-cells = <2>;
130
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 i2s0_bus: i2s0-bus {
136 samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
137 "gpz0-4", "gpz0-5", "gpz0-6";
138 samsung,pin-function = <2>;
139 samsung,pin-pud = <1>;
140 samsung,pin-drv = <0>;
141 };
142
143 pcm0_bus: pcm0-bus {
144 samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
145 samsung,pin-function = <3>;
146 samsung,pin-pud = <1>;
147 samsung,pin-drv = <0>;
148 };
149
150 uart_aud_bus: uart-aud-bus {
151 samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0";
152 samsung,pin-function = <2>;
153 samsung,pin-pud = <0>;
154 samsung,pin-drv = <0>;
155 };
156};
157
158&pinctrl_cpif {
159 gpv6: gpv6 {
160 gpio-controller;
161 #gpio-cells = <2>;
162
163 interrupt-controller;
164 #interrupt-cells = <2>;
165 };
166};
167
168&pinctrl_ese {
169 gpj2: gpj2 {
170 gpio-controller;
171 #gpio-cells = <2>;
172
173 interrupt-controller;
174 #interrupt-cells = <2>;
175 };
176};
177
178&pinctrl_finger {
179 gpd5: gpd5 {
180 gpio-controller;
181 #gpio-cells = <2>;
182
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 };
186
187 spi2_bus: spi2-bus {
188 samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";
189 samsung,pin-function = <2>;
190 samsung,pin-pud = <3>;
191 samsung,pin-drv = <0>;
192 };
193
194 hs_i2c6_bus: hs-i2c6-bus {
195 samsung,pins = "gpd5-3", "gpd5-2";
196 samsung,pin-function = <4>;
197 samsung,pin-pud = <3>;
198 samsung,pin-drv = <0>;
199 };
200};
201
202&pinctrl_fsys {
203 gph1: gph1 {
204 gpio-controller;
205 #gpio-cells = <2>;
206
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 };
210
211 gpr4: gpr4 {
212 gpio-controller;
213 #gpio-cells = <2>;
214
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 };
218
219 gpr0: gpr0 {
220 gpio-controller;
221 #gpio-cells = <2>;
222
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 };
226
227 gpr1: gpr1 {
228 gpio-controller;
229 #gpio-cells = <2>;
230
231 interrupt-controller;
232 #interrupt-cells = <2>;
233 };
234
235 gpr2: gpr2 {
236 gpio-controller;
237 #gpio-cells = <2>;
238
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 };
242
243 gpr3: gpr3 {
244 gpio-controller;
245 #gpio-cells = <2>;
246
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 };
250
251 sd0_clk: sd0-clk {
252 samsung,pins = "gpr0-0";
253 samsung,pin-function = <2>;
254 samsung,pin-pud = <0>;
255 samsung,pin-drv = <3>;
256 };
257
258 sd0_cmd: sd0-cmd {
259 samsung,pins = "gpr0-1";
260 samsung,pin-function = <2>;
261 samsung,pin-pud = <0>;
262 samsung,pin-drv = <3>;
263 };
264
265 sd0_rdqs: sd0-rdqs {
266 samsung,pins = "gpr0-2";
267 samsung,pin-function = <2>;
268 samsung,pin-pud = <1>;
269 samsung,pin-drv = <3>;
270 };
271
272 sd0_qrdy: sd0-qrdy {
273 samsung,pins = "gpr0-3";
274 samsung,pin-function = <2>;
275 samsung,pin-pud = <1>;
276 samsung,pin-drv = <3>;
277 };
278
279 sd0_bus1: sd0-bus-width1 {
280 samsung,pins = "gpr1-0";
281 samsung,pin-function = <2>;
282 samsung,pin-pud = <3>;
283 samsung,pin-drv = <3>;
284 };
285
286 sd0_bus4: sd0-bus-width4 {
287 samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
288 samsung,pin-function = <2>;
289 samsung,pin-pud = <3>;
290 samsung,pin-drv = <3>;
291 };
292
293 sd0_bus8: sd0-bus-width8 {
294 samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
295 samsung,pin-function = <2>;
296 samsung,pin-pud = <3>;
297 samsung,pin-drv = <3>;
298 };
299
300 sd1_clk: sd1-clk {
301 samsung,pins = "gpr2-0";
302 samsung,pin-function = <2>;
303 samsung,pin-pud = <0>;
304 samsung,pin-drv = <3>;
305 };
306
307 sd1_cmd: sd1-cmd {
308 samsung,pins = "gpr2-1";
309 samsung,pin-function = <2>;
310 samsung,pin-pud = <0>;
311 samsung,pin-drv = <3>;
312 };
313
314 sd1_bus1: sd1-bus-width1 {
315 samsung,pins = "gpr3-0";
316 samsung,pin-function = <2>;
317 samsung,pin-pud = <3>;
318 samsung,pin-drv = <3>;
319 };
320
321 sd1_bus4: sd1-bus-width4 {
322 samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
323 samsung,pin-function = <2>;
324 samsung,pin-pud = <3>;
325 samsung,pin-drv = <3>;
326 };
327
328 sd1_bus8: sd1-bus-width8 {
329 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
330 samsung,pin-function = <2>;
331 samsung,pin-pud = <3>;
332 samsung,pin-drv = <3>;
333 };
334
335 pcie_bus: pcie_bus {
336 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
337 samsung,pin-function = <3>;
338 samsung,pin-pud = <3>;
339 };
340
341 sd2_clk: sd2-clk {
342 samsung,pins = "gpr4-0";
343 samsung,pin-function = <2>;
344 samsung,pin-pud = <0>;
345 samsung,pin-drv = <3>;
346 };
347
348 sd2_cmd: sd2-cmd {
349 samsung,pins = "gpr4-1";
350 samsung,pin-function = <2>;
351 samsung,pin-pud = <0>;
352 samsung,pin-drv = <3>;
353 };
354
355 sd2_cd: sd2-cd {
356 samsung,pins = "gpr4-2";
357 samsung,pin-function = <2>;
358 samsung,pin-pud = <3>;
359 samsung,pin-drv = <3>;
360 };
361
362 sd2_bus1: sd2-bus-width1 {
363 samsung,pins = "gpr4-3";
364 samsung,pin-function = <2>;
365 samsung,pin-pud = <3>;
366 samsung,pin-drv = <3>;
367 };
368
369 sd2_bus4: sd2-bus-width4 {
370 samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
371 samsung,pin-function = <2>;
372 samsung,pin-pud = <3>;
373 samsung,pin-drv = <3>;
374 };
375
376 sd2_clk_output: sd2-clk-output {
377 samsung,pins = "gpr4-0";
378 samsung,pin-function = <1>;
379 samsung,pin-pud = <0>;
380 samsung,pin-drv = <2>;
381 };
382
383 sd2_cmd_output: sd2-cmd-output {
384 samsung,pins = "gpr4-1";
385 samsung,pin-function = <1>;
386 samsung,pin-pud = <0>;
387 samsung,pin-drv = <2>;
388 };
389};
390
391&pinctrl_imem {
392 gpf0: gpf0 {
393 gpio-controller;
394 #gpio-cells = <2>;
395
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 };
399};
400
401&pinctrl_nfc {
402 gpj0: gpj0 {
403 gpio-controller;
404 #gpio-cells = <2>;
405
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 };
409
410 hs_i2c4_bus: hs-i2c4-bus {
411 samsung,pins = "gpj0-1", "gpj0-0";
412 samsung,pin-function = <4>;
413 samsung,pin-pud = <3>;
414 samsung,pin-drv = <0>;
415 };
416};
417
418&pinctrl_peric {
419 gpv7: gpv7 {
420 gpio-controller;
421 #gpio-cells = <2>;
422
423 interrupt-controller;
424 #interrupt-cells = <2>;
425 };
426
427 gpb0: gpb0 {
428 gpio-controller;
429 #gpio-cells = <2>;
430
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 };
434
435 gpc0: gpc0 {
436 gpio-controller;
437 #gpio-cells = <2>;
438
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 };
442
443 gpc1: gpc1 {
444 gpio-controller;
445 #gpio-cells = <2>;
446
447 interrupt-controller;
448 #interrupt-cells = <2>;
449 };
450
451 gpc2: gpc2 {
452 gpio-controller;
453 #gpio-cells = <2>;
454
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 };
458
459 gpc3: gpc3 {
460 gpio-controller;
461 #gpio-cells = <2>;
462
463 interrupt-controller;
464 #interrupt-cells = <2>;
465 };
466
467 gpg0: gpg0 {
468 gpio-controller;
469 #gpio-cells = <2>;
470
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 };
474
475 gpd0: gpd0 {
476 gpio-controller;
477 #gpio-cells = <2>;
478
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 };
482
483 gpd1: gpd1 {
484 gpio-controller;
485 #gpio-cells = <2>;
486
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 };
490
491 gpd2: gpd2 {
492 gpio-controller;
493 #gpio-cells = <2>;
494
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 };
498
499 gpd4: gpd4 {
500 gpio-controller;
501 #gpio-cells = <2>;
502
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 };
506
507 gpd8: gpd8 {
508 gpio-controller;
509 #gpio-cells = <2>;
510
511 interrupt-controller;
512 #interrupt-cells = <2>;
513 };
514
515 gpd6: gpd6 {
516 gpio-controller;
517 #gpio-cells = <2>;
518
519 interrupt-controller;
520 #interrupt-cells = <2>;
521 };
522
523 gpd7: gpd7 {
524 gpio-controller;
525 #gpio-cells = <2>;
526
527 interrupt-controller;
528 #interrupt-cells = <2>;
529 };
530
531 gpg1: gpg1 {
532 gpio-controller;
533 #gpio-cells = <2>;
534
535 interrupt-controller;
536 #interrupt-cells = <2>;
537 };
538
539 gpg2: gpg2 {
540 gpio-controller;
541 #gpio-cells = <2>;
542
543 interrupt-controller;
544 #interrupt-cells = <2>;
545 };
546
547 gpg3: gpg3 {
548 gpio-controller;
549 #gpio-cells = <2>;
550
551 interrupt-controller;
552 #interrupt-cells = <2>;
553 };
554
555 hs_i2c8_bus: hs-i2c8-bus {
556 samsung,pins = "gpb0-1", "gpb0-0";
557 samsung,pin-function = <4>;
558 samsung,pin-pud = <3>;
559 samsung,pin-drv = <0>;
560 };
561
562 hs_i2c9_bus: hs-i2c9-bus {
563 samsung,pins = "gpb0-3", "gpb0-2";
564 samsung,pin-function = <4>;
565 samsung,pin-pud = <3>;
566 samsung,pin-drv = <0>;
567 };
568
569 i2s1_bus: i2s1-bus {
570 samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
571 "gpd4-3", "gpd4-4";
572 samsung,pin-function = <2>;
573 samsung,pin-pud = <1>;
574 samsung,pin-drv = <0>;
575 };
576
577 pcm1_bus: pcm1-bus {
578 samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
579 "gpd4-3", "gpd4-4";
580 samsung,pin-function = <3>;
581 samsung,pin-pud = <1>;
582 samsung,pin-drv = <0>;
583 };
584
585 spdif_bus: spdif-bus {
586 samsung,pins = "gpd4-3", "gpd4-4";
587 samsung,pin-function = <4>;
588 samsung,pin-pud = <1>;
589 samsung,pin-drv = <0>;
590 };
591
592 fimc_is_spi_pin0: fimc-is-spi-pin0 {
593 samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0";
594 samsung,pin-function = <2>;
595 samsung,pin-pud = <0>;
596 samsung,pin-drv = <0>;
597 };
598
599 fimc_is_spi_pin1: fimc-is-spi-pin1 {
600 samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4";
601 samsung,pin-function = <2>;
602 samsung,pin-pud = <0>;
603 samsung,pin-drv = <0>;
604 };
605
606 uart0_bus: uart0-bus {
607 samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0";
608 samsung,pin-function = <2>;
609 samsung,pin-pud = <0>;
610 };
611
612 hs_i2c2_bus: hs-i2c2-bus {
613 samsung,pins = "gpd0-3", "gpd0-2";
614 samsung,pin-function = <3>;
615 samsung,pin-pud = <3>;
616 samsung,pin-drv = <0>;
617 };
618
619 uart2_bus: uart2-bus {
620 samsung,pins = "gpd1-5", "gpd1-4";
621 samsung,pin-function = <2>;
622 samsung,pin-pud = <0>;
623 };
624
625 uart1_bus: uart1-bus {
626 samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
627 samsung,pin-function = <2>;
628 samsung,pin-pud = <0>;
629 };
630
631 hs_i2c3_bus: hs-i2c3-bus {
632 samsung,pins = "gpd1-3", "gpd1-2";
633 samsung,pin-function = <3>;
634 samsung,pin-pud = <3>;
635 samsung,pin-drv = <0>;
636 };
637
638 hs_i2c0_bus: hs-i2c0-bus {
639 samsung,pins = "gpd2-1", "gpd2-0";
640 samsung,pin-function = <2>;
641 samsung,pin-pud = <3>;
642 samsung,pin-drv = <0>;
643 };
644
645 hs_i2c1_bus: hs-i2c1-bus {
646 samsung,pins = "gpd2-3", "gpd2-2";
647 samsung,pin-function = <2>;
648 samsung,pin-pud = <3>;
649 samsung,pin-drv = <0>;
650 };
651
652 pwm0_out: pwm0-out {
653 samsung,pins = "gpd2-4";
654 samsung,pin-function = <2>;
655 samsung,pin-pud = <0>;
656 samsung,pin-drv = <0>;
657 };
658
659 pwm1_out: pwm1-out {
660 samsung,pins = "gpd2-5";
661 samsung,pin-function = <2>;
662 samsung,pin-pud = <0>;
663 samsung,pin-drv = <0>;
664 };
665
666 pwm2_out: pwm2-out {
667 samsung,pins = "gpd2-6";
668 samsung,pin-function = <2>;
669 samsung,pin-pud = <0>;
670 samsung,pin-drv = <0>;
671 };
672
673 pwm3_out: pwm3-out {
674 samsung,pins = "gpd2-7";
675 samsung,pin-function = <2>;
676 samsung,pin-pud = <0>;
677 samsung,pin-drv = <0>;
678 };
679
680 spi1_bus: spi1-bus {
681 samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5";
682 samsung,pin-function = <2>;
683 samsung,pin-pud = <3>;
684 samsung,pin-drv = <0>;
685 };
686
687 hs_i2c7_bus: hs-i2c7-bus {
688 samsung,pins = "gpd2-7", "gpd2-6";
689 samsung,pin-function = <4>;
690 samsung,pin-pud = <3>;
691 samsung,pin-drv = <0>;
692 };
693
694 spi0_bus: spi0-bus {
695 samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1";
696 samsung,pin-function = <2>;
697 samsung,pin-pud = <3>;
698 samsung,pin-drv = <0>;
699 };
700
701 hs_i2c10_bus: hs-i2c10-bus {
702 samsung,pins = "gpg3-1", "gpg3-0";
703 samsung,pin-function = <4>;
704 samsung,pin-pud = <3>;
705 samsung,pin-drv = <0>;
706 };
707
708 hs_i2c11_bus: hs-i2c11-bus {
709 samsung,pins = "gpg3-3", "gpg3-2";
710 samsung,pin-function = <4>;
711 samsung,pin-pud = <3>;
712 samsung,pin-drv = <0>;
713 };
714
715 spi3_bus: spi3-bus {
716 samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7";
717 samsung,pin-function = <3>;
718 samsung,pin-pud = <3>;
719 samsung,pin-drv = <0>;
720 };
721
722 spi4_bus: spi4-bus {
723 samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4";
724 samsung,pin-function = <3>;
725 samsung,pin-pud = <3>;
726 samsung,pin-drv = <0>;
727 };
728
729 fimc_is_uart: fimc-is-uart {
730 samsung,pins = "gpc1-1", "gpc0-7";
731 samsung,pin-function = <3>;
732 samsung,pin-pud = <0>;
733 samsung,pin-drv = <0>;
734 };
735
736 fimc_is_ch0_i2c: fimc-is-ch0_i2c {
737 samsung,pins = "gpc2-1", "gpc2-0";
738 samsung,pin-function = <2>;
739 samsung,pin-pud = <0>;
740 samsung,pin-drv = <0>;
741 };
742
743 fimc_is_ch0_mclk: fimc-is-ch0_mclk {
744 samsung,pins = "gpd7-0";
745 samsung,pin-function = <2>;
746 samsung,pin-pud = <0>;
747 samsung,pin-drv = <0>;
748 };
749
750 fimc_is_ch1_i2c: fimc-is-ch1-i2c {
751 samsung,pins = "gpc2-3", "gpc2-2";
752 samsung,pin-function = <2>;
753 samsung,pin-pud = <0>;
754 samsung,pin-drv = <0>;
755 };
756
757 fimc_is_ch1_mclk: fimc-is-ch1-mclk {
758 samsung,pins = "gpd7-1";
759 samsung,pin-function = <2>;
760 samsung,pin-pud = <0>;
761 samsung,pin-drv = <0>;
762 };
763
764 fimc_is_ch2_i2c: fimc-is-ch2-i2c {
765 samsung,pins = "gpc2-5", "gpc2-4";
766 samsung,pin-function = <2>;
767 samsung,pin-pud = <0>;
768 samsung,pin-drv = <0>;
769 };
770
771 fimc_is_ch2_mclk: fimc-is-ch2-mclk {
772 samsung,pins = "gpd7-2";
773 samsung,pin-function = <2>;
774 samsung,pin-pud = <0>;
775 samsung,pin-drv = <0>;
776 };
777};
778
779&pinctrl_touch {
780 gpj1: gpj1 {
781 gpio-controller;
782 #gpio-cells = <2>;
783
784 interrupt-controller;
785 #interrupt-cells = <2>;
786 };
787
788 hs_i2c5_bus: hs-i2c5-bus {
789 samsung,pins = "gpj1-1", "gpj1-0";
790 samsung,pin-function = <4>;
791 samsung,pin-pud = <3>;
792 samsung,pin-drv = <0>;
793 };
794};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
new file mode 100644
index 000000000000..9ea3f32bae9e
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -0,0 +1,974 @@
1/*
2 * SAMSUNG Exynos5433 TM2 board device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 *
6 * Device tree source file for Samsung's TM2 board which is based on
7 * Samsung Exynos5433 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/dts-v1/;
15#include "exynos5433.dtsi"
16#include <dt-bindings/clock/samsung,s2mps11.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/input/input.h>
19#include <dt-bindings/interrupt-controller/irq.h>
20
21/ {
22 model = "Samsung TM2 board";
23 compatible = "samsung,tm2", "samsung,exynos5433";
24
25 aliases {
26 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0;
37 serial1 = &serial_1;
38 serial2 = &serial_2;
39 serial3 = &serial_3;
40 spi0 = &spi_0;
41 spi1 = &spi_1;
42 spi2 = &spi_2;
43 spi3 = &spi_3;
44 spi4 = &spi_4;
45 };
46
47 chosen {
48 stdout-path = &serial_1;
49 };
50
51 memory@20000000 {
52 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0000000>;
54 };
55
56 gpio-keys {
57 compatible = "gpio-keys";
58
59 power-key {
60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_POWER>;
62 label = "power key";
63 debounce-interval = <10>;
64 };
65
66 volume-up-key {
67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_VOLUMEUP>;
69 label = "volume-up key";
70 debounce-interval = <10>;
71 };
72
73 volume-down-key {
74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLUMEDOWN>;
76 label = "volume-down key";
77 debounce-interval = <10>;
78 };
79
80 homepage-key {
81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_MENU>;
83 label = "homepage key";
84 debounce-interval = <10>;
85 };
86 };
87
88 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio";
90 gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
91 &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
92 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>;
94 #size-cells = <0>;
95 status = "okay";
96
97 max98504: max98504@31 {
98 compatible = "maxim,max98504";
99 reg = <0x31>;
100 maxim,rx-path = <1>;
101 maxim,tx-path = <1>;
102 maxim,tx-channel-mask = <3>;
103 maxim,tx-channel-source = <2>;
104 };
105 };
106
107 sound {
108 compatible = "samsung,tm2-audio";
109 audio-codec = <&wm5110>;
110 i2s-controller = <&i2s0>;
111 audio-amplifier = <&max98504>;
112 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
113 model = "wm5110";
114 samsung,audio-routing =
115 /* Headphone */
116 "HP", "HPOUT1L",
117 "HP", "HPOUT1R",
118
119 /* Speaker */
120 "SPK", "SPKOUT",
121 "SPKOUT", "HPOUT2L",
122 "SPKOUT", "HPOUT2R",
123
124 /* Receiver */
125 "RCV", "HPOUT3L",
126 "RCV", "HPOUT3R";
127 status = "okay";
128 };
129};
130
131&adc {
132 vdd-supply = <&ldo3_reg>;
133 status = "okay";
134
135 thermistor-ap {
136 compatible = "murata,ncp03wf104";
137 pullup-uv = <1800000>;
138 pullup-ohm = <100000>;
139 pulldown-ohm = <0>;
140 io-channels = <&adc 0>;
141 };
142
143 thermistor-battery {
144 compatible = "murata,ncp03wf104";
145 pullup-uv = <1800000>;
146 pullup-ohm = <100000>;
147 pulldown-ohm = <0>;
148 io-channels = <&adc 1>;
149 #thermal-sensor-cells = <0>;
150 };
151
152 thermistor-charger {
153 compatible = "murata,ncp03wf104";
154 pullup-uv = <1800000>;
155 pullup-ohm = <100000>;
156 pulldown-ohm = <0>;
157 io-channels = <&adc 2>;
158 };
159};
160
161&cpu0 {
162 cpu-supply = <&buck3_reg>;
163};
164
165&cpu4 {
166 cpu-supply = <&buck2_reg>;
167};
168
169&decon {
170 status = "okay";
171
172 i80-if-timings {
173 };
174};
175
176&dsi {
177 status = "okay";
178 vddcore-supply = <&ldo6_reg>;
179 vddio-supply = <&ldo7_reg>;
180 samsung,pll-clock-frequency = <24000000>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&te_irq>;
183
184 ports {
185 #address-cells = <1>;
186 #size-cells = <0>;
187
188 port@1 {
189 reg = <1>;
190
191 dsi_out: endpoint {
192 samsung,burst-clock-frequency = <512000000>;
193 samsung,esc-clock-frequency = <16000000>;
194 };
195 };
196 };
197};
198
199&hsi2c_0 {
200 status = "okay";
201 clock-frequency = <2500000>;
202
203 s2mps13-pmic@66 {
204 compatible = "samsung,s2mps13-pmic";
205 interrupt-parent = <&gpa0>;
206 interrupts = <7 IRQ_TYPE_NONE>;
207 reg = <0x66>;
208 samsung,s2mps11-wrstbi-ground;
209
210 s2mps13_osc: clocks {
211 compatible = "samsung,s2mps13-clk";
212 #clock-cells = <1>;
213 clock-output-names = "s2mps13_ap", "s2mps13_cp",
214 "s2mps13_bt";
215 };
216
217 regulators {
218 ldo1_reg: LDO1 {
219 regulator-name = "VDD_ALIVE_0.9V_AP";
220 regulator-min-microvolt = <900000>;
221 regulator-max-microvolt = <900000>;
222 regulator-always-on;
223 };
224
225 ldo2_reg: LDO2 {
226 regulator-name = "VDDQ_MMC2_2.8V_AP";
227 regulator-min-microvolt = <2800000>;
228 regulator-max-microvolt = <2800000>;
229 regulator-always-on;
230 regulator-state-mem {
231 regulator-off-in-suspend;
232 };
233 };
234
235 ldo3_reg: LDO3 {
236 regulator-name = "VDD1_E_1.8V_AP";
237 regulator-min-microvolt = <1800000>;
238 regulator-max-microvolt = <1800000>;
239 regulator-always-on;
240 };
241
242 ldo4_reg: LDO4 {
243 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
244 regulator-min-microvolt = <1300000>;
245 regulator-max-microvolt = <1300000>;
246 regulator-always-on;
247 regulator-state-mem {
248 regulator-off-in-suspend;
249 };
250 };
251
252 ldo5_reg: LDO5 {
253 regulator-name = "VDD10_DPLL_1.0V_AP";
254 regulator-min-microvolt = <1000000>;
255 regulator-max-microvolt = <1000000>;
256 regulator-always-on;
257 regulator-state-mem {
258 regulator-off-in-suspend;
259 };
260 };
261
262 ldo6_reg: LDO6 {
263 regulator-name = "VDD10_MIPI2L_1.0V_AP";
264 regulator-min-microvolt = <1000000>;
265 regulator-max-microvolt = <1000000>;
266 regulator-state-mem {
267 regulator-off-in-suspend;
268 };
269 };
270
271 ldo7_reg: LDO7 {
272 regulator-name = "VDD18_MIPI2L_1.8V_AP";
273 regulator-min-microvolt = <1800000>;
274 regulator-max-microvolt = <1800000>;
275 };
276
277 ldo8_reg: LDO8 {
278 regulator-name = "VDD18_LLI_1.8V_AP";
279 regulator-min-microvolt = <1800000>;
280 regulator-max-microvolt = <1800000>;
281 regulator-always-on;
282 regulator-state-mem {
283 regulator-off-in-suspend;
284 };
285 };
286
287 ldo9_reg: LDO9 {
288 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
289 regulator-min-microvolt = <1800000>;
290 regulator-max-microvolt = <1800000>;
291 regulator-always-on;
292 regulator-state-mem {
293 regulator-off-in-suspend;
294 };
295 };
296
297 ldo10_reg: LDO10 {
298 regulator-name = "VDD33_USB30_3.0V_AP";
299 regulator-min-microvolt = <3000000>;
300 regulator-max-microvolt = <3000000>;
301 regulator-state-mem {
302 regulator-off-in-suspend;
303 };
304 };
305
306 ldo11_reg: LDO11 {
307 regulator-name = "VDD_INT_M_1.0V_AP";
308 regulator-min-microvolt = <1000000>;
309 regulator-max-microvolt = <1000000>;
310 regulator-always-on;
311 regulator-state-mem {
312 regulator-off-in-suspend;
313 };
314 };
315
316 ldo12_reg: LDO12 {
317 regulator-name = "VDD_KFC_M_1.1V_AP";
318 regulator-min-microvolt = <800000>;
319 regulator-max-microvolt = <1350000>;
320 regulator-always-on;
321 };
322
323 ldo13_reg: LDO13 {
324 regulator-name = "VDD_G3D_M_0.95V_AP";
325 regulator-min-microvolt = <950000>;
326 regulator-max-microvolt = <950000>;
327 regulator-always-on;
328 regulator-state-mem {
329 regulator-off-in-suspend;
330 };
331 };
332
333 ldo14_reg: LDO14 {
334 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
335 regulator-min-microvolt = <1200000>;
336 regulator-max-microvolt = <1200000>;
337 regulator-always-on;
338 regulator-state-mem {
339 regulator-off-in-suspend;
340 };
341 };
342
343 ldo15_reg: LDO15 {
344 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
345 regulator-min-microvolt = <1200000>;
346 regulator-max-microvolt = <1200000>;
347 regulator-always-on;
348 regulator-state-mem {
349 regulator-off-in-suspend;
350 };
351 };
352
353 ldo16_reg: LDO16 {
354 regulator-name = "VDDQ_EFUSE";
355 regulator-min-microvolt = <1400000>;
356 regulator-max-microvolt = <3400000>;
357 regulator-always-on;
358 };
359
360 ldo17_reg: LDO17 {
361 regulator-name = "V_TFLASH_2.8V_AP";
362 regulator-min-microvolt = <2800000>;
363 regulator-max-microvolt = <2800000>;
364 };
365
366 ldo18_reg: LDO18 {
367 regulator-name = "V_CODEC_1.8V_AP";
368 regulator-min-microvolt = <1800000>;
369 regulator-max-microvolt = <1800000>;
370 };
371
372 ldo19_reg: LDO19 {
373 regulator-name = "VDDA_1.8V_COMP";
374 regulator-min-microvolt = <1800000>;
375 regulator-max-microvolt = <1800000>;
376 regulator-always-on;
377 };
378
379 ldo20_reg: LDO20 {
380 regulator-name = "VCC_2.8V_AP";
381 regulator-min-microvolt = <2800000>;
382 regulator-max-microvolt = <2800000>;
383 regulator-always-on;
384 };
385
386 ldo21_reg: LDO21 {
387 regulator-name = "VT_CAM_1.8V";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 };
391
392 ldo22_reg: LDO22 {
393 regulator-name = "CAM_IO_1.8V_AP";
394 regulator-min-microvolt = <1800000>;
395 regulator-max-microvolt = <1800000>;
396 };
397
398 ldo23_reg: LDO23 {
399 regulator-name = "CAM_SEN_CORE_1.2V_AP";
400 regulator-min-microvolt = <1050000>;
401 regulator-max-microvolt = <1200000>;
402 };
403
404 ldo24_reg: LDO24 {
405 regulator-name = "VT_CAM_1.2V";
406 regulator-min-microvolt = <1200000>;
407 regulator-max-microvolt = <1200000>;
408 };
409
410 ldo25_reg: LDO25 {
411 regulator-name = "CAM_SEN_A2.8V_AP";
412 regulator-min-microvolt = <2800000>;
413 regulator-max-microvolt = <2800000>;
414 };
415
416 ldo26_reg: LDO26 {
417 regulator-name = "CAM_AF_2.8V_AP";
418 regulator-min-microvolt = <2800000>;
419 regulator-max-microvolt = <2800000>;
420 };
421
422 ldo27_reg: LDO27 {
423 regulator-name = "VCC_3.0V_LCD_AP";
424 regulator-min-microvolt = <3000000>;
425 regulator-max-microvolt = <3000000>;
426 };
427
428 ldo28_reg: LDO28 {
429 regulator-name = "VCC_1.8V_LCD_AP";
430 regulator-min-microvolt = <1800000>;
431 regulator-max-microvolt = <1800000>;
432 };
433
434 ldo29_reg: LDO29 {
435 regulator-name = "VT_CAM_2.8V";
436 regulator-min-microvolt = <3000000>;
437 regulator-max-microvolt = <3000000>;
438 };
439
440 ldo30_reg: LDO30 {
441 regulator-name = "TSP_AVDD_3.3V_AP";
442 regulator-min-microvolt = <3300000>;
443 regulator-max-microvolt = <3300000>;
444 };
445
446 ldo31_reg: LDO31 {
447 regulator-name = "TSP_VDD_1.85V_AP";
448 regulator-min-microvolt = <1850000>;
449 regulator-max-microvolt = <1850000>;
450 };
451
452 ldo32_reg: LDO32 {
453 regulator-name = "VTOUCH_1.8V_AP";
454 regulator-min-microvolt = <1800000>;
455 regulator-max-microvolt = <1800000>;
456 };
457
458 ldo33_reg: LDO33 {
459 regulator-name = "VTOUCH_LED_3.3V";
460 regulator-min-microvolt = <2500000>;
461 regulator-max-microvolt = <3300000>;
462 regulator-ramp-delay = <12500>;
463 };
464
465 ldo34_reg: LDO34 {
466 regulator-name = "VCC_1.8V_MHL_AP";
467 regulator-min-microvolt = <1000000>;
468 regulator-max-microvolt = <2100000>;
469 };
470
471 ldo35_reg: LDO35 {
472 regulator-name = "OIS_VM_2.8V";
473 regulator-min-microvolt = <1800000>;
474 regulator-max-microvolt = <2800000>;
475 };
476
477 ldo36_reg: LDO36 {
478 regulator-name = "VSIL_1.0V";
479 regulator-min-microvolt = <1000000>;
480 regulator-max-microvolt = <1000000>;
481 };
482
483 ldo37_reg: LDO37 {
484 regulator-name = "VF_1.8V";
485 regulator-min-microvolt = <1800000>;
486 regulator-max-microvolt = <1800000>;
487 };
488
489 ldo38_reg: LDO38 {
490 regulator-name = "VCC_3.0V_MOTOR_AP";
491 regulator-min-microvolt = <3000000>;
492 regulator-max-microvolt = <3000000>;
493 };
494
495 ldo39_reg: LDO39 {
496 regulator-name = "V_HRM_1.8V";
497 regulator-min-microvolt = <1800000>;
498 regulator-max-microvolt = <1800000>;
499 };
500
501 ldo40_reg: LDO40 {
502 regulator-name = "V_HRM_3.3V";
503 regulator-min-microvolt = <3300000>;
504 regulator-max-microvolt = <3300000>;
505 };
506
507 buck1_reg: BUCK1 {
508 regulator-name = "VDD_MIF_0.9V_AP";
509 regulator-min-microvolt = <600000>;
510 regulator-max-microvolt = <1500000>;
511 regulator-always-on;
512 regulator-state-mem {
513 regulator-off-in-suspend;
514 };
515 };
516
517 buck2_reg: BUCK2 {
518 regulator-name = "VDD_EGL_1.0V_AP";
519 regulator-min-microvolt = <900000>;
520 regulator-max-microvolt = <1300000>;
521 regulator-always-on;
522 regulator-state-mem {
523 regulator-off-in-suspend;
524 };
525 };
526
527 buck3_reg: BUCK3 {
528 regulator-name = "VDD_KFC_1.0V_AP";
529 regulator-min-microvolt = <800000>;
530 regulator-max-microvolt = <1200000>;
531 regulator-always-on;
532 regulator-state-mem {
533 regulator-off-in-suspend;
534 };
535 };
536
537 buck4_reg: BUCK4 {
538 regulator-name = "VDD_INT_0.95V_AP";
539 regulator-min-microvolt = <600000>;
540 regulator-max-microvolt = <1500000>;
541 regulator-always-on;
542 regulator-state-mem {
543 regulator-off-in-suspend;
544 };
545 };
546
547 buck5_reg: BUCK5 {
548 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
549 regulator-min-microvolt = <600000>;
550 regulator-max-microvolt = <1500000>;
551 regulator-always-on;
552 regulator-state-mem {
553 regulator-off-in-suspend;
554 };
555 };
556
557 buck6_reg: BUCK6 {
558 regulator-name = "VDD_G3D_0.9V_AP";
559 regulator-min-microvolt = <600000>;
560 regulator-max-microvolt = <1500000>;
561 regulator-always-on;
562 regulator-state-mem {
563 regulator-off-in-suspend;
564 };
565 };
566
567 buck7_reg: BUCK7 {
568 regulator-name = "VDD_MEM1_1.2V_AP";
569 regulator-min-microvolt = <1200000>;
570 regulator-max-microvolt = <1200000>;
571 regulator-always-on;
572 };
573
574 buck8_reg: BUCK8 {
575 regulator-name = "VDD_LLDO_1.35V_AP";
576 regulator-min-microvolt = <1350000>;
577 regulator-max-microvolt = <3300000>;
578 regulator-always-on;
579 };
580
581 buck9_reg: BUCK9 {
582 regulator-name = "VDD_MLDO_2.0V_AP";
583 regulator-min-microvolt = <1350000>;
584 regulator-max-microvolt = <3300000>;
585 regulator-always-on;
586 };
587
588 buck10_reg: BUCK10 {
589 regulator-name = "vdd_mem2";
590 regulator-min-microvolt = <550000>;
591 regulator-max-microvolt = <1500000>;
592 regulator-always-on;
593 };
594 };
595 };
596};
597
598&hsi2c_8 {
599 status = "okay";
600
601 max77843@66 {
602 compatible = "maxim,max77843";
603 interrupt-parent = <&gpa1>;
604 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
605 reg = <0x66>;
606
607 muic: max77843-muic {
608 compatible = "maxim,max77843-muic";
609 };
610
611 regulators {
612 compatible = "maxim,max77843-regulator";
613 safeout1_reg: SAFEOUT1 {
614 regulator-name = "SAFEOUT1";
615 regulator-min-microvolt = <3300000>;
616 regulator-max-microvolt = <4950000>;
617 };
618
619 safeout2_reg: SAFEOUT2 {
620 regulator-name = "SAFEOUT2";
621 regulator-min-microvolt = <3300000>;
622 regulator-max-microvolt = <4950000>;
623 };
624
625 charger_reg: CHARGER {
626 regulator-name = "CHARGER";
627 regulator-min-microamp = <100000>;
628 regulator-max-microamp = <3150000>;
629 };
630 };
631
632 haptic: max77843-haptic {
633 compatible = "maxim,max77843-haptic";
634 haptic-supply = <&ldo38_reg>;
635 pwms = <&pwm 0 33670 0>;
636 pwm-names = "haptic";
637 };
638 };
639};
640
641&i2s0 {
642 status = "okay";
643};
644
645&mshc_0 {
646 status = "okay";
647 num-slots = <1>;
648 non-removable;
649 card-detect-delay = <200>;
650 samsung,dw-mshc-ciu-div = <3>;
651 samsung,dw-mshc-sdr-timing = <0 4>;
652 samsung,dw-mshc-ddr-timing = <0 2>;
653 samsung,dw-mshc-hs400-timing = <0 3>;
654 samsung,read-strobe-delay = <90>;
655 fifo-depth = <0x80>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
658 &sd0_bus8 &sd0_rdqs>;
659 bus-width = <8>;
660 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
661 assigned-clock-rates = <800000000>;
662};
663
664&pinctrl_alive {
665 pinctrl-names = "default";
666 pinctrl-0 = <&initial_alive>;
667
668 initial_alive: initial-state {
669 PIN(IN, gpa0-0, DOWN, LV1);
670 PIN(IN, gpa0-1, NONE, LV1);
671 PIN(IN, gpa0-2, DOWN, LV1);
672 PIN(IN, gpa0-3, NONE, LV1);
673 PIN(IN, gpa0-4, NONE, LV1);
674 PIN(IN, gpa0-5, DOWN, LV1);
675 PIN(IN, gpa0-6, NONE, LV1);
676 PIN(IN, gpa0-7, NONE, LV1);
677
678 PIN(IN, gpa1-0, UP, LV1);
679 PIN(IN, gpa1-1, NONE, LV1);
680 PIN(IN, gpa1-2, NONE, LV1);
681 PIN(IN, gpa1-3, DOWN, LV1);
682 PIN(IN, gpa1-4, DOWN, LV1);
683 PIN(IN, gpa1-5, NONE, LV1);
684 PIN(IN, gpa1-6, NONE, LV1);
685 PIN(IN, gpa1-7, NONE, LV1);
686
687 PIN(IN, gpa2-0, NONE, LV1);
688 PIN(IN, gpa2-1, NONE, LV1);
689 PIN(IN, gpa2-2, NONE, LV1);
690 PIN(IN, gpa2-3, DOWN, LV1);
691 PIN(IN, gpa2-4, NONE, LV1);
692 PIN(IN, gpa2-5, DOWN, LV1);
693 PIN(IN, gpa2-6, DOWN, LV1);
694 PIN(IN, gpa2-7, NONE, LV1);
695
696 PIN(IN, gpa3-0, DOWN, LV1);
697 PIN(IN, gpa3-1, DOWN, LV1);
698 PIN(IN, gpa3-2, NONE, LV1);
699 PIN(IN, gpa3-3, DOWN, LV1);
700 PIN(IN, gpa3-4, NONE, LV1);
701 PIN(IN, gpa3-5, DOWN, LV1);
702 PIN(IN, gpa3-6, DOWN, LV1);
703 PIN(IN, gpa3-7, DOWN, LV1);
704
705 PIN(IN, gpf1-0, NONE, LV1);
706 PIN(IN, gpf1-1, NONE, LV1);
707 PIN(IN, gpf1-2, DOWN, LV1);
708 PIN(IN, gpf1-4, UP, LV1);
709 PIN(OUT, gpf1-5, NONE, LV1);
710 PIN(IN, gpf1-6, DOWN, LV1);
711 PIN(IN, gpf1-7, DOWN, LV1);
712
713 PIN(IN, gpf2-0, DOWN, LV1);
714 PIN(IN, gpf2-1, DOWN, LV1);
715 PIN(IN, gpf2-2, DOWN, LV1);
716 PIN(IN, gpf2-3, DOWN, LV1);
717
718 PIN(IN, gpf3-0, DOWN, LV1);
719 PIN(IN, gpf3-1, DOWN, LV1);
720 PIN(IN, gpf3-2, NONE, LV1);
721 PIN(IN, gpf3-3, DOWN, LV1);
722
723 PIN(IN, gpf4-0, DOWN, LV1);
724 PIN(IN, gpf4-1, DOWN, LV1);
725 PIN(IN, gpf4-2, DOWN, LV1);
726 PIN(IN, gpf4-3, DOWN, LV1);
727 PIN(IN, gpf4-4, DOWN, LV1);
728 PIN(IN, gpf4-5, DOWN, LV1);
729 PIN(IN, gpf4-6, DOWN, LV1);
730 PIN(IN, gpf4-7, DOWN, LV1);
731
732 PIN(IN, gpf5-0, DOWN, LV1);
733 PIN(IN, gpf5-1, DOWN, LV1);
734 PIN(IN, gpf5-2, DOWN, LV1);
735 PIN(IN, gpf5-3, DOWN, LV1);
736 PIN(OUT, gpf5-4, NONE, LV1);
737 PIN(IN, gpf5-5, DOWN, LV1);
738 PIN(IN, gpf5-6, DOWN, LV1);
739 PIN(IN, gpf5-7, DOWN, LV1);
740 };
741
742 te_irq: te_irq {
743 samsung,pins = "gpf1-3";
744 samsung,pin-function = <0xf>;
745 };
746};
747
748&pinctrl_cpif {
749 pinctrl-names = "default";
750 pinctrl-0 = <&initial_cpif>;
751
752 initial_cpif: initial-state {
753 PIN(IN, gpv6-0, DOWN, LV1);
754 PIN(IN, gpv6-1, DOWN, LV1);
755 };
756};
757
758&pinctrl_ese {
759 pinctrl-names = "default";
760 pinctrl-0 = <&initial_ese>;
761
762 initial_ese: initial-state {
763 PIN(IN, gpj2-0, DOWN, LV1);
764 PIN(IN, gpj2-1, DOWN, LV1);
765 PIN(IN, gpj2-2, DOWN, LV1);
766 };
767};
768
769&pinctrl_fsys {
770 pinctrl-names = "default";
771 pinctrl-0 = <&initial_fsys>;
772
773 initial_fsys: initial-state {
774 PIN(IN, gpr3-0, NONE, LV1);
775 PIN(IN, gpr3-1, DOWN, LV1);
776 PIN(IN, gpr3-2, DOWN, LV1);
777 PIN(IN, gpr3-3, DOWN, LV1);
778 PIN(IN, gpr3-7, NONE, LV1);
779 };
780};
781
782&pinctrl_imem {
783 pinctrl-names = "default";
784 pinctrl-0 = <&initial_imem>;
785
786 initial_imem: initial-state {
787 PIN(IN, gpf0-0, UP, LV1);
788 PIN(IN, gpf0-1, UP, LV1);
789 PIN(IN, gpf0-2, DOWN, LV1);
790 PIN(IN, gpf0-3, UP, LV1);
791 PIN(IN, gpf0-4, DOWN, LV1);
792 PIN(IN, gpf0-5, NONE, LV1);
793 PIN(IN, gpf0-6, DOWN, LV1);
794 PIN(IN, gpf0-7, UP, LV1);
795 };
796};
797
798&pinctrl_nfc {
799 pinctrl-names = "default";
800 pinctrl-0 = <&initial_nfc>;
801
802 initial_nfc: initial-state {
803 PIN(IN, gpj0-2, DOWN, LV1);
804 };
805};
806
807&pinctrl_peric {
808 pinctrl-names = "default";
809 pinctrl-0 = <&initial_peric>;
810
811 initial_peric: initial-state {
812 PIN(IN, gpv7-0, DOWN, LV1);
813 PIN(IN, gpv7-1, DOWN, LV1);
814 PIN(IN, gpv7-2, NONE, LV1);
815 PIN(IN, gpv7-3, DOWN, LV1);
816 PIN(IN, gpv7-4, DOWN, LV1);
817 PIN(IN, gpv7-5, DOWN, LV1);
818
819 PIN(IN, gpb0-4, DOWN, LV1);
820
821 PIN(IN, gpc0-2, DOWN, LV1);
822 PIN(IN, gpc0-5, DOWN, LV1);
823 PIN(IN, gpc0-7, DOWN, LV1);
824
825 PIN(IN, gpc1-1, DOWN, LV1);
826
827 PIN(IN, gpc3-4, NONE, LV1);
828 PIN(IN, gpc3-5, NONE, LV1);
829 PIN(IN, gpc3-6, NONE, LV1);
830 PIN(IN, gpc3-7, NONE, LV1);
831
832 PIN(OUT, gpg0-0, NONE, LV1);
833 PIN(FUNC1, gpg0-1, DOWN, LV1);
834
835 PIN(IN, gpd2-5, DOWN, LV1);
836
837 PIN(IN, gpd4-0, NONE, LV1);
838 PIN(IN, gpd4-1, DOWN, LV1);
839 PIN(IN, gpd4-2, DOWN, LV1);
840 PIN(IN, gpd4-3, DOWN, LV1);
841 PIN(IN, gpd4-4, DOWN, LV1);
842
843 PIN(IN, gpd6-3, DOWN, LV1);
844
845 PIN(IN, gpd8-1, UP, LV1);
846
847 PIN(IN, gpg1-0, DOWN, LV1);
848 PIN(IN, gpg1-1, DOWN, LV1);
849 PIN(IN, gpg1-2, DOWN, LV1);
850 PIN(IN, gpg1-3, DOWN, LV1);
851 PIN(IN, gpg1-4, DOWN, LV1);
852
853 PIN(IN, gpg2-0, DOWN, LV1);
854 PIN(IN, gpg2-1, DOWN, LV1);
855
856 PIN(IN, gpg3-0, DOWN, LV1);
857 PIN(IN, gpg3-1, DOWN, LV1);
858 PIN(IN, gpg3-5, DOWN, LV1);
859 PIN(IN, gpg3-7, DOWN, LV1);
860 };
861};
862
863&pinctrl_touch {
864 pinctrl-names = "default";
865 pinctrl-0 = <&initial_touch>;
866
867 initial_touch: initial-state {
868 PIN(IN, gpj1-2, DOWN, LV1);
869 };
870};
871
872&pwm {
873 pinctrl-0 = <&pwm0_out>;
874 pinctrl-names = "default";
875 status = "okay";
876};
877
878&mic {
879 status = "okay";
880
881 i80-if-timings {
882 };
883};
884
885&serial_1 {
886 status = "okay";
887};
888
889&serial_3 {
890 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
891 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
892 status = "okay";
893};
894
895&spi_1 {
896 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
897 status = "okay";
898
899 wm5110: wm5110-codec@0 {
900 compatible = "wlf,wm5110";
901 reg = <0x0>;
902 spi-max-frequency = <20000000>;
903 interrupt-parent = <&gpa0>;
904 interrupts = <4 IRQ_TYPE_NONE>;
905 clocks = <&pmu_system_controller 0>,
906 <&s2mps13_osc S2MPS11_CLK_BT>;
907 clock-names = "mclk1", "mclk2";
908
909 gpio-controller;
910 #gpio-cells = <2>;
911
912 wlf,micd-detect-debounce = <300>;
913 wlf,micd-bias-start-time = <0x1>;
914 wlf,micd-rate = <0x7>;
915 wlf,micd-dbtime = <0x1>;
916 wlf,micd-force-micbias;
917 wlf,micd-configs = <0x0 1 0>;
918 wlf,hpdet-channel = <1>;
919 wlf,gpsw = <0x1>;
920 wlf,inmode = <2 0 2 0>;
921
922 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
923 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
924
925 /* core supplies */
926 AVDD-supply = <&ldo18_reg>;
927 DBVDD1-supply = <&ldo18_reg>;
928 CPVDD-supply = <&ldo18_reg>;
929 DBVDD2-supply = <&ldo18_reg>;
930 DBVDD3-supply = <&ldo18_reg>;
931
932 controller-data {
933 samsung,spi-feedback-delay = <0>;
934 };
935 };
936};
937
938&timer {
939 clock-frequency = <24000000>;
940};
941
942&tmu_atlas0 {
943 vtmu-supply = <&ldo3_reg>;
944 status = "okay";
945};
946
947&tmu_apollo {
948 vtmu-supply = <&ldo3_reg>;
949 status = "okay";
950};
951
952&tmu_g3d {
953 vtmu-supply = <&ldo3_reg>;
954 status = "okay";
955};
956
957&usbdrd30 {
958 vdd33-supply = <&ldo10_reg>;
959 vdd10-supply = <&ldo6_reg>;
960 status = "okay";
961};
962
963&usbdrd_dwc3_0 {
964 dr_mode = "otg";
965};
966
967&usbdrd30_phy {
968 vbus-supply = <&safeout1_reg>;
969 status = "okay";
970};
971
972&xxti {
973 clock-frequency = <24000000>;
974};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
new file mode 100644
index 000000000000..1db4e7f363a9
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -0,0 +1,41 @@
1/*
2 * SAMSUNG Exynos5433 TM2E board device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 *
6 * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
7 * Samsung Exynos5433 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include "exynos5433-tm2.dts"
15
16/ {
17 model = "Samsung TM2E board";
18 compatible = "samsung,tm2e", "samsung,exynos5433";
19};
20
21&ldo23_reg {
22 regulator-name = "CAM_SEN_CORE_1.025V_AP";
23 regulator-max-microvolt = <1050000>;
24};
25
26&ldo25_reg {
27 regulator-name = "UNUSED_LDO25";
28 regulator-always-off;
29};
30
31&ldo31_reg {
32 regulator-name = "TSP_VDD_1.8V_AP";
33 regulator-min-microvolt = <1800000>;
34 regulator-max-microvolt = <1800000>;
35};
36
37&ldo38_reg {
38 regulator-name = "VCC_3.3V_MOTOR_AP";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
new file mode 100644
index 000000000000..9be2978f1b9a
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
@@ -0,0 +1,23 @@
1/*
2 * Device tree sources for Exynos5433 TMU sensor configuration
3 *
4 * Copyright (c) 2016 Jonghwa Lee <jonghwa3.lee@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <dt-bindings/thermal/thermal_exynos.h>
12
13#thermal-sensor-cells = <0>;
14samsung,tmu_gain = <8>;
15samsung,tmu_reference_voltage = <23>;
16samsung,tmu_noise_cancel_mode = <4>;
17samsung,tmu_efuse_value = <75>;
18samsung,tmu_min_efuse_value = <40>;
19samsung,tmu_max_efuse_value = <150>;
20samsung,tmu_first_point_trim = <25>;
21samsung,tmu_second_point_trim = <85>;
22samsung,tmu_default_temp_offset = <50>;
23samsung,tmu_mux_addr = <6>;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
new file mode 100644
index 000000000000..125fe58d77ce
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
@@ -0,0 +1,22 @@
1/*
2 * Device tree sources for Exynos5433 TMU sensor configuration
3 *
4 * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <dt-bindings/thermal/thermal_exynos.h>
12
13#thermal-sensor-cells = <0>;
14samsung,tmu_gain = <8>;
15samsung,tmu_reference_voltage = <16>;
16samsung,tmu_noise_cancel_mode = <4>;
17samsung,tmu_efuse_value = <75>;
18samsung,tmu_min_efuse_value = <40>;
19samsung,tmu_max_efuse_value = <150>;
20samsung,tmu_first_point_trim = <25>;
21samsung,tmu_second_point_trim = <85>;
22samsung,tmu_default_temp_offset = <50>;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
new file mode 100644
index 000000000000..ceaa05145b8a
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
@@ -0,0 +1,296 @@
1/*
2 * Device tree sources for Exynos5433 thermal zone
3 *
4 * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14thermal-zones {
15 atlas0_thermal: atlas0-thermal {
16 thermal-sensors = <&tmu_atlas0>;
17 polling-delay-passive = <0>;
18 polling-delay = <0>;
19 trips {
20 atlas0_alert_0: atlas0-alert-0 {
21 temperature = <65000>; /* millicelsius */
22 hysteresis = <1000>; /* millicelsius */
23 type = "active";
24 };
25 atlas0_alert_1: atlas0-alert-1 {
26 temperature = <70000>; /* millicelsius */
27 hysteresis = <1000>; /* millicelsius */
28 type = "active";
29 };
30 atlas0_alert_2: atlas0-alert-2 {
31 temperature = <75000>; /* millicelsius */
32 hysteresis = <1000>; /* millicelsius */
33 type = "active";
34 };
35 atlas0_alert_3: atlas0-alert-3 {
36 temperature = <80000>; /* millicelsius */
37 hysteresis = <1000>; /* millicelsius */
38 type = "active";
39 };
40 atlas0_alert_4: atlas0-alert-4 {
41 temperature = <85000>; /* millicelsius */
42 hysteresis = <1000>; /* millicelsius */
43 type = "active";
44 };
45 atlas0_alert_5: atlas0-alert-5 {
46 temperature = <90000>; /* millicelsius */
47 hysteresis = <1000>; /* millicelsius */
48 type = "active";
49 };
50 atlas0_alert_6: atlas0-alert-6 {
51 temperature = <95000>; /* millicelsius */
52 hysteresis = <1000>; /* millicelsius */
53 type = "active";
54 };
55 };
56
57 cooling-maps {
58 map0 {
59 /* Set maximum frequency as 1800MHz */
60 trip = <&atlas0_alert_0>;
61 cooling-device = <&cpu4 1 2>;
62 };
63 map1 {
64 /* Set maximum frequency as 1700MHz */
65 trip = <&atlas0_alert_1>;
66 cooling-device = <&cpu4 2 3>;
67 };
68 map2 {
69 /* Set maximum frequency as 1600MHz */
70 trip = <&atlas0_alert_2>;
71 cooling-device = <&cpu4 3 4>;
72 };
73 map3 {
74 /* Set maximum frequency as 1500MHz */
75 trip = <&atlas0_alert_3>;
76 cooling-device = <&cpu4 4 5>;
77 };
78 map4 {
79 /* Set maximum frequency as 1400MHz */
80 trip = <&atlas0_alert_4>;
81 cooling-device = <&cpu4 5 7>;
82 };
83 map5 {
84 /* Set maximum frequencyas 1200MHz */
85 trip = <&atlas0_alert_5>;
86 cooling-device = <&cpu4 7 9>;
87 };
88 map6 {
89 /* Set maximum frequency as 1000MHz */
90 trip = <&atlas0_alert_6>;
91 cooling-device = <&cpu4 9 14>;
92 };
93 };
94 };
95
96 atlas1_thermal: atlas1-thermal {
97 thermal-sensors = <&tmu_atlas1>;
98 polling-delay-passive = <0>;
99 polling-delay = <0>;
100 trips {
101 atlas1_alert_0: atlas1-alert-0 {
102 temperature = <65000>; /* millicelsius */
103 hysteresis = <1000>; /* millicelsius */
104 type = "active";
105 };
106 atlas1_alert_1: atlas1-alert-1 {
107 temperature = <70000>; /* millicelsius */
108 hysteresis = <1000>; /* millicelsius */
109 type = "active";
110 };
111 atlas1_alert_2: atlas1-alert-2 {
112 temperature = <75000>; /* millicelsius */
113 hysteresis = <1000>; /* millicelsius */
114 type = "active";
115 };
116 atlas1_alert_3: atlas1-alert-3 {
117 temperature = <80000>; /* millicelsius */
118 hysteresis = <1000>; /* millicelsius */
119 type = "active";
120 };
121 atlas1_alert_4: atlas1-alert-4 {
122 temperature = <85000>; /* millicelsius */
123 hysteresis = <1000>; /* millicelsius */
124 type = "active";
125 };
126 atlas1_alert_5: atlas1-alert-5 {
127 temperature = <90000>; /* millicelsius */
128 hysteresis = <1000>; /* millicelsius */
129 type = "active";
130 };
131 atlas1_alert_6: atlas1-alert-6 {
132 temperature = <95000>; /* millicelsius */
133 hysteresis = <1000>; /* millicelsius */
134 type = "active";
135 };
136 };
137 };
138
139 g3d_thermal: g3d-thermal {
140 thermal-sensors = <&tmu_g3d>;
141 polling-delay-passive = <0>;
142 polling-delay = <0>;
143 trips {
144 g3d_alert_0: g3d-alert-0 {
145 temperature = <70000>; /* millicelsius */
146 hysteresis = <1000>; /* millicelsius */
147 type = "active";
148 };
149 g3d_alert_1: g3d-alert-1 {
150 temperature = <75000>; /* millicelsius */
151 hysteresis = <1000>; /* millicelsius */
152 type = "active";
153 };
154 g3d_alert_2: g3d-alert-2 {
155 temperature = <80000>; /* millicelsius */
156 hysteresis = <1000>; /* millicelsius */
157 type = "active";
158 };
159 g3d_alert_3: g3d-alert-3 {
160 temperature = <85000>; /* millicelsius */
161 hysteresis = <1000>; /* millicelsius */
162 type = "active";
163 };
164 g3d_alert_4: g3d-alert-4 {
165 temperature = <90000>; /* millicelsius */
166 hysteresis = <1000>; /* millicelsius */
167 type = "active";
168 };
169 g3d_alert_5: g3d-alert-5 {
170 temperature = <95000>; /* millicelsius */
171 hysteresis = <1000>; /* millicelsius */
172 type = "active";
173 };
174 g3d_alert_6: g3d-alert-6 {
175 temperature = <100000>; /* millicelsius */
176 hysteresis = <1000>; /* millicelsius */
177 type = "active";
178 };
179 };
180 };
181
182 apollo_thermal: apollo-thermal {
183 thermal-sensors = <&tmu_apollo>;
184 polling-delay-passive = <0>;
185 polling-delay = <0>;
186 trips {
187 apollo_alert_0: apollo-alert-0 {
188 temperature = <65000>; /* millicelsius */
189 hysteresis = <1000>; /* millicelsius */
190 type = "active";
191 };
192 apollo_alert_1: apollo-alert-1 {
193 temperature = <70000>; /* millicelsius */
194 hysteresis = <1000>; /* millicelsius */
195 type = "active";
196 };
197 apollo_alert_2: apollo-alert-2 {
198 temperature = <75000>; /* millicelsius */
199 hysteresis = <1000>; /* millicelsius */
200 type = "active";
201 };
202 apollo_alert_3: apollo-alert-3 {
203 temperature = <80000>; /* millicelsius */
204 hysteresis = <1000>; /* millicelsius */
205 type = "active";
206 };
207 apollo_alert_4: apollo-alert-4 {
208 temperature = <85000>; /* millicelsius */
209 hysteresis = <1000>; /* millicelsius */
210 type = "active";
211 };
212 apollo_alert_5: apollo-alert-5 {
213 temperature = <90000>; /* millicelsius */
214 hysteresis = <1000>; /* millicelsius */
215 type = "active";
216 };
217 apollo_alert_6: apollo-alert-6 {
218 temperature = <95000>; /* millicelsius */
219 hysteresis = <1000>; /* millicelsius */
220 type = "active";
221 };
222 };
223
224 cooling-maps {
225 map0 {
226 /* Set maximum frequency as 1200MHz */
227 trip = <&apollo_alert_2>;
228 cooling-device = <&cpu0 1 2>;
229 };
230 map1 {
231 /* Set maximum frequency as 1100MHz */
232 trip = <&apollo_alert_3>;
233 cooling-device = <&cpu0 2 3>;
234 };
235 map2 {
236 /* Set maximum frequency as 1000MHz */
237 trip = <&apollo_alert_4>;
238 cooling-device = <&cpu0 3 4>;
239 };
240 map3 {
241 /* Set maximum frequency as 900MHz */
242 trip = <&apollo_alert_5>;
243 cooling-device = <&cpu0 4 5>;
244 };
245 map4 {
246 /* Set maximum frequency as 800MHz */
247 trip = <&apollo_alert_6>;
248 cooling-device = <&cpu0 5 9>;
249 };
250 };
251 };
252
253 isp_thermal: isp-thermal {
254 thermal-sensors = <&tmu_isp>;
255 polling-delay-passive = <0>;
256 polling-delay = <0>;
257 trips {
258 isp_alert_0: isp-alert-0 {
259 temperature = <80000>; /* millicelsius */
260 hysteresis = <1000>; /* millicelsius */
261 type = "active";
262 };
263 isp_alert_1: isp-alert-1 {
264 temperature = <85000>; /* millicelsius */
265 hysteresis = <1000>; /* millicelsius */
266 type = "active";
267 };
268 isp_alert_2: isp-alert-2 {
269 temperature = <90000>; /* millicelsius */
270 hysteresis = <1000>; /* millicelsius */
271 type = "active";
272 };
273 isp_alert_3: isp-alert-3 {
274 temperature = <95000>; /* millicelsius */
275 hysteresis = <1000>; /* millicelsius */
276 type = "active";
277 };
278 isp_alert_4: isp-alert-4 {
279 temperature = <100000>; /* millicelsius */
280 hysteresis = <1000>; /* millicelsius */
281 type = "active";
282 };
283 isp_alert_5: isp-alert-5 {
284 temperature = <105000>; /* millicelsius */
285 hysteresis = <1000>; /* millicelsius */
286 type = "active";
287 };
288 isp_alert_6: isp-alert-6 {
289 temperature = <110000>; /* millicelsius */
290 hysteresis = <1000>; /* millicelsius */
291 type = "active";
292 };
293 };
294 };
295};
296};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
new file mode 100644
index 000000000000..1188630823a7
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -0,0 +1,1356 @@
1/*
2 * Samsung's Exynos5433 SoC device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 *
6 * Samsung's Exynos5433 SoC device nodes are listed in this file.
7 * Exynos5433 based board files can include this file and provide
8 * values for board specific bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
12 * additional nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <dt-bindings/clock/exynos5433.h>
20#include <dt-bindings/interrupt-controller/arm-gic.h>
21
22/ {
23 compatible = "samsung,exynos5433";
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 interrupt-parent = <&gic>;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@100 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
37 reg = <0x100>;
38 clock-frequency = <1300000000>;
39 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
40 clock-names = "apolloclk";
41 operating-points-v2 = <&cluster_a53_opp_table>;
42 #cooling-cells = <2>;
43 };
44
45 cpu1: cpu@101 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
49 reg = <0x101>;
50 clock-frequency = <1300000000>;
51 operating-points-v2 = <&cluster_a53_opp_table>;
52 #cooling-cells = <2>;
53 };
54
55 cpu2: cpu@102 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
59 reg = <0x102>;
60 clock-frequency = <1300000000>;
61 operating-points-v2 = <&cluster_a53_opp_table>;
62 #cooling-cells = <2>;
63 };
64
65 cpu3: cpu@103 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
69 reg = <0x103>;
70 clock-frequency = <1300000000>;
71 operating-points-v2 = <&cluster_a53_opp_table>;
72 #cooling-cells = <2>;
73 };
74
75 cpu4: cpu@0 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a57", "arm,armv8";
78 enable-method = "psci";
79 reg = <0x0>;
80 clock-frequency = <1900000000>;
81 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
82 clock-names = "atlasclk";
83 operating-points-v2 = <&cluster_a57_opp_table>;
84 #cooling-cells = <2>;
85 };
86
87 cpu5: cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a57", "arm,armv8";
90 enable-method = "psci";
91 reg = <0x1>;
92 clock-frequency = <1900000000>;
93 operating-points-v2 = <&cluster_a57_opp_table>;
94 #cooling-cells = <2>;
95 };
96
97 cpu6: cpu@2 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a57", "arm,armv8";
100 enable-method = "psci";
101 reg = <0x2>;
102 clock-frequency = <1900000000>;
103 operating-points-v2 = <&cluster_a57_opp_table>;
104 #cooling-cells = <2>;
105 };
106
107 cpu7: cpu@3 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a57", "arm,armv8";
110 enable-method = "psci";
111 reg = <0x3>;
112 clock-frequency = <1900000000>;
113 operating-points-v2 = <&cluster_a57_opp_table>;
114 #cooling-cells = <2>;
115 };
116 };
117
118 cluster_a53_opp_table: opp_table0 {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp@400000000 {
123 opp-hz = /bits/ 64 <400000000>;
124 opp-microvolt = <900000>;
125 };
126 opp@500000000 {
127 opp-hz = /bits/ 64 <500000000>;
128 opp-microvolt = <925000>;
129 };
130 opp@600000000 {
131 opp-hz = /bits/ 64 <600000000>;
132 opp-microvolt = <950000>;
133 };
134 opp@700000000 {
135 opp-hz = /bits/ 64 <700000000>;
136 opp-microvolt = <975000>;
137 };
138 opp@800000000 {
139 opp-hz = /bits/ 64 <800000000>;
140 opp-microvolt = <1000000>;
141 };
142 opp@900000000 {
143 opp-hz = /bits/ 64 <900000000>;
144 opp-microvolt = <1050000>;
145 };
146 opp@1000000000 {
147 opp-hz = /bits/ 64 <1000000000>;
148 opp-microvolt = <1075000>;
149 };
150 opp@1100000000 {
151 opp-hz = /bits/ 64 <1100000000>;
152 opp-microvolt = <1112500>;
153 };
154 opp@1200000000 {
155 opp-hz = /bits/ 64 <1200000000>;
156 opp-microvolt = <1112500>;
157 };
158 opp@1300000000 {
159 opp-hz = /bits/ 64 <1300000000>;
160 opp-microvolt = <1150000>;
161 };
162 };
163
164 cluster_a57_opp_table: opp_table1 {
165 compatible = "operating-points-v2";
166 opp-shared;
167
168 opp@500000000 {
169 opp-hz = /bits/ 64 <500000000>;
170 opp-microvolt = <900000>;
171 };
172 opp@600000000 {
173 opp-hz = /bits/ 64 <600000000>;
174 opp-microvolt = <900000>;
175 };
176 opp@700000000 {
177 opp-hz = /bits/ 64 <700000000>;
178 opp-microvolt = <912500>;
179 };
180 opp@800000000 {
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <912500>;
183 };
184 opp@900000000 {
185 opp-hz = /bits/ 64 <900000000>;
186 opp-microvolt = <937500>;
187 };
188 opp@1000000000 {
189 opp-hz = /bits/ 64 <1000000000>;
190 opp-microvolt = <975000>;
191 };
192 opp@1100000000 {
193 opp-hz = /bits/ 64 <1100000000>;
194 opp-microvolt = <1012500>;
195 };
196 opp@1200000000 {
197 opp-hz = /bits/ 64 <1200000000>;
198 opp-microvolt = <1037500>;
199 };
200 opp@1300000000 {
201 opp-hz = /bits/ 64 <1300000000>;
202 opp-microvolt = <1062500>;
203 };
204 opp@1400000000 {
205 opp-hz = /bits/ 64 <1400000000>;
206 opp-microvolt = <1087500>;
207 };
208 opp@1500000000 {
209 opp-hz = /bits/ 64 <1500000000>;
210 opp-microvolt = <1125000>;
211 };
212 opp@1600000000 {
213 opp-hz = /bits/ 64 <1600000000>;
214 opp-microvolt = <1137500>;
215 };
216 opp@1700000000 {
217 opp-hz = /bits/ 64 <1700000000>;
218 opp-microvolt = <1175000>;
219 };
220 opp@1800000000 {
221 opp-hz = /bits/ 64 <1800000000>;
222 opp-microvolt = <1212500>;
223 };
224 opp@1900000000 {
225 opp-hz = /bits/ 64 <1900000000>;
226 opp-microvolt = <1262500>;
227 };
228 };
229
230 psci {
231 compatible = "arm,psci";
232 method = "smc";
233 cpu_off = <0x84000002>;
234 cpu_on = <0xC4000003>;
235 };
236
237 reboot: syscon-reboot {
238 compatible = "syscon-reboot";
239 regmap = <&pmu_system_controller>;
240 offset = <0x400>; /* SWRESET */
241 mask = <0x1>;
242 };
243
244 soc: soc {
245 compatible = "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0x0 0x0 0x0 0x18000000>;
249
250 chipid@10000000 {
251 compatible = "samsung,exynos4210-chipid";
252 reg = <0x10000000 0x100>;
253 };
254
255 xxti: xxti {
256 compatible = "fixed-clock";
257 clock-output-names = "oscclk";
258 #clock-cells = <0>;
259 };
260
261 cmu_top: clock-controller@10030000 {
262 compatible = "samsung,exynos5433-cmu-top";
263 reg = <0x10030000 0x1000>;
264 #clock-cells = <1>;
265
266 clock-names = "oscclk",
267 "sclk_mphy_pll",
268 "sclk_mfc_pll",
269 "sclk_bus_pll";
270 clocks = <&xxti>,
271 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
272 <&cmu_mif CLK_SCLK_MFC_PLL>,
273 <&cmu_mif CLK_SCLK_BUS_PLL>;
274 };
275
276 cmu_cpif: clock-controller@10fc0000 {
277 compatible = "samsung,exynos5433-cmu-cpif";
278 reg = <0x10fc0000 0x1000>;
279 #clock-cells = <1>;
280
281 clock-names = "oscclk";
282 clocks = <&xxti>;
283 };
284
285 cmu_mif: clock-controller@105b0000 {
286 compatible = "samsung,exynos5433-cmu-mif";
287 reg = <0x105b0000 0x2000>;
288 #clock-cells = <1>;
289
290 clock-names = "oscclk",
291 "sclk_mphy_pll";
292 clocks = <&xxti>,
293 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
294 };
295
296 cmu_peric: clock-controller@14c80000 {
297 compatible = "samsung,exynos5433-cmu-peric";
298 reg = <0x14c80000 0x1000>;
299 #clock-cells = <1>;
300 };
301
302 cmu_peris: clock-controller@0x10040000 {
303 compatible = "samsung,exynos5433-cmu-peris";
304 reg = <0x10040000 0x1000>;
305 #clock-cells = <1>;
306 };
307
308 cmu_fsys: clock-controller@156e0000 {
309 compatible = "samsung,exynos5433-cmu-fsys";
310 reg = <0x156e0000 0x1000>;
311 #clock-cells = <1>;
312
313 clock-names = "oscclk",
314 "sclk_ufs_mphy",
315 "div_aclk_fsys_200",
316 "sclk_pcie_100_fsys",
317 "sclk_ufsunipro_fsys",
318 "sclk_mmc2_fsys",
319 "sclk_mmc1_fsys",
320 "sclk_mmc0_fsys",
321 "sclk_usbhost30_fsys",
322 "sclk_usbdrd30_fsys";
323 clocks = <&xxti>,
324 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
325 <&cmu_top CLK_DIV_ACLK_FSYS_200>,
326 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
327 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
328 <&cmu_top CLK_SCLK_MMC2_FSYS>,
329 <&cmu_top CLK_SCLK_MMC1_FSYS>,
330 <&cmu_top CLK_SCLK_MMC0_FSYS>,
331 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
332 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
333 };
334
335 cmu_g2d: clock-controller@12460000 {
336 compatible = "samsung,exynos5433-cmu-g2d";
337 reg = <0x12460000 0x1000>;
338 #clock-cells = <1>;
339
340 clock-names = "oscclk",
341 "aclk_g2d_266",
342 "aclk_g2d_400";
343 clocks = <&xxti>,
344 <&cmu_top CLK_ACLK_G2D_266>,
345 <&cmu_top CLK_ACLK_G2D_400>;
346 };
347
348 cmu_disp: clock-controller@13b90000 {
349 compatible = "samsung,exynos5433-cmu-disp";
350 reg = <0x13b90000 0x1000>;
351 #clock-cells = <1>;
352
353 clock-names = "oscclk",
354 "sclk_dsim1_disp",
355 "sclk_dsim0_disp",
356 "sclk_dsd_disp",
357 "sclk_decon_tv_eclk_disp",
358 "sclk_decon_vclk_disp",
359 "sclk_decon_eclk_disp",
360 "sclk_decon_tv_vclk_disp",
361 "aclk_disp_333";
362 clocks = <&xxti>,
363 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
364 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
365 <&cmu_mif CLK_SCLK_DSD_DISP>,
366 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
367 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
368 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
369 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
370 <&cmu_mif CLK_ACLK_DISP_333>;
371 };
372
373 cmu_aud: clock-controller@114c0000 {
374 compatible = "samsung,exynos5433-cmu-aud";
375 reg = <0x114c0000 0x1000>;
376 #clock-cells = <1>;
377 };
378
379 cmu_bus0: clock-controller@13600000 {
380 compatible = "samsung,exynos5433-cmu-bus0";
381 reg = <0x13600000 0x1000>;
382 #clock-cells = <1>;
383
384 clock-names = "aclk_bus0_400";
385 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
386 };
387
388 cmu_bus1: clock-controller@14800000 {
389 compatible = "samsung,exynos5433-cmu-bus1";
390 reg = <0x14800000 0x1000>;
391 #clock-cells = <1>;
392
393 clock-names = "aclk_bus1_400";
394 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
395 };
396
397 cmu_bus2: clock-controller@13400000 {
398 compatible = "samsung,exynos5433-cmu-bus2";
399 reg = <0x13400000 0x1000>;
400 #clock-cells = <1>;
401
402 clock-names = "oscclk", "aclk_bus2_400";
403 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
404 };
405
406 cmu_g3d: clock-controller@14aa0000 {
407 compatible = "samsung,exynos5433-cmu-g3d";
408 reg = <0x14aa0000 0x2000>;
409 #clock-cells = <1>;
410
411 clock-names = "oscclk", "aclk_g3d_400";
412 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
413 };
414
415 cmu_gscl: clock-controller@13cf0000 {
416 compatible = "samsung,exynos5433-cmu-gscl";
417 reg = <0x13cf0000 0x1000>;
418 #clock-cells = <1>;
419
420 clock-names = "oscclk",
421 "aclk_gscl_111",
422 "aclk_gscl_333";
423 clocks = <&xxti>,
424 <&cmu_top CLK_ACLK_GSCL_111>,
425 <&cmu_top CLK_ACLK_GSCL_333>;
426 };
427
428 cmu_apollo: clock-controller@11900000 {
429 compatible = "samsung,exynos5433-cmu-apollo";
430 reg = <0x11900000 0x2000>;
431 #clock-cells = <1>;
432
433 clock-names = "oscclk", "sclk_bus_pll_apollo";
434 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
435 };
436
437 cmu_atlas: clock-controller@11800000 {
438 compatible = "samsung,exynos5433-cmu-atlas";
439 reg = <0x11800000 0x2000>;
440 #clock-cells = <1>;
441
442 clock-names = "oscclk", "sclk_bus_pll_atlas";
443 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
444 };
445
446 cmu_mscl: clock-controller@105d0000 {
447 compatible = "samsung,exynos5433-cmu-mscl";
448 reg = <0x150d0000 0x1000>;
449 #clock-cells = <1>;
450
451 clock-names = "oscclk",
452 "sclk_jpeg_mscl",
453 "aclk_mscl_400";
454 clocks = <&xxti>,
455 <&cmu_top CLK_SCLK_JPEG_MSCL>,
456 <&cmu_top CLK_ACLK_MSCL_400>;
457 };
458
459 cmu_mfc: clock-controller@15280000 {
460 compatible = "samsung,exynos5433-cmu-mfc";
461 reg = <0x15280000 0x1000>;
462 #clock-cells = <1>;
463
464 clock-names = "oscclk", "aclk_mfc_400";
465 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
466 };
467
468 cmu_hevc: clock-controller@14f80000 {
469 compatible = "samsung,exynos5433-cmu-hevc";
470 reg = <0x14f80000 0x1000>;
471 #clock-cells = <1>;
472
473 clock-names = "oscclk", "aclk_hevc_400";
474 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
475 };
476
477 cmu_isp: clock-controller@146d0000 {
478 compatible = "samsung,exynos5433-cmu-isp";
479 reg = <0x146d0000 0x1000>;
480 #clock-cells = <1>;
481
482 clock-names = "oscclk",
483 "aclk_isp_dis_400",
484 "aclk_isp_400";
485 clocks = <&xxti>,
486 <&cmu_top CLK_ACLK_ISP_DIS_400>,
487 <&cmu_top CLK_ACLK_ISP_400>;
488 };
489
490 cmu_cam0: clock-controller@120d0000 {
491 compatible = "samsung,exynos5433-cmu-cam0";
492 reg = <0x120d0000 0x1000>;
493 #clock-cells = <1>;
494
495 clock-names = "oscclk",
496 "aclk_cam0_333",
497 "aclk_cam0_400",
498 "aclk_cam0_552";
499 clocks = <&xxti>,
500 <&cmu_top CLK_ACLK_CAM0_333>,
501 <&cmu_top CLK_ACLK_CAM0_400>,
502 <&cmu_top CLK_ACLK_CAM0_552>;
503 };
504
505 cmu_cam1: clock-controller@145d0000 {
506 compatible = "samsung,exynos5433-cmu-cam1";
507 reg = <0x145d0000 0x1000>;
508 #clock-cells = <1>;
509
510 clock-names = "oscclk",
511 "sclk_isp_uart_cam1",
512 "sclk_isp_spi1_cam1",
513 "sclk_isp_spi0_cam1",
514 "aclk_cam1_333",
515 "aclk_cam1_400",
516 "aclk_cam1_552";
517 clocks = <&xxti>,
518 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
519 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
520 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
521 <&cmu_top CLK_ACLK_CAM1_333>,
522 <&cmu_top CLK_ACLK_CAM1_400>,
523 <&cmu_top CLK_ACLK_CAM1_552>;
524 };
525
526 tmu_atlas0: tmu@10060000 {
527 compatible = "samsung,exynos5433-tmu";
528 reg = <0x10060000 0x200>;
529 interrupts = <GIC_SPI 95 0>;
530 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
531 <&cmu_peris CLK_SCLK_TMU0>;
532 clock-names = "tmu_apbif", "tmu_sclk";
533 #include "exynos5433-tmu-sensor-conf.dtsi"
534 status = "disabled";
535 };
536
537 tmu_atlas1: tmu@10068000 {
538 compatible = "samsung,exynos5433-tmu";
539 reg = <0x10068000 0x200>;
540 interrupts = <GIC_SPI 96 0>;
541 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
542 <&cmu_peris CLK_SCLK_TMU0>;
543 clock-names = "tmu_apbif", "tmu_sclk";
544 #include "exynos5433-tmu-sensor-conf.dtsi"
545 status = "disabled";
546 };
547
548 tmu_g3d: tmu@10070000 {
549 compatible = "samsung,exynos5433-tmu";
550 reg = <0x10070000 0x200>;
551 interrupts = <GIC_SPI 99 0>;
552 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
553 <&cmu_peris CLK_SCLK_TMU1>;
554 clock-names = "tmu_apbif", "tmu_sclk";
555 #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
556 status = "disabled";
557 };
558
559 tmu_apollo: tmu@10078000 {
560 compatible = "samsung,exynos5433-tmu";
561 reg = <0x10078000 0x200>;
562 interrupts = <GIC_SPI 115 0>;
563 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
564 <&cmu_peris CLK_SCLK_TMU1>;
565 clock-names = "tmu_apbif", "tmu_sclk";
566 #include "exynos5433-tmu-sensor-conf.dtsi"
567 status = "disabled";
568 };
569
570 tmu_isp: tmu@1007c000 {
571 compatible = "samsung,exynos5433-tmu";
572 reg = <0x1007c000 0x200>;
573 interrupts = <GIC_SPI 94 0>;
574 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
575 <&cmu_peris CLK_SCLK_TMU1>;
576 clock-names = "tmu_apbif", "tmu_sclk";
577 #include "exynos5433-tmu-sensor-conf.dtsi"
578 status = "disabled";
579 };
580
581 mct@101c0000 {
582 compatible = "samsung,exynos4210-mct";
583 reg = <0x101c0000 0x800>;
584 interrupts = <GIC_SPI 102 0>, <GIC_SPI 103 0>,
585 <GIC_SPI 104 0>, <GIC_SPI 105 0>,
586 <GIC_SPI 106 0>, <GIC_SPI 107 0>,
587 <GIC_SPI 108 0>, <GIC_SPI 109 0>,
588 <GIC_SPI 110 0>, <GIC_SPI 111 0>,
589 <GIC_SPI 112 0>, <GIC_SPI 113 0>;
590 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
591 clock-names = "fin_pll", "mct";
592 };
593
594 pinctrl_alive: pinctrl@10580000 {
595 compatible = "samsung,exynos5433-pinctrl";
596 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
597
598 wakeup-interrupt-controller {
599 compatible = "samsung,exynos7-wakeup-eint";
600 interrupts = <GIC_SPI 16 0>;
601 };
602 };
603
604 pinctrl_aud: pinctrl@114b0000 {
605 compatible = "samsung,exynos5433-pinctrl";
606 reg = <0x114b0000 0x1000>;
607 interrupts = <GIC_SPI 68 0>;
608 };
609
610 pinctrl_cpif: pinctrl@10fe0000 {
611 compatible = "samsung,exynos5433-pinctrl";
612 reg = <0x10fe0000 0x1000>;
613 interrupts = <GIC_SPI 179 0>;
614 };
615
616 pinctrl_ese: pinctrl@14ca0000 {
617 compatible = "samsung,exynos5433-pinctrl";
618 reg = <0x14ca0000 0x1000>;
619 interrupts = <GIC_SPI 413 0>;
620 };
621
622 pinctrl_finger: pinctrl@14cb0000 {
623 compatible = "samsung,exynos5433-pinctrl";
624 reg = <0x14cb0000 0x1000>;
625 interrupts = <GIC_SPI 414 0>;
626 };
627
628 pinctrl_fsys: pinctrl@15690000 {
629 compatible = "samsung,exynos5433-pinctrl";
630 reg = <0x15690000 0x1000>;
631 interrupts = <GIC_SPI 229 0>;
632 };
633
634 pinctrl_imem: pinctrl@11090000 {
635 compatible = "samsung,exynos5433-pinctrl";
636 reg = <0x11090000 0x1000>;
637 interrupts = <GIC_SPI 325 0>;
638 };
639
640 pinctrl_nfc: pinctrl@14cd0000 {
641 compatible = "samsung,exynos5433-pinctrl";
642 reg = <0x14cd0000 0x1000>;
643 interrupts = <GIC_SPI 441 0>;
644 };
645
646 pinctrl_peric: pinctrl@14cc0000 {
647 compatible = "samsung,exynos5433-pinctrl";
648 reg = <0x14cc0000 0x1100>;
649 interrupts = <GIC_SPI 440 0>;
650 };
651
652 pinctrl_touch: pinctrl@14ce0000 {
653 compatible = "samsung,exynos5433-pinctrl";
654 reg = <0x14ce0000 0x1100>;
655 interrupts = <GIC_SPI 442 0>;
656 };
657
658 pmu_system_controller: system-controller@105c0000 {
659 compatible = "samsung,exynos5433-pmu", "syscon";
660 reg = <0x105c0000 0x5008>;
661 #clock-cells = <1>;
662 clock-names = "clkout16";
663 clocks = <&xxti>;
664 };
665
666 gic: interrupt-controller@11001000 {
667 compatible = "arm,gic-400";
668 #interrupt-cells = <3>;
669 interrupt-controller;
670 reg = <0x11001000 0x1000>,
671 <0x11002000 0x2000>,
672 <0x11004000 0x2000>,
673 <0x11006000 0x2000>;
674 interrupts = <GIC_PPI 9 0xf04>;
675 };
676
677 mipi_phy: video-phy@105c0710 {
678 compatible = "samsung,exynos5433-mipi-video-phy";
679 #phy-cells = <1>;
680 samsung,pmu-syscon = <&pmu_system_controller>;
681 samsung,cam0-sysreg = <&syscon_cam0>;
682 samsung,cam1-sysreg = <&syscon_cam1>;
683 samsung,disp-sysreg = <&syscon_disp>;
684 };
685
686 decon: decon@13800000 {
687 compatible = "samsung,exynos5433-decon";
688 reg = <0x13800000 0x2104>;
689 clocks = <&cmu_disp CLK_PCLK_DECON>,
690 <&cmu_disp CLK_ACLK_DECON>,
691 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
692 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
693 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
694 <&cmu_disp CLK_SCLK_DECON_VCLK>,
695 <&cmu_disp CLK_SCLK_DECON_ECLK>;
696 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
697 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
698 "sclk_decon_vclk", "sclk_decon_eclk";
699 interrupt-names = "fifo", "vsync", "lcd_sys";
700 interrupts = <GIC_SPI 201 0>, <GIC_SPI 202 0>,
701 <GIC_SPI 203 0>;
702 samsung,disp-sysreg = <&syscon_disp>;
703 status = "disabled";
704 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
705 iommu-names = "m0", "m1";
706
707 ports {
708 #address-cells = <1>;
709 #size-cells = <0>;
710
711 port@0 {
712 reg = <0>;
713 decon_to_mic: endpoint {
714 remote-endpoint =
715 <&mic_to_decon>;
716 };
717 };
718 };
719 };
720
721 dsi: dsi@13900000 {
722 compatible = "samsung,exynos5433-mipi-dsi";
723 reg = <0x13900000 0xC0>;
724 interrupts = <GIC_SPI 205 0>;
725 phys = <&mipi_phy 1>;
726 phy-names = "dsim";
727 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
728 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
729 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
730 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
731 <&cmu_disp CLK_SCLK_DSIM0>;
732 clock-names = "bus_clk",
733 "phyclk_mipidphy0_bitclkdiv8",
734 "phyclk_mipidphy0_rxclkesc0",
735 "sclk_rgb_vclk_to_dsim0",
736 "sclk_mipi";
737 status = "disabled";
738 #address-cells = <1>;
739 #size-cells = <0>;
740
741 ports {
742 #address-cells = <1>;
743 #size-cells = <0>;
744
745 port@0 {
746 reg = <0>;
747 dsi_to_mic: endpoint {
748 remote-endpoint = <&mic_to_dsi>;
749 };
750 };
751 };
752 };
753
754 mic: mic@13930000 {
755 compatible = "samsung,exynos5433-mic";
756 reg = <0x13930000 0x48>;
757 clocks = <&cmu_disp CLK_PCLK_MIC0>,
758 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
759 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
760 samsung,disp-syscon = <&syscon_disp>;
761 status = "disabled";
762
763 ports {
764 #address-cells = <1>;
765 #size-cells = <0>;
766
767 port@0 {
768 reg = <0>;
769 mic_to_decon: endpoint {
770 remote-endpoint =
771 <&decon_to_mic>;
772 };
773 };
774
775 port@1 {
776 reg = <1>;
777 mic_to_dsi: endpoint {
778 remote-endpoint = <&dsi_to_mic>;
779 };
780 };
781 };
782 };
783
784 syscon_disp: syscon@13b80000 {
785 compatible = "syscon";
786 reg = <0x13b80000 0x1010>;
787 };
788
789 syscon_cam0: syscon@120f0000 {
790 compatible = "syscon";
791 reg = <0x120f0000 0x1020>;
792 };
793
794 syscon_cam1: syscon@145f0000 {
795 compatible = "syscon";
796 reg = <0x145f0000 0x1038>;
797 };
798
799 sysmmu_decon0x: sysmmu@0x13a00000 {
800 compatible = "samsung,exynos-sysmmu";
801 reg = <0x13a00000 0x1000>;
802 interrupts = <GIC_SPI 192 0>;
803 clock-names = "pclk", "aclk";
804 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
805 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
806 #iommu-cells = <0>;
807 };
808
809 sysmmu_decon1x: sysmmu@0x13a10000 {
810 compatible = "samsung,exynos-sysmmu";
811 reg = <0x13a10000 0x1000>;
812 interrupts = <GIC_SPI 194 0>;
813 clock-names = "pclk", "aclk";
814 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
815 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
816 #iommu-cells = <0>;
817 };
818
819 serial_0: serial@14c10000 {
820 compatible = "samsung,exynos5433-uart";
821 reg = <0x14c10000 0x100>;
822 interrupts = <GIC_SPI 421 0>;
823 clocks = <&cmu_peric CLK_PCLK_UART0>,
824 <&cmu_peric CLK_SCLK_UART0>;
825 clock-names = "uart", "clk_uart_baud0";
826 pinctrl-names = "default";
827 pinctrl-0 = <&uart0_bus>;
828 status = "disabled";
829 };
830
831 serial_1: serial@14c20000 {
832 compatible = "samsung,exynos5433-uart";
833 reg = <0x14c20000 0x100>;
834 interrupts = <GIC_SPI 422 0>;
835 clocks = <&cmu_peric CLK_PCLK_UART1>,
836 <&cmu_peric CLK_SCLK_UART1>;
837 clock-names = "uart", "clk_uart_baud0";
838 pinctrl-names = "default";
839 pinctrl-0 = <&uart1_bus>;
840 status = "disabled";
841 };
842
843 serial_2: serial@14c30000 {
844 compatible = "samsung,exynos5433-uart";
845 reg = <0x14c30000 0x100>;
846 interrupts = <GIC_SPI 423 0>;
847 clocks = <&cmu_peric CLK_PCLK_UART2>,
848 <&cmu_peric CLK_SCLK_UART2>;
849 clock-names = "uart", "clk_uart_baud0";
850 pinctrl-names = "default";
851 pinctrl-0 = <&uart2_bus>;
852 status = "disabled";
853 };
854
855 spi_0: spi@14d20000 {
856 compatible = "samsung,exynos5433-spi";
857 reg = <0x14d20000 0x100>;
858 interrupts = <GIC_SPI 432 0>;
859 dmas = <&pdma0 9>, <&pdma0 8>;
860 dma-names = "tx", "rx";
861 #address-cells = <1>;
862 #size-cells = <0>;
863 clocks = <&cmu_peric CLK_PCLK_SPI0>,
864 <&cmu_peric CLK_SCLK_SPI0>,
865 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
866 clock-names = "spi", "spi_busclk0", "spi_ioclk";
867 samsung,spi-src-clk = <0>;
868 pinctrl-names = "default";
869 pinctrl-0 = <&spi0_bus>;
870 num-cs = <1>;
871 status = "disabled";
872 };
873
874 spi_1: spi@14d30000 {
875 compatible = "samsung,exynos5433-spi";
876 reg = <0x14d30000 0x100>;
877 interrupts = <GIC_SPI 433 0>;
878 dmas = <&pdma0 11>, <&pdma0 10>;
879 dma-names = "tx", "rx";
880 #address-cells = <1>;
881 #size-cells = <0>;
882 clocks = <&cmu_peric CLK_PCLK_SPI1>,
883 <&cmu_peric CLK_SCLK_SPI1>,
884 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
885 clock-names = "spi", "spi_busclk0", "spi_ioclk";
886 samsung,spi-src-clk = <0>;
887 pinctrl-names = "default";
888 pinctrl-0 = <&spi1_bus>;
889 num-cs = <1>;
890 status = "disabled";
891 };
892
893 spi_2: spi@14d40000 {
894 compatible = "samsung,exynos5433-spi";
895 reg = <0x14d40000 0x100>;
896 interrupts = <GIC_SPI 434 0>;
897 dmas = <&pdma0 13>, <&pdma0 12>;
898 dma-names = "tx", "rx";
899 #address-cells = <1>;
900 #size-cells = <0>;
901 clocks = <&cmu_peric CLK_PCLK_SPI2>,
902 <&cmu_peric CLK_SCLK_SPI2>,
903 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
904 clock-names = "spi", "spi_busclk0", "spi_ioclk";
905 samsung,spi-src-clk = <0>;
906 pinctrl-names = "default";
907 pinctrl-0 = <&spi2_bus>;
908 num-cs = <1>;
909 status = "disabled";
910 };
911
912 spi_3: spi@14d50000 {
913 compatible = "samsung,exynos5433-spi";
914 reg = <0x14d50000 0x100>;
915 interrupts = <GIC_SPI 447 0>;
916 dmas = <&pdma0 23>, <&pdma0 22>;
917 dma-names = "tx", "rx";
918 #address-cells = <1>;
919 #size-cells = <0>;
920 clocks = <&cmu_peric CLK_PCLK_SPI3>,
921 <&cmu_peric CLK_SCLK_SPI3>,
922 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
923 clock-names = "spi", "spi_busclk0", "spi_ioclk";
924 samsung,spi-src-clk = <0>;
925 pinctrl-names = "default";
926 pinctrl-0 = <&spi3_bus>;
927 num-cs = <1>;
928 status = "disabled";
929 };
930
931 spi_4: spi@14d00000 {
932 compatible = "samsung,exynos5433-spi";
933 reg = <0x14d00000 0x100>;
934 interrupts = <GIC_SPI 412 0>;
935 dmas = <&pdma0 25>, <&pdma0 24>;
936 dma-names = "tx", "rx";
937 #address-cells = <1>;
938 #size-cells = <0>;
939 clocks = <&cmu_peric CLK_PCLK_SPI4>,
940 <&cmu_peric CLK_SCLK_SPI4>,
941 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
942 clock-names = "spi", "spi_busclk0", "spi_ioclk";
943 samsung,spi-src-clk = <0>;
944 pinctrl-names = "default";
945 pinctrl-0 = <&spi4_bus>;
946 num-cs = <1>;
947 status = "disabled";
948 };
949
950 adc: adc@14d10000 {
951 compatible = "samsung,exynos7-adc";
952 reg = <0x14d10000 0x100>;
953 interrupts = <GIC_SPI 438 0>;
954 clock-names = "adc";
955 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
956 #io-channel-cells = <1>;
957 io-channel-ranges;
958 status = "disabled";
959 };
960
961 pwm: pwm@14dd0000 {
962 compatible = "samsung,exynos4210-pwm";
963 reg = <0x14dd0000 0x100>;
964 interrupts = <GIC_SPI 416 0>, <GIC_SPI 417 0>,
965 <GIC_SPI 418 0>, <GIC_SPI 419 0>,
966 <GIC_SPI 420 0>;
967 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
968 clocks = <&cmu_peric CLK_PCLK_PWM>;
969 clock-names = "timers";
970 #pwm-cells = <3>;
971 status = "disabled";
972 };
973
974 hsi2c_0: hsi2c@14e40000 {
975 compatible = "samsung,exynos7-hsi2c";
976 reg = <0x14e40000 0x1000>;
977 interrupts = <GIC_SPI 428 0>;
978 #address-cells = <1>;
979 #size-cells = <0>;
980 pinctrl-names = "default";
981 pinctrl-0 = <&hs_i2c0_bus>;
982 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
983 clock-names = "hsi2c";
984 status = "disabled";
985 };
986
987 hsi2c_1: hsi2c@14e50000 {
988 compatible = "samsung,exynos7-hsi2c";
989 reg = <0x14e50000 0x1000>;
990 interrupts = <GIC_SPI 429 0>;
991 #address-cells = <1>;
992 #size-cells = <0>;
993 pinctrl-names = "default";
994 pinctrl-0 = <&hs_i2c1_bus>;
995 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
996 clock-names = "hsi2c";
997 status = "disabled";
998 };
999
1000 hsi2c_2: hsi2c@14e60000 {
1001 compatible = "samsung,exynos7-hsi2c";
1002 reg = <0x14e60000 0x1000>;
1003 interrupts = <GIC_SPI 430 0>;
1004 #address-cells = <1>;
1005 #size-cells = <0>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&hs_i2c2_bus>;
1008 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1009 clock-names = "hsi2c";
1010 status = "disabled";
1011 };
1012
1013 hsi2c_3: hsi2c@14e70000 {
1014 compatible = "samsung,exynos7-hsi2c";
1015 reg = <0x14e70000 0x1000>;
1016 interrupts = <GIC_SPI 431 0>;
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&hs_i2c3_bus>;
1021 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1022 clock-names = "hsi2c";
1023 status = "disabled";
1024 };
1025
1026 hsi2c_4: hsi2c@14ec0000 {
1027 compatible = "samsung,exynos7-hsi2c";
1028 reg = <0x14ec0000 0x1000>;
1029 interrupts = <GIC_SPI 424 0>;
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&hs_i2c4_bus>;
1034 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1035 clock-names = "hsi2c";
1036 status = "disabled";
1037 };
1038
1039 hsi2c_5: hsi2c@14ed0000 {
1040 compatible = "samsung,exynos7-hsi2c";
1041 reg = <0x14ed0000 0x1000>;
1042 interrupts = <GIC_SPI 425 0>;
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&hs_i2c5_bus>;
1047 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1048 clock-names = "hsi2c";
1049 status = "disabled";
1050 };
1051
1052 hsi2c_6: hsi2c@14ee0000 {
1053 compatible = "samsung,exynos7-hsi2c";
1054 reg = <0x14ee0000 0x1000>;
1055 interrupts = <GIC_SPI 426 0>;
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&hs_i2c6_bus>;
1060 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1061 clock-names = "hsi2c";
1062 status = "disabled";
1063 };
1064
1065 hsi2c_7: hsi2c@14ef0000 {
1066 compatible = "samsung,exynos7-hsi2c";
1067 reg = <0x14ef0000 0x1000>;
1068 interrupts = <GIC_SPI 427 0>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&hs_i2c7_bus>;
1073 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1074 clock-names = "hsi2c";
1075 status = "disabled";
1076 };
1077
1078 hsi2c_8: hsi2c@14d90000 {
1079 compatible = "samsung,exynos7-hsi2c";
1080 reg = <0x14d90000 0x1000>;
1081 interrupts = <GIC_SPI 443 0>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 pinctrl-names = "default";
1085 pinctrl-0 = <&hs_i2c8_bus>;
1086 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1087 clock-names = "hsi2c";
1088 status = "disabled";
1089 };
1090
1091 hsi2c_9: hsi2c@14da0000 {
1092 compatible = "samsung,exynos7-hsi2c";
1093 reg = <0x14da0000 0x1000>;
1094 interrupts = <GIC_SPI 444 0>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&hs_i2c9_bus>;
1099 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1100 clock-names = "hsi2c";
1101 status = "disabled";
1102 };
1103
1104 hsi2c_10: hsi2c@14de0000 {
1105 compatible = "samsung,exynos7-hsi2c";
1106 reg = <0x14de0000 0x1000>;
1107 interrupts = <GIC_SPI 445 0>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&hs_i2c10_bus>;
1112 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1113 clock-names = "hsi2c";
1114 status = "disabled";
1115 };
1116
1117 hsi2c_11: hsi2c@14df0000 {
1118 compatible = "samsung,exynos7-hsi2c";
1119 reg = <0x14df0000 0x1000>;
1120 interrupts = <GIC_SPI 446 0>;
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&hs_i2c11_bus>;
1125 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1126 clock-names = "hsi2c";
1127 status = "disabled";
1128 };
1129
1130 usbdrd30: usb@15400000 {
1131 compatible = "samsung,exynos5250-dwusb3";
1132 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1133 <&cmu_fsys CLK_SCLK_USBDRD30>;
1134 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1135 assigned-clocks =
1136 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
1137 <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
1138 <&cmu_top CLK_DIV_SCLK_USBDRD30>;
1139 assigned-clock-parents =
1140 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
1141 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
1142 assigned-clock-rates = <0>, <0>, <66700000>;
1143 #address-cells = <1>;
1144 #size-cells = <1>;
1145 ranges;
1146 status = "disabled";
1147
1148 dwc3@15400000 {
1149 compatible = "snps,dwc3";
1150 reg = <0x15400000 0x10000>;
1151 interrupts = <GIC_SPI 231 0>;
1152 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1153 phy-names = "usb2-phy", "usb3-phy";
1154 };
1155 };
1156
1157 usbdrd30_phy: phy@15500000 {
1158 compatible = "samsung,exynos5433-usbdrd-phy";
1159 reg = <0x15500000 0x100>;
1160 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1161 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1162 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1163 <&cmu_fsys CLK_SCLK_USBDRD30>;
1164 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1165 "itp";
1166 assigned-clocks =
1167 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
1168 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
1169 assigned-clock-parents =
1170 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
1171 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
1172 #phy-cells = <1>;
1173 samsung,pmu-syscon = <&pmu_system_controller>;
1174 status = "disabled";
1175 };
1176
1177 usbhost30_phy: phy@15580000 {
1178 compatible = "samsung,exynos5433-usbdrd-phy";
1179 reg = <0x15580000 0x100>;
1180 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1181 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1182 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1183 <&cmu_fsys CLK_SCLK_USBHOST30>;
1184 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1185 "itp";
1186 assigned-clocks =
1187 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
1188 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
1189 assigned-clock-parents =
1190 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
1191 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
1192 #phy-cells = <1>;
1193 samsung,pmu-syscon = <&pmu_system_controller>;
1194 status = "disabled";
1195 };
1196
1197 usbhost30: usb@15a00000 {
1198 compatible = "samsung,exynos5250-dwusb3";
1199 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1200 <&cmu_fsys CLK_SCLK_USBHOST30>;
1201 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1202 assigned-clocks =
1203 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
1204 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
1205 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
1206 assigned-clock-parents =
1207 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
1208 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
1209 assigned-clock-rates = <0>, <0>, <66700000>;
1210 #address-cells = <1>;
1211 #size-cells = <1>;
1212 ranges;
1213 status = "disabled";
1214
1215 usbdrd_dwc3_0: dwc3@15a00000 {
1216 compatible = "snps,dwc3";
1217 reg = <0x15a00000 0x10000>;
1218 interrupts = <GIC_SPI 244 0>;
1219 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1220 phy-names = "usb2-phy", "usb3-phy";
1221 };
1222 };
1223
1224 mshc_0: mshc@15540000 {
1225 compatible = "samsung,exynos7-dw-mshc-smu";
1226 interrupts = <GIC_SPI 225 0>;
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229 reg = <0x15540000 0x2000>;
1230 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1231 <&cmu_fsys CLK_SCLK_MMC0>;
1232 clock-names = "biu", "ciu";
1233 fifo-depth = <0x40>;
1234 status = "disabled";
1235 };
1236
1237 mshc_1: mshc@15550000 {
1238 compatible = "samsung,exynos7-dw-mshc-smu";
1239 interrupts = <GIC_SPI 226 0>;
1240 #address-cells = <1>;
1241 #size-cells = <0>;
1242 reg = <0x15550000 0x2000>;
1243 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1244 <&cmu_fsys CLK_SCLK_MMC1>;
1245 clock-names = "biu", "ciu";
1246 fifo-depth = <0x40>;
1247 status = "disabled";
1248 };
1249
1250 mshc_2: mshc@15560000 {
1251 compatible = "samsung,exynos7-dw-mshc-smu";
1252 interrupts = <GIC_SPI 227 0>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1255 reg = <0x15560000 0x2000>;
1256 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1257 <&cmu_fsys CLK_SCLK_MMC2>;
1258 clock-names = "biu", "ciu";
1259 fifo-depth = <0x40>;
1260 status = "disabled";
1261 };
1262
1263 amba {
1264 compatible = "arm,amba-bus";
1265 #address-cells = <1>;
1266 #size-cells = <1>;
1267 ranges;
1268
1269 pdma0: pdma@15610000 {
1270 compatible = "arm,pl330", "arm,primecell";
1271 reg = <0x15610000 0x1000>;
1272 interrupts = <GIC_SPI 228 0>;
1273 clocks = <&cmu_fsys CLK_PDMA0>;
1274 clock-names = "apb_pclk";
1275 #dma-cells = <1>;
1276 #dma-channels = <8>;
1277 #dma-requests = <32>;
1278 };
1279
1280 pdma1: pdma@15600000 {
1281 compatible = "arm,pl330", "arm,primecell";
1282 reg = <0x15600000 0x1000>;
1283 interrupts = <GIC_SPI 246 0>;
1284 clocks = <&cmu_fsys CLK_PDMA1>;
1285 clock-names = "apb_pclk";
1286 #dma-cells = <1>;
1287 #dma-channels = <8>;
1288 #dma-requests = <32>;
1289 };
1290 };
1291
1292 audio-subsystem@11400000 {
1293 compatible = "samsung,exynos5433-lpass";
1294 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1295 samsung,pmu-syscon = <&pmu_system_controller>;
1296 #address-cells = <1>;
1297 #size-cells = <1>;
1298 ranges;
1299
1300 adma: adma@11420000 {
1301 compatible = "arm,pl330", "arm,primecell";
1302 reg = <0x11420000 0x1000>;
1303 interrupts = <GIC_SPI 73 0>;
1304 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1305 clock-names = "apb_pclk";
1306 #dma-cells = <1>;
1307 #dma-channels = <8>;
1308 #dma-requests = <32>;
1309 };
1310
1311 i2s0: i2s0@11440000 {
1312 compatible = "samsung,exynos7-i2s";
1313 reg = <0x11440000 0x100>;
1314 dmas = <&adma 0 &adma 2>;
1315 dma-names = "tx", "rx";
1316 interrupts = <GIC_SPI 70 0>;
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1319 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1320 <&cmu_aud CLK_SCLK_AUD_I2S>,
1321 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1322 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&i2s0_bus>;
1325 status = "disabled";
1326 };
1327
1328 serial_3: serial@11460000 {
1329 compatible = "samsung,exynos5433-uart";
1330 reg = <0x11460000 0x100>;
1331 interrupts = <GIC_SPI 67 0>;
1332 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1333 <&cmu_aud CLK_SCLK_AUD_UART>;
1334 clock-names = "uart", "clk_uart_baud0";
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&uart_aud_bus>;
1337 status = "disabled";
1338 };
1339 };
1340 };
1341
1342 timer: timer {
1343 compatible = "arm,armv8-timer";
1344 interrupts = <GIC_PPI 13
1345 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1346 <GIC_PPI 14
1347 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1348 <GIC_PPI 11
1349 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1350 <GIC_PPI 10
1351 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1352 };
1353};
1354
1355#include "exynos5433-pinctrl.dtsi"
1356#include "exynos5433-tmu.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 12:13:15 -0400