Merge tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

 - An addition of separate driver for the Exynos 4412 ISP CMU, needed
   to model and properly handle the clock controller's dependencies
   on the ISP power domain.
 - Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
   resume} ops to suppress compiler warnings with CONFIG_PM disabled.

* tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Add a separate driver for Exynos4412 ISP clocks
  clk: samsung: Add dt bindings for Exynos4412 ISP clock controller
  clk: samsung: Instantiate Exynos4412 ISP clocks only when available
  clk: samsung: exynos5433: mark PM functions as __maybe_unused

6 files changed, 284 insertions, 9 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index f5a5b19ed3b2..bc61c952cb0b 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -41,3 +41,46 @@ Example 2: UART controller node that consumes the clock generated by the clock
                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
                 clock-names = "uart", "clk_uart_baud0";
         };
+
+Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
+subsystem. Registers for those clocks are located in the ISP power domain.
+Because those registers are also located in a different memory region than
+the main clock controller, a separate clock controller has to be defined for
+handling them.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos4412-isp-clock".
+
+- reg: physical base address of the ISP clock controller and length of memory
+  mapped region.
+
+- #clock-cells: should be 1.
+
+- clocks: list of the clock controller input clock identifiers,
+  from common clock bindings, should point to CLK_ACLK200 and
+  CLK_ACLK400_MCUISP clocks from the main clock controller.
+
+- clock-names: list of the clock controller input clock names,
+  as described in clock-bindings.txt, should be "aclk200" and
+  "aclk400_mcuisp".
+
+- power-domains: a phandle to ISP power domain node as described by
+  generic PM domain bindings.
+
+Example 3: The clock controllers bindings for Exynos4412 SoCs.
+
+        clock: clock-controller@10030000 {
+                compatible = "samsung,exynos4412-clock";
+                reg = <0x10030000 0x18000>;
+                #clock-cells = <1>;
+        };
+
+        isp_clock: clock-controller@10048000 {
+                compatible = "samsung,exynos4412-isp-clock";
+                reg = <0x10048000 0x1000>;
+                #clock-cells = <1>;
+                power-domains = <&pd_isp>;
+                clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
+                clock-names = "aclk200", "aclk400_mcuisp";
+        };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 7afc21dc374e..8a67a3bb6803 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_COMMON_CLK)        += clk.o clk-pll.o clk-cpu.o
 obj-$(CONFIG_SOC_EXYNOS3250)    += clk-exynos3250.o
 obj-$(CONFIG_ARCH_EXYNOS4)      += clk-exynos4.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += clk-exynos4412-isp.o
 obj-$(CONFIG_SOC_EXYNOS5250)    += clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5260)    += clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5410)    += clk-exynos5410.o
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index f452abc6a702..134f25f2a913 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -836,6 +836,12 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
         DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
         DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
         DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
+        DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
+        DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
+        DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
+};
+
+static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
         DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
                                                 CLK_GET_RATE_NOCACHE, 0),
         DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
@@ -845,9 +851,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
                                                 4, 3, CLK_GET_RATE_NOCACHE, 0),
         DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
                                                 8, 3, CLK_GET_RATE_NOCACHE, 0),
-        DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
-        DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
-        DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
 };
 
 /* list of gate clocks supported in all exynos4 soc's */
@@ -1141,6 +1144,13 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
                         0, 0),
         GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
                         0, 0),
+        GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
+        GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
+        GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
+                0),
+};
+
+static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
         GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
                         CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
         GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
@@ -1193,10 +1203,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
                         CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
         GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
                         CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
-        GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
-        GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
-        GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
-                0),
 };
 
 /*
@@ -1497,6 +1503,8 @@ static void __init exynos4_clk_init(struct device_node *np,
                         e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
                         CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
         } else {
+                struct resource res;
+
                 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
                         ARRAY_SIZE(exynos4x12_mux_clks));
                 samsung_clk_register_div(ctx, exynos4x12_div_clks,
@@ -1506,6 +1514,15 @@ static void __init exynos4_clk_init(struct device_node *np,
                 samsung_clk_register_fixed_factor(ctx,
                         exynos4x12_fixed_factor_clks,
                         ARRAY_SIZE(exynos4x12_fixed_factor_clks));
+
+                of_address_to_resource(np, 0, &res);
+                if (resource_size(&res) > 0x18000) {
+                        samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
+                                ARRAY_SIZE(exynos4x12_isp_div_clks));
+                        samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
+                                ARRAY_SIZE(exynos4x12_isp_gate_clks));
+                }
+
                 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
                         mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
                         e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c
new file mode 100644
index 000000000000..d5f1ccb36300
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4412-isp.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2017 Samsung Electronics Co., Ltd.
+ * Author: Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos4412 ISP module.
+*/
+
+#include <dt-bindings/clock/exynos4.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "clk.h"
+
+/* Exynos4x12 specific registers, which belong to ISP power domain */
+#define E4X12_DIV_ISP0          0x0300
+#define E4X12_DIV_ISP1          0x0304
+#define E4X12_GATE_ISP0         0x0800
+#define E4X12_GATE_ISP1         0x0804
+
+/*
+ * Support for CMU save/restore across system suspends
+ */
+static struct samsung_clk_reg_dump *exynos4x12_save_isp;
+
+static const unsigned long exynos4x12_clk_isp_save[] __initconst = {
+        E4X12_DIV_ISP0,
+        E4X12_DIV_ISP1,
+        E4X12_GATE_ISP0,
+        E4X12_GATE_ISP1,
+};
+
+PNAME(mout_user_aclk400_mcuisp_p4x12) = { "fin_pll", "div_aclk400_mcuisp", };
+
+static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
+        DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
+        DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
+        DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp",
+            E4X12_DIV_ISP1, 4, 3),
+        DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0",
+            E4X12_DIV_ISP1, 8, 3),
+        DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
+};
+
+static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
+        GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
+        GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
+        GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
+        GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
+        GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
+        GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
+        GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0),
+        GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0),
+        GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0),
+        GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0),
+        GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
+             0, 0),
+        GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
+             0, 0),
+        GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
+             0, 0),
+        GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
+             0, 0),
+        GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
+             0, 0),
+        GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
+             0, 0),
+        GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
+             0, 0),
+        GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
+             0, 0),
+        GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
+             0, 0),
+        GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0),
+        GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0),
+        GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
+             0, 0),
+        GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
+             0, 0),
+        GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
+             0, 0),
+        GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
+             0, 0),
+        GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
+             0, 0),
+};
+
+static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev)
+{
+        struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
+
+        samsung_clk_save(ctx->reg_base, exynos4x12_save_isp,
+                         ARRAY_SIZE(exynos4x12_clk_isp_save));
+        return 0;
+}
+
+static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev)
+{
+        struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
+
+        samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp,
+                            ARRAY_SIZE(exynos4x12_clk_isp_save));
+        return 0;
+}
+
+static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
+{
+        struct samsung_clk_provider *ctx;
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct resource *res;
+        void __iomem *reg_base;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        reg_base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(reg_base)) {
+                dev_err(dev, "failed to map registers\n");
+                return PTR_ERR(reg_base);
+        }
+
+        exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
+                                        ARRAY_SIZE(exynos4x12_clk_isp_save));
+        if (!exynos4x12_save_isp)
+                return -ENOMEM;
+
+        ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS);
+        ctx->dev = dev;
+
+        platform_set_drvdata(pdev, ctx);
+
+        pm_runtime_set_active(dev);
+        pm_runtime_enable(dev);
+        pm_runtime_get_sync(dev);
+
+        samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
+                                 ARRAY_SIZE(exynos4x12_isp_div_clks));
+        samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
+                                  ARRAY_SIZE(exynos4x12_isp_gate_clks));
+
+        samsung_clk_of_add_provider(np, ctx);
+        pm_runtime_put(dev);
+
+        return 0;
+}
+
+static const struct of_device_id exynos4x12_isp_clk_of_match[] = {
+        { .compatible = "samsung,exynos4412-isp-clock", },
+        { },
+};
+
+static const struct dev_pm_ops exynos4x12_isp_pm_ops = {
+        SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend,
+                           exynos4x12_isp_clk_resume, NULL)
+        SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+                                     pm_runtime_force_resume)
+};
+
+static struct platform_driver exynos4x12_isp_clk_driver __refdata = {
+        .driver = {
+                .name = "exynos4x12-isp-clk",
+                .of_match_table = exynos4x12_isp_clk_of_match,
+                .suppress_bind_attrs = true,
+                .pm = &exynos4x12_isp_pm_ops,
+        },
+        .probe = exynos4x12_isp_clk_probe,
+};
+
+static int __init exynos4x12_isp_clk_init(void)
+{
+        return platform_driver_register(&exynos4x12_isp_clk_driver);
+}
+core_initcall(exynos4x12_isp_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index cd9337613dd8..db270908037a 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -5450,7 +5450,7 @@ struct exynos5433_cmu_data {
         struct samsung_clk_provider ctx;
 };
 
-static int exynos5433_cmu_suspend(struct device *dev)
+static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
 {
         struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
         int i;
@@ -5473,7 +5473,7 @@ static int exynos5433_cmu_suspend(struct device *dev)
         return 0;
 }
 
-static int exynos5433_cmu_resume(struct device *dev)
+static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
 {
         struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
         int i;
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index c40111f36d5e..e9f9d400c322 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -272,4 +272,39 @@
 /* must be greater than maximal clock id */
 #define CLK_NR_CLKS             461
 
+/* Exynos4x12 ISP clocks */
+#define CLK_ISP_FIMC_ISP                 1
+#define CLK_ISP_FIMC_DRC                 2
+#define CLK_ISP_FIMC_FD                  3
+#define CLK_ISP_FIMC_LITE0               4
+#define CLK_ISP_FIMC_LITE1               5
+#define CLK_ISP_MCUISP                   6
+#define CLK_ISP_GICISP                   7
+#define CLK_ISP_SMMU_ISP                 8
+#define CLK_ISP_SMMU_DRC                 9
+#define CLK_ISP_SMMU_FD                 10
+#define CLK_ISP_SMMU_LITE0              11
+#define CLK_ISP_SMMU_LITE1              12
+#define CLK_ISP_PPMUISPMX               13
+#define CLK_ISP_PPMUISPX                14
+#define CLK_ISP_MCUCTL_ISP              15
+#define CLK_ISP_MPWM_ISP                16
+#define CLK_ISP_I2C0_ISP                17
+#define CLK_ISP_I2C1_ISP                18
+#define CLK_ISP_MTCADC_ISP              19
+#define CLK_ISP_PWM_ISP                 20
+#define CLK_ISP_WDT_ISP                 21
+#define CLK_ISP_UART_ISP                22
+#define CLK_ISP_ASYNCAXIM               23
+#define CLK_ISP_SMMU_ISPCX              24
+#define CLK_ISP_SPI0_ISP                25
+#define CLK_ISP_SPI1_ISP                26
+
+#define CLK_ISP_DIV_ISP0                27
+#define CLK_ISP_DIV_ISP1                28
+#define CLK_ISP_DIV_MCUISP0             29
+#define CLK_ISP_DIV_MCUISP1             30
+
+#define CLK_NR_ISP_CLKS                 31
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */