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authorJiang Liu <jiang.liu@linux.intel.com>2015-04-13 22:29:43 -0400
committerThomas Gleixner <tglx@linutronix.de>2015-04-24 09:36:52 -0400
commitad66e1efc95e548598b032c1fe5bbc34f6460547 (patch)
tree8be83ff18b205ec9a9b52e3f148bebe5d9e76d00
parentaa5cb97f14a2dd5aefabed6538c35ebc087d7c24 (diff)
x86/irq: Remove x86_io_apic_ops.eoi_ioapic_pin and related interfaces
Now there is no user of x86_io_apic_ops.eoi_ioapic_pin anymore, so remove it. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Tested-by: Joerg Roedel <jroedel@suse.de> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: iommu@lists.linux-foundation.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Grant Likely <grant.likely@linaro.org> Link: http://lkml.kernel.org/r/1428978610-28986-7-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r--arch/x86/include/asm/io_apic.h7
-rw-r--r--arch/x86/include/asm/x86_init.h1
-rw-r--r--arch/x86/kernel/apic/io_apic.c20
-rw-r--r--arch/x86/kernel/x86_init.c1
-rw-r--r--drivers/iommu/irq_remapping.c19
5 files changed, 4 insertions, 44 deletions
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 0ff68daa9949..fa4b25ebd658 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -150,10 +150,6 @@ struct irq_cfg;
150extern void ioapic_insert_resources(void); 150extern void ioapic_insert_resources(void);
151extern int arch_early_ioapic_init(void); 151extern int arch_early_ioapic_init(void);
152 152
153extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);
154
155extern void native_eoi_ioapic_pin(int apic, int pin, int vector);
156
157extern int save_ioapic_entries(void); 153extern int save_ioapic_entries(void);
158extern void mask_ioapic_entries(void); 154extern void mask_ioapic_entries(void);
159extern int restore_ioapic_entries(void); 155extern int restore_ioapic_entries(void);
@@ -237,8 +233,6 @@ static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned
237 x86_io_apic_ops.modify(apic, reg, value); 233 x86_io_apic_ops.modify(apic, reg, value);
238} 234}
239 235
240extern void io_apic_eoi(unsigned int apic, unsigned int vector);
241
242extern void setup_IO_APIC(void); 236extern void setup_IO_APIC(void);
243extern void enable_IO_APIC(void); 237extern void enable_IO_APIC(void);
244extern void disable_IO_APIC(void); 238extern void disable_IO_APIC(void);
@@ -282,7 +276,6 @@ static inline void disable_ioapic_support(void) { }
282#define native_io_apic_write NULL 276#define native_io_apic_write NULL
283#define native_io_apic_modify NULL 277#define native_io_apic_modify NULL
284#define native_disable_io_apic NULL 278#define native_disable_io_apic NULL
285#define native_eoi_ioapic_pin NULL
286 279
287static inline void setup_IO_APIC(void) { } 280static inline void setup_IO_APIC(void) { }
288static inline void enable_IO_APIC(void) { } 281static inline void enable_IO_APIC(void) { }
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index f9f83cfabcaa..4ada3d3a0e86 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -191,7 +191,6 @@ struct x86_io_apic_ops {
191 void (*write) (unsigned int apic, unsigned int reg, unsigned int value); 191 void (*write) (unsigned int apic, unsigned int reg, unsigned int value);
192 void (*modify) (unsigned int apic, unsigned int reg, unsigned int value); 192 void (*modify) (unsigned int apic, unsigned int reg, unsigned int value);
193 void (*disable)(void); 193 void (*disable)(void);
194 void (*eoi_ioapic_pin)(int apic, int pin, int vector);
195}; 194};
196 195
197extern struct x86_init_ops x86_init; 196extern struct x86_init_ops x86_init;
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 9ef964512b86..998fefad820e 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -271,7 +271,7 @@ static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
271 + (mpc_ioapic_addr(idx) & ~PAGE_MASK); 271 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
272} 272}
273 273
274void io_apic_eoi(unsigned int apic, unsigned int vector) 274static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
275{ 275{
276 struct io_apic __iomem *io_apic = io_apic_base(apic); 276 struct io_apic __iomem *io_apic = io_apic_base(apic);
277 writel(vector, &io_apic->eoi); 277 writel(vector, &io_apic->eoi);
@@ -527,7 +527,7 @@ static void unmask_ioapic_irq(struct irq_data *data)
527 * Otherwise, we simulate the EOI message manually by changing the trigger 527 * Otherwise, we simulate the EOI message manually by changing the trigger
528 * mode to edge and then back to level, with RTE being masked during this. 528 * mode to edge and then back to level, with RTE being masked during this.
529 */ 529 */
530void native_eoi_ioapic_pin(int apic, int pin, int vector) 530static void __eoi_ioapic_pin(int apic, int pin, int vector)
531{ 531{
532 if (mpc_ioapic_ver(apic) >= 0x20) { 532 if (mpc_ioapic_ver(apic) >= 0x20) {
533 io_apic_eoi(apic, vector); 533 io_apic_eoi(apic, vector);
@@ -558,19 +558,7 @@ void eoi_ioapic_pin(int vector, struct irq_cfg *cfg)
558 558
559 raw_spin_lock_irqsave(&ioapic_lock, flags); 559 raw_spin_lock_irqsave(&ioapic_lock, flags);
560 for_each_irq_pin(entry, cfg->irq_2_pin) 560 for_each_irq_pin(entry, cfg->irq_2_pin)
561 native_eoi_ioapic_pin(entry->apic, entry->pin, vector); 561 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
562 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
563}
564
565void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
566{
567 struct irq_pin_list *entry;
568 unsigned long flags;
569
570 raw_spin_lock_irqsave(&ioapic_lock, flags);
571 for_each_irq_pin(entry, cfg->irq_2_pin)
572 x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
573 cfg->vector);
574 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 562 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
575} 563}
576 564
@@ -606,7 +594,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
606 ioapic_write_entry(apic, pin, entry); 594 ioapic_write_entry(apic, pin, entry);
607 } 595 }
608 raw_spin_lock_irqsave(&ioapic_lock, flags); 596 raw_spin_lock_irqsave(&ioapic_lock, flags);
609 native_eoi_ioapic_pin(apic, pin, entry.vector); 597 __eoi_ioapic_pin(apic, pin, entry.vector);
610 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 598 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
611 } 599 }
612 600
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index f7e8eab3a7c4..f612dc018fb6 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -144,5 +144,4 @@ struct x86_io_apic_ops x86_io_apic_ops = {
144 .write = native_io_apic_write, 144 .write = native_io_apic_write,
145 .modify = native_io_apic_modify, 145 .modify = native_io_apic_modify,
146 .disable = native_disable_io_apic, 146 .disable = native_disable_io_apic,
147 .eoi_ioapic_pin = native_eoi_ioapic_pin,
148}; 147};
diff --git a/drivers/iommu/irq_remapping.c b/drivers/iommu/irq_remapping.c
index 7baa54a13921..bca42550b1ad 100644
--- a/drivers/iommu/irq_remapping.c
+++ b/drivers/iommu/irq_remapping.c
@@ -43,21 +43,9 @@ static void irq_remapping_disable_io_apic(void)
43 disconnect_bsp_APIC(0); 43 disconnect_bsp_APIC(0);
44} 44}
45 45
46static void eoi_ioapic_pin_remapped(int apic, int pin, int vector)
47{
48 /*
49 * Intr-remapping uses pin number as the virtual vector
50 * in the RTE. Actual vector is programmed in
51 * intr-remapping table entry. Hence for the io-apic
52 * EOI we use the pin number.
53 */
54 io_apic_eoi(apic, pin);
55}
56
57static void __init irq_remapping_modify_x86_ops(void) 46static void __init irq_remapping_modify_x86_ops(void)
58{ 47{
59 x86_io_apic_ops.disable = irq_remapping_disable_io_apic; 48 x86_io_apic_ops.disable = irq_remapping_disable_io_apic;
60 x86_io_apic_ops.eoi_ioapic_pin = eoi_ioapic_pin_remapped;
61} 49}
62 50
63static __init int setup_nointremap(char *str) 51static __init int setup_nointremap(char *str)
@@ -171,12 +159,6 @@ void ir_ack_apic_edge(struct irq_data *data)
171 ack_APIC_irq(); 159 ack_APIC_irq();
172} 160}
173 161
174static void ir_ack_apic_level(struct irq_data *data)
175{
176 ack_APIC_irq();
177 eoi_ioapic_irq(data->irq, irqd_cfg(data));
178}
179
180static void ir_print_prefix(struct irq_data *data, struct seq_file *p) 162static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
181{ 163{
182 seq_printf(p, " IR-%s", data->chip->name); 164 seq_printf(p, " IR-%s", data->chip->name);
@@ -186,7 +168,6 @@ void irq_remap_modify_chip_defaults(struct irq_chip *chip)
186{ 168{
187 chip->irq_print_chip = ir_print_prefix; 169 chip->irq_print_chip = ir_print_prefix;
188 chip->irq_ack = ir_ack_apic_edge; 170 chip->irq_ack = ir_ack_apic_edge;
189 chip->irq_eoi = ir_ack_apic_level;
190} 171}
191 172
192bool setup_remapped_irq(int irq, struct irq_cfg *cfg, struct irq_chip *chip) 173bool setup_remapped_irq(int irq, struct irq_cfg *cfg, struct irq_chip *chip)