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authorLinus Torvalds <torvalds@linux-foundation.org>2017-11-15 17:54:53 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2017-11-15 17:54:53 -0500
commitad0835a93008e5901415a0a27847d6a27649aa3a (patch)
treee48be396ebfbb4f1fb02e7ca76461bdb1427490d
parent22714a2ba4b55737cd7d5299db7aaf1fa8287354 (diff)
parent4190b4e96954e2c3597021d29435c3f8db8d3129 (diff)
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
Pull rdma updates from Doug Ledford: "This is a fairly plain pull request. Lots of driver updates across the stack, a huge number of static analysis cleanups including a close to 50 patch series from Bart Van Assche, and a number of new features inside the stack such as general CQ moderation support. Nothing really stands out, but there might be a few conflicts as you take things in. In particular, the cleanups touched some of the same lines as the new timer_setup changes. Everything in this pull request has been through 0day and at least two days of linux-next (since Stephen doesn't necessarily flag new errors/warnings until day2). A few more items (about 30 patches) from Intel and Mellanox showed up on the list on Tuesday. I've excluded those from this pull request, and I'm sure some of them qualify as fixes suitable to send any time, but I still have to review them fully. If they contain mostly fixes and little or no new development, then I will probably send them through by the end of the week just to get them out of the way. There was a break in my acceptance of patches which coincides with the computer problems I had, and then when I got things mostly back under control I had a backlog of patches to process, which I did mostly last Friday and Monday. So there is a larger number of patches processed in that timeframe than I was striving for. Summary: - Add iWARP support to qedr driver - Lots of misc fixes across subsystem - Multiple update series to hns roce driver - Multiple update series to hfi1 driver - Updates to vnic driver - Add kref to wait struct in cxgb4 driver - Updates to i40iw driver - Mellanox shared pull request - timer_setup changes - massive cleanup series from Bart Van Assche - Two series of SRP/SRPT changes from Bart Van Assche - Core updates from Mellanox - i40iw updates - IPoIB updates - mlx5 updates - mlx4 updates - hns updates - bnxt_re fixes - PCI write padding support - Sparse/Smatch/warning cleanups/fixes - CQ moderation support - SRQ support in vmw_pvrdma" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma: (296 commits) RDMA/core: Rename kernel modify_cq to better describe its usage IB/mlx5: Add CQ moderation capability to query_device IB/mlx4: Add CQ moderation capability to query_device IB/uverbs: Add CQ moderation capability to query_device IB/mlx5: Exposing modify CQ callback to uverbs layer IB/mlx4: Exposing modify CQ callback to uverbs layer IB/uverbs: Allow CQ moderation with modify CQ iw_cxgb4: atomically flush the qp iw_cxgb4: only call the cq comp_handler when the cq is armed iw_cxgb4: Fix possible circular dependency locking warning RDMA/bnxt_re: report vlan_id and sl in qp1 recv completion IB/core: Only maintain real QPs in the security lists IB/ocrdma_hw: remove unnecessary code in ocrdma_mbx_dealloc_lkey RDMA/core: Make function rdma_copy_addr return void RDMA/vmw_pvrdma: Add shared receive queue support RDMA/core: avoid uninitialized variable warning in create_udata RDMA/bnxt_re: synchronize poll_cq and req_notify_cq verbs RDMA/bnxt_re: Flush CQ notification Work Queue before destroying QP RDMA/bnxt_re: Set QP state in case of response completion errors RDMA/bnxt_re: Add memory barriers when processing CQ/EQ entries ...
-rw-r--r--MAINTAINERS3
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-rw-r--r--drivers/infiniband/core/Makefile2
-rw-r--r--drivers/infiniband/core/addr.c29
-rw-r--r--drivers/infiniband/core/cm.c38
-rw-r--r--drivers/infiniband/core/cma.c19
-rw-r--r--drivers/infiniband/core/iwcm.c3
-rw-r--r--drivers/infiniband/core/mad.c3
-rw-r--r--drivers/infiniband/core/rw.c24
-rw-r--r--drivers/infiniband/core/security.c66
-rw-r--r--drivers/infiniband/core/sysfs.c16
-rw-r--r--drivers/infiniband/core/umem_odp.c72
-rw-r--r--drivers/infiniband/core/umem_rbtree.c109
-rw-r--r--drivers/infiniband/core/user_mad.c13
-rw-r--r--drivers/infiniband/core/uverbs.h36
-rw-r--r--drivers/infiniband/core/uverbs_cmd.c189
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-rw-r--r--drivers/infiniband/core/uverbs_std_types.c20
-rw-r--r--drivers/infiniband/core/verbs.c52
-rw-r--r--drivers/infiniband/hw/bnxt_re/ib_verbs.c78
-rw-r--r--drivers/infiniband/hw/bnxt_re/main.c19
-rw-r--r--drivers/infiniband/hw/bnxt_re/qplib_fp.c39
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-rw-r--r--drivers/infiniband/hw/bnxt_re/roce_hsi.h2
-rw-r--r--drivers/infiniband/hw/cxgb3/Kconfig2
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-rw-r--r--drivers/infiniband/hw/cxgb4/cq.c127
-rw-r--r--drivers/infiniband/hw/cxgb4/device.c69
-rw-r--r--drivers/infiniband/hw/cxgb4/ev.c10
-rw-r--r--drivers/infiniband/hw/cxgb4/id_table.c1
-rw-r--r--drivers/infiniband/hw/cxgb4/iw_cxgb4.h95
-rw-r--r--drivers/infiniband/hw/cxgb4/mem.c268
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-rw-r--r--drivers/infiniband/hw/cxgb4/qp.c186
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-rw-r--r--drivers/infiniband/hw/cxgb4/t4fw_ri_api.h4
-rw-r--r--drivers/infiniband/hw/hfi1/aspm.h7
-rw-r--r--drivers/infiniband/hw/hfi1/chip.c385
-rw-r--r--drivers/infiniband/hw/hfi1/chip.h6
-rw-r--r--drivers/infiniband/hw/hfi1/common.h1
-rw-r--r--drivers/infiniband/hw/hfi1/debugfs.c60
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-rw-r--r--drivers/infiniband/hw/hfi1/hfi.h35
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-rw-r--r--drivers/infiniband/hw/hfi1/ruc.c11
-rw-r--r--drivers/infiniband/hw/hfi1/sdma.c36
-rw-r--r--drivers/infiniband/hw/hfi1/sysfs.c2
-rw-r--r--drivers/infiniband/hw/hfi1/trace.c27
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-rw-r--r--drivers/infiniband/hw/hfi1/uc.c3
-rw-r--r--drivers/infiniband/hw/hfi1/ud.c8
-rw-r--r--drivers/infiniband/hw/hfi1/user_exp_rcv.c9
-rw-r--r--drivers/infiniband/hw/hfi1/user_sdma.c92
-rw-r--r--drivers/infiniband/hw/hfi1/user_sdma.h29
-rw-r--r--drivers/infiniband/hw/hfi1/verbs.c65
-rw-r--r--drivers/infiniband/hw/hfi1/verbs_txreq.h2
-rw-r--r--drivers/infiniband/hw/hfi1/vnic_main.c44
-rw-r--r--drivers/infiniband/hw/hns/Kconfig25
-rw-r--r--drivers/infiniband/hw/hns/Makefile8
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_ah.c16
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_alloc.c35
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_cmd.c107
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-rw-r--r--drivers/infiniband/hw/hns/hns_roce_common.h23
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_cq.c95
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_device.h134
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_eq.c6
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_hem.c719
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_hem.h33
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_hw_v1.c609
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-rw-r--r--drivers/infiniband/hw/hns/hns_roce_hw_v2.c3296
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-rw-r--r--drivers/infiniband/hw/hns/hns_roce_main.c384
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_mr.c692
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_pd.c20
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_qp.c226
-rw-r--r--drivers/infiniband/hw/i40iw/Kconfig1
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-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_user.h23
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-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_verbs.c47
-rw-r--r--drivers/infiniband/hw/mlx4/ah.c8
-rw-r--r--drivers/infiniband/hw/mlx4/cq.c10
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-rw-r--r--drivers/infiniband/hw/mlx4/mr.c284
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-rw-r--r--drivers/infiniband/hw/mlx5/cq.c38
-rw-r--r--drivers/infiniband/hw/mlx5/main.c57
-rw-r--r--drivers/infiniband/hw/mlx5/mlx5_ib.h18
-rw-r--r--drivers/infiniband/hw/mlx5/mr.c4
-rw-r--r--drivers/infiniband/hw/mlx5/odp.c6
-rw-r--r--drivers/infiniband/hw/mlx5/qp.c149
-rw-r--r--drivers/infiniband/hw/mthca/mthca_main.c10
-rw-r--r--drivers/infiniband/hw/nes/nes.c33
-rw-r--r--drivers/infiniband/hw/nes/nes.h6
-rw-r--r--drivers/infiniband/hw/nes/nes_cm.c14
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.c27
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.h1
-rw-r--r--drivers/infiniband/hw/nes/nes_mgt.c9
-rw-r--r--drivers/infiniband/hw/nes/nes_nic.c12
-rw-r--r--drivers/infiniband/hw/nes/nes_utils.c24
-rw-r--r--drivers/infiniband/hw/nes/nes_verbs.c22
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_ah.c15
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_hw.c14
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_stats.c2
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_verbs.c4
-rw-r--r--drivers/infiniband/hw/qedr/Kconfig1
-rw-r--r--drivers/infiniband/hw/qedr/Makefile2
-rw-r--r--drivers/infiniband/hw/qedr/main.c118
-rw-r--r--drivers/infiniband/hw/qedr/qedr.h31
-rw-r--r--drivers/infiniband/hw/qedr/qedr_hsi_rdma.h6
-rw-r--r--drivers/infiniband/hw/qedr/qedr_iw_cm.c749
-rw-r--r--drivers/infiniband/hw/qedr/qedr_iw_cm.h49
-rw-r--r--drivers/infiniband/hw/qedr/qedr_roce_cm.c (renamed from drivers/infiniband/hw/qedr/qedr_cm.c)31
-rw-r--r--drivers/infiniband/hw/qedr/qedr_roce_cm.h (renamed from drivers/infiniband/hw/qedr/qedr_cm.h)0
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-rw-r--r--drivers/infiniband/hw/qib/qib.h30
-rw-r--r--drivers/infiniband/hw/qib/qib_7220.h2
-rw-r--r--drivers/infiniband/hw/qib/qib_diag.c6
-rw-r--r--drivers/infiniband/hw/qib/qib_driver.c9
-rw-r--r--drivers/infiniband/hw/qib/qib_file_ops.c9
-rw-r--r--drivers/infiniband/hw/qib/qib_iba6120.c81
-rw-r--r--drivers/infiniband/hw/qib/qib_iba7220.c95
-rw-r--r--drivers/infiniband/hw/qib/qib_iba7322.c196
-rw-r--r--drivers/infiniband/hw/qib/qib_init.c29
-rw-r--r--drivers/infiniband/hw/qib/qib_intr.c6
-rw-r--r--drivers/infiniband/hw/qib/qib_mad.c16
-rw-r--r--drivers/infiniband/hw/qib/qib_pcie.c128
-rw-r--r--drivers/infiniband/hw/qib/qib_rc.c2
-rw-r--r--drivers/infiniband/hw/qib/qib_sd7220.c12
-rw-r--r--drivers/infiniband/hw/qib/qib_sdma.c2
-rw-r--r--drivers/infiniband/hw/qib/qib_tx.c8
-rw-r--r--drivers/infiniband/hw/qib/qib_verbs.c9
-rw-r--r--drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c2
-rw-r--r--drivers/infiniband/hw/usnic/usnic_ib_qp_grp.h25
-rw-r--r--drivers/infiniband/hw/usnic/usnic_ib_sysfs.c1
-rw-r--r--drivers/infiniband/hw/usnic/usnic_ib_verbs.c25
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/Makefile2
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma.h25
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h54
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c59
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c55
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c319
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c3
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h18
-rw-r--r--drivers/infiniband/sw/rdmavt/Kconfig1
-rw-r--r--drivers/infiniband/sw/rdmavt/mcast.c2
-rw-r--r--drivers/infiniband/sw/rdmavt/qp.c13
-rw-r--r--drivers/infiniband/sw/rxe/rxe_comp.c8
-rw-r--r--drivers/infiniband/sw/rxe/rxe_loc.h4
-rw-r--r--drivers/infiniband/sw/rxe/rxe_pool.c16
-rw-r--r--drivers/infiniband/sw/rxe/rxe_qp.c4
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-rw-r--r--drivers/infiniband/sw/rxe/rxe_task.c2
-rw-r--r--drivers/infiniband/sw/rxe/rxe_verbs.c11
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib.h16
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_cm.c56
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_ethtool.c5
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_ib.c135
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_main.c29
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_verbs.c17
-rw-r--r--drivers/infiniband/ulp/iser/iser_verbs.c2
-rw-r--r--drivers/infiniband/ulp/isert/ib_isert.c14
-rw-r--r--drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c42
-rw-r--r--drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.h22
-rw-r--r--drivers/infiniband/ulp/opa_vnic/opa_vnic_internal.h7
-rw-r--r--drivers/infiniband/ulp/opa_vnic/opa_vnic_netdev.c44
-rw-r--r--drivers/infiniband/ulp/opa_vnic/opa_vnic_vema.c1
-rw-r--r--drivers/infiniband/ulp/opa_vnic/opa_vnic_vema_iface.c22
-rw-r--r--drivers/infiniband/ulp/srp/ib_srp.c90
-rw-r--r--drivers/infiniband/ulp/srp/ib_srp.h3
-rw-r--r--drivers/infiniband/ulp/srpt/ib_srpt.c331
-rw-r--r--drivers/infiniband/ulp/srpt/ib_srpt.h9
-rw-r--r--drivers/net/ethernet/chelsio/cxgb3/t3cdev.h2
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/catas.c8
-rw-r--r--drivers/staging/lustre/lnet/Kconfig2
-rw-r--r--include/linux/mlx4/cq.h3
-rw-r--r--include/linux/mlx5/cq.h9
-rw-r--r--include/linux/mlx5/mlx5_ifc.h9
-rw-r--r--include/rdma/ib_addr.h16
-rw-r--r--include/rdma/ib_pack.h19
-rw-r--r--include/rdma/ib_sa.h12
-rw-r--r--include/rdma/ib_umem_odp.h4
-rw-r--r--include/rdma/ib_verbs.h35
-rw-r--r--include/rdma/opa_addr.h6
-rw-r--r--include/rdma/rdmavt_qp.h6
-rw-r--r--include/uapi/rdma/ib_user_verbs.h22
-rw-r--r--include/uapi/rdma/mlx5-abi.h52
-rw-r--r--include/uapi/rdma/vmw_pvrdma-abi.h2
231 files changed, 12878 insertions, 3733 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index a74d6a738864..bde9686ffb58 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6805,8 +6805,6 @@ F: drivers/ipack/
6805 6805
6806INFINIBAND SUBSYSTEM 6806INFINIBAND SUBSYSTEM
6807M: Doug Ledford <dledford@redhat.com> 6807M: Doug Ledford <dledford@redhat.com>
6808M: Sean Hefty <sean.hefty@intel.com>
6809M: Hal Rosenstock <hal.rosenstock@gmail.com>
6810L: linux-rdma@vger.kernel.org 6808L: linux-rdma@vger.kernel.org
6811W: http://www.openfabrics.org/ 6809W: http://www.openfabrics.org/
6812Q: http://patchwork.kernel.org/project/linux-rdma/list/ 6810Q: http://patchwork.kernel.org/project/linux-rdma/list/
@@ -11116,6 +11114,7 @@ F: drivers/net/ethernet/qlogic/qede/
11116 11114
11117QLOGIC QL4xxx RDMA DRIVER 11115QLOGIC QL4xxx RDMA DRIVER
11118M: Ram Amrani <Ram.Amrani@cavium.com> 11116M: Ram Amrani <Ram.Amrani@cavium.com>
11117M: Michal Kalderon <Michal.Kalderon@cavium.com>
11119M: Ariel Elior <Ariel.Elior@cavium.com> 11118M: Ariel Elior <Ariel.Elior@cavium.com>
11120L: linux-rdma@vger.kernel.org 11119L: linux-rdma@vger.kernel.org
11121S: Supported 11120S: Supported
diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig
index 3726205c8704..98ac46ed7214 100644
--- a/drivers/infiniband/Kconfig
+++ b/drivers/infiniband/Kconfig
@@ -1,6 +1,5 @@
1menuconfig INFINIBAND 1menuconfig INFINIBAND
2 tristate "InfiniBand support" 2 tristate "InfiniBand support"
3 depends on PCI || BROKEN
4 depends on HAS_IOMEM 3 depends on HAS_IOMEM
5 depends on NET 4 depends on NET
6 depends on INET 5 depends on INET
@@ -46,6 +45,7 @@ config INFINIBAND_EXP_USER_ACCESS
46config INFINIBAND_USER_MEM 45config INFINIBAND_USER_MEM
47 bool 46 bool
48 depends on INFINIBAND_USER_ACCESS != n 47 depends on INFINIBAND_USER_ACCESS != n
48 depends on MMU
49 default y 49 default y
50 50
51config INFINIBAND_ON_DEMAND_PAGING 51config INFINIBAND_ON_DEMAND_PAGING
diff --git a/drivers/infiniband/core/Makefile b/drivers/infiniband/core/Makefile
index 9c0a2b5c834e..504b926552c6 100644
--- a/drivers/infiniband/core/Makefile
+++ b/drivers/infiniband/core/Makefile
@@ -15,7 +15,7 @@ ib_core-y := packer.o ud_header.o verbs.o cq.o rw.o sysfs.o \
15 security.o nldev.o 15 security.o nldev.o
16 16
17ib_core-$(CONFIG_INFINIBAND_USER_MEM) += umem.o 17ib_core-$(CONFIG_INFINIBAND_USER_MEM) += umem.o
18ib_core-$(CONFIG_INFINIBAND_ON_DEMAND_PAGING) += umem_odp.o umem_rbtree.o 18ib_core-$(CONFIG_INFINIBAND_ON_DEMAND_PAGING) += umem_odp.o
19ib_core-$(CONFIG_CGROUP_RDMA) += cgroup.o 19ib_core-$(CONFIG_CGROUP_RDMA) += cgroup.o
20 20
21ib_cm-y := cm.o 21ib_cm-y := cm.o
diff --git a/drivers/infiniband/core/addr.c b/drivers/infiniband/core/addr.c
index 12523f630b61..f4e8185bccd3 100644
--- a/drivers/infiniband/core/addr.c
+++ b/drivers/infiniband/core/addr.c
@@ -229,8 +229,9 @@ void rdma_addr_unregister_client(struct rdma_addr_client *client)
229} 229}
230EXPORT_SYMBOL(rdma_addr_unregister_client); 230EXPORT_SYMBOL(rdma_addr_unregister_client);
231 231
232int rdma_copy_addr(struct rdma_dev_addr *dev_addr, struct net_device *dev, 232void rdma_copy_addr(struct rdma_dev_addr *dev_addr,
233 const unsigned char *dst_dev_addr) 233 const struct net_device *dev,
234 const unsigned char *dst_dev_addr)
234{ 235{
235 dev_addr->dev_type = dev->type; 236 dev_addr->dev_type = dev->type;
236 memcpy(dev_addr->src_dev_addr, dev->dev_addr, MAX_ADDR_LEN); 237 memcpy(dev_addr->src_dev_addr, dev->dev_addr, MAX_ADDR_LEN);
@@ -238,7 +239,6 @@ int rdma_copy_addr(struct rdma_dev_addr *dev_addr, struct net_device *dev,
238 if (dst_dev_addr) 239 if (dst_dev_addr)
239 memcpy(dev_addr->dst_dev_addr, dst_dev_addr, MAX_ADDR_LEN); 240 memcpy(dev_addr->dst_dev_addr, dst_dev_addr, MAX_ADDR_LEN);
240 dev_addr->bound_dev_if = dev->ifindex; 241 dev_addr->bound_dev_if = dev->ifindex;
241 return 0;
242} 242}
243EXPORT_SYMBOL(rdma_copy_addr); 243EXPORT_SYMBOL(rdma_copy_addr);
244 244
@@ -247,15 +247,14 @@ int rdma_translate_ip(const struct sockaddr *addr,
247 u16 *vlan_id) 247 u16 *vlan_id)
248{ 248{
249 struct net_device *dev; 249 struct net_device *dev;
250 int ret = -EADDRNOTAVAIL;
251 250
252 if (dev_addr->bound_dev_if) { 251 if (dev_addr->bound_dev_if) {
253 dev = dev_get_by_index(dev_addr->net, dev_addr->bound_dev_if); 252 dev = dev_get_by_index(dev_addr->net, dev_addr->bound_dev_if);
254 if (!dev) 253 if (!dev)
255 return -ENODEV; 254 return -ENODEV;
256 ret = rdma_copy_addr(dev_addr, dev, NULL); 255 rdma_copy_addr(dev_addr, dev, NULL);
257 dev_put(dev); 256 dev_put(dev);
258 return ret; 257 return 0;
259 } 258 }
260 259
261 switch (addr->sa_family) { 260 switch (addr->sa_family) {
@@ -264,9 +263,9 @@ int rdma_translate_ip(const struct sockaddr *addr,
264 ((const struct sockaddr_in *)addr)->sin_addr.s_addr); 263 ((const struct sockaddr_in *)addr)->sin_addr.s_addr);
265 264
266 if (!dev) 265 if (!dev)
267 return ret; 266 return -EADDRNOTAVAIL;
268 267
269 ret = rdma_copy_addr(dev_addr, dev, NULL); 268 rdma_copy_addr(dev_addr, dev, NULL);
270 dev_addr->bound_dev_if = dev->ifindex; 269 dev_addr->bound_dev_if = dev->ifindex;
271 if (vlan_id) 270 if (vlan_id)
272 *vlan_id = rdma_vlan_dev_vlan_id(dev); 271 *vlan_id = rdma_vlan_dev_vlan_id(dev);
@@ -279,7 +278,7 @@ int rdma_translate_ip(const struct sockaddr *addr,
279 if (ipv6_chk_addr(dev_addr->net, 278 if (ipv6_chk_addr(dev_addr->net,
280 &((const struct sockaddr_in6 *)addr)->sin6_addr, 279 &((const struct sockaddr_in6 *)addr)->sin6_addr,
281 dev, 1)) { 280 dev, 1)) {
282 ret = rdma_copy_addr(dev_addr, dev, NULL); 281 rdma_copy_addr(dev_addr, dev, NULL);
283 dev_addr->bound_dev_if = dev->ifindex; 282 dev_addr->bound_dev_if = dev->ifindex;
284 if (vlan_id) 283 if (vlan_id)
285 *vlan_id = rdma_vlan_dev_vlan_id(dev); 284 *vlan_id = rdma_vlan_dev_vlan_id(dev);
@@ -290,7 +289,7 @@ int rdma_translate_ip(const struct sockaddr *addr,
290 break; 289 break;
291#endif 290#endif
292 } 291 }
293 return ret; 292 return 0;
294} 293}
295EXPORT_SYMBOL(rdma_translate_ip); 294EXPORT_SYMBOL(rdma_translate_ip);
296 295
@@ -336,7 +335,7 @@ static int dst_fetch_ha(struct dst_entry *dst, struct rdma_dev_addr *dev_addr,
336 const void *daddr) 335 const void *daddr)
337{ 336{
338 struct neighbour *n; 337 struct neighbour *n;
339 int ret; 338 int ret = 0;
340 339
341 n = dst_neigh_lookup(dst, daddr); 340 n = dst_neigh_lookup(dst, daddr);
342 341
@@ -346,7 +345,7 @@ static int dst_fetch_ha(struct dst_entry *dst, struct rdma_dev_addr *dev_addr,
346 neigh_event_send(n, NULL); 345 neigh_event_send(n, NULL);
347 ret = -ENODATA; 346 ret = -ENODATA;
348 } else { 347 } else {
349 ret = rdma_copy_addr(dev_addr, dst->dev, n->ha); 348 rdma_copy_addr(dev_addr, dst->dev, n->ha);
350 } 349 }
351 rcu_read_unlock(); 350 rcu_read_unlock();
352 351
@@ -494,7 +493,9 @@ static int addr_resolve_neigh(struct dst_entry *dst,
494 if (!(dst->dev->flags & IFF_NOARP)) 493 if (!(dst->dev->flags & IFF_NOARP))
495 return fetch_ha(dst, addr, dst_in, seq); 494 return fetch_ha(dst, addr, dst_in, seq);
496 495
497 return rdma_copy_addr(addr, dst->dev, NULL); 496 rdma_copy_addr(addr, dst->dev, NULL);
497
498 return 0;
498} 499}
499 500
500static int addr_resolve(struct sockaddr *src_in, 501static int addr_resolve(struct sockaddr *src_in,
@@ -852,7 +853,7 @@ static struct notifier_block nb = {
852 853
853int addr_init(void) 854int addr_init(void)
854{ 855{
855 addr_wq = alloc_ordered_workqueue("ib_addr", WQ_MEM_RECLAIM); 856 addr_wq = alloc_ordered_workqueue("ib_addr", 0);
856 if (!addr_wq) 857 if (!addr_wq)
857 return -ENOMEM; 858 return -ENOMEM;
858 859
diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c
index 4c4b46586af2..f6b159d79977 100644
--- a/drivers/infiniband/core/cm.c
+++ b/drivers/infiniband/core/cm.c
@@ -1472,31 +1472,29 @@ static void cm_format_path_lid_from_req(struct cm_req_msg *req_msg,
1472 1472
1473 if (primary_path->rec_type != SA_PATH_REC_TYPE_OPA) { 1473 if (primary_path->rec_type != SA_PATH_REC_TYPE_OPA) {
1474 sa_path_set_dlid(primary_path, 1474 sa_path_set_dlid(primary_path,
1475 htonl(ntohs(req_msg->primary_local_lid))); 1475 ntohs(req_msg->primary_local_lid));
1476 sa_path_set_slid(primary_path, 1476 sa_path_set_slid(primary_path,
1477 htonl(ntohs(req_msg->primary_remote_lid))); 1477 ntohs(req_msg->primary_remote_lid));
1478 } else { 1478 } else {
1479 lid = opa_get_lid_from_gid(&req_msg->primary_local_gid); 1479 lid = opa_get_lid_from_gid(&req_msg->primary_local_gid);
1480 sa_path_set_dlid(primary_path, cpu_to_be32(lid)); 1480 sa_path_set_dlid(primary_path, lid);
1481 1481
1482 lid = opa_get_lid_from_gid(&req_msg->primary_remote_gid); 1482 lid = opa_get_lid_from_gid(&req_msg->primary_remote_gid);
1483 sa_path_set_slid(primary_path, cpu_to_be32(lid)); 1483 sa_path_set_slid(primary_path, lid);
1484 } 1484 }
1485 1485
1486 if (!cm_req_has_alt_path(req_msg)) 1486 if (!cm_req_has_alt_path(req_msg))
1487 return; 1487 return;
1488 1488
1489 if (alt_path->rec_type != SA_PATH_REC_TYPE_OPA) { 1489 if (alt_path->rec_type != SA_PATH_REC_TYPE_OPA) {
1490 sa_path_set_dlid(alt_path, 1490 sa_path_set_dlid(alt_path, ntohs(req_msg->alt_local_lid));
1491 htonl(ntohs(req_msg->alt_local_lid))); 1491 sa_path_set_slid(alt_path, ntohs(req_msg->alt_remote_lid));
1492 sa_path_set_slid(alt_path,
1493 htonl(ntohs(req_msg->alt_remote_lid)));
1494 } else { 1492 } else {
1495 lid = opa_get_lid_from_gid(&req_msg->alt_local_gid); 1493 lid = opa_get_lid_from_gid(&req_msg->alt_local_gid);
1496 sa_path_set_dlid(alt_path, cpu_to_be32(lid)); 1494 sa_path_set_dlid(alt_path, lid);
1497 1495
1498 lid = opa_get_lid_from_gid(&req_msg->alt_remote_gid); 1496 lid = opa_get_lid_from_gid(&req_msg->alt_remote_gid);
1499 sa_path_set_slid(alt_path, cpu_to_be32(lid)); 1497 sa_path_set_slid(alt_path, lid);
1500 } 1498 }
1501} 1499}
1502 1500
@@ -1575,7 +1573,7 @@ static void cm_format_req_event(struct cm_work *work,
1575 param->bth_pkey = cm_get_bth_pkey(work); 1573 param->bth_pkey = cm_get_bth_pkey(work);
1576 param->port = cm_id_priv->av.port->port_num; 1574 param->port = cm_id_priv->av.port->port_num;
1577 param->primary_path = &work->path[0]; 1575 param->primary_path = &work->path[0];
1578 if (req_msg->alt_local_lid) 1576 if (cm_req_has_alt_path(req_msg))
1579 param->alternate_path = &work->path[1]; 1577 param->alternate_path = &work->path[1];
1580 else 1578 else
1581 param->alternate_path = NULL; 1579 param->alternate_path = NULL;
@@ -1856,7 +1854,8 @@ static int cm_req_handler(struct cm_work *work)
1856 cm_process_routed_req(req_msg, work->mad_recv_wc->wc); 1854 cm_process_routed_req(req_msg, work->mad_recv_wc->wc);
1857 1855
1858 memset(&work->path[0], 0, sizeof(work->path[0])); 1856 memset(&work->path[0], 0, sizeof(work->path[0]));
1859 memset(&work->path[1], 0, sizeof(work->path[1])); 1857 if (cm_req_has_alt_path(req_msg))
1858 memset(&work->path[1], 0, sizeof(work->path[1]));
1860 grh = rdma_ah_read_grh(&cm_id_priv->av.ah_attr); 1859 grh = rdma_ah_read_grh(&cm_id_priv->av.ah_attr);
1861 ret = ib_get_cached_gid(work->port->cm_dev->ib_device, 1860 ret = ib_get_cached_gid(work->port->cm_dev->ib_device,
1862 work->port->port_num, 1861 work->port->port_num,
@@ -2810,6 +2809,7 @@ int ib_send_cm_mra(struct ib_cm_id *cm_id,
2810 msg_response = CM_MSG_RESPONSE_OTHER; 2809 msg_response = CM_MSG_RESPONSE_OTHER;
2811 break; 2810 break;
2812 } 2811 }
2812 /* fall through */
2813 default: 2813 default:
2814 ret = -EINVAL; 2814 ret = -EINVAL;
2815 goto error1; 2815 goto error1;
@@ -3037,14 +3037,14 @@ static void cm_format_path_lid_from_lap(struct cm_lap_msg *lap_msg,
3037 u32 lid; 3037 u32 lid;
3038 3038
3039 if (path->rec_type != SA_PATH_REC_TYPE_OPA) { 3039 if (path->rec_type != SA_PATH_REC_TYPE_OPA) {
3040 sa_path_set_dlid(path, htonl(ntohs(lap_msg->alt_local_lid))); 3040 sa_path_set_dlid(path, ntohs(lap_msg->alt_local_lid));
3041 sa_path_set_slid(path, htonl(ntohs(lap_msg->alt_remote_lid))); 3041 sa_path_set_slid(path, ntohs(lap_msg->alt_remote_lid));
3042 } else { 3042 } else {
3043 lid = opa_get_lid_from_gid(&lap_msg->alt_local_gid); 3043 lid = opa_get_lid_from_gid(&lap_msg->alt_local_gid);
3044 sa_path_set_dlid(path, cpu_to_be32(lid)); 3044 sa_path_set_dlid(path, lid);
3045 3045
3046 lid = opa_get_lid_from_gid(&lap_msg->alt_remote_gid); 3046 lid = opa_get_lid_from_gid(&lap_msg->alt_remote_gid);
3047 sa_path_set_slid(path, cpu_to_be32(lid)); 3047 sa_path_set_slid(path, lid);
3048 } 3048 }
3049} 3049}
3050 3050
@@ -3817,14 +3817,16 @@ static void cm_recv_handler(struct ib_mad_agent *mad_agent,
3817 struct cm_port *port = mad_agent->context; 3817 struct cm_port *port = mad_agent->context;
3818 struct cm_work *work; 3818 struct cm_work *work;
3819 enum ib_cm_event_type event; 3819 enum ib_cm_event_type event;
3820 bool alt_path = false;
3820 u16 attr_id; 3821 u16 attr_id;
3821 int paths = 0; 3822 int paths = 0;
3822 int going_down = 0; 3823 int going_down = 0;
3823 3824
3824 switch (mad_recv_wc->recv_buf.mad->mad_hdr.attr_id) { 3825 switch (mad_recv_wc->recv_buf.mad->mad_hdr.attr_id) {
3825 case CM_REQ_ATTR_ID: 3826 case CM_REQ_ATTR_ID:
3826 paths = 1 + (((struct cm_req_msg *) mad_recv_wc->recv_buf.mad)-> 3827 alt_path = cm_req_has_alt_path((struct cm_req_msg *)
3827 alt_local_lid != 0); 3828 mad_recv_wc->recv_buf.mad);
3829 paths = 1 + (alt_path != 0);
3828 event = IB_CM_REQ_RECEIVED; 3830 event = IB_CM_REQ_RECEIVED;
3829 break; 3831 break;
3830 case CM_MRA_ATTR_ID: 3832 case CM_MRA_ATTR_ID:
diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c
index 852c8fec8088..1fdb473b5df7 100644
--- a/drivers/infiniband/core/cma.c
+++ b/drivers/infiniband/core/cma.c
@@ -1540,7 +1540,7 @@ static struct rdma_id_private *cma_id_from_event(struct ib_cm_id *cm_id,
1540 return id_priv; 1540 return id_priv;
1541} 1541}
1542 1542
1543static inline int cma_user_data_offset(struct rdma_id_private *id_priv) 1543static inline u8 cma_user_data_offset(struct rdma_id_private *id_priv)
1544{ 1544{
1545 return cma_family(id_priv) == AF_IB ? 0 : sizeof(struct cma_hdr); 1545 return cma_family(id_priv) == AF_IB ? 0 : sizeof(struct cma_hdr);
1546} 1546}
@@ -1846,9 +1846,7 @@ static struct rdma_id_private *cma_new_conn_id(struct rdma_cm_id *listen_id,
1846 rt->path_rec[1] = *ib_event->param.req_rcvd.alternate_path; 1846 rt->path_rec[1] = *ib_event->param.req_rcvd.alternate_path;
1847 1847
1848 if (net_dev) { 1848 if (net_dev) {
1849 ret = rdma_copy_addr(&rt->addr.dev_addr, net_dev, NULL); 1849 rdma_copy_addr(&rt->addr.dev_addr, net_dev, NULL);
1850 if (ret)
1851 goto err;
1852 } else { 1850 } else {
1853 if (!cma_protocol_roce(listen_id) && 1851 if (!cma_protocol_roce(listen_id) &&
1854 cma_any_addr(cma_src_addr(id_priv))) { 1852 cma_any_addr(cma_src_addr(id_priv))) {
@@ -1894,9 +1892,7 @@ static struct rdma_id_private *cma_new_udp_id(struct rdma_cm_id *listen_id,
1894 goto err; 1892 goto err;
1895 1893
1896 if (net_dev) { 1894 if (net_dev) {
1897 ret = rdma_copy_addr(&id->route.addr.dev_addr, net_dev, NULL); 1895 rdma_copy_addr(&id->route.addr.dev_addr, net_dev, NULL);
1898 if (ret)
1899 goto err;
1900 } else { 1896 } else {
1901 if (!cma_any_addr(cma_src_addr(id_priv))) { 1897 if (!cma_any_addr(cma_src_addr(id_priv))) {
1902 ret = cma_translate_addr(cma_src_addr(id_priv), 1898 ret = cma_translate_addr(cma_src_addr(id_priv),
@@ -1942,7 +1938,8 @@ static int cma_req_handler(struct ib_cm_id *cm_id, struct ib_cm_event *ib_event)
1942 struct rdma_id_private *listen_id, *conn_id = NULL; 1938 struct rdma_id_private *listen_id, *conn_id = NULL;
1943 struct rdma_cm_event event; 1939 struct rdma_cm_event event;
1944 struct net_device *net_dev; 1940 struct net_device *net_dev;
1945 int offset, ret; 1941 u8 offset;
1942 int ret;
1946 1943
1947 listen_id = cma_id_from_event(cm_id, ib_event, &net_dev); 1944 listen_id = cma_id_from_event(cm_id, ib_event, &net_dev);
1948 if (IS_ERR(listen_id)) 1945 if (IS_ERR(listen_id))
@@ -3440,7 +3437,8 @@ static int cma_resolve_ib_udp(struct rdma_id_private *id_priv,
3440 struct ib_cm_sidr_req_param req; 3437 struct ib_cm_sidr_req_param req;
3441 struct ib_cm_id *id; 3438 struct ib_cm_id *id;
3442 void *private_data; 3439 void *private_data;
3443 int offset, ret; 3440 u8 offset;
3441 int ret;
3444 3442
3445 memset(&req, 0, sizeof req); 3443 memset(&req, 0, sizeof req);
3446 offset = cma_user_data_offset(id_priv); 3444 offset = cma_user_data_offset(id_priv);
@@ -3497,7 +3495,8 @@ static int cma_connect_ib(struct rdma_id_private *id_priv,
3497 struct rdma_route *route; 3495 struct rdma_route *route;
3498 void *private_data; 3496 void *private_data;
3499 struct ib_cm_id *id; 3497 struct ib_cm_id *id;
3500 int offset, ret; 3498 u8 offset;
3499 int ret;
3501 3500
3502 memset(&req, 0, sizeof req); 3501 memset(&req, 0, sizeof req);
3503 offset = cma_user_data_offset(id_priv); 3502 offset = cma_user_data_offset(id_priv);
diff --git a/drivers/infiniband/core/iwcm.c b/drivers/infiniband/core/iwcm.c
index fcf42f6bb82a..e9e189ec7502 100644
--- a/drivers/infiniband/core/iwcm.c
+++ b/drivers/infiniband/core/iwcm.c
@@ -447,9 +447,6 @@ static void destroy_cm_id(struct iw_cm_id *cm_id)
447 */ 447 */
448void iw_destroy_cm_id(struct iw_cm_id *cm_id) 448void iw_destroy_cm_id(struct iw_cm_id *cm_id)
449{ 449{
450 struct iwcm_id_private *cm_id_priv;
451
452 cm_id_priv = container_of(cm_id, struct iwcm_id_private, id);
453 destroy_cm_id(cm_id); 450 destroy_cm_id(cm_id);
454} 451}
455EXPORT_SYMBOL(iw_destroy_cm_id); 452EXPORT_SYMBOL(iw_destroy_cm_id);
diff --git a/drivers/infiniband/core/mad.c b/drivers/infiniband/core/mad.c
index f8f53bb90837..cb91245e9163 100644
--- a/drivers/infiniband/core/mad.c
+++ b/drivers/infiniband/core/mad.c
@@ -1974,14 +1974,15 @@ static void ib_mad_complete_recv(struct ib_mad_agent_private *mad_agent_priv,
1974 unsigned long flags; 1974 unsigned long flags;
1975 int ret; 1975 int ret;
1976 1976
1977 INIT_LIST_HEAD(&mad_recv_wc->rmpp_list);
1977 ret = ib_mad_enforce_security(mad_agent_priv, 1978 ret = ib_mad_enforce_security(mad_agent_priv,
1978 mad_recv_wc->wc->pkey_index); 1979 mad_recv_wc->wc->pkey_index);
1979 if (ret) { 1980 if (ret) {
1980 ib_free_recv_mad(mad_recv_wc); 1981 ib_free_recv_mad(mad_recv_wc);
1981 deref_mad_agent(mad_agent_priv); 1982 deref_mad_agent(mad_agent_priv);
1983 return;
1982 } 1984 }
1983 1985
1984 INIT_LIST_HEAD(&mad_recv_wc->rmpp_list);
1985 list_add(&mad_recv_wc->recv_buf.list, &mad_recv_wc->rmpp_list); 1986 list_add(&mad_recv_wc->recv_buf.list, &mad_recv_wc->rmpp_list);
1986 if (ib_mad_kernel_rmpp_agent(&mad_agent_priv->agent)) { 1987 if (ib_mad_kernel_rmpp_agent(&mad_agent_priv->agent)) {
1987 mad_recv_wc = ib_process_rmpp_recv_wc(mad_agent_priv, 1988 mad_recv_wc = ib_process_rmpp_recv_wc(mad_agent_priv,
diff --git a/drivers/infiniband/core/rw.c b/drivers/infiniband/core/rw.c
index 6ca607e8e293..c8963e91f92a 100644
--- a/drivers/infiniband/core/rw.c
+++ b/drivers/infiniband/core/rw.c
@@ -384,21 +384,17 @@ int rdma_rw_ctx_signature_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
384 count += ret; 384 count += ret;
385 prev_wr = &ctx->sig->data.reg_wr.wr; 385 prev_wr = &ctx->sig->data.reg_wr.wr;
386 386
387 if (prot_sg_cnt) { 387 ret = rdma_rw_init_one_mr(qp, port_num, &ctx->sig->prot,
388 ret = rdma_rw_init_one_mr(qp, port_num, &ctx->sig->prot, 388 prot_sg, prot_sg_cnt, 0);
389 prot_sg, prot_sg_cnt, 0); 389 if (ret < 0)
390 if (ret < 0) 390 goto out_destroy_data_mr;
391 goto out_destroy_data_mr; 391 count += ret;
392 count += ret;
393 392
394 if (ctx->sig->prot.inv_wr.next) 393 if (ctx->sig->prot.inv_wr.next)
395 prev_wr->next = &ctx->sig->prot.inv_wr; 394 prev_wr->next = &ctx->sig->prot.inv_wr;
396 else 395 else
397 prev_wr->next = &ctx->sig->prot.reg_wr.wr; 396 prev_wr->next = &ctx->sig->prot.reg_wr.wr;
398 prev_wr = &ctx->sig->prot.reg_wr.wr; 397 prev_wr = &ctx->sig->prot.reg_wr.wr;
399 } else {
400 ctx->sig->prot.mr = NULL;
401 }
402 398
403 ctx->sig->sig_mr = ib_mr_pool_get(qp, &qp->sig_mrs); 399 ctx->sig->sig_mr = ib_mr_pool_get(qp, &qp->sig_mrs);
404 if (!ctx->sig->sig_mr) { 400 if (!ctx->sig->sig_mr) {
diff --git a/drivers/infiniband/core/security.c b/drivers/infiniband/core/security.c
index 88bdafb297f5..23278ed5be45 100644
--- a/drivers/infiniband/core/security.c
+++ b/drivers/infiniband/core/security.c
@@ -87,16 +87,14 @@ static int enforce_qp_pkey_security(u16 pkey,
87 if (ret) 87 if (ret)
88 return ret; 88 return ret;
89 89
90 if (qp_sec->qp == qp_sec->qp->real_qp) { 90 list_for_each_entry(shared_qp_sec,
91 list_for_each_entry(shared_qp_sec, 91 &qp_sec->shared_qp_list,
92 &qp_sec->shared_qp_list, 92 shared_qp_list) {
93 shared_qp_list) { 93 ret = security_ib_pkey_access(shared_qp_sec->security,
94 ret = security_ib_pkey_access(shared_qp_sec->security, 94 subnet_prefix,
95 subnet_prefix, 95 pkey);
96 pkey); 96 if (ret)
97 if (ret) 97 return ret;
98 return ret;
99 }
100 } 98 }
101 return 0; 99 return 0;
102} 100}
@@ -560,15 +558,22 @@ int ib_security_modify_qp(struct ib_qp *qp,
560 int ret = 0; 558 int ret = 0;
561 struct ib_ports_pkeys *tmp_pps; 559 struct ib_ports_pkeys *tmp_pps;
562 struct ib_ports_pkeys *new_pps; 560 struct ib_ports_pkeys *new_pps;
563 bool special_qp = (qp->qp_type == IB_QPT_SMI || 561 struct ib_qp *real_qp = qp->real_qp;
564 qp->qp_type == IB_QPT_GSI || 562 bool special_qp = (real_qp->qp_type == IB_QPT_SMI ||
565 qp->qp_type >= IB_QPT_RESERVED1); 563 real_qp->qp_type == IB_QPT_GSI ||
564 real_qp->qp_type >= IB_QPT_RESERVED1);
566 bool pps_change = ((qp_attr_mask & (IB_QP_PKEY_INDEX | IB_QP_PORT)) || 565 bool pps_change = ((qp_attr_mask & (IB_QP_PKEY_INDEX | IB_QP_PORT)) ||
567 (qp_attr_mask & IB_QP_ALT_PATH)); 566 (qp_attr_mask & IB_QP_ALT_PATH));
568 567
568 /* The port/pkey settings are maintained only for the real QP. Open
569 * handles on the real QP will be in the shared_qp_list. When
570 * enforcing security on the real QP all the shared QPs will be
571 * checked as well.
572 */
573
569 if (pps_change && !special_qp) { 574 if (pps_change && !special_qp) {
570 mutex_lock(&qp->qp_sec->mutex); 575 mutex_lock(&real_qp->qp_sec->mutex);
571 new_pps = get_new_pps(qp, 576 new_pps = get_new_pps(real_qp,
572 qp_attr, 577 qp_attr,
573 qp_attr_mask); 578 qp_attr_mask);
574 579
@@ -586,14 +591,14 @@ int ib_security_modify_qp(struct ib_qp *qp,
586 591
587 if (!ret) 592 if (!ret)
588 ret = check_qp_port_pkey_settings(new_pps, 593 ret = check_qp_port_pkey_settings(new_pps,
589 qp->qp_sec); 594 real_qp->qp_sec);
590 } 595 }
591 596
592 if (!ret) 597 if (!ret)
593 ret = qp->device->modify_qp(qp->real_qp, 598 ret = real_qp->device->modify_qp(real_qp,
594 qp_attr, 599 qp_attr,
595 qp_attr_mask, 600 qp_attr_mask,
596 udata); 601 udata);
597 602
598 if (pps_change && !special_qp) { 603 if (pps_change && !special_qp) {
599 /* Clean up the lists and free the appropriate 604 /* Clean up the lists and free the appropriate
@@ -602,8 +607,8 @@ int ib_security_modify_qp(struct ib_qp *qp,
602 if (ret) { 607 if (ret) {
603 tmp_pps = new_pps; 608 tmp_pps = new_pps;
604 } else { 609 } else {
605 tmp_pps = qp->qp_sec->ports_pkeys; 610 tmp_pps = real_qp->qp_sec->ports_pkeys;
606 qp->qp_sec->ports_pkeys = new_pps; 611 real_qp->qp_sec->ports_pkeys = new_pps;
607 } 612 }
608 613
609 if (tmp_pps) { 614 if (tmp_pps) {
@@ -611,7 +616,7 @@ int ib_security_modify_qp(struct ib_qp *qp,
611 port_pkey_list_remove(&tmp_pps->alt); 616 port_pkey_list_remove(&tmp_pps->alt);
612 } 617 }
613 kfree(tmp_pps); 618 kfree(tmp_pps);
614 mutex_unlock(&qp->qp_sec->mutex); 619 mutex_unlock(&real_qp->qp_sec->mutex);
615 } 620 }
616 return ret; 621 return ret;
617} 622}
@@ -692,20 +697,13 @@ void ib_mad_agent_security_cleanup(struct ib_mad_agent *agent)
692 697
693int ib_mad_enforce_security(struct ib_mad_agent_private *map, u16 pkey_index) 698int ib_mad_enforce_security(struct ib_mad_agent_private *map, u16 pkey_index)
694{ 699{
695 int ret;
696
697 if (map->agent.qp->qp_type == IB_QPT_SMI && !map->agent.smp_allowed) 700 if (map->agent.qp->qp_type == IB_QPT_SMI && !map->agent.smp_allowed)
698 return -EACCES; 701 return -EACCES;
699 702
700 ret = ib_security_pkey_access(map->agent.device, 703 return ib_security_pkey_access(map->agent.device,
701 map->agent.port_num, 704 map->agent.port_num,
702 pkey_index, 705 pkey_index,
703 map->agent.security); 706 map->agent.security);
704
705 if (ret)
706 return ret;
707
708 return 0;
709} 707}
710 708
711#endif /* CONFIG_SECURITY_INFINIBAND */ 709#endif /* CONFIG_SECURITY_INFINIBAND */
diff --git a/drivers/infiniband/core/sysfs.c b/drivers/infiniband/core/sysfs.c
index abc5ab581f82..e30d86fa1855 100644
--- a/drivers/infiniband/core/sysfs.c
+++ b/drivers/infiniband/core/sysfs.c
@@ -108,8 +108,22 @@ static ssize_t port_attr_show(struct kobject *kobj,
108 return port_attr->show(p, port_attr, buf); 108 return port_attr->show(p, port_attr, buf);
109} 109}
110 110
111static ssize_t port_attr_store(struct kobject *kobj,
112 struct attribute *attr,
113 const char *buf, size_t count)
114{
115 struct port_attribute *port_attr =
116 container_of(attr, struct port_attribute, attr);
117 struct ib_port *p = container_of(kobj, struct ib_port, kobj);
118
119 if (!port_attr->store)
120 return -EIO;
121 return port_attr->store(p, port_attr, buf, count);
122}
123
111static const struct sysfs_ops port_sysfs_ops = { 124static const struct sysfs_ops port_sysfs_ops = {
112 .show = port_attr_show 125 .show = port_attr_show,
126 .store = port_attr_store
113}; 127};
114 128
115static ssize_t gid_attr_show(struct kobject *kobj, 129static ssize_t gid_attr_show(struct kobject *kobj,
diff --git a/drivers/infiniband/core/umem_odp.c b/drivers/infiniband/core/umem_odp.c
index 55e8f5ed8b3c..2aadf5813a40 100644
--- a/drivers/infiniband/core/umem_odp.c
+++ b/drivers/infiniband/core/umem_odp.c
@@ -39,11 +39,44 @@
39#include <linux/export.h> 39#include <linux/export.h>
40#include <linux/vmalloc.h> 40#include <linux/vmalloc.h>
41#include <linux/hugetlb.h> 41#include <linux/hugetlb.h>
42#include <linux/interval_tree_generic.h>
42 43
43#include <rdma/ib_verbs.h> 44#include <rdma/ib_verbs.h>
44#include <rdma/ib_umem.h> 45#include <rdma/ib_umem.h>
45#include <rdma/ib_umem_odp.h> 46#include <rdma/ib_umem_odp.h>
46 47
48/*
49 * The ib_umem list keeps track of memory regions for which the HW
50 * device request to receive notification when the related memory
51 * mapping is changed.
52 *
53 * ib_umem_lock protects the list.
54 */
55
56static u64 node_start(struct umem_odp_node *n)
57{
58 struct ib_umem_odp *umem_odp =
59 container_of(n, struct ib_umem_odp, interval_tree);
60
61 return ib_umem_start(umem_odp->umem);
62}
63
64/* Note that the representation of the intervals in the interval tree
65 * considers the ending point as contained in the interval, while the
66 * function ib_umem_end returns the first address which is not contained
67 * in the umem.
68 */
69static u64 node_last(struct umem_odp_node *n)
70{
71 struct ib_umem_odp *umem_odp =
72 container_of(n, struct ib_umem_odp, interval_tree);
73
74 return ib_umem_end(umem_odp->umem) - 1;
75}
76
77INTERVAL_TREE_DEFINE(struct umem_odp_node, rb, u64, __subtree_last,
78 node_start, node_last, static, rbt_ib_umem)
79
47static void ib_umem_notifier_start_account(struct ib_umem *item) 80static void ib_umem_notifier_start_account(struct ib_umem *item)
48{ 81{
49 mutex_lock(&item->odp_data->umem_mutex); 82 mutex_lock(&item->odp_data->umem_mutex);
@@ -754,3 +787,42 @@ void ib_umem_odp_unmap_dma_pages(struct ib_umem *umem, u64 virt,
754 mutex_unlock(&umem->odp_data->umem_mutex); 787 mutex_unlock(&umem->odp_data->umem_mutex);
755} 788}
756EXPORT_SYMBOL(ib_umem_odp_unmap_dma_pages); 789EXPORT_SYMBOL(ib_umem_odp_unmap_dma_pages);
790
791/* @last is not a part of the interval. See comment for function
792 * node_last.
793 */
794int rbt_ib_umem_for_each_in_range(struct rb_root_cached *root,
795 u64 start, u64 last,
796 umem_call_back cb,
797 void *cookie)
798{
799 int ret_val = 0;
800 struct umem_odp_node *node, *next;
801 struct ib_umem_odp *umem;
802
803 if (unlikely(start == last))
804 return ret_val;
805
806 for (node = rbt_ib_umem_iter_first(root, start, last - 1);
807 node; node = next) {
808 next = rbt_ib_umem_iter_next(node, start, last - 1);
809 umem = container_of(node, struct ib_umem_odp, interval_tree);
810 ret_val = cb(umem->umem, start, last, cookie) || ret_val;
811 }
812
813 return ret_val;
814}
815EXPORT_SYMBOL(rbt_ib_umem_for_each_in_range);
816
817struct ib_umem_odp *rbt_ib_umem_lookup(struct rb_root_cached *root,
818 u64 addr, u64 length)
819{
820 struct umem_odp_node *node;
821
822 node = rbt_ib_umem_iter_first(root, addr, addr + length - 1);
823 if (node)
824 return container_of(node, struct ib_umem_odp, interval_tree);
825 return NULL;
826
827}
828EXPORT_SYMBOL(rbt_ib_umem_lookup);
diff --git a/drivers/infiniband/core/umem_rbtree.c b/drivers/infiniband/core/umem_rbtree.c
deleted file mode 100644
index fc801920e341..000000000000
--- a/drivers/infiniband/core/umem_rbtree.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (c) 2014 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/interval_tree_generic.h>
36#include <linux/sched.h>
37#include <linux/gfp.h>
38#include <rdma/ib_umem_odp.h>
39
40/*
41 * The ib_umem list keeps track of memory regions for which the HW
42 * device request to receive notification when the related memory
43 * mapping is changed.
44 *
45 * ib_umem_lock protects the list.
46 */
47
48static inline u64 node_start(struct umem_odp_node *n)
49{
50 struct ib_umem_odp *umem_odp =
51 container_of(n, struct ib_umem_odp, interval_tree);
52
53 return ib_umem_start(umem_odp->umem);
54}
55
56/* Note that the representation of the intervals in the interval tree
57 * considers the ending point as contained in the interval, while the
58 * function ib_umem_end returns the first address which is not contained
59 * in the umem.
60 */
61static inline u64 node_last(struct umem_odp_node *n)
62{
63 struct ib_umem_odp *umem_odp =
64 container_of(n, struct ib_umem_odp, interval_tree);
65
66 return ib_umem_end(umem_odp->umem) - 1;
67}
68
69INTERVAL_TREE_DEFINE(struct umem_odp_node, rb, u64, __subtree_last,
70 node_start, node_last, , rbt_ib_umem)
71
72/* @last is not a part of the interval. See comment for function
73 * node_last.
74 */
75int rbt_ib_umem_for_each_in_range(struct rb_root_cached *root,
76 u64 start, u64 last,
77 umem_call_back cb,
78 void *cookie)
79{
80 int ret_val = 0;
81 struct umem_odp_node *node, *next;
82 struct ib_umem_odp *umem;
83
84 if (unlikely(start == last))
85 return ret_val;
86
87 for (node = rbt_ib_umem_iter_first(root, start, last - 1);
88 node; node = next) {
89 next = rbt_ib_umem_iter_next(node, start, last - 1);
90 umem = container_of(node, struct ib_umem_odp, interval_tree);
91 ret_val = cb(umem->umem, start, last, cookie) || ret_val;
92 }
93
94 return ret_val;
95}
96EXPORT_SYMBOL(rbt_ib_umem_for_each_in_range);
97
98struct ib_umem_odp *rbt_ib_umem_lookup(struct rb_root_cached *root,
99 u64 addr, u64 length)
100{
101 struct umem_odp_node *node;
102
103 node = rbt_ib_umem_iter_first(root, addr, addr + length - 1);
104 if (node)
105 return container_of(node, struct ib_umem_odp, interval_tree);
106 return NULL;
107
108}
109EXPORT_SYMBOL(rbt_ib_umem_lookup);
diff --git a/drivers/infiniband/core/user_mad.c b/drivers/infiniband/core/user_mad.c
index c1696e6084b2..4b64dd02e090 100644
--- a/drivers/infiniband/core/user_mad.c
+++ b/drivers/infiniband/core/user_mad.c
@@ -229,7 +229,16 @@ static void recv_handler(struct ib_mad_agent *agent,
229 packet->mad.hdr.status = 0; 229 packet->mad.hdr.status = 0;
230 packet->mad.hdr.length = hdr_size(file) + mad_recv_wc->mad_len; 230 packet->mad.hdr.length = hdr_size(file) + mad_recv_wc->mad_len;
231 packet->mad.hdr.qpn = cpu_to_be32(mad_recv_wc->wc->src_qp); 231 packet->mad.hdr.qpn = cpu_to_be32(mad_recv_wc->wc->src_qp);
232 packet->mad.hdr.lid = ib_lid_be16(mad_recv_wc->wc->slid); 232 /*
233 * On OPA devices it is okay to lose the upper 16 bits of LID as this
234 * information is obtained elsewhere. Mask off the upper 16 bits.
235 */
236 if (agent->device->port_immutable[agent->port_num].core_cap_flags &
237 RDMA_CORE_PORT_INTEL_OPA)
238 packet->mad.hdr.lid = ib_lid_be16(0xFFFF &
239 mad_recv_wc->wc->slid);
240 else
241 packet->mad.hdr.lid = ib_lid_be16(mad_recv_wc->wc->slid);
233 packet->mad.hdr.sl = mad_recv_wc->wc->sl; 242 packet->mad.hdr.sl = mad_recv_wc->wc->sl;
234 packet->mad.hdr.path_bits = mad_recv_wc->wc->dlid_path_bits; 243 packet->mad.hdr.path_bits = mad_recv_wc->wc->dlid_path_bits;
235 packet->mad.hdr.pkey_index = mad_recv_wc->wc->pkey_index; 244 packet->mad.hdr.pkey_index = mad_recv_wc->wc->pkey_index;
@@ -506,7 +515,7 @@ static ssize_t ib_umad_write(struct file *filp, const char __user *buf,
506 rdma_ah_set_dgid_raw(&ah_attr, packet->mad.hdr.gid); 515 rdma_ah_set_dgid_raw(&ah_attr, packet->mad.hdr.gid);
507 } 516 }
508 517
509 ah = rdma_create_ah(agent->qp->pd, &ah_attr); 518 ah = rdma_create_user_ah(agent->qp->pd, &ah_attr, NULL);
510 if (IS_ERR(ah)) { 519 if (IS_ERR(ah)) {
511 ret = PTR_ERR(ah); 520 ret = PTR_ERR(ah);
512 goto err_up; 521 goto err_up;
diff --git a/drivers/infiniband/core/uverbs.h b/drivers/infiniband/core/uverbs.h
index 37c8903e7fd0..deccefb71a6b 100644
--- a/drivers/infiniband/core/uverbs.h
+++ b/drivers/infiniband/core/uverbs.h
@@ -47,21 +47,28 @@
47#include <rdma/ib_umem.h> 47#include <rdma/ib_umem.h>
48#include <rdma/ib_user_verbs.h> 48#include <rdma/ib_user_verbs.h>
49 49
50#define INIT_UDATA(udata, ibuf, obuf, ilen, olen) \ 50static inline void
51 do { \ 51ib_uverbs_init_udata(struct ib_udata *udata,
52 (udata)->inbuf = (const void __user *) (ibuf); \ 52 const void __user *ibuf,
53 (udata)->outbuf = (void __user *) (obuf); \ 53 void __user *obuf,
54 (udata)->inlen = (ilen); \ 54 size_t ilen, size_t olen)
55 (udata)->outlen = (olen); \ 55{
56 } while (0) 56 udata->inbuf = ibuf;
57 udata->outbuf = obuf;
58 udata->inlen = ilen;
59 udata->outlen = olen;
60}
57 61
58#define INIT_UDATA_BUF_OR_NULL(udata, ibuf, obuf, ilen, olen) \ 62static inline void
59 do { \ 63ib_uverbs_init_udata_buf_or_null(struct ib_udata *udata,
60 (udata)->inbuf = (ilen) ? (const void __user *) (ibuf) : NULL; \ 64 const void __user *ibuf,
61 (udata)->outbuf = (olen) ? (void __user *) (obuf) : NULL; \ 65 void __user *obuf,
62 (udata)->inlen = (ilen); \ 66 size_t ilen, size_t olen)
63 (udata)->outlen = (olen); \ 67{
64 } while (0) 68 ib_uverbs_init_udata(udata,
69 ilen ? ibuf : NULL, olen ? obuf : NULL,
70 ilen, olen);
71}
65 72
66/* 73/*
67 * Our lifetime rules for these structs are the following: 74 * Our lifetime rules for these structs are the following:
@@ -299,5 +306,6 @@ IB_UVERBS_DECLARE_EX_CMD(destroy_wq);
299IB_UVERBS_DECLARE_EX_CMD(create_rwq_ind_table); 306IB_UVERBS_DECLARE_EX_CMD(create_rwq_ind_table);
300IB_UVERBS_DECLARE_EX_CMD(destroy_rwq_ind_table); 307IB_UVERBS_DECLARE_EX_CMD(destroy_rwq_ind_table);
301IB_UVERBS_DECLARE_EX_CMD(modify_qp); 308IB_UVERBS_DECLARE_EX_CMD(modify_qp);
309IB_UVERBS_DECLARE_EX_CMD(modify_cq);
302 310
303#endif /* UVERBS_H */ 311#endif /* UVERBS_H */
diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c
index 52a2cf2d83aa..16d55710b116 100644
--- a/drivers/infiniband/core/uverbs_cmd.c
+++ b/drivers/infiniband/core/uverbs_cmd.c
@@ -91,8 +91,8 @@ ssize_t ib_uverbs_get_context(struct ib_uverbs_file *file,
91 goto err; 91 goto err;
92 } 92 }
93 93
94 INIT_UDATA(&udata, buf + sizeof(cmd), 94 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
95 (unsigned long) cmd.response + sizeof(resp), 95 u64_to_user_ptr(cmd.response) + sizeof(resp),
96 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 96 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
97 out_len - sizeof(resp)); 97 out_len - sizeof(resp));
98 98
@@ -141,8 +141,7 @@ ssize_t ib_uverbs_get_context(struct ib_uverbs_file *file,
141 goto err_fd; 141 goto err_fd;
142 } 142 }
143 143
144 if (copy_to_user((void __user *) (unsigned long) cmd.response, 144 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp)) {
145 &resp, sizeof resp)) {
146 ret = -EFAULT; 145 ret = -EFAULT;
147 goto err_file; 146 goto err_file;
148 } 147 }
@@ -238,8 +237,7 @@ ssize_t ib_uverbs_query_device(struct ib_uverbs_file *file,
238 memset(&resp, 0, sizeof resp); 237 memset(&resp, 0, sizeof resp);
239 copy_query_dev_fields(file, ib_dev, &resp, &ib_dev->attrs); 238 copy_query_dev_fields(file, ib_dev, &resp, &ib_dev->attrs);
240 239
241 if (copy_to_user((void __user *) (unsigned long) cmd.response, 240 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
242 &resp, sizeof resp))
243 return -EFAULT; 241 return -EFAULT;
244 242
245 return in_len; 243 return in_len;
@@ -295,8 +293,7 @@ ssize_t ib_uverbs_query_port(struct ib_uverbs_file *file,
295 resp.link_layer = rdma_port_get_link_layer(ib_dev, 293 resp.link_layer = rdma_port_get_link_layer(ib_dev,
296 cmd.port_num); 294 cmd.port_num);
297 295
298 if (copy_to_user((void __user *) (unsigned long) cmd.response, 296 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
299 &resp, sizeof resp))
300 return -EFAULT; 297 return -EFAULT;
301 298
302 return in_len; 299 return in_len;
@@ -320,8 +317,8 @@ ssize_t ib_uverbs_alloc_pd(struct ib_uverbs_file *file,
320 if (copy_from_user(&cmd, buf, sizeof cmd)) 317 if (copy_from_user(&cmd, buf, sizeof cmd))
321 return -EFAULT; 318 return -EFAULT;
322 319
323 INIT_UDATA(&udata, buf + sizeof(cmd), 320 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
324 (unsigned long) cmd.response + sizeof(resp), 321 u64_to_user_ptr(cmd.response) + sizeof(resp),
325 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 322 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
326 out_len - sizeof(resp)); 323 out_len - sizeof(resp));
327 324
@@ -344,8 +341,7 @@ ssize_t ib_uverbs_alloc_pd(struct ib_uverbs_file *file,
344 memset(&resp, 0, sizeof resp); 341 memset(&resp, 0, sizeof resp);
345 resp.pd_handle = uobj->id; 342 resp.pd_handle = uobj->id;
346 343
347 if (copy_to_user((void __user *) (unsigned long) cmd.response, 344 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp)) {
348 &resp, sizeof resp)) {
349 ret = -EFAULT; 345 ret = -EFAULT;
350 goto err_copy; 346 goto err_copy;
351 } 347 }
@@ -490,8 +486,8 @@ ssize_t ib_uverbs_open_xrcd(struct ib_uverbs_file *file,
490 if (copy_from_user(&cmd, buf, sizeof cmd)) 486 if (copy_from_user(&cmd, buf, sizeof cmd))
491 return -EFAULT; 487 return -EFAULT;
492 488
493 INIT_UDATA(&udata, buf + sizeof(cmd), 489 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
494 (unsigned long) cmd.response + sizeof(resp), 490 u64_to_user_ptr(cmd.response) + sizeof(resp),
495 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 491 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
496 out_len - sizeof(resp)); 492 out_len - sizeof(resp));
497 493
@@ -556,8 +552,7 @@ ssize_t ib_uverbs_open_xrcd(struct ib_uverbs_file *file,
556 atomic_inc(&xrcd->usecnt); 552 atomic_inc(&xrcd->usecnt);
557 } 553 }
558 554
559 if (copy_to_user((void __user *) (unsigned long) cmd.response, 555 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp)) {
560 &resp, sizeof resp)) {
561 ret = -EFAULT; 556 ret = -EFAULT;
562 goto err_copy; 557 goto err_copy;
563 } 558 }
@@ -655,8 +650,8 @@ ssize_t ib_uverbs_reg_mr(struct ib_uverbs_file *file,
655 if (copy_from_user(&cmd, buf, sizeof cmd)) 650 if (copy_from_user(&cmd, buf, sizeof cmd))
656 return -EFAULT; 651 return -EFAULT;
657 652
658 INIT_UDATA(&udata, buf + sizeof(cmd), 653 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
659 (unsigned long) cmd.response + sizeof(resp), 654 u64_to_user_ptr(cmd.response) + sizeof(resp),
660 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 655 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
661 out_len - sizeof(resp)); 656 out_len - sizeof(resp));
662 657
@@ -705,8 +700,7 @@ ssize_t ib_uverbs_reg_mr(struct ib_uverbs_file *file,
705 resp.rkey = mr->rkey; 700 resp.rkey = mr->rkey;
706 resp.mr_handle = uobj->id; 701 resp.mr_handle = uobj->id;
707 702
708 if (copy_to_user((void __user *) (unsigned long) cmd.response, 703 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp)) {
709 &resp, sizeof resp)) {
710 ret = -EFAULT; 704 ret = -EFAULT;
711 goto err_copy; 705 goto err_copy;
712 } 706 }
@@ -748,8 +742,8 @@ ssize_t ib_uverbs_rereg_mr(struct ib_uverbs_file *file,
748 if (copy_from_user(&cmd, buf, sizeof(cmd))) 742 if (copy_from_user(&cmd, buf, sizeof(cmd)))
749 return -EFAULT; 743 return -EFAULT;
750 744
751 INIT_UDATA(&udata, buf + sizeof(cmd), 745 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
752 (unsigned long) cmd.response + sizeof(resp), 746 u64_to_user_ptr(cmd.response) + sizeof(resp),
753 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 747 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
754 out_len - sizeof(resp)); 748 out_len - sizeof(resp));
755 749
@@ -800,8 +794,7 @@ ssize_t ib_uverbs_rereg_mr(struct ib_uverbs_file *file,
800 resp.lkey = mr->lkey; 794 resp.lkey = mr->lkey;
801 resp.rkey = mr->rkey; 795 resp.rkey = mr->rkey;
802 796
803 if (copy_to_user((void __user *)(unsigned long)cmd.response, 797 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof(resp)))
804 &resp, sizeof(resp)))
805 ret = -EFAULT; 798 ret = -EFAULT;
806 else 799 else
807 ret = in_len; 800 ret = in_len;
@@ -867,8 +860,8 @@ ssize_t ib_uverbs_alloc_mw(struct ib_uverbs_file *file,
867 goto err_free; 860 goto err_free;
868 } 861 }
869 862
870 INIT_UDATA(&udata, buf + sizeof(cmd), 863 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
871 (unsigned long)cmd.response + sizeof(resp), 864 u64_to_user_ptr(cmd.response) + sizeof(resp),
872 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 865 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
873 out_len - sizeof(resp)); 866 out_len - sizeof(resp));
874 867
@@ -889,8 +882,7 @@ ssize_t ib_uverbs_alloc_mw(struct ib_uverbs_file *file,
889 resp.rkey = mw->rkey; 882 resp.rkey = mw->rkey;
890 resp.mw_handle = uobj->id; 883 resp.mw_handle = uobj->id;
891 884
892 if (copy_to_user((void __user *)(unsigned long)cmd.response, 885 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof(resp))) {
893 &resp, sizeof(resp))) {
894 ret = -EFAULT; 886 ret = -EFAULT;
895 goto err_copy; 887 goto err_copy;
896 } 888 }
@@ -956,8 +948,7 @@ ssize_t ib_uverbs_create_comp_channel(struct ib_uverbs_file *file,
956 uobj_file.uobj); 948 uobj_file.uobj);
957 ib_uverbs_init_event_queue(&ev_file->ev_queue); 949 ib_uverbs_init_event_queue(&ev_file->ev_queue);
958 950
959 if (copy_to_user((void __user *) (unsigned long) cmd.response, 951 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp)) {
960 &resp, sizeof resp)) {
961 uobj_alloc_abort(uobj); 952 uobj_alloc_abort(uobj);
962 return -EFAULT; 953 return -EFAULT;
963 } 954 }
@@ -1087,10 +1078,11 @@ ssize_t ib_uverbs_create_cq(struct ib_uverbs_file *file,
1087 if (copy_from_user(&cmd, buf, sizeof(cmd))) 1078 if (copy_from_user(&cmd, buf, sizeof(cmd)))
1088 return -EFAULT; 1079 return -EFAULT;
1089 1080
1090 INIT_UDATA(&ucore, buf, (unsigned long)cmd.response, sizeof(cmd), sizeof(resp)); 1081 ib_uverbs_init_udata(&ucore, buf, u64_to_user_ptr(cmd.response),
1082 sizeof(cmd), sizeof(resp));
1091 1083
1092 INIT_UDATA(&uhw, buf + sizeof(cmd), 1084 ib_uverbs_init_udata(&uhw, buf + sizeof(cmd),
1093 (unsigned long)cmd.response + sizeof(resp), 1085 u64_to_user_ptr(cmd.response) + sizeof(resp),
1094 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 1086 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
1095 out_len - sizeof(resp)); 1087 out_len - sizeof(resp));
1096 1088
@@ -1173,8 +1165,8 @@ ssize_t ib_uverbs_resize_cq(struct ib_uverbs_file *file,
1173 if (copy_from_user(&cmd, buf, sizeof cmd)) 1165 if (copy_from_user(&cmd, buf, sizeof cmd))
1174 return -EFAULT; 1166 return -EFAULT;
1175 1167
1176 INIT_UDATA(&udata, buf + sizeof(cmd), 1168 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
1177 (unsigned long) cmd.response + sizeof(resp), 1169 u64_to_user_ptr(cmd.response) + sizeof(resp),
1178 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 1170 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
1179 out_len - sizeof(resp)); 1171 out_len - sizeof(resp));
1180 1172
@@ -1188,8 +1180,7 @@ ssize_t ib_uverbs_resize_cq(struct ib_uverbs_file *file,
1188 1180
1189 resp.cqe = cq->cqe; 1181 resp.cqe = cq->cqe;
1190 1182
1191 if (copy_to_user((void __user *) (unsigned long) cmd.response, 1183 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp.cqe))
1192 &resp, sizeof resp.cqe))
1193 ret = -EFAULT; 1184 ret = -EFAULT;
1194 1185
1195out: 1186out:
@@ -1249,7 +1240,7 @@ ssize_t ib_uverbs_poll_cq(struct ib_uverbs_file *file,
1249 return -EINVAL; 1240 return -EINVAL;
1250 1241
1251 /* we copy a struct ib_uverbs_poll_cq_resp to user space */ 1242 /* we copy a struct ib_uverbs_poll_cq_resp to user space */
1252 header_ptr = (void __user *)(unsigned long) cmd.response; 1243 header_ptr = u64_to_user_ptr(cmd.response);
1253 data_ptr = header_ptr + sizeof resp; 1244 data_ptr = header_ptr + sizeof resp;
1254 1245
1255 memset(&resp, 0, sizeof resp); 1246 memset(&resp, 0, sizeof resp);
@@ -1343,8 +1334,7 @@ ssize_t ib_uverbs_destroy_cq(struct ib_uverbs_file *file,
1343 resp.async_events_reported = obj->async_events_reported; 1334 resp.async_events_reported = obj->async_events_reported;
1344 1335
1345 uverbs_uobject_put(uobj); 1336 uverbs_uobject_put(uobj);
1346 if (copy_to_user((void __user *) (unsigned long) cmd.response, 1337 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
1347 &resp, sizeof resp))
1348 return -EFAULT; 1338 return -EFAULT;
1349 1339
1350 return in_len; 1340 return in_len;
@@ -1501,7 +1491,8 @@ static int create_qp(struct ib_uverbs_file *file,
1501 IB_QP_CREATE_MANAGED_RECV | 1491 IB_QP_CREATE_MANAGED_RECV |
1502 IB_QP_CREATE_SCATTER_FCS | 1492 IB_QP_CREATE_SCATTER_FCS |
1503 IB_QP_CREATE_CVLAN_STRIPPING | 1493 IB_QP_CREATE_CVLAN_STRIPPING |
1504 IB_QP_CREATE_SOURCE_QPN)) { 1494 IB_QP_CREATE_SOURCE_QPN |
1495 IB_QP_CREATE_PCI_WRITE_END_PADDING)) {
1505 ret = -EINVAL; 1496 ret = -EINVAL;
1506 goto err_put; 1497 goto err_put;
1507 } 1498 }
@@ -1650,10 +1641,10 @@ ssize_t ib_uverbs_create_qp(struct ib_uverbs_file *file,
1650 if (copy_from_user(&cmd, buf, sizeof(cmd))) 1641 if (copy_from_user(&cmd, buf, sizeof(cmd)))
1651 return -EFAULT; 1642 return -EFAULT;
1652 1643
1653 INIT_UDATA(&ucore, buf, (unsigned long)cmd.response, sizeof(cmd), 1644 ib_uverbs_init_udata(&ucore, buf, u64_to_user_ptr(cmd.response),
1654 resp_size); 1645 sizeof(cmd), resp_size);
1655 INIT_UDATA(&uhw, buf + sizeof(cmd), 1646 ib_uverbs_init_udata(&uhw, buf + sizeof(cmd),
1656 (unsigned long)cmd.response + resp_size, 1647 u64_to_user_ptr(cmd.response) + resp_size,
1657 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 1648 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
1658 out_len - resp_size); 1649 out_len - resp_size);
1659 1650
@@ -1750,8 +1741,8 @@ ssize_t ib_uverbs_open_qp(struct ib_uverbs_file *file,
1750 if (copy_from_user(&cmd, buf, sizeof cmd)) 1741 if (copy_from_user(&cmd, buf, sizeof cmd))
1751 return -EFAULT; 1742 return -EFAULT;
1752 1743
1753 INIT_UDATA(&udata, buf + sizeof(cmd), 1744 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
1754 (unsigned long) cmd.response + sizeof(resp), 1745 u64_to_user_ptr(cmd.response) + sizeof(resp),
1755 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 1746 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
1756 out_len - sizeof(resp)); 1747 out_len - sizeof(resp));
1757 1748
@@ -1795,8 +1786,7 @@ ssize_t ib_uverbs_open_qp(struct ib_uverbs_file *file,
1795 resp.qpn = qp->qp_num; 1786 resp.qpn = qp->qp_num;
1796 resp.qp_handle = obj->uevent.uobject.id; 1787 resp.qp_handle = obj->uevent.uobject.id;
1797 1788
1798 if (copy_to_user((void __user *) (unsigned long) cmd.response, 1789 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp)) {
1799 &resp, sizeof resp)) {
1800 ret = -EFAULT; 1790 ret = -EFAULT;
1801 goto err_destroy; 1791 goto err_destroy;
1802 } 1792 }
@@ -1911,8 +1901,7 @@ ssize_t ib_uverbs_query_qp(struct ib_uverbs_file *file,
1911 resp.max_inline_data = init_attr->cap.max_inline_data; 1901 resp.max_inline_data = init_attr->cap.max_inline_data;
1912 resp.sq_sig_all = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1902 resp.sq_sig_all = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR;
1913 1903
1914 if (copy_to_user((void __user *) (unsigned long) cmd.response, 1904 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
1915 &resp, sizeof resp))
1916 ret = -EFAULT; 1905 ret = -EFAULT;
1917 1906
1918out: 1907out:
@@ -2042,7 +2031,7 @@ ssize_t ib_uverbs_modify_qp(struct ib_uverbs_file *file,
2042 ~((IB_USER_LEGACY_LAST_QP_ATTR_MASK << 1) - 1)) 2031 ~((IB_USER_LEGACY_LAST_QP_ATTR_MASK << 1) - 1))
2043 return -EOPNOTSUPP; 2032 return -EOPNOTSUPP;
2044 2033
2045 INIT_UDATA(&udata, buf + sizeof(cmd.base), NULL, 2034 ib_uverbs_init_udata(&udata, buf + sizeof(cmd.base), NULL,
2046 in_len - sizeof(cmd.base) - sizeof(struct ib_uverbs_cmd_hdr), 2035 in_len - sizeof(cmd.base) - sizeof(struct ib_uverbs_cmd_hdr),
2047 out_len); 2036 out_len);
2048 2037
@@ -2126,8 +2115,7 @@ ssize_t ib_uverbs_destroy_qp(struct ib_uverbs_file *file,
2126 resp.events_reported = obj->uevent.events_reported; 2115 resp.events_reported = obj->uevent.events_reported;
2127 uverbs_uobject_put(uobj); 2116 uverbs_uobject_put(uobj);
2128 2117
2129 if (copy_to_user((void __user *) (unsigned long) cmd.response, 2118 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
2130 &resp, sizeof resp))
2131 return -EFAULT; 2119 return -EFAULT;
2132 2120
2133 return in_len; 2121 return in_len;
@@ -2311,8 +2299,7 @@ ssize_t ib_uverbs_post_send(struct ib_uverbs_file *file,
2311 break; 2299 break;
2312 } 2300 }
2313 2301
2314 if (copy_to_user((void __user *) (unsigned long) cmd.response, 2302 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
2315 &resp, sizeof resp))
2316 ret = -EFAULT; 2303 ret = -EFAULT;
2317 2304
2318out_put: 2305out_put:
@@ -2460,8 +2447,7 @@ ssize_t ib_uverbs_post_recv(struct ib_uverbs_file *file,
2460 } 2447 }
2461 } 2448 }
2462 2449
2463 if (copy_to_user((void __user *) (unsigned long) cmd.response, 2450 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
2464 &resp, sizeof resp))
2465 ret = -EFAULT; 2451 ret = -EFAULT;
2466 2452
2467out: 2453out:
@@ -2510,8 +2496,7 @@ ssize_t ib_uverbs_post_srq_recv(struct ib_uverbs_file *file,
2510 break; 2496 break;
2511 } 2497 }
2512 2498
2513 if (copy_to_user((void __user *) (unsigned long) cmd.response, 2499 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
2514 &resp, sizeof resp))
2515 ret = -EFAULT; 2500 ret = -EFAULT;
2516 2501
2517out: 2502out:
@@ -2537,7 +2522,6 @@ ssize_t ib_uverbs_create_ah(struct ib_uverbs_file *file,
2537 struct rdma_ah_attr attr; 2522 struct rdma_ah_attr attr;
2538 int ret; 2523 int ret;
2539 struct ib_udata udata; 2524 struct ib_udata udata;
2540 u8 *dmac;
2541 2525
2542 if (out_len < sizeof resp) 2526 if (out_len < sizeof resp)
2543 return -ENOSPC; 2527 return -ENOSPC;
@@ -2548,8 +2532,8 @@ ssize_t ib_uverbs_create_ah(struct ib_uverbs_file *file,
2548 if (!rdma_is_port_valid(ib_dev, cmd.attr.port_num)) 2532 if (!rdma_is_port_valid(ib_dev, cmd.attr.port_num))
2549 return -EINVAL; 2533 return -EINVAL;
2550 2534
2551 INIT_UDATA(&udata, buf + sizeof(cmd), 2535 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
2552 (unsigned long)cmd.response + sizeof(resp), 2536 u64_to_user_ptr(cmd.response) + sizeof(resp),
2553 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 2537 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
2554 out_len - sizeof(resp)); 2538 out_len - sizeof(resp));
2555 2539
@@ -2580,28 +2564,20 @@ ssize_t ib_uverbs_create_ah(struct ib_uverbs_file *file,
2580 } else { 2564 } else {
2581 rdma_ah_set_ah_flags(&attr, 0); 2565 rdma_ah_set_ah_flags(&attr, 0);
2582 } 2566 }
2583 dmac = rdma_ah_retrieve_dmac(&attr);
2584 if (dmac)
2585 memset(dmac, 0, ETH_ALEN);
2586
2587 ah = pd->device->create_ah(pd, &attr, &udata);
2588 2567
2568 ah = rdma_create_user_ah(pd, &attr, &udata);
2589 if (IS_ERR(ah)) { 2569 if (IS_ERR(ah)) {
2590 ret = PTR_ERR(ah); 2570 ret = PTR_ERR(ah);
2591 goto err_put; 2571 goto err_put;
2592 } 2572 }
2593 2573
2594 ah->device = pd->device;
2595 ah->pd = pd;
2596 atomic_inc(&pd->usecnt);
2597 ah->uobject = uobj; 2574 ah->uobject = uobj;
2598 uobj->user_handle = cmd.user_handle; 2575 uobj->user_handle = cmd.user_handle;
2599 uobj->object = ah; 2576 uobj->object = ah;
2600 2577
2601 resp.ah_handle = uobj->id; 2578 resp.ah_handle = uobj->id;
2602 2579
2603 if (copy_to_user((void __user *) (unsigned long) cmd.response, 2580 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp)) {
2604 &resp, sizeof resp)) {
2605 ret = -EFAULT; 2581 ret = -EFAULT;
2606 goto err_copy; 2582 goto err_copy;
2607 } 2583 }
@@ -3627,8 +3603,8 @@ ssize_t ib_uverbs_create_srq(struct ib_uverbs_file *file,
3627 xcmd.max_sge = cmd.max_sge; 3603 xcmd.max_sge = cmd.max_sge;
3628 xcmd.srq_limit = cmd.srq_limit; 3604 xcmd.srq_limit = cmd.srq_limit;
3629 3605
3630 INIT_UDATA(&udata, buf + sizeof(cmd), 3606 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
3631 (unsigned long) cmd.response + sizeof(resp), 3607 u64_to_user_ptr(cmd.response) + sizeof(resp),
3632 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 3608 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
3633 out_len - sizeof(resp)); 3609 out_len - sizeof(resp));
3634 3610
@@ -3654,8 +3630,8 @@ ssize_t ib_uverbs_create_xsrq(struct ib_uverbs_file *file,
3654 if (copy_from_user(&cmd, buf, sizeof cmd)) 3630 if (copy_from_user(&cmd, buf, sizeof cmd))
3655 return -EFAULT; 3631 return -EFAULT;
3656 3632
3657 INIT_UDATA(&udata, buf + sizeof(cmd), 3633 ib_uverbs_init_udata(&udata, buf + sizeof(cmd),
3658 (unsigned long) cmd.response + sizeof(resp), 3634 u64_to_user_ptr(cmd.response) + sizeof(resp),
3659 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr), 3635 in_len - sizeof(cmd) - sizeof(struct ib_uverbs_cmd_hdr),
3660 out_len - sizeof(resp)); 3636 out_len - sizeof(resp));
3661 3637
@@ -3680,7 +3656,7 @@ ssize_t ib_uverbs_modify_srq(struct ib_uverbs_file *file,
3680 if (copy_from_user(&cmd, buf, sizeof cmd)) 3656 if (copy_from_user(&cmd, buf, sizeof cmd))
3681 return -EFAULT; 3657 return -EFAULT;
3682 3658
3683 INIT_UDATA(&udata, buf + sizeof cmd, NULL, in_len - sizeof cmd, 3659 ib_uverbs_init_udata(&udata, buf + sizeof cmd, NULL, in_len - sizeof cmd,
3684 out_len); 3660 out_len);
3685 3661
3686 srq = uobj_get_obj_read(srq, cmd.srq_handle, file->ucontext); 3662 srq = uobj_get_obj_read(srq, cmd.srq_handle, file->ucontext);
@@ -3731,8 +3707,7 @@ ssize_t ib_uverbs_query_srq(struct ib_uverbs_file *file,
3731 resp.max_sge = attr.max_sge; 3707 resp.max_sge = attr.max_sge;
3732 resp.srq_limit = attr.srq_limit; 3708 resp.srq_limit = attr.srq_limit;
3733 3709
3734 if (copy_to_user((void __user *) (unsigned long) cmd.response, 3710 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof resp))
3735 &resp, sizeof resp))
3736 return -EFAULT; 3711 return -EFAULT;
3737 3712
3738 return in_len; 3713 return in_len;
@@ -3773,8 +3748,7 @@ ssize_t ib_uverbs_destroy_srq(struct ib_uverbs_file *file,
3773 } 3748 }
3774 resp.events_reported = obj->events_reported; 3749 resp.events_reported = obj->events_reported;
3775 uverbs_uobject_put(uobj); 3750 uverbs_uobject_put(uobj);
3776 if (copy_to_user((void __user *)(unsigned long)cmd.response, 3751 if (copy_to_user(u64_to_user_ptr(cmd.response), &resp, sizeof(resp)))
3777 &resp, sizeof(resp)))
3778 return -EFAULT; 3752 return -EFAULT;
3779 3753
3780 return in_len; 3754 return in_len;
@@ -3878,7 +3852,58 @@ int ib_uverbs_ex_query_device(struct ib_uverbs_file *file,
3878 resp.tm_caps.max_sge = attr.tm_caps.max_sge; 3852 resp.tm_caps.max_sge = attr.tm_caps.max_sge;
3879 resp.tm_caps.flags = attr.tm_caps.flags; 3853 resp.tm_caps.flags = attr.tm_caps.flags;
3880 resp.response_length += sizeof(resp.tm_caps); 3854 resp.response_length += sizeof(resp.tm_caps);
3855
3856 if (ucore->outlen < resp.response_length + sizeof(resp.cq_moderation_caps))
3857 goto end;
3858
3859 resp.cq_moderation_caps.max_cq_moderation_count =
3860 attr.cq_caps.max_cq_moderation_count;
3861 resp.cq_moderation_caps.max_cq_moderation_period =
3862 attr.cq_caps.max_cq_moderation_period;
3863 resp.response_length += sizeof(resp.cq_moderation_caps);
3881end: 3864end:
3882 err = ib_copy_to_udata(ucore, &resp, resp.response_length); 3865 err = ib_copy_to_udata(ucore, &resp, resp.response_length);
3883 return err; 3866 return err;
3884} 3867}
3868
3869int ib_uverbs_ex_modify_cq(struct ib_uverbs_file *file,
3870 struct ib_device *ib_dev,
3871 struct ib_udata *ucore,
3872 struct ib_udata *uhw)
3873{
3874 struct ib_uverbs_ex_modify_cq cmd = {};
3875 struct ib_cq *cq;
3876 size_t required_cmd_sz;
3877 int ret;
3878
3879 required_cmd_sz = offsetof(typeof(cmd), reserved) +
3880 sizeof(cmd.reserved);
3881 if (ucore->inlen < required_cmd_sz)
3882 return -EINVAL;
3883
3884 /* sanity checks */
3885 if (ucore->inlen > sizeof(cmd) &&
3886 !ib_is_udata_cleared(ucore, sizeof(cmd),
3887 ucore->inlen - sizeof(cmd)))
3888 return -EOPNOTSUPP;
3889
3890 ret = ib_copy_from_udata(&cmd, ucore, min(sizeof(cmd), ucore->inlen));
3891 if (ret)
3892 return ret;
3893
3894 if (!cmd.attr_mask || cmd.reserved)
3895 return -EINVAL;
3896
3897 if (cmd.attr_mask > IB_CQ_MODERATE)
3898 return -EOPNOTSUPP;
3899
3900 cq = uobj_get_obj_read(cq, cmd.cq_handle, file->ucontext);
3901 if (!cq)
3902 return -EINVAL;
3903
3904 ret = rdma_set_cq_moderation(cq, cmd.attr.cq_count, cmd.attr.cq_period);
3905
3906 uobj_put_obj_read(cq);
3907
3908 return ret;
3909}
diff --git a/drivers/infiniband/core/uverbs_ioctl.c b/drivers/infiniband/core/uverbs_ioctl.c
index 5286ad57d903..71ff2644e053 100644
--- a/drivers/infiniband/core/uverbs_ioctl.c
+++ b/drivers/infiniband/core/uverbs_ioctl.c
@@ -241,9 +241,7 @@ static long ib_uverbs_cmd_verbs(struct ib_device *ib_dev,
241 struct uverbs_attr *curr_attr; 241 struct uverbs_attr *curr_attr;
242 unsigned long *curr_bitmap; 242 unsigned long *curr_bitmap;
243 size_t ctx_size; 243 size_t ctx_size;
244#ifdef UVERBS_OPTIMIZE_USING_STACK_SZ
245 uintptr_t data[UVERBS_OPTIMIZE_USING_STACK_SZ / sizeof(uintptr_t)]; 244 uintptr_t data[UVERBS_OPTIMIZE_USING_STACK_SZ / sizeof(uintptr_t)];
246#endif
247 245
248 if (hdr->reserved) 246 if (hdr->reserved)
249 return -EINVAL; 247 return -EINVAL;
@@ -269,13 +267,10 @@ static long ib_uverbs_cmd_verbs(struct ib_device *ib_dev,
269 (method_spec->num_child_attrs / BITS_PER_LONG + 267 (method_spec->num_child_attrs / BITS_PER_LONG +
270 method_spec->num_buckets); 268 method_spec->num_buckets);
271 269
272#ifdef UVERBS_OPTIMIZE_USING_STACK_SZ
273 if (ctx_size <= UVERBS_OPTIMIZE_USING_STACK_SZ) 270 if (ctx_size <= UVERBS_OPTIMIZE_USING_STACK_SZ)
274 ctx = (void *)data; 271 ctx = (void *)data;
275
276 if (!ctx) 272 if (!ctx)
277#endif 273 ctx = kmalloc(ctx_size, GFP_KERNEL);
278 ctx = kmalloc(ctx_size, GFP_KERNEL);
279 if (!ctx) 274 if (!ctx)
280 return -ENOMEM; 275 return -ENOMEM;
281 276
@@ -311,10 +306,8 @@ static long ib_uverbs_cmd_verbs(struct ib_device *ib_dev,
311 err = uverbs_handle_method(buf, ctx->uattrs, hdr->num_attrs, ib_dev, 306 err = uverbs_handle_method(buf, ctx->uattrs, hdr->num_attrs, ib_dev,
312 file, method_spec, ctx->uverbs_attr_bundle); 307 file, method_spec, ctx->uverbs_attr_bundle);
313out: 308out:
314#ifdef UVERBS_OPTIMIZE_USING_STACK_SZ 309 if (ctx != (void *)data)
315 if (ctx_size > UVERBS_OPTIMIZE_USING_STACK_SZ) 310 kfree(ctx);
316#endif
317 kfree(ctx);
318 return err; 311 return err;
319} 312}
320 313
diff --git a/drivers/infiniband/core/uverbs_ioctl_merge.c b/drivers/infiniband/core/uverbs_ioctl_merge.c
index 76ddb6564578..062485f9300d 100644
--- a/drivers/infiniband/core/uverbs_ioctl_merge.c
+++ b/drivers/infiniband/core/uverbs_ioctl_merge.c
@@ -376,7 +376,7 @@ static struct uverbs_method_spec *build_method_with_attrs(const struct uverbs_me
376 min_id) || 376 min_id) ||
377 WARN(attr_obj_with_special_access && 377 WARN(attr_obj_with_special_access &&
378 !(attr->flags & UVERBS_ATTR_SPEC_F_MANDATORY), 378 !(attr->flags & UVERBS_ATTR_SPEC_F_MANDATORY),
379 "ib_uverbs: Tried to merge attr (%d) but it's an object with new/destroy aceess but isn't mandatory\n", 379 "ib_uverbs: Tried to merge attr (%d) but it's an object with new/destroy access but isn't mandatory\n",
380 min_id) || 380 min_id) ||
381 WARN(IS_ATTR_OBJECT(attr) && 381 WARN(IS_ATTR_OBJECT(attr) &&
382 attr->flags & UVERBS_ATTR_SPEC_F_MIN_SZ, 382 attr->flags & UVERBS_ATTR_SPEC_F_MIN_SZ,
diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c
index dc2aed6fb21b..381fd9c096ae 100644
--- a/drivers/infiniband/core/uverbs_main.c
+++ b/drivers/infiniband/core/uverbs_main.c
@@ -128,6 +128,7 @@ static int (*uverbs_ex_cmd_table[])(struct ib_uverbs_file *file,
128 [IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL] = ib_uverbs_ex_create_rwq_ind_table, 128 [IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL] = ib_uverbs_ex_create_rwq_ind_table,
129 [IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL] = ib_uverbs_ex_destroy_rwq_ind_table, 129 [IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL] = ib_uverbs_ex_destroy_rwq_ind_table,
130 [IB_USER_VERBS_EX_CMD_MODIFY_QP] = ib_uverbs_ex_modify_qp, 130 [IB_USER_VERBS_EX_CMD_MODIFY_QP] = ib_uverbs_ex_modify_qp,
131 [IB_USER_VERBS_EX_CMD_MODIFY_CQ] = ib_uverbs_ex_modify_cq,
131}; 132};
132 133
133static void ib_uverbs_add_one(struct ib_device *device); 134static void ib_uverbs_add_one(struct ib_device *device);
@@ -763,7 +764,7 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
763 } 764 }
764 765
765 if (!access_ok(VERIFY_WRITE, 766 if (!access_ok(VERIFY_WRITE,
766 (void __user *) (unsigned long) ex_hdr.response, 767 u64_to_user_ptr(ex_hdr.response),
767 (hdr.out_words + ex_hdr.provider_out_words) * 8)) { 768 (hdr.out_words + ex_hdr.provider_out_words) * 8)) {
768 ret = -EFAULT; 769 ret = -EFAULT;
769 goto out; 770 goto out;
@@ -775,19 +776,17 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
775 } 776 }
776 } 777 }
777 778
778 INIT_UDATA_BUF_OR_NULL(&ucore, buf, (unsigned long) ex_hdr.response, 779 ib_uverbs_init_udata_buf_or_null(&ucore, buf,
779 hdr.in_words * 8, hdr.out_words * 8); 780 u64_to_user_ptr(ex_hdr.response),
781 hdr.in_words * 8, hdr.out_words * 8);
780 782
781 INIT_UDATA_BUF_OR_NULL(&uhw, 783 ib_uverbs_init_udata_buf_or_null(&uhw,
782 buf + ucore.inlen, 784 buf + ucore.inlen,
783 (unsigned long) ex_hdr.response + ucore.outlen, 785 u64_to_user_ptr(ex_hdr.response) + ucore.outlen,
784 ex_hdr.provider_in_words * 8, 786 ex_hdr.provider_in_words * 8,
785 ex_hdr.provider_out_words * 8); 787 ex_hdr.provider_out_words * 8);
786 788
787 ret = uverbs_ex_cmd_table[command](file, 789 ret = uverbs_ex_cmd_table[command](file, ib_dev, &ucore, &uhw);
788 ib_dev,
789 &ucore,
790 &uhw);
791 if (!ret) 790 if (!ret)
792 ret = written_count; 791 ret = written_count;
793 } else { 792 } else {
diff --git a/drivers/infiniband/core/uverbs_marshall.c b/drivers/infiniband/core/uverbs_marshall.c
index bd0acf376af0..bb372b4713a4 100644
--- a/drivers/infiniband/core/uverbs_marshall.c
+++ b/drivers/infiniband/core/uverbs_marshall.c
@@ -69,8 +69,7 @@ void ib_copy_ah_attr_to_user(struct ib_device *device,
69 memset(&dst->grh.reserved, 0, sizeof(dst->grh.reserved)); 69 memset(&dst->grh.reserved, 0, sizeof(dst->grh.reserved));
70 70
71 if ((ah_attr->type == RDMA_AH_ATTR_TYPE_OPA) && 71 if ((ah_attr->type == RDMA_AH_ATTR_TYPE_OPA) &&
72 (rdma_ah_get_dlid(ah_attr) >= 72 (rdma_ah_get_dlid(ah_attr) > be16_to_cpu(IB_LID_PERMISSIVE)) &&
73 be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
74 (!rdma_ah_conv_opa_to_ib(device, &conv_ah, ah_attr))) 73 (!rdma_ah_conv_opa_to_ib(device, &conv_ah, ah_attr)))
75 src = &conv_ah; 74 src = &conv_ah;
76 75
@@ -176,18 +175,18 @@ EXPORT_SYMBOL(ib_copy_path_rec_to_user);
176void ib_copy_path_rec_from_user(struct sa_path_rec *dst, 175void ib_copy_path_rec_from_user(struct sa_path_rec *dst,
177 struct ib_user_path_rec *src) 176 struct ib_user_path_rec *src)
178{ 177{
179 __be32 slid, dlid; 178 u32 slid, dlid;
180 179
181 memset(dst, 0, sizeof(*dst)); 180 memset(dst, 0, sizeof(*dst));
182 if ((ib_is_opa_gid((union ib_gid *)src->sgid)) || 181 if ((ib_is_opa_gid((union ib_gid *)src->sgid)) ||
183 (ib_is_opa_gid((union ib_gid *)src->dgid))) { 182 (ib_is_opa_gid((union ib_gid *)src->dgid))) {
184 dst->rec_type = SA_PATH_REC_TYPE_OPA; 183 dst->rec_type = SA_PATH_REC_TYPE_OPA;
185 slid = htonl(opa_get_lid_from_gid((union ib_gid *)src->sgid)); 184 slid = opa_get_lid_from_gid((union ib_gid *)src->sgid);
186 dlid = htonl(opa_get_lid_from_gid((union ib_gid *)src->dgid)); 185 dlid = opa_get_lid_from_gid((union ib_gid *)src->dgid);
187 } else { 186 } else {
188 dst->rec_type = SA_PATH_REC_TYPE_IB; 187 dst->rec_type = SA_PATH_REC_TYPE_IB;
189 slid = htonl(ntohs(src->slid)); 188 slid = ntohs(src->slid);
190 dlid = htonl(ntohs(src->dlid)); 189 dlid = ntohs(src->dlid);
191 } 190 }
192 memcpy(dst->dgid.raw, src->dgid, sizeof dst->dgid); 191 memcpy(dst->dgid.raw, src->dgid, sizeof dst->dgid);
193 memcpy(dst->sgid.raw, src->sgid, sizeof dst->sgid); 192 memcpy(dst->sgid.raw, src->sgid, sizeof dst->sgid);
diff --git a/drivers/infiniband/core/uverbs_std_types.c b/drivers/infiniband/core/uverbs_std_types.c
index 0a98579700ec..c3ee5d9b336d 100644
--- a/drivers/infiniband/core/uverbs_std_types.c
+++ b/drivers/infiniband/core/uverbs_std_types.c
@@ -227,26 +227,26 @@ static void create_udata(struct uverbs_attr_bundle *ctx,
227 * to use uverbs_attr_bundle instead of ib_udata. 227 * to use uverbs_attr_bundle instead of ib_udata.
228 * Assume attr == 0 is input and attr == 1 is output. 228 * Assume attr == 0 is input and attr == 1 is output.
229 */ 229 */
230 void __user *inbuf;
231 size_t inbuf_len = 0;
232 void __user *outbuf;
233 size_t outbuf_len = 0;
234 const struct uverbs_attr *uhw_in = 230 const struct uverbs_attr *uhw_in =
235 uverbs_attr_get(ctx, UVERBS_UHW_IN); 231 uverbs_attr_get(ctx, UVERBS_UHW_IN);
236 const struct uverbs_attr *uhw_out = 232 const struct uverbs_attr *uhw_out =
237 uverbs_attr_get(ctx, UVERBS_UHW_OUT); 233 uverbs_attr_get(ctx, UVERBS_UHW_OUT);
238 234
239 if (!IS_ERR(uhw_in)) { 235 if (!IS_ERR(uhw_in)) {
240 inbuf = uhw_in->ptr_attr.ptr; 236 udata->inbuf = uhw_in->ptr_attr.ptr;
241 inbuf_len = uhw_in->ptr_attr.len; 237 udata->inlen = uhw_in->ptr_attr.len;
238 } else {
239 udata->inbuf = NULL;
240 udata->inlen = 0;
242 } 241 }
243 242
244 if (!IS_ERR(uhw_out)) { 243 if (!IS_ERR(uhw_out)) {
245 outbuf = uhw_out->ptr_attr.ptr; 244 udata->outbuf = uhw_out->ptr_attr.ptr;
246 outbuf_len = uhw_out->ptr_attr.len; 245 udata->outlen = uhw_out->ptr_attr.len;
246 } else {
247 udata->outbuf = NULL;
248 udata->outlen = 0;
247 } 249 }
248
249 INIT_UDATA_BUF_OR_NULL(udata, inbuf, outbuf, inbuf_len, outbuf_len);
250} 250}
251 251
252static int uverbs_create_cq_handler(struct ib_device *ib_dev, 252static int uverbs_create_cq_handler(struct ib_device *ib_dev,
diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c
index de57d6c11a25..3fb8fb6cc824 100644
--- a/drivers/infiniband/core/verbs.c
+++ b/drivers/infiniband/core/verbs.c
@@ -53,6 +53,9 @@
53 53
54#include "core_priv.h" 54#include "core_priv.h"
55 55
56static int ib_resolve_eth_dmac(struct ib_device *device,
57 struct rdma_ah_attr *ah_attr);
58
56static const char * const ib_events[] = { 59static const char * const ib_events[] = {
57 [IB_EVENT_CQ_ERR] = "CQ error", 60 [IB_EVENT_CQ_ERR] = "CQ error",
58 [IB_EVENT_QP_FATAL] = "QP fatal error", 61 [IB_EVENT_QP_FATAL] = "QP fatal error",
@@ -302,11 +305,13 @@ EXPORT_SYMBOL(ib_dealloc_pd);
302 305
303/* Address handles */ 306/* Address handles */
304 307
305struct ib_ah *rdma_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr) 308static struct ib_ah *_rdma_create_ah(struct ib_pd *pd,
309 struct rdma_ah_attr *ah_attr,
310 struct ib_udata *udata)
306{ 311{
307 struct ib_ah *ah; 312 struct ib_ah *ah;
308 313
309 ah = pd->device->create_ah(pd, ah_attr, NULL); 314 ah = pd->device->create_ah(pd, ah_attr, udata);
310 315
311 if (!IS_ERR(ah)) { 316 if (!IS_ERR(ah)) {
312 ah->device = pd->device; 317 ah->device = pd->device;
@@ -318,8 +323,42 @@ struct ib_ah *rdma_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr)
318 323
319 return ah; 324 return ah;
320} 325}
326
327struct ib_ah *rdma_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr)
328{
329 return _rdma_create_ah(pd, ah_attr, NULL);
330}
321EXPORT_SYMBOL(rdma_create_ah); 331EXPORT_SYMBOL(rdma_create_ah);
322 332
333/**
334 * rdma_create_user_ah - Creates an address handle for the
335 * given address vector.
336 * It resolves destination mac address for ah attribute of RoCE type.
337 * @pd: The protection domain associated with the address handle.
338 * @ah_attr: The attributes of the address vector.
339 * @udata: pointer to user's input output buffer information need by
340 * provider driver.
341 *
342 * It returns 0 on success and returns appropriate error code on error.
343 * The address handle is used to reference a local or global destination
344 * in all UD QP post sends.
345 */
346struct ib_ah *rdma_create_user_ah(struct ib_pd *pd,
347 struct rdma_ah_attr *ah_attr,
348 struct ib_udata *udata)
349{
350 int err;
351
352 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
353 err = ib_resolve_eth_dmac(pd->device, ah_attr);
354 if (err)
355 return ERR_PTR(err);
356 }
357
358 return _rdma_create_ah(pd, ah_attr, udata);
359}
360EXPORT_SYMBOL(rdma_create_user_ah);
361
323int ib_get_rdma_header_version(const union rdma_network_hdr *hdr) 362int ib_get_rdma_header_version(const union rdma_network_hdr *hdr)
324{ 363{
325 const struct iphdr *ip4h = (struct iphdr *)&hdr->roce4grh; 364 const struct iphdr *ip4h = (struct iphdr *)&hdr->roce4grh;
@@ -1221,8 +1260,8 @@ int ib_modify_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state next_state,
1221} 1260}
1222EXPORT_SYMBOL(ib_modify_qp_is_ok); 1261EXPORT_SYMBOL(ib_modify_qp_is_ok);
1223 1262
1224int ib_resolve_eth_dmac(struct ib_device *device, 1263static int ib_resolve_eth_dmac(struct ib_device *device,
1225 struct rdma_ah_attr *ah_attr) 1264 struct rdma_ah_attr *ah_attr)
1226{ 1265{
1227 int ret = 0; 1266 int ret = 0;
1228 struct ib_global_route *grh; 1267 struct ib_global_route *grh;
@@ -1281,7 +1320,6 @@ int ib_resolve_eth_dmac(struct ib_device *device,
1281out: 1320out:
1282 return ret; 1321 return ret;
1283} 1322}
1284EXPORT_SYMBOL(ib_resolve_eth_dmac);
1285 1323
1286/** 1324/**
1287 * ib_modify_qp_with_udata - Modifies the attributes for the specified QP. 1325 * ib_modify_qp_with_udata - Modifies the attributes for the specified QP.
@@ -1512,12 +1550,12 @@ struct ib_cq *ib_create_cq(struct ib_device *device,
1512} 1550}
1513EXPORT_SYMBOL(ib_create_cq); 1551EXPORT_SYMBOL(ib_create_cq);
1514 1552
1515int ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 1553int rdma_set_cq_moderation(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1516{ 1554{
1517 return cq->device->modify_cq ? 1555 return cq->device->modify_cq ?
1518 cq->device->modify_cq(cq, cq_count, cq_period) : -ENOSYS; 1556 cq->device->modify_cq(cq, cq_count, cq_period) : -ENOSYS;
1519} 1557}
1520EXPORT_SYMBOL(ib_modify_cq); 1558EXPORT_SYMBOL(rdma_set_cq_moderation);
1521 1559
1522int ib_destroy_cq(struct ib_cq *cq) 1560int ib_destroy_cq(struct ib_cq *cq)
1523{ 1561{
diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
index 0d89621d9fe8..2032db7db766 100644
--- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
+++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
@@ -394,6 +394,7 @@ int bnxt_re_add_gid(struct ib_device *ibdev, u8 port_num,
394 ctx->idx = tbl_idx; 394 ctx->idx = tbl_idx;
395 ctx->refcnt = 1; 395 ctx->refcnt = 1;
396 ctx_tbl[tbl_idx] = ctx; 396 ctx_tbl[tbl_idx] = ctx;
397 *context = ctx;
397 398
398 return rc; 399 return rc;
399} 400}
@@ -665,7 +666,6 @@ struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
665 struct bnxt_re_ah *ah; 666 struct bnxt_re_ah *ah;
666 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 667 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
667 int rc; 668 int rc;
668 u16 vlan_tag;
669 u8 nw_type; 669 u8 nw_type;
670 670
671 struct ib_gid_attr sgid_attr; 671 struct ib_gid_attr sgid_attr;
@@ -711,11 +711,8 @@ struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
711 grh->sgid_index); 711 grh->sgid_index);
712 goto fail; 712 goto fail;
713 } 713 }
714 if (sgid_attr.ndev) { 714 if (sgid_attr.ndev)
715 if (is_vlan_dev(sgid_attr.ndev))
716 vlan_tag = vlan_dev_vlan_id(sgid_attr.ndev);
717 dev_put(sgid_attr.ndev); 715 dev_put(sgid_attr.ndev);
718 }
719 /* Get network header type for this GID */ 716 /* Get network header type for this GID */
720 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid); 717 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
721 switch (nw_type) { 718 switch (nw_type) {
@@ -729,14 +726,6 @@ struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
729 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1; 726 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1;
730 break; 727 break;
731 } 728 }
732 rc = rdma_addr_find_l2_eth_by_grh(&sgid, &grh->dgid,
733 ah_attr->roce.dmac, &vlan_tag,
734 &sgid_attr.ndev->ifindex,
735 NULL);
736 if (rc) {
737 dev_err(rdev_to_dev(rdev), "Failed to get dmac\n");
738 goto fail;
739 }
740 } 729 }
741 730
742 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 731 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
@@ -796,6 +785,7 @@ int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
796 struct bnxt_re_dev *rdev = qp->rdev; 785 struct bnxt_re_dev *rdev = qp->rdev;
797 int rc; 786 int rc;
798 787
788 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
799 bnxt_qplib_del_flush_qp(&qp->qplib_qp); 789 bnxt_qplib_del_flush_qp(&qp->qplib_qp);
800 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 790 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
801 if (rc) { 791 if (rc) {
@@ -1643,7 +1633,7 @@ static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
1643 u8 ip_version = 0; 1633 u8 ip_version = 0;
1644 u16 vlan_id = 0xFFFF; 1634 u16 vlan_id = 0xFFFF;
1645 void *buf; 1635 void *buf;
1646 int i, rc = 0, size; 1636 int i, rc = 0;
1647 1637
1648 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 1638 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
1649 1639
@@ -1760,7 +1750,7 @@ static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
1760 /* Pack the QP1 to the transmit buffer */ 1750 /* Pack the QP1 to the transmit buffer */
1761 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 1751 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
1762 if (buf) { 1752 if (buf) {
1763 size = ib_ud_header_pack(&qp->qp1_hdr, buf); 1753 ib_ud_header_pack(&qp->qp1_hdr, buf);
1764 for (i = wqe->num_sge; i; i--) { 1754 for (i = wqe->num_sge; i; i--) {
1765 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 1755 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
1766 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 1756 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
@@ -2216,7 +2206,7 @@ static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2216 struct ib_recv_wr *wr) 2206 struct ib_recv_wr *wr)
2217{ 2207{
2218 struct bnxt_qplib_swqe wqe; 2208 struct bnxt_qplib_swqe wqe;
2219 int rc = 0, payload_sz = 0; 2209 int rc = 0;
2220 2210
2221 memset(&wqe, 0, sizeof(wqe)); 2211 memset(&wqe, 0, sizeof(wqe));
2222 while (wr) { 2212 while (wr) {
@@ -2231,8 +2221,7 @@ static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2231 rc = -EINVAL; 2221 rc = -EINVAL;
2232 break; 2222 break;
2233 } 2223 }
2234 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2224 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2235 wr->num_sge);
2236 wqe.wr_id = wr->wr_id; 2225 wqe.wr_id = wr->wr_id;
2237 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2226 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2238 2227
@@ -2569,7 +2558,7 @@ static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
2569static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 2558static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2570 u16 raweth_qp1_flags2) 2559 u16 raweth_qp1_flags2)
2571{ 2560{
2572 bool is_udp = false, is_ipv6 = false, is_ipv4 = false; 2561 bool is_ipv6 = false, is_ipv4 = false;
2573 2562
2574 /* raweth_qp1_flags Bit 9-6 indicates itype */ 2563 /* raweth_qp1_flags Bit 9-6 indicates itype */
2575 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2564 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
@@ -2580,7 +2569,6 @@ static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2580 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 2569 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
2581 raweth_qp1_flags2 & 2570 raweth_qp1_flags2 &
2582 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 2571 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
2583 is_udp = true;
2584 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 2572 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
2585 (raweth_qp1_flags2 & 2573 (raweth_qp1_flags2 &
2586 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 2574 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
@@ -2781,6 +2769,32 @@ static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
2781 wc->wc_flags |= IB_WC_GRH; 2769 wc->wc_flags |= IB_WC_GRH;
2782} 2770}
2783 2771
2772static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
2773 u16 *vid, u8 *sl)
2774{
2775 bool ret = false;
2776 u32 metadata;
2777 u16 tpid;
2778
2779 metadata = orig_cqe->raweth_qp1_metadata;
2780 if (orig_cqe->raweth_qp1_flags2 &
2781 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
2782 tpid = ((metadata &
2783 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
2784 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
2785 if (tpid == ETH_P_8021Q) {
2786 *vid = metadata &
2787 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
2788 *sl = (metadata &
2789 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
2790 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
2791 ret = true;
2792 }
2793 }
2794
2795 return ret;
2796}
2797
2784static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 2798static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
2785 struct bnxt_qplib_cqe *cqe) 2799 struct bnxt_qplib_cqe *cqe)
2786{ 2800{
@@ -2800,12 +2814,14 @@ static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
2800 struct ib_wc *wc, 2814 struct ib_wc *wc,
2801 struct bnxt_qplib_cqe *cqe) 2815 struct bnxt_qplib_cqe *cqe)
2802{ 2816{
2803 u32 tbl_idx;
2804 struct bnxt_re_dev *rdev = qp->rdev; 2817 struct bnxt_re_dev *rdev = qp->rdev;
2805 struct bnxt_re_qp *qp1_qp = NULL; 2818 struct bnxt_re_qp *qp1_qp = NULL;
2806 struct bnxt_qplib_cqe *orig_cqe = NULL; 2819 struct bnxt_qplib_cqe *orig_cqe = NULL;
2807 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2820 struct bnxt_re_sqp_entries *sqp_entry = NULL;
2808 int nw_type; 2821 int nw_type;
2822 u32 tbl_idx;
2823 u16 vlan_id;
2824 u8 sl;
2809 2825
2810 tbl_idx = cqe->wr_id; 2826 tbl_idx = cqe->wr_id;
2811 2827
@@ -2820,6 +2836,11 @@ static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
2820 wc->ex.imm_data = orig_cqe->immdata; 2836 wc->ex.imm_data = orig_cqe->immdata;
2821 wc->src_qp = orig_cqe->src_qp; 2837 wc->src_qp = orig_cqe->src_qp;
2822 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 2838 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
2839 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
2840 wc->vlan_id = vlan_id;
2841 wc->sl = sl;
2842 wc->wc_flags |= IB_WC_WITH_VLAN;
2843 }
2823 wc->port_num = 1; 2844 wc->port_num = 1;
2824 wc->vendor_err = orig_cqe->status; 2845 wc->vendor_err = orig_cqe->status;
2825 2846
@@ -3008,8 +3029,10 @@ int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3008 enum ib_cq_notify_flags ib_cqn_flags) 3029 enum ib_cq_notify_flags ib_cqn_flags)
3009{ 3030{
3010 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3031 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3011 int type = 0; 3032 int type = 0, rc = 0;
3033 unsigned long flags;
3012 3034
3035 spin_lock_irqsave(&cq->cq_lock, flags);
3013 /* Trigger on the very next completion */ 3036 /* Trigger on the very next completion */
3014 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3037 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3015 type = DBR_DBR_TYPE_CQ_ARMALL; 3038 type = DBR_DBR_TYPE_CQ_ARMALL;
@@ -3019,12 +3042,15 @@ int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3019 3042
3020 /* Poll to see if there are missed events */ 3043 /* Poll to see if there are missed events */
3021 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3044 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3022 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) 3045 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3023 return 1; 3046 rc = 1;
3024 3047 goto exit;
3048 }
3025 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3049 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3026 3050
3027 return 0; 3051exit:
3052 spin_unlock_irqrestore(&cq->cq_lock, flags);
3053 return rc;
3028} 3054}
3029 3055
3030/* Memory Regions */ 3056/* Memory Regions */
diff --git a/drivers/infiniband/hw/bnxt_re/main.c b/drivers/infiniband/hw/bnxt_re/main.c
index e7450ea92aa9..aafc19aa5de1 100644
--- a/drivers/infiniband/hw/bnxt_re/main.c
+++ b/drivers/infiniband/hw/bnxt_re/main.c
@@ -78,6 +78,7 @@ static struct list_head bnxt_re_dev_list = LIST_HEAD_INIT(bnxt_re_dev_list);
78/* Mutex to protect the list of bnxt_re devices added */ 78/* Mutex to protect the list of bnxt_re devices added */
79static DEFINE_MUTEX(bnxt_re_dev_lock); 79static DEFINE_MUTEX(bnxt_re_dev_lock);
80static struct workqueue_struct *bnxt_re_wq; 80static struct workqueue_struct *bnxt_re_wq;
81static void bnxt_re_ib_unreg(struct bnxt_re_dev *rdev, bool lock_wait);
81 82
82/* for handling bnxt_en callbacks later */ 83/* for handling bnxt_en callbacks later */
83static void bnxt_re_stop(void *p) 84static void bnxt_re_stop(void *p)
@@ -92,11 +93,22 @@ static void bnxt_re_sriov_config(void *p, int num_vfs)
92{ 93{
93} 94}
94 95
96static void bnxt_re_shutdown(void *p)
97{
98 struct bnxt_re_dev *rdev = p;
99
100 if (!rdev)
101 return;
102
103 bnxt_re_ib_unreg(rdev, false);
104}
105
95static struct bnxt_ulp_ops bnxt_re_ulp_ops = { 106static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
96 .ulp_async_notifier = NULL, 107 .ulp_async_notifier = NULL,
97 .ulp_stop = bnxt_re_stop, 108 .ulp_stop = bnxt_re_stop,
98 .ulp_start = bnxt_re_start, 109 .ulp_start = bnxt_re_start,
99 .ulp_sriov_config = bnxt_re_sriov_config 110 .ulp_sriov_config = bnxt_re_sriov_config,
111 .ulp_shutdown = bnxt_re_shutdown
100}; 112};
101 113
102/* RoCE -> Net driver */ 114/* RoCE -> Net driver */
@@ -1071,9 +1083,10 @@ static int bnxt_re_ib_reg(struct bnxt_re_dev *rdev)
1071 */ 1083 */
1072 rc = bnxt_qplib_alloc_rcfw_channel(rdev->en_dev->pdev, &rdev->rcfw, 1084 rc = bnxt_qplib_alloc_rcfw_channel(rdev->en_dev->pdev, &rdev->rcfw,
1073 BNXT_RE_MAX_QPC_COUNT); 1085 BNXT_RE_MAX_QPC_COUNT);
1074 if (rc) 1086 if (rc) {
1087 pr_err("Failed to allocate RCFW Channel: %#x\n", rc);
1075 goto fail; 1088 goto fail;
1076 1089 }
1077 rc = bnxt_re_net_ring_alloc 1090 rc = bnxt_re_net_ring_alloc
1078 (rdev, rdev->rcfw.creq.pbl[PBL_LVL_0].pg_map_arr, 1091 (rdev, rdev->rcfw.creq.pbl[PBL_LVL_0].pg_map_arr,
1079 rdev->rcfw.creq.pbl[rdev->rcfw.creq.level].pg_count, 1092 rdev->rcfw.creq.pbl[rdev->rcfw.creq.level].pg_count,
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_fp.c b/drivers/infiniband/hw/bnxt_re/qplib_fp.c
index e8afc47f8949..61764f7aa79b 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.c
+++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.c
@@ -160,11 +160,6 @@ void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp)
160 160
161static void __bnxt_qplib_del_flush_qp(struct bnxt_qplib_qp *qp) 161static void __bnxt_qplib_del_flush_qp(struct bnxt_qplib_qp *qp)
162{ 162{
163 struct bnxt_qplib_cq *scq, *rcq;
164
165 scq = qp->scq;
166 rcq = qp->rcq;
167
168 if (qp->sq.flushed) { 163 if (qp->sq.flushed) {
169 qp->sq.flushed = false; 164 qp->sq.flushed = false;
170 list_del(&qp->sq_flush); 165 list_del(&qp->sq_flush);
@@ -297,6 +292,12 @@ static void bnxt_qplib_service_nq(unsigned long data)
297 if (!NQE_CMP_VALID(nqe, raw_cons, hwq->max_elements)) 292 if (!NQE_CMP_VALID(nqe, raw_cons, hwq->max_elements))
298 break; 293 break;
299 294
295 /*
296 * The valid test of the entry must be done first before
297 * reading any further.
298 */
299 dma_rmb();
300
300 type = le16_to_cpu(nqe->info10_type) & NQ_BASE_TYPE_MASK; 301 type = le16_to_cpu(nqe->info10_type) & NQ_BASE_TYPE_MASK;
301 switch (type) { 302 switch (type) {
302 case NQ_BASE_TYPE_CQ_NOTIFICATION: 303 case NQ_BASE_TYPE_CQ_NOTIFICATION:
@@ -1118,6 +1119,11 @@ static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp)
1118 hw_cqe = &hw_cqe_ptr[CQE_PG(i)][CQE_IDX(i)]; 1119 hw_cqe = &hw_cqe_ptr[CQE_PG(i)][CQE_IDX(i)];
1119 if (!CQE_CMP_VALID(hw_cqe, i, cq_hwq->max_elements)) 1120 if (!CQE_CMP_VALID(hw_cqe, i, cq_hwq->max_elements))
1120 continue; 1121 continue;
1122 /*
1123 * The valid test of the entry must be done first before
1124 * reading any further.
1125 */
1126 dma_rmb();
1121 switch (hw_cqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK) { 1127 switch (hw_cqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK) {
1122 case CQ_BASE_CQE_TYPE_REQ: 1128 case CQ_BASE_CQE_TYPE_REQ:
1123 case CQ_BASE_CQE_TYPE_TERMINAL: 1129 case CQ_BASE_CQE_TYPE_TERMINAL:
@@ -1360,7 +1366,7 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,
1360 1366
1361 break; 1367 break;
1362 } 1368 }
1363 /* else, just fall thru */ 1369 /* fall thru */
1364 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 1370 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
1365 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 1371 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
1366 { 1372 {
@@ -1901,6 +1907,11 @@ static int do_wa9060(struct bnxt_qplib_qp *qp, struct bnxt_qplib_cq *cq,
1901 /* If the next hwcqe is VALID */ 1907 /* If the next hwcqe is VALID */
1902 if (CQE_CMP_VALID(peek_hwcqe, peek_raw_cq_cons, 1908 if (CQE_CMP_VALID(peek_hwcqe, peek_raw_cq_cons,
1903 cq->hwq.max_elements)) { 1909 cq->hwq.max_elements)) {
1910 /*
1911 * The valid test of the entry must be done first before
1912 * reading any further.
1913 */
1914 dma_rmb();
1904 /* If the next hwcqe is a REQ */ 1915 /* If the next hwcqe is a REQ */
1905 if ((peek_hwcqe->cqe_type_toggle & 1916 if ((peek_hwcqe->cqe_type_toggle &
1906 CQ_BASE_CQE_TYPE_MASK) == 1917 CQ_BASE_CQE_TYPE_MASK) ==
@@ -2107,6 +2118,7 @@ static int bnxt_qplib_cq_process_res_rc(struct bnxt_qplib_cq *cq,
2107 *pcqe = cqe; 2118 *pcqe = cqe;
2108 2119
2109 if (hwcqe->status != CQ_RES_RC_STATUS_OK) { 2120 if (hwcqe->status != CQ_RES_RC_STATUS_OK) {
2121 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
2110 /* Add qp to flush list of the CQ */ 2122 /* Add qp to flush list of the CQ */
2111 bnxt_qplib_lock_buddy_cq(qp, cq); 2123 bnxt_qplib_lock_buddy_cq(qp, cq);
2112 __bnxt_qplib_add_flush_qp(qp); 2124 __bnxt_qplib_add_flush_qp(qp);
@@ -2170,6 +2182,7 @@ static int bnxt_qplib_cq_process_res_ud(struct bnxt_qplib_cq *cq,
2170 *pcqe = cqe; 2182 *pcqe = cqe;
2171 2183
2172 if (hwcqe->status != CQ_RES_RC_STATUS_OK) { 2184 if (hwcqe->status != CQ_RES_RC_STATUS_OK) {
2185 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
2173 /* Add qp to flush list of the CQ */ 2186 /* Add qp to flush list of the CQ */
2174 bnxt_qplib_lock_buddy_cq(qp, cq); 2187 bnxt_qplib_lock_buddy_cq(qp, cq);
2175 __bnxt_qplib_add_flush_qp(qp); 2188 __bnxt_qplib_add_flush_qp(qp);
@@ -2241,6 +2254,7 @@ static int bnxt_qplib_cq_process_res_raweth_qp1(struct bnxt_qplib_cq *cq,
2241 2254
2242 cqe->raweth_qp1_flags = le16_to_cpu(hwcqe->raweth_qp1_flags); 2255 cqe->raweth_qp1_flags = le16_to_cpu(hwcqe->raweth_qp1_flags);
2243 cqe->raweth_qp1_flags2 = le32_to_cpu(hwcqe->raweth_qp1_flags2); 2256 cqe->raweth_qp1_flags2 = le32_to_cpu(hwcqe->raweth_qp1_flags2);
2257 cqe->raweth_qp1_metadata = le32_to_cpu(hwcqe->raweth_qp1_metadata);
2244 2258
2245 rq = &qp->rq; 2259 rq = &qp->rq;
2246 if (wr_id_idx > rq->hwq.max_elements) { 2260 if (wr_id_idx > rq->hwq.max_elements) {
@@ -2257,6 +2271,7 @@ static int bnxt_qplib_cq_process_res_raweth_qp1(struct bnxt_qplib_cq *cq,
2257 *pcqe = cqe; 2271 *pcqe = cqe;
2258 2272
2259 if (hwcqe->status != CQ_RES_RC_STATUS_OK) { 2273 if (hwcqe->status != CQ_RES_RC_STATUS_OK) {
2274 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR;
2260 /* Add qp to flush list of the CQ */ 2275 /* Add qp to flush list of the CQ */
2261 bnxt_qplib_lock_buddy_cq(qp, cq); 2276 bnxt_qplib_lock_buddy_cq(qp, cq);
2262 __bnxt_qplib_add_flush_qp(qp); 2277 __bnxt_qplib_add_flush_qp(qp);
@@ -2445,6 +2460,11 @@ int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,
2445 if (!CQE_CMP_VALID(hw_cqe, raw_cons, cq->hwq.max_elements)) 2460 if (!CQE_CMP_VALID(hw_cqe, raw_cons, cq->hwq.max_elements))
2446 break; 2461 break;
2447 2462
2463 /*
2464 * The valid test of the entry must be done first before
2465 * reading any further.
2466 */
2467 dma_rmb();
2448 /* From the device's respective CQE format to qplib_wc*/ 2468 /* From the device's respective CQE format to qplib_wc*/
2449 switch (hw_cqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK) { 2469 switch (hw_cqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK) {
2450 case CQ_BASE_CQE_TYPE_REQ: 2470 case CQ_BASE_CQE_TYPE_REQ:
@@ -2518,3 +2538,10 @@ void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type)
2518 atomic_set(&cq->arm_state, 1); 2538 atomic_set(&cq->arm_state, 1);
2519 spin_unlock_irqrestore(&cq->hwq.lock, flags); 2539 spin_unlock_irqrestore(&cq->hwq.lock, flags);
2520} 2540}
2541
2542void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp)
2543{
2544 flush_workqueue(qp->scq->nq->cqn_wq);
2545 if (qp->scq != qp->rcq)
2546 flush_workqueue(qp->rcq->nq->cqn_wq);
2547}
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_fp.h b/drivers/infiniband/hw/bnxt_re/qplib_fp.h
index 8ead70ca1c1d..c582d4ec8173 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.h
+++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.h
@@ -478,4 +478,5 @@ void bnxt_qplib_release_cq_locks(struct bnxt_qplib_qp *qp,
478int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq, 478int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq,
479 struct bnxt_qplib_cqe *cqe, 479 struct bnxt_qplib_cqe *cqe,
480 int num_cqes); 480 int num_cqes);
481void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp);
481#endif /* __BNXT_QPLIB_FP_H__ */ 482#endif /* __BNXT_QPLIB_FP_H__ */
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
index 2bdb1562bd21..bb5574adf195 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
+++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
@@ -88,7 +88,6 @@ static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req,
88 unsigned long flags; 88 unsigned long flags;
89 u32 size, opcode; 89 u32 size, opcode;
90 u16 cookie, cbit; 90 u16 cookie, cbit;
91 int pg, idx;
92 u8 *preq; 91 u8 *preq;
93 92
94 opcode = req->opcode; 93 opcode = req->opcode;
@@ -149,9 +148,6 @@ static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req,
149 preq = (u8 *)req; 148 preq = (u8 *)req;
150 size = req->cmd_size * BNXT_QPLIB_CMDQE_UNITS; 149 size = req->cmd_size * BNXT_QPLIB_CMDQE_UNITS;
151 do { 150 do {
152 pg = 0;
153 idx = 0;
154
155 /* Locate the next cmdq slot */ 151 /* Locate the next cmdq slot */
156 sw_prod = HWQ_CMP(cmdq->prod, cmdq); 152 sw_prod = HWQ_CMP(cmdq->prod, cmdq);
157 cmdqe = &cmdq_ptr[get_cmdq_pg(sw_prod)][get_cmdq_idx(sw_prod)]; 153 cmdqe = &cmdq_ptr[get_cmdq_pg(sw_prod)][get_cmdq_idx(sw_prod)];
@@ -172,14 +168,14 @@ static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req,
172 rcfw->seq_num++; 168 rcfw->seq_num++;
173 169
174 cmdq_prod = cmdq->prod; 170 cmdq_prod = cmdq->prod;
175 if (rcfw->flags & FIRMWARE_FIRST_FLAG) { 171 if (test_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags)) {
176 /* The very first doorbell write 172 /* The very first doorbell write
177 * is required to set this flag 173 * is required to set this flag
178 * which prompts the FW to reset 174 * which prompts the FW to reset
179 * its internal pointers 175 * its internal pointers
180 */ 176 */
181 cmdq_prod |= FIRMWARE_FIRST_FLAG; 177 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG);
182 rcfw->flags &= ~FIRMWARE_FIRST_FLAG; 178 clear_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags);
183 } 179 }
184 180
185 /* ring CMDQ DB */ 181 /* ring CMDQ DB */
@@ -306,6 +302,8 @@ static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
306 "QPLIB: qpid 0x%x, req_err=0x%x, resp_err=0x%x\n", 302 "QPLIB: qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
307 qp_id, err_event->req_err_state_reason, 303 qp_id, err_event->req_err_state_reason,
308 err_event->res_err_state_reason); 304 err_event->res_err_state_reason);
305 if (!qp)
306 break;
309 bnxt_qplib_acquire_cq_locks(qp, &flags); 307 bnxt_qplib_acquire_cq_locks(qp, &flags);
310 bnxt_qplib_mark_qp_error(qp); 308 bnxt_qplib_mark_qp_error(qp);
311 bnxt_qplib_release_cq_locks(qp, &flags); 309 bnxt_qplib_release_cq_locks(qp, &flags);
@@ -361,6 +359,10 @@ static void bnxt_qplib_service_creq(unsigned long data)
361 creqe = &creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)]; 359 creqe = &creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)];
362 if (!CREQ_CMP_VALID(creqe, raw_cons, creq->max_elements)) 360 if (!CREQ_CMP_VALID(creqe, raw_cons, creq->max_elements))
363 break; 361 break;
362 /* The valid test of the entry must be done first before
363 * reading any further.
364 */
365 dma_rmb();
364 366
365 type = creqe->type & CREQ_BASE_TYPE_MASK; 367 type = creqe->type & CREQ_BASE_TYPE_MASK;
366 switch (type) { 368 switch (type) {
@@ -622,7 +624,7 @@ int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
622 624
623 /* General */ 625 /* General */
624 rcfw->seq_num = 0; 626 rcfw->seq_num = 0;
625 rcfw->flags = FIRMWARE_FIRST_FLAG; 627 set_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags);
626 bmap_size = BITS_TO_LONGS(RCFW_MAX_OUTSTANDING_CMD * 628 bmap_size = BITS_TO_LONGS(RCFW_MAX_OUTSTANDING_CMD *
627 sizeof(unsigned long)); 629 sizeof(unsigned long));
628 rcfw->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL); 630 rcfw->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL);
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
index 85b16da287f9..2946a7cfae82 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
+++ b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
@@ -162,9 +162,9 @@ struct bnxt_qplib_rcfw {
162 unsigned long *cmdq_bitmap; 162 unsigned long *cmdq_bitmap;
163 u32 bmap_size; 163 u32 bmap_size;
164 unsigned long flags; 164 unsigned long flags;
165#define FIRMWARE_INITIALIZED_FLAG BIT(0) 165#define FIRMWARE_INITIALIZED_FLAG 0
166#define FIRMWARE_FIRST_FLAG BIT(31) 166#define FIRMWARE_FIRST_FLAG 31
167#define FIRMWARE_TIMED_OUT BIT(3) 167#define FIRMWARE_TIMED_OUT 3
168 wait_queue_head_t waitq; 168 wait_queue_head_t waitq;
169 int (*aeq_handler)(struct bnxt_qplib_rcfw *, 169 int (*aeq_handler)(struct bnxt_qplib_rcfw *,
170 struct creq_func_event *); 170 struct creq_func_event *);
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.h b/drivers/infiniband/hw/bnxt_re/qplib_res.h
index e87207526d2c..2e5c052da5a9 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_res.h
+++ b/drivers/infiniband/hw/bnxt_re/qplib_res.h
@@ -169,7 +169,7 @@ struct bnxt_qplib_ctx {
169 u32 cq_count; 169 u32 cq_count;
170 struct bnxt_qplib_hwq cq_tbl; 170 struct bnxt_qplib_hwq cq_tbl;
171 struct bnxt_qplib_hwq tim_tbl; 171 struct bnxt_qplib_hwq tim_tbl;
172#define MAX_TQM_ALLOC_REQ 32 172#define MAX_TQM_ALLOC_REQ 48
173#define MAX_TQM_ALLOC_BLK_SIZE 8 173#define MAX_TQM_ALLOC_BLK_SIZE 8
174 u8 tqm_count[MAX_TQM_ALLOC_REQ]; 174 u8 tqm_count[MAX_TQM_ALLOC_REQ];
175 struct bnxt_qplib_hwq tqm_pde; 175 struct bnxt_qplib_hwq tqm_pde;
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_sp.c b/drivers/infiniband/hw/bnxt_re/qplib_sp.c
index e277e54a05eb..9543ce51a28a 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_sp.c
+++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.c
@@ -720,13 +720,12 @@ int bnxt_qplib_map_tc2cos(struct bnxt_qplib_res *res, u16 *cids)
720 struct cmdq_map_tc_to_cos req; 720 struct cmdq_map_tc_to_cos req;
721 struct creq_map_tc_to_cos_resp resp; 721 struct creq_map_tc_to_cos_resp resp;
722 u16 cmd_flags = 0; 722 u16 cmd_flags = 0;
723 int rc = 0;
724 723
725 RCFW_CMD_PREP(req, MAP_TC_TO_COS, cmd_flags); 724 RCFW_CMD_PREP(req, MAP_TC_TO_COS, cmd_flags);
726 req.cos0 = cpu_to_le16(cids[0]); 725 req.cos0 = cpu_to_le16(cids[0]);
727 req.cos1 = cpu_to_le16(cids[1]); 726 req.cos1 = cpu_to_le16(cids[1]);
728 727
729 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 728 bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, NULL,
730 (void *)&resp, NULL, 0); 729 0);
731 return 0; 730 return 0;
732} 731}
diff --git a/drivers/infiniband/hw/bnxt_re/roce_hsi.h b/drivers/infiniband/hw/bnxt_re/roce_hsi.h
index eeb55b2db57e..c3cba6063a03 100644
--- a/drivers/infiniband/hw/bnxt_re/roce_hsi.h
+++ b/drivers/infiniband/hw/bnxt_re/roce_hsi.h
@@ -2644,7 +2644,7 @@ struct creq_query_func_resp_sb {
2644 u8 l2_db_space_size; 2644 u8 l2_db_space_size;
2645 __le16 max_srq; 2645 __le16 max_srq;
2646 __le32 max_gid; 2646 __le32 max_gid;
2647 __le32 tqm_alloc_reqs[8]; 2647 __le32 tqm_alloc_reqs[12];
2648}; 2648};
2649 2649
2650/* Set resources command response (16 bytes) */ 2650/* Set resources command response (16 bytes) */
diff --git a/drivers/infiniband/hw/cxgb3/Kconfig b/drivers/infiniband/hw/cxgb3/Kconfig
index 2b6352b85485..431be733fbbe 100644
--- a/drivers/infiniband/hw/cxgb3/Kconfig
+++ b/drivers/infiniband/hw/cxgb3/Kconfig
@@ -1,6 +1,6 @@
1config INFINIBAND_CXGB3 1config INFINIBAND_CXGB3
2 tristate "Chelsio RDMA Driver" 2 tristate "Chelsio RDMA Driver"
3 depends on CHELSIO_T3 && INET 3 depends on CHELSIO_T3
4 select GENERIC_ALLOCATOR 4 select GENERIC_ALLOCATOR
5 ---help--- 5 ---help---
6 This is an iWARP/RDMA driver for the Chelsio T3 1GbE and 6 This is an iWARP/RDMA driver for the Chelsio T3 1GbE and
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c
index 3eff6541bd6f..3328acc53c2a 100644
--- a/drivers/infiniband/hw/cxgb3/cxio_hal.c
+++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c
@@ -404,12 +404,10 @@ static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
404 404
405int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count) 405int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
406{ 406{
407 __u32 ptr; 407 __u32 ptr = wq->sq_rptr + count;
408 int flushed = 0; 408 int flushed = 0;
409 struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2); 409 struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
410 410
411 ptr = wq->sq_rptr + count;
412 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
413 while (ptr != wq->sq_wptr) { 411 while (ptr != wq->sq_wptr) {
414 sqp->signaled = 0; 412 sqp->signaled = 0;
415 insert_sq_cqe(wq, cq, sqp); 413 insert_sq_cqe(wq, cq, sqp);
diff --git a/drivers/infiniband/hw/cxgb3/iwch_cm.c b/drivers/infiniband/hw/cxgb3/iwch_cm.c
index 86975370a4c0..1c90c86fc8b8 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_cm.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_cm.c
@@ -107,7 +107,7 @@ static struct workqueue_struct *workq;
107static struct sk_buff_head rxq; 107static struct sk_buff_head rxq;
108 108
109static struct sk_buff *get_skb(struct sk_buff *skb, int len, gfp_t gfp); 109static struct sk_buff *get_skb(struct sk_buff *skb, int len, gfp_t gfp);
110static void ep_timeout(unsigned long arg); 110static void ep_timeout(struct timer_list *t);
111static void connect_reply_upcall(struct iwch_ep *ep, int status); 111static void connect_reply_upcall(struct iwch_ep *ep, int status);
112 112
113static void start_ep_timer(struct iwch_ep *ep) 113static void start_ep_timer(struct iwch_ep *ep)
@@ -119,8 +119,6 @@ static void start_ep_timer(struct iwch_ep *ep)
119 } else 119 } else
120 get_ep(&ep->com); 120 get_ep(&ep->com);
121 ep->timer.expires = jiffies + ep_timeout_secs * HZ; 121 ep->timer.expires = jiffies + ep_timeout_secs * HZ;
122 ep->timer.data = (unsigned long)ep;
123 ep->timer.function = ep_timeout;
124 add_timer(&ep->timer); 122 add_timer(&ep->timer);
125} 123}
126 124
@@ -1399,7 +1397,7 @@ static int pass_accept_req(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
1399 child_ep->l2t = l2t; 1397 child_ep->l2t = l2t;
1400 child_ep->dst = dst; 1398 child_ep->dst = dst;
1401 child_ep->hwtid = hwtid; 1399 child_ep->hwtid = hwtid;
1402 init_timer(&child_ep->timer); 1400 timer_setup(&child_ep->timer, ep_timeout, 0);
1403 cxgb3_insert_tid(tdev, &t3c_client, child_ep, hwtid); 1401 cxgb3_insert_tid(tdev, &t3c_client, child_ep, hwtid);
1404 accept_cr(child_ep, req->peer_ip, skb); 1402 accept_cr(child_ep, req->peer_ip, skb);
1405 goto out; 1403 goto out;
@@ -1719,9 +1717,9 @@ static int ec_status(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
1719 return CPL_RET_BUF_DONE; 1717 return CPL_RET_BUF_DONE;
1720} 1718}
1721 1719
1722static void ep_timeout(unsigned long arg) 1720static void ep_timeout(struct timer_list *t)
1723{ 1721{
1724 struct iwch_ep *ep = (struct iwch_ep *)arg; 1722 struct iwch_ep *ep = from_timer(ep, t, timer);
1725 struct iwch_qp_attributes attrs; 1723 struct iwch_qp_attributes attrs;
1726 unsigned long flags; 1724 unsigned long flags;
1727 int abort = 1; 1725 int abort = 1;
@@ -1760,8 +1758,8 @@ static void ep_timeout(unsigned long arg)
1760 1758
1761int iwch_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len) 1759int iwch_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len)
1762{ 1760{
1763 int err;
1764 struct iwch_ep *ep = to_ep(cm_id); 1761 struct iwch_ep *ep = to_ep(cm_id);
1762
1765 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1763 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid);
1766 1764
1767 if (state_read(&ep->com) == DEAD) { 1765 if (state_read(&ep->com) == DEAD) {
@@ -1772,8 +1770,8 @@ int iwch_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len)
1772 if (mpa_rev == 0) 1770 if (mpa_rev == 0)
1773 abort_connection(ep, NULL, GFP_KERNEL); 1771 abort_connection(ep, NULL, GFP_KERNEL);
1774 else { 1772 else {
1775 err = send_mpa_reject(ep, pdata, pdata_len); 1773 send_mpa_reject(ep, pdata, pdata_len);
1776 err = iwch_ep_disconnect(ep, 0, GFP_KERNEL); 1774 iwch_ep_disconnect(ep, 0, GFP_KERNEL);
1777 } 1775 }
1778 put_ep(&ep->com); 1776 put_ep(&ep->com);
1779 return 0; 1777 return 0;
@@ -1899,7 +1897,7 @@ int iwch_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
1899 err = -ENOMEM; 1897 err = -ENOMEM;
1900 goto out; 1898 goto out;
1901 } 1899 }
1902 init_timer(&ep->timer); 1900 timer_setup(&ep->timer, ep_timeout, 0);
1903 ep->plen = conn_param->private_data_len; 1901 ep->plen = conn_param->private_data_len;
1904 if (ep->plen) 1902 if (ep->plen)
1905 memcpy(ep->mpa_pkt + sizeof(struct mpa_message), 1903 memcpy(ep->mpa_pkt + sizeof(struct mpa_message),
diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.c b/drivers/infiniband/hw/cxgb3/iwch_provider.c
index 099e76f3758a..a578ca559e11 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_provider.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_provider.c
@@ -969,7 +969,6 @@ static struct ib_qp *iwch_create_qp(struct ib_pd *pd,
969 insert_mmap(ucontext, mm2); 969 insert_mmap(ucontext, mm2);
970 } 970 }
971 qhp->ibqp.qp_num = qhp->wq.qpid; 971 qhp->ibqp.qp_num = qhp->wq.qpid;
972 init_timer(&(qhp->timer));
973 pr_debug("%s sq_num_entries %d, rq_num_entries %d qpid 0x%0x qhp %p dma_addr 0x%llx size %d rq_addr 0x%x\n", 972 pr_debug("%s sq_num_entries %d, rq_num_entries %d qpid 0x%0x qhp %p dma_addr 0x%llx size %d rq_addr 0x%x\n",
974 __func__, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, 973 __func__, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
975 qhp->wq.qpid, qhp, (unsigned long long)qhp->wq.dma_addr, 974 qhp->wq.qpid, qhp, (unsigned long long)qhp->wq.dma_addr,
diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.h b/drivers/infiniband/hw/cxgb3/iwch_provider.h
index 9e216edec4c0..2e38ddefea8a 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_provider.h
+++ b/drivers/infiniband/hw/cxgb3/iwch_provider.h
@@ -168,7 +168,6 @@ struct iwch_qp {
168 atomic_t refcnt; 168 atomic_t refcnt;
169 wait_queue_head_t wait; 169 wait_queue_head_t wait;
170 enum IWCH_QP_FLAGS flags; 170 enum IWCH_QP_FLAGS flags;
171 struct timer_list timer;
172}; 171};
173 172
174static inline int qp_quiesced(struct iwch_qp *qhp) 173static inline int qp_quiesced(struct iwch_qp *qhp)
diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c b/drivers/infiniband/hw/cxgb3/iwch_qp.c
index 7f633da0185d..3871e1fd8395 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_qp.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c
@@ -722,10 +722,13 @@ int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
722 */ 722 */
723static void __flush_qp(struct iwch_qp *qhp, struct iwch_cq *rchp, 723static void __flush_qp(struct iwch_qp *qhp, struct iwch_cq *rchp,
724 struct iwch_cq *schp) 724 struct iwch_cq *schp)
725 __releases(&qhp->lock)
726 __acquires(&qhp->lock)
725{ 727{
726 int count; 728 int count;
727 int flushed; 729 int flushed;
728 730
731 lockdep_assert_held(&qhp->lock);
729 732
730 pr_debug("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp); 733 pr_debug("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
731 /* take a ref on the qhp since we must release the lock */ 734 /* take a ref on the qhp since we must release the lock */
diff --git a/drivers/infiniband/hw/cxgb4/Kconfig b/drivers/infiniband/hw/cxgb4/Kconfig
index afe8b28e0878..0a671a61fc92 100644
--- a/drivers/infiniband/hw/cxgb4/Kconfig
+++ b/drivers/infiniband/hw/cxgb4/Kconfig
@@ -1,6 +1,6 @@
1config INFINIBAND_CXGB4 1config INFINIBAND_CXGB4
2 tristate "Chelsio T4/T5 RDMA Driver" 2 tristate "Chelsio T4/T5 RDMA Driver"
3 depends on CHELSIO_T4 && INET && (IPV6 || IPV6=n) 3 depends on CHELSIO_T4 && INET
4 select CHELSIO_LIB 4 select CHELSIO_LIB
5 select GENERIC_ALLOCATOR 5 select GENERIC_ALLOCATOR
6 ---help--- 6 ---help---
diff --git a/drivers/infiniband/hw/cxgb4/cm.c b/drivers/infiniband/hw/cxgb4/cm.c
index daf7a56e5d7e..21db3b48a617 100644
--- a/drivers/infiniband/hw/cxgb4/cm.c
+++ b/drivers/infiniband/hw/cxgb4/cm.c
@@ -99,10 +99,6 @@ module_param(enable_tcp_window_scaling, int, 0644);
99MODULE_PARM_DESC(enable_tcp_window_scaling, 99MODULE_PARM_DESC(enable_tcp_window_scaling,
100 "Enable tcp window scaling (default=1)"); 100 "Enable tcp window scaling (default=1)");
101 101
102int c4iw_debug;
103module_param(c4iw_debug, int, 0644);
104MODULE_PARM_DESC(c4iw_debug, "obsolete");
105
106static int peer2peer = 1; 102static int peer2peer = 1;
107module_param(peer2peer, int, 0644); 103module_param(peer2peer, int, 0644);
108MODULE_PARM_DESC(peer2peer, "Support peer2peer ULPs (default=1)"); 104MODULE_PARM_DESC(peer2peer, "Support peer2peer ULPs (default=1)");
@@ -144,7 +140,7 @@ static struct workqueue_struct *workq;
144static struct sk_buff_head rxq; 140static struct sk_buff_head rxq;
145 141
146static struct sk_buff *get_skb(struct sk_buff *skb, int len, gfp_t gfp); 142static struct sk_buff *get_skb(struct sk_buff *skb, int len, gfp_t gfp);
147static void ep_timeout(unsigned long arg); 143static void ep_timeout(struct timer_list *t);
148static void connect_reply_upcall(struct c4iw_ep *ep, int status); 144static void connect_reply_upcall(struct c4iw_ep *ep, int status);
149static int sched(struct c4iw_dev *dev, struct sk_buff *skb); 145static int sched(struct c4iw_dev *dev, struct sk_buff *skb);
150 146
@@ -180,7 +176,7 @@ static void ref_qp(struct c4iw_ep *ep)
180 176
181static void start_ep_timer(struct c4iw_ep *ep) 177static void start_ep_timer(struct c4iw_ep *ep)
182{ 178{
183 pr_debug("%s ep %p\n", __func__, ep); 179 pr_debug("ep %p\n", ep);
184 if (timer_pending(&ep->timer)) { 180 if (timer_pending(&ep->timer)) {
185 pr_err("%s timer already started! ep %p\n", 181 pr_err("%s timer already started! ep %p\n",
186 __func__, ep); 182 __func__, ep);
@@ -189,14 +185,12 @@ static void start_ep_timer(struct c4iw_ep *ep)
189 clear_bit(TIMEOUT, &ep->com.flags); 185 clear_bit(TIMEOUT, &ep->com.flags);
190 c4iw_get_ep(&ep->com); 186 c4iw_get_ep(&ep->com);
191 ep->timer.expires = jiffies + ep_timeout_secs * HZ; 187 ep->timer.expires = jiffies + ep_timeout_secs * HZ;
192 ep->timer.data = (unsigned long)ep;
193 ep->timer.function = ep_timeout;
194 add_timer(&ep->timer); 188 add_timer(&ep->timer);
195} 189}
196 190
197static int stop_ep_timer(struct c4iw_ep *ep) 191static int stop_ep_timer(struct c4iw_ep *ep)
198{ 192{
199 pr_debug("%s ep %p stopping\n", __func__, ep); 193 pr_debug("ep %p stopping\n", ep);
200 del_timer_sync(&ep->timer); 194 del_timer_sync(&ep->timer);
201 if (!test_and_set_bit(TIMEOUT, &ep->com.flags)) { 195 if (!test_and_set_bit(TIMEOUT, &ep->com.flags)) {
202 c4iw_put_ep(&ep->com); 196 c4iw_put_ep(&ep->com);
@@ -212,7 +206,7 @@ static int c4iw_l2t_send(struct c4iw_rdev *rdev, struct sk_buff *skb,
212 206
213 if (c4iw_fatal_error(rdev)) { 207 if (c4iw_fatal_error(rdev)) {
214 kfree_skb(skb); 208 kfree_skb(skb);
215 pr_debug("%s - device in error state - dropping\n", __func__); 209 pr_err("%s - device in error state - dropping\n", __func__);
216 return -EIO; 210 return -EIO;
217 } 211 }
218 error = cxgb4_l2t_send(rdev->lldi.ports[0], skb, l2e); 212 error = cxgb4_l2t_send(rdev->lldi.ports[0], skb, l2e);
@@ -229,7 +223,7 @@ int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb)
229 223
230 if (c4iw_fatal_error(rdev)) { 224 if (c4iw_fatal_error(rdev)) {
231 kfree_skb(skb); 225 kfree_skb(skb);
232 pr_debug("%s - device in error state - dropping\n", __func__); 226 pr_err("%s - device in error state - dropping\n", __func__);
233 return -EIO; 227 return -EIO;
234 } 228 }
235 error = cxgb4_ofld_send(rdev->lldi.ports[0], skb); 229 error = cxgb4_ofld_send(rdev->lldi.ports[0], skb);
@@ -263,10 +257,10 @@ static void set_emss(struct c4iw_ep *ep, u16 opt)
263 if (ep->emss < 128) 257 if (ep->emss < 128)
264 ep->emss = 128; 258 ep->emss = 128;
265 if (ep->emss & 7) 259 if (ep->emss & 7)
266 pr_debug("Warning: misaligned mtu idx %u mss %u emss=%u\n", 260 pr_warn("Warning: misaligned mtu idx %u mss %u emss=%u\n",
267 TCPOPT_MSS_G(opt), ep->mss, ep->emss); 261 TCPOPT_MSS_G(opt), ep->mss, ep->emss);
268 pr_debug("%s mss_idx %u mss %u emss=%u\n", __func__, TCPOPT_MSS_G(opt), 262 pr_debug("mss_idx %u mss %u emss=%u\n", TCPOPT_MSS_G(opt), ep->mss,
269 ep->mss, ep->emss); 263 ep->emss);
270} 264}
271 265
272static enum c4iw_ep_state state_read(struct c4iw_ep_common *epc) 266static enum c4iw_ep_state state_read(struct c4iw_ep_common *epc)
@@ -287,7 +281,7 @@ static void __state_set(struct c4iw_ep_common *epc, enum c4iw_ep_state new)
287static void state_set(struct c4iw_ep_common *epc, enum c4iw_ep_state new) 281static void state_set(struct c4iw_ep_common *epc, enum c4iw_ep_state new)
288{ 282{
289 mutex_lock(&epc->mutex); 283 mutex_lock(&epc->mutex);
290 pr_debug("%s - %s -> %s\n", __func__, states[epc->state], states[new]); 284 pr_debug("%s -> %s\n", states[epc->state], states[new]);
291 __state_set(epc, new); 285 __state_set(epc, new);
292 mutex_unlock(&epc->mutex); 286 mutex_unlock(&epc->mutex);
293 return; 287 return;
@@ -318,11 +312,18 @@ static void *alloc_ep(int size, gfp_t gfp)
318 312
319 epc = kzalloc(size, gfp); 313 epc = kzalloc(size, gfp);
320 if (epc) { 314 if (epc) {
315 epc->wr_waitp = c4iw_alloc_wr_wait(gfp);
316 if (!epc->wr_waitp) {
317 kfree(epc);
318 epc = NULL;
319 goto out;
320 }
321 kref_init(&epc->kref); 321 kref_init(&epc->kref);
322 mutex_init(&epc->mutex); 322 mutex_init(&epc->mutex);
323 c4iw_init_wr_wait(&epc->wr_wait); 323 c4iw_init_wr_wait(epc->wr_waitp);
324 } 324 }
325 pr_debug("%s alloc ep %p\n", __func__, epc); 325 pr_debug("alloc ep %p\n", epc);
326out:
326 return epc; 327 return epc;
327} 328}
328 329
@@ -384,7 +385,7 @@ void _c4iw_free_ep(struct kref *kref)
384 struct c4iw_ep *ep; 385 struct c4iw_ep *ep;
385 386
386 ep = container_of(kref, struct c4iw_ep, com.kref); 387 ep = container_of(kref, struct c4iw_ep, com.kref);
387 pr_debug("%s ep %p state %s\n", __func__, ep, states[ep->com.state]); 388 pr_debug("ep %p state %s\n", ep, states[ep->com.state]);
388 if (test_bit(QP_REFERENCED, &ep->com.flags)) 389 if (test_bit(QP_REFERENCED, &ep->com.flags))
389 deref_qp(ep); 390 deref_qp(ep);
390 if (test_bit(RELEASE_RESOURCES, &ep->com.flags)) { 391 if (test_bit(RELEASE_RESOURCES, &ep->com.flags)) {
@@ -407,6 +408,7 @@ void _c4iw_free_ep(struct kref *kref)
407 } 408 }
408 if (!skb_queue_empty(&ep->com.ep_skb_list)) 409 if (!skb_queue_empty(&ep->com.ep_skb_list))
409 skb_queue_purge(&ep->com.ep_skb_list); 410 skb_queue_purge(&ep->com.ep_skb_list);
411 c4iw_put_wr_wait(ep->com.wr_waitp);
410 kfree(ep); 412 kfree(ep);
411} 413}
412 414
@@ -570,7 +572,7 @@ static void abort_arp_failure(void *handle, struct sk_buff *skb)
570 struct c4iw_rdev *rdev = &ep->com.dev->rdev; 572 struct c4iw_rdev *rdev = &ep->com.dev->rdev;
571 struct cpl_abort_req *req = cplhdr(skb); 573 struct cpl_abort_req *req = cplhdr(skb);
572 574
573 pr_debug("%s rdev %p\n", __func__, rdev); 575 pr_debug("rdev %p\n", rdev);
574 req->cmd = CPL_ABORT_NO_RST; 576 req->cmd = CPL_ABORT_NO_RST;
575 skb_get(skb); 577 skb_get(skb);
576 ret = c4iw_ofld_send(rdev, skb); 578 ret = c4iw_ofld_send(rdev, skb);
@@ -647,7 +649,7 @@ static int send_halfclose(struct c4iw_ep *ep)
647 struct sk_buff *skb = skb_dequeue(&ep->com.ep_skb_list); 649 struct sk_buff *skb = skb_dequeue(&ep->com.ep_skb_list);
648 u32 wrlen = roundup(sizeof(struct cpl_close_con_req), 16); 650 u32 wrlen = roundup(sizeof(struct cpl_close_con_req), 16);
649 651
650 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 652 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
651 if (WARN_ON(!skb)) 653 if (WARN_ON(!skb))
652 return -ENOMEM; 654 return -ENOMEM;
653 655
@@ -662,7 +664,7 @@ static int send_abort(struct c4iw_ep *ep)
662 u32 wrlen = roundup(sizeof(struct cpl_abort_req), 16); 664 u32 wrlen = roundup(sizeof(struct cpl_abort_req), 16);
663 struct sk_buff *req_skb = skb_dequeue(&ep->com.ep_skb_list); 665 struct sk_buff *req_skb = skb_dequeue(&ep->com.ep_skb_list);
664 666
665 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 667 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
666 if (WARN_ON(!req_skb)) 668 if (WARN_ON(!req_skb))
667 return -ENOMEM; 669 return -ENOMEM;
668 670
@@ -725,7 +727,7 @@ static int send_connect(struct c4iw_ep *ep)
725 roundup(sizev4, 16) : 727 roundup(sizev4, 16) :
726 roundup(sizev6, 16); 728 roundup(sizev6, 16);
727 729
728 pr_debug("%s ep %p atid %u\n", __func__, ep, ep->atid); 730 pr_debug("ep %p atid %u\n", ep, ep->atid);
729 731
730 skb = get_skb(NULL, wrlen, GFP_KERNEL); 732 skb = get_skb(NULL, wrlen, GFP_KERNEL);
731 if (!skb) { 733 if (!skb) {
@@ -824,13 +826,13 @@ static int send_connect(struct c4iw_ep *ep)
824 t5req->params = 826 t5req->params =
825 cpu_to_be64(FILTER_TUPLE_V(params)); 827 cpu_to_be64(FILTER_TUPLE_V(params));
826 t5req->rsvd = cpu_to_be32(isn); 828 t5req->rsvd = cpu_to_be32(isn);
827 pr_debug("%s snd_isn %u\n", __func__, t5req->rsvd); 829 pr_debug("snd_isn %u\n", t5req->rsvd);
828 t5req->opt2 = cpu_to_be32(opt2); 830 t5req->opt2 = cpu_to_be32(opt2);
829 } else { 831 } else {
830 t6req->params = 832 t6req->params =
831 cpu_to_be64(FILTER_TUPLE_V(params)); 833 cpu_to_be64(FILTER_TUPLE_V(params));
832 t6req->rsvd = cpu_to_be32(isn); 834 t6req->rsvd = cpu_to_be32(isn);
833 pr_debug("%s snd_isn %u\n", __func__, t6req->rsvd); 835 pr_debug("snd_isn %u\n", t6req->rsvd);
834 t6req->opt2 = cpu_to_be32(opt2); 836 t6req->opt2 = cpu_to_be32(opt2);
835 } 837 }
836 } 838 }
@@ -877,13 +879,13 @@ static int send_connect(struct c4iw_ep *ep)
877 t5req6->params = 879 t5req6->params =
878 cpu_to_be64(FILTER_TUPLE_V(params)); 880 cpu_to_be64(FILTER_TUPLE_V(params));
879 t5req6->rsvd = cpu_to_be32(isn); 881 t5req6->rsvd = cpu_to_be32(isn);
880 pr_debug("%s snd_isn %u\n", __func__, t5req6->rsvd); 882 pr_debug("snd_isn %u\n", t5req6->rsvd);
881 t5req6->opt2 = cpu_to_be32(opt2); 883 t5req6->opt2 = cpu_to_be32(opt2);
882 } else { 884 } else {
883 t6req6->params = 885 t6req6->params =
884 cpu_to_be64(FILTER_TUPLE_V(params)); 886 cpu_to_be64(FILTER_TUPLE_V(params));
885 t6req6->rsvd = cpu_to_be32(isn); 887 t6req6->rsvd = cpu_to_be32(isn);
886 pr_debug("%s snd_isn %u\n", __func__, t6req6->rsvd); 888 pr_debug("snd_isn %u\n", t6req6->rsvd);
887 t6req6->opt2 = cpu_to_be32(opt2); 889 t6req6->opt2 = cpu_to_be32(opt2);
888 } 890 }
889 891
@@ -907,10 +909,8 @@ static int send_mpa_req(struct c4iw_ep *ep, struct sk_buff *skb,
907 struct mpa_message *mpa; 909 struct mpa_message *mpa;
908 struct mpa_v2_conn_params mpa_v2_params; 910 struct mpa_v2_conn_params mpa_v2_params;
909 911
910 pr_debug("%s ep %p tid %u pd_len %d\n", 912 pr_debug("ep %p tid %u pd_len %d\n",
911 __func__, ep, ep->hwtid, ep->plen); 913 ep, ep->hwtid, ep->plen);
912
913 BUG_ON(skb_cloned(skb));
914 914
915 mpalen = sizeof(*mpa) + ep->plen; 915 mpalen = sizeof(*mpa) + ep->plen;
916 if (mpa_rev_to_use == 2) 916 if (mpa_rev_to_use == 2)
@@ -961,7 +961,7 @@ static int send_mpa_req(struct c4iw_ep *ep, struct sk_buff *skb,
961 if (mpa_rev_to_use == 2) { 961 if (mpa_rev_to_use == 2) {
962 mpa->private_data_size = htons(ntohs(mpa->private_data_size) + 962 mpa->private_data_size = htons(ntohs(mpa->private_data_size) +
963 sizeof (struct mpa_v2_conn_params)); 963 sizeof (struct mpa_v2_conn_params));
964 pr_debug("%s initiator ird %u ord %u\n", __func__, ep->ird, 964 pr_debug("initiator ird %u ord %u\n", ep->ird,
965 ep->ord); 965 ep->ord);
966 mpa_v2_params.ird = htons((u16)ep->ird); 966 mpa_v2_params.ird = htons((u16)ep->ird);
967 mpa_v2_params.ord = htons((u16)ep->ord); 967 mpa_v2_params.ord = htons((u16)ep->ord);
@@ -994,7 +994,6 @@ static int send_mpa_req(struct c4iw_ep *ep, struct sk_buff *skb,
994 */ 994 */
995 skb_get(skb); 995 skb_get(skb);
996 t4_set_arp_err_handler(skb, NULL, arp_failure_discard); 996 t4_set_arp_err_handler(skb, NULL, arp_failure_discard);
997 BUG_ON(ep->mpa_skb);
998 ep->mpa_skb = skb; 997 ep->mpa_skb = skb;
999 ret = c4iw_l2t_send(&ep->com.dev->rdev, skb, ep->l2t); 998 ret = c4iw_l2t_send(&ep->com.dev->rdev, skb, ep->l2t);
1000 if (ret) 999 if (ret)
@@ -1014,8 +1013,8 @@ static int send_mpa_reject(struct c4iw_ep *ep, const void *pdata, u8 plen)
1014 struct sk_buff *skb; 1013 struct sk_buff *skb;
1015 struct mpa_v2_conn_params mpa_v2_params; 1014 struct mpa_v2_conn_params mpa_v2_params;
1016 1015
1017 pr_debug("%s ep %p tid %u pd_len %d\n", 1016 pr_debug("ep %p tid %u pd_len %d\n",
1018 __func__, ep, ep->hwtid, ep->plen); 1017 ep, ep->hwtid, ep->plen);
1019 1018
1020 mpalen = sizeof(*mpa) + plen; 1019 mpalen = sizeof(*mpa) + plen;
1021 if (ep->mpa_attr.version == 2 && ep->mpa_attr.enhanced_rdma_conn) 1020 if (ep->mpa_attr.version == 2 && ep->mpa_attr.enhanced_rdma_conn)
@@ -1080,7 +1079,6 @@ static int send_mpa_reject(struct c4iw_ep *ep, const void *pdata, u8 plen)
1080 skb_get(skb); 1079 skb_get(skb);
1081 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx); 1080 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1082 t4_set_arp_err_handler(skb, NULL, mpa_start_arp_failure); 1081 t4_set_arp_err_handler(skb, NULL, mpa_start_arp_failure);
1083 BUG_ON(ep->mpa_skb);
1084 ep->mpa_skb = skb; 1082 ep->mpa_skb = skb;
1085 ep->snd_seq += mpalen; 1083 ep->snd_seq += mpalen;
1086 return c4iw_l2t_send(&ep->com.dev->rdev, skb, ep->l2t); 1084 return c4iw_l2t_send(&ep->com.dev->rdev, skb, ep->l2t);
@@ -1094,8 +1092,8 @@ static int send_mpa_reply(struct c4iw_ep *ep, const void *pdata, u8 plen)
1094 struct sk_buff *skb; 1092 struct sk_buff *skb;
1095 struct mpa_v2_conn_params mpa_v2_params; 1093 struct mpa_v2_conn_params mpa_v2_params;
1096 1094
1097 pr_debug("%s ep %p tid %u pd_len %d\n", 1095 pr_debug("ep %p tid %u pd_len %d\n",
1098 __func__, ep, ep->hwtid, ep->plen); 1096 ep, ep->hwtid, ep->plen);
1099 1097
1100 mpalen = sizeof(*mpa) + plen; 1098 mpalen = sizeof(*mpa) + plen;
1101 if (ep->mpa_attr.version == 2 && ep->mpa_attr.enhanced_rdma_conn) 1099 if (ep->mpa_attr.version == 2 && ep->mpa_attr.enhanced_rdma_conn)
@@ -1185,7 +1183,7 @@ static int act_establish(struct c4iw_dev *dev, struct sk_buff *skb)
1185 1183
1186 ep = lookup_atid(t, atid); 1184 ep = lookup_atid(t, atid);
1187 1185
1188 pr_debug("%s ep %p tid %u snd_isn %u rcv_isn %u\n", __func__, ep, tid, 1186 pr_debug("ep %p tid %u snd_isn %u rcv_isn %u\n", ep, tid,
1189 be32_to_cpu(req->snd_isn), be32_to_cpu(req->rcv_isn)); 1187 be32_to_cpu(req->snd_isn), be32_to_cpu(req->rcv_isn));
1190 1188
1191 mutex_lock(&ep->com.mutex); 1189 mutex_lock(&ep->com.mutex);
@@ -1229,7 +1227,7 @@ static void close_complete_upcall(struct c4iw_ep *ep, int status)
1229{ 1227{
1230 struct iw_cm_event event; 1228 struct iw_cm_event event;
1231 1229
1232 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1230 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1233 memset(&event, 0, sizeof(event)); 1231 memset(&event, 0, sizeof(event));
1234 event.event = IW_CM_EVENT_CLOSE; 1232 event.event = IW_CM_EVENT_CLOSE;
1235 event.status = status; 1233 event.status = status;
@@ -1246,7 +1244,7 @@ static void peer_close_upcall(struct c4iw_ep *ep)
1246{ 1244{
1247 struct iw_cm_event event; 1245 struct iw_cm_event event;
1248 1246
1249 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1247 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1250 memset(&event, 0, sizeof(event)); 1248 memset(&event, 0, sizeof(event));
1251 event.event = IW_CM_EVENT_DISCONNECT; 1249 event.event = IW_CM_EVENT_DISCONNECT;
1252 if (ep->com.cm_id) { 1250 if (ep->com.cm_id) {
@@ -1261,7 +1259,7 @@ static void peer_abort_upcall(struct c4iw_ep *ep)
1261{ 1259{
1262 struct iw_cm_event event; 1260 struct iw_cm_event event;
1263 1261
1264 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1262 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1265 memset(&event, 0, sizeof(event)); 1263 memset(&event, 0, sizeof(event));
1266 event.event = IW_CM_EVENT_CLOSE; 1264 event.event = IW_CM_EVENT_CLOSE;
1267 event.status = -ECONNRESET; 1265 event.status = -ECONNRESET;
@@ -1278,8 +1276,8 @@ static void connect_reply_upcall(struct c4iw_ep *ep, int status)
1278{ 1276{
1279 struct iw_cm_event event; 1277 struct iw_cm_event event;
1280 1278
1281 pr_debug("%s ep %p tid %u status %d\n", 1279 pr_debug("ep %p tid %u status %d\n",
1282 __func__, ep, ep->hwtid, status); 1280 ep, ep->hwtid, status);
1283 memset(&event, 0, sizeof(event)); 1281 memset(&event, 0, sizeof(event));
1284 event.event = IW_CM_EVENT_CONNECT_REPLY; 1282 event.event = IW_CM_EVENT_CONNECT_REPLY;
1285 event.status = status; 1283 event.status = status;
@@ -1308,7 +1306,7 @@ static void connect_reply_upcall(struct c4iw_ep *ep, int status)
1308 } 1306 }
1309 } 1307 }
1310 1308
1311 pr_debug("%s ep %p tid %u status %d\n", __func__, ep, 1309 pr_debug("ep %p tid %u status %d\n", ep,
1312 ep->hwtid, status); 1310 ep->hwtid, status);
1313 set_bit(CONN_RPL_UPCALL, &ep->com.history); 1311 set_bit(CONN_RPL_UPCALL, &ep->com.history);
1314 ep->com.cm_id->event_handler(ep->com.cm_id, &event); 1312 ep->com.cm_id->event_handler(ep->com.cm_id, &event);
@@ -1322,7 +1320,7 @@ static int connect_request_upcall(struct c4iw_ep *ep)
1322 struct iw_cm_event event; 1320 struct iw_cm_event event;
1323 int ret; 1321 int ret;
1324 1322
1325 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1323 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1326 memset(&event, 0, sizeof(event)); 1324 memset(&event, 0, sizeof(event));
1327 event.event = IW_CM_EVENT_CONNECT_REQUEST; 1325 event.event = IW_CM_EVENT_CONNECT_REQUEST;
1328 memcpy(&event.local_addr, &ep->com.local_addr, 1326 memcpy(&event.local_addr, &ep->com.local_addr,
@@ -1359,13 +1357,13 @@ static void established_upcall(struct c4iw_ep *ep)
1359{ 1357{
1360 struct iw_cm_event event; 1358 struct iw_cm_event event;
1361 1359
1362 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1360 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1363 memset(&event, 0, sizeof(event)); 1361 memset(&event, 0, sizeof(event));
1364 event.event = IW_CM_EVENT_ESTABLISHED; 1362 event.event = IW_CM_EVENT_ESTABLISHED;
1365 event.ird = ep->ord; 1363 event.ird = ep->ord;
1366 event.ord = ep->ird; 1364 event.ord = ep->ird;
1367 if (ep->com.cm_id) { 1365 if (ep->com.cm_id) {
1368 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1366 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1369 ep->com.cm_id->event_handler(ep->com.cm_id, &event); 1367 ep->com.cm_id->event_handler(ep->com.cm_id, &event);
1370 set_bit(ESTAB_UPCALL, &ep->com.history); 1368 set_bit(ESTAB_UPCALL, &ep->com.history);
1371 } 1369 }
@@ -1377,8 +1375,8 @@ static int update_rx_credits(struct c4iw_ep *ep, u32 credits)
1377 u32 wrlen = roundup(sizeof(struct cpl_rx_data_ack), 16); 1375 u32 wrlen = roundup(sizeof(struct cpl_rx_data_ack), 16);
1378 u32 credit_dack; 1376 u32 credit_dack;
1379 1377
1380 pr_debug("%s ep %p tid %u credits %u\n", 1378 pr_debug("ep %p tid %u credits %u\n",
1381 __func__, ep, ep->hwtid, credits); 1379 ep, ep->hwtid, credits);
1382 skb = get_skb(NULL, wrlen, GFP_KERNEL); 1380 skb = get_skb(NULL, wrlen, GFP_KERNEL);
1383 if (!skb) { 1381 if (!skb) {
1384 pr_err("update_rx_credits - cannot alloc skb!\n"); 1382 pr_err("update_rx_credits - cannot alloc skb!\n");
@@ -1429,7 +1427,7 @@ static int process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
1429 int err; 1427 int err;
1430 int disconnect = 0; 1428 int disconnect = 0;
1431 1429
1432 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1430 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1433 1431
1434 /* 1432 /*
1435 * If we get more than the supported amount of private data 1433 * If we get more than the supported amount of private data
@@ -1527,8 +1525,7 @@ static int process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
1527 MPA_V2_IRD_ORD_MASK; 1525 MPA_V2_IRD_ORD_MASK;
1528 resp_ord = ntohs(mpa_v2_params->ord) & 1526 resp_ord = ntohs(mpa_v2_params->ord) &
1529 MPA_V2_IRD_ORD_MASK; 1527 MPA_V2_IRD_ORD_MASK;
1530 pr_debug("%s responder ird %u ord %u ep ird %u ord %u\n", 1528 pr_debug("responder ird %u ord %u ep ird %u ord %u\n",
1531 __func__,
1532 resp_ird, resp_ord, ep->ird, ep->ord); 1529 resp_ird, resp_ord, ep->ird, ep->ord);
1533 1530
1534 /* 1531 /*
@@ -1573,8 +1570,8 @@ static int process_mpa_reply(struct c4iw_ep *ep, struct sk_buff *skb)
1573 if (peer2peer) 1570 if (peer2peer)
1574 ep->mpa_attr.p2p_type = p2p_type; 1571 ep->mpa_attr.p2p_type = p2p_type;
1575 1572
1576 pr_debug("%s - crc_enabled=%d, recv_marker_enabled=%d, xmit_marker_enabled=%d, version=%d p2p_type=%d local-p2p_type = %d\n", 1573 pr_debug("crc_enabled=%d, recv_marker_enabled=%d, xmit_marker_enabled=%d, version=%d p2p_type=%d local-p2p_type = %d\n",
1577 __func__, ep->mpa_attr.crc_enabled, 1574 ep->mpa_attr.crc_enabled,
1578 ep->mpa_attr.recv_marker_enabled, 1575 ep->mpa_attr.recv_marker_enabled,
1579 ep->mpa_attr.xmit_marker_enabled, ep->mpa_attr.version, 1576 ep->mpa_attr.xmit_marker_enabled, ep->mpa_attr.version,
1580 ep->mpa_attr.p2p_type, p2p_type); 1577 ep->mpa_attr.p2p_type, p2p_type);
@@ -1670,7 +1667,7 @@ static int process_mpa_request(struct c4iw_ep *ep, struct sk_buff *skb)
1670 struct mpa_v2_conn_params *mpa_v2_params; 1667 struct mpa_v2_conn_params *mpa_v2_params;
1671 u16 plen; 1668 u16 plen;
1672 1669
1673 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1670 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1674 1671
1675 /* 1672 /*
1676 * If we get more than the supported amount of private data 1673 * If we get more than the supported amount of private data
@@ -1679,7 +1676,7 @@ static int process_mpa_request(struct c4iw_ep *ep, struct sk_buff *skb)
1679 if (ep->mpa_pkt_len + skb->len > sizeof(ep->mpa_pkt)) 1676 if (ep->mpa_pkt_len + skb->len > sizeof(ep->mpa_pkt))
1680 goto err_stop_timer; 1677 goto err_stop_timer;
1681 1678
1682 pr_debug("%s enter (%s line %u)\n", __func__, __FILE__, __LINE__); 1679 pr_debug("enter (%s line %u)\n", __FILE__, __LINE__);
1683 1680
1684 /* 1681 /*
1685 * Copy the new data into our accumulation buffer. 1682 * Copy the new data into our accumulation buffer.
@@ -1695,7 +1692,7 @@ static int process_mpa_request(struct c4iw_ep *ep, struct sk_buff *skb)
1695 if (ep->mpa_pkt_len < sizeof(*mpa)) 1692 if (ep->mpa_pkt_len < sizeof(*mpa))
1696 return 0; 1693 return 0;
1697 1694
1698 pr_debug("%s enter (%s line %u)\n", __func__, __FILE__, __LINE__); 1695 pr_debug("enter (%s line %u)\n", __FILE__, __LINE__);
1699 mpa = (struct mpa_message *) ep->mpa_pkt; 1696 mpa = (struct mpa_message *) ep->mpa_pkt;
1700 1697
1701 /* 1698 /*
@@ -1758,8 +1755,8 @@ static int process_mpa_request(struct c4iw_ep *ep, struct sk_buff *skb)
1758 MPA_V2_IRD_ORD_MASK; 1755 MPA_V2_IRD_ORD_MASK;
1759 ep->ord = min_t(u32, ep->ord, 1756 ep->ord = min_t(u32, ep->ord,
1760 cur_max_read_depth(ep->com.dev)); 1757 cur_max_read_depth(ep->com.dev));
1761 pr_debug("%s initiator ird %u ord %u\n", 1758 pr_debug("initiator ird %u ord %u\n",
1762 __func__, ep->ird, ep->ord); 1759 ep->ird, ep->ord);
1763 if (ntohs(mpa_v2_params->ird) & MPA_V2_PEER2PEER_MODEL) 1760 if (ntohs(mpa_v2_params->ird) & MPA_V2_PEER2PEER_MODEL)
1764 if (peer2peer) { 1761 if (peer2peer) {
1765 if (ntohs(mpa_v2_params->ord) & 1762 if (ntohs(mpa_v2_params->ord) &
@@ -1776,8 +1773,7 @@ static int process_mpa_request(struct c4iw_ep *ep, struct sk_buff *skb)
1776 if (peer2peer) 1773 if (peer2peer)
1777 ep->mpa_attr.p2p_type = p2p_type; 1774 ep->mpa_attr.p2p_type = p2p_type;
1778 1775
1779 pr_debug("%s - crc_enabled=%d, recv_marker_enabled=%d, xmit_marker_enabled=%d, version=%d p2p_type=%d\n", 1776 pr_debug("crc_enabled=%d, recv_marker_enabled=%d, xmit_marker_enabled=%d, version=%d p2p_type=%d\n",
1780 __func__,
1781 ep->mpa_attr.crc_enabled, ep->mpa_attr.recv_marker_enabled, 1777 ep->mpa_attr.crc_enabled, ep->mpa_attr.recv_marker_enabled,
1782 ep->mpa_attr.xmit_marker_enabled, ep->mpa_attr.version, 1778 ep->mpa_attr.xmit_marker_enabled, ep->mpa_attr.version,
1783 ep->mpa_attr.p2p_type); 1779 ep->mpa_attr.p2p_type);
@@ -1816,7 +1812,7 @@ static int rx_data(struct c4iw_dev *dev, struct sk_buff *skb)
1816 ep = get_ep_from_tid(dev, tid); 1812 ep = get_ep_from_tid(dev, tid);
1817 if (!ep) 1813 if (!ep)
1818 return 0; 1814 return 0;
1819 pr_debug("%s ep %p tid %u dlen %u\n", __func__, ep, ep->hwtid, dlen); 1815 pr_debug("ep %p tid %u dlen %u\n", ep, ep->hwtid, dlen);
1820 skb_pull(skb, sizeof(*hdr)); 1816 skb_pull(skb, sizeof(*hdr));
1821 skb_trim(skb, dlen); 1817 skb_trim(skb, dlen);
1822 mutex_lock(&ep->com.mutex); 1818 mutex_lock(&ep->com.mutex);
@@ -1836,7 +1832,6 @@ static int rx_data(struct c4iw_dev *dev, struct sk_buff *skb)
1836 struct c4iw_qp_attributes attrs; 1832 struct c4iw_qp_attributes attrs;
1837 1833
1838 update_rx_credits(ep, dlen); 1834 update_rx_credits(ep, dlen);
1839 BUG_ON(!ep->com.qp);
1840 if (status) 1835 if (status)
1841 pr_err("%s Unexpected streaming data." \ 1836 pr_err("%s Unexpected streaming data." \
1842 " qpid %u ep %p state %d tid %u status %d\n", 1837 " qpid %u ep %p state %d tid %u status %d\n",
@@ -1870,11 +1865,11 @@ static int abort_rpl(struct c4iw_dev *dev, struct sk_buff *skb)
1870 pr_warn("Abort rpl to freed endpoint\n"); 1865 pr_warn("Abort rpl to freed endpoint\n");
1871 return 0; 1866 return 0;
1872 } 1867 }
1873 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 1868 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
1874 mutex_lock(&ep->com.mutex); 1869 mutex_lock(&ep->com.mutex);
1875 switch (ep->com.state) { 1870 switch (ep->com.state) {
1876 case ABORTING: 1871 case ABORTING:
1877 c4iw_wake_up(&ep->com.wr_wait, -ECONNRESET); 1872 c4iw_wake_up_noref(ep->com.wr_waitp, -ECONNRESET);
1878 __state_set(&ep->com, DEAD); 1873 __state_set(&ep->com, DEAD);
1879 release = 1; 1874 release = 1;
1880 break; 1875 break;
@@ -1994,8 +1989,8 @@ static void set_tcp_window(struct c4iw_ep *ep, struct port_info *pi)
1994{ 1989{
1995 ep->snd_win = snd_win; 1990 ep->snd_win = snd_win;
1996 ep->rcv_win = rcv_win; 1991 ep->rcv_win = rcv_win;
1997 pr_debug("%s snd_win %d rcv_win %d\n", 1992 pr_debug("snd_win %d rcv_win %d\n",
1998 __func__, ep->snd_win, ep->rcv_win); 1993 ep->snd_win, ep->rcv_win);
1999} 1994}
2000 1995
2001#define ACT_OPEN_RETRY_COUNT 2 1996#define ACT_OPEN_RETRY_COUNT 2
@@ -2100,9 +2095,8 @@ static int c4iw_reconnect(struct c4iw_ep *ep)
2100 int iptype; 2095 int iptype;
2101 __u8 *ra; 2096 __u8 *ra;
2102 2097
2103 pr_debug("%s qp %p cm_id %p\n", __func__, ep->com.qp, ep->com.cm_id); 2098 pr_debug("qp %p cm_id %p\n", ep->com.qp, ep->com.cm_id);
2104 init_timer(&ep->timer); 2099 c4iw_init_wr_wait(ep->com.wr_waitp);
2105 c4iw_init_wr_wait(&ep->com.wr_wait);
2106 2100
2107 /* When MPA revision is different on nodes, the node with MPA_rev=2 2101 /* When MPA revision is different on nodes, the node with MPA_rev=2
2108 * tries to reconnect with MPA_rev 1 for the same EP through 2102 * tries to reconnect with MPA_rev 1 for the same EP through
@@ -2110,7 +2104,7 @@ static int c4iw_reconnect(struct c4iw_ep *ep)
2110 * further connection establishment. As we are using the same EP pointer 2104 * further connection establishment. As we are using the same EP pointer
2111 * for reconnect, few skbs are used during the previous c4iw_connect(), 2105 * for reconnect, few skbs are used during the previous c4iw_connect(),
2112 * which leaves the EP with inadequate skbs for further 2106 * which leaves the EP with inadequate skbs for further
2113 * c4iw_reconnect(), Further causing an assert BUG_ON() due to empty 2107 * c4iw_reconnect(), Further causing a crash due to an empty
2114 * skb_list() during peer_abort(). Allocate skbs which is already used. 2108 * skb_list() during peer_abort(). Allocate skbs which is already used.
2115 */ 2109 */
2116 size = (CN_MAX_CON_BUF - skb_queue_len(&ep->com.ep_skb_list)); 2110 size = (CN_MAX_CON_BUF - skb_queue_len(&ep->com.ep_skb_list));
@@ -2163,8 +2157,8 @@ static int c4iw_reconnect(struct c4iw_ep *ep)
2163 goto fail4; 2157 goto fail4;
2164 } 2158 }
2165 2159
2166 pr_debug("%s txq_idx %u tx_chan %u smac_idx %u rss_qid %u l2t_idx %u\n", 2160 pr_debug("txq_idx %u tx_chan %u smac_idx %u rss_qid %u l2t_idx %u\n",
2167 __func__, ep->txq_idx, ep->tx_chan, ep->smac_idx, ep->rss_qid, 2161 ep->txq_idx, ep->tx_chan, ep->smac_idx, ep->rss_qid,
2168 ep->l2t->idx); 2162 ep->l2t->idx);
2169 2163
2170 state_set(&ep->com, CONNECTING); 2164 state_set(&ep->com, CONNECTING);
@@ -2215,12 +2209,12 @@ static int act_open_rpl(struct c4iw_dev *dev, struct sk_buff *skb)
2215 la6 = (struct sockaddr_in6 *)&ep->com.local_addr; 2209 la6 = (struct sockaddr_in6 *)&ep->com.local_addr;
2216 ra6 = (struct sockaddr_in6 *)&ep->com.remote_addr; 2210 ra6 = (struct sockaddr_in6 *)&ep->com.remote_addr;
2217 2211
2218 pr_debug("%s ep %p atid %u status %u errno %d\n", __func__, ep, atid, 2212 pr_debug("ep %p atid %u status %u errno %d\n", ep, atid,
2219 status, status2errno(status)); 2213 status, status2errno(status));
2220 2214
2221 if (cxgb_is_neg_adv(status)) { 2215 if (cxgb_is_neg_adv(status)) {
2222 pr_debug("%s Connection problems for atid %u status %u (%s)\n", 2216 pr_debug("Connection problems for atid %u status %u (%s)\n",
2223 __func__, atid, status, neg_adv_str(status)); 2217 atid, status, neg_adv_str(status));
2224 ep->stats.connect_neg_adv++; 2218 ep->stats.connect_neg_adv++;
2225 mutex_lock(&dev->rdev.stats.lock); 2219 mutex_lock(&dev->rdev.stats.lock);
2226 dev->rdev.stats.neg_adv++; 2220 dev->rdev.stats.neg_adv++;
@@ -2316,12 +2310,12 @@ static int pass_open_rpl(struct c4iw_dev *dev, struct sk_buff *skb)
2316 struct c4iw_listen_ep *ep = get_ep_from_stid(dev, stid); 2310 struct c4iw_listen_ep *ep = get_ep_from_stid(dev, stid);
2317 2311
2318 if (!ep) { 2312 if (!ep) {
2319 pr_debug("%s stid %d lookup failure!\n", __func__, stid); 2313 pr_warn("%s stid %d lookup failure!\n", __func__, stid);
2320 goto out; 2314 goto out;
2321 } 2315 }
2322 pr_debug("%s ep %p status %d error %d\n", __func__, ep, 2316 pr_debug("ep %p status %d error %d\n", ep,
2323 rpl->status, status2errno(rpl->status)); 2317 rpl->status, status2errno(rpl->status));
2324 c4iw_wake_up(&ep->com.wr_wait, status2errno(rpl->status)); 2318 c4iw_wake_up_noref(ep->com.wr_waitp, status2errno(rpl->status));
2325 c4iw_put_ep(&ep->com); 2319 c4iw_put_ep(&ep->com);
2326out: 2320out:
2327 return 0; 2321 return 0;
@@ -2334,11 +2328,11 @@ static int close_listsrv_rpl(struct c4iw_dev *dev, struct sk_buff *skb)
2334 struct c4iw_listen_ep *ep = get_ep_from_stid(dev, stid); 2328 struct c4iw_listen_ep *ep = get_ep_from_stid(dev, stid);
2335 2329
2336 if (!ep) { 2330 if (!ep) {
2337 pr_debug("%s stid %d lookup failure!\n", __func__, stid); 2331 pr_warn("%s stid %d lookup failure!\n", __func__, stid);
2338 goto out; 2332 goto out;
2339 } 2333 }
2340 pr_debug("%s ep %p\n", __func__, ep); 2334 pr_debug("ep %p\n", ep);
2341 c4iw_wake_up(&ep->com.wr_wait, status2errno(rpl->status)); 2335 c4iw_wake_up_noref(ep->com.wr_waitp, status2errno(rpl->status));
2342 c4iw_put_ep(&ep->com); 2336 c4iw_put_ep(&ep->com);
2343out: 2337out:
2344 return 0; 2338 return 0;
@@ -2356,8 +2350,7 @@ static int accept_cr(struct c4iw_ep *ep, struct sk_buff *skb,
2356 int win; 2350 int win;
2357 enum chip_type adapter_type = ep->com.dev->rdev.lldi.adapter_type; 2351 enum chip_type adapter_type = ep->com.dev->rdev.lldi.adapter_type;
2358 2352
2359 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 2353 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
2360 BUG_ON(skb_cloned(skb));
2361 2354
2362 skb_get(skb); 2355 skb_get(skb);
2363 rpl = cplhdr(skb); 2356 rpl = cplhdr(skb);
@@ -2427,7 +2420,7 @@ static int accept_cr(struct c4iw_ep *ep, struct sk_buff *skb,
2427 if (peer2peer) 2420 if (peer2peer)
2428 isn += 4; 2421 isn += 4;
2429 rpl5->iss = cpu_to_be32(isn); 2422 rpl5->iss = cpu_to_be32(isn);
2430 pr_debug("%s iss %u\n", __func__, be32_to_cpu(rpl5->iss)); 2423 pr_debug("iss %u\n", be32_to_cpu(rpl5->iss));
2431 } 2424 }
2432 2425
2433 rpl->opt0 = cpu_to_be64(opt0); 2426 rpl->opt0 = cpu_to_be64(opt0);
@@ -2440,8 +2433,7 @@ static int accept_cr(struct c4iw_ep *ep, struct sk_buff *skb,
2440 2433
2441static void reject_cr(struct c4iw_dev *dev, u32 hwtid, struct sk_buff *skb) 2434static void reject_cr(struct c4iw_dev *dev, u32 hwtid, struct sk_buff *skb)
2442{ 2435{
2443 pr_debug("%s c4iw_dev %p tid %u\n", __func__, dev, hwtid); 2436 pr_debug("c4iw_dev %p tid %u\n", dev, hwtid);
2444 BUG_ON(skb_cloned(skb));
2445 skb_trim(skb, sizeof(struct cpl_tid_release)); 2437 skb_trim(skb, sizeof(struct cpl_tid_release));
2446 release_tid(&dev->rdev, hwtid, skb); 2438 release_tid(&dev->rdev, hwtid, skb);
2447 return; 2439 return;
@@ -2466,13 +2458,13 @@ static int pass_accept_req(struct c4iw_dev *dev, struct sk_buff *skb)
2466 2458
2467 parent_ep = (struct c4iw_ep *)get_ep_from_stid(dev, stid); 2459 parent_ep = (struct c4iw_ep *)get_ep_from_stid(dev, stid);
2468 if (!parent_ep) { 2460 if (!parent_ep) {
2469 pr_debug("%s connect request on invalid stid %d\n", 2461 pr_err("%s connect request on invalid stid %d\n",
2470 __func__, stid); 2462 __func__, stid);
2471 goto reject; 2463 goto reject;
2472 } 2464 }
2473 2465
2474 if (state_read(&parent_ep->com) != LISTEN) { 2466 if (state_read(&parent_ep->com) != LISTEN) {
2475 pr_debug("%s - listening ep not in LISTEN\n", __func__); 2467 pr_err("%s - listening ep not in LISTEN\n", __func__);
2476 goto reject; 2468 goto reject;
2477 } 2469 }
2478 2470
@@ -2481,16 +2473,16 @@ static int pass_accept_req(struct c4iw_dev *dev, struct sk_buff *skb)
2481 2473
2482 /* Find output route */ 2474 /* Find output route */
2483 if (iptype == 4) { 2475 if (iptype == 4) {
2484 pr_debug("%s parent ep %p hwtid %u laddr %pI4 raddr %pI4 lport %d rport %d peer_mss %d\n" 2476 pr_debug("parent ep %p hwtid %u laddr %pI4 raddr %pI4 lport %d rport %d peer_mss %d\n"
2485 , __func__, parent_ep, hwtid, 2477 , parent_ep, hwtid,
2486 local_ip, peer_ip, ntohs(local_port), 2478 local_ip, peer_ip, ntohs(local_port),
2487 ntohs(peer_port), peer_mss); 2479 ntohs(peer_port), peer_mss);
2488 dst = cxgb_find_route(&dev->rdev.lldi, get_real_dev, 2480 dst = cxgb_find_route(&dev->rdev.lldi, get_real_dev,
2489 *(__be32 *)local_ip, *(__be32 *)peer_ip, 2481 *(__be32 *)local_ip, *(__be32 *)peer_ip,
2490 local_port, peer_port, tos); 2482 local_port, peer_port, tos);
2491 } else { 2483 } else {
2492 pr_debug("%s parent ep %p hwtid %u laddr %pI6 raddr %pI6 lport %d rport %d peer_mss %d\n" 2484 pr_debug("parent ep %p hwtid %u laddr %pI6 raddr %pI6 lport %d rport %d peer_mss %d\n"
2493 , __func__, parent_ep, hwtid, 2485 , parent_ep, hwtid,
2494 local_ip, peer_ip, ntohs(local_port), 2486 local_ip, peer_ip, ntohs(local_port),
2495 ntohs(peer_port), peer_mss); 2487 ntohs(peer_port), peer_mss);
2496 dst = cxgb_find_route6(&dev->rdev.lldi, get_real_dev, 2488 dst = cxgb_find_route6(&dev->rdev.lldi, get_real_dev,
@@ -2576,10 +2568,10 @@ static int pass_accept_req(struct c4iw_dev *dev, struct sk_buff *skb)
2576 child_ep->dst = dst; 2568 child_ep->dst = dst;
2577 child_ep->hwtid = hwtid; 2569 child_ep->hwtid = hwtid;
2578 2570
2579 pr_debug("%s tx_chan %u smac_idx %u rss_qid %u\n", __func__, 2571 pr_debug("tx_chan %u smac_idx %u rss_qid %u\n",
2580 child_ep->tx_chan, child_ep->smac_idx, child_ep->rss_qid); 2572 child_ep->tx_chan, child_ep->smac_idx, child_ep->rss_qid);
2581 2573
2582 init_timer(&child_ep->timer); 2574 timer_setup(&child_ep->timer, ep_timeout, 0);
2583 cxgb4_insert_tid(t, child_ep, hwtid, 2575 cxgb4_insert_tid(t, child_ep, hwtid,
2584 child_ep->com.local_addr.ss_family); 2576 child_ep->com.local_addr.ss_family);
2585 insert_ep_tid(child_ep); 2577 insert_ep_tid(child_ep);
@@ -2613,11 +2605,11 @@ static int pass_establish(struct c4iw_dev *dev, struct sk_buff *skb)
2613 int ret; 2605 int ret;
2614 2606
2615 ep = get_ep_from_tid(dev, tid); 2607 ep = get_ep_from_tid(dev, tid);
2616 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 2608 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
2617 ep->snd_seq = be32_to_cpu(req->snd_isn); 2609 ep->snd_seq = be32_to_cpu(req->snd_isn);
2618 ep->rcv_seq = be32_to_cpu(req->rcv_isn); 2610 ep->rcv_seq = be32_to_cpu(req->rcv_isn);
2619 2611
2620 pr_debug("%s ep %p hwtid %u tcp_opt 0x%02x\n", __func__, ep, tid, 2612 pr_debug("ep %p hwtid %u tcp_opt 0x%02x\n", ep, tid,
2621 ntohs(req->tcp_opt)); 2613 ntohs(req->tcp_opt));
2622 2614
2623 set_emss(ep, ntohs(req->tcp_opt)); 2615 set_emss(ep, ntohs(req->tcp_opt));
@@ -2650,7 +2642,7 @@ static int peer_close(struct c4iw_dev *dev, struct sk_buff *skb)
2650 if (!ep) 2642 if (!ep)
2651 return 0; 2643 return 0;
2652 2644
2653 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 2645 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
2654 dst_confirm(ep->dst); 2646 dst_confirm(ep->dst);
2655 2647
2656 set_bit(PEER_CLOSE, &ep->com.history); 2648 set_bit(PEER_CLOSE, &ep->com.history);
@@ -2673,12 +2665,12 @@ static int peer_close(struct c4iw_dev *dev, struct sk_buff *skb)
2673 */ 2665 */
2674 __state_set(&ep->com, CLOSING); 2666 __state_set(&ep->com, CLOSING);
2675 pr_debug("waking up ep %p tid %u\n", ep, ep->hwtid); 2667 pr_debug("waking up ep %p tid %u\n", ep, ep->hwtid);
2676 c4iw_wake_up(&ep->com.wr_wait, -ECONNRESET); 2668 c4iw_wake_up_noref(ep->com.wr_waitp, -ECONNRESET);
2677 break; 2669 break;
2678 case MPA_REP_SENT: 2670 case MPA_REP_SENT:
2679 __state_set(&ep->com, CLOSING); 2671 __state_set(&ep->com, CLOSING);
2680 pr_debug("waking up ep %p tid %u\n", ep, ep->hwtid); 2672 pr_debug("waking up ep %p tid %u\n", ep, ep->hwtid);
2681 c4iw_wake_up(&ep->com.wr_wait, -ECONNRESET); 2673 c4iw_wake_up_noref(ep->com.wr_waitp, -ECONNRESET);
2682 break; 2674 break;
2683 case FPDU_MODE: 2675 case FPDU_MODE:
2684 start_ep_timer(ep); 2676 start_ep_timer(ep);
@@ -2714,7 +2706,7 @@ static int peer_close(struct c4iw_dev *dev, struct sk_buff *skb)
2714 disconnect = 0; 2706 disconnect = 0;
2715 break; 2707 break;
2716 default: 2708 default:
2717 BUG_ON(1); 2709 WARN_ONCE(1, "Bad endpoint state %u\n", ep->com.state);
2718 } 2710 }
2719 mutex_unlock(&ep->com.mutex); 2711 mutex_unlock(&ep->com.mutex);
2720 if (disconnect) 2712 if (disconnect)
@@ -2741,16 +2733,16 @@ static int peer_abort(struct c4iw_dev *dev, struct sk_buff *skb)
2741 return 0; 2733 return 0;
2742 2734
2743 if (cxgb_is_neg_adv(req->status)) { 2735 if (cxgb_is_neg_adv(req->status)) {
2744 pr_debug("%s Negative advice on abort- tid %u status %d (%s)\n", 2736 pr_warn("%s Negative advice on abort- tid %u status %d (%s)\n",
2745 __func__, ep->hwtid, req->status, 2737 __func__, ep->hwtid, req->status,
2746 neg_adv_str(req->status)); 2738 neg_adv_str(req->status));
2747 ep->stats.abort_neg_adv++; 2739 ep->stats.abort_neg_adv++;
2748 mutex_lock(&dev->rdev.stats.lock); 2740 mutex_lock(&dev->rdev.stats.lock);
2749 dev->rdev.stats.neg_adv++; 2741 dev->rdev.stats.neg_adv++;
2750 mutex_unlock(&dev->rdev.stats.lock); 2742 mutex_unlock(&dev->rdev.stats.lock);
2751 goto deref_ep; 2743 goto deref_ep;
2752 } 2744 }
2753 pr_debug("%s ep %p tid %u state %u\n", __func__, ep, ep->hwtid, 2745 pr_debug("ep %p tid %u state %u\n", ep, ep->hwtid,
2754 ep->com.state); 2746 ep->com.state);
2755 set_bit(PEER_ABORT, &ep->com.history); 2747 set_bit(PEER_ABORT, &ep->com.history);
2756 2748
@@ -2760,7 +2752,7 @@ static int peer_abort(struct c4iw_dev *dev, struct sk_buff *skb)
2760 * MPA_REQ_SENT 2752 * MPA_REQ_SENT
2761 */ 2753 */
2762 if (ep->com.state != MPA_REQ_SENT) 2754 if (ep->com.state != MPA_REQ_SENT)
2763 c4iw_wake_up(&ep->com.wr_wait, -ECONNRESET); 2755 c4iw_wake_up_noref(ep->com.wr_waitp, -ECONNRESET);
2764 2756
2765 mutex_lock(&ep->com.mutex); 2757 mutex_lock(&ep->com.mutex);
2766 switch (ep->com.state) { 2758 switch (ep->com.state) {
@@ -2783,8 +2775,8 @@ static int peer_abort(struct c4iw_dev *dev, struct sk_buff *skb)
2783 * do some housekeeping so as to re-initiate the 2775 * do some housekeeping so as to re-initiate the
2784 * connection 2776 * connection
2785 */ 2777 */
2786 pr_debug("%s: mpa_rev=%d. Retrying with mpav1\n", 2778 pr_info("%s: mpa_rev=%d. Retrying with mpav1\n",
2787 __func__, mpa_rev); 2779 __func__, mpa_rev);
2788 ep->retry_with_mpa_v1 = 1; 2780 ep->retry_with_mpa_v1 = 1;
2789 } 2781 }
2790 break; 2782 break;
@@ -2810,11 +2802,11 @@ static int peer_abort(struct c4iw_dev *dev, struct sk_buff *skb)
2810 case ABORTING: 2802 case ABORTING:
2811 break; 2803 break;
2812 case DEAD: 2804 case DEAD:
2813 pr_debug("%s PEER_ABORT IN DEAD STATE!!!!\n", __func__); 2805 pr_warn("%s PEER_ABORT IN DEAD STATE!!!!\n", __func__);
2814 mutex_unlock(&ep->com.mutex); 2806 mutex_unlock(&ep->com.mutex);
2815 goto deref_ep; 2807 goto deref_ep;
2816 default: 2808 default:
2817 BUG_ON(1); 2809 WARN_ONCE(1, "Bad endpoint state %u\n", ep->com.state);
2818 break; 2810 break;
2819 } 2811 }
2820 dst_confirm(ep->dst); 2812 dst_confirm(ep->dst);
@@ -2875,7 +2867,7 @@ static int close_con_rpl(struct c4iw_dev *dev, struct sk_buff *skb)
2875 if (!ep) 2867 if (!ep)
2876 return 0; 2868 return 0;
2877 2869
2878 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 2870 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
2879 2871
2880 /* The cm_id may be null if we failed to connect */ 2872 /* The cm_id may be null if we failed to connect */
2881 mutex_lock(&ep->com.mutex); 2873 mutex_lock(&ep->com.mutex);
@@ -2901,7 +2893,7 @@ static int close_con_rpl(struct c4iw_dev *dev, struct sk_buff *skb)
2901 case DEAD: 2893 case DEAD:
2902 break; 2894 break;
2903 default: 2895 default:
2904 BUG_ON(1); 2896 WARN_ONCE(1, "Bad endpoint state %u\n", ep->com.state);
2905 break; 2897 break;
2906 } 2898 }
2907 mutex_unlock(&ep->com.mutex); 2899 mutex_unlock(&ep->com.mutex);
@@ -2919,7 +2911,6 @@ static int terminate(struct c4iw_dev *dev, struct sk_buff *skb)
2919 struct c4iw_qp_attributes attrs; 2911 struct c4iw_qp_attributes attrs;
2920 2912
2921 ep = get_ep_from_tid(dev, tid); 2913 ep = get_ep_from_tid(dev, tid);
2922 BUG_ON(!ep);
2923 2914
2924 if (ep && ep->com.qp) { 2915 if (ep && ep->com.qp) {
2925 pr_warn("TERM received tid %u qpid %u\n", 2916 pr_warn("TERM received tid %u qpid %u\n",
@@ -2950,19 +2941,19 @@ static int fw4_ack(struct c4iw_dev *dev, struct sk_buff *skb)
2950 ep = get_ep_from_tid(dev, tid); 2941 ep = get_ep_from_tid(dev, tid);
2951 if (!ep) 2942 if (!ep)
2952 return 0; 2943 return 0;
2953 pr_debug("%s ep %p tid %u credits %u\n", 2944 pr_debug("ep %p tid %u credits %u\n",
2954 __func__, ep, ep->hwtid, credits); 2945 ep, ep->hwtid, credits);
2955 if (credits == 0) { 2946 if (credits == 0) {
2956 pr_debug("%s 0 credit ack ep %p tid %u state %u\n", 2947 pr_debug("0 credit ack ep %p tid %u state %u\n",
2957 __func__, ep, ep->hwtid, state_read(&ep->com)); 2948 ep, ep->hwtid, state_read(&ep->com));
2958 goto out; 2949 goto out;
2959 } 2950 }
2960 2951
2961 dst_confirm(ep->dst); 2952 dst_confirm(ep->dst);
2962 if (ep->mpa_skb) { 2953 if (ep->mpa_skb) {
2963 pr_debug("%s last streaming msg ack ep %p tid %u state %u initiator %u freeing skb\n", 2954 pr_debug("last streaming msg ack ep %p tid %u state %u initiator %u freeing skb\n",
2964 __func__, ep, ep->hwtid, 2955 ep, ep->hwtid, state_read(&ep->com),
2965 state_read(&ep->com), ep->mpa_attr.initiator ? 1 : 0); 2956 ep->mpa_attr.initiator ? 1 : 0);
2966 mutex_lock(&ep->com.mutex); 2957 mutex_lock(&ep->com.mutex);
2967 kfree_skb(ep->mpa_skb); 2958 kfree_skb(ep->mpa_skb);
2968 ep->mpa_skb = NULL; 2959 ep->mpa_skb = NULL;
@@ -2980,7 +2971,7 @@ int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len)
2980 int abort; 2971 int abort;
2981 struct c4iw_ep *ep = to_ep(cm_id); 2972 struct c4iw_ep *ep = to_ep(cm_id);
2982 2973
2983 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 2974 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
2984 2975
2985 mutex_lock(&ep->com.mutex); 2976 mutex_lock(&ep->com.mutex);
2986 if (ep->com.state != MPA_REQ_RCVD) { 2977 if (ep->com.state != MPA_REQ_RCVD) {
@@ -3011,7 +3002,7 @@ int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3011 struct c4iw_qp *qp = get_qhp(h, conn_param->qpn); 3002 struct c4iw_qp *qp = get_qhp(h, conn_param->qpn);
3012 int abort = 0; 3003 int abort = 0;
3013 3004
3014 pr_debug("%s ep %p tid %u\n", __func__, ep, ep->hwtid); 3005 pr_debug("ep %p tid %u\n", ep, ep->hwtid);
3015 3006
3016 mutex_lock(&ep->com.mutex); 3007 mutex_lock(&ep->com.mutex);
3017 if (ep->com.state != MPA_REQ_RCVD) { 3008 if (ep->com.state != MPA_REQ_RCVD) {
@@ -3019,7 +3010,10 @@ int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3019 goto err_out; 3010 goto err_out;
3020 } 3011 }
3021 3012
3022 BUG_ON(!qp); 3013 if (!qp) {
3014 err = -EINVAL;
3015 goto err_out;
3016 }
3023 3017
3024 set_bit(ULP_ACCEPT, &ep->com.history); 3018 set_bit(ULP_ACCEPT, &ep->com.history);
3025 if ((conn_param->ord > cur_max_read_depth(ep->com.dev)) || 3019 if ((conn_param->ord > cur_max_read_depth(ep->com.dev)) ||
@@ -3064,7 +3058,7 @@ int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3064 ep->ird = 1; 3058 ep->ird = 1;
3065 } 3059 }
3066 3060
3067 pr_debug("%s %d ird %d ord %d\n", __func__, __LINE__, ep->ird, ep->ord); 3061 pr_debug("ird %d ord %d\n", ep->ird, ep->ord);
3068 3062
3069 ep->com.cm_id = cm_id; 3063 ep->com.cm_id = cm_id;
3070 ref_cm_id(&ep->com); 3064 ref_cm_id(&ep->com);
@@ -3204,7 +3198,7 @@ int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3204 goto fail1; 3198 goto fail1;
3205 } 3199 }
3206 3200
3207 init_timer(&ep->timer); 3201 timer_setup(&ep->timer, ep_timeout, 0);
3208 ep->plen = conn_param->private_data_len; 3202 ep->plen = conn_param->private_data_len;
3209 if (ep->plen) 3203 if (ep->plen)
3210 memcpy(ep->mpa_pkt + sizeof(struct mpa_message), 3204 memcpy(ep->mpa_pkt + sizeof(struct mpa_message),
@@ -3220,12 +3214,12 @@ int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3220 ep->com.dev = dev; 3214 ep->com.dev = dev;
3221 ep->com.qp = get_qhp(dev, conn_param->qpn); 3215 ep->com.qp = get_qhp(dev, conn_param->qpn);
3222 if (!ep->com.qp) { 3216 if (!ep->com.qp) {
3223 pr_debug("%s qpn 0x%x not found!\n", __func__, conn_param->qpn); 3217 pr_warn("%s qpn 0x%x not found!\n", __func__, conn_param->qpn);
3224 err = -EINVAL; 3218 err = -EINVAL;
3225 goto fail2; 3219 goto fail2;
3226 } 3220 }
3227 ref_qp(ep); 3221 ref_qp(ep);
3228 pr_debug("%s qpn 0x%x qp %p cm_id %p\n", __func__, conn_param->qpn, 3222 pr_debug("qpn 0x%x qp %p cm_id %p\n", conn_param->qpn,
3229 ep->com.qp, cm_id); 3223 ep->com.qp, cm_id);
3230 3224
3231 /* 3225 /*
@@ -3263,8 +3257,8 @@ int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3263 } 3257 }
3264 3258
3265 /* find a route */ 3259 /* find a route */
3266 pr_debug("%s saddr %pI4 sport 0x%x raddr %pI4 rport 0x%x\n", 3260 pr_debug("saddr %pI4 sport 0x%x raddr %pI4 rport 0x%x\n",
3267 __func__, &laddr->sin_addr, ntohs(laddr->sin_port), 3261 &laddr->sin_addr, ntohs(laddr->sin_port),
3268 ra, ntohs(raddr->sin_port)); 3262 ra, ntohs(raddr->sin_port));
3269 ep->dst = cxgb_find_route(&dev->rdev.lldi, get_real_dev, 3263 ep->dst = cxgb_find_route(&dev->rdev.lldi, get_real_dev,
3270 laddr->sin_addr.s_addr, 3264 laddr->sin_addr.s_addr,
@@ -3285,8 +3279,8 @@ int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3285 } 3279 }
3286 3280
3287 /* find a route */ 3281 /* find a route */
3288 pr_debug("%s saddr %pI6 sport 0x%x raddr %pI6 rport 0x%x\n", 3282 pr_debug("saddr %pI6 sport 0x%x raddr %pI6 rport 0x%x\n",
3289 __func__, laddr6->sin6_addr.s6_addr, 3283 laddr6->sin6_addr.s6_addr,
3290 ntohs(laddr6->sin6_port), 3284 ntohs(laddr6->sin6_port),
3291 raddr6->sin6_addr.s6_addr, ntohs(raddr6->sin6_port)); 3285 raddr6->sin6_addr.s6_addr, ntohs(raddr6->sin6_port));
3292 ep->dst = cxgb_find_route6(&dev->rdev.lldi, get_real_dev, 3286 ep->dst = cxgb_find_route6(&dev->rdev.lldi, get_real_dev,
@@ -3309,8 +3303,8 @@ int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3309 goto fail4; 3303 goto fail4;
3310 } 3304 }
3311 3305
3312 pr_debug("%s txq_idx %u tx_chan %u smac_idx %u rss_qid %u l2t_idx %u\n", 3306 pr_debug("txq_idx %u tx_chan %u smac_idx %u rss_qid %u l2t_idx %u\n",
3313 __func__, ep->txq_idx, ep->tx_chan, ep->smac_idx, ep->rss_qid, 3307 ep->txq_idx, ep->tx_chan, ep->smac_idx, ep->rss_qid,
3314 ep->l2t->idx); 3308 ep->l2t->idx);
3315 3309
3316 state_set(&ep->com, CONNECTING); 3310 state_set(&ep->com, CONNECTING);
@@ -3348,14 +3342,14 @@ static int create_server6(struct c4iw_dev *dev, struct c4iw_listen_ep *ep)
3348 if (err) 3342 if (err)
3349 return err; 3343 return err;
3350 } 3344 }
3351 c4iw_init_wr_wait(&ep->com.wr_wait); 3345 c4iw_init_wr_wait(ep->com.wr_waitp);
3352 err = cxgb4_create_server6(ep->com.dev->rdev.lldi.ports[0], 3346 err = cxgb4_create_server6(ep->com.dev->rdev.lldi.ports[0],
3353 ep->stid, &sin6->sin6_addr, 3347 ep->stid, &sin6->sin6_addr,
3354 sin6->sin6_port, 3348 sin6->sin6_port,
3355 ep->com.dev->rdev.lldi.rxq_ids[0]); 3349 ep->com.dev->rdev.lldi.rxq_ids[0]);
3356 if (!err) 3350 if (!err)
3357 err = c4iw_wait_for_reply(&ep->com.dev->rdev, 3351 err = c4iw_wait_for_reply(&ep->com.dev->rdev,
3358 &ep->com.wr_wait, 3352 ep->com.wr_waitp,
3359 0, 0, __func__); 3353 0, 0, __func__);
3360 else if (err > 0) 3354 else if (err > 0)
3361 err = net_xmit_errno(err); 3355 err = net_xmit_errno(err);
@@ -3391,13 +3385,13 @@ static int create_server4(struct c4iw_dev *dev, struct c4iw_listen_ep *ep)
3391 } 3385 }
3392 } while (err == -EBUSY); 3386 } while (err == -EBUSY);
3393 } else { 3387 } else {
3394 c4iw_init_wr_wait(&ep->com.wr_wait); 3388 c4iw_init_wr_wait(ep->com.wr_waitp);
3395 err = cxgb4_create_server(ep->com.dev->rdev.lldi.ports[0], 3389 err = cxgb4_create_server(ep->com.dev->rdev.lldi.ports[0],
3396 ep->stid, sin->sin_addr.s_addr, sin->sin_port, 3390 ep->stid, sin->sin_addr.s_addr, sin->sin_port,
3397 0, ep->com.dev->rdev.lldi.rxq_ids[0]); 3391 0, ep->com.dev->rdev.lldi.rxq_ids[0]);
3398 if (!err) 3392 if (!err)
3399 err = c4iw_wait_for_reply(&ep->com.dev->rdev, 3393 err = c4iw_wait_for_reply(&ep->com.dev->rdev,
3400 &ep->com.wr_wait, 3394 ep->com.wr_waitp,
3401 0, 0, __func__); 3395 0, 0, __func__);
3402 else if (err > 0) 3396 else if (err > 0)
3403 err = net_xmit_errno(err); 3397 err = net_xmit_errno(err);
@@ -3424,7 +3418,7 @@ int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog)
3424 goto fail1; 3418 goto fail1;
3425 } 3419 }
3426 skb_queue_head_init(&ep->com.ep_skb_list); 3420 skb_queue_head_init(&ep->com.ep_skb_list);
3427 pr_debug("%s ep %p\n", __func__, ep); 3421 pr_debug("ep %p\n", ep);
3428 ep->com.cm_id = cm_id; 3422 ep->com.cm_id = cm_id;
3429 ref_cm_id(&ep->com); 3423 ref_cm_id(&ep->com);
3430 ep->com.dev = dev; 3424 ep->com.dev = dev;
@@ -3478,7 +3472,7 @@ int c4iw_destroy_listen(struct iw_cm_id *cm_id)
3478 int err; 3472 int err;
3479 struct c4iw_listen_ep *ep = to_listen_ep(cm_id); 3473 struct c4iw_listen_ep *ep = to_listen_ep(cm_id);
3480 3474
3481 pr_debug("%s ep %p\n", __func__, ep); 3475 pr_debug("ep %p\n", ep);
3482 3476
3483 might_sleep(); 3477 might_sleep();
3484 state_set(&ep->com, DEAD); 3478 state_set(&ep->com, DEAD);
@@ -3489,13 +3483,13 @@ int c4iw_destroy_listen(struct iw_cm_id *cm_id)
3489 ep->com.dev->rdev.lldi.rxq_ids[0], 0); 3483 ep->com.dev->rdev.lldi.rxq_ids[0], 0);
3490 } else { 3484 } else {
3491 struct sockaddr_in6 *sin6; 3485 struct sockaddr_in6 *sin6;
3492 c4iw_init_wr_wait(&ep->com.wr_wait); 3486 c4iw_init_wr_wait(ep->com.wr_waitp);
3493 err = cxgb4_remove_server( 3487 err = cxgb4_remove_server(
3494 ep->com.dev->rdev.lldi.ports[0], ep->stid, 3488 ep->com.dev->rdev.lldi.ports[0], ep->stid,
3495 ep->com.dev->rdev.lldi.rxq_ids[0], 0); 3489 ep->com.dev->rdev.lldi.rxq_ids[0], 0);
3496 if (err) 3490 if (err)
3497 goto done; 3491 goto done;
3498 err = c4iw_wait_for_reply(&ep->com.dev->rdev, &ep->com.wr_wait, 3492 err = c4iw_wait_for_reply(&ep->com.dev->rdev, ep->com.wr_waitp,
3499 0, 0, __func__); 3493 0, 0, __func__);
3500 sin6 = (struct sockaddr_in6 *)&ep->com.local_addr; 3494 sin6 = (struct sockaddr_in6 *)&ep->com.local_addr;
3501 cxgb4_clip_release(ep->com.dev->rdev.lldi.ports[0], 3495 cxgb4_clip_release(ep->com.dev->rdev.lldi.ports[0],
@@ -3519,7 +3513,7 @@ int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp)
3519 3513
3520 mutex_lock(&ep->com.mutex); 3514 mutex_lock(&ep->com.mutex);
3521 3515
3522 pr_debug("%s ep %p state %s, abrupt %d\n", __func__, ep, 3516 pr_debug("ep %p state %s, abrupt %d\n", ep,
3523 states[ep->com.state], abrupt); 3517 states[ep->com.state], abrupt);
3524 3518
3525 /* 3519 /*
@@ -3573,11 +3567,11 @@ int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp)
3573 case MORIBUND: 3567 case MORIBUND:
3574 case ABORTING: 3568 case ABORTING:
3575 case DEAD: 3569 case DEAD:
3576 pr_debug("%s ignoring disconnect ep %p state %u\n", 3570 pr_info("%s ignoring disconnect ep %p state %u\n",
3577 __func__, ep, ep->com.state); 3571 __func__, ep, ep->com.state);
3578 break; 3572 break;
3579 default: 3573 default:
3580 BUG(); 3574 WARN_ONCE(1, "Bad endpoint state %u\n", ep->com.state);
3581 break; 3575 break;
3582 } 3576 }
3583 3577
@@ -3636,6 +3630,7 @@ static void active_ofld_conn_reply(struct c4iw_dev *dev, struct sk_buff *skb,
3636 send_fw_act_open_req(ep, atid); 3630 send_fw_act_open_req(ep, atid);
3637 return; 3631 return;
3638 } 3632 }
3633 /* fall through */
3639 case FW_EADDRINUSE: 3634 case FW_EADDRINUSE:
3640 set_bit(ACT_RETRY_INUSE, &ep->com.history); 3635 set_bit(ACT_RETRY_INUSE, &ep->com.history);
3641 if (ep->retry_count++ < ACT_OPEN_RETRY_COUNT) { 3636 if (ep->retry_count++ < ACT_OPEN_RETRY_COUNT) {
@@ -3676,9 +3671,8 @@ static void passive_ofld_conn_reply(struct c4iw_dev *dev, struct sk_buff *skb,
3676 int ret; 3671 int ret;
3677 3672
3678 rpl_skb = (struct sk_buff *)(unsigned long)req->cookie; 3673 rpl_skb = (struct sk_buff *)(unsigned long)req->cookie;
3679 BUG_ON(!rpl_skb);
3680 if (req->retval) { 3674 if (req->retval) {
3681 pr_debug("%s passive open failure %d\n", __func__, req->retval); 3675 pr_err("%s passive open failure %d\n", __func__, req->retval);
3682 mutex_lock(&dev->rdev.stats.lock); 3676 mutex_lock(&dev->rdev.stats.lock);
3683 dev->rdev.stats.pas_ofld_conn_fails++; 3677 dev->rdev.stats.pas_ofld_conn_fails++;
3684 mutex_unlock(&dev->rdev.stats.lock); 3678 mutex_unlock(&dev->rdev.stats.lock);
@@ -3874,7 +3868,6 @@ static int rx_pkt(struct c4iw_dev *dev, struct sk_buff *skb)
3874 struct net_device *pdev; 3868 struct net_device *pdev;
3875 u16 rss_qid, eth_hdr_len; 3869 u16 rss_qid, eth_hdr_len;
3876 int step; 3870 int step;
3877 u32 tx_chan;
3878 struct neighbour *neigh; 3871 struct neighbour *neigh;
3879 3872
3880 /* Drop all non-SYN packets */ 3873 /* Drop all non-SYN packets */
@@ -3895,8 +3888,8 @@ static int rx_pkt(struct c4iw_dev *dev, struct sk_buff *skb)
3895 3888
3896 lep = (struct c4iw_ep *)get_ep_from_stid(dev, stid); 3889 lep = (struct c4iw_ep *)get_ep_from_stid(dev, stid);
3897 if (!lep) { 3890 if (!lep) {
3898 pr_debug("%s connect request on invalid stid %d\n", 3891 pr_warn("%s connect request on invalid stid %d\n",
3899 __func__, stid); 3892 __func__, stid);
3900 goto reject; 3893 goto reject;
3901 } 3894 }
3902 3895
@@ -3933,7 +3926,7 @@ static int rx_pkt(struct c4iw_dev *dev, struct sk_buff *skb)
3933 skb_set_transport_header(skb, (void *)tcph - (void *)rss); 3926 skb_set_transport_header(skb, (void *)tcph - (void *)rss);
3934 skb_get(skb); 3927 skb_get(skb);
3935 3928
3936 pr_debug("%s lip 0x%x lport %u pip 0x%x pport %u tos %d\n", __func__, 3929 pr_debug("lip 0x%x lport %u pip 0x%x pport %u tos %d\n",
3937 ntohl(iph->daddr), ntohs(tcph->dest), ntohl(iph->saddr), 3930 ntohl(iph->daddr), ntohs(tcph->dest), ntohl(iph->saddr),
3938 ntohs(tcph->source), iph->tos); 3931 ntohs(tcph->source), iph->tos);
3939 3932
@@ -3941,15 +3934,13 @@ static int rx_pkt(struct c4iw_dev *dev, struct sk_buff *skb)
3941 iph->daddr, iph->saddr, tcph->dest, 3934 iph->daddr, iph->saddr, tcph->dest,
3942 tcph->source, iph->tos); 3935 tcph->source, iph->tos);
3943 if (!dst) { 3936 if (!dst) {
3944 pr_err("%s - failed to find dst entry!\n", 3937 pr_err("%s - failed to find dst entry!\n", __func__);
3945 __func__);
3946 goto reject; 3938 goto reject;
3947 } 3939 }
3948 neigh = dst_neigh_lookup_skb(dst, skb); 3940 neigh = dst_neigh_lookup_skb(dst, skb);
3949 3941
3950 if (!neigh) { 3942 if (!neigh) {
3951 pr_err("%s - failed to allocate neigh!\n", 3943 pr_err("%s - failed to allocate neigh!\n", __func__);
3952 __func__);
3953 goto free_dst; 3944 goto free_dst;
3954 } 3945 }
3955 3946
@@ -3958,14 +3949,12 @@ static int rx_pkt(struct c4iw_dev *dev, struct sk_buff *skb)
3958 e = cxgb4_l2t_get(dev->rdev.lldi.l2t, neigh, 3949 e = cxgb4_l2t_get(dev->rdev.lldi.l2t, neigh,
3959 pdev, 0); 3950 pdev, 0);
3960 pi = (struct port_info *)netdev_priv(pdev); 3951 pi = (struct port_info *)netdev_priv(pdev);
3961 tx_chan = cxgb4_port_chan(pdev);
3962 dev_put(pdev); 3952 dev_put(pdev);
3963 } else { 3953 } else {
3964 pdev = get_real_dev(neigh->dev); 3954 pdev = get_real_dev(neigh->dev);
3965 e = cxgb4_l2t_get(dev->rdev.lldi.l2t, neigh, 3955 e = cxgb4_l2t_get(dev->rdev.lldi.l2t, neigh,
3966 pdev, 0); 3956 pdev, 0);
3967 pi = (struct port_info *)netdev_priv(pdev); 3957 pi = (struct port_info *)netdev_priv(pdev);
3968 tx_chan = cxgb4_port_chan(pdev);
3969 } 3958 }
3970 neigh_release(neigh); 3959 neigh_release(neigh);
3971 if (!e) { 3960 if (!e) {
@@ -4032,8 +4021,7 @@ static void process_timeout(struct c4iw_ep *ep)
4032 int abort = 1; 4021 int abort = 1;
4033 4022
4034 mutex_lock(&ep->com.mutex); 4023 mutex_lock(&ep->com.mutex);
4035 pr_debug("%s ep %p tid %u state %d\n", __func__, ep, ep->hwtid, 4024 pr_debug("ep %p tid %u state %d\n", ep, ep->hwtid, ep->com.state);
4036 ep->com.state);
4037 set_bit(TIMEDOUT, &ep->com.history); 4025 set_bit(TIMEDOUT, &ep->com.history);
4038 switch (ep->com.state) { 4026 switch (ep->com.state) {
4039 case MPA_REQ_SENT: 4027 case MPA_REQ_SENT:
@@ -4109,7 +4097,6 @@ static void process_work(struct work_struct *work)
4109 dev = *((struct c4iw_dev **) (skb->cb + sizeof(void *))); 4097 dev = *((struct c4iw_dev **) (skb->cb + sizeof(void *)));
4110 opcode = rpl->ot.opcode; 4098 opcode = rpl->ot.opcode;
4111 4099
4112 BUG_ON(!work_handlers[opcode]);
4113 ret = work_handlers[opcode](dev, skb); 4100 ret = work_handlers[opcode](dev, skb);
4114 if (!ret) 4101 if (!ret)
4115 kfree_skb(skb); 4102 kfree_skb(skb);
@@ -4119,9 +4106,9 @@ static void process_work(struct work_struct *work)
4119 4106
4120static DECLARE_WORK(skb_work, process_work); 4107static DECLARE_WORK(skb_work, process_work);
4121 4108
4122static void ep_timeout(unsigned long arg) 4109static void ep_timeout(struct timer_list *t)
4123{ 4110{
4124 struct c4iw_ep *ep = (struct c4iw_ep *)arg; 4111 struct c4iw_ep *ep = from_timer(ep, t, timer);
4125 int kickit = 0; 4112 int kickit = 0;
4126 4113
4127 spin_lock(&timeout_lock); 4114 spin_lock(&timeout_lock);
@@ -4176,15 +4163,15 @@ static int fw6_msg(struct c4iw_dev *dev, struct sk_buff *skb)
4176 struct c4iw_wr_wait *wr_waitp; 4163 struct c4iw_wr_wait *wr_waitp;
4177 int ret; 4164 int ret;
4178 4165
4179 pr_debug("%s type %u\n", __func__, rpl->type); 4166 pr_debug("type %u\n", rpl->type);
4180 4167
4181 switch (rpl->type) { 4168 switch (rpl->type) {
4182 case FW6_TYPE_WR_RPL: 4169 case FW6_TYPE_WR_RPL:
4183 ret = (int)((be64_to_cpu(rpl->data[0]) >> 8) & 0xff); 4170 ret = (int)((be64_to_cpu(rpl->data[0]) >> 8) & 0xff);
4184 wr_waitp = (struct c4iw_wr_wait *)(__force unsigned long) rpl->data[1]; 4171 wr_waitp = (struct c4iw_wr_wait *)(__force unsigned long) rpl->data[1];
4185 pr_debug("%s wr_waitp %p ret %u\n", __func__, wr_waitp, ret); 4172 pr_debug("wr_waitp %p ret %u\n", wr_waitp, ret);
4186 if (wr_waitp) 4173 if (wr_waitp)
4187 c4iw_wake_up(wr_waitp, ret ? -ret : 0); 4174 c4iw_wake_up_deref(wr_waitp, ret ? -ret : 0);
4188 kfree_skb(skb); 4175 kfree_skb(skb);
4189 break; 4176 break;
4190 case FW6_TYPE_CQE: 4177 case FW6_TYPE_CQE:
@@ -4214,15 +4201,14 @@ static int peer_abort_intr(struct c4iw_dev *dev, struct sk_buff *skb)
4214 return 0; 4201 return 0;
4215 } 4202 }
4216 if (cxgb_is_neg_adv(req->status)) { 4203 if (cxgb_is_neg_adv(req->status)) {
4217 pr_debug("%s Negative advice on abort- tid %u status %d (%s)\n", 4204 pr_warn("%s Negative advice on abort- tid %u status %d (%s)\n",
4218 __func__, ep->hwtid, req->status, 4205 __func__, ep->hwtid, req->status,
4219 neg_adv_str(req->status)); 4206 neg_adv_str(req->status));
4220 goto out; 4207 goto out;
4221 } 4208 }
4222 pr_debug("%s ep %p tid %u state %u\n", __func__, ep, ep->hwtid, 4209 pr_debug("ep %p tid %u state %u\n", ep, ep->hwtid, ep->com.state);
4223 ep->com.state);
4224 4210
4225 c4iw_wake_up(&ep->com.wr_wait, -ECONNRESET); 4211 c4iw_wake_up_noref(ep->com.wr_waitp, -ECONNRESET);
4226out: 4212out:
4227 sched(dev, skb); 4213 sched(dev, skb);
4228 return 0; 4214 return 0;
diff --git a/drivers/infiniband/hw/cxgb4/cq.c b/drivers/infiniband/hw/cxgb4/cq.c
index be07da1997e6..ea55e95cd2c5 100644
--- a/drivers/infiniband/hw/cxgb4/cq.c
+++ b/drivers/infiniband/hw/cxgb4/cq.c
@@ -33,12 +33,12 @@
33#include "iw_cxgb4.h" 33#include "iw_cxgb4.h"
34 34
35static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq, 35static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
36 struct c4iw_dev_ucontext *uctx, struct sk_buff *skb) 36 struct c4iw_dev_ucontext *uctx, struct sk_buff *skb,
37 struct c4iw_wr_wait *wr_waitp)
37{ 38{
38 struct fw_ri_res_wr *res_wr; 39 struct fw_ri_res_wr *res_wr;
39 struct fw_ri_res *res; 40 struct fw_ri_res *res;
40 int wr_len; 41 int wr_len;
41 struct c4iw_wr_wait wr_wait;
42 int ret; 42 int ret;
43 43
44 wr_len = sizeof *res_wr + sizeof *res; 44 wr_len = sizeof *res_wr + sizeof *res;
@@ -50,17 +50,14 @@ static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
50 FW_RI_RES_WR_NRES_V(1) | 50 FW_RI_RES_WR_NRES_V(1) |
51 FW_WR_COMPL_F); 51 FW_WR_COMPL_F);
52 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 52 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
53 res_wr->cookie = (uintptr_t)&wr_wait; 53 res_wr->cookie = (uintptr_t)wr_waitp;
54 res = res_wr->res; 54 res = res_wr->res;
55 res->u.cq.restype = FW_RI_RES_TYPE_CQ; 55 res->u.cq.restype = FW_RI_RES_TYPE_CQ;
56 res->u.cq.op = FW_RI_RES_OP_RESET; 56 res->u.cq.op = FW_RI_RES_OP_RESET;
57 res->u.cq.iqid = cpu_to_be32(cq->cqid); 57 res->u.cq.iqid = cpu_to_be32(cq->cqid);
58 58
59 c4iw_init_wr_wait(&wr_wait); 59 c4iw_init_wr_wait(wr_waitp);
60 ret = c4iw_ofld_send(rdev, skb); 60 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
61 if (!ret) {
62 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
63 }
64 61
65 kfree(cq->sw_queue); 62 kfree(cq->sw_queue);
66 dma_free_coherent(&(rdev->lldi.pdev->dev), 63 dma_free_coherent(&(rdev->lldi.pdev->dev),
@@ -71,13 +68,13 @@ static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
71} 68}
72 69
73static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq, 70static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
74 struct c4iw_dev_ucontext *uctx) 71 struct c4iw_dev_ucontext *uctx,
72 struct c4iw_wr_wait *wr_waitp)
75{ 73{
76 struct fw_ri_res_wr *res_wr; 74 struct fw_ri_res_wr *res_wr;
77 struct fw_ri_res *res; 75 struct fw_ri_res *res;
78 int wr_len; 76 int wr_len;
79 int user = (uctx != &rdev->uctx); 77 int user = (uctx != &rdev->uctx);
80 struct c4iw_wr_wait wr_wait;
81 int ret; 78 int ret;
82 struct sk_buff *skb; 79 struct sk_buff *skb;
83 80
@@ -119,7 +116,7 @@ static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
119 FW_RI_RES_WR_NRES_V(1) | 116 FW_RI_RES_WR_NRES_V(1) |
120 FW_WR_COMPL_F); 117 FW_WR_COMPL_F);
121 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 118 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
122 res_wr->cookie = (uintptr_t)&wr_wait; 119 res_wr->cookie = (uintptr_t)wr_waitp;
123 res = res_wr->res; 120 res = res_wr->res;
124 res->u.cq.restype = FW_RI_RES_TYPE_CQ; 121 res->u.cq.restype = FW_RI_RES_TYPE_CQ;
125 res->u.cq.op = FW_RI_RES_OP_WRITE; 122 res->u.cq.op = FW_RI_RES_OP_WRITE;
@@ -139,13 +136,8 @@ static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
139 res->u.cq.iqsize = cpu_to_be16(cq->size); 136 res->u.cq.iqsize = cpu_to_be16(cq->size);
140 res->u.cq.iqaddr = cpu_to_be64(cq->dma_addr); 137 res->u.cq.iqaddr = cpu_to_be64(cq->dma_addr);
141 138
142 c4iw_init_wr_wait(&wr_wait); 139 c4iw_init_wr_wait(wr_waitp);
143 140 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
144 ret = c4iw_ofld_send(rdev, skb);
145 if (ret)
146 goto err4;
147 pr_debug("%s wait_event wr_wait %p\n", __func__, &wr_wait);
148 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
149 if (ret) 141 if (ret)
150 goto err4; 142 goto err4;
151 143
@@ -178,7 +170,7 @@ static void insert_recv_cqe(struct t4_wq *wq, struct t4_cq *cq)
178{ 170{
179 struct t4_cqe cqe; 171 struct t4_cqe cqe;
180 172
181 pr_debug("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__, 173 pr_debug("wq %p cq %p sw_cidx %u sw_pidx %u\n",
182 wq, cq, cq->sw_cidx, cq->sw_pidx); 174 wq, cq, cq->sw_cidx, cq->sw_pidx);
183 memset(&cqe, 0, sizeof(cqe)); 175 memset(&cqe, 0, sizeof(cqe));
184 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) | 176 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
@@ -196,8 +188,7 @@ int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count)
196 int flushed = 0; 188 int flushed = 0;
197 int in_use = wq->rq.in_use - count; 189 int in_use = wq->rq.in_use - count;
198 190
199 BUG_ON(in_use < 0); 191 pr_debug("wq %p cq %p rq.in_use %u skip count %u\n",
200 pr_debug("%s wq %p cq %p rq.in_use %u skip count %u\n", __func__,
201 wq, cq, wq->rq.in_use, count); 192 wq, cq, wq->rq.in_use, count);
202 while (in_use--) { 193 while (in_use--) {
203 insert_recv_cqe(wq, cq); 194 insert_recv_cqe(wq, cq);
@@ -211,7 +202,7 @@ static void insert_sq_cqe(struct t4_wq *wq, struct t4_cq *cq,
211{ 202{
212 struct t4_cqe cqe; 203 struct t4_cqe cqe;
213 204
214 pr_debug("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__, 205 pr_debug("wq %p cq %p sw_cidx %u sw_pidx %u\n",
215 wq, cq, cq->sw_cidx, cq->sw_pidx); 206 wq, cq, cq->sw_cidx, cq->sw_pidx);
216 memset(&cqe, 0, sizeof(cqe)); 207 memset(&cqe, 0, sizeof(cqe));
217 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) | 208 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
@@ -239,14 +230,11 @@ int c4iw_flush_sq(struct c4iw_qp *qhp)
239 if (wq->sq.flush_cidx == -1) 230 if (wq->sq.flush_cidx == -1)
240 wq->sq.flush_cidx = wq->sq.cidx; 231 wq->sq.flush_cidx = wq->sq.cidx;
241 idx = wq->sq.flush_cidx; 232 idx = wq->sq.flush_cidx;
242 BUG_ON(idx >= wq->sq.size);
243 while (idx != wq->sq.pidx) { 233 while (idx != wq->sq.pidx) {
244 swsqe = &wq->sq.sw_sq[idx]; 234 swsqe = &wq->sq.sw_sq[idx];
245 BUG_ON(swsqe->flushed);
246 swsqe->flushed = 1; 235 swsqe->flushed = 1;
247 insert_sq_cqe(wq, cq, swsqe); 236 insert_sq_cqe(wq, cq, swsqe);
248 if (wq->sq.oldest_read == swsqe) { 237 if (wq->sq.oldest_read == swsqe) {
249 BUG_ON(swsqe->opcode != FW_RI_READ_REQ);
250 advance_oldest_read(wq); 238 advance_oldest_read(wq);
251 } 239 }
252 flushed++; 240 flushed++;
@@ -267,7 +255,6 @@ static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq)
267 if (wq->sq.flush_cidx == -1) 255 if (wq->sq.flush_cidx == -1)
268 wq->sq.flush_cidx = wq->sq.cidx; 256 wq->sq.flush_cidx = wq->sq.cidx;
269 cidx = wq->sq.flush_cidx; 257 cidx = wq->sq.flush_cidx;
270 BUG_ON(cidx > wq->sq.size);
271 258
272 while (cidx != wq->sq.pidx) { 259 while (cidx != wq->sq.pidx) {
273 swsqe = &wq->sq.sw_sq[cidx]; 260 swsqe = &wq->sq.sw_sq[cidx];
@@ -276,13 +263,11 @@ static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq)
276 cidx = 0; 263 cidx = 0;
277 } else if (swsqe->complete) { 264 } else if (swsqe->complete) {
278 265
279 BUG_ON(swsqe->flushed);
280
281 /* 266 /*
282 * Insert this completed cqe into the swcq. 267 * Insert this completed cqe into the swcq.
283 */ 268 */
284 pr_debug("%s moving cqe into swcq sq idx %u cq idx %u\n", 269 pr_debug("moving cqe into swcq sq idx %u cq idx %u\n",
285 __func__, cidx, cq->sw_pidx); 270 cidx, cq->sw_pidx);
286 swsqe->cqe.header |= htonl(CQE_SWCQE_V(1)); 271 swsqe->cqe.header |= htonl(CQE_SWCQE_V(1));
287 cq->sw_queue[cq->sw_pidx] = swsqe->cqe; 272 cq->sw_queue[cq->sw_pidx] = swsqe->cqe;
288 t4_swcq_produce(cq); 273 t4_swcq_produce(cq);
@@ -337,7 +322,7 @@ void c4iw_flush_hw_cq(struct c4iw_cq *chp)
337 struct t4_swsqe *swsqe; 322 struct t4_swsqe *swsqe;
338 int ret; 323 int ret;
339 324
340 pr_debug("%s cqid 0x%x\n", __func__, chp->cq.cqid); 325 pr_debug("cqid 0x%x\n", chp->cq.cqid);
341 ret = t4_next_hw_cqe(&chp->cq, &hw_cqe); 326 ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
342 327
343 /* 328 /*
@@ -430,7 +415,7 @@ void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count)
430 u32 ptr; 415 u32 ptr;
431 416
432 *count = 0; 417 *count = 0;
433 pr_debug("%s count zero %d\n", __func__, *count); 418 pr_debug("count zero %d\n", *count);
434 ptr = cq->sw_cidx; 419 ptr = cq->sw_cidx;
435 while (ptr != cq->sw_pidx) { 420 while (ptr != cq->sw_pidx) {
436 cqe = &cq->sw_queue[ptr]; 421 cqe = &cq->sw_queue[ptr];
@@ -440,7 +425,7 @@ void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count)
440 if (++ptr == cq->size) 425 if (++ptr == cq->size)
441 ptr = 0; 426 ptr = 0;
442 } 427 }
443 pr_debug("%s cq %p count %d\n", __func__, cq, *count); 428 pr_debug("cq %p count %d\n", cq, *count);
444} 429}
445 430
446/* 431/*
@@ -471,8 +456,8 @@ static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
471 if (ret) 456 if (ret)
472 return ret; 457 return ret;
473 458
474 pr_debug("%s CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n", 459 pr_debug("CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
475 __func__, CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe), 460 CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe),
476 CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe), 461 CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe),
477 CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe), 462 CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe),
478 CQE_WRID_LOW(hw_cqe)); 463 CQE_WRID_LOW(hw_cqe));
@@ -603,8 +588,8 @@ static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
603 if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) { 588 if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) {
604 struct t4_swsqe *swsqe; 589 struct t4_swsqe *swsqe;
605 590
606 pr_debug("%s out of order completion going in sw_sq at idx %u\n", 591 pr_debug("out of order completion going in sw_sq at idx %u\n",
607 __func__, CQE_WRID_SQ_IDX(hw_cqe)); 592 CQE_WRID_SQ_IDX(hw_cqe));
608 swsqe = &wq->sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)]; 593 swsqe = &wq->sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
609 swsqe->cqe = *hw_cqe; 594 swsqe->cqe = *hw_cqe;
610 swsqe->complete = 1; 595 swsqe->complete = 1;
@@ -621,7 +606,6 @@ proc_cqe:
621 */ 606 */
622 if (SQ_TYPE(hw_cqe)) { 607 if (SQ_TYPE(hw_cqe)) {
623 int idx = CQE_WRID_SQ_IDX(hw_cqe); 608 int idx = CQE_WRID_SQ_IDX(hw_cqe);
624 BUG_ON(idx >= wq->sq.size);
625 609
626 /* 610 /*
627 * Account for any unsignaled completions completed by 611 * Account for any unsignaled completions completed by
@@ -635,18 +619,16 @@ proc_cqe:
635 wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx; 619 wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx;
636 else 620 else
637 wq->sq.in_use -= idx - wq->sq.cidx; 621 wq->sq.in_use -= idx - wq->sq.cidx;
638 BUG_ON(wq->sq.in_use <= 0 && wq->sq.in_use >= wq->sq.size);
639 622
640 wq->sq.cidx = (uint16_t)idx; 623 wq->sq.cidx = (uint16_t)idx;
641 pr_debug("%s completing sq idx %u\n", __func__, wq->sq.cidx); 624 pr_debug("completing sq idx %u\n", wq->sq.cidx);
642 *cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id; 625 *cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id;
643 if (c4iw_wr_log) 626 if (c4iw_wr_log)
644 c4iw_log_wr_stats(wq, hw_cqe); 627 c4iw_log_wr_stats(wq, hw_cqe);
645 t4_sq_consume(wq); 628 t4_sq_consume(wq);
646 } else { 629 } else {
647 pr_debug("%s completing rq idx %u\n", __func__, wq->rq.cidx); 630 pr_debug("completing rq idx %u\n", wq->rq.cidx);
648 *cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id; 631 *cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id;
649 BUG_ON(t4_rq_empty(wq));
650 if (c4iw_wr_log) 632 if (c4iw_wr_log)
651 c4iw_log_wr_stats(wq, hw_cqe); 633 c4iw_log_wr_stats(wq, hw_cqe);
652 t4_rq_consume(wq); 634 t4_rq_consume(wq);
@@ -661,12 +643,12 @@ flush_wq:
661 643
662skip_cqe: 644skip_cqe:
663 if (SW_CQE(hw_cqe)) { 645 if (SW_CQE(hw_cqe)) {
664 pr_debug("%s cq %p cqid 0x%x skip sw cqe cidx %u\n", 646 pr_debug("cq %p cqid 0x%x skip sw cqe cidx %u\n",
665 __func__, cq, cq->cqid, cq->sw_cidx); 647 cq, cq->cqid, cq->sw_cidx);
666 t4_swcq_consume(cq); 648 t4_swcq_consume(cq);
667 } else { 649 } else {
668 pr_debug("%s cq %p cqid 0x%x skip hw cqe cidx %u\n", 650 pr_debug("cq %p cqid 0x%x skip hw cqe cidx %u\n",
669 __func__, cq, cq->cqid, cq->cidx); 651 cq, cq->cqid, cq->cidx);
670 t4_hwcq_consume(cq); 652 t4_hwcq_consume(cq);
671 } 653 }
672 return ret; 654 return ret;
@@ -712,8 +694,8 @@ static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc)
712 wc->vendor_err = CQE_STATUS(&cqe); 694 wc->vendor_err = CQE_STATUS(&cqe);
713 wc->wc_flags = 0; 695 wc->wc_flags = 0;
714 696
715 pr_debug("%s qpid 0x%x type %d opcode %d status 0x%x len %u wrid hi 0x%x lo 0x%x cookie 0x%llx\n", 697 pr_debug("qpid 0x%x type %d opcode %d status 0x%x len %u wrid hi 0x%x lo 0x%x cookie 0x%llx\n",
716 __func__, CQE_QPID(&cqe), 698 CQE_QPID(&cqe),
717 CQE_TYPE(&cqe), CQE_OPCODE(&cqe), 699 CQE_TYPE(&cqe), CQE_OPCODE(&cqe),
718 CQE_STATUS(&cqe), CQE_LEN(&cqe), 700 CQE_STATUS(&cqe), CQE_LEN(&cqe),
719 CQE_WRID_HI(&cqe), CQE_WRID_LOW(&cqe), 701 CQE_WRID_HI(&cqe), CQE_WRID_LOW(&cqe),
@@ -857,7 +839,7 @@ int c4iw_destroy_cq(struct ib_cq *ib_cq)
857 struct c4iw_cq *chp; 839 struct c4iw_cq *chp;
858 struct c4iw_ucontext *ucontext; 840 struct c4iw_ucontext *ucontext;
859 841
860 pr_debug("%s ib_cq %p\n", __func__, ib_cq); 842 pr_debug("ib_cq %p\n", ib_cq);
861 chp = to_c4iw_cq(ib_cq); 843 chp = to_c4iw_cq(ib_cq);
862 844
863 remove_handle(chp->rhp, &chp->rhp->cqidr, chp->cq.cqid); 845 remove_handle(chp->rhp, &chp->rhp->cqidr, chp->cq.cqid);
@@ -868,8 +850,8 @@ int c4iw_destroy_cq(struct ib_cq *ib_cq)
868 : NULL; 850 : NULL;
869 destroy_cq(&chp->rhp->rdev, &chp->cq, 851 destroy_cq(&chp->rhp->rdev, &chp->cq,
870 ucontext ? &ucontext->uctx : &chp->cq.rdev->uctx, 852 ucontext ? &ucontext->uctx : &chp->cq.rdev->uctx,
871 chp->destroy_skb); 853 chp->destroy_skb, chp->wr_waitp);
872 chp->destroy_skb = NULL; 854 c4iw_put_wr_wait(chp->wr_waitp);
873 kfree(chp); 855 kfree(chp);
874 return 0; 856 return 0;
875} 857}
@@ -889,7 +871,7 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
889 size_t memsize, hwentries; 871 size_t memsize, hwentries;
890 struct c4iw_mm_entry *mm, *mm2; 872 struct c4iw_mm_entry *mm, *mm2;
891 873
892 pr_debug("%s ib_dev %p entries %d\n", __func__, ibdev, entries); 874 pr_debug("ib_dev %p entries %d\n", ibdev, entries);
893 if (attr->flags) 875 if (attr->flags)
894 return ERR_PTR(-EINVAL); 876 return ERR_PTR(-EINVAL);
895 877
@@ -901,12 +883,18 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
901 chp = kzalloc(sizeof(*chp), GFP_KERNEL); 883 chp = kzalloc(sizeof(*chp), GFP_KERNEL);
902 if (!chp) 884 if (!chp)
903 return ERR_PTR(-ENOMEM); 885 return ERR_PTR(-ENOMEM);
886 chp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
887 if (!chp->wr_waitp) {
888 ret = -ENOMEM;
889 goto err_free_chp;
890 }
891 c4iw_init_wr_wait(chp->wr_waitp);
904 892
905 wr_len = sizeof(struct fw_ri_res_wr) + sizeof(struct fw_ri_res); 893 wr_len = sizeof(struct fw_ri_res_wr) + sizeof(struct fw_ri_res);
906 chp->destroy_skb = alloc_skb(wr_len, GFP_KERNEL); 894 chp->destroy_skb = alloc_skb(wr_len, GFP_KERNEL);
907 if (!chp->destroy_skb) { 895 if (!chp->destroy_skb) {
908 ret = -ENOMEM; 896 ret = -ENOMEM;
909 goto err1; 897 goto err_free_wr_wait;
910 } 898 }
911 899
912 if (ib_context) 900 if (ib_context)
@@ -947,9 +935,10 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
947 chp->cq.vector = vector; 935 chp->cq.vector = vector;
948 936
949 ret = create_cq(&rhp->rdev, &chp->cq, 937 ret = create_cq(&rhp->rdev, &chp->cq,
950 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 938 ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
939 chp->wr_waitp);
951 if (ret) 940 if (ret)
952 goto err2; 941 goto err_free_skb;
953 942
954 chp->rhp = rhp; 943 chp->rhp = rhp;
955 chp->cq.size--; /* status page */ 944 chp->cq.size--; /* status page */
@@ -960,16 +949,16 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
960 init_waitqueue_head(&chp->wait); 949 init_waitqueue_head(&chp->wait);
961 ret = insert_handle(rhp, &rhp->cqidr, chp, chp->cq.cqid); 950 ret = insert_handle(rhp, &rhp->cqidr, chp, chp->cq.cqid);
962 if (ret) 951 if (ret)
963 goto err3; 952 goto err_destroy_cq;
964 953
965 if (ucontext) { 954 if (ucontext) {
966 ret = -ENOMEM; 955 ret = -ENOMEM;
967 mm = kmalloc(sizeof *mm, GFP_KERNEL); 956 mm = kmalloc(sizeof *mm, GFP_KERNEL);
968 if (!mm) 957 if (!mm)
969 goto err4; 958 goto err_remove_handle;
970 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); 959 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
971 if (!mm2) 960 if (!mm2)
972 goto err5; 961 goto err_free_mm;
973 962
974 uresp.qid_mask = rhp->rdev.cqmask; 963 uresp.qid_mask = rhp->rdev.cqmask;
975 uresp.cqid = chp->cq.cqid; 964 uresp.cqid = chp->cq.cqid;
@@ -984,7 +973,7 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
984 ret = ib_copy_to_udata(udata, &uresp, 973 ret = ib_copy_to_udata(udata, &uresp,
985 sizeof(uresp) - sizeof(uresp.reserved)); 974 sizeof(uresp) - sizeof(uresp.reserved));
986 if (ret) 975 if (ret)
987 goto err6; 976 goto err_free_mm2;
988 977
989 mm->key = uresp.key; 978 mm->key = uresp.key;
990 mm->addr = virt_to_phys(chp->cq.queue); 979 mm->addr = virt_to_phys(chp->cq.queue);
@@ -996,23 +985,25 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
996 mm2->len = PAGE_SIZE; 985 mm2->len = PAGE_SIZE;
997 insert_mmap(ucontext, mm2); 986 insert_mmap(ucontext, mm2);
998 } 987 }
999 pr_debug("%s cqid 0x%0x chp %p size %u memsize %zu, dma_addr 0x%0llx\n", 988 pr_debug("cqid 0x%0x chp %p size %u memsize %zu, dma_addr 0x%0llx\n",
1000 __func__, chp->cq.cqid, chp, chp->cq.size, 989 chp->cq.cqid, chp, chp->cq.size,
1001 chp->cq.memsize, (unsigned long long)chp->cq.dma_addr); 990 chp->cq.memsize, (unsigned long long)chp->cq.dma_addr);
1002 return &chp->ibcq; 991 return &chp->ibcq;
1003err6: 992err_free_mm2:
1004 kfree(mm2); 993 kfree(mm2);
1005err5: 994err_free_mm:
1006 kfree(mm); 995 kfree(mm);
1007err4: 996err_remove_handle:
1008 remove_handle(rhp, &rhp->cqidr, chp->cq.cqid); 997 remove_handle(rhp, &rhp->cqidr, chp->cq.cqid);
1009err3: 998err_destroy_cq:
1010 destroy_cq(&chp->rhp->rdev, &chp->cq, 999 destroy_cq(&chp->rhp->rdev, &chp->cq,
1011 ucontext ? &ucontext->uctx : &rhp->rdev.uctx, 1000 ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
1012 chp->destroy_skb); 1001 chp->destroy_skb, chp->wr_waitp);
1013err2: 1002err_free_skb:
1014 kfree_skb(chp->destroy_skb); 1003 kfree_skb(chp->destroy_skb);
1015err1: 1004err_free_wr_wait:
1005 c4iw_put_wr_wait(chp->wr_waitp);
1006err_free_chp:
1016 kfree(chp); 1007 kfree(chp);
1017 return ERR_PTR(ret); 1008 return ERR_PTR(ret);
1018} 1009}
diff --git a/drivers/infiniband/hw/cxgb4/device.c b/drivers/infiniband/hw/cxgb4/device.c
index fc886f81b885..af77d128d242 100644
--- a/drivers/infiniband/hw/cxgb4/device.c
+++ b/drivers/infiniband/hw/cxgb4/device.c
@@ -64,14 +64,9 @@ module_param(c4iw_wr_log_size_order, int, 0444);
64MODULE_PARM_DESC(c4iw_wr_log_size_order, 64MODULE_PARM_DESC(c4iw_wr_log_size_order,
65 "Number of entries (log2) in the work request timing log."); 65 "Number of entries (log2) in the work request timing log.");
66 66
67struct uld_ctx {
68 struct list_head entry;
69 struct cxgb4_lld_info lldi;
70 struct c4iw_dev *dev;
71};
72
73static LIST_HEAD(uld_ctx_list); 67static LIST_HEAD(uld_ctx_list);
74static DEFINE_MUTEX(dev_mutex); 68static DEFINE_MUTEX(dev_mutex);
69struct workqueue_struct *reg_workq;
75 70
76#define DB_FC_RESUME_SIZE 64 71#define DB_FC_RESUME_SIZE 64
77#define DB_FC_RESUME_DELAY 1 72#define DB_FC_RESUME_DELAY 1
@@ -811,8 +806,8 @@ static int c4iw_rdev_open(struct c4iw_rdev *rdev)
811 806
812 rdev->qpmask = rdev->lldi.udb_density - 1; 807 rdev->qpmask = rdev->lldi.udb_density - 1;
813 rdev->cqmask = rdev->lldi.ucq_density - 1; 808 rdev->cqmask = rdev->lldi.ucq_density - 1;
814 pr_debug("%s dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u\n", 809 pr_debug("dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u\n",
815 __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start, 810 pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
816 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev), 811 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
817 rdev->lldi.vr->pbl.start, 812 rdev->lldi.vr->pbl.start,
818 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start, 813 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
@@ -912,7 +907,7 @@ static void c4iw_rdev_close(struct c4iw_rdev *rdev)
912 c4iw_destroy_resource(&rdev->resource); 907 c4iw_destroy_resource(&rdev->resource);
913} 908}
914 909
915static void c4iw_dealloc(struct uld_ctx *ctx) 910void c4iw_dealloc(struct uld_ctx *ctx)
916{ 911{
917 c4iw_rdev_close(&ctx->dev->rdev); 912 c4iw_rdev_close(&ctx->dev->rdev);
918 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr)); 913 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr));
@@ -935,7 +930,7 @@ static void c4iw_dealloc(struct uld_ctx *ctx)
935 930
936static void c4iw_remove(struct uld_ctx *ctx) 931static void c4iw_remove(struct uld_ctx *ctx)
937{ 932{
938 pr_debug("%s c4iw_dev %p\n", __func__, ctx->dev); 933 pr_debug("c4iw_dev %p\n", ctx->dev);
939 c4iw_unregister_device(ctx->dev); 934 c4iw_unregister_device(ctx->dev);
940 c4iw_dealloc(ctx); 935 c4iw_dealloc(ctx);
941} 936}
@@ -969,8 +964,8 @@ static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
969 devp->rdev.lldi = *infop; 964 devp->rdev.lldi = *infop;
970 965
971 /* init various hw-queue params based on lld info */ 966 /* init various hw-queue params based on lld info */
972 pr_debug("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n", 967 pr_debug("Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
973 __func__, devp->rdev.lldi.sge_ingpadboundary, 968 devp->rdev.lldi.sge_ingpadboundary,
974 devp->rdev.lldi.sge_egrstatuspagesize); 969 devp->rdev.lldi.sge_egrstatuspagesize);
975 970
976 devp->rdev.hw_queue.t4_eq_status_entries = 971 devp->rdev.hw_queue.t4_eq_status_entries =
@@ -1069,8 +1064,8 @@ static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
1069 } 1064 }
1070 ctx->lldi = *infop; 1065 ctx->lldi = *infop;
1071 1066
1072 pr_debug("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n", 1067 pr_debug("found device %s nchan %u nrxq %u ntxq %u nports %u\n",
1073 __func__, pci_name(ctx->lldi.pdev), 1068 pci_name(ctx->lldi.pdev),
1074 ctx->lldi.nchan, ctx->lldi.nrxq, 1069 ctx->lldi.nchan, ctx->lldi.nrxq,
1075 ctx->lldi.ntxq, ctx->lldi.nports); 1070 ctx->lldi.ntxq, ctx->lldi.nports);
1076 1071
@@ -1102,8 +1097,8 @@ static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
1102 if (unlikely(!skb)) 1097 if (unlikely(!skb))
1103 return NULL; 1098 return NULL;
1104 1099
1105 __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) + 1100 __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
1106 sizeof(struct rss_header) - pktshift); 1101 sizeof(struct rss_header) - pktshift);
1107 1102
1108 /* 1103 /*
1109 * This skb will contain: 1104 * This skb will contain:
@@ -1203,13 +1198,11 @@ static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
1203{ 1198{
1204 struct uld_ctx *ctx = handle; 1199 struct uld_ctx *ctx = handle;
1205 1200
1206 pr_debug("%s new_state %u\n", __func__, new_state); 1201 pr_debug("new_state %u\n", new_state);
1207 switch (new_state) { 1202 switch (new_state) {
1208 case CXGB4_STATE_UP: 1203 case CXGB4_STATE_UP:
1209 pr_info("%s: Up\n", pci_name(ctx->lldi.pdev)); 1204 pr_info("%s: Up\n", pci_name(ctx->lldi.pdev));
1210 if (!ctx->dev) { 1205 if (!ctx->dev) {
1211 int ret;
1212
1213 ctx->dev = c4iw_alloc(&ctx->lldi); 1206 ctx->dev = c4iw_alloc(&ctx->lldi);
1214 if (IS_ERR(ctx->dev)) { 1207 if (IS_ERR(ctx->dev)) {
1215 pr_err("%s: initialization failed: %ld\n", 1208 pr_err("%s: initialization failed: %ld\n",
@@ -1218,12 +1211,9 @@ static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
1218 ctx->dev = NULL; 1211 ctx->dev = NULL;
1219 break; 1212 break;
1220 } 1213 }
1221 ret = c4iw_register_device(ctx->dev); 1214
1222 if (ret) { 1215 INIT_WORK(&ctx->reg_work, c4iw_register_device);
1223 pr_err("%s: RDMA registration failed: %d\n", 1216 queue_work(reg_workq, &ctx->reg_work);
1224 pci_name(ctx->lldi.pdev), ret);
1225 c4iw_dealloc(ctx);
1226 }
1227 } 1217 }
1228 break; 1218 break;
1229 case CXGB4_STATE_DOWN: 1219 case CXGB4_STATE_DOWN:
@@ -1518,6 +1508,27 @@ static struct cxgb4_uld_info c4iw_uld_info = {
1518 .control = c4iw_uld_control, 1508 .control = c4iw_uld_control,
1519}; 1509};
1520 1510
1511void _c4iw_free_wr_wait(struct kref *kref)
1512{
1513 struct c4iw_wr_wait *wr_waitp;
1514
1515 wr_waitp = container_of(kref, struct c4iw_wr_wait, kref);
1516 pr_debug("Free wr_wait %p\n", wr_waitp);
1517 kfree(wr_waitp);
1518}
1519
1520struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp)
1521{
1522 struct c4iw_wr_wait *wr_waitp;
1523
1524 wr_waitp = kzalloc(sizeof(*wr_waitp), gfp);
1525 if (wr_waitp) {
1526 kref_init(&wr_waitp->kref);
1527 pr_debug("wr_wait %p\n", wr_waitp);
1528 }
1529 return wr_waitp;
1530}
1531
1521static int __init c4iw_init_module(void) 1532static int __init c4iw_init_module(void)
1522{ 1533{
1523 int err; 1534 int err;
@@ -1530,6 +1541,12 @@ static int __init c4iw_init_module(void)
1530 if (!c4iw_debugfs_root) 1541 if (!c4iw_debugfs_root)
1531 pr_warn("could not create debugfs entry, continuing\n"); 1542 pr_warn("could not create debugfs entry, continuing\n");
1532 1543
1544 reg_workq = create_singlethread_workqueue("Register_iWARP_device");
1545 if (!reg_workq) {
1546 pr_err("Failed creating workqueue to register iwarp device\n");
1547 return -ENOMEM;
1548 }
1549
1533 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info); 1550 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
1534 1551
1535 return 0; 1552 return 0;
@@ -1546,6 +1563,8 @@ static void __exit c4iw_exit_module(void)
1546 kfree(ctx); 1563 kfree(ctx);
1547 } 1564 }
1548 mutex_unlock(&dev_mutex); 1565 mutex_unlock(&dev_mutex);
1566 flush_workqueue(reg_workq);
1567 destroy_workqueue(reg_workq);
1549 cxgb4_unregister_uld(CXGB4_ULD_RDMA); 1568 cxgb4_unregister_uld(CXGB4_ULD_RDMA);
1550 c4iw_cm_term(); 1569 c4iw_cm_term();
1551 debugfs_remove_recursive(c4iw_debugfs_root); 1570 debugfs_remove_recursive(c4iw_debugfs_root);
diff --git a/drivers/infiniband/hw/cxgb4/ev.c b/drivers/infiniband/hw/cxgb4/ev.c
index 8f963df0bffc..a252d5c40ae3 100644
--- a/drivers/infiniband/hw/cxgb4/ev.c
+++ b/drivers/infiniband/hw/cxgb4/ev.c
@@ -109,9 +109,11 @@ static void post_qp_event(struct c4iw_dev *dev, struct c4iw_cq *chp,
109 if (qhp->ibqp.event_handler) 109 if (qhp->ibqp.event_handler)
110 (*qhp->ibqp.event_handler)(&event, qhp->ibqp.qp_context); 110 (*qhp->ibqp.event_handler)(&event, qhp->ibqp.qp_context);
111 111
112 spin_lock_irqsave(&chp->comp_handler_lock, flag); 112 if (t4_clear_cq_armed(&chp->cq)) {
113 (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context); 113 spin_lock_irqsave(&chp->comp_handler_lock, flag);
114 spin_unlock_irqrestore(&chp->comp_handler_lock, flag); 114 (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);
115 spin_unlock_irqrestore(&chp->comp_handler_lock, flag);
116 }
115} 117}
116 118
117void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe) 119void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe)
@@ -234,7 +236,7 @@ int c4iw_ev_handler(struct c4iw_dev *dev, u32 qid)
234 if (atomic_dec_and_test(&chp->refcnt)) 236 if (atomic_dec_and_test(&chp->refcnt))
235 wake_up(&chp->wait); 237 wake_up(&chp->wait);
236 } else { 238 } else {
237 pr_debug("%s unknown cqid 0x%x\n", __func__, qid); 239 pr_warn("%s unknown cqid 0x%x\n", __func__, qid);
238 spin_unlock_irqrestore(&dev->lock, flag); 240 spin_unlock_irqrestore(&dev->lock, flag);
239 } 241 }
240 return 0; 242 return 0;
diff --git a/drivers/infiniband/hw/cxgb4/id_table.c b/drivers/infiniband/hw/cxgb4/id_table.c
index 0161ae6ad629..5c2cfdea06ad 100644
--- a/drivers/infiniband/hw/cxgb4/id_table.c
+++ b/drivers/infiniband/hw/cxgb4/id_table.c
@@ -73,7 +73,6 @@ void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj)
73 unsigned long flags; 73 unsigned long flags;
74 74
75 obj -= alloc->start; 75 obj -= alloc->start;
76 BUG_ON((int)obj < 0);
77 76
78 spin_lock_irqsave(&alloc->lock, flags); 77 spin_lock_irqsave(&alloc->lock, flags);
79 clear_bit(obj, alloc->table); 78 clear_bit(obj, alloc->table);
diff --git a/drivers/infiniband/hw/cxgb4/iw_cxgb4.h b/drivers/infiniband/hw/cxgb4/iw_cxgb4.h
index 819a30635d53..470f97a79ebb 100644
--- a/drivers/infiniband/hw/cxgb4/iw_cxgb4.h
+++ b/drivers/infiniband/hw/cxgb4/iw_cxgb4.h
@@ -202,18 +202,50 @@ static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
202struct c4iw_wr_wait { 202struct c4iw_wr_wait {
203 struct completion completion; 203 struct completion completion;
204 int ret; 204 int ret;
205 struct kref kref;
205}; 206};
206 207
208void _c4iw_free_wr_wait(struct kref *kref);
209
210static inline void c4iw_put_wr_wait(struct c4iw_wr_wait *wr_waitp)
211{
212 pr_debug("wr_wait %p ref before put %u\n", wr_waitp,
213 kref_read(&wr_waitp->kref));
214 WARN_ON(kref_read(&wr_waitp->kref) == 0);
215 kref_put(&wr_waitp->kref, _c4iw_free_wr_wait);
216}
217
218static inline void c4iw_get_wr_wait(struct c4iw_wr_wait *wr_waitp)
219{
220 pr_debug("wr_wait %p ref before get %u\n", wr_waitp,
221 kref_read(&wr_waitp->kref));
222 WARN_ON(kref_read(&wr_waitp->kref) == 0);
223 kref_get(&wr_waitp->kref);
224}
225
207static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 226static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
208{ 227{
209 wr_waitp->ret = 0; 228 wr_waitp->ret = 0;
210 init_completion(&wr_waitp->completion); 229 init_completion(&wr_waitp->completion);
211} 230}
212 231
213static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret) 232static inline void _c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret,
233 bool deref)
214{ 234{
215 wr_waitp->ret = ret; 235 wr_waitp->ret = ret;
216 complete(&wr_waitp->completion); 236 complete(&wr_waitp->completion);
237 if (deref)
238 c4iw_put_wr_wait(wr_waitp);
239}
240
241static inline void c4iw_wake_up_noref(struct c4iw_wr_wait *wr_waitp, int ret)
242{
243 _c4iw_wake_up(wr_waitp, ret, false);
244}
245
246static inline void c4iw_wake_up_deref(struct c4iw_wr_wait *wr_waitp, int ret)
247{
248 _c4iw_wake_up(wr_waitp, ret, true);
217} 249}
218 250
219static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev, 251static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
@@ -230,18 +262,40 @@ static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
230 262
231 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO); 263 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
232 if (!ret) { 264 if (!ret) {
233 pr_debug("%s - Device %s not responding (disabling device) - tid %u qpid %u\n", 265 pr_err("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
234 func, pci_name(rdev->lldi.pdev), hwtid, qpid); 266 func, pci_name(rdev->lldi.pdev), hwtid, qpid);
235 rdev->flags |= T4_FATAL_ERROR; 267 rdev->flags |= T4_FATAL_ERROR;
236 wr_waitp->ret = -EIO; 268 wr_waitp->ret = -EIO;
269 goto out;
237 } 270 }
238out:
239 if (wr_waitp->ret) 271 if (wr_waitp->ret)
240 pr_debug("%s: FW reply %d tid %u qpid %u\n", 272 pr_debug("%s: FW reply %d tid %u qpid %u\n",
241 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid); 273 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
274out:
242 return wr_waitp->ret; 275 return wr_waitp->ret;
243} 276}
244 277
278int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
279
280static inline int c4iw_ref_send_wait(struct c4iw_rdev *rdev,
281 struct sk_buff *skb,
282 struct c4iw_wr_wait *wr_waitp,
283 u32 hwtid, u32 qpid,
284 const char *func)
285{
286 int ret;
287
288 pr_debug("%s wr_wait %p hwtid %u qpid %u\n", func, wr_waitp, hwtid,
289 qpid);
290 c4iw_get_wr_wait(wr_waitp);
291 ret = c4iw_ofld_send(rdev, skb);
292 if (ret) {
293 c4iw_put_wr_wait(wr_waitp);
294 return ret;
295 }
296 return c4iw_wait_for_reply(rdev, wr_waitp, hwtid, qpid, func);
297}
298
245enum db_state { 299enum db_state {
246 NORMAL = 0, 300 NORMAL = 0,
247 FLOW_CONTROL = 1, 301 FLOW_CONTROL = 1,
@@ -268,6 +322,13 @@ struct c4iw_dev {
268 wait_queue_head_t wait; 322 wait_queue_head_t wait;
269}; 323};
270 324
325struct uld_ctx {
326 struct list_head entry;
327 struct cxgb4_lld_info lldi;
328 struct c4iw_dev *dev;
329 struct work_struct reg_work;
330};
331
271static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 332static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
272{ 333{
273 return container_of(ibdev, struct c4iw_dev, ibdev); 334 return container_of(ibdev, struct c4iw_dev, ibdev);
@@ -310,7 +371,6 @@ static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
310 idr_preload_end(); 371 idr_preload_end();
311 } 372 }
312 373
313 BUG_ON(ret == -ENOSPC);
314 return ret < 0 ? ret : 0; 374 return ret < 0 ? ret : 0;
315} 375}
316 376
@@ -394,6 +454,7 @@ struct c4iw_mr {
394 dma_addr_t mpl_addr; 454 dma_addr_t mpl_addr;
395 u32 max_mpl_len; 455 u32 max_mpl_len;
396 u32 mpl_len; 456 u32 mpl_len;
457 struct c4iw_wr_wait *wr_waitp;
397}; 458};
398 459
399static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 460static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
@@ -407,6 +468,7 @@ struct c4iw_mw {
407 struct sk_buff *dereg_skb; 468 struct sk_buff *dereg_skb;
408 u64 kva; 469 u64 kva;
409 struct tpt_attributes attr; 470 struct tpt_attributes attr;
471 struct c4iw_wr_wait *wr_waitp;
410}; 472};
411 473
412static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 474static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
@@ -423,6 +485,7 @@ struct c4iw_cq {
423 spinlock_t comp_handler_lock; 485 spinlock_t comp_handler_lock;
424 atomic_t refcnt; 486 atomic_t refcnt;
425 wait_queue_head_t wait; 487 wait_queue_head_t wait;
488 struct c4iw_wr_wait *wr_waitp;
426}; 489};
427 490
428static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 491static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
@@ -480,10 +543,10 @@ struct c4iw_qp {
480 struct mutex mutex; 543 struct mutex mutex;
481 struct kref kref; 544 struct kref kref;
482 wait_queue_head_t wait; 545 wait_queue_head_t wait;
483 struct timer_list timer;
484 int sq_sig_all; 546 int sq_sig_all;
485 struct work_struct free_work; 547 struct work_struct free_work;
486 struct c4iw_ucontext *ucontext; 548 struct c4iw_ucontext *ucontext;
549 struct c4iw_wr_wait *wr_waitp;
487}; 550};
488 551
489static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 552static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
@@ -537,8 +600,7 @@ static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
537 if (mm->key == key && mm->len == len) { 600 if (mm->key == key && mm->len == len) {
538 list_del_init(&mm->entry); 601 list_del_init(&mm->entry);
539 spin_unlock(&ucontext->mmap_lock); 602 spin_unlock(&ucontext->mmap_lock);
540 pr_debug("%s key 0x%x addr 0x%llx len %d\n", 603 pr_debug("key 0x%x addr 0x%llx len %d\n", key,
541 __func__, key,
542 (unsigned long long)mm->addr, mm->len); 604 (unsigned long long)mm->addr, mm->len);
543 return mm; 605 return mm;
544 } 606 }
@@ -551,8 +613,8 @@ static inline void insert_mmap(struct c4iw_ucontext *ucontext,
551 struct c4iw_mm_entry *mm) 613 struct c4iw_mm_entry *mm)
552{ 614{
553 spin_lock(&ucontext->mmap_lock); 615 spin_lock(&ucontext->mmap_lock);
554 pr_debug("%s key 0x%x addr 0x%llx len %d\n", 616 pr_debug("key 0x%x addr 0x%llx len %d\n",
555 __func__, mm->key, (unsigned long long)mm->addr, mm->len); 617 mm->key, (unsigned long long)mm->addr, mm->len);
556 list_add_tail(&mm->entry, &ucontext->mmaps); 618 list_add_tail(&mm->entry, &ucontext->mmaps);
557 spin_unlock(&ucontext->mmap_lock); 619 spin_unlock(&ucontext->mmap_lock);
558} 620}
@@ -671,16 +733,14 @@ enum c4iw_mmid_state {
671#define MPA_V2_IRD_ORD_MASK 0x3FFF 733#define MPA_V2_IRD_ORD_MASK 0x3FFF
672 734
673#define c4iw_put_ep(ep) { \ 735#define c4iw_put_ep(ep) { \
674 pr_debug("put_ep (via %s:%u) ep %p refcnt %d\n", \ 736 pr_debug("put_ep ep %p refcnt %d\n", \
675 __func__, __LINE__, \
676 ep, kref_read(&((ep)->kref))); \ 737 ep, kref_read(&((ep)->kref))); \
677 WARN_ON(kref_read(&((ep)->kref)) < 1); \ 738 WARN_ON(kref_read(&((ep)->kref)) < 1); \
678 kref_put(&((ep)->kref), _c4iw_free_ep); \ 739 kref_put(&((ep)->kref), _c4iw_free_ep); \
679} 740}
680 741
681#define c4iw_get_ep(ep) { \ 742#define c4iw_get_ep(ep) { \
682 pr_debug("get_ep (via %s:%u) ep %p, refcnt %d\n", \ 743 pr_debug("get_ep ep %p, refcnt %d\n", \
683 __func__, __LINE__, \
684 ep, kref_read(&((ep)->kref))); \ 744 ep, kref_read(&((ep)->kref))); \
685 kref_get(&((ep)->kref)); \ 745 kref_get(&((ep)->kref)); \
686} 746}
@@ -841,7 +901,7 @@ struct c4iw_ep_common {
841 struct mutex mutex; 901 struct mutex mutex;
842 struct sockaddr_storage local_addr; 902 struct sockaddr_storage local_addr;
843 struct sockaddr_storage remote_addr; 903 struct sockaddr_storage remote_addr;
844 struct c4iw_wr_wait wr_wait; 904 struct c4iw_wr_wait *wr_waitp;
845 unsigned long flags; 905 unsigned long flags;
846 unsigned long history; 906 unsigned long history;
847}; 907};
@@ -935,7 +995,7 @@ void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
935void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev); 995void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
936void c4iw_destroy_resource(struct c4iw_resource *rscp); 996void c4iw_destroy_resource(struct c4iw_resource *rscp);
937int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 997int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
938int c4iw_register_device(struct c4iw_dev *dev); 998void c4iw_register_device(struct work_struct *work);
939void c4iw_unregister_device(struct c4iw_dev *dev); 999void c4iw_unregister_device(struct c4iw_dev *dev);
940int __init c4iw_cm_init(void); 1000int __init c4iw_cm_init(void);
941void c4iw_cm_term(void); 1001void c4iw_cm_term(void);
@@ -961,6 +1021,7 @@ struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
961int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1021int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
962 unsigned int *sg_offset); 1022 unsigned int *sg_offset);
963int c4iw_dealloc_mw(struct ib_mw *mw); 1023int c4iw_dealloc_mw(struct ib_mw *mw);
1024void c4iw_dealloc(struct uld_ctx *ctx);
964struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1025struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
965 struct ib_udata *udata); 1026 struct ib_udata *udata);
966struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, 1027struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
@@ -990,7 +1051,6 @@ u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
990void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1051void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
991u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size); 1052u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
992void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1053void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
993int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
994void c4iw_flush_hw_cq(struct c4iw_cq *chp); 1054void c4iw_flush_hw_cq(struct c4iw_cq *chp);
995void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 1055void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
996int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 1056int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
@@ -1018,5 +1078,6 @@ extern int db_fc_threshold;
1018extern int db_coalescing_threshold; 1078extern int db_coalescing_threshold;
1019extern int use_dsgl; 1079extern int use_dsgl;
1020void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey); 1080void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
1081struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp);
1021 1082
1022#endif 1083#endif
diff --git a/drivers/infiniband/hw/cxgb4/mem.c b/drivers/infiniband/hw/cxgb4/mem.c
index c2fba76becd4..7e0eb201cc26 100644
--- a/drivers/infiniband/hw/cxgb4/mem.c
+++ b/drivers/infiniband/hw/cxgb4/mem.c
@@ -60,18 +60,18 @@ static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
60 60
61static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, 61static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
62 u32 len, dma_addr_t data, 62 u32 len, dma_addr_t data,
63 int wait, struct sk_buff *skb) 63 struct sk_buff *skb,
64 struct c4iw_wr_wait *wr_waitp)
64{ 65{
65 struct ulp_mem_io *req; 66 struct ulp_mem_io *req;
66 struct ulptx_sgl *sgl; 67 struct ulptx_sgl *sgl;
67 u8 wr_len; 68 u8 wr_len;
68 int ret = 0; 69 int ret = 0;
69 struct c4iw_wr_wait wr_wait;
70 70
71 addr &= 0x7FFFFFF; 71 addr &= 0x7FFFFFF;
72 72
73 if (wait) 73 if (wr_waitp)
74 c4iw_init_wr_wait(&wr_wait); 74 c4iw_init_wr_wait(wr_waitp);
75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16); 75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16);
76 76
77 if (!skb) { 77 if (!skb) {
@@ -84,8 +84,8 @@ static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
84 req = __skb_put_zero(skb, wr_len); 84 req = __skb_put_zero(skb, wr_len);
85 INIT_ULPTX_WR(req, wr_len, 0, 0); 85 INIT_ULPTX_WR(req, wr_len, 0, 0);
86 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 86 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
87 (wait ? FW_WR_COMPL_F : 0)); 87 (wr_waitp ? FW_WR_COMPL_F : 0));
88 req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L; 88 req->wr.wr_lo = wr_waitp ? (__force __be64)(unsigned long)wr_waitp : 0L;
89 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 89 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
90 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) | 90 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
91 T5_ULP_MEMIO_ORDER_V(1) | 91 T5_ULP_MEMIO_ORDER_V(1) |
@@ -100,22 +100,21 @@ static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
100 sgl->len0 = cpu_to_be32(len); 100 sgl->len0 = cpu_to_be32(len);
101 sgl->addr0 = cpu_to_be64(data); 101 sgl->addr0 = cpu_to_be64(data);
102 102
103 ret = c4iw_ofld_send(rdev, skb); 103 if (wr_waitp)
104 if (ret) 104 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
105 return ret; 105 else
106 if (wait) 106 ret = c4iw_ofld_send(rdev, skb);
107 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
108 return ret; 107 return ret;
109} 108}
110 109
111static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, 110static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
112 void *data, struct sk_buff *skb) 111 void *data, struct sk_buff *skb,
112 struct c4iw_wr_wait *wr_waitp)
113{ 113{
114 struct ulp_mem_io *req; 114 struct ulp_mem_io *req;
115 struct ulptx_idata *sc; 115 struct ulptx_idata *sc;
116 u8 wr_len, *to_dp, *from_dp; 116 u8 wr_len, *to_dp, *from_dp;
117 int copy_len, num_wqe, i, ret = 0; 117 int copy_len, num_wqe, i, ret = 0;
118 struct c4iw_wr_wait wr_wait;
119 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE)); 118 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
120 119
121 if (is_t4(rdev->lldi.adapter_type)) 120 if (is_t4(rdev->lldi.adapter_type))
@@ -124,9 +123,9 @@ static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
124 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F); 123 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F);
125 124
126 addr &= 0x7FFFFFF; 125 addr &= 0x7FFFFFF;
127 pr_debug("%s addr 0x%x len %u\n", __func__, addr, len); 126 pr_debug("addr 0x%x len %u\n", addr, len);
128 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE); 127 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
129 c4iw_init_wr_wait(&wr_wait); 128 c4iw_init_wr_wait(wr_waitp);
130 for (i = 0; i < num_wqe; i++) { 129 for (i = 0; i < num_wqe; i++) {
131 130
132 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE : 131 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
@@ -147,7 +146,7 @@ static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
147 if (i == (num_wqe-1)) { 146 if (i == (num_wqe-1)) {
148 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 147 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
149 FW_WR_COMPL_F); 148 FW_WR_COMPL_F);
150 req->wr.wr_lo = (__force __be64)(unsigned long)&wr_wait; 149 req->wr.wr_lo = (__force __be64)(unsigned long)wr_waitp;
151 } else 150 } else
152 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR)); 151 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
153 req->wr.wr_mid = cpu_to_be32( 152 req->wr.wr_mid = cpu_to_be32(
@@ -173,19 +172,23 @@ static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
173 if (copy_len % T4_ULPTX_MIN_IO) 172 if (copy_len % T4_ULPTX_MIN_IO)
174 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO - 173 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
175 (copy_len % T4_ULPTX_MIN_IO)); 174 (copy_len % T4_ULPTX_MIN_IO));
176 ret = c4iw_ofld_send(rdev, skb); 175 if (i == (num_wqe-1))
177 skb = NULL; 176 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0,
177 __func__);
178 else
179 ret = c4iw_ofld_send(rdev, skb);
178 if (ret) 180 if (ret)
179 return ret; 181 break;
182 skb = NULL;
180 len -= C4IW_MAX_INLINE_SIZE; 183 len -= C4IW_MAX_INLINE_SIZE;
181 } 184 }
182 185
183 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
184 return ret; 186 return ret;
185} 187}
186 188
187static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, 189static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len,
188 void *data, struct sk_buff *skb) 190 void *data, struct sk_buff *skb,
191 struct c4iw_wr_wait *wr_waitp)
189{ 192{
190 u32 remain = len; 193 u32 remain = len;
191 u32 dmalen; 194 u32 dmalen;
@@ -208,7 +211,7 @@ static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len,
208 dmalen = T4_ULPTX_MAX_DMA; 211 dmalen = T4_ULPTX_MAX_DMA;
209 remain -= dmalen; 212 remain -= dmalen;
210 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr, 213 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
211 !remain, skb); 214 skb, remain ? NULL : wr_waitp);
212 if (ret) 215 if (ret)
213 goto out; 216 goto out;
214 addr += dmalen >> 5; 217 addr += dmalen >> 5;
@@ -216,7 +219,8 @@ static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len,
216 daddr += dmalen; 219 daddr += dmalen;
217 } 220 }
218 if (remain) 221 if (remain)
219 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb); 222 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb,
223 wr_waitp);
220out: 224out:
221 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE); 225 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
222 return ret; 226 return ret;
@@ -227,23 +231,33 @@ out:
227 * If data is NULL, clear len byte of memory to zero. 231 * If data is NULL, clear len byte of memory to zero.
228 */ 232 */
229static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, 233static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
230 void *data, struct sk_buff *skb) 234 void *data, struct sk_buff *skb,
235 struct c4iw_wr_wait *wr_waitp)
231{ 236{
232 if (rdev->lldi.ulptx_memwrite_dsgl && use_dsgl) { 237 int ret;
233 if (len > inline_threshold) { 238
234 if (_c4iw_write_mem_dma(rdev, addr, len, data, skb)) { 239 if (!rdev->lldi.ulptx_memwrite_dsgl || !use_dsgl) {
235 pr_warn_ratelimited("%s: dma map failure (non fatal)\n", 240 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
236 pci_name(rdev->lldi.pdev)); 241 wr_waitp);
237 return _c4iw_write_mem_inline(rdev, addr, len, 242 goto out;
238 data, skb); 243 }
239 } else { 244
240 return 0; 245 if (len <= inline_threshold) {
241 } 246 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
242 } else 247 wr_waitp);
243 return _c4iw_write_mem_inline(rdev, addr, 248 goto out;
244 len, data, skb); 249 }
245 } else 250
246 return _c4iw_write_mem_inline(rdev, addr, len, data, skb); 251 ret = _c4iw_write_mem_dma(rdev, addr, len, data, skb, wr_waitp);
252 if (ret) {
253 pr_warn_ratelimited("%s: dma map failure (non fatal)\n",
254 pci_name(rdev->lldi.pdev));
255 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb,
256 wr_waitp);
257 }
258out:
259 return ret;
260
247} 261}
248 262
249/* 263/*
@@ -257,7 +271,7 @@ static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
257 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, 271 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
258 int bind_enabled, u32 zbva, u64 to, 272 int bind_enabled, u32 zbva, u64 to,
259 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr, 273 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr,
260 struct sk_buff *skb) 274 struct sk_buff *skb, struct c4iw_wr_wait *wr_waitp)
261{ 275{
262 int err; 276 int err;
263 struct fw_ri_tpte tpt; 277 struct fw_ri_tpte tpt;
@@ -285,8 +299,8 @@ static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
285 mutex_unlock(&rdev->stats.lock); 299 mutex_unlock(&rdev->stats.lock);
286 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff); 300 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
287 } 301 }
288 pr_debug("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n", 302 pr_debug("stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
289 __func__, stag_state, type, pdid, stag_idx); 303 stag_state, type, pdid, stag_idx);
290 304
291 /* write TPT entry */ 305 /* write TPT entry */
292 if (reset_tpt_entry) 306 if (reset_tpt_entry)
@@ -311,7 +325,7 @@ static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
311 } 325 }
312 err = write_adapter_mem(rdev, stag_idx + 326 err = write_adapter_mem(rdev, stag_idx +
313 (rdev->lldi.vr->stag.start >> 5), 327 (rdev->lldi.vr->stag.start >> 5),
314 sizeof(tpt), &tpt, skb); 328 sizeof(tpt), &tpt, skb, wr_waitp);
315 329
316 if (reset_tpt_entry) { 330 if (reset_tpt_entry) {
317 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx); 331 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
@@ -323,45 +337,50 @@ static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
323} 337}
324 338
325static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, 339static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
326 u32 pbl_addr, u32 pbl_size) 340 u32 pbl_addr, u32 pbl_size, struct c4iw_wr_wait *wr_waitp)
327{ 341{
328 int err; 342 int err;
329 343
330 pr_debug("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n", 344 pr_debug("*pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
331 __func__, pbl_addr, rdev->lldi.vr->pbl.start, 345 pbl_addr, rdev->lldi.vr->pbl.start,
332 pbl_size); 346 pbl_size);
333 347
334 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL); 348 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL,
349 wr_waitp);
335 return err; 350 return err;
336} 351}
337 352
338static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, 353static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
339 u32 pbl_addr, struct sk_buff *skb) 354 u32 pbl_addr, struct sk_buff *skb,
355 struct c4iw_wr_wait *wr_waitp)
340{ 356{
341 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 357 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
342 pbl_size, pbl_addr, skb); 358 pbl_size, pbl_addr, skb, wr_waitp);
343} 359}
344 360
345static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid) 361static int allocate_window(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
362 struct c4iw_wr_wait *wr_waitp)
346{ 363{
347 *stag = T4_STAG_UNSET; 364 *stag = T4_STAG_UNSET;
348 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0, 365 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
349 0UL, 0, 0, 0, 0, NULL); 366 0UL, 0, 0, 0, 0, NULL, wr_waitp);
350} 367}
351 368
352static int deallocate_window(struct c4iw_rdev *rdev, u32 stag, 369static int deallocate_window(struct c4iw_rdev *rdev, u32 stag,
353 struct sk_buff *skb) 370 struct sk_buff *skb,
371 struct c4iw_wr_wait *wr_waitp)
354{ 372{
355 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0, 373 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
356 0, skb); 374 0, skb, wr_waitp);
357} 375}
358 376
359static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, 377static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
360 u32 pbl_size, u32 pbl_addr) 378 u32 pbl_size, u32 pbl_addr,
379 struct c4iw_wr_wait *wr_waitp)
361{ 380{
362 *stag = T4_STAG_UNSET; 381 *stag = T4_STAG_UNSET;
363 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0, 382 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
364 0UL, 0, 0, pbl_size, pbl_addr, NULL); 383 0UL, 0, 0, pbl_size, pbl_addr, NULL, wr_waitp);
365} 384}
366 385
367static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag) 386static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
@@ -372,7 +391,7 @@ static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
372 mhp->attr.stag = stag; 391 mhp->attr.stag = stag;
373 mmid = stag >> 8; 392 mmid = stag >> 8;
374 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 393 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
375 pr_debug("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp); 394 pr_debug("mmid 0x%x mhp %p\n", mmid, mhp);
376 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid); 395 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
377} 396}
378 397
@@ -388,14 +407,15 @@ static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
388 mhp->attr.mw_bind_enable, mhp->attr.zbva, 407 mhp->attr.mw_bind_enable, mhp->attr.zbva,
389 mhp->attr.va_fbo, mhp->attr.len ? 408 mhp->attr.va_fbo, mhp->attr.len ?
390 mhp->attr.len : -1, shift - 12, 409 mhp->attr.len : -1, shift - 12,
391 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL); 410 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL,
411 mhp->wr_waitp);
392 if (ret) 412 if (ret)
393 return ret; 413 return ret;
394 414
395 ret = finish_mem_reg(mhp, stag); 415 ret = finish_mem_reg(mhp, stag);
396 if (ret) { 416 if (ret) {
397 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 417 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
398 mhp->attr.pbl_addr, mhp->dereg_skb); 418 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
399 mhp->dereg_skb = NULL; 419 mhp->dereg_skb = NULL;
400 } 420 }
401 return ret; 421 return ret;
@@ -422,18 +442,24 @@ struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
422 int ret; 442 int ret;
423 u32 stag = T4_STAG_UNSET; 443 u32 stag = T4_STAG_UNSET;
424 444
425 pr_debug("%s ib_pd %p\n", __func__, pd); 445 pr_debug("ib_pd %p\n", pd);
426 php = to_c4iw_pd(pd); 446 php = to_c4iw_pd(pd);
427 rhp = php->rhp; 447 rhp = php->rhp;
428 448
429 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 449 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
430 if (!mhp) 450 if (!mhp)
431 return ERR_PTR(-ENOMEM); 451 return ERR_PTR(-ENOMEM);
452 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
453 if (!mhp->wr_waitp) {
454 ret = -ENOMEM;
455 goto err_free_mhp;
456 }
457 c4iw_init_wr_wait(mhp->wr_waitp);
432 458
433 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 459 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
434 if (!mhp->dereg_skb) { 460 if (!mhp->dereg_skb) {
435 ret = -ENOMEM; 461 ret = -ENOMEM;
436 goto err0; 462 goto err_free_wr_wait;
437 } 463 }
438 464
439 mhp->rhp = rhp; 465 mhp->rhp = rhp;
@@ -449,20 +475,22 @@ struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
449 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid, 475 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
450 FW_RI_STAG_NSMR, mhp->attr.perms, 476 FW_RI_STAG_NSMR, mhp->attr.perms,
451 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0, 477 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0,
452 NULL); 478 NULL, mhp->wr_waitp);
453 if (ret) 479 if (ret)
454 goto err1; 480 goto err_free_skb;
455 481
456 ret = finish_mem_reg(mhp, stag); 482 ret = finish_mem_reg(mhp, stag);
457 if (ret) 483 if (ret)
458 goto err2; 484 goto err_dereg_mem;
459 return &mhp->ibmr; 485 return &mhp->ibmr;
460err2: 486err_dereg_mem:
461 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 487 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
462 mhp->attr.pbl_addr, mhp->dereg_skb); 488 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
463err1: 489err_free_wr_wait:
490 c4iw_put_wr_wait(mhp->wr_waitp);
491err_free_skb:
464 kfree_skb(mhp->dereg_skb); 492 kfree_skb(mhp->dereg_skb);
465err0: 493err_free_mhp:
466 kfree(mhp); 494 kfree(mhp);
467 return ERR_PTR(ret); 495 return ERR_PTR(ret);
468} 496}
@@ -473,13 +501,13 @@ struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
473 __be64 *pages; 501 __be64 *pages;
474 int shift, n, len; 502 int shift, n, len;
475 int i, k, entry; 503 int i, k, entry;
476 int err = 0; 504 int err = -ENOMEM;
477 struct scatterlist *sg; 505 struct scatterlist *sg;
478 struct c4iw_dev *rhp; 506 struct c4iw_dev *rhp;
479 struct c4iw_pd *php; 507 struct c4iw_pd *php;
480 struct c4iw_mr *mhp; 508 struct c4iw_mr *mhp;
481 509
482 pr_debug("%s ib_pd %p\n", __func__, pd); 510 pr_debug("ib_pd %p\n", pd);
483 511
484 if (length == ~0ULL) 512 if (length == ~0ULL)
485 return ERR_PTR(-EINVAL); 513 return ERR_PTR(-EINVAL);
@@ -496,34 +524,31 @@ struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
496 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 524 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
497 if (!mhp) 525 if (!mhp)
498 return ERR_PTR(-ENOMEM); 526 return ERR_PTR(-ENOMEM);
527 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
528 if (!mhp->wr_waitp)
529 goto err_free_mhp;
499 530
500 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 531 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
501 if (!mhp->dereg_skb) { 532 if (!mhp->dereg_skb)
502 kfree(mhp); 533 goto err_free_wr_wait;
503 return ERR_PTR(-ENOMEM);
504 }
505 534
506 mhp->rhp = rhp; 535 mhp->rhp = rhp;
507 536
508 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0); 537 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0);
509 if (IS_ERR(mhp->umem)) { 538 if (IS_ERR(mhp->umem))
510 err = PTR_ERR(mhp->umem); 539 goto err_free_skb;
511 kfree_skb(mhp->dereg_skb);
512 kfree(mhp);
513 return ERR_PTR(err);
514 }
515 540
516 shift = mhp->umem->page_shift; 541 shift = mhp->umem->page_shift;
517 542
518 n = mhp->umem->nmap; 543 n = mhp->umem->nmap;
519 err = alloc_pbl(mhp, n); 544 err = alloc_pbl(mhp, n);
520 if (err) 545 if (err)
521 goto err; 546 goto err_umem_release;
522 547
523 pages = (__be64 *) __get_free_page(GFP_KERNEL); 548 pages = (__be64 *) __get_free_page(GFP_KERNEL);
524 if (!pages) { 549 if (!pages) {
525 err = -ENOMEM; 550 err = -ENOMEM;
526 goto err_pbl; 551 goto err_pbl_free;
527 } 552 }
528 553
529 i = n = 0; 554 i = n = 0;
@@ -536,7 +561,8 @@ struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
536 if (i == PAGE_SIZE / sizeof *pages) { 561 if (i == PAGE_SIZE / sizeof *pages) {
537 err = write_pbl(&mhp->rhp->rdev, 562 err = write_pbl(&mhp->rhp->rdev,
538 pages, 563 pages,
539 mhp->attr.pbl_addr + (n << 3), i); 564 mhp->attr.pbl_addr + (n << 3), i,
565 mhp->wr_waitp);
540 if (err) 566 if (err)
541 goto pbl_done; 567 goto pbl_done;
542 n += i; 568 n += i;
@@ -547,12 +573,13 @@ struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
547 573
548 if (i) 574 if (i)
549 err = write_pbl(&mhp->rhp->rdev, pages, 575 err = write_pbl(&mhp->rhp->rdev, pages,
550 mhp->attr.pbl_addr + (n << 3), i); 576 mhp->attr.pbl_addr + (n << 3), i,
577 mhp->wr_waitp);
551 578
552pbl_done: 579pbl_done:
553 free_page((unsigned long) pages); 580 free_page((unsigned long) pages);
554 if (err) 581 if (err)
555 goto err_pbl; 582 goto err_pbl_free;
556 583
557 mhp->attr.pdid = php->pdid; 584 mhp->attr.pdid = php->pdid;
558 mhp->attr.zbva = 0; 585 mhp->attr.zbva = 0;
@@ -563,17 +590,20 @@ pbl_done:
563 590
564 err = register_mem(rhp, php, mhp, shift); 591 err = register_mem(rhp, php, mhp, shift);
565 if (err) 592 if (err)
566 goto err_pbl; 593 goto err_pbl_free;
567 594
568 return &mhp->ibmr; 595 return &mhp->ibmr;
569 596
570err_pbl: 597err_pbl_free:
571 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 598 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
572 mhp->attr.pbl_size << 3); 599 mhp->attr.pbl_size << 3);
573 600err_umem_release:
574err:
575 ib_umem_release(mhp->umem); 601 ib_umem_release(mhp->umem);
602err_free_skb:
576 kfree_skb(mhp->dereg_skb); 603 kfree_skb(mhp->dereg_skb);
604err_free_wr_wait:
605 c4iw_put_wr_wait(mhp->wr_waitp);
606err_free_mhp:
577 kfree(mhp); 607 kfree(mhp);
578 return ERR_PTR(err); 608 return ERR_PTR(err);
579} 609}
@@ -597,13 +627,19 @@ struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
597 if (!mhp) 627 if (!mhp)
598 return ERR_PTR(-ENOMEM); 628 return ERR_PTR(-ENOMEM);
599 629
630 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
631 if (!mhp->wr_waitp) {
632 ret = -ENOMEM;
633 goto free_mhp;
634 }
635
600 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 636 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
601 if (!mhp->dereg_skb) { 637 if (!mhp->dereg_skb) {
602 ret = -ENOMEM; 638 ret = -ENOMEM;
603 goto free_mhp; 639 goto free_wr_wait;
604 } 640 }
605 641
606 ret = allocate_window(&rhp->rdev, &stag, php->pdid); 642 ret = allocate_window(&rhp->rdev, &stag, php->pdid, mhp->wr_waitp);
607 if (ret) 643 if (ret)
608 goto free_skb; 644 goto free_skb;
609 mhp->rhp = rhp; 645 mhp->rhp = rhp;
@@ -616,13 +652,16 @@ struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
616 ret = -ENOMEM; 652 ret = -ENOMEM;
617 goto dealloc_win; 653 goto dealloc_win;
618 } 654 }
619 pr_debug("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 655 pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag);
620 return &(mhp->ibmw); 656 return &(mhp->ibmw);
621 657
622dealloc_win: 658dealloc_win:
623 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb); 659 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb,
660 mhp->wr_waitp);
624free_skb: 661free_skb:
625 kfree_skb(mhp->dereg_skb); 662 kfree_skb(mhp->dereg_skb);
663free_wr_wait:
664 c4iw_put_wr_wait(mhp->wr_waitp);
626free_mhp: 665free_mhp:
627 kfree(mhp); 666 kfree(mhp);
628 return ERR_PTR(ret); 667 return ERR_PTR(ret);
@@ -638,10 +677,12 @@ int c4iw_dealloc_mw(struct ib_mw *mw)
638 rhp = mhp->rhp; 677 rhp = mhp->rhp;
639 mmid = (mw->rkey) >> 8; 678 mmid = (mw->rkey) >> 8;
640 remove_handle(rhp, &rhp->mmidr, mmid); 679 remove_handle(rhp, &rhp->mmidr, mmid);
641 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb); 680 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb,
681 mhp->wr_waitp);
642 kfree_skb(mhp->dereg_skb); 682 kfree_skb(mhp->dereg_skb);
683 c4iw_put_wr_wait(mhp->wr_waitp);
643 kfree(mhp); 684 kfree(mhp);
644 pr_debug("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp); 685 pr_debug("ib_mw %p mmid 0x%x ptr %p\n", mw, mmid, mhp);
645 return 0; 686 return 0;
646} 687}
647 688
@@ -671,23 +712,31 @@ struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
671 goto err; 712 goto err;
672 } 713 }
673 714
715 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
716 if (!mhp->wr_waitp) {
717 ret = -ENOMEM;
718 goto err_free_mhp;
719 }
720 c4iw_init_wr_wait(mhp->wr_waitp);
721
674 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev, 722 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev,
675 length, &mhp->mpl_addr, GFP_KERNEL); 723 length, &mhp->mpl_addr, GFP_KERNEL);
676 if (!mhp->mpl) { 724 if (!mhp->mpl) {
677 ret = -ENOMEM; 725 ret = -ENOMEM;
678 goto err_mpl; 726 goto err_free_wr_wait;
679 } 727 }
680 mhp->max_mpl_len = length; 728 mhp->max_mpl_len = length;
681 729
682 mhp->rhp = rhp; 730 mhp->rhp = rhp;
683 ret = alloc_pbl(mhp, max_num_sg); 731 ret = alloc_pbl(mhp, max_num_sg);
684 if (ret) 732 if (ret)
685 goto err1; 733 goto err_free_dma;
686 mhp->attr.pbl_size = max_num_sg; 734 mhp->attr.pbl_size = max_num_sg;
687 ret = allocate_stag(&rhp->rdev, &stag, php->pdid, 735 ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
688 mhp->attr.pbl_size, mhp->attr.pbl_addr); 736 mhp->attr.pbl_size, mhp->attr.pbl_addr,
737 mhp->wr_waitp);
689 if (ret) 738 if (ret)
690 goto err2; 739 goto err_free_pbl;
691 mhp->attr.pdid = php->pdid; 740 mhp->attr.pdid = php->pdid;
692 mhp->attr.type = FW_RI_STAG_NSMR; 741 mhp->attr.type = FW_RI_STAG_NSMR;
693 mhp->attr.stag = stag; 742 mhp->attr.stag = stag;
@@ -696,21 +745,23 @@ struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
696 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 745 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
697 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 746 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
698 ret = -ENOMEM; 747 ret = -ENOMEM;
699 goto err3; 748 goto err_dereg;
700 } 749 }
701 750
702 pr_debug("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 751 pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag);
703 return &(mhp->ibmr); 752 return &(mhp->ibmr);
704err3: 753err_dereg:
705 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size, 754 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
706 mhp->attr.pbl_addr, mhp->dereg_skb); 755 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
707err2: 756err_free_pbl:
708 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 757 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
709 mhp->attr.pbl_size << 3); 758 mhp->attr.pbl_size << 3);
710err1: 759err_free_dma:
711 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev, 760 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
712 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 761 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
713err_mpl: 762err_free_wr_wait:
763 c4iw_put_wr_wait(mhp->wr_waitp);
764err_free_mhp:
714 kfree(mhp); 765 kfree(mhp);
715err: 766err:
716 return ERR_PTR(ret); 767 return ERR_PTR(ret);
@@ -744,7 +795,7 @@ int c4iw_dereg_mr(struct ib_mr *ib_mr)
744 struct c4iw_mr *mhp; 795 struct c4iw_mr *mhp;
745 u32 mmid; 796 u32 mmid;
746 797
747 pr_debug("%s ib_mr %p\n", __func__, ib_mr); 798 pr_debug("ib_mr %p\n", ib_mr);
748 799
749 mhp = to_c4iw_mr(ib_mr); 800 mhp = to_c4iw_mr(ib_mr);
750 rhp = mhp->rhp; 801 rhp = mhp->rhp;
@@ -754,7 +805,7 @@ int c4iw_dereg_mr(struct ib_mr *ib_mr)
754 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev, 805 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
755 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 806 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
756 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 807 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
757 mhp->attr.pbl_addr, mhp->dereg_skb); 808 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp);
758 if (mhp->attr.pbl_size) 809 if (mhp->attr.pbl_size)
759 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 810 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
760 mhp->attr.pbl_size << 3); 811 mhp->attr.pbl_size << 3);
@@ -762,7 +813,8 @@ int c4iw_dereg_mr(struct ib_mr *ib_mr)
762 kfree((void *) (unsigned long) mhp->kva); 813 kfree((void *) (unsigned long) mhp->kva);
763 if (mhp->umem) 814 if (mhp->umem)
764 ib_umem_release(mhp->umem); 815 ib_umem_release(mhp->umem);
765 pr_debug("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp); 816 pr_debug("mmid 0x%x ptr %p\n", mmid, mhp);
817 c4iw_put_wr_wait(mhp->wr_waitp);
766 kfree(mhp); 818 kfree(mhp);
767 return 0; 819 return 0;
768} 820}
diff --git a/drivers/infiniband/hw/cxgb4/provider.c b/drivers/infiniband/hw/cxgb4/provider.c
index 346e8334279a..1b5c6cd2ac4d 100644
--- a/drivers/infiniband/hw/cxgb4/provider.c
+++ b/drivers/infiniband/hw/cxgb4/provider.c
@@ -102,7 +102,7 @@ void _c4iw_free_ucontext(struct kref *kref)
102 ucontext = container_of(kref, struct c4iw_ucontext, kref); 102 ucontext = container_of(kref, struct c4iw_ucontext, kref);
103 rhp = to_c4iw_dev(ucontext->ibucontext.device); 103 rhp = to_c4iw_dev(ucontext->ibucontext.device);
104 104
105 pr_debug("%s ucontext %p\n", __func__, ucontext); 105 pr_debug("ucontext %p\n", ucontext);
106 list_for_each_entry_safe(mm, tmp, &ucontext->mmaps, entry) 106 list_for_each_entry_safe(mm, tmp, &ucontext->mmaps, entry)
107 kfree(mm); 107 kfree(mm);
108 c4iw_release_dev_ucontext(&rhp->rdev, &ucontext->uctx); 108 c4iw_release_dev_ucontext(&rhp->rdev, &ucontext->uctx);
@@ -113,7 +113,7 @@ static int c4iw_dealloc_ucontext(struct ib_ucontext *context)
113{ 113{
114 struct c4iw_ucontext *ucontext = to_c4iw_ucontext(context); 114 struct c4iw_ucontext *ucontext = to_c4iw_ucontext(context);
115 115
116 pr_debug("%s context %p\n", __func__, context); 116 pr_debug("context %p\n", context);
117 c4iw_put_ucontext(ucontext); 117 c4iw_put_ucontext(ucontext);
118 return 0; 118 return 0;
119} 119}
@@ -127,7 +127,7 @@ static struct ib_ucontext *c4iw_alloc_ucontext(struct ib_device *ibdev,
127 int ret = 0; 127 int ret = 0;
128 struct c4iw_mm_entry *mm = NULL; 128 struct c4iw_mm_entry *mm = NULL;
129 129
130 pr_debug("%s ibdev %p\n", __func__, ibdev); 130 pr_debug("ibdev %p\n", ibdev);
131 context = kzalloc(sizeof(*context), GFP_KERNEL); 131 context = kzalloc(sizeof(*context), GFP_KERNEL);
132 if (!context) { 132 if (!context) {
133 ret = -ENOMEM; 133 ret = -ENOMEM;
@@ -185,7 +185,7 @@ static int c4iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
185 struct c4iw_ucontext *ucontext; 185 struct c4iw_ucontext *ucontext;
186 u64 addr; 186 u64 addr;
187 187
188 pr_debug("%s pgoff 0x%lx key 0x%x len %d\n", __func__, vma->vm_pgoff, 188 pr_debug("pgoff 0x%lx key 0x%x len %d\n", vma->vm_pgoff,
189 key, len); 189 key, len);
190 190
191 if (vma->vm_start & (PAGE_SIZE-1)) 191 if (vma->vm_start & (PAGE_SIZE-1))
@@ -251,7 +251,7 @@ static int c4iw_deallocate_pd(struct ib_pd *pd)
251 251
252 php = to_c4iw_pd(pd); 252 php = to_c4iw_pd(pd);
253 rhp = php->rhp; 253 rhp = php->rhp;
254 pr_debug("%s ibpd %p pdid 0x%x\n", __func__, pd, php->pdid); 254 pr_debug("ibpd %p pdid 0x%x\n", pd, php->pdid);
255 c4iw_put_resource(&rhp->rdev.resource.pdid_table, php->pdid); 255 c4iw_put_resource(&rhp->rdev.resource.pdid_table, php->pdid);
256 mutex_lock(&rhp->rdev.stats.lock); 256 mutex_lock(&rhp->rdev.stats.lock);
257 rhp->rdev.stats.pd.cur--; 257 rhp->rdev.stats.pd.cur--;
@@ -268,7 +268,7 @@ static struct ib_pd *c4iw_allocate_pd(struct ib_device *ibdev,
268 u32 pdid; 268 u32 pdid;
269 struct c4iw_dev *rhp; 269 struct c4iw_dev *rhp;
270 270
271 pr_debug("%s ibdev %p\n", __func__, ibdev); 271 pr_debug("ibdev %p\n", ibdev);
272 rhp = (struct c4iw_dev *) ibdev; 272 rhp = (struct c4iw_dev *) ibdev;
273 pdid = c4iw_get_resource(&rhp->rdev.resource.pdid_table); 273 pdid = c4iw_get_resource(&rhp->rdev.resource.pdid_table);
274 if (!pdid) 274 if (!pdid)
@@ -291,14 +291,14 @@ static struct ib_pd *c4iw_allocate_pd(struct ib_device *ibdev,
291 if (rhp->rdev.stats.pd.cur > rhp->rdev.stats.pd.max) 291 if (rhp->rdev.stats.pd.cur > rhp->rdev.stats.pd.max)
292 rhp->rdev.stats.pd.max = rhp->rdev.stats.pd.cur; 292 rhp->rdev.stats.pd.max = rhp->rdev.stats.pd.cur;
293 mutex_unlock(&rhp->rdev.stats.lock); 293 mutex_unlock(&rhp->rdev.stats.lock);
294 pr_debug("%s pdid 0x%0x ptr 0x%p\n", __func__, pdid, php); 294 pr_debug("pdid 0x%0x ptr 0x%p\n", pdid, php);
295 return &php->ibpd; 295 return &php->ibpd;
296} 296}
297 297
298static int c4iw_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 298static int c4iw_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
299 u16 *pkey) 299 u16 *pkey)
300{ 300{
301 pr_debug("%s ibdev %p\n", __func__, ibdev); 301 pr_debug("ibdev %p\n", ibdev);
302 *pkey = 0; 302 *pkey = 0;
303 return 0; 303 return 0;
304} 304}
@@ -308,10 +308,11 @@ static int c4iw_query_gid(struct ib_device *ibdev, u8 port, int index,
308{ 308{
309 struct c4iw_dev *dev; 309 struct c4iw_dev *dev;
310 310
311 pr_debug("%s ibdev %p, port %d, index %d, gid %p\n", 311 pr_debug("ibdev %p, port %d, index %d, gid %p\n",
312 __func__, ibdev, port, index, gid); 312 ibdev, port, index, gid);
313 if (!port)
314 return -EINVAL;
313 dev = to_c4iw_dev(ibdev); 315 dev = to_c4iw_dev(ibdev);
314 BUG_ON(port == 0);
315 memset(&(gid->raw[0]), 0, sizeof(gid->raw)); 316 memset(&(gid->raw[0]), 0, sizeof(gid->raw));
316 memcpy(&(gid->raw[0]), dev->rdev.lldi.ports[port-1]->dev_addr, 6); 317 memcpy(&(gid->raw[0]), dev->rdev.lldi.ports[port-1]->dev_addr, 6);
317 return 0; 318 return 0;
@@ -323,7 +324,7 @@ static int c4iw_query_device(struct ib_device *ibdev, struct ib_device_attr *pro
323 324
324 struct c4iw_dev *dev; 325 struct c4iw_dev *dev;
325 326
326 pr_debug("%s ibdev %p\n", __func__, ibdev); 327 pr_debug("ibdev %p\n", ibdev);
327 328
328 if (uhw->inlen || uhw->outlen) 329 if (uhw->inlen || uhw->outlen)
329 return -EINVAL; 330 return -EINVAL;
@@ -364,7 +365,7 @@ static int c4iw_query_port(struct ib_device *ibdev, u8 port,
364 struct net_device *netdev; 365 struct net_device *netdev;
365 struct in_device *inetdev; 366 struct in_device *inetdev;
366 367
367 pr_debug("%s ibdev %p\n", __func__, ibdev); 368 pr_debug("ibdev %p\n", ibdev);
368 369
369 dev = to_c4iw_dev(ibdev); 370 dev = to_c4iw_dev(ibdev);
370 netdev = dev->rdev.lldi.ports[port-1]; 371 netdev = dev->rdev.lldi.ports[port-1];
@@ -406,7 +407,7 @@ static ssize_t show_rev(struct device *dev, struct device_attribute *attr,
406{ 407{
407 struct c4iw_dev *c4iw_dev = container_of(dev, struct c4iw_dev, 408 struct c4iw_dev *c4iw_dev = container_of(dev, struct c4iw_dev,
408 ibdev.dev); 409 ibdev.dev);
409 pr_debug("%s dev 0x%p\n", __func__, dev); 410 pr_debug("dev 0x%p\n", dev);
410 return sprintf(buf, "%d\n", 411 return sprintf(buf, "%d\n",
411 CHELSIO_CHIP_RELEASE(c4iw_dev->rdev.lldi.adapter_type)); 412 CHELSIO_CHIP_RELEASE(c4iw_dev->rdev.lldi.adapter_type));
412} 413}
@@ -419,7 +420,7 @@ static ssize_t show_hca(struct device *dev, struct device_attribute *attr,
419 struct ethtool_drvinfo info; 420 struct ethtool_drvinfo info;
420 struct net_device *lldev = c4iw_dev->rdev.lldi.ports[0]; 421 struct net_device *lldev = c4iw_dev->rdev.lldi.ports[0];
421 422
422 pr_debug("%s dev 0x%p\n", __func__, dev); 423 pr_debug("dev 0x%p\n", dev);
423 lldev->ethtool_ops->get_drvinfo(lldev, &info); 424 lldev->ethtool_ops->get_drvinfo(lldev, &info);
424 return sprintf(buf, "%s\n", info.driver); 425 return sprintf(buf, "%s\n", info.driver);
425} 426}
@@ -429,7 +430,7 @@ static ssize_t show_board(struct device *dev, struct device_attribute *attr,
429{ 430{
430 struct c4iw_dev *c4iw_dev = container_of(dev, struct c4iw_dev, 431 struct c4iw_dev *c4iw_dev = container_of(dev, struct c4iw_dev,
431 ibdev.dev); 432 ibdev.dev);
432 pr_debug("%s dev 0x%p\n", __func__, dev); 433 pr_debug("dev 0x%p\n", dev);
433 return sprintf(buf, "%x.%x\n", c4iw_dev->rdev.lldi.pdev->vendor, 434 return sprintf(buf, "%x.%x\n", c4iw_dev->rdev.lldi.pdev->vendor,
434 c4iw_dev->rdev.lldi.pdev->device); 435 c4iw_dev->rdev.lldi.pdev->device);
435} 436}
@@ -521,7 +522,7 @@ static void get_dev_fw_str(struct ib_device *dev, char *str)
521{ 522{
522 struct c4iw_dev *c4iw_dev = container_of(dev, struct c4iw_dev, 523 struct c4iw_dev *c4iw_dev = container_of(dev, struct c4iw_dev,
523 ibdev); 524 ibdev);
524 pr_debug("%s dev 0x%p\n", __func__, dev); 525 pr_debug("dev 0x%p\n", dev);
525 526
526 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u.%u", 527 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%u.%u",
527 FW_HDR_FW_VER_MAJOR_G(c4iw_dev->rdev.lldi.fw_vers), 528 FW_HDR_FW_VER_MAJOR_G(c4iw_dev->rdev.lldi.fw_vers),
@@ -530,13 +531,14 @@ static void get_dev_fw_str(struct ib_device *dev, char *str)
530 FW_HDR_FW_VER_BUILD_G(c4iw_dev->rdev.lldi.fw_vers)); 531 FW_HDR_FW_VER_BUILD_G(c4iw_dev->rdev.lldi.fw_vers));
531} 532}
532 533
533int c4iw_register_device(struct c4iw_dev *dev) 534void c4iw_register_device(struct work_struct *work)
534{ 535{
535 int ret; 536 int ret;
536 int i; 537 int i;
538 struct uld_ctx *ctx = container_of(work, struct uld_ctx, reg_work);
539 struct c4iw_dev *dev = ctx->dev;
537 540
538 pr_debug("%s c4iw_dev %p\n", __func__, dev); 541 pr_debug("c4iw_dev %p\n", dev);
539 BUG_ON(!dev->rdev.lldi.ports[0]);
540 strlcpy(dev->ibdev.name, "cxgb4_%d", IB_DEVICE_NAME_MAX); 542 strlcpy(dev->ibdev.name, "cxgb4_%d", IB_DEVICE_NAME_MAX);
541 memset(&dev->ibdev.node_guid, 0, sizeof(dev->ibdev.node_guid)); 543 memset(&dev->ibdev.node_guid, 0, sizeof(dev->ibdev.node_guid));
542 memcpy(&dev->ibdev.node_guid, dev->rdev.lldi.ports[0]->dev_addr, 6); 544 memcpy(&dev->ibdev.node_guid, dev->rdev.lldi.ports[0]->dev_addr, 6);
@@ -609,8 +611,10 @@ int c4iw_register_device(struct c4iw_dev *dev)
609 dev->ibdev.get_dev_fw_str = get_dev_fw_str; 611 dev->ibdev.get_dev_fw_str = get_dev_fw_str;
610 612
611 dev->ibdev.iwcm = kmalloc(sizeof(struct iw_cm_verbs), GFP_KERNEL); 613 dev->ibdev.iwcm = kmalloc(sizeof(struct iw_cm_verbs), GFP_KERNEL);
612 if (!dev->ibdev.iwcm) 614 if (!dev->ibdev.iwcm) {
613 return -ENOMEM; 615 ret = -ENOMEM;
616 goto err_dealloc_ctx;
617 }
614 618
615 dev->ibdev.iwcm->connect = c4iw_connect; 619 dev->ibdev.iwcm->connect = c4iw_connect;
616 dev->ibdev.iwcm->accept = c4iw_accept_cr; 620 dev->ibdev.iwcm->accept = c4iw_accept_cr;
@@ -625,27 +629,31 @@ int c4iw_register_device(struct c4iw_dev *dev)
625 629
626 ret = ib_register_device(&dev->ibdev, NULL); 630 ret = ib_register_device(&dev->ibdev, NULL);
627 if (ret) 631 if (ret)
628 goto bail1; 632 goto err_kfree_iwcm;
629 633
630 for (i = 0; i < ARRAY_SIZE(c4iw_class_attributes); ++i) { 634 for (i = 0; i < ARRAY_SIZE(c4iw_class_attributes); ++i) {
631 ret = device_create_file(&dev->ibdev.dev, 635 ret = device_create_file(&dev->ibdev.dev,
632 c4iw_class_attributes[i]); 636 c4iw_class_attributes[i]);
633 if (ret) 637 if (ret)
634 goto bail2; 638 goto err_unregister_device;
635 } 639 }
636 return 0; 640 return;
637bail2: 641err_unregister_device:
638 ib_unregister_device(&dev->ibdev); 642 ib_unregister_device(&dev->ibdev);
639bail1: 643err_kfree_iwcm:
640 kfree(dev->ibdev.iwcm); 644 kfree(dev->ibdev.iwcm);
641 return ret; 645err_dealloc_ctx:
646 pr_err("%s - Failed registering iwarp device: %d\n",
647 pci_name(ctx->lldi.pdev), ret);
648 c4iw_dealloc(ctx);
649 return;
642} 650}
643 651
644void c4iw_unregister_device(struct c4iw_dev *dev) 652void c4iw_unregister_device(struct c4iw_dev *dev)
645{ 653{
646 int i; 654 int i;
647 655
648 pr_debug("%s c4iw_dev %p\n", __func__, dev); 656 pr_debug("c4iw_dev %p\n", dev);
649 for (i = 0; i < ARRAY_SIZE(c4iw_class_attributes); ++i) 657 for (i = 0; i < ARRAY_SIZE(c4iw_class_attributes); ++i)
650 device_remove_file(&dev->ibdev.dev, 658 device_remove_file(&dev->ibdev.dev,
651 c4iw_class_attributes[i]); 659 c4iw_class_attributes[i]);
diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index cb7fc0d35d1d..5ee7fe433136 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -194,13 +194,13 @@ void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
194 194
195static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 195static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
196 struct t4_cq *rcq, struct t4_cq *scq, 196 struct t4_cq *rcq, struct t4_cq *scq,
197 struct c4iw_dev_ucontext *uctx) 197 struct c4iw_dev_ucontext *uctx,
198 struct c4iw_wr_wait *wr_waitp)
198{ 199{
199 int user = (uctx != &rdev->uctx); 200 int user = (uctx != &rdev->uctx);
200 struct fw_ri_res_wr *res_wr; 201 struct fw_ri_res_wr *res_wr;
201 struct fw_ri_res *res; 202 struct fw_ri_res *res;
202 int wr_len; 203 int wr_len;
203 struct c4iw_wr_wait wr_wait;
204 struct sk_buff *skb; 204 struct sk_buff *skb;
205 int ret = 0; 205 int ret = 0;
206 int eqsize; 206 int eqsize;
@@ -254,8 +254,8 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
254 ret = -ENOMEM; 254 ret = -ENOMEM;
255 goto free_sq; 255 goto free_sq;
256 } 256 }
257 pr_debug("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n", 257 pr_debug("sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
258 __func__, wq->sq.queue, 258 wq->sq.queue,
259 (unsigned long long)virt_to_phys(wq->sq.queue), 259 (unsigned long long)virt_to_phys(wq->sq.queue),
260 wq->rq.queue, 260 wq->rq.queue,
261 (unsigned long long)virt_to_phys(wq->rq.queue)); 261 (unsigned long long)virt_to_phys(wq->rq.queue));
@@ -299,7 +299,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
299 FW_RI_RES_WR_NRES_V(2) | 299 FW_RI_RES_WR_NRES_V(2) |
300 FW_WR_COMPL_F); 300 FW_WR_COMPL_F);
301 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 301 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
302 res_wr->cookie = (uintptr_t)&wr_wait; 302 res_wr->cookie = (uintptr_t)wr_waitp;
303 res = res_wr->res; 303 res = res_wr->res;
304 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 304 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
305 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 305 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
@@ -352,17 +352,13 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
354 354
355 c4iw_init_wr_wait(&wr_wait); 355 c4iw_init_wr_wait(wr_waitp);
356 356 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, wq->sq.qid, __func__);
357 ret = c4iw_ofld_send(rdev, skb);
358 if (ret)
359 goto free_dma;
360 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
361 if (ret) 357 if (ret)
362 goto free_dma; 358 goto free_dma;
363 359
364 pr_debug("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n", 360 pr_debug("sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
365 __func__, wq->sq.qid, wq->rq.qid, wq->db, 361 wq->sq.qid, wq->rq.qid, wq->db,
366 wq->sq.bar2_va, wq->rq.bar2_va); 362 wq->sq.bar2_va, wq->rq.bar2_va);
367 363
368 return 0; 364 return 0;
@@ -693,7 +689,6 @@ static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
693 if (++p == (__be64 *)&sq->queue[sq->size]) 689 if (++p == (__be64 *)&sq->queue[sq->size])
694 p = (__be64 *)sq->queue; 690 p = (__be64 *)sq->queue;
695 } 691 }
696 BUG_ON(rem < 0);
697 while (rem) { 692 while (rem) {
698 *p = 0; 693 *p = 0;
699 rem -= sizeof(*p); 694 rem -= sizeof(*p);
@@ -724,12 +719,13 @@ static void free_qp_work(struct work_struct *work)
724 ucontext = qhp->ucontext; 719 ucontext = qhp->ucontext;
725 rhp = qhp->rhp; 720 rhp = qhp->rhp;
726 721
727 pr_debug("%s qhp %p ucontext %p\n", __func__, qhp, ucontext); 722 pr_debug("qhp %p ucontext %p\n", qhp, ucontext);
728 destroy_qp(&rhp->rdev, &qhp->wq, 723 destroy_qp(&rhp->rdev, &qhp->wq,
729 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 724 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
730 725
731 if (ucontext) 726 if (ucontext)
732 c4iw_put_ucontext(ucontext); 727 c4iw_put_ucontext(ucontext);
728 c4iw_put_wr_wait(qhp->wr_waitp);
733 kfree(qhp); 729 kfree(qhp);
734} 730}
735 731
@@ -738,19 +734,19 @@ static void queue_qp_free(struct kref *kref)
738 struct c4iw_qp *qhp; 734 struct c4iw_qp *qhp;
739 735
740 qhp = container_of(kref, struct c4iw_qp, kref); 736 qhp = container_of(kref, struct c4iw_qp, kref);
741 pr_debug("%s qhp %p\n", __func__, qhp); 737 pr_debug("qhp %p\n", qhp);
742 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work); 738 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work);
743} 739}
744 740
745void c4iw_qp_add_ref(struct ib_qp *qp) 741void c4iw_qp_add_ref(struct ib_qp *qp)
746{ 742{
747 pr_debug("%s ib_qp %p\n", __func__, qp); 743 pr_debug("ib_qp %p\n", qp);
748 kref_get(&to_c4iw_qp(qp)->kref); 744 kref_get(&to_c4iw_qp(qp)->kref);
749} 745}
750 746
751void c4iw_qp_rem_ref(struct ib_qp *qp) 747void c4iw_qp_rem_ref(struct ib_qp *qp)
752{ 748{
753 pr_debug("%s ib_qp %p\n", __func__, qp); 749 pr_debug("ib_qp %p\n", qp);
754 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free); 750 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free);
755} 751}
756 752
@@ -817,10 +813,12 @@ static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
817 t4_swcq_produce(cq); 813 t4_swcq_produce(cq);
818 spin_unlock_irqrestore(&schp->lock, flag); 814 spin_unlock_irqrestore(&schp->lock, flag);
819 815
820 spin_lock_irqsave(&schp->comp_handler_lock, flag); 816 if (t4_clear_cq_armed(&schp->cq)) {
821 (*schp->ibcq.comp_handler)(&schp->ibcq, 817 spin_lock_irqsave(&schp->comp_handler_lock, flag);
822 schp->ibcq.cq_context); 818 (*schp->ibcq.comp_handler)(&schp->ibcq,
823 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 819 schp->ibcq.cq_context);
820 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
821 }
824} 822}
825 823
826static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr) 824static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
@@ -846,10 +844,12 @@ static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
846 t4_swcq_produce(cq); 844 t4_swcq_produce(cq);
847 spin_unlock_irqrestore(&rchp->lock, flag); 845 spin_unlock_irqrestore(&rchp->lock, flag);
848 846
849 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 847 if (t4_clear_cq_armed(&rchp->cq)) {
850 (*rchp->ibcq.comp_handler)(&rchp->ibcq, 848 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
851 rchp->ibcq.cq_context); 849 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
852 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 850 rchp->ibcq.cq_context);
851 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
852 }
853} 853}
854 854
855int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 855int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
@@ -958,8 +958,8 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
958 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey); 958 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
959 break; 959 break;
960 default: 960 default:
961 pr_debug("%s post of type=%d TBD!\n", __func__, 961 pr_warn("%s post of type=%d TBD!\n", __func__,
962 wr->opcode); 962 wr->opcode);
963 err = -EINVAL; 963 err = -EINVAL;
964 } 964 }
965 if (err) { 965 if (err) {
@@ -980,8 +980,7 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
980 980
981 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 981 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
982 982
983 pr_debug("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n", 983 pr_debug("cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
984 __func__,
985 (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 984 (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
986 swsqe->opcode, swsqe->read_len); 985 swsqe->opcode, swsqe->read_len);
987 wr = wr->next; 986 wr = wr->next;
@@ -1057,8 +1056,7 @@ int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1057 wqe->recv.r2[1] = 0; 1056 wqe->recv.r2[1] = 0;
1058 wqe->recv.r2[2] = 0; 1057 wqe->recv.r2[2] = 0;
1059 wqe->recv.len16 = len16; 1058 wqe->recv.len16 = len16;
1060 pr_debug("%s cookie 0x%llx pidx %u\n", 1059 pr_debug("cookie 0x%llx pidx %u\n",
1061 __func__,
1062 (unsigned long long)wr->wr_id, qhp->wq.rq.pidx); 1060 (unsigned long long)wr->wr_id, qhp->wq.rq.pidx);
1063 t4_rq_produce(&qhp->wq, len16); 1061 t4_rq_produce(&qhp->wq, len16);
1064 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 1062 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
@@ -1218,7 +1216,7 @@ static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1218 struct sk_buff *skb; 1216 struct sk_buff *skb;
1219 struct terminate_message *term; 1217 struct terminate_message *term;
1220 1218
1221 pr_debug("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1219 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid,
1222 qhp->ep->hwtid); 1220 qhp->ep->hwtid);
1223 1221
1224 skb = skb_dequeue(&qhp->ep->com.ep_skb_list); 1222 skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
@@ -1255,33 +1253,36 @@ static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1255 int rq_flushed, sq_flushed; 1253 int rq_flushed, sq_flushed;
1256 unsigned long flag; 1254 unsigned long flag;
1257 1255
1258 pr_debug("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp); 1256 pr_debug("qhp %p rchp %p schp %p\n", qhp, rchp, schp);
1259 1257
1260 /* locking hierarchy: cq lock first, then qp lock. */ 1258 /* locking hierarchy: cqs lock first, then qp lock. */
1261 spin_lock_irqsave(&rchp->lock, flag); 1259 spin_lock_irqsave(&rchp->lock, flag);
1260 if (schp != rchp)
1261 spin_lock(&schp->lock);
1262 spin_lock(&qhp->lock); 1262 spin_lock(&qhp->lock);
1263 1263
1264 if (qhp->wq.flushed) { 1264 if (qhp->wq.flushed) {
1265 spin_unlock(&qhp->lock); 1265 spin_unlock(&qhp->lock);
1266 if (schp != rchp)
1267 spin_unlock(&schp->lock);
1266 spin_unlock_irqrestore(&rchp->lock, flag); 1268 spin_unlock_irqrestore(&rchp->lock, flag);
1267 return; 1269 return;
1268 } 1270 }
1269 qhp->wq.flushed = 1; 1271 qhp->wq.flushed = 1;
1272 t4_set_wq_in_error(&qhp->wq);
1270 1273
1271 c4iw_flush_hw_cq(rchp); 1274 c4iw_flush_hw_cq(rchp);
1272 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 1275 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1273 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 1276 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1274 spin_unlock(&qhp->lock);
1275 spin_unlock_irqrestore(&rchp->lock, flag);
1276 1277
1277 /* locking hierarchy: cq lock first, then qp lock. */
1278 spin_lock_irqsave(&schp->lock, flag);
1279 spin_lock(&qhp->lock);
1280 if (schp != rchp) 1278 if (schp != rchp)
1281 c4iw_flush_hw_cq(schp); 1279 c4iw_flush_hw_cq(schp);
1282 sq_flushed = c4iw_flush_sq(qhp); 1280 sq_flushed = c4iw_flush_sq(qhp);
1281
1283 spin_unlock(&qhp->lock); 1282 spin_unlock(&qhp->lock);
1284 spin_unlock_irqrestore(&schp->lock, flag); 1283 if (schp != rchp)
1284 spin_unlock(&schp->lock);
1285 spin_unlock_irqrestore(&rchp->lock, flag);
1285 1286
1286 if (schp == rchp) { 1287 if (schp == rchp) {
1287 if (t4_clear_cq_armed(&rchp->cq) && 1288 if (t4_clear_cq_armed(&rchp->cq) &&
@@ -1315,8 +1316,8 @@ static void flush_qp(struct c4iw_qp *qhp)
1315 rchp = to_c4iw_cq(qhp->ibqp.recv_cq); 1316 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1316 schp = to_c4iw_cq(qhp->ibqp.send_cq); 1317 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1317 1318
1318 t4_set_wq_in_error(&qhp->wq);
1319 if (qhp->ibqp.uobject) { 1319 if (qhp->ibqp.uobject) {
1320 t4_set_wq_in_error(&qhp->wq);
1320 t4_set_cq_in_error(&rchp->cq); 1321 t4_set_cq_in_error(&rchp->cq);
1321 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 1322 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1322 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 1323 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
@@ -1340,8 +1341,7 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1340 int ret; 1341 int ret;
1341 struct sk_buff *skb; 1342 struct sk_buff *skb;
1342 1343
1343 pr_debug("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, 1344 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid, ep->hwtid);
1344 ep->hwtid);
1345 1345
1346 skb = skb_dequeue(&ep->com.ep_skb_list); 1346 skb = skb_dequeue(&ep->com.ep_skb_list);
1347 if (WARN_ON(!skb)) 1347 if (WARN_ON(!skb))
@@ -1357,23 +1357,20 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1357 wqe->flowid_len16 = cpu_to_be32( 1357 wqe->flowid_len16 = cpu_to_be32(
1358 FW_WR_FLOWID_V(ep->hwtid) | 1358 FW_WR_FLOWID_V(ep->hwtid) |
1359 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1359 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1360 wqe->cookie = (uintptr_t)&ep->com.wr_wait; 1360 wqe->cookie = (uintptr_t)ep->com.wr_waitp;
1361 1361
1362 wqe->u.fini.type = FW_RI_TYPE_FINI; 1362 wqe->u.fini.type = FW_RI_TYPE_FINI;
1363 ret = c4iw_ofld_send(&rhp->rdev, skb);
1364 if (ret)
1365 goto out;
1366 1363
1367 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid, 1364 ret = c4iw_ref_send_wait(&rhp->rdev, skb, ep->com.wr_waitp,
1368 qhp->wq.sq.qid, __func__); 1365 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1369out: 1366
1370 pr_debug("%s ret %d\n", __func__, ret); 1367 pr_debug("ret %d\n", ret);
1371 return ret; 1368 return ret;
1372} 1369}
1373 1370
1374static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1371static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1375{ 1372{
1376 pr_debug("%s p2p_type = %d\n", __func__, p2p_type); 1373 pr_debug("p2p_type = %d\n", p2p_type);
1377 memset(&init->u, 0, sizeof init->u); 1374 memset(&init->u, 0, sizeof init->u);
1378 switch (p2p_type) { 1375 switch (p2p_type) {
1379 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1376 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
@@ -1402,7 +1399,7 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1402 int ret; 1399 int ret;
1403 struct sk_buff *skb; 1400 struct sk_buff *skb;
1404 1401
1405 pr_debug("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp, 1402 pr_debug("qhp %p qid 0x%x tid %u ird %u ord %u\n", qhp,
1406 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord); 1403 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1407 1404
1408 skb = alloc_skb(sizeof *wqe, GFP_KERNEL); 1405 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
@@ -1427,7 +1424,7 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1427 FW_WR_FLOWID_V(qhp->ep->hwtid) | 1424 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1428 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16))); 1425 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1429 1426
1430 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait; 1427 wqe->cookie = (uintptr_t)qhp->ep->com.wr_waitp;
1431 1428
1432 wqe->u.init.type = FW_RI_TYPE_INIT; 1429 wqe->u.init.type = FW_RI_TYPE_INIT;
1433 wqe->u.init.mpareqbit_p2ptype = 1430 wqe->u.init.mpareqbit_p2ptype =
@@ -1464,18 +1461,14 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1464 if (qhp->attr.mpa_attr.initiator) 1461 if (qhp->attr.mpa_attr.initiator)
1465 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1462 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1466 1463
1467 ret = c4iw_ofld_send(&rhp->rdev, skb); 1464 ret = c4iw_ref_send_wait(&rhp->rdev, skb, qhp->ep->com.wr_waitp,
1468 if (ret) 1465 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1469 goto err1;
1470
1471 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1472 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1473 if (!ret) 1466 if (!ret)
1474 goto out; 1467 goto out;
1475err1: 1468
1476 free_ird(rhp, qhp->attr.max_ird); 1469 free_ird(rhp, qhp->attr.max_ird);
1477out: 1470out:
1478 pr_debug("%s ret %d\n", __func__, ret); 1471 pr_debug("ret %d\n", ret);
1479 return ret; 1472 return ret;
1480} 1473}
1481 1474
@@ -1492,8 +1485,7 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1492 int free = 0; 1485 int free = 0;
1493 struct c4iw_ep *ep = NULL; 1486 struct c4iw_ep *ep = NULL;
1494 1487
1495 pr_debug("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", 1488 pr_debug("qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n",
1496 __func__,
1497 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state, 1489 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1498 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1490 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1499 1491
@@ -1582,7 +1574,6 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1582 case C4IW_QP_STATE_RTS: 1574 case C4IW_QP_STATE_RTS:
1583 switch (attrs->next_state) { 1575 switch (attrs->next_state) {
1584 case C4IW_QP_STATE_CLOSING: 1576 case C4IW_QP_STATE_CLOSING:
1585 BUG_ON(kref_read(&qhp->ep->com.kref) < 2);
1586 t4_set_wq_in_error(&qhp->wq); 1577 t4_set_wq_in_error(&qhp->wq);
1587 set_state(qhp, C4IW_QP_STATE_CLOSING); 1578 set_state(qhp, C4IW_QP_STATE_CLOSING);
1588 ep = qhp->ep; 1579 ep = qhp->ep;
@@ -1680,7 +1671,7 @@ int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1680 } 1671 }
1681 goto out; 1672 goto out;
1682err: 1673err:
1683 pr_debug("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep, 1674 pr_debug("disassociating ep %p qpid 0x%x\n", qhp->ep,
1684 qhp->wq.sq.qid); 1675 qhp->wq.sq.qid);
1685 1676
1686 /* disassociate the LLP connection */ 1677 /* disassociate the LLP connection */
@@ -1691,7 +1682,6 @@ err:
1691 set_state(qhp, C4IW_QP_STATE_ERROR); 1682 set_state(qhp, C4IW_QP_STATE_ERROR);
1692 free = 1; 1683 free = 1;
1693 abort = 1; 1684 abort = 1;
1694 BUG_ON(!ep);
1695 flush_qp(qhp); 1685 flush_qp(qhp);
1696 wake_up(&qhp->wait); 1686 wake_up(&qhp->wait);
1697out: 1687out:
@@ -1717,7 +1707,7 @@ out:
1717 */ 1707 */
1718 if (free) 1708 if (free)
1719 c4iw_put_ep(&ep->com); 1709 c4iw_put_ep(&ep->com);
1720 pr_debug("%s exit state %d\n", __func__, qhp->attr.state); 1710 pr_debug("exit state %d\n", qhp->attr.state);
1721 return ret; 1711 return ret;
1722} 1712}
1723 1713
@@ -1747,7 +1737,7 @@ int c4iw_destroy_qp(struct ib_qp *ib_qp)
1747 1737
1748 c4iw_qp_rem_ref(ib_qp); 1738 c4iw_qp_rem_ref(ib_qp);
1749 1739
1750 pr_debug("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid); 1740 pr_debug("ib_qp %p qpid 0x%0x\n", ib_qp, qhp->wq.sq.qid);
1751 return 0; 1741 return 0;
1752} 1742}
1753 1743
@@ -1766,7 +1756,7 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1766 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm; 1756 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1767 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL; 1757 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1768 1758
1769 pr_debug("%s ib_pd %p\n", __func__, pd); 1759 pr_debug("ib_pd %p\n", pd);
1770 1760
1771 if (attrs->qp_type != IB_QPT_RC) 1761 if (attrs->qp_type != IB_QPT_RC)
1772 return ERR_PTR(-EINVAL); 1762 return ERR_PTR(-EINVAL);
@@ -1798,6 +1788,13 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1798 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1788 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1799 if (!qhp) 1789 if (!qhp)
1800 return ERR_PTR(-ENOMEM); 1790 return ERR_PTR(-ENOMEM);
1791
1792 qhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
1793 if (!qhp->wr_waitp) {
1794 ret = -ENOMEM;
1795 goto err_free_qhp;
1796 }
1797
1801 qhp->wq.sq.size = sqsize; 1798 qhp->wq.sq.size = sqsize;
1802 qhp->wq.sq.memsize = 1799 qhp->wq.sq.memsize =
1803 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) * 1800 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
@@ -1814,9 +1811,10 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1814 } 1811 }
1815 1812
1816 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1813 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1817 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1814 ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
1815 qhp->wr_waitp);
1818 if (ret) 1816 if (ret)
1819 goto err1; 1817 goto err_free_wr_wait;
1820 1818
1821 attrs->cap.max_recv_wr = rqsize - 1; 1819 attrs->cap.max_recv_wr = rqsize - 1;
1822 attrs->cap.max_send_wr = sqsize - 1; 1820 attrs->cap.max_send_wr = sqsize - 1;
@@ -1847,35 +1845,35 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1847 1845
1848 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1846 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1849 if (ret) 1847 if (ret)
1850 goto err2; 1848 goto err_destroy_qp;
1851 1849
1852 if (udata) { 1850 if (udata && ucontext) {
1853 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL); 1851 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1854 if (!sq_key_mm) { 1852 if (!sq_key_mm) {
1855 ret = -ENOMEM; 1853 ret = -ENOMEM;
1856 goto err3; 1854 goto err_remove_handle;
1857 } 1855 }
1858 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL); 1856 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1859 if (!rq_key_mm) { 1857 if (!rq_key_mm) {
1860 ret = -ENOMEM; 1858 ret = -ENOMEM;
1861 goto err4; 1859 goto err_free_sq_key;
1862 } 1860 }
1863 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL); 1861 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1864 if (!sq_db_key_mm) { 1862 if (!sq_db_key_mm) {
1865 ret = -ENOMEM; 1863 ret = -ENOMEM;
1866 goto err5; 1864 goto err_free_rq_key;
1867 } 1865 }
1868 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL); 1866 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1869 if (!rq_db_key_mm) { 1867 if (!rq_db_key_mm) {
1870 ret = -ENOMEM; 1868 ret = -ENOMEM;
1871 goto err6; 1869 goto err_free_sq_db_key;
1872 } 1870 }
1873 if (t4_sq_onchip(&qhp->wq.sq)) { 1871 if (t4_sq_onchip(&qhp->wq.sq)) {
1874 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm), 1872 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
1875 GFP_KERNEL); 1873 GFP_KERNEL);
1876 if (!ma_sync_key_mm) { 1874 if (!ma_sync_key_mm) {
1877 ret = -ENOMEM; 1875 ret = -ENOMEM;
1878 goto err7; 1876 goto err_free_rq_db_key;
1879 } 1877 }
1880 uresp.flags = C4IW_QPF_ONCHIP; 1878 uresp.flags = C4IW_QPF_ONCHIP;
1881 } else 1879 } else
@@ -1905,7 +1903,7 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1905 spin_unlock(&ucontext->mmap_lock); 1903 spin_unlock(&ucontext->mmap_lock);
1906 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1904 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1907 if (ret) 1905 if (ret)
1908 goto err8; 1906 goto err_free_ma_sync_key;
1909 sq_key_mm->key = uresp.sq_key; 1907 sq_key_mm->key = uresp.sq_key;
1910 sq_key_mm->addr = qhp->wq.sq.phys_addr; 1908 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1911 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1909 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
@@ -1935,30 +1933,30 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1935 qhp->ucontext = ucontext; 1933 qhp->ucontext = ucontext;
1936 } 1934 }
1937 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1935 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1938 init_timer(&(qhp->timer));
1939 INIT_LIST_HEAD(&qhp->db_fc_entry); 1936 INIT_LIST_HEAD(&qhp->db_fc_entry);
1940 pr_debug("%s sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n", 1937 pr_debug("sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n",
1941 __func__,
1942 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize, 1938 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
1943 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size, 1939 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
1944 qhp->wq.rq.memsize, attrs->cap.max_recv_wr); 1940 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1945 return &qhp->ibqp; 1941 return &qhp->ibqp;
1946err8: 1942err_free_ma_sync_key:
1947 kfree(ma_sync_key_mm); 1943 kfree(ma_sync_key_mm);
1948err7: 1944err_free_rq_db_key:
1949 kfree(rq_db_key_mm); 1945 kfree(rq_db_key_mm);
1950err6: 1946err_free_sq_db_key:
1951 kfree(sq_db_key_mm); 1947 kfree(sq_db_key_mm);
1952err5: 1948err_free_rq_key:
1953 kfree(rq_key_mm); 1949 kfree(rq_key_mm);
1954err4: 1950err_free_sq_key:
1955 kfree(sq_key_mm); 1951 kfree(sq_key_mm);
1956err3: 1952err_remove_handle:
1957 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1953 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1958err2: 1954err_destroy_qp:
1959 destroy_qp(&rhp->rdev, &qhp->wq, 1955 destroy_qp(&rhp->rdev, &qhp->wq,
1960 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1956 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1961err1: 1957err_free_wr_wait:
1958 c4iw_put_wr_wait(qhp->wr_waitp);
1959err_free_qhp:
1962 kfree(qhp); 1960 kfree(qhp);
1963 return ERR_PTR(ret); 1961 return ERR_PTR(ret);
1964} 1962}
@@ -1971,7 +1969,7 @@ int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1971 enum c4iw_qp_attr_mask mask = 0; 1969 enum c4iw_qp_attr_mask mask = 0;
1972 struct c4iw_qp_attributes attrs; 1970 struct c4iw_qp_attributes attrs;
1973 1971
1974 pr_debug("%s ib_qp %p\n", __func__, ibqp); 1972 pr_debug("ib_qp %p\n", ibqp);
1975 1973
1976 /* iwarp does not support the RTR state */ 1974 /* iwarp does not support the RTR state */
1977 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1975 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
@@ -2017,7 +2015,7 @@ int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2017 2015
2018struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 2016struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
2019{ 2017{
2020 pr_debug("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn); 2018 pr_debug("ib_dev %p qpn 0x%x\n", dev, qpn);
2021 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 2019 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
2022} 2020}
2023 2021
diff --git a/drivers/infiniband/hw/cxgb4/resource.c b/drivers/infiniband/hw/cxgb4/resource.c
index 8ff0cbe5cb16..3cf25997ed2b 100644
--- a/drivers/infiniband/hw/cxgb4/resource.c
+++ b/drivers/infiniband/hw/cxgb4/resource.c
@@ -90,7 +90,7 @@ u32 c4iw_get_resource(struct c4iw_id_table *id_table)
90 90
91void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry) 91void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry)
92{ 92{
93 pr_debug("%s entry 0x%x\n", __func__, entry); 93 pr_debug("entry 0x%x\n", entry);
94 c4iw_id_free(id_table, entry); 94 c4iw_id_free(id_table, entry);
95} 95}
96 96
@@ -141,7 +141,7 @@ u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx)
141 } 141 }
142out: 142out:
143 mutex_unlock(&uctx->lock); 143 mutex_unlock(&uctx->lock);
144 pr_debug("%s qid 0x%x\n", __func__, qid); 144 pr_debug("qid 0x%x\n", qid);
145 mutex_lock(&rdev->stats.lock); 145 mutex_lock(&rdev->stats.lock);
146 if (rdev->stats.qid.cur > rdev->stats.qid.max) 146 if (rdev->stats.qid.cur > rdev->stats.qid.max)
147 rdev->stats.qid.max = rdev->stats.qid.cur; 147 rdev->stats.qid.max = rdev->stats.qid.cur;
@@ -157,7 +157,7 @@ void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
157 entry = kmalloc(sizeof *entry, GFP_KERNEL); 157 entry = kmalloc(sizeof *entry, GFP_KERNEL);
158 if (!entry) 158 if (!entry)
159 return; 159 return;
160 pr_debug("%s qid 0x%x\n", __func__, qid); 160 pr_debug("qid 0x%x\n", qid);
161 entry->qid = qid; 161 entry->qid = qid;
162 mutex_lock(&uctx->lock); 162 mutex_lock(&uctx->lock);
163 list_add_tail(&entry->entry, &uctx->cqids); 163 list_add_tail(&entry->entry, &uctx->cqids);
@@ -215,7 +215,7 @@ u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx)
215 } 215 }
216out: 216out:
217 mutex_unlock(&uctx->lock); 217 mutex_unlock(&uctx->lock);
218 pr_debug("%s qid 0x%x\n", __func__, qid); 218 pr_debug("qid 0x%x\n", qid);
219 mutex_lock(&rdev->stats.lock); 219 mutex_lock(&rdev->stats.lock);
220 if (rdev->stats.qid.cur > rdev->stats.qid.max) 220 if (rdev->stats.qid.cur > rdev->stats.qid.max)
221 rdev->stats.qid.max = rdev->stats.qid.cur; 221 rdev->stats.qid.max = rdev->stats.qid.cur;
@@ -231,7 +231,7 @@ void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
231 entry = kmalloc(sizeof *entry, GFP_KERNEL); 231 entry = kmalloc(sizeof *entry, GFP_KERNEL);
232 if (!entry) 232 if (!entry)
233 return; 233 return;
234 pr_debug("%s qid 0x%x\n", __func__, qid); 234 pr_debug("qid 0x%x\n", qid);
235 entry->qid = qid; 235 entry->qid = qid;
236 mutex_lock(&uctx->lock); 236 mutex_lock(&uctx->lock);
237 list_add_tail(&entry->entry, &uctx->qpids); 237 list_add_tail(&entry->entry, &uctx->qpids);
@@ -254,7 +254,7 @@ void c4iw_destroy_resource(struct c4iw_resource *rscp)
254u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size) 254u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size)
255{ 255{
256 unsigned long addr = gen_pool_alloc(rdev->pbl_pool, size); 256 unsigned long addr = gen_pool_alloc(rdev->pbl_pool, size);
257 pr_debug("%s addr 0x%x size %d\n", __func__, (u32)addr, size); 257 pr_debug("addr 0x%x size %d\n", (u32)addr, size);
258 mutex_lock(&rdev->stats.lock); 258 mutex_lock(&rdev->stats.lock);
259 if (addr) { 259 if (addr) {
260 rdev->stats.pbl.cur += roundup(size, 1 << MIN_PBL_SHIFT); 260 rdev->stats.pbl.cur += roundup(size, 1 << MIN_PBL_SHIFT);
@@ -268,7 +268,7 @@ u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size)
268 268
269void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size) 269void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size)
270{ 270{
271 pr_debug("%s addr 0x%x size %d\n", __func__, addr, size); 271 pr_debug("addr 0x%x size %d\n", addr, size);
272 mutex_lock(&rdev->stats.lock); 272 mutex_lock(&rdev->stats.lock);
273 rdev->stats.pbl.cur -= roundup(size, 1 << MIN_PBL_SHIFT); 273 rdev->stats.pbl.cur -= roundup(size, 1 << MIN_PBL_SHIFT);
274 mutex_unlock(&rdev->stats.lock); 274 mutex_unlock(&rdev->stats.lock);
@@ -290,8 +290,8 @@ int c4iw_pblpool_create(struct c4iw_rdev *rdev)
290 while (pbl_start < pbl_top) { 290 while (pbl_start < pbl_top) {
291 pbl_chunk = min(pbl_top - pbl_start + 1, pbl_chunk); 291 pbl_chunk = min(pbl_top - pbl_start + 1, pbl_chunk);
292 if (gen_pool_add(rdev->pbl_pool, pbl_start, pbl_chunk, -1)) { 292 if (gen_pool_add(rdev->pbl_pool, pbl_start, pbl_chunk, -1)) {
293 pr_debug("%s failed to add PBL chunk (%x/%x)\n", 293 pr_debug("failed to add PBL chunk (%x/%x)\n",
294 __func__, pbl_start, pbl_chunk); 294 pbl_start, pbl_chunk);
295 if (pbl_chunk <= 1024 << MIN_PBL_SHIFT) { 295 if (pbl_chunk <= 1024 << MIN_PBL_SHIFT) {
296 pr_warn("Failed to add all PBL chunks (%x/%x)\n", 296 pr_warn("Failed to add all PBL chunks (%x/%x)\n",
297 pbl_start, pbl_top - pbl_start); 297 pbl_start, pbl_top - pbl_start);
@@ -299,8 +299,8 @@ int c4iw_pblpool_create(struct c4iw_rdev *rdev)
299 } 299 }
300 pbl_chunk >>= 1; 300 pbl_chunk >>= 1;
301 } else { 301 } else {
302 pr_debug("%s added PBL chunk (%x/%x)\n", 302 pr_debug("added PBL chunk (%x/%x)\n",
303 __func__, pbl_start, pbl_chunk); 303 pbl_start, pbl_chunk);
304 pbl_start += pbl_chunk; 304 pbl_start += pbl_chunk;
305 } 305 }
306 } 306 }
@@ -322,7 +322,7 @@ void c4iw_pblpool_destroy(struct c4iw_rdev *rdev)
322u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size) 322u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size)
323{ 323{
324 unsigned long addr = gen_pool_alloc(rdev->rqt_pool, size << 6); 324 unsigned long addr = gen_pool_alloc(rdev->rqt_pool, size << 6);
325 pr_debug("%s addr 0x%x size %d\n", __func__, (u32)addr, size << 6); 325 pr_debug("addr 0x%x size %d\n", (u32)addr, size << 6);
326 if (!addr) 326 if (!addr)
327 pr_warn_ratelimited("%s: Out of RQT memory\n", 327 pr_warn_ratelimited("%s: Out of RQT memory\n",
328 pci_name(rdev->lldi.pdev)); 328 pci_name(rdev->lldi.pdev));
@@ -339,7 +339,7 @@ u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size)
339 339
340void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size) 340void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size)
341{ 341{
342 pr_debug("%s addr 0x%x size %d\n", __func__, addr, size << 6); 342 pr_debug("addr 0x%x size %d\n", addr, size << 6);
343 mutex_lock(&rdev->stats.lock); 343 mutex_lock(&rdev->stats.lock);
344 rdev->stats.rqt.cur -= roundup(size << 6, 1 << MIN_RQT_SHIFT); 344 rdev->stats.rqt.cur -= roundup(size << 6, 1 << MIN_RQT_SHIFT);
345 mutex_unlock(&rdev->stats.lock); 345 mutex_unlock(&rdev->stats.lock);
@@ -361,8 +361,8 @@ int c4iw_rqtpool_create(struct c4iw_rdev *rdev)
361 while (rqt_start < rqt_top) { 361 while (rqt_start < rqt_top) {
362 rqt_chunk = min(rqt_top - rqt_start + 1, rqt_chunk); 362 rqt_chunk = min(rqt_top - rqt_start + 1, rqt_chunk);
363 if (gen_pool_add(rdev->rqt_pool, rqt_start, rqt_chunk, -1)) { 363 if (gen_pool_add(rdev->rqt_pool, rqt_start, rqt_chunk, -1)) {
364 pr_debug("%s failed to add RQT chunk (%x/%x)\n", 364 pr_debug("failed to add RQT chunk (%x/%x)\n",
365 __func__, rqt_start, rqt_chunk); 365 rqt_start, rqt_chunk);
366 if (rqt_chunk <= 1024 << MIN_RQT_SHIFT) { 366 if (rqt_chunk <= 1024 << MIN_RQT_SHIFT) {
367 pr_warn("Failed to add all RQT chunks (%x/%x)\n", 367 pr_warn("Failed to add all RQT chunks (%x/%x)\n",
368 rqt_start, rqt_top - rqt_start); 368 rqt_start, rqt_top - rqt_start);
@@ -370,8 +370,8 @@ int c4iw_rqtpool_create(struct c4iw_rdev *rdev)
370 } 370 }
371 rqt_chunk >>= 1; 371 rqt_chunk >>= 1;
372 } else { 372 } else {
373 pr_debug("%s added RQT chunk (%x/%x)\n", 373 pr_debug("added RQT chunk (%x/%x)\n",
374 __func__, rqt_start, rqt_chunk); 374 rqt_start, rqt_chunk);
375 rqt_start += rqt_chunk; 375 rqt_start += rqt_chunk;
376 } 376 }
377 } 377 }
@@ -391,7 +391,7 @@ void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev)
391u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size) 391u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size)
392{ 392{
393 unsigned long addr = gen_pool_alloc(rdev->ocqp_pool, size); 393 unsigned long addr = gen_pool_alloc(rdev->ocqp_pool, size);
394 pr_debug("%s addr 0x%x size %d\n", __func__, (u32)addr, size); 394 pr_debug("addr 0x%x size %d\n", (u32)addr, size);
395 if (addr) { 395 if (addr) {
396 mutex_lock(&rdev->stats.lock); 396 mutex_lock(&rdev->stats.lock);
397 rdev->stats.ocqp.cur += roundup(size, 1 << MIN_OCQP_SHIFT); 397 rdev->stats.ocqp.cur += roundup(size, 1 << MIN_OCQP_SHIFT);
@@ -404,7 +404,7 @@ u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size)
404 404
405void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size) 405void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size)
406{ 406{
407 pr_debug("%s addr 0x%x size %d\n", __func__, addr, size); 407 pr_debug("addr 0x%x size %d\n", addr, size);
408 mutex_lock(&rdev->stats.lock); 408 mutex_lock(&rdev->stats.lock);
409 rdev->stats.ocqp.cur -= roundup(size, 1 << MIN_OCQP_SHIFT); 409 rdev->stats.ocqp.cur -= roundup(size, 1 << MIN_OCQP_SHIFT);
410 mutex_unlock(&rdev->stats.lock); 410 mutex_unlock(&rdev->stats.lock);
@@ -426,8 +426,8 @@ int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev)
426 while (start < top) { 426 while (start < top) {
427 chunk = min(top - start + 1, chunk); 427 chunk = min(top - start + 1, chunk);
428 if (gen_pool_add(rdev->ocqp_pool, start, chunk, -1)) { 428 if (gen_pool_add(rdev->ocqp_pool, start, chunk, -1)) {
429 pr_debug("%s failed to add OCQP chunk (%x/%x)\n", 429 pr_debug("failed to add OCQP chunk (%x/%x)\n",
430 __func__, start, chunk); 430 start, chunk);
431 if (chunk <= 1024 << MIN_OCQP_SHIFT) { 431 if (chunk <= 1024 << MIN_OCQP_SHIFT) {
432 pr_warn("Failed to add all OCQP chunks (%x/%x)\n", 432 pr_warn("Failed to add all OCQP chunks (%x/%x)\n",
433 start, top - start); 433 start, top - start);
@@ -435,8 +435,8 @@ int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev)
435 } 435 }
436 chunk >>= 1; 436 chunk >>= 1;
437 } else { 437 } else {
438 pr_debug("%s added OCQP chunk (%x/%x)\n", 438 pr_debug("added OCQP chunk (%x/%x)\n",
439 __func__, start, chunk); 439 start, chunk);
440 start += chunk; 440 start += chunk;
441 } 441 }
442 } 442 }
diff --git a/drivers/infiniband/hw/cxgb4/t4.h b/drivers/infiniband/hw/cxgb4/t4.h
index e765c00303cd..e9ea94268d51 100644
--- a/drivers/infiniband/hw/cxgb4/t4.h
+++ b/drivers/infiniband/hw/cxgb4/t4.h
@@ -171,7 +171,7 @@ struct t4_cqe {
171 __be32 msn; 171 __be32 msn;
172 } rcqe; 172 } rcqe;
173 struct { 173 struct {
174 u32 stag; 174 __be32 stag;
175 u16 nada2; 175 u16 nada2;
176 u16 cidx; 176 u16 cidx;
177 } scqe; 177 } scqe;
@@ -425,7 +425,6 @@ static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
425 425
426static inline void t4_sq_consume(struct t4_wq *wq) 426static inline void t4_sq_consume(struct t4_wq *wq)
427{ 427{
428 BUG_ON(wq->sq.in_use < 1);
429 if (wq->sq.cidx == wq->sq.flush_cidx) 428 if (wq->sq.cidx == wq->sq.flush_cidx)
430 wq->sq.flush_cidx = -1; 429 wq->sq.flush_cidx = -1;
431 wq->sq.in_use--; 430 wq->sq.in_use--;
@@ -466,14 +465,12 @@ static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe)
466 wmb(); 465 wmb();
467 if (wq->sq.bar2_va) { 466 if (wq->sq.bar2_va) {
468 if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) { 467 if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) {
469 pr_debug("%s: WC wq->sq.pidx = %d\n", 468 pr_debug("WC wq->sq.pidx = %d\n", wq->sq.pidx);
470 __func__, wq->sq.pidx);
471 pio_copy((u64 __iomem *) 469 pio_copy((u64 __iomem *)
472 (wq->sq.bar2_va + SGE_UDB_WCDOORBELL), 470 (wq->sq.bar2_va + SGE_UDB_WCDOORBELL),
473 (u64 *)wqe); 471 (u64 *)wqe);
474 } else { 472 } else {
475 pr_debug("%s: DB wq->sq.pidx = %d\n", 473 pr_debug("DB wq->sq.pidx = %d\n", wq->sq.pidx);
476 __func__, wq->sq.pidx);
477 writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid), 474 writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid),
478 wq->sq.bar2_va + SGE_UDB_KDOORBELL); 475 wq->sq.bar2_va + SGE_UDB_KDOORBELL);
479 } 476 }
@@ -493,14 +490,12 @@ static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc,
493 wmb(); 490 wmb();
494 if (wq->rq.bar2_va) { 491 if (wq->rq.bar2_va) {
495 if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) { 492 if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) {
496 pr_debug("%s: WC wq->rq.pidx = %d\n", 493 pr_debug("WC wq->rq.pidx = %d\n", wq->rq.pidx);
497 __func__, wq->rq.pidx);
498 pio_copy((u64 __iomem *) 494 pio_copy((u64 __iomem *)
499 (wq->rq.bar2_va + SGE_UDB_WCDOORBELL), 495 (wq->rq.bar2_va + SGE_UDB_WCDOORBELL),
500 (void *)wqe); 496 (void *)wqe);
501 } else { 497 } else {
502 pr_debug("%s: DB wq->rq.pidx = %d\n", 498 pr_debug("DB wq->rq.pidx = %d\n", wq->rq.pidx);
503 __func__, wq->rq.pidx);
504 writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid), 499 writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid),
505 wq->rq.bar2_va + SGE_UDB_KDOORBELL); 500 wq->rq.bar2_va + SGE_UDB_KDOORBELL);
506 } 501 }
@@ -601,10 +596,11 @@ static inline void t4_swcq_produce(struct t4_cq *cq)
601{ 596{
602 cq->sw_in_use++; 597 cq->sw_in_use++;
603 if (cq->sw_in_use == cq->size) { 598 if (cq->sw_in_use == cq->size) {
604 pr_debug("%s cxgb4 sw cq overflow cqid %u\n", 599 pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
605 __func__, cq->cqid); 600 __func__, cq->cqid);
606 cq->error = 1; 601 cq->error = 1;
607 BUG_ON(1); 602 cq->sw_in_use--;
603 return;
608 } 604 }
609 if (++cq->sw_pidx == cq->size) 605 if (++cq->sw_pidx == cq->size)
610 cq->sw_pidx = 0; 606 cq->sw_pidx = 0;
@@ -612,7 +608,6 @@ static inline void t4_swcq_produce(struct t4_cq *cq)
612 608
613static inline void t4_swcq_consume(struct t4_cq *cq) 609static inline void t4_swcq_consume(struct t4_cq *cq)
614{ 610{
615 BUG_ON(cq->sw_in_use < 1);
616 cq->sw_in_use--; 611 cq->sw_in_use--;
617 if (++cq->sw_cidx == cq->size) 612 if (++cq->sw_cidx == cq->size)
618 cq->sw_cidx = 0; 613 cq->sw_cidx = 0;
@@ -658,7 +653,6 @@ static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
658 ret = -EOVERFLOW; 653 ret = -EOVERFLOW;
659 cq->error = 1; 654 cq->error = 1;
660 pr_err("cq overflow cqid %u\n", cq->cqid); 655 pr_err("cq overflow cqid %u\n", cq->cqid);
661 BUG_ON(1);
662 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 656 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
663 657
664 /* Ensure CQE is flushed to memory */ 658 /* Ensure CQE is flushed to memory */
@@ -673,10 +667,9 @@ static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
673static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) 667static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
674{ 668{
675 if (cq->sw_in_use == cq->size) { 669 if (cq->sw_in_use == cq->size) {
676 pr_debug("%s cxgb4 sw cq overflow cqid %u\n", 670 pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
677 __func__, cq->cqid); 671 __func__, cq->cqid);
678 cq->error = 1; 672 cq->error = 1;
679 BUG_ON(1);
680 return NULL; 673 return NULL;
681 } 674 }
682 if (cq->sw_in_use) 675 if (cq->sw_in_use)
diff --git a/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h b/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h
index 010c709ba3bb..58c531db4f4a 100644
--- a/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h
+++ b/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h
@@ -675,8 +675,8 @@ struct fw_ri_fr_nsmr_tpte_wr {
675 __u16 wrid; 675 __u16 wrid;
676 __u8 r1[3]; 676 __u8 r1[3];
677 __u8 len16; 677 __u8 len16;
678 __u32 r2; 678 __be32 r2;
679 __u32 stag; 679 __be32 stag;
680 struct fw_ri_tpte tpte; 680 struct fw_ri_tpte tpte;
681 __u64 pbl[2]; 681 __u64 pbl[2];
682}; 682};
diff --git a/drivers/infiniband/hw/hfi1/aspm.h b/drivers/infiniband/hw/hfi1/aspm.h
index 522b40ed9937..e8133870ee87 100644
--- a/drivers/infiniband/hw/hfi1/aspm.h
+++ b/drivers/infiniband/hw/hfi1/aspm.h
@@ -218,9 +218,9 @@ unlock:
218} 218}
219 219
220/* Timer function for re-enabling ASPM in the absence of interrupt activity */ 220/* Timer function for re-enabling ASPM in the absence of interrupt activity */
221static inline void aspm_ctx_timer_function(unsigned long data) 221static inline void aspm_ctx_timer_function(struct timer_list *t)
222{ 222{
223 struct hfi1_ctxtdata *rcd = (struct hfi1_ctxtdata *)data; 223 struct hfi1_ctxtdata *rcd = from_timer(rcd, t, aspm_timer);
224 unsigned long flags; 224 unsigned long flags;
225 225
226 spin_lock_irqsave(&rcd->aspm_lock, flags); 226 spin_lock_irqsave(&rcd->aspm_lock, flags);
@@ -281,8 +281,7 @@ static inline void aspm_enable_all(struct hfi1_devdata *dd)
281static inline void aspm_ctx_init(struct hfi1_ctxtdata *rcd) 281static inline void aspm_ctx_init(struct hfi1_ctxtdata *rcd)
282{ 282{
283 spin_lock_init(&rcd->aspm_lock); 283 spin_lock_init(&rcd->aspm_lock);
284 setup_timer(&rcd->aspm_timer, aspm_ctx_timer_function, 284 timer_setup(&rcd->aspm_timer, aspm_ctx_timer_function, 0);
285 (unsigned long)rcd);
286 rcd->aspm_intr_supported = rcd->dd->aspm_supported && 285 rcd->aspm_intr_supported = rcd->dd->aspm_supported &&
287 aspm_mode == ASPM_MODE_DYNAMIC && 286 aspm_mode == ASPM_MODE_DYNAMIC &&
288 rcd->ctxt < rcd->dd->first_dyn_alloc_ctxt; 287 rcd->ctxt < rcd->dd->first_dyn_alloc_ctxt;
diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c
index 0be42787759f..4f057e8ffe50 100644
--- a/drivers/infiniband/hw/hfi1/chip.c
+++ b/drivers/infiniband/hw/hfi1/chip.c
@@ -1036,7 +1036,6 @@ static void read_vc_local_link_width(struct hfi1_devdata *dd, u8 *misc_bits,
1036 u8 *flag_bits, u16 *link_widths); 1036 u8 *flag_bits, u16 *link_widths);
1037static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id, 1037static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1038 u8 *device_rev); 1038 u8 *device_rev);
1039static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed);
1040static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx); 1039static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1041static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx, 1040static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1042 u8 *tx_polarity_inversion, 1041 u8 *tx_polarity_inversion,
@@ -5538,9 +5537,9 @@ static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5538 * associated with them. 5537 * associated with them.
5539 */ 5538 */
5540#define RCVERR_CHECK_TIME 10 5539#define RCVERR_CHECK_TIME 10
5541static void update_rcverr_timer(unsigned long opaque) 5540static void update_rcverr_timer(struct timer_list *t)
5542{ 5541{
5543 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque; 5542 struct hfi1_devdata *dd = from_timer(dd, t, rcverr_timer);
5544 struct hfi1_pportdata *ppd = dd->pport; 5543 struct hfi1_pportdata *ppd = dd->pport;
5545 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL); 5544 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5546 5545
@@ -5559,7 +5558,7 @@ static void update_rcverr_timer(unsigned long opaque)
5559 5558
5560static int init_rcverr(struct hfi1_devdata *dd) 5559static int init_rcverr(struct hfi1_devdata *dd)
5561{ 5560{
5562 setup_timer(&dd->rcverr_timer, update_rcverr_timer, (unsigned long)dd); 5561 timer_setup(&dd->rcverr_timer, update_rcverr_timer, 0);
5563 /* Assume the hardware counter has been reset */ 5562 /* Assume the hardware counter has been reset */
5564 dd->rcv_ovfl_cnt = 0; 5563 dd->rcv_ovfl_cnt = 0;
5565 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME); 5564 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
@@ -5567,9 +5566,8 @@ static int init_rcverr(struct hfi1_devdata *dd)
5567 5566
5568static void free_rcverr(struct hfi1_devdata *dd) 5567static void free_rcverr(struct hfi1_devdata *dd)
5569{ 5568{
5570 if (dd->rcverr_timer.data) 5569 if (dd->rcverr_timer.function)
5571 del_timer_sync(&dd->rcverr_timer); 5570 del_timer_sync(&dd->rcverr_timer);
5572 dd->rcverr_timer.data = 0;
5573} 5571}
5574 5572
5575static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) 5573static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
@@ -6520,12 +6518,11 @@ static void _dc_start(struct hfi1_devdata *dd)
6520 if (!dd->dc_shutdown) 6518 if (!dd->dc_shutdown)
6521 return; 6519 return;
6522 6520
6523 /* Take the 8051 out of reset */ 6521 /*
6524 write_csr(dd, DC_DC8051_CFG_RST, 0ull); 6522 * Take the 8051 out of reset, wait until 8051 is ready, and set host
6525 /* Wait until 8051 is ready */ 6523 * version bit.
6526 if (wait_fm_ready(dd, TIMEOUT_8051_START)) 6524 */
6527 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n", 6525 release_and_wait_ready_8051_firmware(dd);
6528 __func__);
6529 6526
6530 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */ 6527 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6531 write_csr(dd, DCC_CFG_RESET, 0x10); 6528 write_csr(dd, DCC_CFG_RESET, 0x10);
@@ -6819,7 +6816,8 @@ static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6819 rcd = hfi1_rcd_get_by_index(dd, i); 6816 rcd = hfi1_rcd_get_by_index(dd, i);
6820 6817
6821 /* Ensure all non-user contexts(including vnic) are enabled */ 6818 /* Ensure all non-user contexts(including vnic) are enabled */
6822 if (!rcd || !rcd->sc || (rcd->sc->type == SC_USER)) { 6819 if (!rcd ||
6820 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) {
6823 hfi1_rcd_put(rcd); 6821 hfi1_rcd_put(rcd);
6824 continue; 6822 continue;
6825 } 6823 }
@@ -7199,27 +7197,6 @@ static int lcb_to_port_ltp(int lcb_crc)
7199 return port_ltp; 7197 return port_ltp;
7200} 7198}
7201 7199
7202/*
7203 * Our neighbor has indicated that we are allowed to act as a fabric
7204 * manager, so place the full management partition key in the second
7205 * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
7206 * that we should already have the limited management partition key in
7207 * array element 1, and also that the port is not yet up when
7208 * add_full_mgmt_pkey() is invoked.
7209 */
7210static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7211{
7212 struct hfi1_devdata *dd = ppd->dd;
7213
7214 /* Sanity check - ppd->pkeys[2] should be 0, or already initialized */
7215 if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
7216 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
7217 __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
7218 ppd->pkeys[2] = FULL_MGMT_P_KEY;
7219 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
7220 hfi1_event_pkey_change(ppd->dd, ppd->port);
7221}
7222
7223static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd) 7200static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7224{ 7201{
7225 if (ppd->pkeys[2] != 0) { 7202 if (ppd->pkeys[2] != 0) {
@@ -7416,11 +7393,7 @@ void handle_verify_cap(struct work_struct *work)
7416 &partner_supported_crc); 7393 &partner_supported_crc);
7417 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths); 7394 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7418 read_remote_device_id(dd, &device_id, &device_rev); 7395 read_remote_device_id(dd, &device_id, &device_rev);
7419 /* 7396
7420 * And the 'MgmtAllowed' information, which is exchanged during
7421 * LNI, is also be available at this point.
7422 */
7423 read_mgmt_allowed(dd, &ppd->mgmt_allowed);
7424 /* print the active widths */ 7397 /* print the active widths */
7425 get_link_widths(dd, &active_tx, &active_rx); 7398 get_link_widths(dd, &active_tx, &active_rx);
7426 dd_dev_info(dd, 7399 dd_dev_info(dd,
@@ -7548,9 +7521,6 @@ void handle_verify_cap(struct work_struct *work)
7548 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ 7521 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7549 set_8051_lcb_access(dd); 7522 set_8051_lcb_access(dd);
7550 7523
7551 if (ppd->mgmt_allowed)
7552 add_full_mgmt_pkey(ppd);
7553
7554 /* tell the 8051 to go to LinkUp */ 7524 /* tell the 8051 to go to LinkUp */
7555 set_link_state(ppd, HLS_GOING_UP); 7525 set_link_state(ppd, HLS_GOING_UP);
7556} 7526}
@@ -8124,8 +8094,7 @@ static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
8124 rcd = hfi1_rcd_get_by_index(dd, source); 8094 rcd = hfi1_rcd_get_by_index(dd, source);
8125 if (rcd) { 8095 if (rcd) {
8126 /* Check for non-user contexts, including vnic */ 8096 /* Check for non-user contexts, including vnic */
8127 if ((source < dd->first_dyn_alloc_ctxt) || 8097 if (source < dd->first_dyn_alloc_ctxt || rcd->is_vnic)
8128 (rcd->sc && (rcd->sc->type == SC_KERNEL)))
8129 rcd->do_interrupt(rcd, 0); 8098 rcd->do_interrupt(rcd, 0);
8130 else 8099 else
8131 handle_user_interrupt(rcd); 8100 handle_user_interrupt(rcd);
@@ -8155,8 +8124,8 @@ static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
8155 rcd = hfi1_rcd_get_by_index(dd, source); 8124 rcd = hfi1_rcd_get_by_index(dd, source);
8156 if (rcd) { 8125 if (rcd) {
8157 /* only pay attention to user urgent interrupts */ 8126 /* only pay attention to user urgent interrupts */
8158 if ((source >= dd->first_dyn_alloc_ctxt) && 8127 if (source >= dd->first_dyn_alloc_ctxt &&
8159 (!rcd->sc || (rcd->sc->type == SC_USER))) 8128 !rcd->is_vnic)
8160 handle_user_interrupt(rcd); 8129 handle_user_interrupt(rcd);
8161 8130
8162 hfi1_rcd_put(rcd); 8131 hfi1_rcd_put(rcd);
@@ -8595,30 +8564,23 @@ int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8595} 8564}
8596 8565
8597/* 8566/*
8567 * If the 8051 is in reset mode (dd->dc_shutdown == 1), this function
8568 * will still continue executing.
8569 *
8598 * Returns: 8570 * Returns:
8599 * < 0 = Linux error, not able to get access 8571 * < 0 = Linux error, not able to get access
8600 * > 0 = 8051 command RETURN_CODE 8572 * > 0 = 8051 command RETURN_CODE
8601 */ 8573 */
8602static int do_8051_command( 8574static int _do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
8603 struct hfi1_devdata *dd, 8575 u64 *out_data)
8604 u32 type,
8605 u64 in_data,
8606 u64 *out_data)
8607{ 8576{
8608 u64 reg, completed; 8577 u64 reg, completed;
8609 int return_code; 8578 int return_code;
8610 unsigned long timeout; 8579 unsigned long timeout;
8611 8580
8581 lockdep_assert_held(&dd->dc8051_lock);
8612 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data); 8582 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8613 8583
8614 mutex_lock(&dd->dc8051_lock);
8615
8616 /* We can't send any commands to the 8051 if it's in reset */
8617 if (dd->dc_shutdown) {
8618 return_code = -ENODEV;
8619 goto fail;
8620 }
8621
8622 /* 8584 /*
8623 * If an 8051 host command timed out previously, then the 8051 is 8585 * If an 8051 host command timed out previously, then the 8051 is
8624 * stuck. 8586 * stuck.
@@ -8719,6 +8681,29 @@ static int do_8051_command(
8719 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); 8681 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8720 8682
8721fail: 8683fail:
8684 return return_code;
8685}
8686
8687/*
8688 * Returns:
8689 * < 0 = Linux error, not able to get access
8690 * > 0 = 8051 command RETURN_CODE
8691 */
8692static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
8693 u64 *out_data)
8694{
8695 int return_code;
8696
8697 mutex_lock(&dd->dc8051_lock);
8698 /* We can't send any commands to the 8051 if it's in reset */
8699 if (dd->dc_shutdown) {
8700 return_code = -ENODEV;
8701 goto fail;
8702 }
8703
8704 return_code = _do_8051_command(dd, type, in_data, out_data);
8705
8706fail:
8722 mutex_unlock(&dd->dc8051_lock); 8707 mutex_unlock(&dd->dc8051_lock);
8723 return return_code; 8708 return return_code;
8724} 8709}
@@ -8728,16 +8713,17 @@ static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8728 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL); 8713 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8729} 8714}
8730 8715
8731int load_8051_config(struct hfi1_devdata *dd, u8 field_id, 8716static int _load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8732 u8 lane_id, u32 config_data) 8717 u8 lane_id, u32 config_data)
8733{ 8718{
8734 u64 data; 8719 u64 data;
8735 int ret; 8720 int ret;
8736 8721
8722 lockdep_assert_held(&dd->dc8051_lock);
8737 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT 8723 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8738 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT 8724 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8739 | (u64)config_data << LOAD_DATA_DATA_SHIFT; 8725 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8740 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL); 8726 ret = _do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8741 if (ret != HCMD_SUCCESS) { 8727 if (ret != HCMD_SUCCESS) {
8742 dd_dev_err(dd, 8728 dd_dev_err(dd,
8743 "load 8051 config: field id %d, lane %d, err %d\n", 8729 "load 8051 config: field id %d, lane %d, err %d\n",
@@ -8746,6 +8732,18 @@ int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8746 return ret; 8732 return ret;
8747} 8733}
8748 8734
8735int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8736 u8 lane_id, u32 config_data)
8737{
8738 int return_code;
8739
8740 mutex_lock(&dd->dc8051_lock);
8741 return_code = _load_8051_config(dd, field_id, lane_id, config_data);
8742 mutex_unlock(&dd->dc8051_lock);
8743
8744 return return_code;
8745}
8746
8749/* 8747/*
8750 * Read the 8051 firmware "registers". Use the RAM directly. Always 8748 * Read the 8051 firmware "registers". Use the RAM directly. Always
8751 * set the result, even on error. 8749 * set the result, even on error.
@@ -8861,13 +8859,14 @@ int write_host_interface_version(struct hfi1_devdata *dd, u8 version)
8861 u32 frame; 8859 u32 frame;
8862 u32 mask; 8860 u32 mask;
8863 8861
8862 lockdep_assert_held(&dd->dc8051_lock);
8864 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT); 8863 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT);
8865 read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame); 8864 read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame);
8866 /* Clear, then set field */ 8865 /* Clear, then set field */
8867 frame &= ~mask; 8866 frame &= ~mask;
8868 frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT); 8867 frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT);
8869 return load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, 8868 return _load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG,
8870 frame); 8869 frame);
8871} 8870}
8872 8871
8873void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor, 8872void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
@@ -8932,14 +8931,6 @@ static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
8932 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK; 8931 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
8933} 8932}
8934 8933
8935static void read_mgmt_allowed(struct hfi1_devdata *dd, u8 *mgmt_allowed)
8936{
8937 u32 frame;
8938
8939 read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
8940 *mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT) & MGMT_ALLOWED_MASK;
8941}
8942
8943static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls) 8934static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
8944{ 8935{
8945 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls); 8936 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
@@ -9161,25 +9152,6 @@ static int do_quick_linkup(struct hfi1_devdata *dd)
9161} 9152}
9162 9153
9163/* 9154/*
9164 * Set the SerDes to internal loopback mode.
9165 * Returns 0 on success, -errno on error.
9166 */
9167static int set_serdes_loopback_mode(struct hfi1_devdata *dd)
9168{
9169 int ret;
9170
9171 ret = set_physical_link_state(dd, PLS_INTERNAL_SERDES_LOOPBACK);
9172 if (ret == HCMD_SUCCESS)
9173 return 0;
9174 dd_dev_err(dd,
9175 "Set physical link state to SerDes Loopback failed with return %d\n",
9176 ret);
9177 if (ret >= 0)
9178 ret = -EINVAL;
9179 return ret;
9180}
9181
9182/*
9183 * Do all special steps to set up loopback. 9155 * Do all special steps to set up loopback.
9184 */ 9156 */
9185static int init_loopback(struct hfi1_devdata *dd) 9157static int init_loopback(struct hfi1_devdata *dd)
@@ -9204,13 +9176,11 @@ static int init_loopback(struct hfi1_devdata *dd)
9204 return 0; 9176 return 0;
9205 } 9177 }
9206 9178
9207 /* handle serdes loopback */ 9179 /*
9208 if (loopback == LOOPBACK_SERDES) { 9180 * SerDes loopback init sequence is handled in set_local_link_attributes
9209 /* internal serdes loopack needs quick linkup on RTL */ 9181 */
9210 if (dd->icode == ICODE_RTL_SILICON) 9182 if (loopback == LOOPBACK_SERDES)
9211 quick_linkup = 1; 9183 return 0;
9212 return set_serdes_loopback_mode(dd);
9213 }
9214 9184
9215 /* LCB loopback - handled at poll time */ 9185 /* LCB loopback - handled at poll time */
9216 if (loopback == LOOPBACK_LCB) { 9186 if (loopback == LOOPBACK_LCB) {
@@ -9269,7 +9239,7 @@ static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9269 u8 tx_polarity_inversion; 9239 u8 tx_polarity_inversion;
9270 u8 rx_polarity_inversion; 9240 u8 rx_polarity_inversion;
9271 int ret; 9241 int ret;
9272 9242 u32 misc_bits = 0;
9273 /* reset our fabric serdes to clear any lingering problems */ 9243 /* reset our fabric serdes to clear any lingering problems */
9274 fabric_serdes_reset(dd); 9244 fabric_serdes_reset(dd);
9275 9245
@@ -9315,7 +9285,14 @@ static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9315 if (ret != HCMD_SUCCESS) 9285 if (ret != HCMD_SUCCESS)
9316 goto set_local_link_attributes_fail; 9286 goto set_local_link_attributes_fail;
9317 9287
9318 ret = write_vc_local_link_width(dd, 0, 0, 9288 /*
9289 * SerDes loopback init sequence requires
9290 * setting bit 0 of MISC_CONFIG_BITS
9291 */
9292 if (loopback == LOOPBACK_SERDES)
9293 misc_bits |= 1 << LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT;
9294
9295 ret = write_vc_local_link_width(dd, misc_bits, 0,
9319 opa_to_vc_link_widths( 9296 opa_to_vc_link_widths(
9320 ppd->link_width_enabled)); 9297 ppd->link_width_enabled));
9321 if (ret != HCMD_SUCCESS) 9298 if (ret != HCMD_SUCCESS)
@@ -9809,9 +9786,9 @@ void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9809 cancel_delayed_work_sync(&ppd->start_link_work); 9786 cancel_delayed_work_sync(&ppd->start_link_work);
9810 9787
9811 ppd->offline_disabled_reason = 9788 ppd->offline_disabled_reason =
9812 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED); 9789 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_REBOOT);
9813 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SMA_DISABLED, 0, 9790 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_REBOOT, 0,
9814 OPA_LINKDOWN_REASON_SMA_DISABLED); 9791 OPA_LINKDOWN_REASON_REBOOT);
9815 set_link_state(ppd, HLS_DN_OFFLINE); 9792 set_link_state(ppd, HLS_DN_OFFLINE);
9816 9793
9817 /* disable the port */ 9794 /* disable the port */
@@ -9952,7 +9929,7 @@ int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9952 goto unimplemented; 9929 goto unimplemented;
9953 9930
9954 case HFI1_IB_CFG_OP_VLS: 9931 case HFI1_IB_CFG_OP_VLS:
9955 val = ppd->vls_operational; 9932 val = ppd->actual_vls_operational;
9956 break; 9933 break;
9957 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */ 9934 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
9958 val = VL_ARB_HIGH_PRIO_TABLE_SIZE; 9935 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
@@ -9967,7 +9944,7 @@ int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
9967 val = ppd->phy_error_threshold; 9944 val = ppd->phy_error_threshold;
9968 break; 9945 break;
9969 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 9946 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
9970 val = dd->link_default; 9947 val = HLS_DEFAULT;
9971 break; 9948 break;
9972 9949
9973 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */ 9950 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
@@ -10170,6 +10147,10 @@ static const char * const state_complete_reasons[] = {
10170 [0x33] = 10147 [0x33] =
10171 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy", 10148 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10172 [0x34] = tx_out_of_policy, 10149 [0x34] = tx_out_of_policy,
10150 [0x35] = "Negotiated link width is mutually exclusive",
10151 [0x36] =
10152 "Timed out before receiving verifycap frames in VerifyCap.Exchange",
10153 [0x37] = "Unable to resolve secure data exchange",
10173}; 10154};
10174 10155
10175static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd, 10156static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd,
@@ -10298,9 +10279,6 @@ static void force_logical_link_state_down(struct hfi1_pportdata *ppd)
10298 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); 10279 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
10299 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); 10280 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
10300 10281
10301 /* adjust ppd->statusp, if needed */
10302 update_statusp(ppd, IB_PORT_DOWN);
10303
10304 dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n"); 10282 dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n");
10305} 10283}
10306 10284
@@ -10382,6 +10360,7 @@ static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
10382 force_logical_link_state_down(ppd); 10360 force_logical_link_state_down(ppd);
10383 10361
10384 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */ 10362 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
10363 update_statusp(ppd, IB_PORT_DOWN);
10385 10364
10386 /* 10365 /*
10387 * The LNI has a mandatory wait time after the physical state 10366 * The LNI has a mandatory wait time after the physical state
@@ -10569,7 +10548,7 @@ int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10569 10548
10570 orig_new_state = state; 10549 orig_new_state = state;
10571 if (state == HLS_DN_DOWNDEF) 10550 if (state == HLS_DN_DOWNDEF)
10572 state = dd->link_default; 10551 state = HLS_DEFAULT;
10573 10552
10574 /* interpret poll -> poll as a link bounce */ 10553 /* interpret poll -> poll as a link bounce */
10575 poll_bounce = ppd->host_link_state == HLS_DN_POLL && 10554 poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
@@ -10643,6 +10622,7 @@ int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10643 10622
10644 handle_linkup_change(dd, 1); 10623 handle_linkup_change(dd, 1);
10645 ppd->host_link_state = HLS_UP_INIT; 10624 ppd->host_link_state = HLS_UP_INIT;
10625 update_statusp(ppd, IB_PORT_INIT);
10646 break; 10626 break;
10647 case HLS_UP_ARMED: 10627 case HLS_UP_ARMED:
10648 if (ppd->host_link_state != HLS_UP_INIT) 10628 if (ppd->host_link_state != HLS_UP_INIT)
@@ -10664,6 +10644,7 @@ int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10664 break; 10644 break;
10665 } 10645 }
10666 ppd->host_link_state = HLS_UP_ARMED; 10646 ppd->host_link_state = HLS_UP_ARMED;
10647 update_statusp(ppd, IB_PORT_ARMED);
10667 /* 10648 /*
10668 * The simulator does not currently implement SMA messages, 10649 * The simulator does not currently implement SMA messages,
10669 * so neighbor_normal is not set. Set it here when we first 10650 * so neighbor_normal is not set. Set it here when we first
@@ -10686,6 +10667,7 @@ int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10686 /* tell all engines to go running */ 10667 /* tell all engines to go running */
10687 sdma_all_running(dd); 10668 sdma_all_running(dd);
10688 ppd->host_link_state = HLS_UP_ACTIVE; 10669 ppd->host_link_state = HLS_UP_ACTIVE;
10670 update_statusp(ppd, IB_PORT_ACTIVE);
10689 10671
10690 /* Signal the IB layer that the port has went active */ 10672 /* Signal the IB layer that the port has went active */
10691 event.device = &dd->verbs_dev.rdi.ibdev; 10673 event.device = &dd->verbs_dev.rdi.ibdev;
@@ -12089,9 +12071,8 @@ static void free_cntrs(struct hfi1_devdata *dd)
12089 struct hfi1_pportdata *ppd; 12071 struct hfi1_pportdata *ppd;
12090 int i; 12072 int i;
12091 12073
12092 if (dd->synth_stats_timer.data) 12074 if (dd->synth_stats_timer.function)
12093 del_timer_sync(&dd->synth_stats_timer); 12075 del_timer_sync(&dd->synth_stats_timer);
12094 dd->synth_stats_timer.data = 0;
12095 ppd = (struct hfi1_pportdata *)(dd + 1); 12076 ppd = (struct hfi1_pportdata *)(dd + 1);
12096 for (i = 0; i < dd->num_pports; i++, ppd++) { 12077 for (i = 0; i < dd->num_pports; i++, ppd++) {
12097 kfree(ppd->cntrs); 12078 kfree(ppd->cntrs);
@@ -12367,9 +12348,9 @@ static void do_update_synth_timer(struct work_struct *work)
12367 } 12348 }
12368} 12349}
12369 12350
12370static void update_synth_timer(unsigned long opaque) 12351static void update_synth_timer(struct timer_list *t)
12371{ 12352{
12372 struct hfi1_devdata *dd = (struct hfi1_devdata *)opaque; 12353 struct hfi1_devdata *dd = from_timer(dd, t, synth_stats_timer);
12373 12354
12374 queue_work(dd->update_cntr_wq, &dd->update_cntr_work); 12355 queue_work(dd->update_cntr_wq, &dd->update_cntr_work);
12375 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); 12356 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
@@ -12387,8 +12368,7 @@ static int init_cntrs(struct hfi1_devdata *dd)
12387 const int bit_type_32_sz = strlen(bit_type_32); 12368 const int bit_type_32_sz = strlen(bit_type_32);
12388 12369
12389 /* set up the stats timer; the add_timer is done at the end */ 12370 /* set up the stats timer; the add_timer is done at the end */
12390 setup_timer(&dd->synth_stats_timer, update_synth_timer, 12371 timer_setup(&dd->synth_stats_timer, update_synth_timer, 0);
12391 (unsigned long)dd);
12392 12372
12393 /***********************/ 12373 /***********************/
12394 /* per device counters */ 12374 /* per device counters */
@@ -12701,6 +12681,17 @@ const char *opa_pstate_name(u32 pstate)
12701 return "unknown"; 12681 return "unknown";
12702} 12682}
12703 12683
12684/**
12685 * update_statusp - Update userspace status flag
12686 * @ppd: Port data structure
12687 * @state: port state information
12688 *
12689 * Actual port status is determined by the host_link_state value
12690 * in the ppd.
12691 *
12692 * host_link_state MUST be updated before updating the user space
12693 * statusp.
12694 */
12704static void update_statusp(struct hfi1_pportdata *ppd, u32 state) 12695static void update_statusp(struct hfi1_pportdata *ppd, u32 state)
12705{ 12696{
12706 /* 12697 /*
@@ -12726,9 +12717,11 @@ static void update_statusp(struct hfi1_pportdata *ppd, u32 state)
12726 break; 12717 break;
12727 } 12718 }
12728 } 12719 }
12720 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
12721 opa_lstate_name(state), state);
12729} 12722}
12730 12723
12731/* 12724/**
12732 * wait_logical_linkstate - wait for an IB link state change to occur 12725 * wait_logical_linkstate - wait for an IB link state change to occur
12733 * @ppd: port device 12726 * @ppd: port device
12734 * @state: the state to wait for 12727 * @state: the state to wait for
@@ -12759,11 +12752,6 @@ static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
12759 msleep(20); 12752 msleep(20);
12760 } 12753 }
12761 12754
12762 update_statusp(ppd, state);
12763 dd_dev_info(ppd->dd,
12764 "logical state changed to %s (0x%x)\n",
12765 opa_lstate_name(state),
12766 state);
12767 return 0; 12755 return 0;
12768} 12756}
12769 12757
@@ -12910,6 +12898,32 @@ int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
12910 return ret; 12898 return ret;
12911} 12899}
12912 12900
12901/**
12902 * get_int_mask - get 64 bit int mask
12903 * @dd - the devdata
12904 * @i - the csr (relative to CCE_INT_MASK)
12905 *
12906 * Returns the mask with the urgent interrupt mask
12907 * bit clear for kernel receive contexts.
12908 */
12909static u64 get_int_mask(struct hfi1_devdata *dd, u32 i)
12910{
12911 u64 mask = U64_MAX; /* default to no change */
12912
12913 if (i >= (IS_RCVURGENT_START / 64) && i < (IS_RCVURGENT_END / 64)) {
12914 int j = (i - (IS_RCVURGENT_START / 64)) * 64;
12915 int k = !j ? IS_RCVURGENT_START % 64 : 0;
12916
12917 if (j)
12918 j -= IS_RCVURGENT_START % 64;
12919 /* j = 0..dd->first_dyn_alloc_ctxt - 1,k = 0..63 */
12920 for (; j < dd->first_dyn_alloc_ctxt && k < 64; j++, k++)
12921 /* convert to bit in mask and clear */
12922 mask &= ~BIT_ULL(k);
12923 }
12924 return mask;
12925}
12926
12913/* ========================================================================= */ 12927/* ========================================================================= */
12914 12928
12915/* 12929/*
@@ -12923,9 +12937,12 @@ void set_intr_state(struct hfi1_devdata *dd, u32 enable)
12923 * In HFI, the mask needs to be 1 to allow interrupts. 12937 * In HFI, the mask needs to be 1 to allow interrupts.
12924 */ 12938 */
12925 if (enable) { 12939 if (enable) {
12926 /* enable all interrupts */ 12940 /* enable all interrupts but urgent on kernel contexts */
12927 for (i = 0; i < CCE_NUM_INT_CSRS; i++) 12941 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
12928 write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0); 12942 u64 mask = get_int_mask(dd, i);
12943
12944 write_csr(dd, CCE_INT_MASK + (8 * i), mask);
12945 }
12929 12946
12930 init_qsfp_int(dd); 12947 init_qsfp_int(dd);
12931 } else { 12948 } else {
@@ -12980,7 +12997,7 @@ static void clean_up_interrupts(struct hfi1_devdata *dd)
12980 if (!me->arg) /* => no irq, no affinity */ 12997 if (!me->arg) /* => no irq, no affinity */
12981 continue; 12998 continue;
12982 hfi1_put_irq_affinity(dd, me); 12999 hfi1_put_irq_affinity(dd, me);
12983 free_irq(me->irq, me->arg); 13000 pci_free_irq(dd->pcidev, i, me->arg);
12984 } 13001 }
12985 13002
12986 /* clean structures */ 13003 /* clean structures */
@@ -12990,7 +13007,7 @@ static void clean_up_interrupts(struct hfi1_devdata *dd)
12990 } else { 13007 } else {
12991 /* INTx */ 13008 /* INTx */
12992 if (dd->requested_intx_irq) { 13009 if (dd->requested_intx_irq) {
12993 free_irq(dd->pcidev->irq, dd); 13010 pci_free_irq(dd->pcidev, 0, dd);
12994 dd->requested_intx_irq = 0; 13011 dd->requested_intx_irq = 0;
12995 } 13012 }
12996 disable_intx(dd->pcidev); 13013 disable_intx(dd->pcidev);
@@ -13049,10 +13066,8 @@ static int request_intx_irq(struct hfi1_devdata *dd)
13049{ 13066{
13050 int ret; 13067 int ret;
13051 13068
13052 snprintf(dd->intx_name, sizeof(dd->intx_name), DRIVER_NAME "_%d", 13069 ret = pci_request_irq(dd->pcidev, 0, general_interrupt, NULL, dd,
13053 dd->unit); 13070 DRIVER_NAME "_%d", dd->unit);
13054 ret = request_irq(dd->pcidev->irq, general_interrupt,
13055 IRQF_SHARED, dd->intx_name, dd);
13056 if (ret) 13071 if (ret)
13057 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n", 13072 dd_dev_err(dd, "unable to request INTx interrupt, err %d\n",
13058 ret); 13073 ret);
@@ -13074,7 +13089,7 @@ static int request_msix_irqs(struct hfi1_devdata *dd)
13074 first_sdma = last_general; 13089 first_sdma = last_general;
13075 last_sdma = first_sdma + dd->num_sdma; 13090 last_sdma = first_sdma + dd->num_sdma;
13076 first_rx = last_sdma; 13091 first_rx = last_sdma;
13077 last_rx = first_rx + dd->n_krcv_queues + HFI1_NUM_VNIC_CTXT; 13092 last_rx = first_rx + dd->n_krcv_queues + dd->num_vnic_contexts;
13078 13093
13079 /* VNIC MSIx interrupts get mapped when VNIC contexts are created */ 13094 /* VNIC MSIx interrupts get mapped when VNIC contexts are created */
13080 dd->first_dyn_msix_idx = first_rx + dd->n_krcv_queues; 13095 dd->first_dyn_msix_idx = first_rx + dd->n_krcv_queues;
@@ -13095,13 +13110,14 @@ static int request_msix_irqs(struct hfi1_devdata *dd)
13095 int idx; 13110 int idx;
13096 struct hfi1_ctxtdata *rcd = NULL; 13111 struct hfi1_ctxtdata *rcd = NULL;
13097 struct sdma_engine *sde = NULL; 13112 struct sdma_engine *sde = NULL;
13113 char name[MAX_NAME_SIZE];
13098 13114
13099 /* obtain the arguments to request_irq */ 13115 /* obtain the arguments to pci_request_irq */
13100 if (first_general <= i && i < last_general) { 13116 if (first_general <= i && i < last_general) {
13101 idx = i - first_general; 13117 idx = i - first_general;
13102 handler = general_interrupt; 13118 handler = general_interrupt;
13103 arg = dd; 13119 arg = dd;
13104 snprintf(me->name, sizeof(me->name), 13120 snprintf(name, sizeof(name),
13105 DRIVER_NAME "_%d", dd->unit); 13121 DRIVER_NAME "_%d", dd->unit);
13106 err_info = "general"; 13122 err_info = "general";
13107 me->type = IRQ_GENERAL; 13123 me->type = IRQ_GENERAL;
@@ -13110,14 +13126,14 @@ static int request_msix_irqs(struct hfi1_devdata *dd)
13110 sde = &dd->per_sdma[idx]; 13126 sde = &dd->per_sdma[idx];
13111 handler = sdma_interrupt; 13127 handler = sdma_interrupt;
13112 arg = sde; 13128 arg = sde;
13113 snprintf(me->name, sizeof(me->name), 13129 snprintf(name, sizeof(name),
13114 DRIVER_NAME "_%d sdma%d", dd->unit, idx); 13130 DRIVER_NAME "_%d sdma%d", dd->unit, idx);
13115 err_info = "sdma"; 13131 err_info = "sdma";
13116 remap_sdma_interrupts(dd, idx, i); 13132 remap_sdma_interrupts(dd, idx, i);
13117 me->type = IRQ_SDMA; 13133 me->type = IRQ_SDMA;
13118 } else if (first_rx <= i && i < last_rx) { 13134 } else if (first_rx <= i && i < last_rx) {
13119 idx = i - first_rx; 13135 idx = i - first_rx;
13120 rcd = hfi1_rcd_get_by_index(dd, idx); 13136 rcd = hfi1_rcd_get_by_index_safe(dd, idx);
13121 if (rcd) { 13137 if (rcd) {
13122 /* 13138 /*
13123 * Set the interrupt register and mask for this 13139 * Set the interrupt register and mask for this
@@ -13129,7 +13145,7 @@ static int request_msix_irqs(struct hfi1_devdata *dd)
13129 handler = receive_context_interrupt; 13145 handler = receive_context_interrupt;
13130 thread = receive_context_thread; 13146 thread = receive_context_thread;
13131 arg = rcd; 13147 arg = rcd;
13132 snprintf(me->name, sizeof(me->name), 13148 snprintf(name, sizeof(name),
13133 DRIVER_NAME "_%d kctxt%d", 13149 DRIVER_NAME "_%d kctxt%d",
13134 dd->unit, idx); 13150 dd->unit, idx);
13135 err_info = "receive context"; 13151 err_info = "receive context";
@@ -13150,18 +13166,10 @@ static int request_msix_irqs(struct hfi1_devdata *dd)
13150 if (!arg) 13166 if (!arg)
13151 continue; 13167 continue;
13152 /* make sure the name is terminated */ 13168 /* make sure the name is terminated */
13153 me->name[sizeof(me->name) - 1] = 0; 13169 name[sizeof(name) - 1] = 0;
13154 me->irq = pci_irq_vector(dd->pcidev, i); 13170 me->irq = pci_irq_vector(dd->pcidev, i);
13155 /* 13171 ret = pci_request_irq(dd->pcidev, i, handler, thread, arg,
13156 * On err return me->irq. Don't need to clear this 13172 name);
13157 * because 'arg' has not been set, and cleanup will
13158 * do the right thing.
13159 */
13160 if (me->irq < 0)
13161 return me->irq;
13162
13163 ret = request_threaded_irq(me->irq, handler, thread, 0,
13164 me->name, arg);
13165 if (ret) { 13173 if (ret) {
13166 dd_dev_err(dd, 13174 dd_dev_err(dd,
13167 "unable to allocate %s interrupt, irq %d, index %d, err %d\n", 13175 "unable to allocate %s interrupt, irq %d, index %d, err %d\n",
@@ -13169,7 +13177,7 @@ static int request_msix_irqs(struct hfi1_devdata *dd)
13169 return ret; 13177 return ret;
13170 } 13178 }
13171 /* 13179 /*
13172 * assign arg after request_irq call, so it will be 13180 * assign arg after pci_request_irq call, so it will be
13173 * cleaned up 13181 * cleaned up
13174 */ 13182 */
13175 me->arg = arg; 13183 me->arg = arg;
@@ -13187,7 +13195,7 @@ void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd)
13187 int i; 13195 int i;
13188 13196
13189 if (!dd->num_msix_entries) { 13197 if (!dd->num_msix_entries) {
13190 synchronize_irq(dd->pcidev->irq); 13198 synchronize_irq(pci_irq_vector(dd->pcidev, 0));
13191 return; 13199 return;
13192 } 13200 }
13193 13201
@@ -13208,7 +13216,7 @@ void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd)
13208 return; 13216 return;
13209 13217
13210 hfi1_put_irq_affinity(dd, me); 13218 hfi1_put_irq_affinity(dd, me);
13211 free_irq(me->irq, me->arg); 13219 pci_free_irq(dd->pcidev, rcd->msix_intr, me->arg);
13212 13220
13213 me->arg = NULL; 13221 me->arg = NULL;
13214} 13222}
@@ -13231,28 +13239,21 @@ void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd)
13231 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64; 13239 rcd->ireg = (IS_RCVAVAIL_START + idx) / 64;
13232 rcd->imask = ((u64)1) << 13240 rcd->imask = ((u64)1) <<
13233 ((IS_RCVAVAIL_START + idx) % 64); 13241 ((IS_RCVAVAIL_START + idx) % 64);
13234
13235 snprintf(me->name, sizeof(me->name),
13236 DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
13237 me->name[sizeof(me->name) - 1] = 0;
13238 me->type = IRQ_RCVCTXT; 13242 me->type = IRQ_RCVCTXT;
13239 me->irq = pci_irq_vector(dd->pcidev, rcd->msix_intr); 13243 me->irq = pci_irq_vector(dd->pcidev, rcd->msix_intr);
13240 if (me->irq < 0) {
13241 dd_dev_err(dd, "vnic irq vector request (idx %d) fail %d\n",
13242 idx, me->irq);
13243 return;
13244 }
13245 remap_intr(dd, IS_RCVAVAIL_START + idx, rcd->msix_intr); 13244 remap_intr(dd, IS_RCVAVAIL_START + idx, rcd->msix_intr);
13246 13245
13247 ret = request_threaded_irq(me->irq, receive_context_interrupt, 13246 ret = pci_request_irq(dd->pcidev, rcd->msix_intr,
13248 receive_context_thread, 0, me->name, arg); 13247 receive_context_interrupt,
13248 receive_context_thread, arg,
13249 DRIVER_NAME "_%d kctxt%d", dd->unit, idx);
13249 if (ret) { 13250 if (ret) {
13250 dd_dev_err(dd, "vnic irq request (irq %d, idx %d) fail %d\n", 13251 dd_dev_err(dd, "vnic irq request (irq %d, idx %d) fail %d\n",
13251 me->irq, idx, ret); 13252 me->irq, idx, ret);
13252 return; 13253 return;
13253 } 13254 }
13254 /* 13255 /*
13255 * assign arg after request_irq call, so it will be 13256 * assign arg after pci_request_irq call, so it will be
13256 * cleaned up 13257 * cleaned up
13257 */ 13258 */
13258 me->arg = arg; 13259 me->arg = arg;
@@ -13261,7 +13262,7 @@ void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd)
13261 if (ret) { 13262 if (ret) {
13262 dd_dev_err(dd, 13263 dd_dev_err(dd,
13263 "unable to pin IRQ %d\n", ret); 13264 "unable to pin IRQ %d\n", ret);
13264 free_irq(me->irq, me->arg); 13265 pci_free_irq(dd->pcidev, rcd->msix_intr, me->arg);
13265 } 13266 }
13266} 13267}
13267 13268
@@ -13294,8 +13295,9 @@ static int set_up_interrupts(struct hfi1_devdata *dd)
13294 * slow source, SDMACleanupDone) 13295 * slow source, SDMACleanupDone)
13295 * N interrupts - one per used SDMA engine 13296 * N interrupts - one per used SDMA engine
13296 * M interrupt - one per kernel receive context 13297 * M interrupt - one per kernel receive context
13298 * V interrupt - one for each VNIC context
13297 */ 13299 */
13298 total = 1 + dd->num_sdma + dd->n_krcv_queues + HFI1_NUM_VNIC_CTXT; 13300 total = 1 + dd->num_sdma + dd->n_krcv_queues + dd->num_vnic_contexts;
13299 13301
13300 /* ask for MSI-X interrupts */ 13302 /* ask for MSI-X interrupts */
13301 request = request_msix(dd, total); 13303 request = request_msix(dd, total);
@@ -13356,15 +13358,18 @@ fail:
13356 * in array of contexts 13358 * in array of contexts
13357 * freectxts - number of free user contexts 13359 * freectxts - number of free user contexts
13358 * num_send_contexts - number of PIO send contexts being used 13360 * num_send_contexts - number of PIO send contexts being used
13361 * num_vnic_contexts - number of contexts reserved for VNIC
13359 */ 13362 */
13360static int set_up_context_variables(struct hfi1_devdata *dd) 13363static int set_up_context_variables(struct hfi1_devdata *dd)
13361{ 13364{
13362 unsigned long num_kernel_contexts; 13365 unsigned long num_kernel_contexts;
13366 u16 num_vnic_contexts = HFI1_NUM_VNIC_CTXT;
13363 int total_contexts; 13367 int total_contexts;
13364 int ret; 13368 int ret;
13365 unsigned ngroups; 13369 unsigned ngroups;
13366 int qos_rmt_count; 13370 int qos_rmt_count;
13367 int user_rmt_reduced; 13371 int user_rmt_reduced;
13372 u32 n_usr_ctxts;
13368 13373
13369 /* 13374 /*
13370 * Kernel receive contexts: 13375 * Kernel receive contexts:
@@ -13393,59 +13398,63 @@ static int set_up_context_variables(struct hfi1_devdata *dd)
13393 num_kernel_contexts); 13398 num_kernel_contexts);
13394 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1; 13399 num_kernel_contexts = dd->chip_send_contexts - num_vls - 1;
13395 } 13400 }
13401
13402 /* Accommodate VNIC contexts if possible */
13403 if ((num_kernel_contexts + num_vnic_contexts) > dd->chip_rcv_contexts) {
13404 dd_dev_err(dd, "No receive contexts available for VNIC\n");
13405 num_vnic_contexts = 0;
13406 }
13407 total_contexts = num_kernel_contexts + num_vnic_contexts;
13408
13396 /* 13409 /*
13397 * User contexts: 13410 * User contexts:
13398 * - default to 1 user context per real (non-HT) CPU core if 13411 * - default to 1 user context per real (non-HT) CPU core if
13399 * num_user_contexts is negative 13412 * num_user_contexts is negative
13400 */ 13413 */
13401 if (num_user_contexts < 0) 13414 if (num_user_contexts < 0)
13402 num_user_contexts = 13415 n_usr_ctxts = cpumask_weight(&node_affinity.real_cpu_mask);
13403 cpumask_weight(&node_affinity.real_cpu_mask); 13416 else
13404 13417 n_usr_ctxts = num_user_contexts;
13405 total_contexts = num_kernel_contexts + num_user_contexts;
13406
13407 /* 13418 /*
13408 * Adjust the counts given a global max. 13419 * Adjust the counts given a global max.
13409 */ 13420 */
13410 if (total_contexts > dd->chip_rcv_contexts) { 13421 if (total_contexts + n_usr_ctxts > dd->chip_rcv_contexts) {
13411 dd_dev_err(dd, 13422 dd_dev_err(dd,
13412 "Reducing # user receive contexts to: %d, from %d\n", 13423 "Reducing # user receive contexts to: %d, from %u\n",
13413 (int)(dd->chip_rcv_contexts - num_kernel_contexts), 13424 (int)(dd->chip_rcv_contexts - total_contexts),
13414 (int)num_user_contexts); 13425 n_usr_ctxts);
13415 num_user_contexts = dd->chip_rcv_contexts - num_kernel_contexts;
13416 /* recalculate */ 13426 /* recalculate */
13417 total_contexts = num_kernel_contexts + num_user_contexts; 13427 n_usr_ctxts = dd->chip_rcv_contexts - total_contexts;
13418 } 13428 }
13419 13429
13420 /* each user context requires an entry in the RMT */ 13430 /* each user context requires an entry in the RMT */
13421 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL); 13431 qos_rmt_count = qos_rmt_entries(dd, NULL, NULL);
13422 if (qos_rmt_count + num_user_contexts > NUM_MAP_ENTRIES) { 13432 if (qos_rmt_count + n_usr_ctxts > NUM_MAP_ENTRIES) {
13423 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count; 13433 user_rmt_reduced = NUM_MAP_ENTRIES - qos_rmt_count;
13424 dd_dev_err(dd, 13434 dd_dev_err(dd,
13425 "RMT size is reducing the number of user receive contexts from %d to %d\n", 13435 "RMT size is reducing the number of user receive contexts from %u to %d\n",
13426 (int)num_user_contexts, 13436 n_usr_ctxts,
13427 user_rmt_reduced); 13437 user_rmt_reduced);
13428 /* recalculate */ 13438 /* recalculate */
13429 num_user_contexts = user_rmt_reduced; 13439 n_usr_ctxts = user_rmt_reduced;
13430 total_contexts = num_kernel_contexts + num_user_contexts;
13431 } 13440 }
13432 13441
13433 /* Accommodate VNIC contexts */ 13442 total_contexts += n_usr_ctxts;
13434 if ((total_contexts + HFI1_NUM_VNIC_CTXT) <= dd->chip_rcv_contexts)
13435 total_contexts += HFI1_NUM_VNIC_CTXT;
13436 13443
13437 /* the first N are kernel contexts, the rest are user/vnic contexts */ 13444 /* the first N are kernel contexts, the rest are user/vnic contexts */
13438 dd->num_rcv_contexts = total_contexts; 13445 dd->num_rcv_contexts = total_contexts;
13439 dd->n_krcv_queues = num_kernel_contexts; 13446 dd->n_krcv_queues = num_kernel_contexts;
13440 dd->first_dyn_alloc_ctxt = num_kernel_contexts; 13447 dd->first_dyn_alloc_ctxt = num_kernel_contexts;
13441 dd->num_user_contexts = num_user_contexts; 13448 dd->num_vnic_contexts = num_vnic_contexts;
13442 dd->freectxts = num_user_contexts; 13449 dd->num_user_contexts = n_usr_ctxts;
13450 dd->freectxts = n_usr_ctxts;
13443 dd_dev_info(dd, 13451 dd_dev_info(dd,
13444 "rcv contexts: chip %d, used %d (kernel %d, user %d)\n", 13452 "rcv contexts: chip %d, used %d (kernel %d, vnic %u, user %u)\n",
13445 (int)dd->chip_rcv_contexts, 13453 (int)dd->chip_rcv_contexts,
13446 (int)dd->num_rcv_contexts, 13454 (int)dd->num_rcv_contexts,
13447 (int)dd->n_krcv_queues, 13455 (int)dd->n_krcv_queues,
13448 (int)dd->num_rcv_contexts - dd->n_krcv_queues); 13456 dd->num_vnic_contexts,
13457 dd->num_user_contexts);
13449 13458
13450 /* 13459 /*
13451 * Receive array allocation: 13460 * Receive array allocation:
@@ -14962,8 +14971,6 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
14962 init_vl_arb_caches(ppd); 14971 init_vl_arb_caches(ppd);
14963 } 14972 }
14964 14973
14965 dd->link_default = HLS_DN_POLL;
14966
14967 /* 14974 /*
14968 * Do remaining PCIe setup and save PCIe values in dd. 14975 * Do remaining PCIe setup and save PCIe values in dd.
14969 * Any error printing is already done by the init code. 14976 * Any error printing is already done by the init code.
diff --git a/drivers/infiniband/hw/hfi1/chip.h b/drivers/infiniband/hw/hfi1/chip.h
index 50b8645d0b87..133e313feca4 100644
--- a/drivers/infiniband/hw/hfi1/chip.h
+++ b/drivers/infiniband/hw/hfi1/chip.h
@@ -560,7 +560,7 @@ enum {
560/* timeouts */ 560/* timeouts */
561#define LINK_RESTART_DELAY 1000 /* link restart delay, in ms */ 561#define LINK_RESTART_DELAY 1000 /* link restart delay, in ms */
562#define TIMEOUT_8051_START 5000 /* 8051 start timeout, in ms */ 562#define TIMEOUT_8051_START 5000 /* 8051 start timeout, in ms */
563#define DC8051_COMMAND_TIMEOUT 20000 /* DC8051 command timeout, in ms */ 563#define DC8051_COMMAND_TIMEOUT 1000 /* DC8051 command timeout, in ms */
564#define FREEZE_STATUS_TIMEOUT 20 /* wait for freeze indicators, in ms */ 564#define FREEZE_STATUS_TIMEOUT 20 /* wait for freeze indicators, in ms */
565#define VL_STATUS_CLEAR_TIMEOUT 5000 /* per-VL status clear, in ms */ 565#define VL_STATUS_CLEAR_TIMEOUT 5000 /* per-VL status clear, in ms */
566#define CCE_STATUS_TIMEOUT 10 /* time to clear CCE Status, in ms */ 566#define CCE_STATUS_TIMEOUT 10 /* time to clear CCE Status, in ms */
@@ -583,6 +583,9 @@ enum {
583#define LOOPBACK_LCB 2 583#define LOOPBACK_LCB 2
584#define LOOPBACK_CABLE 3 /* external cable */ 584#define LOOPBACK_CABLE 3 /* external cable */
585 585
586/* set up serdes bit in MISC_CONFIG_BITS */
587#define LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT 0
588
586/* read and write hardware registers */ 589/* read and write hardware registers */
587u64 read_csr(const struct hfi1_devdata *dd, u32 offset); 590u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
588void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value); 591void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
@@ -710,6 +713,7 @@ void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
710 u8 *ver_patch); 713 u8 *ver_patch);
711int write_host_interface_version(struct hfi1_devdata *dd, u8 version); 714int write_host_interface_version(struct hfi1_devdata *dd, u8 version);
712void read_guid(struct hfi1_devdata *dd); 715void read_guid(struct hfi1_devdata *dd);
716int release_and_wait_ready_8051_firmware(struct hfi1_devdata *dd);
713int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout); 717int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout);
714void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason, 718void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
715 u8 neigh_reason, u8 rem_reason); 719 u8 neigh_reason, u8 rem_reason);
diff --git a/drivers/infiniband/hw/hfi1/common.h b/drivers/infiniband/hw/hfi1/common.h
index 3e27794ec750..7108d4d92259 100644
--- a/drivers/infiniband/hw/hfi1/common.h
+++ b/drivers/infiniband/hw/hfi1/common.h
@@ -328,6 +328,7 @@ struct diag_pkt {
328#define SC15_PACKET 0xF 328#define SC15_PACKET 0xF
329#define SIZE_OF_CRC 1 329#define SIZE_OF_CRC 1
330#define SIZE_OF_LT 1 330#define SIZE_OF_LT 1
331#define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
331 332
332#define LIM_MGMT_P_KEY 0x7FFF 333#define LIM_MGMT_P_KEY 0x7FFF
333#define FULL_MGMT_P_KEY 0xFFFF 334#define FULL_MGMT_P_KEY 0xFFFF
diff --git a/drivers/infiniband/hw/hfi1/debugfs.c b/drivers/infiniband/hw/hfi1/debugfs.c
index 36ae1fd86502..76157cc03eca 100644
--- a/drivers/infiniband/hw/hfi1/debugfs.c
+++ b/drivers/infiniband/hw/hfi1/debugfs.c
@@ -165,6 +165,17 @@ static void _opcode_stats_seq_stop(struct seq_file *s, void *v)
165{ 165{
166} 166}
167 167
168static int opcode_stats_show(struct seq_file *s, u8 i, u64 packets, u64 bytes)
169{
170 if (!packets && !bytes)
171 return SEQ_SKIP;
172 seq_printf(s, "%02x %llu/%llu\n", i,
173 (unsigned long long)packets,
174 (unsigned long long)bytes);
175
176 return 0;
177}
178
168static int _opcode_stats_seq_show(struct seq_file *s, void *v) 179static int _opcode_stats_seq_show(struct seq_file *s, void *v)
169{ 180{
170 loff_t *spos = v; 181 loff_t *spos = v;
@@ -182,19 +193,49 @@ static int _opcode_stats_seq_show(struct seq_file *s, void *v)
182 } 193 }
183 hfi1_rcd_put(rcd); 194 hfi1_rcd_put(rcd);
184 } 195 }
185 if (!n_packets && !n_bytes) 196 return opcode_stats_show(s, i, n_packets, n_bytes);
186 return SEQ_SKIP;
187 seq_printf(s, "%02llx %llu/%llu\n", i,
188 (unsigned long long)n_packets,
189 (unsigned long long)n_bytes);
190
191 return 0;
192} 197}
193 198
194DEBUGFS_SEQ_FILE_OPS(opcode_stats); 199DEBUGFS_SEQ_FILE_OPS(opcode_stats);
195DEBUGFS_SEQ_FILE_OPEN(opcode_stats) 200DEBUGFS_SEQ_FILE_OPEN(opcode_stats)
196DEBUGFS_FILE_OPS(opcode_stats); 201DEBUGFS_FILE_OPS(opcode_stats);
197 202
203static void *_tx_opcode_stats_seq_start(struct seq_file *s, loff_t *pos)
204{
205 return _opcode_stats_seq_start(s, pos);
206}
207
208static void *_tx_opcode_stats_seq_next(struct seq_file *s, void *v, loff_t *pos)
209{
210 return _opcode_stats_seq_next(s, v, pos);
211}
212
213static void _tx_opcode_stats_seq_stop(struct seq_file *s, void *v)
214{
215}
216
217static int _tx_opcode_stats_seq_show(struct seq_file *s, void *v)
218{
219 loff_t *spos = v;
220 loff_t i = *spos;
221 int j;
222 u64 n_packets = 0, n_bytes = 0;
223 struct hfi1_ibdev *ibd = (struct hfi1_ibdev *)s->private;
224 struct hfi1_devdata *dd = dd_from_dev(ibd);
225
226 for_each_possible_cpu(j) {
227 struct hfi1_opcode_stats_perctx *s =
228 per_cpu_ptr(dd->tx_opstats, j);
229 n_packets += s->stats[i].n_packets;
230 n_bytes += s->stats[i].n_bytes;
231 }
232 return opcode_stats_show(s, i, n_packets, n_bytes);
233}
234
235DEBUGFS_SEQ_FILE_OPS(tx_opcode_stats);
236DEBUGFS_SEQ_FILE_OPEN(tx_opcode_stats)
237DEBUGFS_FILE_OPS(tx_opcode_stats);
238
198static void *_ctx_stats_seq_start(struct seq_file *s, loff_t *pos) 239static void *_ctx_stats_seq_start(struct seq_file *s, loff_t *pos)
199{ 240{
200 struct hfi1_ibdev *ibd = (struct hfi1_ibdev *)s->private; 241 struct hfi1_ibdev *ibd = (struct hfi1_ibdev *)s->private;
@@ -243,7 +284,7 @@ static int _ctx_stats_seq_show(struct seq_file *s, void *v)
243 spos = v; 284 spos = v;
244 i = *spos; 285 i = *spos;
245 286
246 rcd = hfi1_rcd_get_by_index(dd, i); 287 rcd = hfi1_rcd_get_by_index_safe(dd, i);
247 if (!rcd) 288 if (!rcd)
248 return SEQ_SKIP; 289 return SEQ_SKIP;
249 290
@@ -402,7 +443,7 @@ static int _rcds_seq_show(struct seq_file *s, void *v)
402 loff_t *spos = v; 443 loff_t *spos = v;
403 loff_t i = *spos; 444 loff_t i = *spos;
404 445
405 rcd = hfi1_rcd_get_by_index(dd, i); 446 rcd = hfi1_rcd_get_by_index_safe(dd, i);
406 if (rcd) 447 if (rcd)
407 seqfile_dump_rcd(s, rcd); 448 seqfile_dump_rcd(s, rcd);
408 hfi1_rcd_put(rcd); 449 hfi1_rcd_put(rcd);
@@ -1363,6 +1404,7 @@ void hfi1_dbg_ibdev_init(struct hfi1_ibdev *ibd)
1363 return; 1404 return;
1364 } 1405 }
1365 DEBUGFS_SEQ_FILE_CREATE(opcode_stats, ibd->hfi1_ibdev_dbg, ibd); 1406 DEBUGFS_SEQ_FILE_CREATE(opcode_stats, ibd->hfi1_ibdev_dbg, ibd);
1407 DEBUGFS_SEQ_FILE_CREATE(tx_opcode_stats, ibd->hfi1_ibdev_dbg, ibd);
1366 DEBUGFS_SEQ_FILE_CREATE(ctx_stats, ibd->hfi1_ibdev_dbg, ibd); 1408 DEBUGFS_SEQ_FILE_CREATE(ctx_stats, ibd->hfi1_ibdev_dbg, ibd);
1367 DEBUGFS_SEQ_FILE_CREATE(qp_stats, ibd->hfi1_ibdev_dbg, ibd); 1409 DEBUGFS_SEQ_FILE_CREATE(qp_stats, ibd->hfi1_ibdev_dbg, ibd);
1368 DEBUGFS_SEQ_FILE_CREATE(sdes, ibd->hfi1_ibdev_dbg, ibd); 1410 DEBUGFS_SEQ_FILE_CREATE(sdes, ibd->hfi1_ibdev_dbg, ibd);
diff --git a/drivers/infiniband/hw/hfi1/driver.c b/drivers/infiniband/hw/hfi1/driver.c
index 7372cc00cb2d..4f65ac671044 100644
--- a/drivers/infiniband/hw/hfi1/driver.c
+++ b/drivers/infiniband/hw/hfi1/driver.c
@@ -433,6 +433,12 @@ static inline void init_packet(struct hfi1_ctxtdata *rcd,
433 packet->numpkt = 0; 433 packet->numpkt = 0;
434} 434}
435 435
436/* We support only two types - 9B and 16B for now */
437static const hfi1_handle_cnp hfi1_handle_cnp_tbl[2] = {
438 [HFI1_PKT_TYPE_9B] = &return_cnp,
439 [HFI1_PKT_TYPE_16B] = &return_cnp_16B
440};
441
436void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt, 442void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
437 bool do_cnp) 443 bool do_cnp)
438{ 444{
@@ -866,7 +872,7 @@ static inline void set_nodma_rtail(struct hfi1_devdata *dd, u16 ctxt)
866 * interrupt handler for all statically allocated kernel contexts. 872 * interrupt handler for all statically allocated kernel contexts.
867 */ 873 */
868 if (ctxt >= dd->first_dyn_alloc_ctxt) { 874 if (ctxt >= dd->first_dyn_alloc_ctxt) {
869 rcd = hfi1_rcd_get_by_index(dd, ctxt); 875 rcd = hfi1_rcd_get_by_index_safe(dd, ctxt);
870 if (rcd) { 876 if (rcd) {
871 rcd->do_interrupt = 877 rcd->do_interrupt =
872 &handle_receive_interrupt_nodma_rtail; 878 &handle_receive_interrupt_nodma_rtail;
@@ -895,7 +901,7 @@ static inline void set_dma_rtail(struct hfi1_devdata *dd, u16 ctxt)
895 * interrupt handler for all statically allocated kernel contexts. 901 * interrupt handler for all statically allocated kernel contexts.
896 */ 902 */
897 if (ctxt >= dd->first_dyn_alloc_ctxt) { 903 if (ctxt >= dd->first_dyn_alloc_ctxt) {
898 rcd = hfi1_rcd_get_by_index(dd, ctxt); 904 rcd = hfi1_rcd_get_by_index_safe(dd, ctxt);
899 if (rcd) { 905 if (rcd) {
900 rcd->do_interrupt = 906 rcd->do_interrupt =
901 &handle_receive_interrupt_dma_rtail; 907 &handle_receive_interrupt_dma_rtail;
@@ -923,10 +929,9 @@ void set_all_slowpath(struct hfi1_devdata *dd)
923 rcd = hfi1_rcd_get_by_index(dd, i); 929 rcd = hfi1_rcd_get_by_index(dd, i);
924 if (!rcd) 930 if (!rcd)
925 continue; 931 continue;
926 if ((i < dd->first_dyn_alloc_ctxt) || 932 if (i < dd->first_dyn_alloc_ctxt || rcd->is_vnic)
927 (rcd->sc && (rcd->sc->type == SC_KERNEL))) {
928 rcd->do_interrupt = &handle_receive_interrupt; 933 rcd->do_interrupt = &handle_receive_interrupt;
929 } 934
930 hfi1_rcd_put(rcd); 935 hfi1_rcd_put(rcd);
931 } 936 }
932} 937}
@@ -1252,9 +1257,9 @@ void shutdown_led_override(struct hfi1_pportdata *ppd)
1252 write_csr(dd, DCC_CFG_LED_CNTRL, 0); 1257 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
1253} 1258}
1254 1259
1255static void run_led_override(unsigned long opaque) 1260static void run_led_override(struct timer_list *t)
1256{ 1261{
1257 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)opaque; 1262 struct hfi1_pportdata *ppd = from_timer(ppd, t, led_override_timer);
1258 struct hfi1_devdata *dd = ppd->dd; 1263 struct hfi1_devdata *dd = ppd->dd;
1259 unsigned long timeout; 1264 unsigned long timeout;
1260 int phase_idx; 1265 int phase_idx;
@@ -1298,8 +1303,7 @@ void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1298 * timeout so the handler will be called soon to look at our request. 1303 * timeout so the handler will be called soon to look at our request.
1299 */ 1304 */
1300 if (!timer_pending(&ppd->led_override_timer)) { 1305 if (!timer_pending(&ppd->led_override_timer)) {
1301 setup_timer(&ppd->led_override_timer, run_led_override, 1306 timer_setup(&ppd->led_override_timer, run_led_override, 0);
1302 (unsigned long)ppd);
1303 ppd->led_override_timer.expires = jiffies + 1; 1307 ppd->led_override_timer.expires = jiffies + 1;
1304 add_timer(&ppd->led_override_timer); 1308 add_timer(&ppd->led_override_timer);
1305 atomic_set(&ppd->led_override_timer_active, 1); 1309 atomic_set(&ppd->led_override_timer_active, 1);
diff --git a/drivers/infiniband/hw/hfi1/file_ops.c b/drivers/infiniband/hw/hfi1/file_ops.c
index 97bea2e1aa6a..7750a9c38b06 100644
--- a/drivers/infiniband/hw/hfi1/file_ops.c
+++ b/drivers/infiniband/hw/hfi1/file_ops.c
@@ -78,16 +78,20 @@ static unsigned int hfi1_poll(struct file *fp, struct poll_table_struct *pt);
78static int hfi1_file_mmap(struct file *fp, struct vm_area_struct *vma); 78static int hfi1_file_mmap(struct file *fp, struct vm_area_struct *vma);
79 79
80static u64 kvirt_to_phys(void *addr); 80static u64 kvirt_to_phys(void *addr);
81static int assign_ctxt(struct hfi1_filedata *fd, struct hfi1_user_info *uinfo); 81static int assign_ctxt(struct hfi1_filedata *fd, unsigned long arg, u32 len);
82static void init_subctxts(struct hfi1_ctxtdata *uctxt, 82static void init_subctxts(struct hfi1_ctxtdata *uctxt,
83 const struct hfi1_user_info *uinfo); 83 const struct hfi1_user_info *uinfo);
84static int init_user_ctxt(struct hfi1_filedata *fd, 84static int init_user_ctxt(struct hfi1_filedata *fd,
85 struct hfi1_ctxtdata *uctxt); 85 struct hfi1_ctxtdata *uctxt);
86static void user_init(struct hfi1_ctxtdata *uctxt); 86static void user_init(struct hfi1_ctxtdata *uctxt);
87static int get_ctxt_info(struct hfi1_filedata *fd, void __user *ubase, 87static int get_ctxt_info(struct hfi1_filedata *fd, unsigned long arg, u32 len);
88 __u32 len); 88static int get_base_info(struct hfi1_filedata *fd, unsigned long arg, u32 len);
89static int get_base_info(struct hfi1_filedata *fd, void __user *ubase, 89static int user_exp_rcv_setup(struct hfi1_filedata *fd, unsigned long arg,
90 __u32 len); 90 u32 len);
91static int user_exp_rcv_clear(struct hfi1_filedata *fd, unsigned long arg,
92 u32 len);
93static int user_exp_rcv_invalid(struct hfi1_filedata *fd, unsigned long arg,
94 u32 len);
91static int setup_base_ctxt(struct hfi1_filedata *fd, 95static int setup_base_ctxt(struct hfi1_filedata *fd,
92 struct hfi1_ctxtdata *uctxt); 96 struct hfi1_ctxtdata *uctxt);
93static int setup_subctxt(struct hfi1_ctxtdata *uctxt); 97static int setup_subctxt(struct hfi1_ctxtdata *uctxt);
@@ -101,10 +105,11 @@ static void deallocate_ctxt(struct hfi1_ctxtdata *uctxt);
101static unsigned int poll_urgent(struct file *fp, struct poll_table_struct *pt); 105static unsigned int poll_urgent(struct file *fp, struct poll_table_struct *pt);
102static unsigned int poll_next(struct file *fp, struct poll_table_struct *pt); 106static unsigned int poll_next(struct file *fp, struct poll_table_struct *pt);
103static int user_event_ack(struct hfi1_ctxtdata *uctxt, u16 subctxt, 107static int user_event_ack(struct hfi1_ctxtdata *uctxt, u16 subctxt,
104 unsigned long events); 108 unsigned long arg);
105static int set_ctxt_pkey(struct hfi1_ctxtdata *uctxt, u16 subctxt, u16 pkey); 109static int set_ctxt_pkey(struct hfi1_ctxtdata *uctxt, unsigned long arg);
110static int ctxt_reset(struct hfi1_ctxtdata *uctxt);
106static int manage_rcvq(struct hfi1_ctxtdata *uctxt, u16 subctxt, 111static int manage_rcvq(struct hfi1_ctxtdata *uctxt, u16 subctxt,
107 int start_stop); 112 unsigned long arg);
108static int vma_fault(struct vm_fault *vmf); 113static int vma_fault(struct vm_fault *vmf);
109static long hfi1_file_ioctl(struct file *fp, unsigned int cmd, 114static long hfi1_file_ioctl(struct file *fp, unsigned int cmd,
110 unsigned long arg); 115 unsigned long arg);
@@ -221,13 +226,8 @@ static long hfi1_file_ioctl(struct file *fp, unsigned int cmd,
221{ 226{
222 struct hfi1_filedata *fd = fp->private_data; 227 struct hfi1_filedata *fd = fp->private_data;
223 struct hfi1_ctxtdata *uctxt = fd->uctxt; 228 struct hfi1_ctxtdata *uctxt = fd->uctxt;
224 struct hfi1_user_info uinfo;
225 struct hfi1_tid_info tinfo;
226 int ret = 0; 229 int ret = 0;
227 unsigned long addr;
228 int uval = 0; 230 int uval = 0;
229 unsigned long ul_uval = 0;
230 u16 uval16 = 0;
231 231
232 hfi1_cdbg(IOCTL, "IOCTL recv: 0x%x", cmd); 232 hfi1_cdbg(IOCTL, "IOCTL recv: 0x%x", cmd);
233 if (cmd != HFI1_IOCTL_ASSIGN_CTXT && 233 if (cmd != HFI1_IOCTL_ASSIGN_CTXT &&
@@ -237,171 +237,55 @@ static long hfi1_file_ioctl(struct file *fp, unsigned int cmd,
237 237
238 switch (cmd) { 238 switch (cmd) {
239 case HFI1_IOCTL_ASSIGN_CTXT: 239 case HFI1_IOCTL_ASSIGN_CTXT:
240 if (uctxt) 240 ret = assign_ctxt(fd, arg, _IOC_SIZE(cmd));
241 return -EINVAL;
242
243 if (copy_from_user(&uinfo,
244 (struct hfi1_user_info __user *)arg,
245 sizeof(uinfo)))
246 return -EFAULT;
247
248 ret = assign_ctxt(fd, &uinfo);
249 break; 241 break;
242
250 case HFI1_IOCTL_CTXT_INFO: 243 case HFI1_IOCTL_CTXT_INFO:
251 ret = get_ctxt_info(fd, (void __user *)(unsigned long)arg, 244 ret = get_ctxt_info(fd, arg, _IOC_SIZE(cmd));
252 sizeof(struct hfi1_ctxt_info));
253 break; 245 break;
246
254 case HFI1_IOCTL_USER_INFO: 247 case HFI1_IOCTL_USER_INFO:
255 ret = get_base_info(fd, (void __user *)(unsigned long)arg, 248 ret = get_base_info(fd, arg, _IOC_SIZE(cmd));
256 sizeof(struct hfi1_base_info));
257 break; 249 break;
250
258 case HFI1_IOCTL_CREDIT_UPD: 251 case HFI1_IOCTL_CREDIT_UPD:
259 if (uctxt) 252 if (uctxt)
260 sc_return_credits(uctxt->sc); 253 sc_return_credits(uctxt->sc);
261 break; 254 break;
262 255
263 case HFI1_IOCTL_TID_UPDATE: 256 case HFI1_IOCTL_TID_UPDATE:
264 if (copy_from_user(&tinfo, 257 ret = user_exp_rcv_setup(fd, arg, _IOC_SIZE(cmd));
265 (struct hfi11_tid_info __user *)arg,
266 sizeof(tinfo)))
267 return -EFAULT;
268
269 ret = hfi1_user_exp_rcv_setup(fd, &tinfo);
270 if (!ret) {
271 /*
272 * Copy the number of tidlist entries we used
273 * and the length of the buffer we registered.
274 */
275 addr = arg + offsetof(struct hfi1_tid_info, tidcnt);
276 if (copy_to_user((void __user *)addr, &tinfo.tidcnt,
277 sizeof(tinfo.tidcnt)))
278 return -EFAULT;
279
280 addr = arg + offsetof(struct hfi1_tid_info, length);
281 if (copy_to_user((void __user *)addr, &tinfo.length,
282 sizeof(tinfo.length)))
283 ret = -EFAULT;
284 }
285 break; 258 break;
286 259
287 case HFI1_IOCTL_TID_FREE: 260 case HFI1_IOCTL_TID_FREE:
288 if (copy_from_user(&tinfo, 261 ret = user_exp_rcv_clear(fd, arg, _IOC_SIZE(cmd));
289 (struct hfi11_tid_info __user *)arg,
290 sizeof(tinfo)))
291 return -EFAULT;
292
293 ret = hfi1_user_exp_rcv_clear(fd, &tinfo);
294 if (ret)
295 break;
296 addr = arg + offsetof(struct hfi1_tid_info, tidcnt);
297 if (copy_to_user((void __user *)addr, &tinfo.tidcnt,
298 sizeof(tinfo.tidcnt)))
299 ret = -EFAULT;
300 break; 262 break;
301 263
302 case HFI1_IOCTL_TID_INVAL_READ: 264 case HFI1_IOCTL_TID_INVAL_READ:
303 if (copy_from_user(&tinfo, 265 ret = user_exp_rcv_invalid(fd, arg, _IOC_SIZE(cmd));
304 (struct hfi11_tid_info __user *)arg,
305 sizeof(tinfo)))
306 return -EFAULT;
307
308 ret = hfi1_user_exp_rcv_invalid(fd, &tinfo);
309 if (ret)
310 break;
311 addr = arg + offsetof(struct hfi1_tid_info, tidcnt);
312 if (copy_to_user((void __user *)addr, &tinfo.tidcnt,
313 sizeof(tinfo.tidcnt)))
314 ret = -EFAULT;
315 break; 266 break;
316 267
317 case HFI1_IOCTL_RECV_CTRL: 268 case HFI1_IOCTL_RECV_CTRL:
318 ret = get_user(uval, (int __user *)arg); 269 ret = manage_rcvq(uctxt, fd->subctxt, arg);
319 if (ret != 0)
320 return -EFAULT;
321 ret = manage_rcvq(uctxt, fd->subctxt, uval);
322 break; 270 break;
323 271
324 case HFI1_IOCTL_POLL_TYPE: 272 case HFI1_IOCTL_POLL_TYPE:
325 ret = get_user(uval, (int __user *)arg); 273 if (get_user(uval, (int __user *)arg))
326 if (ret != 0)
327 return -EFAULT; 274 return -EFAULT;
328 uctxt->poll_type = (typeof(uctxt->poll_type))uval; 275 uctxt->poll_type = (typeof(uctxt->poll_type))uval;
329 break; 276 break;
330 277
331 case HFI1_IOCTL_ACK_EVENT: 278 case HFI1_IOCTL_ACK_EVENT:
332 ret = get_user(ul_uval, (unsigned long __user *)arg); 279 ret = user_event_ack(uctxt, fd->subctxt, arg);
333 if (ret != 0)
334 return -EFAULT;
335 ret = user_event_ack(uctxt, fd->subctxt, ul_uval);
336 break; 280 break;
337 281
338 case HFI1_IOCTL_SET_PKEY: 282 case HFI1_IOCTL_SET_PKEY:
339 ret = get_user(uval16, (u16 __user *)arg); 283 ret = set_ctxt_pkey(uctxt, arg);
340 if (ret != 0)
341 return -EFAULT;
342 if (HFI1_CAP_IS_USET(PKEY_CHECK))
343 ret = set_ctxt_pkey(uctxt, fd->subctxt, uval16);
344 else
345 return -EPERM;
346 break; 284 break;
347 285
348 case HFI1_IOCTL_CTXT_RESET: { 286 case HFI1_IOCTL_CTXT_RESET:
349 struct send_context *sc; 287 ret = ctxt_reset(uctxt);
350 struct hfi1_devdata *dd;
351
352 if (!uctxt || !uctxt->dd || !uctxt->sc)
353 return -EINVAL;
354
355 /*
356 * There is no protection here. User level has to
357 * guarantee that no one will be writing to the send
358 * context while it is being re-initialized.
359 * If user level breaks that guarantee, it will break
360 * it's own context and no one else's.
361 */
362 dd = uctxt->dd;
363 sc = uctxt->sc;
364 /*
365 * Wait until the interrupt handler has marked the
366 * context as halted or frozen. Report error if we time
367 * out.
368 */
369 wait_event_interruptible_timeout(
370 sc->halt_wait, (sc->flags & SCF_HALTED),
371 msecs_to_jiffies(SEND_CTXT_HALT_TIMEOUT));
372 if (!(sc->flags & SCF_HALTED))
373 return -ENOLCK;
374
375 /*
376 * If the send context was halted due to a Freeze,
377 * wait until the device has been "unfrozen" before
378 * resetting the context.
379 */
380 if (sc->flags & SCF_FROZEN) {
381 wait_event_interruptible_timeout(
382 dd->event_queue,
383 !(READ_ONCE(dd->flags) & HFI1_FROZEN),
384 msecs_to_jiffies(SEND_CTXT_HALT_TIMEOUT));
385 if (dd->flags & HFI1_FROZEN)
386 return -ENOLCK;
387
388 if (dd->flags & HFI1_FORCED_FREEZE)
389 /*
390 * Don't allow context reset if we are into
391 * forced freeze
392 */
393 return -ENODEV;
394
395 sc_disable(sc);
396 ret = sc_enable(sc);
397 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_ENB, uctxt);
398 } else {
399 ret = sc_restart(sc);
400 }
401 if (!ret)
402 sc_return_credits(sc);
403 break; 288 break;
404 }
405 289
406 case HFI1_IOCTL_GET_VERS: 290 case HFI1_IOCTL_GET_VERS:
407 uval = HFI1_USER_SWVERSION; 291 uval = HFI1_USER_SWVERSION;
@@ -595,9 +479,8 @@ static int hfi1_file_mmap(struct file *fp, struct vm_area_struct *vma)
595 * Use the page where this context's flags are. User level 479 * Use the page where this context's flags are. User level
596 * knows where it's own bitmap is within the page. 480 * knows where it's own bitmap is within the page.
597 */ 481 */
598 memaddr = (unsigned long)(dd->events + 482 memaddr = (unsigned long)
599 ((uctxt->ctxt - dd->first_dyn_alloc_ctxt) * 483 (dd->events + uctxt_offset(uctxt)) & PAGE_MASK;
600 HFI1_MAX_SHARED_CTXTS)) & PAGE_MASK;
601 memlen = PAGE_SIZE; 484 memlen = PAGE_SIZE;
602 /* 485 /*
603 * v3.7 removes VM_RESERVED but the effect is kept by 486 * v3.7 removes VM_RESERVED but the effect is kept by
@@ -779,8 +662,7 @@ static int hfi1_file_close(struct inode *inode, struct file *fp)
779 * Clear any left over, unhandled events so the next process that 662 * Clear any left over, unhandled events so the next process that
780 * gets this context doesn't get confused. 663 * gets this context doesn't get confused.
781 */ 664 */
782 ev = dd->events + ((uctxt->ctxt - dd->first_dyn_alloc_ctxt) * 665 ev = dd->events + uctxt_offset(uctxt) + fdata->subctxt;
783 HFI1_MAX_SHARED_CTXTS) + fdata->subctxt;
784 *ev = 0; 666 *ev = 0;
785 667
786 spin_lock_irqsave(&dd->uctxt_lock, flags); 668 spin_lock_irqsave(&dd->uctxt_lock, flags);
@@ -891,21 +773,29 @@ static int complete_subctxt(struct hfi1_filedata *fd)
891 return ret; 773 return ret;
892} 774}
893 775
894static int assign_ctxt(struct hfi1_filedata *fd, struct hfi1_user_info *uinfo) 776static int assign_ctxt(struct hfi1_filedata *fd, unsigned long arg, u32 len)
895{ 777{
896 int ret; 778 int ret;
897 unsigned int swmajor, swminor; 779 unsigned int swmajor;
898 struct hfi1_ctxtdata *uctxt = NULL; 780 struct hfi1_ctxtdata *uctxt = NULL;
781 struct hfi1_user_info uinfo;
782
783 if (fd->uctxt)
784 return -EINVAL;
785
786 if (sizeof(uinfo) != len)
787 return -EINVAL;
899 788
900 swmajor = uinfo->userversion >> 16; 789 if (copy_from_user(&uinfo, (void __user *)arg, sizeof(uinfo)))
790 return -EFAULT;
791
792 swmajor = uinfo.userversion >> 16;
901 if (swmajor != HFI1_USER_SWMAJOR) 793 if (swmajor != HFI1_USER_SWMAJOR)
902 return -ENODEV; 794 return -ENODEV;
903 795
904 if (uinfo->subctxt_cnt > HFI1_MAX_SHARED_CTXTS) 796 if (uinfo.subctxt_cnt > HFI1_MAX_SHARED_CTXTS)
905 return -EINVAL; 797 return -EINVAL;
906 798
907 swminor = uinfo->userversion & 0xffff;
908
909 /* 799 /*
910 * Acquire the mutex to protect against multiple creations of what 800 * Acquire the mutex to protect against multiple creations of what
911 * could be a shared base context. 801 * could be a shared base context.
@@ -915,14 +805,14 @@ static int assign_ctxt(struct hfi1_filedata *fd, struct hfi1_user_info *uinfo)
915 * Get a sub context if available (fd->uctxt will be set). 805 * Get a sub context if available (fd->uctxt will be set).
916 * ret < 0 error, 0 no context, 1 sub-context found 806 * ret < 0 error, 0 no context, 1 sub-context found
917 */ 807 */
918 ret = find_sub_ctxt(fd, uinfo); 808 ret = find_sub_ctxt(fd, &uinfo);
919 809
920 /* 810 /*
921 * Allocate a base context if context sharing is not required or a 811 * Allocate a base context if context sharing is not required or a
922 * sub context wasn't found. 812 * sub context wasn't found.
923 */ 813 */
924 if (!ret) 814 if (!ret)
925 ret = allocate_ctxt(fd, fd->dd, uinfo, &uctxt); 815 ret = allocate_ctxt(fd, fd->dd, &uinfo, &uctxt);
926 816
927 mutex_unlock(&hfi1_mutex); 817 mutex_unlock(&hfi1_mutex);
928 818
@@ -1230,12 +1120,13 @@ static void user_init(struct hfi1_ctxtdata *uctxt)
1230 hfi1_rcvctrl(uctxt->dd, rcvctrl_ops, uctxt); 1120 hfi1_rcvctrl(uctxt->dd, rcvctrl_ops, uctxt);
1231} 1121}
1232 1122
1233static int get_ctxt_info(struct hfi1_filedata *fd, void __user *ubase, 1123static int get_ctxt_info(struct hfi1_filedata *fd, unsigned long arg, u32 len)
1234 __u32 len)
1235{ 1124{
1236 struct hfi1_ctxt_info cinfo; 1125 struct hfi1_ctxt_info cinfo;
1237 struct hfi1_ctxtdata *uctxt = fd->uctxt; 1126 struct hfi1_ctxtdata *uctxt = fd->uctxt;
1238 int ret = 0; 1127
1128 if (sizeof(cinfo) != len)
1129 return -EINVAL;
1239 1130
1240 memset(&cinfo, 0, sizeof(cinfo)); 1131 memset(&cinfo, 0, sizeof(cinfo));
1241 cinfo.runtime_flags = (((uctxt->flags >> HFI1_CAP_MISC_SHIFT) & 1132 cinfo.runtime_flags = (((uctxt->flags >> HFI1_CAP_MISC_SHIFT) &
@@ -1265,10 +1156,10 @@ static int get_ctxt_info(struct hfi1_filedata *fd, void __user *ubase,
1265 cinfo.rcvegr_size = uctxt->egrbufs.rcvtid_size; 1156 cinfo.rcvegr_size = uctxt->egrbufs.rcvtid_size;
1266 1157
1267 trace_hfi1_ctxt_info(uctxt->dd, uctxt->ctxt, fd->subctxt, cinfo); 1158 trace_hfi1_ctxt_info(uctxt->dd, uctxt->ctxt, fd->subctxt, cinfo);
1268 if (copy_to_user(ubase, &cinfo, sizeof(cinfo))) 1159 if (copy_to_user((void __user *)arg, &cinfo, len))
1269 ret = -EFAULT; 1160 return -EFAULT;
1270 1161
1271 return ret; 1162 return 0;
1272} 1163}
1273 1164
1274static int init_user_ctxt(struct hfi1_filedata *fd, 1165static int init_user_ctxt(struct hfi1_filedata *fd,
@@ -1344,18 +1235,18 @@ done:
1344 return ret; 1235 return ret;
1345} 1236}
1346 1237
1347static int get_base_info(struct hfi1_filedata *fd, void __user *ubase, 1238static int get_base_info(struct hfi1_filedata *fd, unsigned long arg, u32 len)
1348 __u32 len)
1349{ 1239{
1350 struct hfi1_base_info binfo; 1240 struct hfi1_base_info binfo;
1351 struct hfi1_ctxtdata *uctxt = fd->uctxt; 1241 struct hfi1_ctxtdata *uctxt = fd->uctxt;
1352 struct hfi1_devdata *dd = uctxt->dd; 1242 struct hfi1_devdata *dd = uctxt->dd;
1353 ssize_t sz;
1354 unsigned offset; 1243 unsigned offset;
1355 int ret = 0;
1356 1244
1357 trace_hfi1_uctxtdata(uctxt->dd, uctxt, fd->subctxt); 1245 trace_hfi1_uctxtdata(uctxt->dd, uctxt, fd->subctxt);
1358 1246
1247 if (sizeof(binfo) != len)
1248 return -EINVAL;
1249
1359 memset(&binfo, 0, sizeof(binfo)); 1250 memset(&binfo, 0, sizeof(binfo));
1360 binfo.hw_version = dd->revision; 1251 binfo.hw_version = dd->revision;
1361 binfo.sw_version = HFI1_KERN_SWVERSION; 1252 binfo.sw_version = HFI1_KERN_SWVERSION;
@@ -1385,39 +1276,152 @@ static int get_base_info(struct hfi1_filedata *fd, void __user *ubase,
1385 fd->subctxt, 1276 fd->subctxt,
1386 uctxt->egrbufs.rcvtids[0].dma); 1277 uctxt->egrbufs.rcvtids[0].dma);
1387 binfo.sdma_comp_bufbase = HFI1_MMAP_TOKEN(SDMA_COMP, uctxt->ctxt, 1278 binfo.sdma_comp_bufbase = HFI1_MMAP_TOKEN(SDMA_COMP, uctxt->ctxt,
1388 fd->subctxt, 0); 1279 fd->subctxt, 0);
1389 /* 1280 /*
1390 * user regs are at 1281 * user regs are at
1391 * (RXE_PER_CONTEXT_USER + (ctxt * RXE_PER_CONTEXT_SIZE)) 1282 * (RXE_PER_CONTEXT_USER + (ctxt * RXE_PER_CONTEXT_SIZE))
1392 */ 1283 */
1393 binfo.user_regbase = HFI1_MMAP_TOKEN(UREGS, uctxt->ctxt, 1284 binfo.user_regbase = HFI1_MMAP_TOKEN(UREGS, uctxt->ctxt,
1394 fd->subctxt, 0); 1285 fd->subctxt, 0);
1395 offset = offset_in_page((((uctxt->ctxt - dd->first_dyn_alloc_ctxt) * 1286 offset = offset_in_page((uctxt_offset(uctxt) + fd->subctxt) *
1396 HFI1_MAX_SHARED_CTXTS) + fd->subctxt) * 1287 sizeof(*dd->events));
1397 sizeof(*dd->events));
1398 binfo.events_bufbase = HFI1_MMAP_TOKEN(EVENTS, uctxt->ctxt, 1288 binfo.events_bufbase = HFI1_MMAP_TOKEN(EVENTS, uctxt->ctxt,
1399 fd->subctxt, 1289 fd->subctxt,
1400 offset); 1290 offset);
1401 binfo.status_bufbase = HFI1_MMAP_TOKEN(STATUS, uctxt->ctxt, 1291 binfo.status_bufbase = HFI1_MMAP_TOKEN(STATUS, uctxt->ctxt,
1402 fd->subctxt, 1292 fd->subctxt,
1403 dd->status); 1293 dd->status);
1404 if (HFI1_CAP_IS_USET(DMA_RTAIL)) 1294 if (HFI1_CAP_IS_USET(DMA_RTAIL))
1405 binfo.rcvhdrtail_base = HFI1_MMAP_TOKEN(RTAIL, uctxt->ctxt, 1295 binfo.rcvhdrtail_base = HFI1_MMAP_TOKEN(RTAIL, uctxt->ctxt,
1406 fd->subctxt, 0); 1296 fd->subctxt, 0);
1407 if (uctxt->subctxt_cnt) { 1297 if (uctxt->subctxt_cnt) {
1408 binfo.subctxt_uregbase = HFI1_MMAP_TOKEN(SUBCTXT_UREGS, 1298 binfo.subctxt_uregbase = HFI1_MMAP_TOKEN(SUBCTXT_UREGS,
1409 uctxt->ctxt,
1410 fd->subctxt, 0);
1411 binfo.subctxt_rcvhdrbuf = HFI1_MMAP_TOKEN(SUBCTXT_RCV_HDRQ,
1412 uctxt->ctxt, 1299 uctxt->ctxt,
1413 fd->subctxt, 0); 1300 fd->subctxt, 0);
1301 binfo.subctxt_rcvhdrbuf = HFI1_MMAP_TOKEN(SUBCTXT_RCV_HDRQ,
1302 uctxt->ctxt,
1303 fd->subctxt, 0);
1414 binfo.subctxt_rcvegrbuf = HFI1_MMAP_TOKEN(SUBCTXT_EGRBUF, 1304 binfo.subctxt_rcvegrbuf = HFI1_MMAP_TOKEN(SUBCTXT_EGRBUF,
1415 uctxt->ctxt, 1305 uctxt->ctxt,
1416 fd->subctxt, 0); 1306 fd->subctxt, 0);
1417 } 1307 }
1418 sz = (len < sizeof(binfo)) ? len : sizeof(binfo); 1308
1419 if (copy_to_user(ubase, &binfo, sz)) 1309 if (copy_to_user((void __user *)arg, &binfo, len))
1310 return -EFAULT;
1311
1312 return 0;
1313}
1314
1315/**
1316 * user_exp_rcv_setup - Set up the given tid rcv list
1317 * @fd: file data of the current driver instance
1318 * @arg: ioctl argumnent for user space information
1319 * @len: length of data structure associated with ioctl command
1320 *
1321 * Wrapper to validate ioctl information before doing _rcv_setup.
1322 *
1323 */
1324static int user_exp_rcv_setup(struct hfi1_filedata *fd, unsigned long arg,
1325 u32 len)
1326{
1327 int ret;
1328 unsigned long addr;
1329 struct hfi1_tid_info tinfo;
1330
1331 if (sizeof(tinfo) != len)
1332 return -EINVAL;
1333
1334 if (copy_from_user(&tinfo, (void __user *)arg, (sizeof(tinfo))))
1335 return -EFAULT;
1336
1337 ret = hfi1_user_exp_rcv_setup(fd, &tinfo);
1338 if (!ret) {
1339 /*
1340 * Copy the number of tidlist entries we used
1341 * and the length of the buffer we registered.
1342 */
1343 addr = arg + offsetof(struct hfi1_tid_info, tidcnt);
1344 if (copy_to_user((void __user *)addr, &tinfo.tidcnt,
1345 sizeof(tinfo.tidcnt)))
1346 return -EFAULT;
1347
1348 addr = arg + offsetof(struct hfi1_tid_info, length);
1349 if (copy_to_user((void __user *)addr, &tinfo.length,
1350 sizeof(tinfo.length)))
1351 ret = -EFAULT;
1352 }
1353
1354 return ret;
1355}
1356
1357/**
1358 * user_exp_rcv_clear - Clear the given tid rcv list
1359 * @fd: file data of the current driver instance
1360 * @arg: ioctl argumnent for user space information
1361 * @len: length of data structure associated with ioctl command
1362 *
1363 * The hfi1_user_exp_rcv_clear() can be called from the error path. Because
1364 * of this, we need to use this wrapper to copy the user space information
1365 * before doing the clear.
1366 */
1367static int user_exp_rcv_clear(struct hfi1_filedata *fd, unsigned long arg,
1368 u32 len)
1369{
1370 int ret;
1371 unsigned long addr;
1372 struct hfi1_tid_info tinfo;
1373
1374 if (sizeof(tinfo) != len)
1375 return -EINVAL;
1376
1377 if (copy_from_user(&tinfo, (void __user *)arg, (sizeof(tinfo))))
1378 return -EFAULT;
1379
1380 ret = hfi1_user_exp_rcv_clear(fd, &tinfo);
1381 if (!ret) {
1382 addr = arg + offsetof(struct hfi1_tid_info, tidcnt);
1383 if (copy_to_user((void __user *)addr, &tinfo.tidcnt,
1384 sizeof(tinfo.tidcnt)))
1385 return -EFAULT;
1386 }
1387
1388 return ret;
1389}
1390
1391/**
1392 * user_exp_rcv_invalid - Invalidate the given tid rcv list
1393 * @fd: file data of the current driver instance
1394 * @arg: ioctl argumnent for user space information
1395 * @len: length of data structure associated with ioctl command
1396 *
1397 * Wrapper to validate ioctl information before doing _rcv_invalid.
1398 *
1399 */
1400static int user_exp_rcv_invalid(struct hfi1_filedata *fd, unsigned long arg,
1401 u32 len)
1402{
1403 int ret;
1404 unsigned long addr;
1405 struct hfi1_tid_info tinfo;
1406
1407 if (sizeof(tinfo) != len)
1408 return -EINVAL;
1409
1410 if (!fd->invalid_tids)
1411 return -EINVAL;
1412
1413 if (copy_from_user(&tinfo, (void __user *)arg, (sizeof(tinfo))))
1414 return -EFAULT;
1415
1416 ret = hfi1_user_exp_rcv_invalid(fd, &tinfo);
1417 if (ret)
1418 return ret;
1419
1420 addr = arg + offsetof(struct hfi1_tid_info, tidcnt);
1421 if (copy_to_user((void __user *)addr, &tinfo.tidcnt,
1422 sizeof(tinfo.tidcnt)))
1420 ret = -EFAULT; 1423 ret = -EFAULT;
1424
1421 return ret; 1425 return ret;
1422} 1426}
1423 1427
@@ -1485,14 +1489,13 @@ int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit)
1485 ctxt++) { 1489 ctxt++) {
1486 uctxt = hfi1_rcd_get_by_index(dd, ctxt); 1490 uctxt = hfi1_rcd_get_by_index(dd, ctxt);
1487 if (uctxt) { 1491 if (uctxt) {
1488 unsigned long *evs = dd->events + 1492 unsigned long *evs;
1489 (uctxt->ctxt - dd->first_dyn_alloc_ctxt) *
1490 HFI1_MAX_SHARED_CTXTS;
1491 int i; 1493 int i;
1492 /* 1494 /*
1493 * subctxt_cnt is 0 if not shared, so do base 1495 * subctxt_cnt is 0 if not shared, so do base
1494 * separately, first, then remaining subctxt, if any 1496 * separately, first, then remaining subctxt, if any
1495 */ 1497 */
1498 evs = dd->events + uctxt_offset(uctxt);
1496 set_bit(evtbit, evs); 1499 set_bit(evtbit, evs);
1497 for (i = 1; i < uctxt->subctxt_cnt; i++) 1500 for (i = 1; i < uctxt->subctxt_cnt; i++)
1498 set_bit(evtbit, evs + i); 1501 set_bit(evtbit, evs + i);
@@ -1514,13 +1517,18 @@ int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit)
1514 * re-init the software copy of the head register 1517 * re-init the software copy of the head register
1515 */ 1518 */
1516static int manage_rcvq(struct hfi1_ctxtdata *uctxt, u16 subctxt, 1519static int manage_rcvq(struct hfi1_ctxtdata *uctxt, u16 subctxt,
1517 int start_stop) 1520 unsigned long arg)
1518{ 1521{
1519 struct hfi1_devdata *dd = uctxt->dd; 1522 struct hfi1_devdata *dd = uctxt->dd;
1520 unsigned int rcvctrl_op; 1523 unsigned int rcvctrl_op;
1524 int start_stop;
1521 1525
1522 if (subctxt) 1526 if (subctxt)
1523 goto bail; 1527 return 0;
1528
1529 if (get_user(start_stop, (int __user *)arg))
1530 return -EFAULT;
1531
1524 /* atomically clear receive enable ctxt. */ 1532 /* atomically clear receive enable ctxt. */
1525 if (start_stop) { 1533 if (start_stop) {
1526 /* 1534 /*
@@ -1539,7 +1547,7 @@ static int manage_rcvq(struct hfi1_ctxtdata *uctxt, u16 subctxt,
1539 } 1547 }
1540 hfi1_rcvctrl(dd, rcvctrl_op, uctxt); 1548 hfi1_rcvctrl(dd, rcvctrl_op, uctxt);
1541 /* always; new head should be equal to new tail; see above */ 1549 /* always; new head should be equal to new tail; see above */
1542bail: 1550
1543 return 0; 1551 return 0;
1544} 1552}
1545 1553
@@ -1549,17 +1557,20 @@ bail:
1549 * set, if desired, and checks again in future. 1557 * set, if desired, and checks again in future.
1550 */ 1558 */
1551static int user_event_ack(struct hfi1_ctxtdata *uctxt, u16 subctxt, 1559static int user_event_ack(struct hfi1_ctxtdata *uctxt, u16 subctxt,
1552 unsigned long events) 1560 unsigned long arg)
1553{ 1561{
1554 int i; 1562 int i;
1555 struct hfi1_devdata *dd = uctxt->dd; 1563 struct hfi1_devdata *dd = uctxt->dd;
1556 unsigned long *evs; 1564 unsigned long *evs;
1565 unsigned long events;
1557 1566
1558 if (!dd->events) 1567 if (!dd->events)
1559 return 0; 1568 return 0;
1560 1569
1561 evs = dd->events + ((uctxt->ctxt - dd->first_dyn_alloc_ctxt) * 1570 if (get_user(events, (unsigned long __user *)arg))
1562 HFI1_MAX_SHARED_CTXTS) + subctxt; 1571 return -EFAULT;
1572
1573 evs = dd->events + uctxt_offset(uctxt) + subctxt;
1563 1574
1564 for (i = 0; i <= _HFI1_MAX_EVENT_BIT; i++) { 1575 for (i = 0; i <= _HFI1_MAX_EVENT_BIT; i++) {
1565 if (!test_bit(i, &events)) 1576 if (!test_bit(i, &events))
@@ -1569,26 +1580,89 @@ static int user_event_ack(struct hfi1_ctxtdata *uctxt, u16 subctxt,
1569 return 0; 1580 return 0;
1570} 1581}
1571 1582
1572static int set_ctxt_pkey(struct hfi1_ctxtdata *uctxt, u16 subctxt, u16 pkey) 1583static int set_ctxt_pkey(struct hfi1_ctxtdata *uctxt, unsigned long arg)
1573{ 1584{
1574 int ret = -ENOENT, i, intable = 0; 1585 int i;
1575 struct hfi1_pportdata *ppd = uctxt->ppd; 1586 struct hfi1_pportdata *ppd = uctxt->ppd;
1576 struct hfi1_devdata *dd = uctxt->dd; 1587 struct hfi1_devdata *dd = uctxt->dd;
1588 u16 pkey;
1577 1589
1578 if (pkey == LIM_MGMT_P_KEY || pkey == FULL_MGMT_P_KEY) { 1590 if (!HFI1_CAP_IS_USET(PKEY_CHECK))
1579 ret = -EINVAL; 1591 return -EPERM;
1580 goto done; 1592
1581 } 1593 if (get_user(pkey, (u16 __user *)arg))
1594 return -EFAULT;
1595
1596 if (pkey == LIM_MGMT_P_KEY || pkey == FULL_MGMT_P_KEY)
1597 return -EINVAL;
1582 1598
1583 for (i = 0; i < ARRAY_SIZE(ppd->pkeys); i++) 1599 for (i = 0; i < ARRAY_SIZE(ppd->pkeys); i++)
1584 if (pkey == ppd->pkeys[i]) { 1600 if (pkey == ppd->pkeys[i])
1585 intable = 1; 1601 return hfi1_set_ctxt_pkey(dd, uctxt, pkey);
1586 break; 1602
1587 } 1603 return -ENOENT;
1604}
1605
1606/**
1607 * ctxt_reset - Reset the user context
1608 * @uctxt: valid user context
1609 */
1610static int ctxt_reset(struct hfi1_ctxtdata *uctxt)
1611{
1612 struct send_context *sc;
1613 struct hfi1_devdata *dd;
1614 int ret = 0;
1615
1616 if (!uctxt || !uctxt->dd || !uctxt->sc)
1617 return -EINVAL;
1618
1619 /*
1620 * There is no protection here. User level has to guarantee that
1621 * no one will be writing to the send context while it is being
1622 * re-initialized. If user level breaks that guarantee, it will
1623 * break it's own context and no one else's.
1624 */
1625 dd = uctxt->dd;
1626 sc = uctxt->sc;
1627
1628 /*
1629 * Wait until the interrupt handler has marked the context as
1630 * halted or frozen. Report error if we time out.
1631 */
1632 wait_event_interruptible_timeout(
1633 sc->halt_wait, (sc->flags & SCF_HALTED),
1634 msecs_to_jiffies(SEND_CTXT_HALT_TIMEOUT));
1635 if (!(sc->flags & SCF_HALTED))
1636 return -ENOLCK;
1637
1638 /*
1639 * If the send context was halted due to a Freeze, wait until the
1640 * device has been "unfrozen" before resetting the context.
1641 */
1642 if (sc->flags & SCF_FROZEN) {
1643 wait_event_interruptible_timeout(
1644 dd->event_queue,
1645 !(READ_ONCE(dd->flags) & HFI1_FROZEN),
1646 msecs_to_jiffies(SEND_CTXT_HALT_TIMEOUT));
1647 if (dd->flags & HFI1_FROZEN)
1648 return -ENOLCK;
1649
1650 if (dd->flags & HFI1_FORCED_FREEZE)
1651 /*
1652 * Don't allow context reset if we are into
1653 * forced freeze
1654 */
1655 return -ENODEV;
1656
1657 sc_disable(sc);
1658 ret = sc_enable(sc);
1659 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_ENB, uctxt);
1660 } else {
1661 ret = sc_restart(sc);
1662 }
1663 if (!ret)
1664 sc_return_credits(sc);
1588 1665
1589 if (intable)
1590 ret = hfi1_set_ctxt_pkey(dd, uctxt, pkey);
1591done:
1592 return ret; 1666 return ret;
1593} 1667}
1594 1668
diff --git a/drivers/infiniband/hw/hfi1/firmware.c b/drivers/infiniband/hw/hfi1/firmware.c
index 5aea8f47e670..98868df78a7e 100644
--- a/drivers/infiniband/hw/hfi1/firmware.c
+++ b/drivers/infiniband/hw/hfi1/firmware.c
@@ -70,6 +70,11 @@
70#define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw" 70#define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw"
71#define HOST_INTERFACE_VERSION 1 71#define HOST_INTERFACE_VERSION 1
72 72
73MODULE_FIRMWARE(DEFAULT_FW_8051_NAME_ASIC);
74MODULE_FIRMWARE(DEFAULT_FW_FABRIC_NAME);
75MODULE_FIRMWARE(DEFAULT_FW_SBUS_NAME);
76MODULE_FIRMWARE(DEFAULT_FW_PCIE_NAME);
77
73static uint fw_8051_load = 1; 78static uint fw_8051_load = 1;
74static uint fw_fabric_serdes_load = 1; 79static uint fw_fabric_serdes_load = 1;
75static uint fw_pcie_serdes_load = 1; 80static uint fw_pcie_serdes_load = 1;
@@ -113,6 +118,12 @@ struct css_header {
113#define MU_SIZE 8 118#define MU_SIZE 8
114#define EXPONENT_SIZE 4 119#define EXPONENT_SIZE 4
115 120
121/* size of platform configuration partition */
122#define MAX_PLATFORM_CONFIG_FILE_SIZE 4096
123
124/* size of file of plaform configuration encoded in format version 4 */
125#define PLATFORM_CONFIG_FORMAT_4_FILE_SIZE 528
126
116/* the file itself */ 127/* the file itself */
117struct firmware_file { 128struct firmware_file {
118 struct css_header css_header; 129 struct css_header css_header;
@@ -965,6 +976,46 @@ int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout)
965} 976}
966 977
967/* 978/*
979 * Clear all reset bits, releasing the 8051.
980 * Wait for firmware to be ready to accept host requests.
981 * Then, set host version bit.
982 *
983 * This function executes even if the 8051 is in reset mode when
984 * dd->dc_shutdown == 1.
985 *
986 * Expects dd->dc8051_lock to be held.
987 */
988int release_and_wait_ready_8051_firmware(struct hfi1_devdata *dd)
989{
990 int ret;
991
992 lockdep_assert_held(&dd->dc8051_lock);
993 /* clear all reset bits, releasing the 8051 */
994 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
995
996 /*
997 * Wait for firmware to be ready to accept host
998 * requests.
999 */
1000 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
1001 if (ret) {
1002 dd_dev_err(dd, "8051 start timeout, current FW state 0x%x\n",
1003 get_firmware_state(dd));
1004 return ret;
1005 }
1006
1007 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION);
1008 if (ret != HCMD_SUCCESS) {
1009 dd_dev_err(dd,
1010 "Failed to set host interface version, return 0x%x\n",
1011 ret);
1012 return -EIO;
1013 }
1014
1015 return 0;
1016}
1017
1018/*
968 * Load the 8051 firmware. 1019 * Load the 8051 firmware.
969 */ 1020 */
970static int load_8051_firmware(struct hfi1_devdata *dd, 1021static int load_8051_firmware(struct hfi1_devdata *dd,
@@ -1029,31 +1080,22 @@ static int load_8051_firmware(struct hfi1_devdata *dd,
1029 if (ret) 1080 if (ret)
1030 return ret; 1081 return ret;
1031 1082
1032 /* clear all reset bits, releasing the 8051 */
1033 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
1034
1035 /* 1083 /*
1084 * Clear all reset bits, releasing the 8051.
1036 * DC reset step 5. Wait for firmware to be ready to accept host 1085 * DC reset step 5. Wait for firmware to be ready to accept host
1037 * requests. 1086 * requests.
1087 * Then, set host version bit.
1038 */ 1088 */
1039 ret = wait_fm_ready(dd, TIMEOUT_8051_START); 1089 mutex_lock(&dd->dc8051_lock);
1040 if (ret) { /* timed out */ 1090 ret = release_and_wait_ready_8051_firmware(dd);
1041 dd_dev_err(dd, "8051 start timeout, current state 0x%x\n", 1091 mutex_unlock(&dd->dc8051_lock);
1042 get_firmware_state(dd)); 1092 if (ret)
1043 return -ETIMEDOUT; 1093 return ret;
1044 }
1045 1094
1046 read_misc_status(dd, &ver_major, &ver_minor, &ver_patch); 1095 read_misc_status(dd, &ver_major, &ver_minor, &ver_patch);
1047 dd_dev_info(dd, "8051 firmware version %d.%d.%d\n", 1096 dd_dev_info(dd, "8051 firmware version %d.%d.%d\n",
1048 (int)ver_major, (int)ver_minor, (int)ver_patch); 1097 (int)ver_major, (int)ver_minor, (int)ver_patch);
1049 dd->dc8051_ver = dc8051_ver(ver_major, ver_minor, ver_patch); 1098 dd->dc8051_ver = dc8051_ver(ver_major, ver_minor, ver_patch);
1050 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION);
1051 if (ret != HCMD_SUCCESS) {
1052 dd_dev_err(dd,
1053 "Failed to set host interface version, return 0x%x\n",
1054 ret);
1055 return -EIO;
1056 }
1057 1099
1058 return 0; 1100 return 0;
1059} 1101}
@@ -1387,7 +1429,14 @@ int acquire_hw_mutex(struct hfi1_devdata *dd)
1387 unsigned long timeout; 1429 unsigned long timeout;
1388 int try = 0; 1430 int try = 0;
1389 u8 mask = 1 << dd->hfi1_id; 1431 u8 mask = 1 << dd->hfi1_id;
1390 u8 user; 1432 u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1433
1434 if (user == mask) {
1435 dd_dev_info(dd,
1436 "Hardware mutex already acquired, mutex mask %u\n",
1437 (u32)mask);
1438 return 0;
1439 }
1391 1440
1392retry: 1441retry:
1393 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies; 1442 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies;
@@ -1418,7 +1467,15 @@ retry:
1418 1467
1419void release_hw_mutex(struct hfi1_devdata *dd) 1468void release_hw_mutex(struct hfi1_devdata *dd)
1420{ 1469{
1421 write_csr(dd, ASIC_CFG_MUTEX, 0); 1470 u8 mask = 1 << dd->hfi1_id;
1471 u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1472
1473 if (user != mask)
1474 dd_dev_warn(dd,
1475 "Unable to release hardware mutex, mutex mask %u, my mask %u\n",
1476 (u32)user, (u32)mask);
1477 else
1478 write_csr(dd, ASIC_CFG_MUTEX, 0);
1422} 1479}
1423 1480
1424/* return the given resource bit(s) as a mask for the given HFI */ 1481/* return the given resource bit(s) as a mask for the given HFI */
@@ -1733,7 +1790,7 @@ static int check_meta_version(struct hfi1_devdata *dd, u32 *system_table)
1733 ver_start /= 8; 1790 ver_start /= 8;
1734 meta_ver = *((u8 *)system_table + ver_start) & ((1 << ver_len) - 1); 1791 meta_ver = *((u8 *)system_table + ver_start) & ((1 << ver_len) - 1);
1735 1792
1736 if (meta_ver < 5) { 1793 if (meta_ver < 4) {
1737 dd_dev_info( 1794 dd_dev_info(
1738 dd, "%s:Please update platform config\n", __func__); 1795 dd, "%s:Please update platform config\n", __func__);
1739 return -EINVAL; 1796 return -EINVAL;
@@ -1774,7 +1831,20 @@ int parse_platform_config(struct hfi1_devdata *dd)
1774 1831
1775 /* Field is file size in DWORDs */ 1832 /* Field is file size in DWORDs */
1776 file_length = (*ptr) * 4; 1833 file_length = (*ptr) * 4;
1777 ptr++; 1834
1835 /*
1836 * Length can't be larger than partition size. Assume platform
1837 * config format version 4 is being used. Interpret the file size
1838 * field as header instead by not moving the pointer.
1839 */
1840 if (file_length > MAX_PLATFORM_CONFIG_FILE_SIZE) {
1841 dd_dev_info(dd,
1842 "%s:File length out of bounds, using alternative format\n",
1843 __func__);
1844 file_length = PLATFORM_CONFIG_FORMAT_4_FILE_SIZE;
1845 } else {
1846 ptr++;
1847 }
1778 1848
1779 if (file_length > dd->platform_config.size) { 1849 if (file_length > dd->platform_config.size) {
1780 dd_dev_info(dd, "%s:File claims to be larger than read size\n", 1850 dd_dev_info(dd, "%s:File claims to be larger than read size\n",
@@ -1789,7 +1859,8 @@ int parse_platform_config(struct hfi1_devdata *dd)
1789 1859
1790 /* 1860 /*
1791 * In both cases where we proceed, using the self-reported file length 1861 * In both cases where we proceed, using the self-reported file length
1792 * is the safer option 1862 * is the safer option. In case of old format a predefined value is
1863 * being used.
1793 */ 1864 */
1794 while (ptr < (u32 *)(dd->platform_config.data + file_length)) { 1865 while (ptr < (u32 *)(dd->platform_config.data + file_length)) {
1795 header1 = *ptr; 1866 header1 = *ptr;
diff --git a/drivers/infiniband/hw/hfi1/hfi.h b/drivers/infiniband/hw/hfi1/hfi.h
index 3ac9c307a285..4a9b4d7efe63 100644
--- a/drivers/infiniband/hw/hfi1/hfi.h
+++ b/drivers/infiniband/hw/hfi1/hfi.h
@@ -95,6 +95,9 @@
95#define DROP_PACKET_OFF 0 95#define DROP_PACKET_OFF 0
96#define DROP_PACKET_ON 1 96#define DROP_PACKET_ON 1
97 97
98#define NEIGHBOR_TYPE_HFI 0
99#define NEIGHBOR_TYPE_SWITCH 1
100
98extern unsigned long hfi1_cap_mask; 101extern unsigned long hfi1_cap_mask;
99#define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) 102#define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
100#define HFI1_CAP_UGET_MASK(mask, cap) \ 103#define HFI1_CAP_UGET_MASK(mask, cap) \
@@ -164,9 +167,7 @@ extern const struct pci_error_handlers hfi1_pci_err_handler;
164 * Below contains all data related to a single context (formerly called port). 167 * Below contains all data related to a single context (formerly called port).
165 */ 168 */
166 169
167#ifdef CONFIG_DEBUG_FS
168struct hfi1_opcode_stats_perctx; 170struct hfi1_opcode_stats_perctx;
169#endif
170 171
171struct ctxt_eager_bufs { 172struct ctxt_eager_bufs {
172 ssize_t size; /* total size of eager buffers */ 173 ssize_t size; /* total size of eager buffers */
@@ -283,7 +284,7 @@ struct hfi1_ctxtdata {
283 u64 imask; /* clear interrupt mask */ 284 u64 imask; /* clear interrupt mask */
284 int ireg; /* clear interrupt register */ 285 int ireg; /* clear interrupt register */
285 unsigned numa_id; /* numa node of this context */ 286 unsigned numa_id; /* numa node of this context */
286 /* verbs stats per CTX */ 287 /* verbs rx_stats per rcd */
287 struct hfi1_opcode_stats_perctx *opstats; 288 struct hfi1_opcode_stats_perctx *opstats;
288 289
289 /* Is ASPM interrupt supported for this context */ 290 /* Is ASPM interrupt supported for this context */
@@ -390,6 +391,7 @@ struct hfi1_packet {
390/* 391/*
391 * OPA 16B L2/L4 Encodings 392 * OPA 16B L2/L4 Encodings
392 */ 393 */
394#define OPA_16B_L4_9B 0x00
393#define OPA_16B_L2_TYPE 0x02 395#define OPA_16B_L2_TYPE 0x02
394#define OPA_16B_L4_IB_LOCAL 0x09 396#define OPA_16B_L4_IB_LOCAL 0x09
395#define OPA_16B_L4_IB_GLOBAL 0x0A 397#define OPA_16B_L4_IB_GLOBAL 0x0A
@@ -535,6 +537,8 @@ struct rvt_sge_state;
535#define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE) 537#define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
536#define HLS_DOWN ~(HLS_UP) 538#define HLS_DOWN ~(HLS_UP)
537 539
540#define HLS_DEFAULT HLS_DN_POLL
541
538/* use this MTU size if none other is given */ 542/* use this MTU size if none other is given */
539#define HFI1_DEFAULT_ACTIVE_MTU 10240 543#define HFI1_DEFAULT_ACTIVE_MTU 10240
540/* use this MTU size as the default maximum */ 544/* use this MTU size as the default maximum */
@@ -616,7 +620,6 @@ struct hfi1_msix_entry {
616 enum irq_type type; 620 enum irq_type type;
617 int irq; 621 int irq;
618 void *arg; 622 void *arg;
619 char name[MAX_NAME_SIZE];
620 cpumask_t mask; 623 cpumask_t mask;
621 struct irq_affinity_notify notify; 624 struct irq_affinity_notify notify;
622}; 625};
@@ -1047,6 +1050,8 @@ struct hfi1_devdata {
1047 u64 z_send_schedule; 1050 u64 z_send_schedule;
1048 1051
1049 u64 __percpu *send_schedule; 1052 u64 __percpu *send_schedule;
1053 /* number of reserved contexts for VNIC usage */
1054 u16 num_vnic_contexts;
1050 /* number of receive contexts in use by the driver */ 1055 /* number of receive contexts in use by the driver */
1051 u32 num_rcv_contexts; 1056 u32 num_rcv_contexts;
1052 /* number of pio send contexts in use by the driver */ 1057 /* number of pio send contexts in use by the driver */
@@ -1109,8 +1114,7 @@ struct hfi1_devdata {
1109 u16 rcvegrbufsize_shift; 1114 u16 rcvegrbufsize_shift;
1110 /* both sides of the PCIe link are gen3 capable */ 1115 /* both sides of the PCIe link are gen3 capable */
1111 u8 link_gen3_capable; 1116 u8 link_gen3_capable;
1112 /* default link down value (poll/sleep) */ 1117 u8 dc_shutdown;
1113 u8 link_default;
1114 /* localbus width (1, 2,4,8,16,32) from config space */ 1118 /* localbus width (1, 2,4,8,16,32) from config space */
1115 u32 lbus_width; 1119 u32 lbus_width;
1116 /* localbus speed in MHz */ 1120 /* localbus speed in MHz */
@@ -1183,7 +1187,6 @@ struct hfi1_devdata {
1183 1187
1184 /* INTx information */ 1188 /* INTx information */
1185 u32 requested_intx_irq; /* did we request one? */ 1189 u32 requested_intx_irq; /* did we request one? */
1186 char intx_name[MAX_NAME_SIZE]; /* INTx name */
1187 1190
1188 /* general interrupt: mask of handled interrupts */ 1191 /* general interrupt: mask of handled interrupts */
1189 u64 gi_mask[CCE_NUM_INT_CSRS]; 1192 u64 gi_mask[CCE_NUM_INT_CSRS];
@@ -1274,6 +1277,8 @@ struct hfi1_devdata {
1274 /* receive context data */ 1277 /* receive context data */
1275 struct hfi1_ctxtdata **rcd; 1278 struct hfi1_ctxtdata **rcd;
1276 u64 __percpu *int_counter; 1279 u64 __percpu *int_counter;
1280 /* verbs tx opcode stats */
1281 struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
1277 /* device (not port) flags, basically device capabilities */ 1282 /* device (not port) flags, basically device capabilities */
1278 u16 flags; 1283 u16 flags;
1279 /* Number of physical ports available */ 1284 /* Number of physical ports available */
@@ -1295,7 +1300,6 @@ struct hfi1_devdata {
1295 u8 oui1; 1300 u8 oui1;
1296 u8 oui2; 1301 u8 oui2;
1297 u8 oui3; 1302 u8 oui3;
1298 u8 dc_shutdown;
1299 1303
1300 /* Timer and counter used to detect RcvBufOvflCnt changes */ 1304 /* Timer and counter used to detect RcvBufOvflCnt changes */
1301 struct timer_list rcverr_timer; 1305 struct timer_list rcverr_timer;
@@ -1373,8 +1377,12 @@ struct hfi1_filedata {
1373extern struct list_head hfi1_dev_list; 1377extern struct list_head hfi1_dev_list;
1374extern spinlock_t hfi1_devs_lock; 1378extern spinlock_t hfi1_devs_lock;
1375struct hfi1_devdata *hfi1_lookup(int unit); 1379struct hfi1_devdata *hfi1_lookup(int unit);
1376extern u32 hfi1_cpulist_count; 1380
1377extern unsigned long *hfi1_cpulist; 1381static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1382{
1383 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1384 HFI1_MAX_SHARED_CTXTS;
1385}
1378 1386
1379int hfi1_init(struct hfi1_devdata *dd, int reinit); 1387int hfi1_init(struct hfi1_devdata *dd, int reinit);
1380int hfi1_count_active_units(void); 1388int hfi1_count_active_units(void);
@@ -1396,6 +1404,8 @@ void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1396void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd); 1404void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1397int hfi1_rcd_put(struct hfi1_ctxtdata *rcd); 1405int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1398void hfi1_rcd_get(struct hfi1_ctxtdata *rcd); 1406void hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1407struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1408 u16 ctxt);
1399struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt); 1409struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1400int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread); 1410int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1401int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread); 1411int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
@@ -1531,11 +1541,6 @@ typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1531 u32 remote_qpn, u32 pkey, u32 slid, u32 dlid, 1541 u32 remote_qpn, u32 pkey, u32 slid, u32 dlid,
1532 u8 sc5, const struct ib_grh *old_grh); 1542 u8 sc5, const struct ib_grh *old_grh);
1533 1543
1534/* We support only two types - 9B and 16B for now */
1535static const hfi1_handle_cnp hfi1_handle_cnp_tbl[2] = {
1536 [HFI1_PKT_TYPE_9B] = &return_cnp,
1537 [HFI1_PKT_TYPE_16B] = &return_cnp_16B
1538};
1539#define PKEY_CHECK_INVALID -1 1544#define PKEY_CHECK_INVALID -1
1540int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey, 1545int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1541 u8 sc5, int8_t s_pkey_index); 1546 u8 sc5, int8_t s_pkey_index);
diff --git a/drivers/infiniband/hw/hfi1/init.c b/drivers/infiniband/hw/hfi1/init.c
index fba77001c3a7..8e3b3e7d829a 100644
--- a/drivers/infiniband/hw/hfi1/init.c
+++ b/drivers/infiniband/hw/hfi1/init.c
@@ -123,8 +123,6 @@ MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user
123static inline u64 encode_rcv_header_entry_size(u16 size); 123static inline u64 encode_rcv_header_entry_size(u16 size);
124 124
125static struct idr hfi1_unit_table; 125static struct idr hfi1_unit_table;
126u32 hfi1_cpulist_count;
127unsigned long *hfi1_cpulist;
128 126
129static int hfi1_create_kctxt(struct hfi1_devdata *dd, 127static int hfi1_create_kctxt(struct hfi1_devdata *dd,
130 struct hfi1_pportdata *ppd) 128 struct hfi1_pportdata *ppd)
@@ -286,6 +284,27 @@ static int allocate_rcd_index(struct hfi1_devdata *dd,
286} 284}
287 285
288/** 286/**
287 * hfi1_rcd_get_by_index_safe - validate the ctxt index before accessing the
288 * array
289 * @dd: pointer to a valid devdata structure
290 * @ctxt: the index of an possilbe rcd
291 *
292 * This is a wrapper for hfi1_rcd_get_by_index() to validate that the given
293 * ctxt index is valid.
294 *
295 * The caller is responsible for making the _put().
296 *
297 */
298struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
299 u16 ctxt)
300{
301 if (ctxt < dd->num_rcv_contexts)
302 return hfi1_rcd_get_by_index(dd, ctxt);
303
304 return NULL;
305}
306
307/**
289 * hfi1_rcd_get_by_index 308 * hfi1_rcd_get_by_index
290 * @dd: pointer to a valid devdata structure 309 * @dd: pointer to a valid devdata structure
291 * @ctxt: the index of an possilbe rcd 310 * @ctxt: the index of an possilbe rcd
@@ -1006,7 +1025,7 @@ static void stop_timers(struct hfi1_devdata *dd)
1006 1025
1007 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1026 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1008 ppd = dd->pport + pidx; 1027 ppd = dd->pport + pidx;
1009 if (ppd->led_override_timer.data) { 1028 if (ppd->led_override_timer.function) {
1010 del_timer_sync(&ppd->led_override_timer); 1029 del_timer_sync(&ppd->led_override_timer);
1011 atomic_set(&ppd->led_override_timer_active, 0); 1030 atomic_set(&ppd->led_override_timer_active, 0);
1012 } 1031 }
@@ -1198,6 +1217,7 @@ static void __hfi1_free_devdata(struct kobject *kobj)
1198 free_percpu(dd->int_counter); 1217 free_percpu(dd->int_counter);
1199 free_percpu(dd->rcv_limit); 1218 free_percpu(dd->rcv_limit);
1200 free_percpu(dd->send_schedule); 1219 free_percpu(dd->send_schedule);
1220 free_percpu(dd->tx_opstats);
1201 rvt_dealloc_device(&dd->verbs_dev.rdi); 1221 rvt_dealloc_device(&dd->verbs_dev.rdi);
1202} 1222}
1203 1223
@@ -1272,39 +1292,27 @@ struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra)
1272 dd->int_counter = alloc_percpu(u64); 1292 dd->int_counter = alloc_percpu(u64);
1273 if (!dd->int_counter) { 1293 if (!dd->int_counter) {
1274 ret = -ENOMEM; 1294 ret = -ENOMEM;
1275 hfi1_early_err(&pdev->dev,
1276 "Could not allocate per-cpu int_counter\n");
1277 goto bail; 1295 goto bail;
1278 } 1296 }
1279 1297
1280 dd->rcv_limit = alloc_percpu(u64); 1298 dd->rcv_limit = alloc_percpu(u64);
1281 if (!dd->rcv_limit) { 1299 if (!dd->rcv_limit) {
1282 ret = -ENOMEM; 1300 ret = -ENOMEM;
1283 hfi1_early_err(&pdev->dev,
1284 "Could not allocate per-cpu rcv_limit\n");
1285 goto bail; 1301 goto bail;
1286 } 1302 }
1287 1303
1288 dd->send_schedule = alloc_percpu(u64); 1304 dd->send_schedule = alloc_percpu(u64);
1289 if (!dd->send_schedule) { 1305 if (!dd->send_schedule) {
1290 ret = -ENOMEM; 1306 ret = -ENOMEM;
1291 hfi1_early_err(&pdev->dev,
1292 "Could not allocate per-cpu int_counter\n");
1293 goto bail; 1307 goto bail;
1294 } 1308 }
1295 1309
1296 if (!hfi1_cpulist_count) { 1310 dd->tx_opstats = alloc_percpu(struct hfi1_opcode_stats_perctx);
1297 u32 count = num_online_cpus(); 1311 if (!dd->tx_opstats) {
1298 1312 ret = -ENOMEM;
1299 hfi1_cpulist = kcalloc(BITS_TO_LONGS(count), sizeof(long), 1313 goto bail;
1300 GFP_KERNEL);
1301 if (hfi1_cpulist)
1302 hfi1_cpulist_count = count;
1303 else
1304 hfi1_early_err(
1305 &pdev->dev,
1306 "Could not alloc cpulist info, cpu affinity might be wrong\n");
1307 } 1314 }
1315
1308 kobject_init(&dd->kobj, &hfi1_devdata_type); 1316 kobject_init(&dd->kobj, &hfi1_devdata_type);
1309 return dd; 1317 return dd;
1310 1318
@@ -1477,8 +1485,6 @@ static void __exit hfi1_mod_cleanup(void)
1477 node_affinity_destroy(); 1485 node_affinity_destroy();
1478 hfi1_wss_exit(); 1486 hfi1_wss_exit();
1479 hfi1_dbg_exit(); 1487 hfi1_dbg_exit();
1480 hfi1_cpulist_count = 0;
1481 kfree(hfi1_cpulist);
1482 1488
1483 idr_destroy(&hfi1_unit_table); 1489 idr_destroy(&hfi1_unit_table);
1484 dispose_firmware(); /* asymmetric with obtain_firmware() */ 1490 dispose_firmware(); /* asymmetric with obtain_firmware() */
@@ -1801,8 +1807,7 @@ int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1801 amt = PAGE_ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize * 1807 amt = PAGE_ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize *
1802 sizeof(u32)); 1808 sizeof(u32));
1803 1809
1804 if ((rcd->ctxt < dd->first_dyn_alloc_ctxt) || 1810 if (rcd->ctxt < dd->first_dyn_alloc_ctxt || rcd->is_vnic)
1805 (rcd->sc && (rcd->sc->type == SC_KERNEL)))
1806 gfp_flags = GFP_KERNEL; 1811 gfp_flags = GFP_KERNEL;
1807 else 1812 else
1808 gfp_flags = GFP_USER; 1813 gfp_flags = GFP_USER;
diff --git a/drivers/infiniband/hw/hfi1/intr.c b/drivers/infiniband/hw/hfi1/intr.c
index 96845dfed5c5..387305b768e9 100644
--- a/drivers/infiniband/hw/hfi1/intr.c
+++ b/drivers/infiniband/hw/hfi1/intr.c
@@ -53,6 +53,42 @@
53#include "common.h" 53#include "common.h"
54#include "sdma.h" 54#include "sdma.h"
55 55
56#define LINK_UP_DELAY 500 /* in microseconds */
57
58static void set_mgmt_allowed(struct hfi1_pportdata *ppd)
59{
60 u32 frame;
61 struct hfi1_devdata *dd = ppd->dd;
62
63 if (ppd->neighbor_type == NEIGHBOR_TYPE_HFI) {
64 ppd->mgmt_allowed = 1;
65 } else {
66 read_8051_config(dd, REMOTE_LNI_INFO, GENERAL_CONFIG, &frame);
67 ppd->mgmt_allowed = (frame >> MGMT_ALLOWED_SHIFT)
68 & MGMT_ALLOWED_MASK;
69 }
70}
71
72/*
73 * Our neighbor has indicated that we are allowed to act as a fabric
74 * manager, so place the full management partition key in the second
75 * (0-based) pkey array position. Note that we should already have
76 * the limited management partition key in array element 1, and also
77 * that the port is not yet up when add_full_mgmt_pkey() is invoked.
78 */
79static void add_full_mgmt_pkey(struct hfi1_pportdata *ppd)
80{
81 struct hfi1_devdata *dd = ppd->dd;
82
83 /* Sanity check - ppd->pkeys[2] should be 0, or already initialized */
84 if (!((ppd->pkeys[2] == 0) || (ppd->pkeys[2] == FULL_MGMT_P_KEY)))
85 dd_dev_warn(dd, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
86 __func__, ppd->pkeys[2], FULL_MGMT_P_KEY);
87 ppd->pkeys[2] = FULL_MGMT_P_KEY;
88 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
89 hfi1_event_pkey_change(ppd->dd, ppd->port);
90}
91
56/** 92/**
57 * format_hwmsg - format a single hwerror message 93 * format_hwmsg - format a single hwerror message
58 * @msg message buffer 94 * @msg message buffer
@@ -102,9 +138,16 @@ static void signal_ib_event(struct hfi1_pportdata *ppd, enum ib_event_type ev)
102 ib_dispatch_event(&event); 138 ib_dispatch_event(&event);
103} 139}
104 140
105/* 141/**
142 * handle_linkup_change - finish linkup/down state changes
143 * @dd: valid device
144 * @linkup: link state information
145 *
106 * Handle a linkup or link down notification. 146 * Handle a linkup or link down notification.
147 * The HW needs time to finish its link up state change. Give it that chance.
148 *
107 * This is called outside an interrupt. 149 * This is called outside an interrupt.
150 *
108 */ 151 */
109void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup) 152void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup)
110{ 153{
@@ -151,6 +194,18 @@ void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup)
151 ppd->neighbor_guid, ppd->neighbor_type, 194 ppd->neighbor_guid, ppd->neighbor_type,
152 ppd->neighbor_port_number); 195 ppd->neighbor_port_number);
153 196
197 /* HW needs LINK_UP_DELAY to settle, give it that chance */
198 udelay(LINK_UP_DELAY);
199
200 /*
201 * 'MgmtAllowed' information, which is exchanged during
202 * LNI, is available at this point.
203 */
204 set_mgmt_allowed(ppd);
205
206 if (ppd->mgmt_allowed)
207 add_full_mgmt_pkey(ppd);
208
154 /* physical link went up */ 209 /* physical link went up */
155 ppd->linkup = 1; 210 ppd->linkup = 1;
156 ppd->offline_disabled_reason = 211 ppd->offline_disabled_reason =
diff --git a/drivers/infiniband/hw/hfi1/mad.c b/drivers/infiniband/hw/hfi1/mad.c
index f4c0ffc040cc..cf8dba34fe30 100644
--- a/drivers/infiniband/hw/hfi1/mad.c
+++ b/drivers/infiniband/hw/hfi1/mad.c
@@ -98,6 +98,16 @@ static inline void clear_opa_smp_data(struct opa_smp *smp)
98 memset(data, 0, size); 98 memset(data, 0, size);
99} 99}
100 100
101static u16 hfi1_lookup_pkey_value(struct hfi1_ibport *ibp, int pkey_idx)
102{
103 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
104
105 if (pkey_idx < ARRAY_SIZE(ppd->pkeys))
106 return ppd->pkeys[pkey_idx];
107
108 return 0;
109}
110
101void hfi1_event_pkey_change(struct hfi1_devdata *dd, u8 port) 111void hfi1_event_pkey_change(struct hfi1_devdata *dd, u8 port)
102{ 112{
103 struct ib_event event; 113 struct ib_event event;
@@ -399,9 +409,9 @@ static void send_trap(struct hfi1_ibport *ibp, struct trap_node *trap)
399 ib_free_send_mad(send_buf); 409 ib_free_send_mad(send_buf);
400} 410}
401 411
402void hfi1_handle_trap_timer(unsigned long data) 412void hfi1_handle_trap_timer(struct timer_list *t)
403{ 413{
404 struct hfi1_ibport *ibp = (struct hfi1_ibport *)data; 414 struct hfi1_ibport *ibp = from_timer(ibp, t, rvp.trap_timer);
405 struct trap_node *trap = NULL; 415 struct trap_node *trap = NULL;
406 unsigned long flags; 416 unsigned long flags;
407 int i; 417 int i;
@@ -711,6 +721,7 @@ static int check_mkey(struct hfi1_ibport *ibp, struct ib_mad_hdr *mad,
711 /* Bad mkey not a violation below level 2 */ 721 /* Bad mkey not a violation below level 2 */
712 if (ibp->rvp.mkeyprot < 2) 722 if (ibp->rvp.mkeyprot < 2)
713 break; 723 break;
724 /* fall through */
714 case IB_MGMT_METHOD_SET: 725 case IB_MGMT_METHOD_SET:
715 case IB_MGMT_METHOD_TRAP_REPRESS: 726 case IB_MGMT_METHOD_TRAP_REPRESS:
716 if (ibp->rvp.mkey_violations != 0xFFFF) 727 if (ibp->rvp.mkey_violations != 0xFFFF)
@@ -1227,8 +1238,7 @@ static int port_states_transition_allowed(struct hfi1_pportdata *ppd,
1227} 1238}
1228 1239
1229static int set_port_states(struct hfi1_pportdata *ppd, struct opa_smp *smp, 1240static int set_port_states(struct hfi1_pportdata *ppd, struct opa_smp *smp,
1230 u32 logical_state, u32 phys_state, 1241 u32 logical_state, u32 phys_state)
1231 int suppress_idle_sma)
1232{ 1242{
1233 struct hfi1_devdata *dd = ppd->dd; 1243 struct hfi1_devdata *dd = ppd->dd;
1234 u32 link_state; 1244 u32 link_state;
@@ -1309,7 +1319,7 @@ static int set_port_states(struct hfi1_pportdata *ppd, struct opa_smp *smp,
1309 break; 1319 break;
1310 case IB_PORT_ARMED: 1320 case IB_PORT_ARMED:
1311 ret = set_link_state(ppd, HLS_UP_ARMED); 1321 ret = set_link_state(ppd, HLS_UP_ARMED);
1312 if ((ret == 0) && (suppress_idle_sma == 0)) 1322 if (!ret)
1313 send_idle_sma(dd, SMA_IDLE_ARM); 1323 send_idle_sma(dd, SMA_IDLE_ARM);
1314 break; 1324 break;
1315 case IB_PORT_ACTIVE: 1325 case IB_PORT_ACTIVE:
@@ -1603,8 +1613,10 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
1603 if (ls_new == ls_old || (ls_new == IB_PORT_ARMED)) 1613 if (ls_new == ls_old || (ls_new == IB_PORT_ARMED))
1604 ppd->is_sm_config_started = 1; 1614 ppd->is_sm_config_started = 1;
1605 } else if (ls_new == IB_PORT_ARMED) { 1615 } else if (ls_new == IB_PORT_ARMED) {
1606 if (ppd->is_sm_config_started == 0) 1616 if (ppd->is_sm_config_started == 0) {
1607 invalid = 1; 1617 invalid = 1;
1618 smp->status |= IB_SMP_INVALID_FIELD;
1619 }
1608 } 1620 }
1609 } 1621 }
1610 1622
@@ -1621,9 +1633,11 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
1621 * is down or is being set to down. 1633 * is down or is being set to down.
1622 */ 1634 */
1623 1635
1624 ret = set_port_states(ppd, smp, ls_new, ps_new, invalid); 1636 if (!invalid) {
1625 if (ret) 1637 ret = set_port_states(ppd, smp, ls_new, ps_new);
1626 return ret; 1638 if (ret)
1639 return ret;
1640 }
1627 1641
1628 ret = __subn_get_opa_portinfo(smp, am, data, ibdev, port, resp_len, 1642 ret = __subn_get_opa_portinfo(smp, am, data, ibdev, port, resp_len,
1629 max_len); 1643 max_len);
@@ -2100,17 +2114,18 @@ static int __subn_set_opa_psi(struct opa_smp *smp, u32 am, u8 *data,
2100 if (ls_new == ls_old || (ls_new == IB_PORT_ARMED)) 2114 if (ls_new == ls_old || (ls_new == IB_PORT_ARMED))
2101 ppd->is_sm_config_started = 1; 2115 ppd->is_sm_config_started = 1;
2102 } else if (ls_new == IB_PORT_ARMED) { 2116 } else if (ls_new == IB_PORT_ARMED) {
2103 if (ppd->is_sm_config_started == 0) 2117 if (ppd->is_sm_config_started == 0) {
2104 invalid = 1; 2118 invalid = 1;
2119 smp->status |= IB_SMP_INVALID_FIELD;
2120 }
2105 } 2121 }
2106 } 2122 }
2107 2123
2108 ret = set_port_states(ppd, smp, ls_new, ps_new, invalid); 2124 if (!invalid) {
2109 if (ret) 2125 ret = set_port_states(ppd, smp, ls_new, ps_new);
2110 return ret; 2126 if (ret)
2111 2127 return ret;
2112 if (invalid) 2128 }
2113 smp->status |= IB_SMP_INVALID_FIELD;
2114 2129
2115 return __subn_get_opa_psi(smp, am, data, ibdev, port, resp_len, 2130 return __subn_get_opa_psi(smp, am, data, ibdev, port, resp_len,
2116 max_len); 2131 max_len);
@@ -2888,7 +2903,6 @@ static int pma_get_opa_datacounters(struct opa_pma_mad *pmp,
2888 struct _vls_dctrs *vlinfo; 2903 struct _vls_dctrs *vlinfo;
2889 size_t response_data_size; 2904 size_t response_data_size;
2890 u32 num_ports; 2905 u32 num_ports;
2891 u8 num_pslm;
2892 u8 lq, num_vls; 2906 u8 lq, num_vls;
2893 u8 res_lli, res_ler; 2907 u8 res_lli, res_ler;
2894 u64 port_mask; 2908 u64 port_mask;
@@ -2898,7 +2912,6 @@ static int pma_get_opa_datacounters(struct opa_pma_mad *pmp,
2898 int vfi; 2912 int vfi;
2899 2913
2900 num_ports = be32_to_cpu(pmp->mad_hdr.attr_mod) >> 24; 2914 num_ports = be32_to_cpu(pmp->mad_hdr.attr_mod) >> 24;
2901 num_pslm = hweight64(be64_to_cpu(req->port_select_mask[3]));
2902 num_vls = hweight32(be32_to_cpu(req->vl_select_mask)); 2915 num_vls = hweight32(be32_to_cpu(req->vl_select_mask));
2903 vl_select_mask = be32_to_cpu(req->vl_select_mask); 2916 vl_select_mask = be32_to_cpu(req->vl_select_mask);
2904 res_lli = (u8)(be32_to_cpu(req->resolution) & MSK_LLI) >> MSK_LLI_SFT; 2917 res_lli = (u8)(be32_to_cpu(req->resolution) & MSK_LLI) >> MSK_LLI_SFT;
@@ -3688,7 +3701,11 @@ static void apply_cc_state(struct hfi1_pportdata *ppd)
3688 3701
3689 *new_cc_state = *old_cc_state; 3702 *new_cc_state = *old_cc_state;
3690 3703
3691 new_cc_state->cct.ccti_limit = ppd->total_cct_entry - 1; 3704 if (ppd->total_cct_entry)
3705 new_cc_state->cct.ccti_limit = ppd->total_cct_entry - 1;
3706 else
3707 new_cc_state->cct.ccti_limit = 0;
3708
3692 memcpy(new_cc_state->cct.entries, ppd->ccti_entries, 3709 memcpy(new_cc_state->cct.entries, ppd->ccti_entries,
3693 ppd->total_cct_entry * sizeof(struct ib_cc_table_entry)); 3710 ppd->total_cct_entry * sizeof(struct ib_cc_table_entry));
3694 3711
@@ -3751,7 +3768,7 @@ static int __subn_get_opa_hfi1_cong_log(struct opa_smp *smp, u32 am,
3751 struct hfi1_ibport *ibp = to_iport(ibdev, port); 3768 struct hfi1_ibport *ibp = to_iport(ibdev, port);
3752 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 3769 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
3753 struct opa_hfi1_cong_log *cong_log = (struct opa_hfi1_cong_log *)data; 3770 struct opa_hfi1_cong_log *cong_log = (struct opa_hfi1_cong_log *)data;
3754 s64 ts; 3771 u64 ts;
3755 int i; 3772 int i;
3756 3773
3757 if (am || smp_length_check(sizeof(*cong_log), max_len)) { 3774 if (am || smp_length_check(sizeof(*cong_log), max_len)) {
@@ -3769,7 +3786,7 @@ static int __subn_get_opa_hfi1_cong_log(struct opa_smp *smp, u32 am,
3769 ppd->threshold_cong_event_map, 3786 ppd->threshold_cong_event_map,
3770 sizeof(cong_log->threshold_cong_event_map)); 3787 sizeof(cong_log->threshold_cong_event_map));
3771 /* keep timestamp in units of 1.024 usec */ 3788 /* keep timestamp in units of 1.024 usec */
3772 ts = ktime_to_ns(ktime_get()) / 1024; 3789 ts = ktime_get_ns() / 1024;
3773 cong_log->current_time_stamp = cpu_to_be32(ts); 3790 cong_log->current_time_stamp = cpu_to_be32(ts);
3774 for (i = 0; i < OPA_CONG_LOG_ELEMS; i++) { 3791 for (i = 0; i < OPA_CONG_LOG_ELEMS; i++) {
3775 struct opa_hfi1_cong_log_event_internal *cce = 3792 struct opa_hfi1_cong_log_event_internal *cce =
@@ -3781,7 +3798,7 @@ static int __subn_get_opa_hfi1_cong_log(struct opa_smp *smp, u32 am,
3781 * required to wrap the counter are supposed to 3798 * required to wrap the counter are supposed to
3782 * be zeroed (CA10-49 IBTA, release 1.2.1, V1). 3799 * be zeroed (CA10-49 IBTA, release 1.2.1, V1).
3783 */ 3800 */
3784 if ((u64)(ts - cce->timestamp) > (2 * UINT_MAX)) 3801 if ((ts - cce->timestamp) / 2 > U32_MAX)
3785 continue; 3802 continue;
3786 memcpy(cong_log->events[i].local_qp_cn_entry, &cce->lqpn, 3); 3803 memcpy(cong_log->events[i].local_qp_cn_entry, &cce->lqpn, 3);
3787 memcpy(cong_log->events[i].remote_qp_number_cn_entry, 3804 memcpy(cong_log->events[i].remote_qp_number_cn_entry,
@@ -4260,6 +4277,18 @@ void clear_linkup_counters(struct hfi1_devdata *dd)
4260 dd->err_info_xmit_constraint.status &= ~OPA_EI_STATUS_SMASK; 4277 dd->err_info_xmit_constraint.status &= ~OPA_EI_STATUS_SMASK;
4261} 4278}
4262 4279
4280static int is_full_mgmt_pkey_in_table(struct hfi1_ibport *ibp)
4281{
4282 unsigned int i;
4283 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
4284
4285 for (i = 0; i < ARRAY_SIZE(ppd->pkeys); ++i)
4286 if (ppd->pkeys[i] == FULL_MGMT_P_KEY)
4287 return 1;
4288
4289 return 0;
4290}
4291
4263/* 4292/*
4264 * is_local_mad() returns 1 if 'mad' is sent from, and destined to the 4293 * is_local_mad() returns 1 if 'mad' is sent from, and destined to the
4265 * local node, 0 otherwise. 4294 * local node, 0 otherwise.
@@ -4293,7 +4322,6 @@ static int opa_local_smp_check(struct hfi1_ibport *ibp,
4293 const struct ib_wc *in_wc) 4322 const struct ib_wc *in_wc)
4294{ 4323{
4295 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 4324 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
4296 u16 slid = ib_lid_cpu16(in_wc->slid);
4297 u16 pkey; 4325 u16 pkey;
4298 4326
4299 if (in_wc->pkey_index >= ARRAY_SIZE(ppd->pkeys)) 4327 if (in_wc->pkey_index >= ARRAY_SIZE(ppd->pkeys))
@@ -4320,10 +4348,71 @@ static int opa_local_smp_check(struct hfi1_ibport *ibp,
4320 */ 4348 */
4321 if (pkey == LIM_MGMT_P_KEY || pkey == FULL_MGMT_P_KEY) 4349 if (pkey == LIM_MGMT_P_KEY || pkey == FULL_MGMT_P_KEY)
4322 return 0; 4350 return 0;
4323 ingress_pkey_table_fail(ppd, pkey, slid); 4351 /*
4352 * On OPA devices it is okay to lose the upper 16 bits of LID as this
4353 * information is obtained elsewhere. Mask off the upper 16 bits.
4354 */
4355 ingress_pkey_table_fail(ppd, pkey, ib_lid_cpu16(0xFFFF & in_wc->slid));
4324 return 1; 4356 return 1;
4325} 4357}
4326 4358
4359/**
4360 * hfi1_pkey_validation_pma - It validates PKEYs for incoming PMA MAD packets.
4361 * @ibp: IB port data
4362 * @in_mad: MAD packet with header and data
4363 * @in_wc: Work completion data such as source LID, port number, etc.
4364 *
4365 * These are all the possible logic rules for validating a pkey:
4366 *
4367 * a) If pkey neither FULL_MGMT_P_KEY nor LIM_MGMT_P_KEY,
4368 * and NOT self-originated packet:
4369 * Drop MAD packet as it should always be part of the
4370 * management partition unless it's a self-originated packet.
4371 *
4372 * b) If pkey_index -> FULL_MGMT_P_KEY, and LIM_MGMT_P_KEY in pkey table:
4373 * The packet is coming from a management node and the receiving node
4374 * is also a management node, so it is safe for the packet to go through.
4375 *
4376 * c) If pkey_index -> FULL_MGMT_P_KEY, and LIM_MGMT_P_KEY is NOT in pkey table:
4377 * Drop the packet as LIM_MGMT_P_KEY should always be in the pkey table.
4378 * It could be an FM misconfiguration.
4379 *
4380 * d) If pkey_index -> LIM_MGMT_P_KEY and FULL_MGMT_P_KEY is NOT in pkey table:
4381 * It is safe for the packet to go through since a non-management node is
4382 * talking to another non-management node.
4383 *
4384 * e) If pkey_index -> LIM_MGMT_P_KEY and FULL_MGMT_P_KEY in pkey table:
4385 * Drop the packet because a non-management node is talking to a
4386 * management node, and it could be an attack.
4387 *
4388 * For the implementation, these rules can be simplied to only checking
4389 * for (a) and (e). There's no need to check for rule (b) as
4390 * the packet doesn't need to be dropped. Rule (c) is not possible in
4391 * the driver as LIM_MGMT_P_KEY is always in the pkey table.
4392 *
4393 * Return:
4394 * 0 - pkey is okay, -EINVAL it's a bad pkey
4395 */
4396static int hfi1_pkey_validation_pma(struct hfi1_ibport *ibp,
4397 const struct opa_mad *in_mad,
4398 const struct ib_wc *in_wc)
4399{
4400 u16 pkey_value = hfi1_lookup_pkey_value(ibp, in_wc->pkey_index);
4401
4402 /* Rule (a) from above */
4403 if (!is_local_mad(ibp, in_mad, in_wc) &&
4404 pkey_value != LIM_MGMT_P_KEY &&
4405 pkey_value != FULL_MGMT_P_KEY)
4406 return -EINVAL;
4407
4408 /* Rule (e) from above */
4409 if (pkey_value == LIM_MGMT_P_KEY &&
4410 is_full_mgmt_pkey_in_table(ibp))
4411 return -EINVAL;
4412
4413 return 0;
4414}
4415
4327static int process_subn_opa(struct ib_device *ibdev, int mad_flags, 4416static int process_subn_opa(struct ib_device *ibdev, int mad_flags,
4328 u8 port, const struct opa_mad *in_mad, 4417 u8 port, const struct opa_mad *in_mad,
4329 struct opa_mad *out_mad, 4418 struct opa_mad *out_mad,
@@ -4663,8 +4752,11 @@ static int hfi1_process_opa_mad(struct ib_device *ibdev, int mad_flags,
4663 out_mad, &resp_len); 4752 out_mad, &resp_len);
4664 goto bail; 4753 goto bail;
4665 case IB_MGMT_CLASS_PERF_MGMT: 4754 case IB_MGMT_CLASS_PERF_MGMT:
4666 ret = process_perf_opa(ibdev, port, in_mad, out_mad, 4755 ret = hfi1_pkey_validation_pma(ibp, in_mad, in_wc);
4667 &resp_len); 4756 if (ret)
4757 return IB_MAD_RESULT_FAILURE;
4758
4759 ret = process_perf_opa(ibdev, port, in_mad, out_mad, &resp_len);
4668 goto bail; 4760 goto bail;
4669 4761
4670 default: 4762 default:
diff --git a/drivers/infiniband/hw/hfi1/mad.h b/drivers/infiniband/hw/hfi1/mad.h
index 4c1245072093..c4938f3d97c8 100644
--- a/drivers/infiniband/hw/hfi1/mad.h
+++ b/drivers/infiniband/hw/hfi1/mad.h
@@ -239,7 +239,7 @@ struct opa_hfi1_cong_log_event_internal {
239 u8 sl; 239 u8 sl;
240 u8 svc_type; 240 u8 svc_type;
241 u32 rlid; 241 u32 rlid;
242 s64 timestamp; /* wider than 32 bits to detect 32 bit rollover */ 242 u64 timestamp; /* wider than 32 bits to detect 32 bit rollover */
243}; 243};
244 244
245struct opa_hfi1_cong_log_event { 245struct opa_hfi1_cong_log_event {
@@ -428,6 +428,6 @@ struct sc2vlnt {
428 COUNTER_MASK(1, 4)) 428 COUNTER_MASK(1, 4))
429 429
430void hfi1_event_pkey_change(struct hfi1_devdata *dd, u8 port); 430void hfi1_event_pkey_change(struct hfi1_devdata *dd, u8 port);
431void hfi1_handle_trap_timer(unsigned long data); 431void hfi1_handle_trap_timer(struct timer_list *t);
432 432
433#endif /* _HFI1_MAD_H */ 433#endif /* _HFI1_MAD_H */
diff --git a/drivers/infiniband/hw/hfi1/mmu_rb.c b/drivers/infiniband/hw/hfi1/mmu_rb.c
index 175002c046ed..e7b3ce123da6 100644
--- a/drivers/infiniband/hw/hfi1/mmu_rb.c
+++ b/drivers/infiniband/hw/hfi1/mmu_rb.c
@@ -67,12 +67,9 @@ struct mmu_rb_handler {
67 67
68static unsigned long mmu_node_start(struct mmu_rb_node *); 68static unsigned long mmu_node_start(struct mmu_rb_node *);
69static unsigned long mmu_node_last(struct mmu_rb_node *); 69static unsigned long mmu_node_last(struct mmu_rb_node *);
70static inline void mmu_notifier_range_start(struct mmu_notifier *, 70static void mmu_notifier_range_start(struct mmu_notifier *,
71 struct mm_struct *, 71 struct mm_struct *,
72 unsigned long, unsigned long); 72 unsigned long, unsigned long);
73static void mmu_notifier_mem_invalidate(struct mmu_notifier *,
74 struct mm_struct *,
75 unsigned long, unsigned long);
76static struct mmu_rb_node *__mmu_rb_search(struct mmu_rb_handler *, 73static struct mmu_rb_node *__mmu_rb_search(struct mmu_rb_handler *,
77 unsigned long, unsigned long); 74 unsigned long, unsigned long);
78static void do_remove(struct mmu_rb_handler *handler, 75static void do_remove(struct mmu_rb_handler *handler,
@@ -286,17 +283,10 @@ void hfi1_mmu_rb_remove(struct mmu_rb_handler *handler,
286 handler->ops->remove(handler->ops_arg, node); 283 handler->ops->remove(handler->ops_arg, node);
287} 284}
288 285
289static inline void mmu_notifier_range_start(struct mmu_notifier *mn, 286static void mmu_notifier_range_start(struct mmu_notifier *mn,
290 struct mm_struct *mm, 287 struct mm_struct *mm,
291 unsigned long start, 288 unsigned long start,
292 unsigned long end) 289 unsigned long end)
293{
294 mmu_notifier_mem_invalidate(mn, mm, start, end);
295}
296
297static void mmu_notifier_mem_invalidate(struct mmu_notifier *mn,
298 struct mm_struct *mm,
299 unsigned long start, unsigned long end)
300{ 290{
301 struct mmu_rb_handler *handler = 291 struct mmu_rb_handler *handler =
302 container_of(mn, struct mmu_rb_handler, mn); 292 container_of(mn, struct mmu_rb_handler, mn);
diff --git a/drivers/infiniband/hw/hfi1/pio.c b/drivers/infiniband/hw/hfi1/pio.c
index 75e740780285..4c1198bc5e70 100644
--- a/drivers/infiniband/hw/hfi1/pio.c
+++ b/drivers/infiniband/hw/hfi1/pio.c
@@ -703,7 +703,6 @@ struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
703{ 703{
704 struct send_context_info *sci; 704 struct send_context_info *sci;
705 struct send_context *sc = NULL; 705 struct send_context *sc = NULL;
706 int req_type = type;
707 dma_addr_t dma; 706 dma_addr_t dma;
708 unsigned long flags; 707 unsigned long flags;
709 u64 reg; 708 u64 reg;
@@ -730,13 +729,6 @@ struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
730 return NULL; 729 return NULL;
731 } 730 }
732 731
733 /*
734 * VNIC contexts are dynamically allocated.
735 * Hence, pick a user context for VNIC.
736 */
737 if (type == SC_VNIC)
738 type = SC_USER;
739
740 spin_lock_irqsave(&dd->sc_lock, flags); 732 spin_lock_irqsave(&dd->sc_lock, flags);
741 ret = sc_hw_alloc(dd, type, &sw_index, &hw_context); 733 ret = sc_hw_alloc(dd, type, &sw_index, &hw_context);
742 if (ret) { 734 if (ret) {
@@ -746,15 +738,6 @@ struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
746 return NULL; 738 return NULL;
747 } 739 }
748 740
749 /*
750 * VNIC contexts are used by kernel driver.
751 * Hence, mark them as kernel contexts.
752 */
753 if (req_type == SC_VNIC) {
754 dd->send_contexts[sw_index].type = SC_KERNEL;
755 type = SC_KERNEL;
756 }
757
758 sci = &dd->send_contexts[sw_index]; 741 sci = &dd->send_contexts[sw_index];
759 sci->sc = sc; 742 sci->sc = sc;
760 743
diff --git a/drivers/infiniband/hw/hfi1/pio.h b/drivers/infiniband/hw/hfi1/pio.h
index 99ca5edb0b43..058b08f459ab 100644
--- a/drivers/infiniband/hw/hfi1/pio.h
+++ b/drivers/infiniband/hw/hfi1/pio.h
@@ -54,12 +54,6 @@
54#define SC_USER 3 /* must be the last one: it may take all left */ 54#define SC_USER 3 /* must be the last one: it may take all left */
55#define SC_MAX 4 /* count of send context types */ 55#define SC_MAX 4 /* count of send context types */
56 56
57/*
58 * SC_VNIC types are allocated (dynamically) from the user context pool,
59 * (SC_USER) and used by kernel driver as kernel contexts (SC_KERNEL).
60 */
61#define SC_VNIC SC_MAX
62
63/* invalid send context index */ 57/* invalid send context index */
64#define INVALID_SCI 0xff 58#define INVALID_SCI 0xff
65 59
diff --git a/drivers/infiniband/hw/hfi1/rc.c b/drivers/infiniband/hw/hfi1/rc.c
index e1cf0c08ca6f..fd01a760259f 100644
--- a/drivers/infiniband/hw/hfi1/rc.c
+++ b/drivers/infiniband/hw/hfi1/rc.c
@@ -276,7 +276,6 @@ int hfi1_make_rc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
276 if (IS_ERR(ps->s_txreq)) 276 if (IS_ERR(ps->s_txreq))
277 goto bail_no_tx; 277 goto bail_no_tx;
278 278
279 ps->s_txreq->phdr.hdr.hdr_type = priv->hdr_type;
280 if (priv->hdr_type == HFI1_PKT_TYPE_9B) { 279 if (priv->hdr_type == HFI1_PKT_TYPE_9B) {
281 /* header size in 32-bit words LRH+BTH = (8+12)/4. */ 280 /* header size in 32-bit words LRH+BTH = (8+12)/4. */
282 hwords = 5; 281 hwords = 5;
@@ -1966,7 +1965,7 @@ static void log_cca_event(struct hfi1_pportdata *ppd, u8 sl, u32 rlid,
1966 cc_event->svc_type = svc_type; 1965 cc_event->svc_type = svc_type;
1967 cc_event->rlid = rlid; 1966 cc_event->rlid = rlid;
1968 /* keep timestamp in units of 1.024 usec */ 1967 /* keep timestamp in units of 1.024 usec */
1969 cc_event->timestamp = ktime_to_ns(ktime_get()) / 1024; 1968 cc_event->timestamp = ktime_get_ns() / 1024;
1970 1969
1971 spin_unlock_irqrestore(&ppd->cc_log_lock, flags); 1970 spin_unlock_irqrestore(&ppd->cc_log_lock, flags);
1972} 1971}
@@ -2175,7 +2174,7 @@ send_middle:
2175 goto no_immediate_data; 2174 goto no_immediate_data;
2176 if (opcode == OP(SEND_ONLY_WITH_INVALIDATE)) 2175 if (opcode == OP(SEND_ONLY_WITH_INVALIDATE))
2177 goto send_last_inv; 2176 goto send_last_inv;
2178 /* FALLTHROUGH for SEND_ONLY_WITH_IMMEDIATE */ 2177 /* FALLTHROUGH -- for SEND_ONLY_WITH_IMMEDIATE */
2179 case OP(SEND_LAST_WITH_IMMEDIATE): 2178 case OP(SEND_LAST_WITH_IMMEDIATE):
2180send_last_imm: 2179send_last_imm:
2181 wc.ex.imm_data = ohdr->u.imm_data; 2180 wc.ex.imm_data = ohdr->u.imm_data;
@@ -2220,7 +2219,7 @@ send_last:
2220 wc.opcode = IB_WC_RECV; 2219 wc.opcode = IB_WC_RECV;
2221 wc.qp = &qp->ibqp; 2220 wc.qp = &qp->ibqp;
2222 wc.src_qp = qp->remote_qpn; 2221 wc.src_qp = qp->remote_qpn;
2223 wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr); 2222 wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr) & U16_MAX;
2224 /* 2223 /*
2225 * It seems that IB mandates the presence of an SL in a 2224 * It seems that IB mandates the presence of an SL in a
2226 * work completion only for the UD transport (see section 2225 * work completion only for the UD transport (see section
diff --git a/drivers/infiniband/hw/hfi1/ruc.c b/drivers/infiniband/hw/hfi1/ruc.c
index a7fc664f0d4e..2c7fc6e331ea 100644
--- a/drivers/infiniband/hw/hfi1/ruc.c
+++ b/drivers/infiniband/hw/hfi1/ruc.c
@@ -560,7 +560,7 @@ do_write:
560 wc.byte_len = wqe->length; 560 wc.byte_len = wqe->length;
561 wc.qp = &qp->ibqp; 561 wc.qp = &qp->ibqp;
562 wc.src_qp = qp->remote_qpn; 562 wc.src_qp = qp->remote_qpn;
563 wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr); 563 wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr) & U16_MAX;
564 wc.sl = rdma_ah_get_sl(&qp->remote_ah_attr); 564 wc.sl = rdma_ah_get_sl(&qp->remote_ah_attr);
565 wc.port_num = 1; 565 wc.port_num = 1;
566 /* Signal completion event if the solicited bit is set. */ 566 /* Signal completion event if the solicited bit is set. */
@@ -825,11 +825,9 @@ static inline void hfi1_make_ruc_header_9B(struct rvt_qp *qp,
825{ 825{
826 struct hfi1_qp_priv *priv = qp->priv; 826 struct hfi1_qp_priv *priv = qp->priv;
827 struct hfi1_ibport *ibp = ps->ibp; 827 struct hfi1_ibport *ibp = ps->ibp;
828 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
829 u32 bth1 = 0; 828 u32 bth1 = 0;
830 u16 pkey = hfi1_get_pkey(ibp, qp->s_pkey_index); 829 u16 pkey = hfi1_get_pkey(ibp, qp->s_pkey_index);
831 u16 lrh0 = HFI1_LRH_BTH; 830 u16 lrh0 = HFI1_LRH_BTH;
832 u16 slid;
833 u8 extra_bytes = -ps->s_txreq->s_cur_size & 3; 831 u8 extra_bytes = -ps->s_txreq->s_cur_size & 3;
834 u32 nwords = SIZE_OF_CRC + ((ps->s_txreq->s_cur_size + 832 u32 nwords = SIZE_OF_CRC + ((ps->s_txreq->s_cur_size +
835 extra_bytes) >> 2); 833 extra_bytes) >> 2);
@@ -866,13 +864,6 @@ static inline void hfi1_make_ruc_header_9B(struct rvt_qp *qp,
866 bth1 |= (IB_BECN_MASK << IB_BECN_SHIFT); 864 bth1 |= (IB_BECN_MASK << IB_BECN_SHIFT);
867 } 865 }
868 hfi1_make_ruc_bth(qp, ohdr, bth0, bth1, bth2); 866 hfi1_make_ruc_bth(qp, ohdr, bth0, bth1, bth2);
869
870 if (!ppd->lid)
871 slid = be16_to_cpu(IB_LID_PERMISSIVE);
872 else
873 slid = ppd->lid |
874 (rdma_ah_get_path_bits(&qp->remote_ah_attr) &
875 ((1 << ppd->lmc) - 1));
876 hfi1_make_ib_hdr(&ps->s_txreq->phdr.hdr.ibh, 867 hfi1_make_ib_hdr(&ps->s_txreq->phdr.hdr.ibh,
877 lrh0, 868 lrh0,
878 qp->s_hdrwords + nwords, 869 qp->s_hdrwords + nwords,
diff --git a/drivers/infiniband/hw/hfi1/sdma.c b/drivers/infiniband/hw/hfi1/sdma.c
index 08346d25441c..31c8f89b5fc8 100644
--- a/drivers/infiniband/hw/hfi1/sdma.c
+++ b/drivers/infiniband/hw/hfi1/sdma.c
@@ -491,10 +491,10 @@ static void sdma_err_progress_check_schedule(struct sdma_engine *sde)
491 } 491 }
492} 492}
493 493
494static void sdma_err_progress_check(unsigned long data) 494static void sdma_err_progress_check(struct timer_list *t)
495{ 495{
496 unsigned index; 496 unsigned index;
497 struct sdma_engine *sde = (struct sdma_engine *)data; 497 struct sdma_engine *sde = from_timer(sde, t, err_progress_check_timer);
498 498
499 dd_dev_err(sde->dd, "SDE progress check event\n"); 499 dd_dev_err(sde->dd, "SDE progress check event\n");
500 for (index = 0; index < sde->dd->num_sdma; index++) { 500 for (index = 0; index < sde->dd->num_sdma; index++) {
@@ -1392,6 +1392,13 @@ int sdma_init(struct hfi1_devdata *dd, u8 port)
1392 return ret; 1392 return ret;
1393 1393
1394 idle_cnt = ns_to_cclock(dd, idle_cnt); 1394 idle_cnt = ns_to_cclock(dd, idle_cnt);
1395 if (idle_cnt)
1396 dd->default_desc1 =
1397 SDMA_DESC1_HEAD_TO_HOST_FLAG;
1398 else
1399 dd->default_desc1 =
1400 SDMA_DESC1_INT_REQ_FLAG;
1401
1395 if (!sdma_desct_intr) 1402 if (!sdma_desct_intr)
1396 sdma_desct_intr = SDMA_DESC_INTR; 1403 sdma_desct_intr = SDMA_DESC_INTR;
1397 1404
@@ -1436,13 +1443,6 @@ int sdma_init(struct hfi1_devdata *dd, u8 port)
1436 sde->tail_csr = 1443 sde->tail_csr =
1437 get_kctxt_csr_addr(dd, this_idx, SD(TAIL)); 1444 get_kctxt_csr_addr(dd, this_idx, SD(TAIL));
1438 1445
1439 if (idle_cnt)
1440 dd->default_desc1 =
1441 SDMA_DESC1_HEAD_TO_HOST_FLAG;
1442 else
1443 dd->default_desc1 =
1444 SDMA_DESC1_INT_REQ_FLAG;
1445
1446 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task, 1446 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task,
1447 (unsigned long)sde); 1447 (unsigned long)sde);
1448 1448
@@ -1453,8 +1453,8 @@ int sdma_init(struct hfi1_devdata *dd, u8 port)
1453 1453
1454 sde->progress_check_head = 0; 1454 sde->progress_check_head = 0;
1455 1455
1456 setup_timer(&sde->err_progress_check_timer, 1456 timer_setup(&sde->err_progress_check_timer,
1457 sdma_err_progress_check, (unsigned long)sde); 1457 sdma_err_progress_check, 0);
1458 1458
1459 sde->descq = dma_zalloc_coherent( 1459 sde->descq = dma_zalloc_coherent(
1460 &dd->pcidev->dev, 1460 &dd->pcidev->dev,
@@ -1465,13 +1465,8 @@ int sdma_init(struct hfi1_devdata *dd, u8 port)
1465 if (!sde->descq) 1465 if (!sde->descq)
1466 goto bail; 1466 goto bail;
1467 sde->tx_ring = 1467 sde->tx_ring =
1468 kcalloc(descq_cnt, sizeof(struct sdma_txreq *), 1468 kvzalloc_node(sizeof(struct sdma_txreq *) * descq_cnt,
1469 GFP_KERNEL); 1469 GFP_KERNEL, dd->node);
1470 if (!sde->tx_ring)
1471 sde->tx_ring =
1472 vzalloc(
1473 sizeof(struct sdma_txreq *) *
1474 descq_cnt);
1475 if (!sde->tx_ring) 1470 if (!sde->tx_ring)
1476 goto bail; 1471 goto bail;
1477 } 1472 }
@@ -2144,7 +2139,6 @@ void sdma_dumpstate(struct sdma_engine *sde)
2144 2139
2145static void dump_sdma_state(struct sdma_engine *sde) 2140static void dump_sdma_state(struct sdma_engine *sde)
2146{ 2141{
2147 struct hw_sdma_desc *descq;
2148 struct hw_sdma_desc *descqp; 2142 struct hw_sdma_desc *descqp;
2149 u64 desc[2]; 2143 u64 desc[2];
2150 u64 addr; 2144 u64 addr;
@@ -2155,7 +2149,6 @@ static void dump_sdma_state(struct sdma_engine *sde)
2155 head = sde->descq_head & sde->sdma_mask; 2149 head = sde->descq_head & sde->sdma_mask;
2156 tail = sde->descq_tail & sde->sdma_mask; 2150 tail = sde->descq_tail & sde->sdma_mask;
2157 cnt = sdma_descq_freecnt(sde); 2151 cnt = sdma_descq_freecnt(sde);
2158 descq = sde->descq;
2159 2152
2160 dd_dev_err(sde->dd, 2153 dd_dev_err(sde->dd,
2161 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n", 2154 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
@@ -2593,7 +2586,7 @@ static void __sdma_process_event(struct sdma_engine *sde,
2593 * 7220, e.g. 2586 * 7220, e.g.
2594 */ 2587 */
2595 ss->go_s99_running = 1; 2588 ss->go_s99_running = 1;
2596 /* fall through and start dma engine */ 2589 /* fall through -- and start dma engine */
2597 case sdma_event_e10_go_hw_start: 2590 case sdma_event_e10_go_hw_start:
2598 /* This reference means the state machine is started */ 2591 /* This reference means the state machine is started */
2599 sdma_get(&sde->state); 2592 sdma_get(&sde->state);
@@ -3016,6 +3009,7 @@ static void __sdma_process_event(struct sdma_engine *sde,
3016 case sdma_event_e60_hw_halted: 3009 case sdma_event_e60_hw_halted:
3017 need_progress = 1; 3010 need_progress = 1;
3018 sdma_err_progress_check_schedule(sde); 3011 sdma_err_progress_check_schedule(sde);
3012 /* fall through */
3019 case sdma_event_e90_sw_halted: 3013 case sdma_event_e90_sw_halted:
3020 /* 3014 /*
3021 * SW initiated halt does not perform engines 3015 * SW initiated halt does not perform engines
diff --git a/drivers/infiniband/hw/hfi1/sysfs.c b/drivers/infiniband/hw/hfi1/sysfs.c
index 6d2702ef34ac..25e867393463 100644
--- a/drivers/infiniband/hw/hfi1/sysfs.c
+++ b/drivers/infiniband/hw/hfi1/sysfs.c
@@ -543,7 +543,7 @@ static ssize_t show_nctxts(struct device *device,
543 * give a more accurate picture of total contexts available. 543 * give a more accurate picture of total contexts available.
544 */ 544 */
545 return scnprintf(buf, PAGE_SIZE, "%u\n", 545 return scnprintf(buf, PAGE_SIZE, "%u\n",
546 min(dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt, 546 min(dd->num_user_contexts,
547 (u32)dd->sc_sizes[SC_USER].count)); 547 (u32)dd->sc_sizes[SC_USER].count));
548} 548}
549 549
diff --git a/drivers/infiniband/hw/hfi1/trace.c b/drivers/infiniband/hw/hfi1/trace.c
index 9938bb983ce6..959a80429ee9 100644
--- a/drivers/infiniband/hw/hfi1/trace.c
+++ b/drivers/infiniband/hw/hfi1/trace.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright(c) 2015, 2016 Intel Corporation. 2 * Copyright(c) 2015 - 2017 Intel Corporation.
3 * 3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license. 5 * redistributing this file, you may do so under either license.
@@ -91,12 +91,17 @@ u8 hfi1_trace_opa_hdr_len(struct hfi1_opa_header *opa_hdr)
91 return __get_16b_hdr_len(&opa_hdr->opah); 91 return __get_16b_hdr_len(&opa_hdr->opah);
92} 92}
93 93
94const char *hfi1_trace_get_packet_str(struct hfi1_packet *packet) 94const char *hfi1_trace_get_packet_l4_str(u8 l4)
95{ 95{
96 if (packet->etype != RHF_RCV_TYPE_BYPASS) 96 if (l4)
97 return "IB"; 97 return "16B";
98 else
99 return "9B";
100}
98 101
99 switch (hfi1_16B_get_l2(packet->hdr)) { 102const char *hfi1_trace_get_packet_l2_str(u8 l2)
103{
104 switch (l2) {
100 case 0: 105 case 0:
101 return "0"; 106 return "0";
102 case 1: 107 case 1:
@@ -109,14 +114,6 @@ const char *hfi1_trace_get_packet_str(struct hfi1_packet *packet)
109 return ""; 114 return "";
110} 115}
111 116
112const char *hfi1_trace_get_packet_type_str(u8 l4)
113{
114 if (l4)
115 return "16B";
116 else
117 return "9B";
118}
119
120#define IMM_PRN "imm:%d" 117#define IMM_PRN "imm:%d"
121#define RETH_PRN "reth vaddr:0x%.16llx rkey:0x%.8x dlen:0x%.8x" 118#define RETH_PRN "reth vaddr:0x%.16llx rkey:0x%.8x dlen:0x%.8x"
122#define AETH_PRN "aeth syn:0x%.2x %s msn:0x%.8x" 119#define AETH_PRN "aeth syn:0x%.2x %s msn:0x%.8x"
@@ -154,7 +151,7 @@ void hfi1_trace_parse_9b_bth(struct ib_other_headers *ohdr,
154 *opcode = ib_bth_get_opcode(ohdr); 151 *opcode = ib_bth_get_opcode(ohdr);
155 *tver = ib_bth_get_tver(ohdr); 152 *tver = ib_bth_get_tver(ohdr);
156 *pkey = ib_bth_get_pkey(ohdr); 153 *pkey = ib_bth_get_pkey(ohdr);
157 *psn = ib_bth_get_psn(ohdr); 154 *psn = mask_psn(ib_bth_get_psn(ohdr));
158 *qpn = ib_bth_get_qpn(ohdr); 155 *qpn = ib_bth_get_qpn(ohdr);
159} 156}
160 157
@@ -169,7 +166,7 @@ void hfi1_trace_parse_16b_bth(struct ib_other_headers *ohdr,
169 *pad = ib_bth_get_pad(ohdr); 166 *pad = ib_bth_get_pad(ohdr);
170 *se = ib_bth_get_se(ohdr); 167 *se = ib_bth_get_se(ohdr);
171 *tver = ib_bth_get_tver(ohdr); 168 *tver = ib_bth_get_tver(ohdr);
172 *psn = ib_bth_get_psn(ohdr); 169 *psn = mask_psn(ib_bth_get_psn(ohdr));
173 *qpn = ib_bth_get_qpn(ohdr); 170 *qpn = ib_bth_get_qpn(ohdr);
174} 171}
175 172
diff --git a/drivers/infiniband/hw/hfi1/trace.h b/drivers/infiniband/hw/hfi1/trace.h
index af50c0793450..8540463ef3f7 100644
--- a/drivers/infiniband/hw/hfi1/trace.h
+++ b/drivers/infiniband/hw/hfi1/trace.h
@@ -44,6 +44,16 @@
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 * 45 *
46 */ 46 */
47
48#define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype }
49#define show_packettype(etype) \
50__print_symbolic(etype, \
51 packettype_name(EXPECTED), \
52 packettype_name(EAGER), \
53 packettype_name(IB), \
54 packettype_name(ERROR), \
55 packettype_name(BYPASS))
56
47#include "trace_dbg.h" 57#include "trace_dbg.h"
48#include "trace_misc.h" 58#include "trace_misc.h"
49#include "trace_ctxts.h" 59#include "trace_ctxts.h"
diff --git a/drivers/infiniband/hw/hfi1/trace_ibhdrs.h b/drivers/infiniband/hw/hfi1/trace_ibhdrs.h
index 6721f84dafa5..fb631278eccd 100644
--- a/drivers/infiniband/hw/hfi1/trace_ibhdrs.h
+++ b/drivers/infiniband/hw/hfi1/trace_ibhdrs.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright(c) 2015, 2016 Intel Corporation. 2 * Copyright(c) 2015 - 2017 Intel Corporation.
3 * 3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license. 5 * redistributing this file, you may do so under either license.
@@ -99,8 +99,7 @@ u8 ibhdr_exhdr_len(struct ib_header *hdr);
99const char *parse_everbs_hdrs(struct trace_seq *p, u8 opcode, void *ehdrs); 99const char *parse_everbs_hdrs(struct trace_seq *p, u8 opcode, void *ehdrs);
100u8 hfi1_trace_opa_hdr_len(struct hfi1_opa_header *opah); 100u8 hfi1_trace_opa_hdr_len(struct hfi1_opa_header *opah);
101u8 hfi1_trace_packet_hdr_len(struct hfi1_packet *packet); 101u8 hfi1_trace_packet_hdr_len(struct hfi1_packet *packet);
102const char *hfi1_trace_get_packet_type_str(u8 l4); 102const char *hfi1_trace_get_packet_l4_str(u8 l4);
103const char *hfi1_trace_get_packet_str(struct hfi1_packet *packet);
104void hfi1_trace_parse_9b_bth(struct ib_other_headers *ohdr, 103void hfi1_trace_parse_9b_bth(struct ib_other_headers *ohdr,
105 u8 *ack, u8 *becn, u8 *fecn, u8 *mig, 104 u8 *ack, u8 *becn, u8 *fecn, u8 *mig,
106 u8 *se, u8 *pad, u8 *opcode, u8 *tver, 105 u8 *se, u8 *pad, u8 *opcode, u8 *tver,
@@ -129,6 +128,8 @@ const char *hfi1_trace_fmt_bth(struct trace_seq *p, bool bypass,
129 u8 se, u8 pad, u8 opcode, const char *opname, 128 u8 se, u8 pad, u8 opcode, const char *opname,
130 u8 tver, u16 pkey, u32 psn, u32 qpn); 129 u8 tver, u16 pkey, u32 psn, u32 qpn);
131 130
131const char *hfi1_trace_get_packet_l2_str(u8 l2);
132
132#define __parse_ib_ehdrs(op, ehdrs) parse_everbs_hdrs(p, op, ehdrs) 133#define __parse_ib_ehdrs(op, ehdrs) parse_everbs_hdrs(p, op, ehdrs)
133 134
134#define lrh_name(lrh) { HFI1_##lrh, #lrh } 135#define lrh_name(lrh) { HFI1_##lrh, #lrh }
@@ -136,8 +137,6 @@ const char *hfi1_trace_fmt_bth(struct trace_seq *p, bool bypass,
136__print_symbolic(lrh, \ 137__print_symbolic(lrh, \
137 lrh_name(LRH_BTH), \ 138 lrh_name(LRH_BTH), \
138 lrh_name(LRH_GRH)) 139 lrh_name(LRH_GRH))
139#define PKT_ENTRY(pkt) __string(ptype, hfi1_trace_get_packet_str(packet))
140#define PKT_ASSIGN(pkt) __assign_str(ptype, hfi1_trace_get_packet_str(packet))
141 140
142DECLARE_EVENT_CLASS(hfi1_input_ibhdr_template, 141DECLARE_EVENT_CLASS(hfi1_input_ibhdr_template,
143 TP_PROTO(struct hfi1_devdata *dd, 142 TP_PROTO(struct hfi1_devdata *dd,
@@ -146,12 +145,12 @@ DECLARE_EVENT_CLASS(hfi1_input_ibhdr_template,
146 TP_ARGS(dd, packet, sc5), 145 TP_ARGS(dd, packet, sc5),
147 TP_STRUCT__entry( 146 TP_STRUCT__entry(
148 DD_DEV_ENTRY(dd) 147 DD_DEV_ENTRY(dd)
149 PKT_ENTRY(packet) 148 __field(u8, etype)
150 __field(bool, bypass)
151 __field(u8, ack) 149 __field(u8, ack)
152 __field(u8, age) 150 __field(u8, age)
153 __field(u8, becn) 151 __field(u8, becn)
154 __field(u8, fecn) 152 __field(u8, fecn)
153 __field(u8, l2)
155 __field(u8, l4) 154 __field(u8, l4)
156 __field(u8, lnh) 155 __field(u8, lnh)
157 __field(u8, lver) 156 __field(u8, lver)
@@ -176,10 +175,10 @@ DECLARE_EVENT_CLASS(hfi1_input_ibhdr_template,
176 ), 175 ),
177 TP_fast_assign( 176 TP_fast_assign(
178 DD_DEV_ASSIGN(dd); 177 DD_DEV_ASSIGN(dd);
179 PKT_ASSIGN(packet);
180 178
181 if (packet->etype == RHF_RCV_TYPE_BYPASS) { 179 __entry->etype = packet->etype;
182 __entry->bypass = true; 180 __entry->l2 = hfi1_16B_get_l2(packet->hdr);
181 if (__entry->etype == RHF_RCV_TYPE_BYPASS) {
183 hfi1_trace_parse_16b_hdr(packet->hdr, 182 hfi1_trace_parse_16b_hdr(packet->hdr,
184 &__entry->age, 183 &__entry->age,
185 &__entry->becn, 184 &__entry->becn,
@@ -203,7 +202,6 @@ DECLARE_EVENT_CLASS(hfi1_input_ibhdr_template,
203 &__entry->psn, 202 &__entry->psn,
204 &__entry->qpn); 203 &__entry->qpn);
205 } else { 204 } else {
206 __entry->bypass = false;
207 hfi1_trace_parse_9b_hdr(packet->hdr, sc5, 205 hfi1_trace_parse_9b_hdr(packet->hdr, sc5,
208 &__entry->lnh, 206 &__entry->lnh,
209 &__entry->lver, 207 &__entry->lver,
@@ -233,9 +231,13 @@ DECLARE_EVENT_CLASS(hfi1_input_ibhdr_template,
233 ), 231 ),
234 TP_printk("[%s] (%s) %s %s hlen:%d %s", 232 TP_printk("[%s] (%s) %s %s hlen:%d %s",
235 __get_str(dev), 233 __get_str(dev),
236 __get_str(ptype), 234 __entry->etype != RHF_RCV_TYPE_BYPASS ?
235 show_packettype(__entry->etype) :
236 hfi1_trace_get_packet_l2_str(
237 __entry->l2),
237 hfi1_trace_fmt_lrh(p, 238 hfi1_trace_fmt_lrh(p,
238 __entry->bypass, 239 __entry->etype ==
240 RHF_RCV_TYPE_BYPASS,
239 __entry->age, 241 __entry->age,
240 __entry->becn, 242 __entry->becn,
241 __entry->fecn, 243 __entry->fecn,
@@ -252,7 +254,8 @@ DECLARE_EVENT_CLASS(hfi1_input_ibhdr_template,
252 __entry->dlid, 254 __entry->dlid,
253 __entry->slid), 255 __entry->slid),
254 hfi1_trace_fmt_bth(p, 256 hfi1_trace_fmt_bth(p,
255 __entry->bypass, 257 __entry->etype ==
258 RHF_RCV_TYPE_BYPASS,
256 __entry->ack, 259 __entry->ack,
257 __entry->becn, 260 __entry->becn,
258 __entry->fecn, 261 __entry->fecn,
@@ -284,7 +287,7 @@ DECLARE_EVENT_CLASS(hfi1_output_ibhdr_template,
284 TP_ARGS(dd, opah, sc5), 287 TP_ARGS(dd, opah, sc5),
285 TP_STRUCT__entry( 288 TP_STRUCT__entry(
286 DD_DEV_ENTRY(dd) 289 DD_DEV_ENTRY(dd)
287 __field(bool, bypass) 290 __field(u8, hdr_type)
288 __field(u8, ack) 291 __field(u8, ack)
289 __field(u8, age) 292 __field(u8, age)
290 __field(u8, becn) 293 __field(u8, becn)
@@ -316,8 +319,8 @@ DECLARE_EVENT_CLASS(hfi1_output_ibhdr_template,
316 319
317 DD_DEV_ASSIGN(dd); 320 DD_DEV_ASSIGN(dd);
318 321
319 if (opah->hdr_type) { 322 __entry->hdr_type = opah->hdr_type;
320 __entry->bypass = true; 323 if (__entry->hdr_type) {
321 hfi1_trace_parse_16b_hdr(&opah->opah, 324 hfi1_trace_parse_16b_hdr(&opah->opah,
322 &__entry->age, 325 &__entry->age,
323 &__entry->becn, 326 &__entry->becn,
@@ -331,7 +334,7 @@ DECLARE_EVENT_CLASS(hfi1_output_ibhdr_template,
331 &__entry->dlid, 334 &__entry->dlid,
332 &__entry->slid); 335 &__entry->slid);
333 336
334 if (entry->l4 == OPA_16B_L4_IB_LOCAL) 337 if (__entry->l4 == OPA_16B_L4_IB_LOCAL)
335 ohdr = &opah->opah.u.oth; 338 ohdr = &opah->opah.u.oth;
336 else 339 else
337 ohdr = &opah->opah.u.l.oth; 340 ohdr = &opah->opah.u.l.oth;
@@ -345,7 +348,7 @@ DECLARE_EVENT_CLASS(hfi1_output_ibhdr_template,
345 &__entry->psn, 348 &__entry->psn,
346 &__entry->qpn); 349 &__entry->qpn);
347 } else { 350 } else {
348 __entry->bypass = false; 351 __entry->l4 = OPA_16B_L4_9B;
349 hfi1_trace_parse_9b_hdr(&opah->ibh, sc5, 352 hfi1_trace_parse_9b_hdr(&opah->ibh, sc5,
350 &__entry->lnh, 353 &__entry->lnh,
351 &__entry->lver, 354 &__entry->lver,
@@ -354,7 +357,7 @@ DECLARE_EVENT_CLASS(hfi1_output_ibhdr_template,
354 &__entry->len, 357 &__entry->len,
355 &__entry->dlid, 358 &__entry->dlid,
356 &__entry->slid); 359 &__entry->slid);
357 if (entry->lnh == HFI1_LRH_BTH) 360 if (__entry->lnh == HFI1_LRH_BTH)
358 ohdr = &opah->ibh.u.oth; 361 ohdr = &opah->ibh.u.oth;
359 else 362 else
360 ohdr = &opah->ibh.u.l.oth; 363 ohdr = &opah->ibh.u.l.oth;
@@ -378,9 +381,9 @@ DECLARE_EVENT_CLASS(hfi1_output_ibhdr_template,
378 ), 381 ),
379 TP_printk("[%s] (%s) %s %s hlen:%d %s", 382 TP_printk("[%s] (%s) %s %s hlen:%d %s",
380 __get_str(dev), 383 __get_str(dev),
381 hfi1_trace_get_packet_type_str(__entry->l4), 384 hfi1_trace_get_packet_l4_str(__entry->l4),
382 hfi1_trace_fmt_lrh(p, 385 hfi1_trace_fmt_lrh(p,
383 __entry->bypass, 386 !!__entry->hdr_type,
384 __entry->age, 387 __entry->age,
385 __entry->becn, 388 __entry->becn,
386 __entry->fecn, 389 __entry->fecn,
@@ -397,7 +400,7 @@ DECLARE_EVENT_CLASS(hfi1_output_ibhdr_template,
397 __entry->dlid, 400 __entry->dlid,
398 __entry->slid), 401 __entry->slid),
399 hfi1_trace_fmt_bth(p, 402 hfi1_trace_fmt_bth(p,
400 __entry->bypass, 403 !!__entry->hdr_type,
401 __entry->ack, 404 __entry->ack,
402 __entry->becn, 405 __entry->becn,
403 __entry->fecn, 406 __entry->fecn,
diff --git a/drivers/infiniband/hw/hfi1/trace_rx.h b/drivers/infiniband/hw/hfi1/trace_rx.h
index f9909d240dcc..4d487fee105d 100644
--- a/drivers/infiniband/hw/hfi1/trace_rx.h
+++ b/drivers/infiniband/hw/hfi1/trace_rx.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright(c) 2015, 2016 Intel Corporation. 2 * Copyright(c) 2015 - 2017 Intel Corporation.
3 * 3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license. 5 * redistributing this file, you may do so under either license.
@@ -62,15 +62,6 @@ __print_symbolic(type, \
62#undef TRACE_SYSTEM 62#undef TRACE_SYSTEM
63#define TRACE_SYSTEM hfi1_rx 63#define TRACE_SYSTEM hfi1_rx
64 64
65#define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype }
66#define show_packettype(etype) \
67__print_symbolic(etype, \
68 packettype_name(EXPECTED), \
69 packettype_name(EAGER), \
70 packettype_name(IB), \
71 packettype_name(ERROR), \
72 packettype_name(BYPASS))
73
74TRACE_EVENT(hfi1_rcvhdr, 65TRACE_EVENT(hfi1_rcvhdr,
75 TP_PROTO(struct hfi1_devdata *dd, 66 TP_PROTO(struct hfi1_devdata *dd,
76 u32 ctxt, 67 u32 ctxt,
diff --git a/drivers/infiniband/hw/hfi1/uc.c b/drivers/infiniband/hw/hfi1/uc.c
index 9a31c585427f..991bbee04821 100644
--- a/drivers/infiniband/hw/hfi1/uc.c
+++ b/drivers/infiniband/hw/hfi1/uc.c
@@ -93,7 +93,6 @@ int hfi1_make_uc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
93 goto done_free_tx; 93 goto done_free_tx;
94 } 94 }
95 95
96 ps->s_txreq->phdr.hdr.hdr_type = priv->hdr_type;
97 if (priv->hdr_type == HFI1_PKT_TYPE_9B) { 96 if (priv->hdr_type == HFI1_PKT_TYPE_9B) {
98 /* header size in 32-bit words LRH+BTH = (8+12)/4. */ 97 /* header size in 32-bit words LRH+BTH = (8+12)/4. */
99 hwords = 5; 98 hwords = 5;
@@ -463,7 +462,7 @@ last_imm:
463 wc.status = IB_WC_SUCCESS; 462 wc.status = IB_WC_SUCCESS;
464 wc.qp = &qp->ibqp; 463 wc.qp = &qp->ibqp;
465 wc.src_qp = qp->remote_qpn; 464 wc.src_qp = qp->remote_qpn;
466 wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr); 465 wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr) & U16_MAX;
467 /* 466 /*
468 * It seems that IB mandates the presence of an SL in a 467 * It seems that IB mandates the presence of an SL in a
469 * work completion only for the UD transport (see section 468 * work completion only for the UD transport (see section
diff --git a/drivers/infiniband/hw/hfi1/ud.c b/drivers/infiniband/hw/hfi1/ud.c
index 7fec6b984e3e..beb5091eccca 100644
--- a/drivers/infiniband/hw/hfi1/ud.c
+++ b/drivers/infiniband/hw/hfi1/ud.c
@@ -265,8 +265,8 @@ static void ud_loopback(struct rvt_qp *sqp, struct rvt_swqe *swqe)
265 } else { 265 } else {
266 wc.pkey_index = 0; 266 wc.pkey_index = 0;
267 } 267 }
268 wc.slid = ppd->lid | (rdma_ah_get_path_bits(ah_attr) & 268 wc.slid = (ppd->lid | (rdma_ah_get_path_bits(ah_attr) &
269 ((1 << ppd->lmc) - 1)); 269 ((1 << ppd->lmc) - 1))) & U16_MAX;
270 /* Check for loopback when the port lid is not set */ 270 /* Check for loopback when the port lid is not set */
271 if (wc.slid == 0 && sqp->ibqp.qp_type == IB_QPT_GSI) 271 if (wc.slid == 0 && sqp->ibqp.qp_type == IB_QPT_GSI)
272 wc.slid = be16_to_cpu(IB_LID_PERMISSIVE); 272 wc.slid = be16_to_cpu(IB_LID_PERMISSIVE);
@@ -854,7 +854,6 @@ void hfi1_ud_rcv(struct hfi1_packet *packet)
854 int mgmt_pkey_idx = -1; 854 int mgmt_pkey_idx = -1;
855 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd); 855 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
856 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 856 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
857 struct ib_header *hdr = packet->hdr;
858 void *data = packet->payload; 857 void *data = packet->payload;
859 u32 tlen = packet->tlen; 858 u32 tlen = packet->tlen;
860 struct rvt_qp *qp = packet->qp; 859 struct rvt_qp *qp = packet->qp;
@@ -880,7 +879,6 @@ void hfi1_ud_rcv(struct hfi1_packet *packet)
880 dlid_is_permissive = (dlid == permissive_lid); 879 dlid_is_permissive = (dlid == permissive_lid);
881 slid_is_permissive = (slid == permissive_lid); 880 slid_is_permissive = (slid == permissive_lid);
882 } else { 881 } else {
883 hdr = packet->hdr;
884 pkey = ib_bth_get_pkey(ohdr); 882 pkey = ib_bth_get_pkey(ohdr);
885 dlid_is_permissive = (dlid == be16_to_cpu(IB_LID_PERMISSIVE)); 883 dlid_is_permissive = (dlid == be16_to_cpu(IB_LID_PERMISSIVE));
886 slid_is_permissive = (slid == be16_to_cpu(IB_LID_PERMISSIVE)); 884 slid_is_permissive = (slid == be16_to_cpu(IB_LID_PERMISSIVE));
@@ -1039,7 +1037,7 @@ void hfi1_ud_rcv(struct hfi1_packet *packet)
1039 } 1037 }
1040 if (slid_is_permissive) 1038 if (slid_is_permissive)
1041 slid = be32_to_cpu(OPA_LID_PERMISSIVE); 1039 slid = be32_to_cpu(OPA_LID_PERMISSIVE);
1042 wc.slid = slid; 1040 wc.slid = slid & U16_MAX;
1043 wc.sl = sl_from_sc; 1041 wc.sl = sl_from_sc;
1044 1042
1045 /* 1043 /*
diff --git a/drivers/infiniband/hw/hfi1/user_exp_rcv.c b/drivers/infiniband/hw/hfi1/user_exp_rcv.c
index 6f6c14df383e..c1c596adcd01 100644
--- a/drivers/infiniband/hw/hfi1/user_exp_rcv.c
+++ b/drivers/infiniband/hw/hfi1/user_exp_rcv.c
@@ -542,14 +542,10 @@ int hfi1_user_exp_rcv_invalid(struct hfi1_filedata *fd,
542{ 542{
543 struct hfi1_ctxtdata *uctxt = fd->uctxt; 543 struct hfi1_ctxtdata *uctxt = fd->uctxt;
544 unsigned long *ev = uctxt->dd->events + 544 unsigned long *ev = uctxt->dd->events +
545 (((uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) * 545 (uctxt_offset(uctxt) + fd->subctxt);
546 HFI1_MAX_SHARED_CTXTS) + fd->subctxt);
547 u32 *array; 546 u32 *array;
548 int ret = 0; 547 int ret = 0;
549 548
550 if (!fd->invalid_tids)
551 return -EINVAL;
552
553 /* 549 /*
554 * copy_to_user() can sleep, which will leave the invalid_lock 550 * copy_to_user() can sleep, which will leave the invalid_lock
555 * locked and cause the MMU notifier to be blocked on the lock 551 * locked and cause the MMU notifier to be blocked on the lock
@@ -942,8 +938,7 @@ static int tid_rb_invalidate(void *arg, struct mmu_rb_node *mnode)
942 * process in question. 938 * process in question.
943 */ 939 */
944 ev = uctxt->dd->events + 940 ev = uctxt->dd->events +
945 (((uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) * 941 (uctxt_offset(uctxt) + fdata->subctxt);
946 HFI1_MAX_SHARED_CTXTS) + fdata->subctxt);
947 set_bit(_HFI1_EVENT_TID_MMU_NOTIFY_BIT, ev); 942 set_bit(_HFI1_EVENT_TID_MMU_NOTIFY_BIT, ev);
948 } 943 }
949 fdata->invalid_tid_idx++; 944 fdata->invalid_tid_idx++;
diff --git a/drivers/infiniband/hw/hfi1/user_sdma.c b/drivers/infiniband/hw/hfi1/user_sdma.c
index 8ec6e8a8d6f7..a3a7b33196d6 100644
--- a/drivers/infiniband/hw/hfi1/user_sdma.c
+++ b/drivers/infiniband/hw/hfi1/user_sdma.c
@@ -956,10 +956,8 @@ static int pin_sdma_pages(struct user_sdma_request *req,
956 struct hfi1_user_sdma_pkt_q *pq = req->pq; 956 struct hfi1_user_sdma_pkt_q *pq = req->pq;
957 957
958 pages = kcalloc(npages, sizeof(*pages), GFP_KERNEL); 958 pages = kcalloc(npages, sizeof(*pages), GFP_KERNEL);
959 if (!pages) { 959 if (!pages)
960 SDMA_DBG(req, "Failed page array alloc");
961 return -ENOMEM; 960 return -ENOMEM;
962 }
963 memcpy(pages, node->pages, node->npages * sizeof(*pages)); 961 memcpy(pages, node->pages, node->npages * sizeof(*pages));
964 962
965 npages -= node->npages; 963 npages -= node->npages;
@@ -1254,20 +1252,25 @@ static int set_txreq_header_ahg(struct user_sdma_request *req,
1254 struct user_sdma_txreq *tx, u32 datalen) 1252 struct user_sdma_txreq *tx, u32 datalen)
1255{ 1253{
1256 u32 ahg[AHG_KDETH_ARRAY_SIZE]; 1254 u32 ahg[AHG_KDETH_ARRAY_SIZE];
1257 int diff = 0; 1255 int idx = 0;
1258 u8 omfactor; /* KDETH.OM */ 1256 u8 omfactor; /* KDETH.OM */
1259 struct hfi1_user_sdma_pkt_q *pq = req->pq; 1257 struct hfi1_user_sdma_pkt_q *pq = req->pq;
1260 struct hfi1_pkt_header *hdr = &req->hdr; 1258 struct hfi1_pkt_header *hdr = &req->hdr;
1261 u16 pbclen = le16_to_cpu(hdr->pbc[0]); 1259 u16 pbclen = le16_to_cpu(hdr->pbc[0]);
1262 u32 val32, tidval = 0, lrhlen = get_lrh_len(*hdr, pad_len(datalen)); 1260 u32 val32, tidval = 0, lrhlen = get_lrh_len(*hdr, pad_len(datalen));
1261 size_t array_size = ARRAY_SIZE(ahg);
1263 1262
1264 if (PBC2LRH(pbclen) != lrhlen) { 1263 if (PBC2LRH(pbclen) != lrhlen) {
1265 /* PBC.PbcLengthDWs */ 1264 /* PBC.PbcLengthDWs */
1266 AHG_HEADER_SET(ahg, diff, 0, 0, 12, 1265 idx = ahg_header_set(ahg, idx, array_size, 0, 0, 12,
1267 cpu_to_le16(LRH2PBC(lrhlen))); 1266 (__force u16)cpu_to_le16(LRH2PBC(lrhlen)));
1267 if (idx < 0)
1268 return idx;
1268 /* LRH.PktLen (we need the full 16 bits due to byte swap) */ 1269 /* LRH.PktLen (we need the full 16 bits due to byte swap) */
1269 AHG_HEADER_SET(ahg, diff, 3, 0, 16, 1270 idx = ahg_header_set(ahg, idx, array_size, 3, 0, 16,
1270 cpu_to_be16(lrhlen >> 2)); 1271 (__force u16)cpu_to_be16(lrhlen >> 2));
1272 if (idx < 0)
1273 return idx;
1271 } 1274 }
1272 1275
1273 /* 1276 /*
@@ -1278,12 +1281,23 @@ static int set_txreq_header_ahg(struct user_sdma_request *req,
1278 (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffff : 0xffffff); 1281 (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffff : 0xffffff);
1279 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_ACK)) 1282 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_ACK))
1280 val32 |= 1UL << 31; 1283 val32 |= 1UL << 31;
1281 AHG_HEADER_SET(ahg, diff, 6, 0, 16, cpu_to_be16(val32 >> 16)); 1284 idx = ahg_header_set(ahg, idx, array_size, 6, 0, 16,
1282 AHG_HEADER_SET(ahg, diff, 6, 16, 16, cpu_to_be16(val32 & 0xffff)); 1285 (__force u16)cpu_to_be16(val32 >> 16));
1286 if (idx < 0)
1287 return idx;
1288 idx = ahg_header_set(ahg, idx, array_size, 6, 16, 16,
1289 (__force u16)cpu_to_be16(val32 & 0xffff));
1290 if (idx < 0)
1291 return idx;
1283 /* KDETH.Offset */ 1292 /* KDETH.Offset */
1284 AHG_HEADER_SET(ahg, diff, 15, 0, 16, 1293 idx = ahg_header_set(ahg, idx, array_size, 15, 0, 16,
1285 cpu_to_le16(req->koffset & 0xffff)); 1294 (__force u16)cpu_to_le16(req->koffset & 0xffff));
1286 AHG_HEADER_SET(ahg, diff, 15, 16, 16, cpu_to_le16(req->koffset >> 16)); 1295 if (idx < 0)
1296 return idx;
1297 idx = ahg_header_set(ahg, idx, array_size, 15, 16, 16,
1298 (__force u16)cpu_to_le16(req->koffset >> 16));
1299 if (idx < 0)
1300 return idx;
1287 if (req_opcode(req->info.ctrl) == EXPECTED) { 1301 if (req_opcode(req->info.ctrl) == EXPECTED) {
1288 __le16 val; 1302 __le16 val;
1289 1303
@@ -1310,10 +1324,13 @@ static int set_txreq_header_ahg(struct user_sdma_request *req,
1310 KDETH_OM_MAX_SIZE) ? KDETH_OM_LARGE_SHIFT : 1324 KDETH_OM_MAX_SIZE) ? KDETH_OM_LARGE_SHIFT :
1311 KDETH_OM_SMALL_SHIFT; 1325 KDETH_OM_SMALL_SHIFT;
1312 /* KDETH.OM and KDETH.OFFSET (TID) */ 1326 /* KDETH.OM and KDETH.OFFSET (TID) */
1313 AHG_HEADER_SET(ahg, diff, 7, 0, 16, 1327 idx = ahg_header_set(
1314 ((!!(omfactor - KDETH_OM_SMALL_SHIFT)) << 15 | 1328 ahg, idx, array_size, 7, 0, 16,
1329 ((!!(omfactor - KDETH_OM_SMALL_SHIFT)) << 15 |
1315 ((req->tidoffset >> omfactor) 1330 ((req->tidoffset >> omfactor)
1316 & 0x7fff))); 1331 & 0x7fff)));
1332 if (idx < 0)
1333 return idx;
1317 /* KDETH.TIDCtrl, KDETH.TID, KDETH.Intr, KDETH.SH */ 1334 /* KDETH.TIDCtrl, KDETH.TID, KDETH.Intr, KDETH.SH */
1318 val = cpu_to_le16(((EXP_TID_GET(tidval, CTRL) & 0x3) << 10) | 1335 val = cpu_to_le16(((EXP_TID_GET(tidval, CTRL) & 0x3) << 10) |
1319 (EXP_TID_GET(tidval, IDX) & 0x3ff)); 1336 (EXP_TID_GET(tidval, IDX) & 0x3ff));
@@ -1330,21 +1347,22 @@ static int set_txreq_header_ahg(struct user_sdma_request *req,
1330 AHG_KDETH_INTR_SHIFT)); 1347 AHG_KDETH_INTR_SHIFT));
1331 } 1348 }
1332 1349
1333 AHG_HEADER_SET(ahg, diff, 7, 16, 14, val); 1350 idx = ahg_header_set(ahg, idx, array_size,
1351 7, 16, 14, (__force u16)val);
1352 if (idx < 0)
1353 return idx;
1334 } 1354 }
1335 if (diff < 0)
1336 return diff;
1337 1355
1338 trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt, 1356 trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt,
1339 req->info.comp_idx, req->sde->this_idx, 1357 req->info.comp_idx, req->sde->this_idx,
1340 req->ahg_idx, ahg, diff, tidval); 1358 req->ahg_idx, ahg, idx, tidval);
1341 sdma_txinit_ahg(&tx->txreq, 1359 sdma_txinit_ahg(&tx->txreq,
1342 SDMA_TXREQ_F_USE_AHG, 1360 SDMA_TXREQ_F_USE_AHG,
1343 datalen, req->ahg_idx, diff, 1361 datalen, req->ahg_idx, idx,
1344 ahg, sizeof(req->hdr), 1362 ahg, sizeof(req->hdr),
1345 user_sdma_txreq_cb); 1363 user_sdma_txreq_cb);
1346 1364
1347 return diff; 1365 return idx;
1348} 1366}
1349 1367
1350/* 1368/*
@@ -1410,6 +1428,8 @@ static inline void pq_update(struct hfi1_user_sdma_pkt_q *pq)
1410 1428
1411static void user_sdma_free_request(struct user_sdma_request *req, bool unpin) 1429static void user_sdma_free_request(struct user_sdma_request *req, bool unpin)
1412{ 1430{
1431 int i;
1432
1413 if (!list_empty(&req->txps)) { 1433 if (!list_empty(&req->txps)) {
1414 struct sdma_txreq *t, *p; 1434 struct sdma_txreq *t, *p;
1415 1435
@@ -1421,22 +1441,20 @@ static void user_sdma_free_request(struct user_sdma_request *req, bool unpin)
1421 kmem_cache_free(req->pq->txreq_cache, tx); 1441 kmem_cache_free(req->pq->txreq_cache, tx);
1422 } 1442 }
1423 } 1443 }
1424 if (req->data_iovs) { 1444
1425 struct sdma_mmu_node *node; 1445 for (i = 0; i < req->data_iovs; i++) {
1426 int i; 1446 struct sdma_mmu_node *node = req->iovs[i].node;
1427 1447
1428 for (i = 0; i < req->data_iovs; i++) { 1448 if (!node)
1429 node = req->iovs[i].node; 1449 continue;
1430 if (!node) 1450
1431 continue; 1451 if (unpin)
1432 1452 hfi1_mmu_rb_remove(req->pq->handler,
1433 if (unpin) 1453 &node->rb);
1434 hfi1_mmu_rb_remove(req->pq->handler, 1454 else
1435 &node->rb); 1455 atomic_dec(&node->refcount);
1436 else
1437 atomic_dec(&node->refcount);
1438 }
1439 } 1456 }
1457
1440 kfree(req->tids); 1458 kfree(req->tids);
1441 clear_bit(req->info.comp_idx, req->pq->req_in_use); 1459 clear_bit(req->info.comp_idx, req->pq->req_in_use);
1442} 1460}
diff --git a/drivers/infiniband/hw/hfi1/user_sdma.h b/drivers/infiniband/hw/hfi1/user_sdma.h
index 9b8bb5634c0d..a3d192424344 100644
--- a/drivers/infiniband/hw/hfi1/user_sdma.h
+++ b/drivers/infiniband/hw/hfi1/user_sdma.h
@@ -80,15 +80,26 @@
80#define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4) 80#define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
81#define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff) 81#define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff)
82 82
83#define AHG_HEADER_SET(arr, idx, dw, bit, width, value) \ 83/**
84 do { \ 84 * Build an SDMA AHG header update descriptor and save it to an array.
85 if ((idx) < ARRAY_SIZE((arr))) \ 85 * @arr - Array to save the descriptor to.
86 (arr)[(idx++)] = sdma_build_ahg_descriptor( \ 86 * @idx - Index of the array at which the descriptor will be saved.
87 (__force u16)(value), (dw), (bit), \ 87 * @array_size - Size of the array arr.
88 (width)); \ 88 * @dw - Update index into the header in DWs.
89 else \ 89 * @bit - Start bit.
90 return -ERANGE; \ 90 * @width - Field width.
91 } while (0) 91 * @value - 16 bits of immediate data to write into the field.
92 * Returns -ERANGE if idx is invalid. If successful, returns the next index
93 * (idx + 1) of the array to be used for the next descriptor.
94 */
95static inline int ahg_header_set(u32 *arr, int idx, size_t array_size,
96 u8 dw, u8 bit, u8 width, u16 value)
97{
98 if ((size_t)idx >= array_size)
99 return -ERANGE;
100 arr[idx++] = sdma_build_ahg_descriptor(value, dw, bit, width);
101 return idx;
102}
92 103
93/* Tx request flag bits */ 104/* Tx request flag bits */
94#define TXREQ_FLAGS_REQ_ACK BIT(0) /* Set the ACK bit in the header */ 105#define TXREQ_FLAGS_REQ_ACK BIT(0) /* Set the ACK bit in the header */
diff --git a/drivers/infiniband/hw/hfi1/verbs.c b/drivers/infiniband/hw/hfi1/verbs.c
index e232f3c608b4..a38785e224cc 100644
--- a/drivers/infiniband/hw/hfi1/verbs.c
+++ b/drivers/infiniband/hw/hfi1/verbs.c
@@ -146,6 +146,9 @@ static int pio_wait(struct rvt_qp *qp,
146/* Length of buffer to create verbs txreq cache name */ 146/* Length of buffer to create verbs txreq cache name */
147#define TXREQ_NAME_LEN 24 147#define TXREQ_NAME_LEN 24
148 148
149/* 16B trailing buffer */
150static const u8 trail_buf[MAX_16B_PADDING];
151
149static uint wss_threshold; 152static uint wss_threshold;
150module_param(wss_threshold, uint, S_IRUGO); 153module_param(wss_threshold, uint, S_IRUGO);
151MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy"); 154MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
@@ -667,9 +670,9 @@ void hfi1_16B_rcv(struct hfi1_packet *packet)
667 * This is called from a timer to check for QPs 670 * This is called from a timer to check for QPs
668 * which need kernel memory in order to send a packet. 671 * which need kernel memory in order to send a packet.
669 */ 672 */
670static void mem_timer(unsigned long data) 673static void mem_timer(struct timer_list *t)
671{ 674{
672 struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data; 675 struct hfi1_ibdev *dev = from_timer(dev, t, mem_timer);
673 struct list_head *list = &dev->memwait; 676 struct list_head *list = &dev->memwait;
674 struct rvt_qp *qp = NULL; 677 struct rvt_qp *qp = NULL;
675 struct iowait *wait; 678 struct iowait *wait;
@@ -793,6 +796,27 @@ bail_txadd:
793 return ret; 796 return ret;
794} 797}
795 798
799/**
800 * update_tx_opstats - record stats by opcode
801 * @qp; the qp
802 * @ps: transmit packet state
803 * @plen: the plen in dwords
804 *
805 * This is a routine to record the tx opstats after a
806 * packet has been presented to the egress mechanism.
807 */
808static void update_tx_opstats(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
809 u32 plen)
810{
811#ifdef CONFIG_DEBUG_FS
812 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
813 struct hfi1_opcode_stats_perctx *s = get_cpu_ptr(dd->tx_opstats);
814
815 inc_opstats(plen * 4, &s->stats[ps->opcode]);
816 put_cpu_ptr(s);
817#endif
818}
819
796/* 820/*
797 * Build the number of DMA descriptors needed to send length bytes of data. 821 * Build the number of DMA descriptors needed to send length bytes of data.
798 * 822 *
@@ -812,9 +836,7 @@ static int build_verbs_tx_desc(
812 int ret = 0; 836 int ret = 0;
813 struct hfi1_sdma_header *phdr = &tx->phdr; 837 struct hfi1_sdma_header *phdr = &tx->phdr;
814 u16 hdrbytes = tx->hdr_dwords << 2; 838 u16 hdrbytes = tx->hdr_dwords << 2;
815 u32 *hdr;
816 u8 extra_bytes = 0; 839 u8 extra_bytes = 0;
817 static char trail_buf[12]; /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
818 840
819 if (tx->phdr.hdr.hdr_type) { 841 if (tx->phdr.hdr.hdr_type) {
820 /* 842 /*
@@ -823,9 +845,6 @@ static int build_verbs_tx_desc(
823 */ 845 */
824 extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) + 846 extra_bytes = hfi1_get_16b_padding(hdrbytes - 8, length) +
825 (SIZE_OF_CRC << 2) + SIZE_OF_LT; 847 (SIZE_OF_CRC << 2) + SIZE_OF_LT;
826 hdr = (u32 *)&phdr->hdr.opah;
827 } else {
828 hdr = (u32 *)&phdr->hdr.ibh;
829 } 848 }
830 if (!ahg_info->ahgcount) { 849 if (!ahg_info->ahgcount) {
831 ret = sdma_txinit_ahg( 850 ret = sdma_txinit_ahg(
@@ -869,9 +888,9 @@ static int build_verbs_tx_desc(
869 } 888 }
870 889
871 /* add icrc, lt byte, and padding to flit */ 890 /* add icrc, lt byte, and padding to flit */
872 if (extra_bytes != 0) 891 if (extra_bytes)
873 ret = sdma_txadd_kvaddr(sde->dd, &tx->txreq, 892 ret = sdma_txadd_kvaddr(sde->dd, &tx->txreq,
874 trail_buf, extra_bytes); 893 (void *)trail_buf, extra_bytes);
875 894
876bail_txadd: 895bail_txadd:
877 return ret; 896 return ret;
@@ -891,14 +910,12 @@ int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
891 u8 sc5 = priv->s_sc; 910 u8 sc5 = priv->s_sc;
892 int ret; 911 int ret;
893 u32 dwords; 912 u32 dwords;
894 bool bypass = false;
895 913
896 if (ps->s_txreq->phdr.hdr.hdr_type) { 914 if (ps->s_txreq->phdr.hdr.hdr_type) {
897 u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len); 915 u8 extra_bytes = hfi1_get_16b_padding((hdrwords << 2), len);
898 916
899 dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) + 917 dwords = (len + extra_bytes + (SIZE_OF_CRC << 2) +
900 SIZE_OF_LT) >> 2; 918 SIZE_OF_LT) >> 2;
901 bypass = true;
902 } else { 919 } else {
903 dwords = (len + 3) >> 2; 920 dwords = (len + 3) >> 2;
904 } 921 }
@@ -938,6 +955,8 @@ int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
938 goto bail_ecomm; 955 goto bail_ecomm;
939 return ret; 956 return ret;
940 } 957 }
958
959 update_tx_opstats(qp, ps, plen);
941 trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device), 960 trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
942 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5)); 961 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
943 return ret; 962 return ret;
@@ -1033,8 +1052,6 @@ int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1033 int wc_status = IB_WC_SUCCESS; 1052 int wc_status = IB_WC_SUCCESS;
1034 int ret = 0; 1053 int ret = 0;
1035 pio_release_cb cb = NULL; 1054 pio_release_cb cb = NULL;
1036 u32 lrh0_16b;
1037 bool bypass = false;
1038 u8 extra_bytes = 0; 1055 u8 extra_bytes = 0;
1039 1056
1040 if (ps->s_txreq->phdr.hdr.hdr_type) { 1057 if (ps->s_txreq->phdr.hdr.hdr_type) {
@@ -1043,8 +1060,6 @@ int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1043 extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT; 1060 extra_bytes = pad_size + (SIZE_OF_CRC << 2) + SIZE_OF_LT;
1044 dwords = (len + extra_bytes) >> 2; 1061 dwords = (len + extra_bytes) >> 2;
1045 hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah; 1062 hdr = (u32 *)&ps->s_txreq->phdr.hdr.opah;
1046 lrh0_16b = ps->s_txreq->phdr.hdr.opah.lrh[0];
1047 bypass = true;
1048 } else { 1063 } else {
1049 dwords = (len + 3) >> 2; 1064 dwords = (len + 3) >> 2;
1050 hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh; 1065 hdr = (u32 *)&ps->s_txreq->phdr.hdr.ibh;
@@ -1128,21 +1143,14 @@ int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1128 len -= slen; 1143 len -= slen;
1129 } 1144 }
1130 } 1145 }
1131 /* 1146 /* add icrc, lt byte, and padding to flit */
1132 * Bypass packet will need to copy additional 1147 if (extra_bytes)
1133 * bytes to accommodate for CRC and LT bytes 1148 seg_pio_copy_mid(pbuf, trail_buf, extra_bytes);
1134 */
1135 if (extra_bytes) {
1136 u8 *empty_buf;
1137 1149
1138 empty_buf = kcalloc(extra_bytes, sizeof(u8),
1139 GFP_KERNEL);
1140 seg_pio_copy_mid(pbuf, empty_buf, extra_bytes);
1141 kfree(empty_buf);
1142 }
1143 seg_pio_copy_end(pbuf); 1150 seg_pio_copy_end(pbuf);
1144 } 1151 }
1145 1152
1153 update_tx_opstats(qp, ps, plen);
1146 trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device), 1154 trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1147 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5)); 1155 &ps->s_txreq->phdr.hdr, ib_is_sc5(sc5));
1148 1156
@@ -1636,8 +1644,7 @@ static void init_ibport(struct hfi1_pportdata *ppd)
1636 1644
1637 for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++) 1645 for (i = 0; i < RVT_MAX_TRAP_LISTS ; i++)
1638 INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list); 1646 INIT_LIST_HEAD(&ibp->rvp.trap_lists[i].list);
1639 setup_timer(&ibp->rvp.trap_timer, hfi1_handle_trap_timer, 1647 timer_setup(&ibp->rvp.trap_timer, hfi1_handle_trap_timer, 0);
1640 (unsigned long)ibp);
1641 1648
1642 spin_lock_init(&ibp->rvp.lock); 1649 spin_lock_init(&ibp->rvp.lock);
1643 /* Set the prefix to the default value (see ch. 4.1.1) */ 1650 /* Set the prefix to the default value (see ch. 4.1.1) */
@@ -1844,7 +1851,7 @@ int hfi1_register_ib_device(struct hfi1_devdata *dd)
1844 1851
1845 /* Only need to initialize non-zero fields. */ 1852 /* Only need to initialize non-zero fields. */
1846 1853
1847 setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev); 1854 timer_setup(&dev->mem_timer, mem_timer, 0);
1848 1855
1849 seqlock_init(&dev->iowait_lock); 1856 seqlock_init(&dev->iowait_lock);
1850 seqlock_init(&dev->txwait_lock); 1857 seqlock_init(&dev->txwait_lock);
diff --git a/drivers/infiniband/hw/hfi1/verbs_txreq.h b/drivers/infiniband/hw/hfi1/verbs_txreq.h
index 76216f2ef35a..cec7a4b34d16 100644
--- a/drivers/infiniband/hw/hfi1/verbs_txreq.h
+++ b/drivers/infiniband/hw/hfi1/verbs_txreq.h
@@ -92,6 +92,8 @@ static inline struct verbs_txreq *get_txreq(struct hfi1_ibdev *dev,
92 tx->psc = priv->s_sendcontext; 92 tx->psc = priv->s_sendcontext;
93 /* so that we can test if the sdma decriptors are there */ 93 /* so that we can test if the sdma decriptors are there */
94 tx->txreq.num_desc = 0; 94 tx->txreq.num_desc = 0;
95 /* Set the header type */
96 tx->phdr.hdr.hdr_type = priv->hdr_type;
95 return tx; 97 return tx;
96} 98}
97 99
diff --git a/drivers/infiniband/hw/hfi1/vnic_main.c b/drivers/infiniband/hw/hfi1/vnic_main.c
index f419cbb05928..5d65582fe4d9 100644
--- a/drivers/infiniband/hw/hfi1/vnic_main.c
+++ b/drivers/infiniband/hw/hfi1/vnic_main.c
@@ -67,8 +67,6 @@ static int setup_vnic_ctxt(struct hfi1_devdata *dd, struct hfi1_ctxtdata *uctxt)
67 unsigned int rcvctrl_ops = 0; 67 unsigned int rcvctrl_ops = 0;
68 int ret; 68 int ret;
69 69
70 hfi1_init_ctxt(uctxt->sc);
71
72 uctxt->do_interrupt = &handle_receive_interrupt; 70 uctxt->do_interrupt = &handle_receive_interrupt;
73 71
74 /* Now allocate the RcvHdr queue and eager buffers. */ 72 /* Now allocate the RcvHdr queue and eager buffers. */
@@ -96,8 +94,6 @@ static int setup_vnic_ctxt(struct hfi1_devdata *dd, struct hfi1_ctxtdata *uctxt)
96 rcvctrl_ops |= HFI1_RCVCTRL_TAILUPD_ENB; 94 rcvctrl_ops |= HFI1_RCVCTRL_TAILUPD_ENB;
97 95
98 hfi1_rcvctrl(uctxt->dd, rcvctrl_ops, uctxt); 96 hfi1_rcvctrl(uctxt->dd, rcvctrl_ops, uctxt);
99
100 uctxt->is_vnic = true;
101done: 97done:
102 return ret; 98 return ret;
103} 99}
@@ -122,20 +118,7 @@ static int allocate_vnic_ctxt(struct hfi1_devdata *dd,
122 HFI1_CAP_KGET(NODROP_EGR_FULL) | 118 HFI1_CAP_KGET(NODROP_EGR_FULL) |
123 HFI1_CAP_KGET(DMA_RTAIL); 119 HFI1_CAP_KGET(DMA_RTAIL);
124 uctxt->seq_cnt = 1; 120 uctxt->seq_cnt = 1;
125 121 uctxt->is_vnic = true;
126 /* Allocate and enable a PIO send context */
127 uctxt->sc = sc_alloc(dd, SC_VNIC, uctxt->rcvhdrqentsize,
128 uctxt->numa_id);
129
130 ret = uctxt->sc ? 0 : -ENOMEM;
131 if (ret)
132 goto bail;
133
134 dd_dev_dbg(dd, "allocated vnic send context %u(%u)\n",
135 uctxt->sc->sw_index, uctxt->sc->hw_context);
136 ret = sc_enable(uctxt->sc);
137 if (ret)
138 goto bail;
139 122
140 if (dd->num_msix_entries) 123 if (dd->num_msix_entries)
141 hfi1_set_vnic_msix_info(uctxt); 124 hfi1_set_vnic_msix_info(uctxt);
@@ -144,11 +127,7 @@ static int allocate_vnic_ctxt(struct hfi1_devdata *dd,
144 dd_dev_dbg(dd, "created vnic context %d\n", uctxt->ctxt); 127 dd_dev_dbg(dd, "created vnic context %d\n", uctxt->ctxt);
145 *vnic_ctxt = uctxt; 128 *vnic_ctxt = uctxt;
146 129
147 return ret; 130 return 0;
148bail:
149 hfi1_free_ctxt(uctxt);
150 dd_dev_dbg(dd, "vnic allocation failed. rc %d\n", ret);
151 return ret;
152} 131}
153 132
154static void deallocate_vnic_ctxt(struct hfi1_devdata *dd, 133static void deallocate_vnic_ctxt(struct hfi1_devdata *dd,
@@ -170,18 +149,6 @@ static void deallocate_vnic_ctxt(struct hfi1_devdata *dd,
170 HFI1_RCVCTRL_ONE_PKT_EGR_DIS | 149 HFI1_RCVCTRL_ONE_PKT_EGR_DIS |
171 HFI1_RCVCTRL_NO_RHQ_DROP_DIS | 150 HFI1_RCVCTRL_NO_RHQ_DROP_DIS |
172 HFI1_RCVCTRL_NO_EGR_DROP_DIS, uctxt); 151 HFI1_RCVCTRL_NO_EGR_DROP_DIS, uctxt);
173 /*
174 * VNIC contexts are allocated from user context pool.
175 * Release them back to user context pool.
176 *
177 * Reset context integrity checks to default.
178 * (writes to CSRs probably belong in chip.c)
179 */
180 write_kctxt_csr(dd, uctxt->sc->hw_context, SEND_CTXT_CHECK_ENABLE,
181 hfi1_pkt_default_send_ctxt_mask(dd, SC_USER));
182 sc_disable(uctxt->sc);
183
184 dd->send_contexts[uctxt->sc->sw_index].type = SC_USER;
185 152
186 uctxt->event_flags = 0; 153 uctxt->event_flags = 0;
187 154
@@ -840,6 +807,9 @@ struct net_device *hfi1_vnic_alloc_rn(struct ib_device *device,
840 struct rdma_netdev *rn; 807 struct rdma_netdev *rn;
841 int i, size, rc; 808 int i, size, rc;
842 809
810 if (!dd->num_vnic_contexts)
811 return ERR_PTR(-ENOMEM);
812
843 if (!port_num || (port_num > dd->num_pports)) 813 if (!port_num || (port_num > dd->num_pports))
844 return ERR_PTR(-EINVAL); 814 return ERR_PTR(-EINVAL);
845 815
@@ -848,7 +818,7 @@ struct net_device *hfi1_vnic_alloc_rn(struct ib_device *device,
848 818
849 size = sizeof(struct opa_vnic_rdma_netdev) + sizeof(*vinfo); 819 size = sizeof(struct opa_vnic_rdma_netdev) + sizeof(*vinfo);
850 netdev = alloc_netdev_mqs(size, name, name_assign_type, setup, 820 netdev = alloc_netdev_mqs(size, name, name_assign_type, setup,
851 dd->chip_sdma_engines, HFI1_NUM_VNIC_CTXT); 821 dd->chip_sdma_engines, dd->num_vnic_contexts);
852 if (!netdev) 822 if (!netdev)
853 return ERR_PTR(-ENOMEM); 823 return ERR_PTR(-ENOMEM);
854 824
@@ -856,7 +826,7 @@ struct net_device *hfi1_vnic_alloc_rn(struct ib_device *device,
856 vinfo = opa_vnic_dev_priv(netdev); 826 vinfo = opa_vnic_dev_priv(netdev);
857 vinfo->dd = dd; 827 vinfo->dd = dd;
858 vinfo->num_tx_q = dd->chip_sdma_engines; 828 vinfo->num_tx_q = dd->chip_sdma_engines;
859 vinfo->num_rx_q = HFI1_NUM_VNIC_CTXT; 829 vinfo->num_rx_q = dd->num_vnic_contexts;
860 vinfo->netdev = netdev; 830 vinfo->netdev = netdev;
861 rn->free_rdma_netdev = hfi1_vnic_free_rn; 831 rn->free_rdma_netdev = hfi1_vnic_free_rn;
862 rn->set_id = hfi1_vnic_set_vesw_id; 832 rn->set_id = hfi1_vnic_set_vesw_id;
diff --git a/drivers/infiniband/hw/hns/Kconfig b/drivers/infiniband/hw/hns/Kconfig
index 61c93bbd230d..fddb5fdf92de 100644
--- a/drivers/infiniband/hw/hns/Kconfig
+++ b/drivers/infiniband/hw/hns/Kconfig
@@ -1,10 +1,31 @@
1config INFINIBAND_HNS 1config INFINIBAND_HNS
2 tristate "HNS RoCE Driver" 2 tristate "HNS RoCE Driver"
3 depends on NET_VENDOR_HISILICON 3 depends on NET_VENDOR_HISILICON
4 depends on (ARM64 || (COMPILE_TEST && 64BIT)) && HNS && HNS_DSAF && HNS_ENET 4 depends on ARM64 || (COMPILE_TEST && 64BIT)
5 ---help--- 5 ---help---
6 This is a RoCE/RDMA driver for the Hisilicon RoCE engine. The engine 6 This is a RoCE/RDMA driver for the Hisilicon RoCE engine. The engine
7 is used in Hisilicon Hi1610 and more further ICT SoC. 7 is used in Hisilicon Hip06 and more further ICT SoC based on
8 platform device.
8 9
9 To compile this driver as a module, choose M here: the module 10 To compile this driver as a module, choose M here: the module
10 will be called hns-roce. 11 will be called hns-roce.
12
13config INFINIBAND_HNS_HIP06
14 tristate "Hisilicon Hip06 Family RoCE support"
15 depends on INFINIBAND_HNS && HNS && HNS_DSAF && HNS_ENET
16 ---help---
17 RoCE driver support for Hisilicon RoCE engine in Hisilicon Hip06 and
18 Hip07 SoC. These RoCE engines are platform devices.
19
20 To compile this driver as a module, choose M here: the module
21 will be called hns-roce-hw-v1.
22
23config INFINIBAND_HNS_HIP08
24 tristate "Hisilicon Hip08 Family RoCE support"
25 depends on INFINIBAND_HNS && PCI && HNS3
26 ---help---
27 RoCE driver support for Hisilicon RoCE engine in Hisilicon Hip08 SoC.
28 The RoCE engine is a PCI device.
29
30 To compile this driver as a module, choose M here: the module
31 will be called hns-roce-hw-v2.
diff --git a/drivers/infiniband/hw/hns/Makefile b/drivers/infiniband/hw/hns/Makefile
index 7e8ebd24dcae..ff426a625e13 100644
--- a/drivers/infiniband/hw/hns/Makefile
+++ b/drivers/infiniband/hw/hns/Makefile
@@ -2,7 +2,13 @@
2# Makefile for the Hisilicon RoCE drivers. 2# Makefile for the Hisilicon RoCE drivers.
3# 3#
4 4
5ccflags-y := -Idrivers/net/ethernet/hisilicon/hns3
6
5obj-$(CONFIG_INFINIBAND_HNS) += hns-roce.o 7obj-$(CONFIG_INFINIBAND_HNS) += hns-roce.o
6hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_eq.o hns_roce_pd.o \ 8hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_eq.o hns_roce_pd.o \
7 hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \ 9 hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \
8 hns_roce_cq.o hns_roce_alloc.o hns_roce_hw_v1.o 10 hns_roce_cq.o hns_roce_alloc.o
11obj-$(CONFIG_INFINIBAND_HNS_HIP06) += hns-roce-hw-v1.o
12hns-roce-hw-v1-objs := hns_roce_hw_v1.o
13obj-$(CONFIG_INFINIBAND_HNS_HIP08) += hns-roce-hw-v2.o
14hns-roce-hw-v2-objs := hns_roce_hw_v2.o
diff --git a/drivers/infiniband/hw/hns/hns_roce_ah.c b/drivers/infiniband/hw/hns/hns_roce_ah.c
index d545302b8ef8..7dd6a66ea244 100644
--- a/drivers/infiniband/hw/hns/hns_roce_ah.c
+++ b/drivers/infiniband/hw/hns/hns_roce_ah.c
@@ -44,11 +44,10 @@ struct ib_ah *hns_roce_create_ah(struct ib_pd *ibpd,
44 struct ib_udata *udata) 44 struct ib_udata *udata)
45{ 45{
46 struct hns_roce_dev *hr_dev = to_hr_dev(ibpd->device); 46 struct hns_roce_dev *hr_dev = to_hr_dev(ibpd->device);
47 struct device *dev = &hr_dev->pdev->dev; 47 struct device *dev = hr_dev->dev;
48 struct ib_gid_attr gid_attr; 48 struct ib_gid_attr gid_attr;
49 struct hns_roce_ah *ah; 49 struct hns_roce_ah *ah;
50 u16 vlan_tag = 0xffff; 50 u16 vlan_tag = 0xffff;
51 struct in6_addr in6;
52 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 51 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
53 union ib_gid sgid; 52 union ib_gid sgid;
54 int ret; 53 int ret;
@@ -58,18 +57,7 @@ struct ib_ah *hns_roce_create_ah(struct ib_pd *ibpd,
58 return ERR_PTR(-ENOMEM); 57 return ERR_PTR(-ENOMEM);
59 58
60 /* Get mac address */ 59 /* Get mac address */
61 memcpy(&in6, grh->dgid.raw, sizeof(grh->dgid.raw)); 60 memcpy(ah->av.mac, ah_attr->roce.dmac, ETH_ALEN);
62 if (rdma_is_multicast_addr(&in6)) {
63 rdma_get_mcast_mac(&in6, ah->av.mac);
64 } else {
65 u8 *dmac = rdma_ah_retrieve_dmac(ah_attr);
66
67 if (!dmac) {
68 kfree(ah);
69 return ERR_PTR(-EINVAL);
70 }
71 memcpy(ah->av.mac, dmac, ETH_ALEN);
72 }
73 61
74 /* Get source gid */ 62 /* Get source gid */
75 ret = ib_get_cached_gid(ibpd->device, rdma_ah_get_port_num(ah_attr), 63 ret = ib_get_cached_gid(ibpd->device, rdma_ah_get_port_num(ah_attr),
diff --git a/drivers/infiniband/hw/hns/hns_roce_alloc.c b/drivers/infiniband/hw/hns/hns_roce_alloc.c
index e1b433cdd5e2..3e4c5253ab5c 100644
--- a/drivers/infiniband/hw/hns/hns_roce_alloc.c
+++ b/drivers/infiniband/hw/hns/hns_roce_alloc.c
@@ -67,6 +67,7 @@ void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
67{ 67{
68 hns_roce_bitmap_free_range(bitmap, obj, 1, rr); 68 hns_roce_bitmap_free_range(bitmap, obj, 1, rr);
69} 69}
70EXPORT_SYMBOL_GPL(hns_roce_bitmap_free);
70 71
71int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 72int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
72 int align, unsigned long *obj) 73 int align, unsigned long *obj)
@@ -160,39 +161,47 @@ void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
160 struct hns_roce_buf *buf) 161 struct hns_roce_buf *buf)
161{ 162{
162 int i; 163 int i;
163 struct device *dev = &hr_dev->pdev->dev; 164 struct device *dev = hr_dev->dev;
164 u32 bits_per_long = BITS_PER_LONG; 165 u32 bits_per_long = BITS_PER_LONG;
165 166
166 if (buf->nbufs == 1) { 167 if (buf->nbufs == 1) {
167 dma_free_coherent(dev, size, buf->direct.buf, buf->direct.map); 168 dma_free_coherent(dev, size, buf->direct.buf, buf->direct.map);
168 } else { 169 } else {
169 if (bits_per_long == 64) 170 if (bits_per_long == 64 && buf->page_shift == PAGE_SHIFT)
170 vunmap(buf->direct.buf); 171 vunmap(buf->direct.buf);
171 172
172 for (i = 0; i < buf->nbufs; ++i) 173 for (i = 0; i < buf->nbufs; ++i)
173 if (buf->page_list[i].buf) 174 if (buf->page_list[i].buf)
174 dma_free_coherent(&hr_dev->pdev->dev, PAGE_SIZE, 175 dma_free_coherent(dev, 1 << buf->page_shift,
175 buf->page_list[i].buf, 176 buf->page_list[i].buf,
176 buf->page_list[i].map); 177 buf->page_list[i].map);
177 kfree(buf->page_list); 178 kfree(buf->page_list);
178 } 179 }
179} 180}
181EXPORT_SYMBOL_GPL(hns_roce_buf_free);
180 182
181int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 183int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
182 struct hns_roce_buf *buf) 184 struct hns_roce_buf *buf, u32 page_shift)
183{ 185{
184 int i = 0; 186 int i = 0;
185 dma_addr_t t; 187 dma_addr_t t;
186 struct page **pages; 188 struct page **pages;
187 struct device *dev = &hr_dev->pdev->dev; 189 struct device *dev = hr_dev->dev;
188 u32 bits_per_long = BITS_PER_LONG; 190 u32 bits_per_long = BITS_PER_LONG;
191 u32 page_size = 1 << page_shift;
192 u32 order;
189 193
190 /* SQ/RQ buf lease than one page, SQ + RQ = 8K */ 194 /* SQ/RQ buf lease than one page, SQ + RQ = 8K */
191 if (size <= max_direct) { 195 if (size <= max_direct) {
192 buf->nbufs = 1; 196 buf->nbufs = 1;
193 /* Npages calculated by page_size */ 197 /* Npages calculated by page_size */
194 buf->npages = 1 << get_order(size); 198 order = get_order(size);
195 buf->page_shift = PAGE_SHIFT; 199 if (order <= page_shift - PAGE_SHIFT)
200 order = 0;
201 else
202 order -= page_shift - PAGE_SHIFT;
203 buf->npages = 1 << order;
204 buf->page_shift = page_shift;
196 /* MTT PA must be recorded in 4k alignment, t is 4k aligned */ 205 /* MTT PA must be recorded in 4k alignment, t is 4k aligned */
197 buf->direct.buf = dma_alloc_coherent(dev, size, &t, GFP_KERNEL); 206 buf->direct.buf = dma_alloc_coherent(dev, size, &t, GFP_KERNEL);
198 if (!buf->direct.buf) 207 if (!buf->direct.buf)
@@ -207,9 +216,9 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
207 216
208 memset(buf->direct.buf, 0, size); 217 memset(buf->direct.buf, 0, size);
209 } else { 218 } else {
210 buf->nbufs = (size + PAGE_SIZE - 1) / PAGE_SIZE; 219 buf->nbufs = (size + page_size - 1) / page_size;
211 buf->npages = buf->nbufs; 220 buf->npages = buf->nbufs;
212 buf->page_shift = PAGE_SHIFT; 221 buf->page_shift = page_shift;
213 buf->page_list = kcalloc(buf->nbufs, sizeof(*buf->page_list), 222 buf->page_list = kcalloc(buf->nbufs, sizeof(*buf->page_list),
214 GFP_KERNEL); 223 GFP_KERNEL);
215 224
@@ -218,16 +227,16 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
218 227
219 for (i = 0; i < buf->nbufs; ++i) { 228 for (i = 0; i < buf->nbufs; ++i) {
220 buf->page_list[i].buf = dma_alloc_coherent(dev, 229 buf->page_list[i].buf = dma_alloc_coherent(dev,
221 PAGE_SIZE, &t, 230 page_size, &t,
222 GFP_KERNEL); 231 GFP_KERNEL);
223 232
224 if (!buf->page_list[i].buf) 233 if (!buf->page_list[i].buf)
225 goto err_free; 234 goto err_free;
226 235
227 buf->page_list[i].map = t; 236 buf->page_list[i].map = t;
228 memset(buf->page_list[i].buf, 0, PAGE_SIZE); 237 memset(buf->page_list[i].buf, 0, page_size);
229 } 238 }
230 if (bits_per_long == 64) { 239 if (bits_per_long == 64 && page_shift == PAGE_SHIFT) {
231 pages = kmalloc_array(buf->nbufs, sizeof(*pages), 240 pages = kmalloc_array(buf->nbufs, sizeof(*pages),
232 GFP_KERNEL); 241 GFP_KERNEL);
233 if (!pages) 242 if (!pages)
@@ -241,6 +250,8 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
241 kfree(pages); 250 kfree(pages);
242 if (!buf->direct.buf) 251 if (!buf->direct.buf)
243 goto err_free; 252 goto err_free;
253 } else {
254 buf->direct.buf = NULL;
244 } 255 }
245 } 256 }
246 257
diff --git a/drivers/infiniband/hw/hns/hns_roce_cmd.c b/drivers/infiniband/hw/hns/hns_roce_cmd.c
index b94dcd823ad1..1085cb249bc1 100644
--- a/drivers/infiniband/hw/hns/hns_roce_cmd.c
+++ b/drivers/infiniband/hw/hns/hns_roce_cmd.c
@@ -38,69 +38,7 @@
38 38
39#define CMD_POLL_TOKEN 0xffff 39#define CMD_POLL_TOKEN 0xffff
40#define CMD_MAX_NUM 32 40#define CMD_MAX_NUM 32
41#define STATUS_MASK 0xff
42#define CMD_TOKEN_MASK 0x1f 41#define CMD_TOKEN_MASK 0x1f
43#define GO_BIT_TIMEOUT_MSECS 10000
44
45enum {
46 HCR_TOKEN_OFFSET = 0x14,
47 HCR_STATUS_OFFSET = 0x18,
48 HCR_GO_BIT = 15,
49};
50
51static int cmd_pending(struct hns_roce_dev *hr_dev)
52{
53 u32 status = readl(hr_dev->cmd.hcr + HCR_TOKEN_OFFSET);
54
55 return (!!(status & (1 << HCR_GO_BIT)));
56}
57
58/* this function should be serialized with "hcr_mutex" */
59static int __hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev,
60 u64 in_param, u64 out_param,
61 u32 in_modifier, u8 op_modifier, u16 op,
62 u16 token, int event)
63{
64 struct hns_roce_cmdq *cmd = &hr_dev->cmd;
65 struct device *dev = &hr_dev->pdev->dev;
66 u32 __iomem *hcr = (u32 *)cmd->hcr;
67 int ret = -EAGAIN;
68 unsigned long end;
69 u32 val = 0;
70
71 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
72 while (cmd_pending(hr_dev)) {
73 if (time_after(jiffies, end)) {
74 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
75 (int)end);
76 goto out;
77 }
78 cond_resched();
79 }
80
81 roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
82 op);
83 roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
84 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
85 roce_set_bit(val, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
86 roce_set_bit(val, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
87 roce_set_field(val, ROCEE_MB6_ROCEE_MB_TOKEN_M,
88 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
89
90 __raw_writeq(cpu_to_le64(in_param), hcr + 0);
91 __raw_writeq(cpu_to_le64(out_param), hcr + 2);
92 __raw_writel(cpu_to_le32(in_modifier), hcr + 4);
93 /* Memory barrier */
94 wmb();
95
96 __raw_writel(cpu_to_le32(val), hcr + 5);
97
98 mmiowb();
99 ret = 0;
100
101out:
102 return ret;
103}
104 42
105static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev, u64 in_param, 43static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev, u64 in_param,
106 u64 out_param, u32 in_modifier, 44 u64 out_param, u32 in_modifier,
@@ -108,12 +46,11 @@ static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev, u64 in_param,
108 int event) 46 int event)
109{ 47{
110 struct hns_roce_cmdq *cmd = &hr_dev->cmd; 48 struct hns_roce_cmdq *cmd = &hr_dev->cmd;
111 int ret = -EAGAIN; 49 int ret;
112 50
113 mutex_lock(&cmd->hcr_mutex); 51 mutex_lock(&cmd->hcr_mutex);
114 ret = __hns_roce_cmd_mbox_post_hw(hr_dev, in_param, out_param, 52 ret = hr_dev->hw->post_mbox(hr_dev, in_param, out_param, in_modifier,
115 in_modifier, op_modifier, op, token, 53 op_modifier, op, token, event);
116 event);
117 mutex_unlock(&cmd->hcr_mutex); 54 mutex_unlock(&cmd->hcr_mutex);
118 55
119 return ret; 56 return ret;
@@ -125,10 +62,7 @@ static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
125 u8 op_modifier, u16 op, 62 u8 op_modifier, u16 op,
126 unsigned long timeout) 63 unsigned long timeout)
127{ 64{
128 struct device *dev = &hr_dev->pdev->dev; 65 struct device *dev = hr_dev->dev;
129 u8 __iomem *hcr = hr_dev->cmd.hcr;
130 unsigned long end = 0;
131 u32 status = 0;
132 int ret; 66 int ret;
133 67
134 ret = hns_roce_cmd_mbox_post_hw(hr_dev, in_param, out_param, 68 ret = hns_roce_cmd_mbox_post_hw(hr_dev, in_param, out_param,
@@ -136,29 +70,10 @@ static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
136 CMD_POLL_TOKEN, 0); 70 CMD_POLL_TOKEN, 0);
137 if (ret) { 71 if (ret) {
138 dev_err(dev, "[cmd_poll]hns_roce_cmd_mbox_post_hw failed\n"); 72 dev_err(dev, "[cmd_poll]hns_roce_cmd_mbox_post_hw failed\n");
139 goto out; 73 return ret;
140 }
141
142 end = msecs_to_jiffies(timeout) + jiffies;
143 while (cmd_pending(hr_dev) && time_before(jiffies, end))
144 cond_resched();
145
146 if (cmd_pending(hr_dev)) {
147 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
148 ret = -ETIMEDOUT;
149 goto out;
150 } 74 }
151 75
152 status = le32_to_cpu((__force __be32) 76 return hr_dev->hw->chk_mbox(hr_dev, timeout);
153 __raw_readl(hcr + HCR_STATUS_OFFSET));
154 if ((status & STATUS_MASK) != 0x1) {
155 dev_err(dev, "mailbox status 0x%x!\n", status);
156 ret = -EBUSY;
157 goto out;
158 }
159
160out:
161 return ret;
162} 77}
163 78
164static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param, 79static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev, u64 in_param,
@@ -196,9 +111,9 @@ static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
196 unsigned long timeout) 111 unsigned long timeout)
197{ 112{
198 struct hns_roce_cmdq *cmd = &hr_dev->cmd; 113 struct hns_roce_cmdq *cmd = &hr_dev->cmd;
199 struct device *dev = &hr_dev->pdev->dev;
200 struct hns_roce_cmd_context *context; 114 struct hns_roce_cmd_context *context;
201 int ret = 0; 115 struct device *dev = hr_dev->dev;
116 int ret;
202 117
203 spin_lock(&cmd->context_lock); 118 spin_lock(&cmd->context_lock);
204 WARN_ON(cmd->free_head < 0); 119 WARN_ON(cmd->free_head < 0);
@@ -269,17 +184,17 @@ int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
269 in_modifier, op_modifier, op, 184 in_modifier, op_modifier, op,
270 timeout); 185 timeout);
271} 186}
187EXPORT_SYMBOL_GPL(hns_roce_cmd_mbox);
272 188
273int hns_roce_cmd_init(struct hns_roce_dev *hr_dev) 189int hns_roce_cmd_init(struct hns_roce_dev *hr_dev)
274{ 190{
275 struct device *dev = &hr_dev->pdev->dev; 191 struct device *dev = hr_dev->dev;
276 192
277 mutex_init(&hr_dev->cmd.hcr_mutex); 193 mutex_init(&hr_dev->cmd.hcr_mutex);
278 sema_init(&hr_dev->cmd.poll_sem, 1); 194 sema_init(&hr_dev->cmd.poll_sem, 1);
279 hr_dev->cmd.use_events = 0; 195 hr_dev->cmd.use_events = 0;
280 hr_dev->cmd.toggle = 1; 196 hr_dev->cmd.toggle = 1;
281 hr_dev->cmd.max_cmds = CMD_MAX_NUM; 197 hr_dev->cmd.max_cmds = CMD_MAX_NUM;
282 hr_dev->cmd.hcr = hr_dev->reg_base + ROCEE_MB1_REG;
283 hr_dev->cmd.pool = dma_pool_create("hns_roce_cmd", dev, 198 hr_dev->cmd.pool = dma_pool_create("hns_roce_cmd", dev,
284 HNS_ROCE_MAILBOX_SIZE, 199 HNS_ROCE_MAILBOX_SIZE,
285 HNS_ROCE_MAILBOX_SIZE, 0); 200 HNS_ROCE_MAILBOX_SIZE, 0);
@@ -356,6 +271,7 @@ struct hns_roce_cmd_mailbox
356 271
357 return mailbox; 272 return mailbox;
358} 273}
274EXPORT_SYMBOL_GPL(hns_roce_alloc_cmd_mailbox);
359 275
360void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev, 276void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
361 struct hns_roce_cmd_mailbox *mailbox) 277 struct hns_roce_cmd_mailbox *mailbox)
@@ -366,3 +282,4 @@ void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
366 dma_pool_free(hr_dev->cmd.pool, mailbox->buf, mailbox->dma); 282 dma_pool_free(hr_dev->cmd.pool, mailbox->buf, mailbox->dma);
367 kfree(mailbox); 283 kfree(mailbox);
368} 284}
285EXPORT_SYMBOL_GPL(hns_roce_free_cmd_mailbox);
diff --git a/drivers/infiniband/hw/hns/hns_roce_cmd.h b/drivers/infiniband/hw/hns/hns_roce_cmd.h
index f5a9ee2fc53d..b1c94223c28b 100644
--- a/drivers/infiniband/hw/hns/hns_roce_cmd.h
+++ b/drivers/infiniband/hw/hns/hns_roce_cmd.h
@@ -37,6 +37,60 @@
37#define HNS_ROCE_CMD_TIMEOUT_MSECS 10000 37#define HNS_ROCE_CMD_TIMEOUT_MSECS 10000
38 38
39enum { 39enum {
40 /* QPC BT commands */
41 HNS_ROCE_CMD_WRITE_QPC_BT0 = 0x0,
42 HNS_ROCE_CMD_WRITE_QPC_BT1 = 0x1,
43 HNS_ROCE_CMD_WRITE_QPC_BT2 = 0x2,
44 HNS_ROCE_CMD_READ_QPC_BT0 = 0x4,
45 HNS_ROCE_CMD_READ_QPC_BT1 = 0x5,
46 HNS_ROCE_CMD_READ_QPC_BT2 = 0x6,
47 HNS_ROCE_CMD_DESTROY_QPC_BT0 = 0x8,
48 HNS_ROCE_CMD_DESTROY_QPC_BT1 = 0x9,
49 HNS_ROCE_CMD_DESTROY_QPC_BT2 = 0xa,
50
51 /* QPC operation */
52 HNS_ROCE_CMD_MODIFY_QPC = 0x41,
53 HNS_ROCE_CMD_QUERY_QPC = 0x42,
54
55 HNS_ROCE_CMD_MODIFY_CQC = 0x52,
56 /* CQC BT commands */
57 HNS_ROCE_CMD_WRITE_CQC_BT0 = 0x10,
58 HNS_ROCE_CMD_WRITE_CQC_BT1 = 0x11,
59 HNS_ROCE_CMD_WRITE_CQC_BT2 = 0x12,
60 HNS_ROCE_CMD_READ_CQC_BT0 = 0x14,
61 HNS_ROCE_CMD_READ_CQC_BT1 = 0x15,
62 HNS_ROCE_CMD_READ_CQC_BT2 = 0x1b,
63 HNS_ROCE_CMD_DESTROY_CQC_BT0 = 0x18,
64 HNS_ROCE_CMD_DESTROY_CQC_BT1 = 0x19,
65 HNS_ROCE_CMD_DESTROY_CQC_BT2 = 0x1a,
66
67 /* MPT BT commands */
68 HNS_ROCE_CMD_WRITE_MPT_BT0 = 0x20,
69 HNS_ROCE_CMD_WRITE_MPT_BT1 = 0x21,
70 HNS_ROCE_CMD_WRITE_MPT_BT2 = 0x22,
71 HNS_ROCE_CMD_READ_MPT_BT0 = 0x24,
72 HNS_ROCE_CMD_READ_MPT_BT1 = 0x25,
73 HNS_ROCE_CMD_READ_MPT_BT2 = 0x26,
74 HNS_ROCE_CMD_DESTROY_MPT_BT0 = 0x28,
75 HNS_ROCE_CMD_DESTROY_MPT_BT1 = 0x29,
76 HNS_ROCE_CMD_DESTROY_MPT_BT2 = 0x2a,
77
78 /* MPT commands */
79 HNS_ROCE_CMD_QUERY_MPT = 0x62,
80
81 /* SRQC BT commands */
82 HNS_ROCE_CMD_WRITE_SRQC_BT0 = 0x30,
83 HNS_ROCE_CMD_WRITE_SRQC_BT1 = 0x31,
84 HNS_ROCE_CMD_WRITE_SRQC_BT2 = 0x32,
85 HNS_ROCE_CMD_READ_SRQC_BT0 = 0x34,
86 HNS_ROCE_CMD_READ_SRQC_BT1 = 0x35,
87 HNS_ROCE_CMD_READ_SRQC_BT2 = 0x36,
88 HNS_ROCE_CMD_DESTROY_SRQC_BT0 = 0x38,
89 HNS_ROCE_CMD_DESTROY_SRQC_BT1 = 0x39,
90 HNS_ROCE_CMD_DESTROY_SRQC_BT2 = 0x3a,
91};
92
93enum {
40 /* TPT commands */ 94 /* TPT commands */
41 HNS_ROCE_CMD_SW2HW_MPT = 0xd, 95 HNS_ROCE_CMD_SW2HW_MPT = 0xd,
42 HNS_ROCE_CMD_HW2SW_MPT = 0xf, 96 HNS_ROCE_CMD_HW2SW_MPT = 0xf,
diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h
index 4af403e1348c..7ecb7a4147a8 100644
--- a/drivers/infiniband/hw/hns/hns_roce_common.h
+++ b/drivers/infiniband/hw/hns/hns_roce_common.h
@@ -341,6 +341,7 @@
341#define ROCEE_BT_CMD_L_REG 0x200 341#define ROCEE_BT_CMD_L_REG 0x200
342 342
343#define ROCEE_MB1_REG 0x210 343#define ROCEE_MB1_REG 0x210
344#define ROCEE_MB6_REG 0x224
344#define ROCEE_DB_SQ_L_0_REG 0x230 345#define ROCEE_DB_SQ_L_0_REG 0x230
345#define ROCEE_DB_OTHERS_L_0_REG 0x238 346#define ROCEE_DB_OTHERS_L_0_REG 0x238
346#define ROCEE_QP1C_CFG0_0_REG 0x270 347#define ROCEE_QP1C_CFG0_0_REG 0x270
@@ -362,4 +363,26 @@
362#define ROCEE_ECC_UCERR_ALM0_REG 0xB34 363#define ROCEE_ECC_UCERR_ALM0_REG 0xB34
363#define ROCEE_ECC_CERR_ALM0_REG 0xB40 364#define ROCEE_ECC_CERR_ALM0_REG 0xB40
364 365
366/* V2 ROCEE REG */
367#define ROCEE_TX_CMQ_BASEADDR_L_REG 0x07000
368#define ROCEE_TX_CMQ_BASEADDR_H_REG 0x07004
369#define ROCEE_TX_CMQ_DEPTH_REG 0x07008
370#define ROCEE_TX_CMQ_TAIL_REG 0x07010
371#define ROCEE_TX_CMQ_HEAD_REG 0x07014
372
373#define ROCEE_RX_CMQ_BASEADDR_L_REG 0x07018
374#define ROCEE_RX_CMQ_BASEADDR_H_REG 0x0701c
375#define ROCEE_RX_CMQ_DEPTH_REG 0x07020
376#define ROCEE_RX_CMQ_TAIL_REG 0x07024
377#define ROCEE_RX_CMQ_HEAD_REG 0x07028
378
379#define ROCEE_VF_SMAC_CFG0_REG 0x12000
380#define ROCEE_VF_SMAC_CFG1_REG 0x12004
381
382#define ROCEE_VF_SGID_CFG0_REG 0x10000
383#define ROCEE_VF_SGID_CFG1_REG 0x10004
384#define ROCEE_VF_SGID_CFG2_REG 0x10008
385#define ROCEE_VF_SGID_CFG3_REG 0x1000c
386#define ROCEE_VF_SGID_CFG4_REG 0x10010
387
365#endif /* _HNS_ROCE_COMMON_H */ 388#endif /* _HNS_ROCE_COMMON_H */
diff --git a/drivers/infiniband/hw/hns/hns_roce_cq.c b/drivers/infiniband/hw/hns/hns_roce_cq.c
index b89fd711019e..2111b57a3489 100644
--- a/drivers/infiniband/hw/hns/hns_roce_cq.c
+++ b/drivers/infiniband/hw/hns/hns_roce_cq.c
@@ -58,7 +58,7 @@ static void hns_roce_ib_cq_event(struct hns_roce_cq *hr_cq,
58 if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID && 58 if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID &&
59 event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR && 59 event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR &&
60 event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) { 60 event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) {
61 dev_err(&hr_dev->pdev->dev, 61 dev_err(hr_dev->dev,
62 "hns_roce_ib: Unexpected event type 0x%x on CQ %06lx\n", 62 "hns_roce_ib: Unexpected event type 0x%x on CQ %06lx\n",
63 event_type, hr_cq->cqn); 63 event_type, hr_cq->cqn);
64 return; 64 return;
@@ -85,17 +85,23 @@ static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
85 struct hns_roce_uar *hr_uar, 85 struct hns_roce_uar *hr_uar,
86 struct hns_roce_cq *hr_cq, int vector) 86 struct hns_roce_cq *hr_cq, int vector)
87{ 87{
88 struct hns_roce_cmd_mailbox *mailbox = NULL; 88 struct hns_roce_cmd_mailbox *mailbox;
89 struct hns_roce_cq_table *cq_table = NULL; 89 struct hns_roce_hem_table *mtt_table;
90 struct device *dev = &hr_dev->pdev->dev; 90 struct hns_roce_cq_table *cq_table;
91 struct device *dev = hr_dev->dev;
91 dma_addr_t dma_handle; 92 dma_addr_t dma_handle;
92 u64 *mtts = NULL; 93 u64 *mtts;
93 int ret = 0; 94 int ret;
94 95
95 cq_table = &hr_dev->cq_table; 96 cq_table = &hr_dev->cq_table;
96 97
97 /* Get the physical address of cq buf */ 98 /* Get the physical address of cq buf */
98 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table, 99 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
100 mtt_table = &hr_dev->mr_table.mtt_cqe_table;
101 else
102 mtt_table = &hr_dev->mr_table.mtt_table;
103
104 mtts = hns_roce_table_find(hr_dev, mtt_table,
99 hr_mtt->first_seg, &dma_handle); 105 hr_mtt->first_seg, &dma_handle);
100 if (!mtts) { 106 if (!mtts) {
101 dev_err(dev, "CQ alloc.Failed to find cq buf addr.\n"); 107 dev_err(dev, "CQ alloc.Failed to find cq buf addr.\n");
@@ -150,6 +156,7 @@ static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
150 } 156 }
151 157
152 hr_cq->cons_index = 0; 158 hr_cq->cons_index = 0;
159 hr_cq->arm_sn = 1;
153 hr_cq->uar = hr_uar; 160 hr_cq->uar = hr_uar;
154 161
155 atomic_set(&hr_cq->refcount, 1); 162 atomic_set(&hr_cq->refcount, 1);
@@ -182,21 +189,22 @@ static int hns_roce_hw2sw_cq(struct hns_roce_dev *dev,
182void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) 189void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
183{ 190{
184 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 191 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
185 struct device *dev = &hr_dev->pdev->dev; 192 struct device *dev = hr_dev->dev;
186 int ret; 193 int ret;
187 194
188 ret = hns_roce_hw2sw_cq(hr_dev, NULL, hr_cq->cqn); 195 ret = hns_roce_hw2sw_cq(hr_dev, NULL, hr_cq->cqn);
189 if (ret) 196 if (ret)
190 dev_err(dev, "HW2SW_CQ failed (%d) for CQN %06lx\n", ret, 197 dev_err(dev, "HW2SW_CQ failed (%d) for CQN %06lx\n", ret,
191 hr_cq->cqn); 198 hr_cq->cqn);
192 199 if (hr_dev->eq_table.eq) {
193 /* Waiting interrupt process procedure carried out */ 200 /* Waiting interrupt process procedure carried out */
194 synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq); 201 synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq);
195 202
196 /* wait for all interrupt processed */ 203 /* wait for all interrupt processed */
197 if (atomic_dec_and_test(&hr_cq->refcount)) 204 if (atomic_dec_and_test(&hr_cq->refcount))
198 complete(&hr_cq->free); 205 complete(&hr_cq->free);
199 wait_for_completion(&hr_cq->free); 206 wait_for_completion(&hr_cq->free);
207 }
200 208
201 spin_lock_irq(&cq_table->lock); 209 spin_lock_irq(&cq_table->lock);
202 radix_tree_delete(&cq_table->tree, hr_cq->cqn); 210 radix_tree_delete(&cq_table->tree, hr_cq->cqn);
@@ -205,6 +213,7 @@ void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
205 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); 213 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
206 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR); 214 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
207} 215}
216EXPORT_SYMBOL_GPL(hns_roce_free_cq);
208 217
209static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev, 218static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev,
210 struct ib_ucontext *context, 219 struct ib_ucontext *context,
@@ -212,14 +221,31 @@ static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev,
212 struct ib_umem **umem, u64 buf_addr, int cqe) 221 struct ib_umem **umem, u64 buf_addr, int cqe)
213{ 222{
214 int ret; 223 int ret;
224 u32 page_shift;
225 u32 npages;
215 226
216 *umem = ib_umem_get(context, buf_addr, cqe * hr_dev->caps.cq_entry_sz, 227 *umem = ib_umem_get(context, buf_addr, cqe * hr_dev->caps.cq_entry_sz,
217 IB_ACCESS_LOCAL_WRITE, 1); 228 IB_ACCESS_LOCAL_WRITE, 1);
218 if (IS_ERR(*umem)) 229 if (IS_ERR(*umem))
219 return PTR_ERR(*umem); 230 return PTR_ERR(*umem);
220 231
221 ret = hns_roce_mtt_init(hr_dev, ib_umem_page_count(*umem), 232 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
222 (*umem)->page_shift, &buf->hr_mtt); 233 buf->hr_mtt.mtt_type = MTT_TYPE_CQE;
234 else
235 buf->hr_mtt.mtt_type = MTT_TYPE_WQE;
236
237 if (hr_dev->caps.cqe_buf_pg_sz) {
238 npages = (ib_umem_page_count(*umem) +
239 (1 << hr_dev->caps.cqe_buf_pg_sz) - 1) /
240 (1 << hr_dev->caps.cqe_buf_pg_sz);
241 page_shift = PAGE_SHIFT + hr_dev->caps.cqe_buf_pg_sz;
242 ret = hns_roce_mtt_init(hr_dev, npages, page_shift,
243 &buf->hr_mtt);
244 } else {
245 ret = hns_roce_mtt_init(hr_dev, ib_umem_page_count(*umem),
246 (*umem)->page_shift,
247 &buf->hr_mtt);
248 }
223 if (ret) 249 if (ret)
224 goto err_buf; 250 goto err_buf;
225 251
@@ -241,12 +267,19 @@ static int hns_roce_ib_alloc_cq_buf(struct hns_roce_dev *hr_dev,
241 struct hns_roce_cq_buf *buf, u32 nent) 267 struct hns_roce_cq_buf *buf, u32 nent)
242{ 268{
243 int ret; 269 int ret;
270 u32 page_shift = PAGE_SHIFT + hr_dev->caps.cqe_buf_pg_sz;
244 271
245 ret = hns_roce_buf_alloc(hr_dev, nent * hr_dev->caps.cq_entry_sz, 272 ret = hns_roce_buf_alloc(hr_dev, nent * hr_dev->caps.cq_entry_sz,
246 PAGE_SIZE * 2, &buf->hr_buf); 273 (1 << page_shift) * 2, &buf->hr_buf,
274 page_shift);
247 if (ret) 275 if (ret)
248 goto out; 276 goto out;
249 277
278 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
279 buf->hr_mtt.mtt_type = MTT_TYPE_CQE;
280 else
281 buf->hr_mtt.mtt_type = MTT_TYPE_WQE;
282
250 ret = hns_roce_mtt_init(hr_dev, buf->hr_buf.npages, 283 ret = hns_roce_mtt_init(hr_dev, buf->hr_buf.npages,
251 buf->hr_buf.page_shift, &buf->hr_mtt); 284 buf->hr_buf.page_shift, &buf->hr_mtt);
252 if (ret) 285 if (ret)
@@ -281,13 +314,13 @@ struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
281 struct ib_udata *udata) 314 struct ib_udata *udata)
282{ 315{
283 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 316 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
284 struct device *dev = &hr_dev->pdev->dev; 317 struct device *dev = hr_dev->dev;
285 struct hns_roce_ib_create_cq ucmd; 318 struct hns_roce_ib_create_cq ucmd;
286 struct hns_roce_cq *hr_cq = NULL; 319 struct hns_roce_cq *hr_cq = NULL;
287 struct hns_roce_uar *uar = NULL; 320 struct hns_roce_uar *uar = NULL;
288 int vector = attr->comp_vector; 321 int vector = attr->comp_vector;
289 int cq_entries = attr->cqe; 322 int cq_entries = attr->cqe;
290 int ret = 0; 323 int ret;
291 324
292 if (cq_entries < 1 || cq_entries > hr_dev->caps.max_cqes) { 325 if (cq_entries < 1 || cq_entries > hr_dev->caps.max_cqes) {
293 dev_err(dev, "Creat CQ failed. entries=%d, max=%d\n", 326 dev_err(dev, "Creat CQ failed. entries=%d, max=%d\n",
@@ -295,13 +328,12 @@ struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
295 return ERR_PTR(-EINVAL); 328 return ERR_PTR(-EINVAL);
296 } 329 }
297 330
298 hr_cq = kmalloc(sizeof(*hr_cq), GFP_KERNEL); 331 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
299 if (!hr_cq) 332 if (!hr_cq)
300 return ERR_PTR(-ENOMEM); 333 return ERR_PTR(-ENOMEM);
301 334
302 /* In v1 engine, parameter verification */ 335 if (hr_dev->caps.min_cqes)
303 if (cq_entries < HNS_ROCE_MIN_CQE_NUM) 336 cq_entries = max(cq_entries, hr_dev->caps.min_cqes);
304 cq_entries = HNS_ROCE_MIN_CQE_NUM;
305 337
306 cq_entries = roundup_pow_of_two((unsigned int)cq_entries); 338 cq_entries = roundup_pow_of_two((unsigned int)cq_entries);
307 hr_cq->ib_cq.cqe = cq_entries - 1; 339 hr_cq->ib_cq.cqe = cq_entries - 1;
@@ -335,8 +367,8 @@ struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
335 } 367 }
336 368
337 uar = &hr_dev->priv_uar; 369 uar = &hr_dev->priv_uar;
338 hr_cq->cq_db_l = hr_dev->reg_base + ROCEE_DB_OTHERS_L_0_REG + 370 hr_cq->cq_db_l = hr_dev->reg_base + hr_dev->odb_offset +
339 0x1000 * uar->index; 371 DB_REG_OFFSET * uar->index;
340 } 372 }
341 373
342 /* Allocate cq index, fill cq_context */ 374 /* Allocate cq index, fill cq_context */
@@ -353,7 +385,7 @@ struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
353 * problems if tptr is set to zero here, so we initialze it in user 385 * problems if tptr is set to zero here, so we initialze it in user
354 * space. 386 * space.
355 */ 387 */
356 if (!context) 388 if (!context && hr_cq->tptr_addr)
357 *hr_cq->tptr_addr = 0; 389 *hr_cq->tptr_addr = 0;
358 390
359 /* Get created cq handler and carry out event */ 391 /* Get created cq handler and carry out event */
@@ -385,6 +417,7 @@ err_cq:
385 kfree(hr_cq); 417 kfree(hr_cq);
386 return ERR_PTR(ret); 418 return ERR_PTR(ret);
387} 419}
420EXPORT_SYMBOL_GPL(hns_roce_ib_create_cq);
388 421
389int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq) 422int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq)
390{ 423{
@@ -410,10 +443,11 @@ int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq)
410 443
411 return ret; 444 return ret;
412} 445}
446EXPORT_SYMBOL_GPL(hns_roce_ib_destroy_cq);
413 447
414void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn) 448void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
415{ 449{
416 struct device *dev = &hr_dev->pdev->dev; 450 struct device *dev = hr_dev->dev;
417 struct hns_roce_cq *cq; 451 struct hns_roce_cq *cq;
418 452
419 cq = radix_tree_lookup(&hr_dev->cq_table.tree, 453 cq = radix_tree_lookup(&hr_dev->cq_table.tree,
@@ -423,13 +457,14 @@ void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
423 return; 457 return;
424 } 458 }
425 459
460 ++cq->arm_sn;
426 cq->comp(cq); 461 cq->comp(cq);
427} 462}
428 463
429void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type) 464void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type)
430{ 465{
431 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 466 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
432 struct device *dev = &hr_dev->pdev->dev; 467 struct device *dev = hr_dev->dev;
433 struct hns_roce_cq *cq; 468 struct hns_roce_cq *cq;
434 469
435 cq = radix_tree_lookup(&cq_table->tree, 470 cq = radix_tree_lookup(&cq_table->tree,
diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
index e493a61e14e1..01d3d695cbba 100644
--- a/drivers/infiniband/hw/hns/hns_roce_device.h
+++ b/drivers/infiniband/hw/hns/hns_roce_device.h
@@ -78,6 +78,8 @@
78#define HNS_ROCE_MAX_GID_NUM 16 78#define HNS_ROCE_MAX_GID_NUM 16
79#define HNS_ROCE_GID_SIZE 16 79#define HNS_ROCE_GID_SIZE 16
80 80
81#define HNS_ROCE_HOP_NUM_0 0xff
82
81#define BITMAP_NO_RR 0 83#define BITMAP_NO_RR 0
82#define BITMAP_RR 1 84#define BITMAP_RR 1
83 85
@@ -168,6 +170,16 @@ enum {
168 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 170 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07,
169}; 171};
170 172
173enum {
174 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
175 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
176};
177
178enum hns_roce_mtt_type {
179 MTT_TYPE_WQE,
180 MTT_TYPE_CQE,
181};
182
171#define HNS_ROCE_CMD_SUCCESS 1 183#define HNS_ROCE_CMD_SUCCESS 1
172 184
173#define HNS_ROCE_PORT_DOWN 0 185#define HNS_ROCE_PORT_DOWN 0
@@ -229,15 +241,21 @@ struct hns_roce_hem_table {
229 unsigned long num_obj; 241 unsigned long num_obj;
230 /*Single obj size */ 242 /*Single obj size */
231 unsigned long obj_size; 243 unsigned long obj_size;
244 unsigned long table_chunk_size;
232 int lowmem; 245 int lowmem;
233 struct mutex mutex; 246 struct mutex mutex;
234 struct hns_roce_hem **hem; 247 struct hns_roce_hem **hem;
248 u64 **bt_l1;
249 dma_addr_t *bt_l1_dma_addr;
250 u64 **bt_l0;
251 dma_addr_t *bt_l0_dma_addr;
235}; 252};
236 253
237struct hns_roce_mtt { 254struct hns_roce_mtt {
238 unsigned long first_seg; 255 unsigned long first_seg;
239 int order; 256 int order;
240 int page_shift; 257 int page_shift;
258 enum hns_roce_mtt_type mtt_type;
241}; 259};
242 260
243/* Only support 4K page size for mr register */ 261/* Only support 4K page size for mr register */
@@ -255,6 +273,19 @@ struct hns_roce_mr {
255 int type; /* MR's register type */ 273 int type; /* MR's register type */
256 u64 *pbl_buf;/* MR's PBL space */ 274 u64 *pbl_buf;/* MR's PBL space */
257 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */ 275 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */
276 u32 pbl_size;/* PA number in the PBL */
277 u64 pbl_ba;/* page table address */
278 u32 l0_chunk_last_num;/* L0 last number */
279 u32 l1_chunk_last_num;/* L1 last number */
280 u64 **pbl_bt_l2;/* PBL BT L2 */
281 u64 **pbl_bt_l1;/* PBL BT L1 */
282 u64 *pbl_bt_l0;/* PBL BT L0 */
283 dma_addr_t *pbl_l2_dma_addr;/* PBL BT L2 dma addr */
284 dma_addr_t *pbl_l1_dma_addr;/* PBL BT L1 dma addr */
285 dma_addr_t pbl_l0_dma_addr;/* PBL BT L0 dma addr */
286 u32 pbl_ba_pg_sz;/* BT chunk page size */
287 u32 pbl_buf_pg_sz;/* buf chunk page size */
288 u32 pbl_hop_num;/* multi-hop number */
258}; 289};
259 290
260struct hns_roce_mr_table { 291struct hns_roce_mr_table {
@@ -262,6 +293,8 @@ struct hns_roce_mr_table {
262 struct hns_roce_buddy mtt_buddy; 293 struct hns_roce_buddy mtt_buddy;
263 struct hns_roce_hem_table mtt_table; 294 struct hns_roce_hem_table mtt_table;
264 struct hns_roce_hem_table mtpt_table; 295 struct hns_roce_hem_table mtpt_table;
296 struct hns_roce_buddy mtt_cqe_buddy;
297 struct hns_roce_hem_table mtt_cqe_table;
265}; 298};
266 299
267struct hns_roce_wq { 300struct hns_roce_wq {
@@ -277,6 +310,12 @@ struct hns_roce_wq {
277 void __iomem *db_reg_l; 310 void __iomem *db_reg_l;
278}; 311};
279 312
313struct hns_roce_sge {
314 int sge_cnt; /* SGE num */
315 int offset;
316 int sge_shift;/* SGE size */
317};
318
280struct hns_roce_buf_list { 319struct hns_roce_buf_list {
281 void *buf; 320 void *buf;
282 dma_addr_t map; 321 dma_addr_t map;
@@ -308,6 +347,7 @@ struct hns_roce_cq {
308 u32 cons_index; 347 u32 cons_index;
309 void __iomem *cq_db_l; 348 void __iomem *cq_db_l;
310 u16 *tptr_addr; 349 u16 *tptr_addr;
350 int arm_sn;
311 unsigned long cqn; 351 unsigned long cqn;
312 u32 vector; 352 u32 vector;
313 atomic_t refcount; 353 atomic_t refcount;
@@ -328,6 +368,7 @@ struct hns_roce_qp_table {
328 spinlock_t lock; 368 spinlock_t lock;
329 struct hns_roce_hem_table qp_table; 369 struct hns_roce_hem_table qp_table;
330 struct hns_roce_hem_table irrl_table; 370 struct hns_roce_hem_table irrl_table;
371 struct hns_roce_hem_table trrl_table;
331}; 372};
332 373
333struct hns_roce_cq_table { 374struct hns_roce_cq_table {
@@ -367,7 +408,6 @@ struct hns_roce_cmd_context {
367 408
368struct hns_roce_cmdq { 409struct hns_roce_cmdq {
369 struct dma_pool *pool; 410 struct dma_pool *pool;
370 u8 __iomem *hcr;
371 struct mutex hcr_mutex; 411 struct mutex hcr_mutex;
372 struct semaphore poll_sem; 412 struct semaphore poll_sem;
373 /* 413 /*
@@ -429,6 +469,9 @@ struct hns_roce_qp {
429 469
430 atomic_t refcount; 470 atomic_t refcount;
431 struct completion free; 471 struct completion free;
472
473 struct hns_roce_sge sge;
474 u32 next_sge;
432}; 475};
433 476
434struct hns_roce_sqp { 477struct hns_roce_sqp {
@@ -439,7 +482,6 @@ struct hns_roce_ib_iboe {
439 spinlock_t lock; 482 spinlock_t lock;
440 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 483 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
441 struct notifier_block nb; 484 struct notifier_block nb;
442 struct notifier_block nb_inet;
443 u8 phy_port[HNS_ROCE_MAX_PORTS]; 485 u8 phy_port[HNS_ROCE_MAX_PORTS];
444}; 486};
445 487
@@ -477,16 +519,20 @@ struct hns_roce_caps {
477 u32 max_wqes; /* 16k */ 519 u32 max_wqes; /* 16k */
478 u32 max_sq_desc_sz; /* 64 */ 520 u32 max_sq_desc_sz; /* 64 */
479 u32 max_rq_desc_sz; /* 64 */ 521 u32 max_rq_desc_sz; /* 64 */
522 u32 max_srq_desc_sz;
480 int max_qp_init_rdma; 523 int max_qp_init_rdma;
481 int max_qp_dest_rdma; 524 int max_qp_dest_rdma;
482 int num_cqs; 525 int num_cqs;
483 int max_cqes; 526 int max_cqes;
527 int min_cqes;
528 u32 min_wqes;
484 int reserved_cqs; 529 int reserved_cqs;
485 int num_aeq_vectors; /* 1 */ 530 int num_aeq_vectors; /* 1 */
486 int num_comp_vectors; /* 32 ceq */ 531 int num_comp_vectors; /* 32 ceq */
487 int num_other_vectors; 532 int num_other_vectors;
488 int num_mtpts; 533 int num_mtpts;
489 u32 num_mtt_segs; 534 u32 num_mtt_segs;
535 u32 num_cqe_segs;
490 int reserved_mrws; 536 int reserved_mrws;
491 int reserved_uars; 537 int reserved_uars;
492 int num_pds; 538 int num_pds;
@@ -498,29 +544,70 @@ struct hns_roce_caps {
498 int mtpt_entry_sz; 544 int mtpt_entry_sz;
499 int qpc_entry_sz; 545 int qpc_entry_sz;
500 int irrl_entry_sz; 546 int irrl_entry_sz;
547 int trrl_entry_sz;
501 int cqc_entry_sz; 548 int cqc_entry_sz;
549 u32 pbl_ba_pg_sz;
550 u32 pbl_buf_pg_sz;
551 u32 pbl_hop_num;
502 int aeqe_depth; 552 int aeqe_depth;
503 int ceqe_depth[HNS_ROCE_COMP_VEC_NUM]; 553 int ceqe_depth[HNS_ROCE_COMP_VEC_NUM];
504 enum ib_mtu max_mtu; 554 enum ib_mtu max_mtu;
555 u32 qpc_bt_num;
556 u32 srqc_bt_num;
557 u32 cqc_bt_num;
558 u32 mpt_bt_num;
559 u32 qpc_ba_pg_sz;
560 u32 qpc_buf_pg_sz;
561 u32 qpc_hop_num;
562 u32 srqc_ba_pg_sz;
563 u32 srqc_buf_pg_sz;
564 u32 srqc_hop_num;
565 u32 cqc_ba_pg_sz;
566 u32 cqc_buf_pg_sz;
567 u32 cqc_hop_num;
568 u32 mpt_ba_pg_sz;
569 u32 mpt_buf_pg_sz;
570 u32 mpt_hop_num;
571 u32 mtt_ba_pg_sz;
572 u32 mtt_buf_pg_sz;
573 u32 mtt_hop_num;
574 u32 cqe_ba_pg_sz;
575 u32 cqe_buf_pg_sz;
576 u32 cqe_hop_num;
577 u32 chunk_sz; /* chunk size in non multihop mode*/
578 u64 flags;
505}; 579};
506 580
507struct hns_roce_hw { 581struct hns_roce_hw {
508 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 582 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
509 void (*hw_profile)(struct hns_roce_dev *hr_dev); 583 int (*cmq_init)(struct hns_roce_dev *hr_dev);
584 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
585 int (*hw_profile)(struct hns_roce_dev *hr_dev);
510 int (*hw_init)(struct hns_roce_dev *hr_dev); 586 int (*hw_init)(struct hns_roce_dev *hr_dev);
511 void (*hw_exit)(struct hns_roce_dev *hr_dev); 587 void (*hw_exit)(struct hns_roce_dev *hr_dev);
512 void (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 588 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
513 union ib_gid *gid); 589 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
514 void (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 590 u16 token, int event);
591 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
592 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
593 union ib_gid *gid, const struct ib_gid_attr *attr);
594 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
515 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 595 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
516 enum ib_mtu mtu); 596 enum ib_mtu mtu);
517 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr, 597 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
518 unsigned long mtpt_idx); 598 unsigned long mtpt_idx);
599 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
600 struct hns_roce_mr *mr, int flags, u32 pdn,
601 int mr_access_flags, u64 iova, u64 size,
602 void *mb_buf);
519 void (*write_cqc)(struct hns_roce_dev *hr_dev, 603 void (*write_cqc)(struct hns_roce_dev *hr_dev,
520 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 604 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
521 dma_addr_t dma_handle, int nent, u32 vector); 605 dma_addr_t dma_handle, int nent, u32 vector);
606 int (*set_hem)(struct hns_roce_dev *hr_dev,
607 struct hns_roce_hem_table *table, int obj, int step_idx);
522 int (*clear_hem)(struct hns_roce_dev *hr_dev, 608 int (*clear_hem)(struct hns_roce_dev *hr_dev,
523 struct hns_roce_hem_table *table, int obj); 609 struct hns_roce_hem_table *table, int obj,
610 int step_idx);
524 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 611 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
525 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 612 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
526 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 613 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
@@ -535,12 +622,14 @@ struct hns_roce_hw {
535 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 622 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
536 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr); 623 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr);
537 int (*destroy_cq)(struct ib_cq *ibcq); 624 int (*destroy_cq)(struct ib_cq *ibcq);
538 void *priv; 625 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
539}; 626};
540 627
541struct hns_roce_dev { 628struct hns_roce_dev {
542 struct ib_device ib_dev; 629 struct ib_device ib_dev;
543 struct platform_device *pdev; 630 struct platform_device *pdev;
631 struct pci_dev *pci_dev;
632 struct device *dev;
544 struct hns_roce_uar priv_uar; 633 struct hns_roce_uar priv_uar;
545 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 634 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
546 spinlock_t sm_lock; 635 spinlock_t sm_lock;
@@ -569,9 +658,12 @@ struct hns_roce_dev {
569 658
570 int cmd_mod; 659 int cmd_mod;
571 int loop_idc; 660 int loop_idc;
661 u32 sdb_offset;
662 u32 odb_offset;
572 dma_addr_t tptr_dma_addr; /*only for hw v1*/ 663 dma_addr_t tptr_dma_addr; /*only for hw v1*/
573 u32 tptr_size; /*only for hw v1*/ 664 u32 tptr_size; /*only for hw v1*/
574 struct hns_roce_hw *hw; 665 const struct hns_roce_hw *hw;
666 void *priv;
575}; 667};
576 668
577static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 669static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
@@ -635,12 +727,14 @@ static inline struct hns_roce_qp
635static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) 727static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
636{ 728{
637 u32 bits_per_long_val = BITS_PER_LONG; 729 u32 bits_per_long_val = BITS_PER_LONG;
730 u32 page_size = 1 << buf->page_shift;
638 731
639 if (bits_per_long_val == 64 || buf->nbufs == 1) 732 if ((bits_per_long_val == 64 && buf->page_shift == PAGE_SHIFT) ||
733 buf->nbufs == 1)
640 return (char *)(buf->direct.buf) + offset; 734 return (char *)(buf->direct.buf) + offset;
641 else 735 else
642 return (char *)(buf->page_list[offset >> PAGE_SHIFT].buf) + 736 return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
643 (offset & (PAGE_SIZE - 1)); 737 (offset & (page_size - 1));
644} 738}
645 739
646int hns_roce_init_uar_table(struct hns_roce_dev *dev); 740int hns_roce_init_uar_table(struct hns_roce_dev *dev);
@@ -702,6 +796,9 @@ struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
702struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 796struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
703 u64 virt_addr, int access_flags, 797 u64 virt_addr, int access_flags,
704 struct ib_udata *udata); 798 struct ib_udata *udata);
799int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
800 u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
801 struct ib_udata *udata);
705int hns_roce_dereg_mr(struct ib_mr *ibmr); 802int hns_roce_dereg_mr(struct ib_mr *ibmr);
706int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev, 803int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
707 struct hns_roce_cmd_mailbox *mailbox, 804 struct hns_roce_cmd_mailbox *mailbox,
@@ -711,7 +808,7 @@ unsigned long key_to_hw_index(u32 key);
711void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, 808void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
712 struct hns_roce_buf *buf); 809 struct hns_roce_buf *buf);
713int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 810int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
714 struct hns_roce_buf *buf); 811 struct hns_roce_buf *buf, u32 page_shift);
715 812
716int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev, 813int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
717 struct hns_roce_mtt *mtt, struct ib_umem *umem); 814 struct hns_roce_mtt *mtt, struct ib_umem *umem);
@@ -723,6 +820,7 @@ int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
723 int attr_mask, struct ib_udata *udata); 820 int attr_mask, struct ib_udata *udata);
724void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n); 821void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
725void *get_send_wqe(struct hns_roce_qp *hr_qp, int n); 822void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
823void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n);
726bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 824bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
727 struct ib_cq *ib_cq); 825 struct ib_cq *ib_cq);
728enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 826enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
@@ -749,7 +847,7 @@ void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
749void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 847void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
750void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 848void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
751int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 849int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
752 850int hns_roce_init(struct hns_roce_dev *hr_dev);
753extern struct hns_roce_hw hns_roce_hw_v1; 851void hns_roce_exit(struct hns_roce_dev *hr_dev);
754 852
755#endif /* _HNS_ROCE_DEVICE_H */ 853#endif /* _HNS_ROCE_DEVICE_H */
diff --git a/drivers/infiniband/hw/hns/hns_roce_eq.c b/drivers/infiniband/hw/hns/hns_roce_eq.c
index b0f43735de1a..d184431e2bf5 100644
--- a/drivers/infiniband/hw/hns/hns_roce_eq.c
+++ b/drivers/infiniband/hw/hns/hns_roce_eq.c
@@ -558,7 +558,7 @@ static int hns_roce_create_eq(struct hns_roce_dev *hr_dev,
558 writel(eqshift_val, eqc); 558 writel(eqshift_val, eqc);
559 559
560 /* Configure eq extended address 12~44bit */ 560 /* Configure eq extended address 12~44bit */
561 writel((u32)(eq->buf_list[0].map >> 12), (u8 *)eqc + 4); 561 writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
562 562
563 /* 563 /*
564 * Configure eq extended address 45~49 bit. 564 * Configure eq extended address 45~49 bit.
@@ -572,13 +572,13 @@ static int hns_roce_create_eq(struct hns_roce_dev *hr_dev,
572 roce_set_field(eqcuridx_val, 572 roce_set_field(eqcuridx_val,
573 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M, 573 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
574 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0); 574 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
575 writel(eqcuridx_val, (u8 *)eqc + 8); 575 writel(eqcuridx_val, eqc + 8);
576 576
577 /* Configure eq consumer index */ 577 /* Configure eq consumer index */
578 roce_set_field(eqconsindx_val, 578 roce_set_field(eqconsindx_val,
579 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M, 579 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
580 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0); 580 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
581 writel(eqconsindx_val, (u8 *)eqc + 0xc); 581 writel(eqconsindx_val, eqc + 0xc);
582 582
583 return 0; 583 return 0;
584 584
diff --git a/drivers/infiniband/hw/hns/hns_roce_hem.c b/drivers/infiniband/hw/hns/hns_roce_hem.c
index c5104e0b2916..8b733a66fae5 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hem.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hem.c
@@ -36,14 +36,165 @@
36#include "hns_roce_hem.h" 36#include "hns_roce_hem.h"
37#include "hns_roce_common.h" 37#include "hns_roce_common.h"
38 38
39#define HNS_ROCE_HEM_ALLOC_SIZE (1 << 17)
40#define HNS_ROCE_TABLE_CHUNK_SIZE (1 << 17)
41
42#define DMA_ADDR_T_SHIFT 12 39#define DMA_ADDR_T_SHIFT 12
43#define BT_BA_SHIFT 32 40#define BT_BA_SHIFT 32
44 41
45struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, int npages, 42bool hns_roce_check_whether_mhop(struct hns_roce_dev *hr_dev, u32 type)
46 gfp_t gfp_mask) 43{
44 if ((hr_dev->caps.qpc_hop_num && type == HEM_TYPE_QPC) ||
45 (hr_dev->caps.mpt_hop_num && type == HEM_TYPE_MTPT) ||
46 (hr_dev->caps.cqc_hop_num && type == HEM_TYPE_CQC) ||
47 (hr_dev->caps.srqc_hop_num && type == HEM_TYPE_SRQC) ||
48 (hr_dev->caps.cqe_hop_num && type == HEM_TYPE_CQE) ||
49 (hr_dev->caps.mtt_hop_num && type == HEM_TYPE_MTT))
50 return true;
51
52 return false;
53}
54EXPORT_SYMBOL_GPL(hns_roce_check_whether_mhop);
55
56static bool hns_roce_check_hem_null(struct hns_roce_hem **hem, u64 start_idx,
57 u32 bt_chunk_num)
58{
59 int i;
60
61 for (i = 0; i < bt_chunk_num; i++)
62 if (hem[start_idx + i])
63 return false;
64
65 return true;
66}
67
68static bool hns_roce_check_bt_null(u64 **bt, u64 start_idx, u32 bt_chunk_num)
69{
70 int i;
71
72 for (i = 0; i < bt_chunk_num; i++)
73 if (bt[start_idx + i])
74 return false;
75
76 return true;
77}
78
79static int hns_roce_get_bt_num(u32 table_type, u32 hop_num)
80{
81 if (check_whether_bt_num_3(table_type, hop_num))
82 return 3;
83 else if (check_whether_bt_num_2(table_type, hop_num))
84 return 2;
85 else if (check_whether_bt_num_1(table_type, hop_num))
86 return 1;
87 else
88 return 0;
89}
90
91int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev,
92 struct hns_roce_hem_table *table, unsigned long *obj,
93 struct hns_roce_hem_mhop *mhop)
94{
95 struct device *dev = hr_dev->dev;
96 u32 chunk_ba_num;
97 u32 table_idx;
98 u32 bt_num;
99 u32 chunk_size;
100
101 switch (table->type) {
102 case HEM_TYPE_QPC:
103 mhop->buf_chunk_size = 1 << (hr_dev->caps.qpc_buf_pg_sz
104 + PAGE_SHIFT);
105 mhop->bt_chunk_size = 1 << (hr_dev->caps.qpc_ba_pg_sz
106 + PAGE_SHIFT);
107 mhop->ba_l0_num = hr_dev->caps.qpc_bt_num;
108 mhop->hop_num = hr_dev->caps.qpc_hop_num;
109 break;
110 case HEM_TYPE_MTPT:
111 mhop->buf_chunk_size = 1 << (hr_dev->caps.mpt_buf_pg_sz
112 + PAGE_SHIFT);
113 mhop->bt_chunk_size = 1 << (hr_dev->caps.mpt_ba_pg_sz
114 + PAGE_SHIFT);
115 mhop->ba_l0_num = hr_dev->caps.mpt_bt_num;
116 mhop->hop_num = hr_dev->caps.mpt_hop_num;
117 break;
118 case HEM_TYPE_CQC:
119 mhop->buf_chunk_size = 1 << (hr_dev->caps.cqc_buf_pg_sz
120 + PAGE_SHIFT);
121 mhop->bt_chunk_size = 1 << (hr_dev->caps.cqc_ba_pg_sz
122 + PAGE_SHIFT);
123 mhop->ba_l0_num = hr_dev->caps.cqc_bt_num;
124 mhop->hop_num = hr_dev->caps.cqc_hop_num;
125 break;
126 case HEM_TYPE_SRQC:
127 mhop->buf_chunk_size = 1 << (hr_dev->caps.srqc_buf_pg_sz
128 + PAGE_SHIFT);
129 mhop->bt_chunk_size = 1 << (hr_dev->caps.srqc_ba_pg_sz
130 + PAGE_SHIFT);
131 mhop->ba_l0_num = hr_dev->caps.srqc_bt_num;
132 mhop->hop_num = hr_dev->caps.srqc_hop_num;
133 break;
134 case HEM_TYPE_MTT:
135 mhop->buf_chunk_size = 1 << (hr_dev->caps.mtt_buf_pg_sz
136 + PAGE_SHIFT);
137 mhop->bt_chunk_size = 1 << (hr_dev->caps.mtt_ba_pg_sz
138 + PAGE_SHIFT);
139 mhop->ba_l0_num = mhop->bt_chunk_size / 8;
140 mhop->hop_num = hr_dev->caps.mtt_hop_num;
141 break;
142 case HEM_TYPE_CQE:
143 mhop->buf_chunk_size = 1 << (hr_dev->caps.cqe_buf_pg_sz
144 + PAGE_SHIFT);
145 mhop->bt_chunk_size = 1 << (hr_dev->caps.cqe_ba_pg_sz
146 + PAGE_SHIFT);
147 mhop->ba_l0_num = mhop->bt_chunk_size / 8;
148 mhop->hop_num = hr_dev->caps.cqe_hop_num;
149 break;
150 default:
151 dev_err(dev, "Table %d not support multi-hop addressing!\n",
152 table->type);
153 return -EINVAL;
154 }
155
156 if (!obj)
157 return 0;
158
159 /*
160 * QPC/MTPT/CQC/SRQC alloc hem for buffer pages.
161 * MTT/CQE alloc hem for bt pages.
162 */
163 bt_num = hns_roce_get_bt_num(table->type, mhop->hop_num);
164 chunk_ba_num = mhop->bt_chunk_size / 8;
165 chunk_size = table->type < HEM_TYPE_MTT ? mhop->buf_chunk_size :
166 mhop->bt_chunk_size;
167 table_idx = (*obj & (table->num_obj - 1)) /
168 (chunk_size / table->obj_size);
169 switch (bt_num) {
170 case 3:
171 mhop->l2_idx = table_idx & (chunk_ba_num - 1);
172 mhop->l1_idx = table_idx / chunk_ba_num & (chunk_ba_num - 1);
173 mhop->l0_idx = table_idx / chunk_ba_num / chunk_ba_num;
174 break;
175 case 2:
176 mhop->l1_idx = table_idx & (chunk_ba_num - 1);
177 mhop->l0_idx = table_idx / chunk_ba_num;
178 break;
179 case 1:
180 mhop->l0_idx = table_idx;
181 break;
182 default:
183 dev_err(dev, "Table %d not support hop_num = %d!\n",
184 table->type, mhop->hop_num);
185 return -EINVAL;
186 }
187 if (mhop->l0_idx >= mhop->ba_l0_num)
188 mhop->l0_idx %= mhop->ba_l0_num;
189
190 return 0;
191}
192EXPORT_SYMBOL_GPL(hns_roce_calc_hem_mhop);
193
194static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
195 int npages,
196 unsigned long hem_alloc_size,
197 gfp_t gfp_mask)
47{ 198{
48 struct hns_roce_hem_chunk *chunk = NULL; 199 struct hns_roce_hem_chunk *chunk = NULL;
49 struct hns_roce_hem *hem; 200 struct hns_roce_hem *hem;
@@ -61,7 +212,7 @@ struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, int npages,
61 hem->refcount = 0; 212 hem->refcount = 0;
62 INIT_LIST_HEAD(&hem->chunk_list); 213 INIT_LIST_HEAD(&hem->chunk_list);
63 214
64 order = get_order(HNS_ROCE_HEM_ALLOC_SIZE); 215 order = get_order(hem_alloc_size);
65 216
66 while (npages > 0) { 217 while (npages > 0) {
67 if (!chunk) { 218 if (!chunk) {
@@ -84,7 +235,7 @@ struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, int npages,
84 * memory, directly return fail. 235 * memory, directly return fail.
85 */ 236 */
86 mem = &chunk->mem[chunk->npages]; 237 mem = &chunk->mem[chunk->npages];
87 buf = dma_alloc_coherent(&hr_dev->pdev->dev, PAGE_SIZE << order, 238 buf = dma_alloc_coherent(hr_dev->dev, PAGE_SIZE << order,
88 &sg_dma_address(mem), gfp_mask); 239 &sg_dma_address(mem), gfp_mask);
89 if (!buf) 240 if (!buf)
90 goto fail; 241 goto fail;
@@ -115,7 +266,7 @@ void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem)
115 266
116 list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) { 267 list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) {
117 for (i = 0; i < chunk->npages; ++i) 268 for (i = 0; i < chunk->npages; ++i)
118 dma_free_coherent(&hr_dev->pdev->dev, 269 dma_free_coherent(hr_dev->dev,
119 chunk->mem[i].length, 270 chunk->mem[i].length,
120 lowmem_page_address(sg_page(&chunk->mem[i])), 271 lowmem_page_address(sg_page(&chunk->mem[i])),
121 sg_dma_address(&chunk->mem[i])); 272 sg_dma_address(&chunk->mem[i]));
@@ -128,8 +279,8 @@ void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem)
128static int hns_roce_set_hem(struct hns_roce_dev *hr_dev, 279static int hns_roce_set_hem(struct hns_roce_dev *hr_dev,
129 struct hns_roce_hem_table *table, unsigned long obj) 280 struct hns_roce_hem_table *table, unsigned long obj)
130{ 281{
131 struct device *dev = &hr_dev->pdev->dev;
132 spinlock_t *lock = &hr_dev->bt_cmd_lock; 282 spinlock_t *lock = &hr_dev->bt_cmd_lock;
283 struct device *dev = hr_dev->dev;
133 unsigned long end = 0; 284 unsigned long end = 0;
134 unsigned long flags; 285 unsigned long flags;
135 struct hns_roce_hem_iter iter; 286 struct hns_roce_hem_iter iter;
@@ -142,7 +293,7 @@ static int hns_roce_set_hem(struct hns_roce_dev *hr_dev,
142 293
143 /* Find the HEM(Hardware Entry Memory) entry */ 294 /* Find the HEM(Hardware Entry Memory) entry */
144 unsigned long i = (obj & (table->num_obj - 1)) / 295 unsigned long i = (obj & (table->num_obj - 1)) /
145 (HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size); 296 (table->table_chunk_size / table->obj_size);
146 297
147 switch (table->type) { 298 switch (table->type) {
148 case HEM_TYPE_QPC: 299 case HEM_TYPE_QPC:
@@ -209,14 +360,185 @@ static int hns_roce_set_hem(struct hns_roce_dev *hr_dev,
209 return ret; 360 return ret;
210} 361}
211 362
363static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev,
364 struct hns_roce_hem_table *table,
365 unsigned long obj)
366{
367 struct device *dev = hr_dev->dev;
368 struct hns_roce_hem_mhop mhop;
369 struct hns_roce_hem_iter iter;
370 u32 buf_chunk_size;
371 u32 bt_chunk_size;
372 u32 chunk_ba_num;
373 u32 hop_num;
374 u32 size;
375 u32 bt_num;
376 u64 hem_idx;
377 u64 bt_l1_idx = 0;
378 u64 bt_l0_idx = 0;
379 u64 bt_ba;
380 unsigned long mhop_obj = obj;
381 int bt_l1_allocated = 0;
382 int bt_l0_allocated = 0;
383 int step_idx;
384 int ret;
385
386 ret = hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
387 if (ret)
388 return ret;
389
390 buf_chunk_size = mhop.buf_chunk_size;
391 bt_chunk_size = mhop.bt_chunk_size;
392 hop_num = mhop.hop_num;
393 chunk_ba_num = bt_chunk_size / 8;
394
395 bt_num = hns_roce_get_bt_num(table->type, hop_num);
396 switch (bt_num) {
397 case 3:
398 hem_idx = mhop.l0_idx * chunk_ba_num * chunk_ba_num +
399 mhop.l1_idx * chunk_ba_num + mhop.l2_idx;
400 bt_l1_idx = mhop.l0_idx * chunk_ba_num + mhop.l1_idx;
401 bt_l0_idx = mhop.l0_idx;
402 break;
403 case 2:
404 hem_idx = mhop.l0_idx * chunk_ba_num + mhop.l1_idx;
405 bt_l0_idx = mhop.l0_idx;
406 break;
407 case 1:
408 hem_idx = mhop.l0_idx;
409 break;
410 default:
411 dev_err(dev, "Table %d not support hop_num = %d!\n",
412 table->type, hop_num);
413 return -EINVAL;
414 }
415
416 mutex_lock(&table->mutex);
417
418 if (table->hem[hem_idx]) {
419 ++table->hem[hem_idx]->refcount;
420 goto out;
421 }
422
423 /* alloc L1 BA's chunk */
424 if ((check_whether_bt_num_3(table->type, hop_num) ||
425 check_whether_bt_num_2(table->type, hop_num)) &&
426 !table->bt_l0[bt_l0_idx]) {
427 table->bt_l0[bt_l0_idx] = dma_alloc_coherent(dev, bt_chunk_size,
428 &(table->bt_l0_dma_addr[bt_l0_idx]),
429 GFP_KERNEL);
430 if (!table->bt_l0[bt_l0_idx]) {
431 ret = -ENOMEM;
432 goto out;
433 }
434 bt_l0_allocated = 1;
435
436 /* set base address to hardware */
437 if (table->type < HEM_TYPE_MTT) {
438 step_idx = 0;
439 if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
440 ret = -ENODEV;
441 dev_err(dev, "set HEM base address to HW failed!\n");
442 goto err_dma_alloc_l1;
443 }
444 }
445 }
446
447 /* alloc L2 BA's chunk */
448 if (check_whether_bt_num_3(table->type, hop_num) &&
449 !table->bt_l1[bt_l1_idx]) {
450 table->bt_l1[bt_l1_idx] = dma_alloc_coherent(dev, bt_chunk_size,
451 &(table->bt_l1_dma_addr[bt_l1_idx]),
452 GFP_KERNEL);
453 if (!table->bt_l1[bt_l1_idx]) {
454 ret = -ENOMEM;
455 goto err_dma_alloc_l1;
456 }
457 bt_l1_allocated = 1;
458 *(table->bt_l0[bt_l0_idx] + mhop.l1_idx) =
459 table->bt_l1_dma_addr[bt_l1_idx];
460
461 /* set base address to hardware */
462 step_idx = 1;
463 if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
464 ret = -ENODEV;
465 dev_err(dev, "set HEM base address to HW failed!\n");
466 goto err_alloc_hem_buf;
467 }
468 }
469
470 /*
471 * alloc buffer space chunk for QPC/MTPT/CQC/SRQC.
472 * alloc bt space chunk for MTT/CQE.
473 */
474 size = table->type < HEM_TYPE_MTT ? buf_chunk_size : bt_chunk_size;
475 table->hem[hem_idx] = hns_roce_alloc_hem(hr_dev,
476 size >> PAGE_SHIFT,
477 size,
478 (table->lowmem ? GFP_KERNEL :
479 GFP_HIGHUSER) | __GFP_NOWARN);
480 if (!table->hem[hem_idx]) {
481 ret = -ENOMEM;
482 goto err_alloc_hem_buf;
483 }
484
485 hns_roce_hem_first(table->hem[hem_idx], &iter);
486 bt_ba = hns_roce_hem_addr(&iter);
487
488 if (table->type < HEM_TYPE_MTT) {
489 if (hop_num == 2) {
490 *(table->bt_l1[bt_l1_idx] + mhop.l2_idx) = bt_ba;
491 step_idx = 2;
492 } else if (hop_num == 1) {
493 *(table->bt_l0[bt_l0_idx] + mhop.l1_idx) = bt_ba;
494 step_idx = 1;
495 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
496 step_idx = 0;
497 }
498
499 /* set HEM base address to hardware */
500 if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
501 ret = -ENODEV;
502 dev_err(dev, "set HEM base address to HW failed!\n");
503 goto err_alloc_hem_buf;
504 }
505 } else if (hop_num == 2) {
506 *(table->bt_l0[bt_l0_idx] + mhop.l1_idx) = bt_ba;
507 }
508
509 ++table->hem[hem_idx]->refcount;
510 goto out;
511
512err_alloc_hem_buf:
513 if (bt_l1_allocated) {
514 dma_free_coherent(dev, bt_chunk_size, table->bt_l1[bt_l1_idx],
515 table->bt_l1_dma_addr[bt_l1_idx]);
516 table->bt_l1[bt_l1_idx] = NULL;
517 }
518
519err_dma_alloc_l1:
520 if (bt_l0_allocated) {
521 dma_free_coherent(dev, bt_chunk_size, table->bt_l0[bt_l0_idx],
522 table->bt_l0_dma_addr[bt_l0_idx]);
523 table->bt_l0[bt_l0_idx] = NULL;
524 }
525
526out:
527 mutex_unlock(&table->mutex);
528 return ret;
529}
530
212int hns_roce_table_get(struct hns_roce_dev *hr_dev, 531int hns_roce_table_get(struct hns_roce_dev *hr_dev,
213 struct hns_roce_hem_table *table, unsigned long obj) 532 struct hns_roce_hem_table *table, unsigned long obj)
214{ 533{
215 struct device *dev = &hr_dev->pdev->dev; 534 struct device *dev = hr_dev->dev;
216 int ret = 0; 535 int ret = 0;
217 unsigned long i; 536 unsigned long i;
218 537
219 i = (obj & (table->num_obj - 1)) / (HNS_ROCE_TABLE_CHUNK_SIZE / 538 if (hns_roce_check_whether_mhop(hr_dev, table->type))
539 return hns_roce_table_mhop_get(hr_dev, table, obj);
540
541 i = (obj & (table->num_obj - 1)) / (table->table_chunk_size /
220 table->obj_size); 542 table->obj_size);
221 543
222 mutex_lock(&table->mutex); 544 mutex_lock(&table->mutex);
@@ -227,7 +549,8 @@ int hns_roce_table_get(struct hns_roce_dev *hr_dev,
227 } 549 }
228 550
229 table->hem[i] = hns_roce_alloc_hem(hr_dev, 551 table->hem[i] = hns_roce_alloc_hem(hr_dev,
230 HNS_ROCE_TABLE_CHUNK_SIZE >> PAGE_SHIFT, 552 table->table_chunk_size >> PAGE_SHIFT,
553 table->table_chunk_size,
231 (table->lowmem ? GFP_KERNEL : 554 (table->lowmem ? GFP_KERNEL :
232 GFP_HIGHUSER) | __GFP_NOWARN); 555 GFP_HIGHUSER) | __GFP_NOWARN);
233 if (!table->hem[i]) { 556 if (!table->hem[i]) {
@@ -237,6 +560,8 @@ int hns_roce_table_get(struct hns_roce_dev *hr_dev,
237 560
238 /* Set HEM base address(128K/page, pa) to Hardware */ 561 /* Set HEM base address(128K/page, pa) to Hardware */
239 if (hns_roce_set_hem(hr_dev, table, obj)) { 562 if (hns_roce_set_hem(hr_dev, table, obj)) {
563 hns_roce_free_hem(hr_dev, table->hem[i]);
564 table->hem[i] = NULL;
240 ret = -ENODEV; 565 ret = -ENODEV;
241 dev_err(dev, "set HEM base address to HW failed.\n"); 566 dev_err(dev, "set HEM base address to HW failed.\n");
242 goto out; 567 goto out;
@@ -248,20 +573,139 @@ out:
248 return ret; 573 return ret;
249} 574}
250 575
576static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
577 struct hns_roce_hem_table *table,
578 unsigned long obj,
579 int check_refcount)
580{
581 struct device *dev = hr_dev->dev;
582 struct hns_roce_hem_mhop mhop;
583 unsigned long mhop_obj = obj;
584 u32 bt_chunk_size;
585 u32 chunk_ba_num;
586 u32 hop_num;
587 u32 start_idx;
588 u32 bt_num;
589 u64 hem_idx;
590 u64 bt_l1_idx = 0;
591 int ret;
592
593 ret = hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
594 if (ret)
595 return;
596
597 bt_chunk_size = mhop.bt_chunk_size;
598 hop_num = mhop.hop_num;
599 chunk_ba_num = bt_chunk_size / 8;
600
601 bt_num = hns_roce_get_bt_num(table->type, hop_num);
602 switch (bt_num) {
603 case 3:
604 hem_idx = mhop.l0_idx * chunk_ba_num * chunk_ba_num +
605 mhop.l1_idx * chunk_ba_num + mhop.l2_idx;
606 bt_l1_idx = mhop.l0_idx * chunk_ba_num + mhop.l1_idx;
607 break;
608 case 2:
609 hem_idx = mhop.l0_idx * chunk_ba_num + mhop.l1_idx;
610 break;
611 case 1:
612 hem_idx = mhop.l0_idx;
613 break;
614 default:
615 dev_err(dev, "Table %d not support hop_num = %d!\n",
616 table->type, hop_num);
617 return;
618 }
619
620 mutex_lock(&table->mutex);
621
622 if (check_refcount && (--table->hem[hem_idx]->refcount > 0)) {
623 mutex_unlock(&table->mutex);
624 return;
625 }
626
627 if (table->type < HEM_TYPE_MTT && hop_num == 1) {
628 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 1))
629 dev_warn(dev, "Clear HEM base address failed.\n");
630 } else if (table->type < HEM_TYPE_MTT && hop_num == 2) {
631 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 2))
632 dev_warn(dev, "Clear HEM base address failed.\n");
633 } else if (table->type < HEM_TYPE_MTT &&
634 hop_num == HNS_ROCE_HOP_NUM_0) {
635 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
636 dev_warn(dev, "Clear HEM base address failed.\n");
637 }
638
639 /*
640 * free buffer space chunk for QPC/MTPT/CQC/SRQC.
641 * free bt space chunk for MTT/CQE.
642 */
643 hns_roce_free_hem(hr_dev, table->hem[hem_idx]);
644 table->hem[hem_idx] = NULL;
645
646 if (check_whether_bt_num_2(table->type, hop_num)) {
647 start_idx = mhop.l0_idx * chunk_ba_num;
648 if (hns_roce_check_hem_null(table->hem, start_idx,
649 chunk_ba_num)) {
650 if (table->type < HEM_TYPE_MTT &&
651 hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
652 dev_warn(dev, "Clear HEM base address failed.\n");
653
654 dma_free_coherent(dev, bt_chunk_size,
655 table->bt_l0[mhop.l0_idx],
656 table->bt_l0_dma_addr[mhop.l0_idx]);
657 table->bt_l0[mhop.l0_idx] = NULL;
658 }
659 } else if (check_whether_bt_num_3(table->type, hop_num)) {
660 start_idx = mhop.l0_idx * chunk_ba_num * chunk_ba_num +
661 mhop.l1_idx * chunk_ba_num;
662 if (hns_roce_check_hem_null(table->hem, start_idx,
663 chunk_ba_num)) {
664 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 1))
665 dev_warn(dev, "Clear HEM base address failed.\n");
666
667 dma_free_coherent(dev, bt_chunk_size,
668 table->bt_l1[bt_l1_idx],
669 table->bt_l1_dma_addr[bt_l1_idx]);
670 table->bt_l1[bt_l1_idx] = NULL;
671
672 start_idx = mhop.l0_idx * chunk_ba_num;
673 if (hns_roce_check_bt_null(table->bt_l1, start_idx,
674 chunk_ba_num)) {
675 if (hr_dev->hw->clear_hem(hr_dev, table, obj,
676 0))
677 dev_warn(dev, "Clear HEM base address failed.\n");
678
679 dma_free_coherent(dev, bt_chunk_size,
680 table->bt_l0[mhop.l0_idx],
681 table->bt_l0_dma_addr[mhop.l0_idx]);
682 table->bt_l0[mhop.l0_idx] = NULL;
683 }
684 }
685 }
686
687 mutex_unlock(&table->mutex);
688}
689
251void hns_roce_table_put(struct hns_roce_dev *hr_dev, 690void hns_roce_table_put(struct hns_roce_dev *hr_dev,
252 struct hns_roce_hem_table *table, unsigned long obj) 691 struct hns_roce_hem_table *table, unsigned long obj)
253{ 692{
254 struct device *dev = &hr_dev->pdev->dev; 693 struct device *dev = hr_dev->dev;
255 unsigned long i; 694 unsigned long i;
256 695
696 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
697 hns_roce_table_mhop_put(hr_dev, table, obj, 1);
698 return;
699 }
700
257 i = (obj & (table->num_obj - 1)) / 701 i = (obj & (table->num_obj - 1)) /
258 (HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size); 702 (table->table_chunk_size / table->obj_size);
259 703
260 mutex_lock(&table->mutex); 704 mutex_lock(&table->mutex);
261 705
262 if (--table->hem[i]->refcount == 0) { 706 if (--table->hem[i]->refcount == 0) {
263 /* Clear HEM base address */ 707 /* Clear HEM base address */
264 if (hr_dev->hw->clear_hem(hr_dev, table, obj)) 708 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
265 dev_warn(dev, "Clear HEM base address failed.\n"); 709 dev_warn(dev, "Clear HEM base address failed.\n");
266 710
267 hns_roce_free_hem(hr_dev, table->hem[i]); 711 hns_roce_free_hem(hr_dev, table->hem[i]);
@@ -271,23 +715,48 @@ void hns_roce_table_put(struct hns_roce_dev *hr_dev,
271 mutex_unlock(&table->mutex); 715 mutex_unlock(&table->mutex);
272} 716}
273 717
274void *hns_roce_table_find(struct hns_roce_hem_table *table, unsigned long obj, 718void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
275 dma_addr_t *dma_handle) 719 struct hns_roce_hem_table *table,
720 unsigned long obj, dma_addr_t *dma_handle)
276{ 721{
277 struct hns_roce_hem_chunk *chunk; 722 struct hns_roce_hem_chunk *chunk;
278 unsigned long idx; 723 struct hns_roce_hem_mhop mhop;
279 int i;
280 int offset, dma_offset;
281 struct hns_roce_hem *hem; 724 struct hns_roce_hem *hem;
282 struct page *page = NULL; 725 struct page *page = NULL;
726 unsigned long mhop_obj = obj;
727 unsigned long obj_per_chunk;
728 unsigned long idx_offset;
729 int offset, dma_offset;
730 int i, j;
731 u32 hem_idx = 0;
283 732
284 if (!table->lowmem) 733 if (!table->lowmem)
285 return NULL; 734 return NULL;
286 735
287 mutex_lock(&table->mutex); 736 mutex_lock(&table->mutex);
288 idx = (obj & (table->num_obj - 1)) * table->obj_size; 737
289 hem = table->hem[idx / HNS_ROCE_TABLE_CHUNK_SIZE]; 738 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) {
290 dma_offset = offset = idx % HNS_ROCE_TABLE_CHUNK_SIZE; 739 obj_per_chunk = table->table_chunk_size / table->obj_size;
740 hem = table->hem[(obj & (table->num_obj - 1)) / obj_per_chunk];
741 idx_offset = (obj & (table->num_obj - 1)) % obj_per_chunk;
742 dma_offset = offset = idx_offset * table->obj_size;
743 } else {
744 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
745 /* mtt mhop */
746 i = mhop.l0_idx;
747 j = mhop.l1_idx;
748 if (mhop.hop_num == 2)
749 hem_idx = i * (mhop.bt_chunk_size / 8) + j;
750 else if (mhop.hop_num == 1 ||
751 mhop.hop_num == HNS_ROCE_HOP_NUM_0)
752 hem_idx = i;
753
754 hem = table->hem[hem_idx];
755 dma_offset = offset = (obj & (table->num_obj - 1)) *
756 table->obj_size % mhop.bt_chunk_size;
757 if (mhop.hop_num == 2)
758 dma_offset = offset = 0;
759 }
291 760
292 if (!hem) 761 if (!hem)
293 goto out; 762 goto out;
@@ -314,14 +783,21 @@ out:
314 mutex_unlock(&table->mutex); 783 mutex_unlock(&table->mutex);
315 return page ? lowmem_page_address(page) + offset : NULL; 784 return page ? lowmem_page_address(page) + offset : NULL;
316} 785}
786EXPORT_SYMBOL_GPL(hns_roce_table_find);
317 787
318int hns_roce_table_get_range(struct hns_roce_dev *hr_dev, 788int hns_roce_table_get_range(struct hns_roce_dev *hr_dev,
319 struct hns_roce_hem_table *table, 789 struct hns_roce_hem_table *table,
320 unsigned long start, unsigned long end) 790 unsigned long start, unsigned long end)
321{ 791{
322 unsigned long inc = HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size; 792 struct hns_roce_hem_mhop mhop;
323 unsigned long i = 0; 793 unsigned long inc = table->table_chunk_size / table->obj_size;
324 int ret = 0; 794 unsigned long i;
795 int ret;
796
797 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
798 hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
799 inc = mhop.bt_chunk_size / table->obj_size;
800 }
325 801
326 /* Allocate MTT entry memory according to chunk(128K) */ 802 /* Allocate MTT entry memory according to chunk(128K) */
327 for (i = start; i <= end; i += inc) { 803 for (i = start; i <= end; i += inc) {
@@ -344,10 +820,16 @@ void hns_roce_table_put_range(struct hns_roce_dev *hr_dev,
344 struct hns_roce_hem_table *table, 820 struct hns_roce_hem_table *table,
345 unsigned long start, unsigned long end) 821 unsigned long start, unsigned long end)
346{ 822{
823 struct hns_roce_hem_mhop mhop;
824 unsigned long inc = table->table_chunk_size / table->obj_size;
347 unsigned long i; 825 unsigned long i;
348 826
349 for (i = start; i <= end; 827 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
350 i += HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size) 828 hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
829 inc = mhop.bt_chunk_size / table->obj_size;
830 }
831
832 for (i = start; i <= end; i += inc)
351 hns_roce_table_put(hr_dev, table, i); 833 hns_roce_table_put(hr_dev, table, i);
352} 834}
353 835
@@ -356,15 +838,120 @@ int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
356 unsigned long obj_size, unsigned long nobj, 838 unsigned long obj_size, unsigned long nobj,
357 int use_lowmem) 839 int use_lowmem)
358{ 840{
841 struct device *dev = hr_dev->dev;
359 unsigned long obj_per_chunk; 842 unsigned long obj_per_chunk;
360 unsigned long num_hem; 843 unsigned long num_hem;
361 844
362 obj_per_chunk = HNS_ROCE_TABLE_CHUNK_SIZE / obj_size; 845 if (!hns_roce_check_whether_mhop(hr_dev, type)) {
363 num_hem = (nobj + obj_per_chunk - 1) / obj_per_chunk; 846 table->table_chunk_size = hr_dev->caps.chunk_sz;
847 obj_per_chunk = table->table_chunk_size / obj_size;
848 num_hem = (nobj + obj_per_chunk - 1) / obj_per_chunk;
849
850 table->hem = kcalloc(num_hem, sizeof(*table->hem), GFP_KERNEL);
851 if (!table->hem)
852 return -ENOMEM;
853 } else {
854 unsigned long buf_chunk_size;
855 unsigned long bt_chunk_size;
856 unsigned long bt_chunk_num;
857 unsigned long num_bt_l0 = 0;
858 u32 hop_num;
859
860 switch (type) {
861 case HEM_TYPE_QPC:
862 buf_chunk_size = 1 << (hr_dev->caps.qpc_buf_pg_sz
863 + PAGE_SHIFT);
864 bt_chunk_size = 1 << (hr_dev->caps.qpc_ba_pg_sz
865 + PAGE_SHIFT);
866 num_bt_l0 = hr_dev->caps.qpc_bt_num;
867 hop_num = hr_dev->caps.qpc_hop_num;
868 break;
869 case HEM_TYPE_MTPT:
870 buf_chunk_size = 1 << (hr_dev->caps.mpt_buf_pg_sz
871 + PAGE_SHIFT);
872 bt_chunk_size = 1 << (hr_dev->caps.mpt_ba_pg_sz
873 + PAGE_SHIFT);
874 num_bt_l0 = hr_dev->caps.mpt_bt_num;
875 hop_num = hr_dev->caps.mpt_hop_num;
876 break;
877 case HEM_TYPE_CQC:
878 buf_chunk_size = 1 << (hr_dev->caps.cqc_buf_pg_sz
879 + PAGE_SHIFT);
880 bt_chunk_size = 1 << (hr_dev->caps.cqc_ba_pg_sz
881 + PAGE_SHIFT);
882 num_bt_l0 = hr_dev->caps.cqc_bt_num;
883 hop_num = hr_dev->caps.cqc_hop_num;
884 break;
885 case HEM_TYPE_SRQC:
886 buf_chunk_size = 1 << (hr_dev->caps.srqc_buf_pg_sz
887 + PAGE_SHIFT);
888 bt_chunk_size = 1 << (hr_dev->caps.srqc_ba_pg_sz
889 + PAGE_SHIFT);
890 num_bt_l0 = hr_dev->caps.srqc_bt_num;
891 hop_num = hr_dev->caps.srqc_hop_num;
892 break;
893 case HEM_TYPE_MTT:
894 buf_chunk_size = 1 << (hr_dev->caps.mtt_ba_pg_sz
895 + PAGE_SHIFT);
896 bt_chunk_size = buf_chunk_size;
897 hop_num = hr_dev->caps.mtt_hop_num;
898 break;
899 case HEM_TYPE_CQE:
900 buf_chunk_size = 1 << (hr_dev->caps.cqe_ba_pg_sz
901 + PAGE_SHIFT);
902 bt_chunk_size = buf_chunk_size;
903 hop_num = hr_dev->caps.cqe_hop_num;
904 break;
905 default:
906 dev_err(dev,
907 "Table %d not support to init hem table here!\n",
908 type);
909 return -EINVAL;
910 }
911 obj_per_chunk = buf_chunk_size / obj_size;
912 num_hem = (nobj + obj_per_chunk - 1) / obj_per_chunk;
913 bt_chunk_num = bt_chunk_size / 8;
914 if (table->type >= HEM_TYPE_MTT)
915 num_bt_l0 = bt_chunk_num;
916
917 table->hem = kcalloc(num_hem, sizeof(*table->hem),
918 GFP_KERNEL);
919 if (!table->hem)
920 goto err_kcalloc_hem_buf;
921
922 if (check_whether_bt_num_3(table->type, hop_num)) {
923 unsigned long num_bt_l1;
924
925 num_bt_l1 = (num_hem + bt_chunk_num - 1) /
926 bt_chunk_num;
927 table->bt_l1 = kcalloc(num_bt_l1,
928 sizeof(*table->bt_l1),
929 GFP_KERNEL);
930 if (!table->bt_l1)
931 goto err_kcalloc_bt_l1;
932
933 table->bt_l1_dma_addr = kcalloc(num_bt_l1,
934 sizeof(*table->bt_l1_dma_addr),
935 GFP_KERNEL);
936
937 if (!table->bt_l1_dma_addr)
938 goto err_kcalloc_l1_dma;
939 }
364 940
365 table->hem = kcalloc(num_hem, sizeof(*table->hem), GFP_KERNEL); 941 if (check_whether_bt_num_2(table->type, hop_num) ||
366 if (!table->hem) 942 check_whether_bt_num_3(table->type, hop_num)) {
367 return -ENOMEM; 943 table->bt_l0 = kcalloc(num_bt_l0, sizeof(*table->bt_l0),
944 GFP_KERNEL);
945 if (!table->bt_l0)
946 goto err_kcalloc_bt_l0;
947
948 table->bt_l0_dma_addr = kcalloc(num_bt_l0,
949 sizeof(*table->bt_l0_dma_addr),
950 GFP_KERNEL);
951 if (!table->bt_l0_dma_addr)
952 goto err_kcalloc_l0_dma;
953 }
954 }
368 955
369 table->type = type; 956 table->type = type;
370 table->num_hem = num_hem; 957 table->num_hem = num_hem;
@@ -374,18 +961,72 @@ int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
374 mutex_init(&table->mutex); 961 mutex_init(&table->mutex);
375 962
376 return 0; 963 return 0;
964
965err_kcalloc_l0_dma:
966 kfree(table->bt_l0);
967 table->bt_l0 = NULL;
968
969err_kcalloc_bt_l0:
970 kfree(table->bt_l1_dma_addr);
971 table->bt_l1_dma_addr = NULL;
972
973err_kcalloc_l1_dma:
974 kfree(table->bt_l1);
975 table->bt_l1 = NULL;
976
977err_kcalloc_bt_l1:
978 kfree(table->hem);
979 table->hem = NULL;
980
981err_kcalloc_hem_buf:
982 return -ENOMEM;
983}
984
985static void hns_roce_cleanup_mhop_hem_table(struct hns_roce_dev *hr_dev,
986 struct hns_roce_hem_table *table)
987{
988 struct hns_roce_hem_mhop mhop;
989 u32 buf_chunk_size;
990 int i;
991 u64 obj;
992
993 hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
994 buf_chunk_size = table->type < HEM_TYPE_MTT ? mhop.buf_chunk_size :
995 mhop.bt_chunk_size;
996
997 for (i = 0; i < table->num_hem; ++i) {
998 obj = i * buf_chunk_size / table->obj_size;
999 if (table->hem[i])
1000 hns_roce_table_mhop_put(hr_dev, table, obj, 0);
1001 }
1002
1003 kfree(table->hem);
1004 table->hem = NULL;
1005 kfree(table->bt_l1);
1006 table->bt_l1 = NULL;
1007 kfree(table->bt_l1_dma_addr);
1008 table->bt_l1_dma_addr = NULL;
1009 kfree(table->bt_l0);
1010 table->bt_l0 = NULL;
1011 kfree(table->bt_l0_dma_addr);
1012 table->bt_l0_dma_addr = NULL;
377} 1013}
378 1014
379void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev, 1015void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
380 struct hns_roce_hem_table *table) 1016 struct hns_roce_hem_table *table)
381{ 1017{
382 struct device *dev = &hr_dev->pdev->dev; 1018 struct device *dev = hr_dev->dev;
383 unsigned long i; 1019 unsigned long i;
384 1020
1021 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
1022 hns_roce_cleanup_mhop_hem_table(hr_dev, table);
1023 return;
1024 }
1025
385 for (i = 0; i < table->num_hem; ++i) 1026 for (i = 0; i < table->num_hem; ++i)
386 if (table->hem[i]) { 1027 if (table->hem[i]) {
387 if (hr_dev->hw->clear_hem(hr_dev, table, 1028 if (hr_dev->hw->clear_hem(hr_dev, table,
388 i * HNS_ROCE_TABLE_CHUNK_SIZE / table->obj_size)) 1029 i * table->table_chunk_size / table->obj_size, 0))
389 dev_err(dev, "Clear HEM base address failed.\n"); 1030 dev_err(dev, "Clear HEM base address failed.\n");
390 1031
391 hns_roce_free_hem(hr_dev, table->hem[i]); 1032 hns_roce_free_hem(hr_dev, table->hem[i]);
@@ -398,7 +1039,13 @@ void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev)
398{ 1039{
399 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 1040 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
400 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 1041 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
1042 if (hr_dev->caps.trrl_entry_sz)
1043 hns_roce_cleanup_hem_table(hr_dev,
1044 &hr_dev->qp_table.trrl_table);
401 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 1045 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
402 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 1046 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
403 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table); 1047 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
1048 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
1049 hns_roce_cleanup_hem_table(hr_dev,
1050 &hr_dev->mr_table.mtt_cqe_table);
404} 1051}
diff --git a/drivers/infiniband/hw/hns/hns_roce_hem.h b/drivers/infiniband/hw/hns/hns_roce_hem.h
index 435748858252..db66db12075e 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hem.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hem.h
@@ -47,13 +47,27 @@ enum {
47 47
48 /* UNMAP HEM */ 48 /* UNMAP HEM */
49 HEM_TYPE_MTT, 49 HEM_TYPE_MTT,
50 HEM_TYPE_CQE,
50 HEM_TYPE_IRRL, 51 HEM_TYPE_IRRL,
52 HEM_TYPE_TRRL,
51}; 53};
52 54
53#define HNS_ROCE_HEM_CHUNK_LEN \ 55#define HNS_ROCE_HEM_CHUNK_LEN \
54 ((256 - sizeof(struct list_head) - 2 * sizeof(int)) / \ 56 ((256 - sizeof(struct list_head) - 2 * sizeof(int)) / \
55 (sizeof(struct scatterlist))) 57 (sizeof(struct scatterlist)))
56 58
59#define check_whether_bt_num_3(type, hop_num) \
60 (type < HEM_TYPE_MTT && hop_num == 2)
61
62#define check_whether_bt_num_2(type, hop_num) \
63 ((type < HEM_TYPE_MTT && hop_num == 1) || \
64 (type >= HEM_TYPE_MTT && hop_num == 2))
65
66#define check_whether_bt_num_1(type, hop_num) \
67 ((type < HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0) || \
68 (type >= HEM_TYPE_MTT && hop_num == 1) || \
69 (type >= HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0))
70
57enum { 71enum {
58 HNS_ROCE_HEM_PAGE_SHIFT = 12, 72 HNS_ROCE_HEM_PAGE_SHIFT = 12,
59 HNS_ROCE_HEM_PAGE_SIZE = 1 << HNS_ROCE_HEM_PAGE_SHIFT, 73 HNS_ROCE_HEM_PAGE_SIZE = 1 << HNS_ROCE_HEM_PAGE_SHIFT,
@@ -77,12 +91,23 @@ struct hns_roce_hem_iter {
77 int page_idx; 91 int page_idx;
78}; 92};
79 93
94struct hns_roce_hem_mhop {
95 u32 hop_num;
96 u32 buf_chunk_size;
97 u32 bt_chunk_size;
98 u32 ba_l0_num;
99 u32 l0_idx;/* level 0 base address table index */
100 u32 l1_idx;/* level 1 base address table index */
101 u32 l2_idx;/* level 2 base address table index */
102};
103
80void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem); 104void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem);
81int hns_roce_table_get(struct hns_roce_dev *hr_dev, 105int hns_roce_table_get(struct hns_roce_dev *hr_dev,
82 struct hns_roce_hem_table *table, unsigned long obj); 106 struct hns_roce_hem_table *table, unsigned long obj);
83void hns_roce_table_put(struct hns_roce_dev *hr_dev, 107void hns_roce_table_put(struct hns_roce_dev *hr_dev,
84 struct hns_roce_hem_table *table, unsigned long obj); 108 struct hns_roce_hem_table *table, unsigned long obj);
85void *hns_roce_table_find(struct hns_roce_hem_table *table, unsigned long obj, 109void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
110 struct hns_roce_hem_table *table, unsigned long obj,
86 dma_addr_t *dma_handle); 111 dma_addr_t *dma_handle);
87int hns_roce_table_get_range(struct hns_roce_dev *hr_dev, 112int hns_roce_table_get_range(struct hns_roce_dev *hr_dev,
88 struct hns_roce_hem_table *table, 113 struct hns_roce_hem_table *table,
@@ -97,6 +122,10 @@ int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
97void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev, 122void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
98 struct hns_roce_hem_table *table); 123 struct hns_roce_hem_table *table);
99void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev); 124void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev);
125int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev,
126 struct hns_roce_hem_table *table, unsigned long *obj,
127 struct hns_roce_hem_mhop *mhop);
128bool hns_roce_check_whether_mhop(struct hns_roce_dev *hr_dev, u32 type);
100 129
101static inline void hns_roce_hem_first(struct hns_roce_hem *hem, 130static inline void hns_roce_hem_first(struct hns_roce_hem *hem,
102 struct hns_roce_hem_iter *iter) 131 struct hns_roce_hem_iter *iter)
@@ -105,7 +134,7 @@ static inline void hns_roce_hem_first(struct hns_roce_hem *hem,
105 iter->chunk = list_empty(&hem->chunk_list) ? NULL : 134 iter->chunk = list_empty(&hem->chunk_list) ? NULL :
106 list_entry(hem->chunk_list.next, 135 list_entry(hem->chunk_list.next,
107 struct hns_roce_hem_chunk, list); 136 struct hns_roce_hem_chunk, list);
108 iter->page_idx = 0; 137 iter->page_idx = 0;
109} 138}
110 139
111static inline int hns_roce_hem_last(struct hns_roce_hem_iter *iter) 140static inline int hns_roce_hem_last(struct hns_roce_hem_iter *iter)
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
index 747efd1ae5a6..af27168faf0f 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
@@ -34,6 +34,7 @@
34#include <linux/acpi.h> 34#include <linux/acpi.h>
35#include <linux/etherdevice.h> 35#include <linux/etherdevice.h>
36#include <linux/of.h> 36#include <linux/of.h>
37#include <linux/of_platform.h>
37#include <rdma/ib_umem.h> 38#include <rdma/ib_umem.h>
38#include "hns_roce_common.h" 39#include "hns_roce_common.h"
39#include "hns_roce_device.h" 40#include "hns_roce_device.h"
@@ -56,8 +57,8 @@ static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
56 rseg->len = 0; 57 rseg->len = 0;
57} 58}
58 59
59int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 60static int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
60 struct ib_send_wr **bad_wr) 61 struct ib_send_wr **bad_wr)
61{ 62{
62 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 63 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
63 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 64 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
@@ -316,8 +317,8 @@ out:
316 return ret; 317 return ret;
317} 318}
318 319
319int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 320static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
320 struct ib_recv_wr **bad_wr) 321 struct ib_recv_wr **bad_wr)
321{ 322{
322 int ret = 0; 323 int ret = 0;
323 int nreq = 0; 324 int nreq = 0;
@@ -472,7 +473,7 @@ static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
472 dma_addr_t sdb_dma_addr; 473 dma_addr_t sdb_dma_addr;
473 u32 val; 474 u32 val;
474 475
475 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 476 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
476 db = &priv->db_table; 477 db = &priv->db_table;
477 478
478 /* Configure extend SDB threshold */ 479 /* Configure extend SDB threshold */
@@ -511,7 +512,7 @@ static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
511 dma_addr_t odb_dma_addr; 512 dma_addr_t odb_dma_addr;
512 u32 val; 513 u32 val;
513 514
514 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 515 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
515 db = &priv->db_table; 516 db = &priv->db_table;
516 517
517 /* Configure extend ODB threshold */ 518 /* Configure extend ODB threshold */
@@ -547,7 +548,7 @@ static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
547 dma_addr_t odb_dma_addr; 548 dma_addr_t odb_dma_addr;
548 int ret = 0; 549 int ret = 0;
549 550
550 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 551 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
551 db = &priv->db_table; 552 db = &priv->db_table;
552 553
553 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL); 554 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
@@ -668,7 +669,7 @@ static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
668 u8 port = 0; 669 u8 port = 0;
669 u8 sl; 670 u8 sl;
670 671
671 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 672 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
672 free_mr = &priv->free_mr; 673 free_mr = &priv->free_mr;
673 674
674 /* Reserved cq for loop qp */ 675 /* Reserved cq for loop qp */
@@ -816,7 +817,7 @@ static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
816 int ret; 817 int ret;
817 int i; 818 int i;
818 819
819 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 820 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
820 free_mr = &priv->free_mr; 821 free_mr = &priv->free_mr;
821 822
822 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) { 823 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
@@ -850,7 +851,7 @@ static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
850 u32 odb_evt_mod; 851 u32 odb_evt_mod;
851 int ret = 0; 852 int ret = 0;
852 853
853 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 854 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
854 db = &priv->db_table; 855 db = &priv->db_table;
855 856
856 memset(db, 0, sizeof(*db)); 857 memset(db, 0, sizeof(*db));
@@ -876,7 +877,7 @@ static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
876 return 0; 877 return 0;
877} 878}
878 879
879void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work) 880static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
880{ 881{
881 struct hns_roce_recreate_lp_qp_work *lp_qp_work; 882 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
882 struct hns_roce_dev *hr_dev; 883 struct hns_roce_dev *hr_dev;
@@ -906,11 +907,13 @@ static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
906 unsigned long end = 907 unsigned long end =
907 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies; 908 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
908 909
909 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 910 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
910 free_mr = &priv->free_mr; 911 free_mr = &priv->free_mr;
911 912
912 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work), 913 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
913 GFP_KERNEL); 914 GFP_KERNEL);
915 if (!lp_qp_work)
916 return -ENOMEM;
914 917
915 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn); 918 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
916 919
@@ -982,7 +985,7 @@ static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
982 hr_dev = to_hr_dev(mr_work->ib_dev); 985 hr_dev = to_hr_dev(mr_work->ib_dev);
983 dev = &hr_dev->pdev->dev; 986 dev = &hr_dev->pdev->dev;
984 987
985 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 988 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
986 free_mr = &priv->free_mr; 989 free_mr = &priv->free_mr;
987 mr_free_cq = free_mr->mr_free_cq; 990 mr_free_cq = free_mr->mr_free_cq;
988 991
@@ -1001,6 +1004,11 @@ static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1001 } 1004 }
1002 } 1005 }
1003 1006
1007 if (!ne) {
1008 dev_err(dev, "Reserved loop qp is absent!\n");
1009 goto free_work;
1010 }
1011
1004 do { 1012 do {
1005 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc); 1013 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1006 if (ret < 0) { 1014 if (ret < 0) {
@@ -1025,7 +1033,8 @@ free_work:
1025 kfree(mr_work); 1033 kfree(mr_work);
1026} 1034}
1027 1035
1028int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr) 1036static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1037 struct hns_roce_mr *mr)
1029{ 1038{
1030 struct device *dev = &hr_dev->pdev->dev; 1039 struct device *dev = &hr_dev->pdev->dev;
1031 struct hns_roce_mr_free_work *mr_work; 1040 struct hns_roce_mr_free_work *mr_work;
@@ -1038,7 +1047,7 @@ int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr)
1038 int npages; 1047 int npages;
1039 int ret = 0; 1048 int ret = 0;
1040 1049
1041 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1050 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1042 free_mr = &priv->free_mr; 1051 free_mr = &priv->free_mr;
1043 1052
1044 if (mr->enabled) { 1053 if (mr->enabled) {
@@ -1103,7 +1112,7 @@ static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1103 struct hns_roce_v1_priv *priv; 1112 struct hns_roce_v1_priv *priv;
1104 struct hns_roce_db_table *db; 1113 struct hns_roce_db_table *db;
1105 1114
1106 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1115 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1107 db = &priv->db_table; 1116 db = &priv->db_table;
1108 1117
1109 if (db->sdb_ext_mod) { 1118 if (db->sdb_ext_mod) {
@@ -1133,7 +1142,7 @@ static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1133 struct hns_roce_raq_table *raq; 1142 struct hns_roce_raq_table *raq;
1134 struct device *dev = &hr_dev->pdev->dev; 1143 struct device *dev = &hr_dev->pdev->dev;
1135 1144
1136 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1145 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1137 raq = &priv->raq_table; 1146 raq = &priv->raq_table;
1138 1147
1139 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL); 1148 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
@@ -1210,7 +1219,7 @@ static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1210 struct hns_roce_v1_priv *priv; 1219 struct hns_roce_v1_priv *priv;
1211 struct hns_roce_raq_table *raq; 1220 struct hns_roce_raq_table *raq;
1212 1221
1213 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1222 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1214 raq = &priv->raq_table; 1223 raq = &priv->raq_table;
1215 1224
1216 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf, 1225 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
@@ -1244,7 +1253,7 @@ static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1244 struct hns_roce_v1_priv *priv; 1253 struct hns_roce_v1_priv *priv;
1245 int ret; 1254 int ret;
1246 1255
1247 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1256 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1248 1257
1249 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev, 1258 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1250 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map, 1259 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
@@ -1286,7 +1295,7 @@ static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1286 struct device *dev = &hr_dev->pdev->dev; 1295 struct device *dev = &hr_dev->pdev->dev;
1287 struct hns_roce_v1_priv *priv; 1296 struct hns_roce_v1_priv *priv;
1288 1297
1289 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1298 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1290 1299
1291 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE, 1300 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1292 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map); 1301 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
@@ -1304,7 +1313,7 @@ static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1304 struct hns_roce_buf_list *tptr_buf; 1313 struct hns_roce_buf_list *tptr_buf;
1305 struct hns_roce_v1_priv *priv; 1314 struct hns_roce_v1_priv *priv;
1306 1315
1307 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1316 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1308 tptr_buf = &priv->tptr_table.tptr_buf; 1317 tptr_buf = &priv->tptr_table.tptr_buf;
1309 1318
1310 /* 1319 /*
@@ -1330,7 +1339,7 @@ static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1330 struct hns_roce_buf_list *tptr_buf; 1339 struct hns_roce_buf_list *tptr_buf;
1331 struct hns_roce_v1_priv *priv; 1340 struct hns_roce_v1_priv *priv;
1332 1341
1333 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1342 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1334 tptr_buf = &priv->tptr_table.tptr_buf; 1343 tptr_buf = &priv->tptr_table.tptr_buf;
1335 1344
1336 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE, 1345 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
@@ -1344,7 +1353,7 @@ static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1344 struct hns_roce_v1_priv *priv; 1353 struct hns_roce_v1_priv *priv;
1345 int ret = 0; 1354 int ret = 0;
1346 1355
1347 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1356 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1348 free_mr = &priv->free_mr; 1357 free_mr = &priv->free_mr;
1349 1358
1350 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr"); 1359 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
@@ -1368,7 +1377,7 @@ static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1368 struct hns_roce_free_mr *free_mr; 1377 struct hns_roce_free_mr *free_mr;
1369 struct hns_roce_v1_priv *priv; 1378 struct hns_roce_v1_priv *priv;
1370 1379
1371 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1380 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1372 free_mr = &priv->free_mr; 1381 free_mr = &priv->free_mr;
1373 1382
1374 flush_workqueue(free_mr->free_mr_wq); 1383 flush_workqueue(free_mr->free_mr_wq);
@@ -1383,7 +1392,7 @@ static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1383 * @enable: true -- drop reset, false -- reset 1392 * @enable: true -- drop reset, false -- reset
1384 * return 0 - success , negative --fail 1393 * return 0 - success , negative --fail
1385 */ 1394 */
1386int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset) 1395static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1387{ 1396{
1388 struct device_node *dsaf_node; 1397 struct device_node *dsaf_node;
1389 struct device *dev = &hr_dev->pdev->dev; 1398 struct device *dev = &hr_dev->pdev->dev;
@@ -1432,7 +1441,7 @@ static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1432 struct hns_roce_v1_priv *priv; 1441 struct hns_roce_v1_priv *priv;
1433 struct hns_roce_des_qp *des_qp; 1442 struct hns_roce_des_qp *des_qp;
1434 1443
1435 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1444 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1436 des_qp = &priv->des_qp; 1445 des_qp = &priv->des_qp;
1437 1446
1438 des_qp->requeue_flag = 1; 1447 des_qp->requeue_flag = 1;
@@ -1450,7 +1459,7 @@ static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1450 struct hns_roce_v1_priv *priv; 1459 struct hns_roce_v1_priv *priv;
1451 struct hns_roce_des_qp *des_qp; 1460 struct hns_roce_des_qp *des_qp;
1452 1461
1453 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 1462 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1454 des_qp = &priv->des_qp; 1463 des_qp = &priv->des_qp;
1455 1464
1456 des_qp->requeue_flag = 0; 1465 des_qp->requeue_flag = 0;
@@ -1458,7 +1467,7 @@ static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1458 destroy_workqueue(des_qp->qp_wq); 1467 destroy_workqueue(des_qp->qp_wq);
1459} 1468}
1460 1469
1461void hns_roce_v1_profile(struct hns_roce_dev *hr_dev) 1470static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1462{ 1471{
1463 int i = 0; 1472 int i = 0;
1464 struct hns_roce_caps *caps = &hr_dev->caps; 1473 struct hns_roce_caps *caps = &hr_dev->caps;
@@ -1474,7 +1483,9 @@ void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1474 1483
1475 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM; 1484 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1476 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM; 1485 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1486 caps->min_wqes = HNS_ROCE_MIN_WQE_NUM;
1477 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM; 1487 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1488 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1478 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM; 1489 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1479 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM; 1490 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1480 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM; 1491 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
@@ -1503,6 +1514,7 @@ void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1503 caps->reserved_mrws = 1; 1514 caps->reserved_mrws = 1;
1504 caps->reserved_uars = 0; 1515 caps->reserved_uars = 0;
1505 caps->reserved_cqs = 0; 1516 caps->reserved_cqs = 0;
1517 caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1506 1518
1507 for (i = 0; i < caps->num_ports; i++) 1519 for (i = 0; i < caps->num_ports; i++)
1508 caps->pkey_table_len[i] = 1; 1520 caps->pkey_table_len[i] = 1;
@@ -1524,9 +1536,11 @@ void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1524 caps->local_ca_ack_delay = le32_to_cpu(roce_read(hr_dev, 1536 caps->local_ca_ack_delay = le32_to_cpu(roce_read(hr_dev,
1525 ROCEE_ACK_DELAY_REG)); 1537 ROCEE_ACK_DELAY_REG));
1526 caps->max_mtu = IB_MTU_2048; 1538 caps->max_mtu = IB_MTU_2048;
1539
1540 return 0;
1527} 1541}
1528 1542
1529int hns_roce_v1_init(struct hns_roce_dev *hr_dev) 1543static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1530{ 1544{
1531 int ret; 1545 int ret;
1532 u32 val; 1546 u32 val;
@@ -1605,7 +1619,7 @@ error_failed_raq_init:
1605 return ret; 1619 return ret;
1606} 1620}
1607 1621
1608void hns_roce_v1_exit(struct hns_roce_dev *hr_dev) 1622static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1609{ 1623{
1610 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN); 1624 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1611 hns_roce_free_mr_free(hr_dev); 1625 hns_roce_free_mr_free(hr_dev);
@@ -1616,8 +1630,82 @@ void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1616 hns_roce_db_free(hr_dev); 1630 hns_roce_db_free(hr_dev);
1617} 1631}
1618 1632
1619void hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 1633static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1620 union ib_gid *gid) 1634{
1635 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1636
1637 return (!!(status & (1 << HCR_GO_BIT)));
1638}
1639
1640static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1641 u64 out_param, u32 in_modifier, u8 op_modifier,
1642 u16 op, u16 token, int event)
1643{
1644 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1645 unsigned long end;
1646 u32 val = 0;
1647
1648 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1649 while (hns_roce_v1_cmd_pending(hr_dev)) {
1650 if (time_after(jiffies, end)) {
1651 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1652 (int)jiffies, (int)end);
1653 return -EAGAIN;
1654 }
1655 cond_resched();
1656 }
1657
1658 roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1659 op);
1660 roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1661 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1662 roce_set_bit(val, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1663 roce_set_bit(val, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1664 roce_set_field(val, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1665 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1666
1667 __raw_writeq(cpu_to_le64(in_param), hcr + 0);
1668 __raw_writeq(cpu_to_le64(out_param), hcr + 2);
1669 __raw_writel(cpu_to_le32(in_modifier), hcr + 4);
1670 /* Memory barrier */
1671 wmb();
1672
1673 __raw_writel(cpu_to_le32(val), hcr + 5);
1674
1675 mmiowb();
1676
1677 return 0;
1678}
1679
1680static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1681 unsigned long timeout)
1682{
1683 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1684 unsigned long end = 0;
1685 u32 status = 0;
1686
1687 end = msecs_to_jiffies(timeout) + jiffies;
1688 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1689 cond_resched();
1690
1691 if (hns_roce_v1_cmd_pending(hr_dev)) {
1692 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1693 return -ETIMEDOUT;
1694 }
1695
1696 status = le32_to_cpu((__force __be32)
1697 __raw_readl(hcr + HCR_STATUS_OFFSET));
1698 if ((status & STATUS_MASK) != 0x1) {
1699 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1700 return -EBUSY;
1701 }
1702
1703 return 0;
1704}
1705
1706static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1707 int gid_index, union ib_gid *gid,
1708 const struct ib_gid_attr *attr)
1621{ 1709{
1622 u32 *p = NULL; 1710 u32 *p = NULL;
1623 u8 gid_idx = 0; 1711 u8 gid_idx = 0;
@@ -1639,9 +1727,12 @@ void hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
1639 p = (u32 *)&gid->raw[0xc]; 1727 p = (u32 *)&gid->raw[0xc];
1640 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG + 1728 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1641 (HNS_ROCE_V1_GID_NUM * gid_idx)); 1729 (HNS_ROCE_V1_GID_NUM * gid_idx));
1730
1731 return 0;
1642} 1732}
1643 1733
1644void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr) 1734static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1735 u8 *addr)
1645{ 1736{
1646 u32 reg_smac_l; 1737 u32 reg_smac_l;
1647 u16 reg_smac_h; 1738 u16 reg_smac_h;
@@ -1654,8 +1745,13 @@ void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1654 * because of smac not equal to dmac. 1745 * because of smac not equal to dmac.
1655 * We Need to release and create reserved qp again. 1746 * We Need to release and create reserved qp again.
1656 */ 1747 */
1657 if (hr_dev->hw->dereg_mr && hns_roce_v1_recreate_lp_qp(hr_dev)) 1748 if (hr_dev->hw->dereg_mr) {
1658 dev_warn(&hr_dev->pdev->dev, "recreate lp qp timeout!\n"); 1749 int ret;
1750
1751 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1752 if (ret && ret != -ETIMEDOUT)
1753 return ret;
1754 }
1659 1755
1660 p = (u32 *)(&addr[0]); 1756 p = (u32 *)(&addr[0]);
1661 reg_smac_l = *p; 1757 reg_smac_l = *p;
@@ -1670,10 +1766,12 @@ void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1670 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h); 1766 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1671 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET, 1767 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1672 val); 1768 val);
1769
1770 return 0;
1673} 1771}
1674 1772
1675void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port, 1773static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1676 enum ib_mtu mtu) 1774 enum ib_mtu mtu)
1677{ 1775{
1678 u32 val; 1776 u32 val;
1679 1777
@@ -1685,8 +1783,8 @@ void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1685 val); 1783 val);
1686} 1784}
1687 1785
1688int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, 1786static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1689 unsigned long mtpt_idx) 1787 unsigned long mtpt_idx)
1690{ 1788{
1691 struct hns_roce_v1_mpt_entry *mpt_entry; 1789 struct hns_roce_v1_mpt_entry *mpt_entry;
1692 struct scatterlist *sg; 1790 struct scatterlist *sg;
@@ -1858,7 +1956,7 @@ static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1858 return get_sw_cqe(hr_cq, hr_cq->cons_index); 1956 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1859} 1957}
1860 1958
1861void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index) 1959static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1862{ 1960{
1863 u32 doorbell[2]; 1961 u32 doorbell[2];
1864 1962
@@ -1931,9 +2029,10 @@ static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1931 spin_unlock_irq(&hr_cq->lock); 2029 spin_unlock_irq(&hr_cq->lock);
1932} 2030}
1933 2031
1934void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev, 2032static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1935 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 2033 struct hns_roce_cq *hr_cq, void *mb_buf,
1936 dma_addr_t dma_handle, int nent, u32 vector) 2034 u64 *mtts, dma_addr_t dma_handle, int nent,
2035 u32 vector)
1937{ 2036{
1938 struct hns_roce_cq_context *cq_context = NULL; 2037 struct hns_roce_cq_context *cq_context = NULL;
1939 struct hns_roce_buf_list *tptr_buf; 2038 struct hns_roce_buf_list *tptr_buf;
@@ -1941,7 +2040,7 @@ void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1941 dma_addr_t tptr_dma_addr; 2040 dma_addr_t tptr_dma_addr;
1942 int offset; 2041 int offset;
1943 2042
1944 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 2043 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1945 tptr_buf = &priv->tptr_table.tptr_buf; 2044 tptr_buf = &priv->tptr_table.tptr_buf;
1946 2045
1947 cq_context = mb_buf; 2046 cq_context = mb_buf;
@@ -2018,7 +2117,13 @@ void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2018 cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32); 2117 cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32);
2019} 2118}
2020 2119
2021int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 2120static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2121{
2122 return -EOPNOTSUPP;
2123}
2124
2125static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2126 enum ib_cq_notify_flags flags)
2022{ 2127{
2023 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 2128 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2024 u32 notification_flag; 2129 u32 notification_flag;
@@ -2279,8 +2384,9 @@ int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2279 return ret; 2384 return ret;
2280} 2385}
2281 2386
2282int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev, 2387static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2283 struct hns_roce_hem_table *table, int obj) 2388 struct hns_roce_hem_table *table, int obj,
2389 int step_idx)
2284{ 2390{
2285 struct device *dev = &hr_dev->pdev->dev; 2391 struct device *dev = &hr_dev->pdev->dev;
2286 struct hns_roce_v1_priv *priv; 2392 struct hns_roce_v1_priv *priv;
@@ -2289,7 +2395,7 @@ int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2289 void __iomem *bt_cmd; 2395 void __iomem *bt_cmd;
2290 u64 bt_ba = 0; 2396 u64 bt_ba = 0;
2291 2397
2292 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 2398 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2293 2399
2294 switch (table->type) { 2400 switch (table->type) {
2295 case HEM_TYPE_QPC: 2401 case HEM_TYPE_QPC:
@@ -2441,14 +2547,14 @@ static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2441 int rq_pa_start; 2547 int rq_pa_start;
2442 u32 reg_val; 2548 u32 reg_val;
2443 u64 *mtts; 2549 u64 *mtts;
2444 u32 *addr; 2550 u32 __iomem *addr;
2445 2551
2446 context = kzalloc(sizeof(*context), GFP_KERNEL); 2552 context = kzalloc(sizeof(*context), GFP_KERNEL);
2447 if (!context) 2553 if (!context)
2448 return -ENOMEM; 2554 return -ENOMEM;
2449 2555
2450 /* Search QP buf's MTTs */ 2556 /* Search QP buf's MTTs */
2451 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table, 2557 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2452 hr_qp->mtt.first_seg, &dma_handle); 2558 hr_qp->mtt.first_seg, &dma_handle);
2453 if (!mtts) { 2559 if (!mtts) {
2454 dev_err(dev, "qp buf pa find failed\n"); 2560 dev_err(dev, "qp buf pa find failed\n");
@@ -2523,8 +2629,9 @@ static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2523 QP1C_BYTES_40_SQ_CUR_IDX_S, 0); 2629 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2524 2630
2525 /* Copy context to QP1C register */ 2631 /* Copy context to QP1C register */
2526 addr = (u32 *)(hr_dev->reg_base + ROCEE_QP1C_CFG0_0_REG + 2632 addr = (u32 __iomem *)(hr_dev->reg_base +
2527 hr_qp->phy_port * sizeof(*context)); 2633 ROCEE_QP1C_CFG0_0_REG +
2634 hr_qp->phy_port * sizeof(*context));
2528 2635
2529 writel(context->qp1c_bytes_4, addr); 2636 writel(context->qp1c_bytes_4, addr);
2530 writel(context->sq_rq_bt_l, addr + 1); 2637 writel(context->sq_rq_bt_l, addr + 1);
@@ -2595,7 +2702,7 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2595 return -ENOMEM; 2702 return -ENOMEM;
2596 2703
2597 /* Search qp buf's mtts */ 2704 /* Search qp buf's mtts */
2598 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table, 2705 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2599 hr_qp->mtt.first_seg, &dma_handle); 2706 hr_qp->mtt.first_seg, &dma_handle);
2600 if (mtts == NULL) { 2707 if (mtts == NULL) {
2601 dev_err(dev, "qp buf pa find failed\n"); 2708 dev_err(dev, "qp buf pa find failed\n");
@@ -2603,8 +2710,8 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2603 } 2710 }
2604 2711
2605 /* Search IRRL's mtts */ 2712 /* Search IRRL's mtts */
2606 mtts_2 = hns_roce_table_find(&hr_dev->qp_table.irrl_table, hr_qp->qpn, 2713 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2607 &dma_handle_2); 2714 hr_qp->qpn, &dma_handle_2);
2608 if (mtts_2 == NULL) { 2715 if (mtts_2 == NULL) {
2609 dev_err(dev, "qp irrl_table find failed\n"); 2716 dev_err(dev, "qp irrl_table find failed\n");
2610 goto out; 2717 goto out;
@@ -2800,10 +2907,11 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2800 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S, 2907 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2801 ilog2((unsigned int)attr->max_dest_rd_atomic)); 2908 ilog2((unsigned int)attr->max_dest_rd_atomic));
2802 2909
2803 roce_set_field(context->qpc_bytes_36, 2910 if (attr_mask & IB_QP_DEST_QPN)
2804 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M, 2911 roce_set_field(context->qpc_bytes_36,
2805 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S, 2912 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2806 attr->dest_qp_num); 2913 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2914 attr->dest_qp_num);
2807 2915
2808 /* Configure GID index */ 2916 /* Configure GID index */
2809 port_num = rdma_ah_get_port_num(&attr->ah_attr); 2917 port_num = rdma_ah_get_port_num(&attr->ah_attr);
@@ -3143,7 +3251,7 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
3143 3251
3144 if (ibqp->uobject) { 3252 if (ibqp->uobject) {
3145 hr_qp->rq.db_reg_l = hr_dev->reg_base + 3253 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3146 ROCEE_DB_OTHERS_L_0_REG + 3254 hr_dev->odb_offset +
3147 DB_REG_OFFSET * hr_dev->priv_uar.index; 3255 DB_REG_OFFSET * hr_dev->priv_uar.index;
3148 } 3256 }
3149 3257
@@ -3177,9 +3285,10 @@ out:
3177 return ret; 3285 return ret;
3178} 3286}
3179 3287
3180int hns_roce_v1_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 3288static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3181 int attr_mask, enum ib_qp_state cur_state, 3289 const struct ib_qp_attr *attr, int attr_mask,
3182 enum ib_qp_state new_state) 3290 enum ib_qp_state cur_state,
3291 enum ib_qp_state new_state)
3183{ 3292{
3184 3293
3185 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) 3294 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
@@ -3270,6 +3379,7 @@ static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3270 qp_attr->path_mtu = IB_MTU_256; 3379 qp_attr->path_mtu = IB_MTU_256;
3271 qp_attr->path_mig_state = IB_MIG_ARMED; 3380 qp_attr->path_mig_state = IB_MIG_ARMED;
3272 qp_attr->qkey = QKEY_VAL; 3381 qp_attr->qkey = QKEY_VAL;
3382 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3273 qp_attr->rq_psn = 0; 3383 qp_attr->rq_psn = 0;
3274 qp_attr->sq_psn = 0; 3384 qp_attr->sq_psn = 0;
3275 qp_attr->dest_qp_num = 1; 3385 qp_attr->dest_qp_num = 1;
@@ -3351,6 +3461,7 @@ static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3351 QP_CONTEXT_QPC_BYTES_48_MTU_M, 3461 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3352 QP_CONTEXT_QPC_BYTES_48_MTU_S); 3462 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3353 qp_attr->path_mig_state = IB_MIG_ARMED; 3463 qp_attr->path_mig_state = IB_MIG_ARMED;
3464 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3354 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 3465 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3355 qp_attr->qkey = QKEY_VAL; 3466 qp_attr->qkey = QKEY_VAL;
3356 3467
@@ -3406,10 +3517,10 @@ static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3406 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S); 3517 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3407 qp_attr->port_num = hr_qp->port + 1; 3518 qp_attr->port_num = hr_qp->port + 1;
3408 qp_attr->sq_draining = 0; 3519 qp_attr->sq_draining = 0;
3409 qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156, 3520 qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3410 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M, 3521 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3411 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S); 3522 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3412 qp_attr->max_dest_rd_atomic = roce_get_field(context->qpc_bytes_32, 3523 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3413 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M, 3524 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3414 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S); 3525 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3415 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24, 3526 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
@@ -3444,8 +3555,9 @@ out:
3444 return ret; 3555 return ret;
3445} 3556}
3446 3557
3447int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 3558static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3448 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 3559 int qp_attr_mask,
3560 struct ib_qp_init_attr *qp_init_attr)
3449{ 3561{
3450 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3562 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3451 3563
@@ -3454,6 +3566,53 @@ int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3454 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr); 3566 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3455} 3567}
3456 3568
3569static void hns_roce_check_sdb_status(struct hns_roce_dev *hr_dev,
3570 u32 *old_send, u32 *old_retry,
3571 u32 *tsp_st, u32 *success_flags)
3572{
3573 u32 sdb_retry_cnt;
3574 u32 sdb_send_ptr;
3575 u32 cur_cnt, old_cnt;
3576 u32 send_ptr;
3577
3578 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3579 sdb_retry_cnt = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3580 cur_cnt = roce_get_field(sdb_send_ptr,
3581 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3582 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3583 roce_get_field(sdb_retry_cnt,
3584 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3585 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3586 if (!roce_get_bit(*tsp_st, ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3587 old_cnt = roce_get_field(*old_send,
3588 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3589 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3590 roce_get_field(*old_retry,
3591 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3592 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3593 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3594 *success_flags = 1;
3595 } else {
3596 old_cnt = roce_get_field(*old_send,
3597 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3598 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3599 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL) {
3600 *success_flags = 1;
3601 } else {
3602 send_ptr = roce_get_field(*old_send,
3603 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3604 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3605 roce_get_field(sdb_retry_cnt,
3606 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3607 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3608 roce_set_field(*old_send,
3609 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3610 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3611 send_ptr);
3612 }
3613 }
3614}
3615
3457static int check_qp_db_process_status(struct hns_roce_dev *hr_dev, 3616static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3458 struct hns_roce_qp *hr_qp, 3617 struct hns_roce_qp *hr_qp,
3459 u32 sdb_issue_ptr, 3618 u32 sdb_issue_ptr,
@@ -3461,12 +3620,10 @@ static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3461 u32 *wait_stage) 3620 u32 *wait_stage)
3462{ 3621{
3463 struct device *dev = &hr_dev->pdev->dev; 3622 struct device *dev = &hr_dev->pdev->dev;
3464 u32 sdb_retry_cnt, old_retry;
3465 u32 sdb_send_ptr, old_send; 3623 u32 sdb_send_ptr, old_send;
3466 u32 success_flags = 0; 3624 u32 success_flags = 0;
3467 u32 cur_cnt, old_cnt;
3468 unsigned long end; 3625 unsigned long end;
3469 u32 send_ptr; 3626 u32 old_retry;
3470 u32 inv_cnt; 3627 u32 inv_cnt;
3471 u32 tsp_st; 3628 u32 tsp_st;
3472 3629
@@ -3524,47 +3681,9 @@ static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3524 3681
3525 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS); 3682 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3526 3683
3527 sdb_send_ptr = roce_read(hr_dev, 3684 hns_roce_check_sdb_status(hr_dev, &old_send,
3528 ROCEE_SDB_SEND_PTR_REG); 3685 &old_retry, &tsp_st,
3529 sdb_retry_cnt = roce_read(hr_dev, 3686 &success_flags);
3530 ROCEE_SDB_RETRY_CNT_REG);
3531 cur_cnt = roce_get_field(sdb_send_ptr,
3532 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3533 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3534 roce_get_field(sdb_retry_cnt,
3535 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3536 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3537 if (!roce_get_bit(tsp_st,
3538 ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3539 old_cnt = roce_get_field(old_send,
3540 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3541 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3542 roce_get_field(old_retry,
3543 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3544 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3545 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3546 success_flags = 1;
3547 } else {
3548 old_cnt = roce_get_field(old_send,
3549 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3550 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3551 if (cur_cnt - old_cnt >
3552 SDB_ST_CMP_VAL) {
3553 success_flags = 1;
3554 } else {
3555 send_ptr =
3556 roce_get_field(old_send,
3557 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3558 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3559 roce_get_field(sdb_retry_cnt,
3560 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3561 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3562 roce_set_field(old_send,
3563 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3564 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3565 send_ptr);
3566 }
3567 }
3568 } while (!success_flags); 3687 } while (!success_flags);
3569 } 3688 }
3570 3689
@@ -3664,7 +3783,7 @@ static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3664 qp_work_entry = container_of(work, struct hns_roce_qp_work, work); 3783 qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3665 hr_dev = to_hr_dev(qp_work_entry->ib_dev); 3784 hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3666 dev = &hr_dev->pdev->dev; 3785 dev = &hr_dev->pdev->dev;
3667 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 3786 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3668 hr_qp = qp_work_entry->qp; 3787 hr_qp = qp_work_entry->qp;
3669 qpn = hr_qp->qpn; 3788 qpn = hr_qp->qpn;
3670 3789
@@ -3781,7 +3900,7 @@ int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3781 qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt; 3900 qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3782 qp_work->sche_cnt = qp_work_entry.sche_cnt; 3901 qp_work->sche_cnt = qp_work_entry.sche_cnt;
3783 3902
3784 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv; 3903 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3785 queue_work(priv->des_qp.qp_wq, &qp_work->work); 3904 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3786 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn); 3905 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3787 } 3906 }
@@ -3789,7 +3908,7 @@ int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3789 return 0; 3908 return 0;
3790} 3909}
3791 3910
3792int hns_roce_v1_destroy_cq(struct ib_cq *ibcq) 3911static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3793{ 3912{
3794 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3913 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3795 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3914 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
@@ -3841,18 +3960,19 @@ int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3841 return ret; 3960 return ret;
3842} 3961}
3843 3962
3844struct hns_roce_v1_priv hr_v1_priv; 3963static const struct hns_roce_hw hns_roce_hw_v1 = {
3845
3846struct hns_roce_hw hns_roce_hw_v1 = {
3847 .reset = hns_roce_v1_reset, 3964 .reset = hns_roce_v1_reset,
3848 .hw_profile = hns_roce_v1_profile, 3965 .hw_profile = hns_roce_v1_profile,
3849 .hw_init = hns_roce_v1_init, 3966 .hw_init = hns_roce_v1_init,
3850 .hw_exit = hns_roce_v1_exit, 3967 .hw_exit = hns_roce_v1_exit,
3968 .post_mbox = hns_roce_v1_post_mbox,
3969 .chk_mbox = hns_roce_v1_chk_mbox,
3851 .set_gid = hns_roce_v1_set_gid, 3970 .set_gid = hns_roce_v1_set_gid,
3852 .set_mac = hns_roce_v1_set_mac, 3971 .set_mac = hns_roce_v1_set_mac,
3853 .set_mtu = hns_roce_v1_set_mtu, 3972 .set_mtu = hns_roce_v1_set_mtu,
3854 .write_mtpt = hns_roce_v1_write_mtpt, 3973 .write_mtpt = hns_roce_v1_write_mtpt,
3855 .write_cqc = hns_roce_v1_write_cqc, 3974 .write_cqc = hns_roce_v1_write_cqc,
3975 .modify_cq = hns_roce_v1_modify_cq,
3856 .clear_hem = hns_roce_v1_clear_hem, 3976 .clear_hem = hns_roce_v1_clear_hem,
3857 .modify_qp = hns_roce_v1_modify_qp, 3977 .modify_qp = hns_roce_v1_modify_qp,
3858 .query_qp = hns_roce_v1_query_qp, 3978 .query_qp = hns_roce_v1_query_qp,
@@ -3863,5 +3983,258 @@ struct hns_roce_hw hns_roce_hw_v1 = {
3863 .poll_cq = hns_roce_v1_poll_cq, 3983 .poll_cq = hns_roce_v1_poll_cq,
3864 .dereg_mr = hns_roce_v1_dereg_mr, 3984 .dereg_mr = hns_roce_v1_dereg_mr,
3865 .destroy_cq = hns_roce_v1_destroy_cq, 3985 .destroy_cq = hns_roce_v1_destroy_cq,
3866 .priv = &hr_v1_priv,
3867}; 3986};
3987
3988static const struct of_device_id hns_roce_of_match[] = {
3989 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
3990 {},
3991};
3992MODULE_DEVICE_TABLE(of, hns_roce_of_match);
3993
3994static const struct acpi_device_id hns_roce_acpi_match[] = {
3995 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
3996 {},
3997};
3998MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
3999
4000static int hns_roce_node_match(struct device *dev, void *fwnode)
4001{
4002 return dev->fwnode == fwnode;
4003}
4004
4005static struct
4006platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4007{
4008 struct device *dev;
4009
4010 /* get the 'device' corresponding to the matching 'fwnode' */
4011 dev = bus_find_device(&platform_bus_type, NULL,
4012 fwnode, hns_roce_node_match);
4013 /* get the platform device */
4014 return dev ? to_platform_device(dev) : NULL;
4015}
4016
4017static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4018{
4019 struct device *dev = &hr_dev->pdev->dev;
4020 struct platform_device *pdev = NULL;
4021 struct net_device *netdev = NULL;
4022 struct device_node *net_node;
4023 struct resource *res;
4024 int port_cnt = 0;
4025 u8 phy_port;
4026 int ret;
4027 int i;
4028
4029 /* check if we are compatible with the underlying SoC */
4030 if (dev_of_node(dev)) {
4031 const struct of_device_id *of_id;
4032
4033 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4034 if (!of_id) {
4035 dev_err(dev, "device is not compatible!\n");
4036 return -ENXIO;
4037 }
4038 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4039 if (!hr_dev->hw) {
4040 dev_err(dev, "couldn't get H/W specific DT data!\n");
4041 return -ENXIO;
4042 }
4043 } else if (is_acpi_device_node(dev->fwnode)) {
4044 const struct acpi_device_id *acpi_id;
4045
4046 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4047 if (!acpi_id) {
4048 dev_err(dev, "device is not compatible!\n");
4049 return -ENXIO;
4050 }
4051 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4052 if (!hr_dev->hw) {
4053 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4054 return -ENXIO;
4055 }
4056 } else {
4057 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4058 return -ENXIO;
4059 }
4060
4061 /* get the mapped register base address */
4062 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4063 if (!res) {
4064 dev_err(dev, "memory resource not found!\n");
4065 return -EINVAL;
4066 }
4067 hr_dev->reg_base = devm_ioremap_resource(dev, res);
4068 if (IS_ERR(hr_dev->reg_base))
4069 return PTR_ERR(hr_dev->reg_base);
4070
4071 /* read the node_guid of IB device from the DT or ACPI */
4072 ret = device_property_read_u8_array(dev, "node-guid",
4073 (u8 *)&hr_dev->ib_dev.node_guid,
4074 GUID_LEN);
4075 if (ret) {
4076 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4077 return ret;
4078 }
4079
4080 /* get the RoCE associated ethernet ports or netdevices */
4081 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4082 if (dev_of_node(dev)) {
4083 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4084 i);
4085 if (!net_node)
4086 continue;
4087 pdev = of_find_device_by_node(net_node);
4088 } else if (is_acpi_device_node(dev->fwnode)) {
4089 struct acpi_reference_args args;
4090 struct fwnode_handle *fwnode;
4091
4092 ret = acpi_node_get_property_reference(dev->fwnode,
4093 "eth-handle",
4094 i, &args);
4095 if (ret)
4096 continue;
4097 fwnode = acpi_fwnode_handle(args.adev);
4098 pdev = hns_roce_find_pdev(fwnode);
4099 } else {
4100 dev_err(dev, "cannot read data from DT or ACPI\n");
4101 return -ENXIO;
4102 }
4103
4104 if (pdev) {
4105 netdev = platform_get_drvdata(pdev);
4106 phy_port = (u8)i;
4107 if (netdev) {
4108 hr_dev->iboe.netdevs[port_cnt] = netdev;
4109 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4110 } else {
4111 dev_err(dev, "no netdev found with pdev %s\n",
4112 pdev->name);
4113 return -ENODEV;
4114 }
4115 port_cnt++;
4116 }
4117 }
4118
4119 if (port_cnt == 0) {
4120 dev_err(dev, "unable to get eth-handle for available ports!\n");
4121 return -EINVAL;
4122 }
4123
4124 hr_dev->caps.num_ports = port_cnt;
4125
4126 /* cmd issue mode: 0 is poll, 1 is event */
4127 hr_dev->cmd_mod = 1;
4128 hr_dev->loop_idc = 0;
4129 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4130 hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4131
4132 /* read the interrupt names from the DT or ACPI */
4133 ret = device_property_read_string_array(dev, "interrupt-names",
4134 hr_dev->irq_names,
4135 HNS_ROCE_MAX_IRQ_NUM);
4136 if (ret < 0) {
4137 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4138 return ret;
4139 }
4140
4141 /* fetch the interrupt numbers */
4142 for (i = 0; i < HNS_ROCE_MAX_IRQ_NUM; i++) {
4143 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4144 if (hr_dev->irq[i] <= 0) {
4145 dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4146 return -EINVAL;
4147 }
4148 }
4149
4150 return 0;
4151}
4152
4153/**
4154 * hns_roce_probe - RoCE driver entrance
4155 * @pdev: pointer to platform device
4156 * Return : int
4157 *
4158 */
4159static int hns_roce_probe(struct platform_device *pdev)
4160{
4161 int ret;
4162 struct hns_roce_dev *hr_dev;
4163 struct device *dev = &pdev->dev;
4164
4165 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
4166 if (!hr_dev)
4167 return -ENOMEM;
4168
4169 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4170 if (!hr_dev->priv) {
4171 ret = -ENOMEM;
4172 goto error_failed_kzalloc;
4173 }
4174
4175 hr_dev->pdev = pdev;
4176 hr_dev->dev = dev;
4177 platform_set_drvdata(pdev, hr_dev);
4178
4179 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4180 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4181 dev_err(dev, "Not usable DMA addressing mode\n");
4182 ret = -EIO;
4183 goto error_failed_get_cfg;
4184 }
4185
4186 ret = hns_roce_get_cfg(hr_dev);
4187 if (ret) {
4188 dev_err(dev, "Get Configuration failed!\n");
4189 goto error_failed_get_cfg;
4190 }
4191
4192 ret = hns_roce_init(hr_dev);
4193 if (ret) {
4194 dev_err(dev, "RoCE engine init failed!\n");
4195 goto error_failed_get_cfg;
4196 }
4197
4198 return 0;
4199
4200error_failed_get_cfg:
4201 kfree(hr_dev->priv);
4202
4203error_failed_kzalloc:
4204 ib_dealloc_device(&hr_dev->ib_dev);
4205
4206 return ret;
4207}
4208
4209/**
4210 * hns_roce_remove - remove RoCE device
4211 * @pdev: pointer to platform device
4212 */
4213static int hns_roce_remove(struct platform_device *pdev)
4214{
4215 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4216
4217 hns_roce_exit(hr_dev);
4218 kfree(hr_dev->priv);
4219 ib_dealloc_device(&hr_dev->ib_dev);
4220
4221 return 0;
4222}
4223
4224static struct platform_driver hns_roce_driver = {
4225 .probe = hns_roce_probe,
4226 .remove = hns_roce_remove,
4227 .driver = {
4228 .name = DRV_NAME,
4229 .of_match_table = hns_roce_of_match,
4230 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4231 },
4232};
4233
4234module_platform_driver(hns_roce_driver);
4235
4236MODULE_LICENSE("Dual BSD/GPL");
4237MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4238MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4239MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4240MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.h b/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
index b213b5e6fef1..21a07ef0afc9 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
@@ -72,6 +72,8 @@
72#define HNS_ROCE_V1_CQE_ENTRY_SIZE 32 72#define HNS_ROCE_V1_CQE_ENTRY_SIZE 32
73#define HNS_ROCE_V1_PAGE_SIZE_SUPPORT 0xFFFFF000 73#define HNS_ROCE_V1_PAGE_SIZE_SUPPORT 0xFFFFF000
74 74
75#define HNS_ROCE_V1_TABLE_CHUNK_SIZE (1 << 17)
76
75#define HNS_ROCE_V1_EXT_RAQ_WF 8 77#define HNS_ROCE_V1_EXT_RAQ_WF 8
76#define HNS_ROCE_V1_RAQ_ENTRY 64 78#define HNS_ROCE_V1_RAQ_ENTRY 64
77#define HNS_ROCE_V1_RAQ_DEPTH 32768 79#define HNS_ROCE_V1_RAQ_DEPTH 32768
@@ -948,6 +950,11 @@ struct hns_roce_qp_context {
948#define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M \ 950#define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M \
949 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S) 951 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S)
950 952
953#define STATUS_MASK 0xff
954#define GO_BIT_TIMEOUT_MSECS 10000
955#define HCR_STATUS_OFFSET 0x18
956#define HCR_GO_BIT 15
957
951struct hns_roce_rq_db { 958struct hns_roce_rq_db {
952 u32 u32_4; 959 u32 u32_4;
953 u32 u32_8; 960 u32 u32_8;
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
new file mode 100644
index 000000000000..8f719c00467b
--- /dev/null
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -0,0 +1,3296 @@
1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
37#include <rdma/ib_umem.h>
38
39#include "hnae3.h"
40#include "hns_roce_common.h"
41#include "hns_roce_device.h"
42#include "hns_roce_cmd.h"
43#include "hns_roce_hem.h"
44#include "hns_roce_hw_v2.h"
45
46static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
47 struct ib_sge *sg)
48{
49 dseg->lkey = cpu_to_le32(sg->lkey);
50 dseg->addr = cpu_to_le64(sg->addr);
51 dseg->len = cpu_to_le32(sg->length);
52}
53
54static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
55 struct ib_send_wr **bad_wr)
56{
57 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
58 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
59 struct hns_roce_qp *qp = to_hr_qp(ibqp);
60 struct hns_roce_v2_wqe_data_seg *dseg;
61 struct device *dev = hr_dev->dev;
62 struct hns_roce_v2_db sq_db;
63 unsigned int sge_ind = 0;
64 unsigned int wqe_sz = 0;
65 unsigned int owner_bit;
66 unsigned long flags;
67 unsigned int ind;
68 void *wqe = NULL;
69 int ret = 0;
70 int nreq;
71 int i;
72
73 if (unlikely(ibqp->qp_type != IB_QPT_RC)) {
74 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
75 *bad_wr = NULL;
76 return -EOPNOTSUPP;
77 }
78
79 if (unlikely(qp->state != IB_QPS_RTS && qp->state != IB_QPS_SQD)) {
80 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
81 *bad_wr = wr;
82 return -EINVAL;
83 }
84
85 spin_lock_irqsave(&qp->sq.lock, flags);
86 ind = qp->sq_next_wqe;
87 sge_ind = qp->next_sge;
88
89 for (nreq = 0; wr; ++nreq, wr = wr->next) {
90 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
91 ret = -ENOMEM;
92 *bad_wr = wr;
93 goto out;
94 }
95
96 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
97 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
98 wr->num_sge, qp->sq.max_gs);
99 ret = -EINVAL;
100 *bad_wr = wr;
101 goto out;
102 }
103
104 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
105 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
106 wr->wr_id;
107
108 owner_bit = ~(qp->sq.head >> ilog2(qp->sq.wqe_cnt)) & 0x1;
109 rc_sq_wqe = wqe;
110 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
111 for (i = 0; i < wr->num_sge; i++)
112 rc_sq_wqe->msg_len += wr->sg_list[i].length;
113
114 rc_sq_wqe->inv_key_immtdata = send_ieth(wr);
115
116 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
117 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
118
119 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
120 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
121
122 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
123 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
124
125 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
126 owner_bit);
127
128 switch (wr->opcode) {
129 case IB_WR_RDMA_READ:
130 roce_set_field(rc_sq_wqe->byte_4,
131 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
132 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
133 HNS_ROCE_V2_WQE_OP_RDMA_READ);
134 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
135 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
136 break;
137 case IB_WR_RDMA_WRITE:
138 roce_set_field(rc_sq_wqe->byte_4,
139 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
140 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
141 HNS_ROCE_V2_WQE_OP_RDMA_WRITE);
142 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
143 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
144 break;
145 case IB_WR_RDMA_WRITE_WITH_IMM:
146 roce_set_field(rc_sq_wqe->byte_4,
147 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
148 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
149 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM);
150 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
151 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
152 break;
153 case IB_WR_SEND:
154 roce_set_field(rc_sq_wqe->byte_4,
155 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
156 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
157 HNS_ROCE_V2_WQE_OP_SEND);
158 break;
159 case IB_WR_SEND_WITH_INV:
160 roce_set_field(rc_sq_wqe->byte_4,
161 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
162 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
163 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV);
164 break;
165 case IB_WR_SEND_WITH_IMM:
166 roce_set_field(rc_sq_wqe->byte_4,
167 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
168 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
169 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM);
170 break;
171 case IB_WR_LOCAL_INV:
172 roce_set_field(rc_sq_wqe->byte_4,
173 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
174 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
175 HNS_ROCE_V2_WQE_OP_LOCAL_INV);
176 break;
177 case IB_WR_ATOMIC_CMP_AND_SWP:
178 roce_set_field(rc_sq_wqe->byte_4,
179 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
180 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
181 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP);
182 break;
183 case IB_WR_ATOMIC_FETCH_AND_ADD:
184 roce_set_field(rc_sq_wqe->byte_4,
185 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
186 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
187 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD);
188 break;
189 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
190 roce_set_field(rc_sq_wqe->byte_4,
191 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
192 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
193 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP);
194 break;
195 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
196 roce_set_field(rc_sq_wqe->byte_4,
197 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
198 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
199 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD);
200 break;
201 default:
202 roce_set_field(rc_sq_wqe->byte_4,
203 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
204 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
205 HNS_ROCE_V2_WQE_OP_MASK);
206 break;
207 }
208
209 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
210 dseg = wqe;
211 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
212 if (rc_sq_wqe->msg_len >
213 hr_dev->caps.max_sq_inline) {
214 ret = -EINVAL;
215 *bad_wr = wr;
216 dev_err(dev, "inline len(1-%d)=%d, illegal",
217 rc_sq_wqe->msg_len,
218 hr_dev->caps.max_sq_inline);
219 goto out;
220 }
221
222 for (i = 0; i < wr->num_sge; i++) {
223 memcpy(wqe, ((void *)wr->sg_list[i].addr),
224 wr->sg_list[i].length);
225 wqe += wr->sg_list[i].length;
226 wqe_sz += wr->sg_list[i].length;
227 }
228
229 roce_set_bit(rc_sq_wqe->byte_4,
230 V2_RC_SEND_WQE_BYTE_4_INLINE_S, 1);
231 } else {
232 if (wr->num_sge <= 2) {
233 for (i = 0; i < wr->num_sge; i++)
234 set_data_seg_v2(dseg + i,
235 wr->sg_list + i);
236 } else {
237 roce_set_field(rc_sq_wqe->byte_20,
238 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
239 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
240 sge_ind & (qp->sge.sge_cnt - 1));
241
242 for (i = 0; i < 2; i++)
243 set_data_seg_v2(dseg + i,
244 wr->sg_list + i);
245
246 dseg = get_send_extend_sge(qp,
247 sge_ind & (qp->sge.sge_cnt - 1));
248
249 for (i = 0; i < wr->num_sge - 2; i++) {
250 set_data_seg_v2(dseg + i,
251 wr->sg_list + 2 + i);
252 sge_ind++;
253 }
254 }
255
256 roce_set_field(rc_sq_wqe->byte_16,
257 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
258 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
259 wr->num_sge);
260 wqe_sz += wr->num_sge *
261 sizeof(struct hns_roce_v2_wqe_data_seg);
262 }
263 ind++;
264 }
265
266out:
267 if (likely(nreq)) {
268 qp->sq.head += nreq;
269 /* Memory barrier */
270 wmb();
271
272 sq_db.byte_4 = 0;
273 sq_db.parameter = 0;
274
275 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
276 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
277 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
278 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
279 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_CONS_IDX_M,
280 V2_DB_PARAMETER_CONS_IDX_S,
281 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
282 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
283 V2_DB_PARAMETER_SL_S, qp->sl);
284
285 hns_roce_write64_k((__be32 *)&sq_db, qp->sq.db_reg_l);
286
287 qp->sq_next_wqe = ind;
288 qp->next_sge = sge_ind;
289 }
290
291 spin_unlock_irqrestore(&qp->sq.lock, flags);
292
293 return ret;
294}
295
296static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
297 struct ib_recv_wr **bad_wr)
298{
299 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
300 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
301 struct hns_roce_v2_wqe_data_seg *dseg;
302 struct device *dev = hr_dev->dev;
303 struct hns_roce_v2_db rq_db;
304 unsigned long flags;
305 void *wqe = NULL;
306 int ret = 0;
307 int nreq;
308 int ind;
309 int i;
310
311 spin_lock_irqsave(&hr_qp->rq.lock, flags);
312 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
313
314 if (hr_qp->state == IB_QPS_RESET || hr_qp->state == IB_QPS_ERR) {
315 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
316 *bad_wr = wr;
317 return -EINVAL;
318 }
319
320 for (nreq = 0; wr; ++nreq, wr = wr->next) {
321 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
322 hr_qp->ibqp.recv_cq)) {
323 ret = -ENOMEM;
324 *bad_wr = wr;
325 goto out;
326 }
327
328 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
329 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
330 wr->num_sge, hr_qp->rq.max_gs);
331 ret = -EINVAL;
332 *bad_wr = wr;
333 goto out;
334 }
335
336 wqe = get_recv_wqe(hr_qp, ind);
337 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
338 for (i = 0; i < wr->num_sge; i++) {
339 if (!wr->sg_list[i].length)
340 continue;
341 set_data_seg_v2(dseg, wr->sg_list + i);
342 dseg++;
343 }
344
345 if (i < hr_qp->rq.max_gs) {
346 dseg[i].lkey = cpu_to_be32(HNS_ROCE_INVALID_LKEY);
347 dseg[i].addr = 0;
348 }
349
350 hr_qp->rq.wrid[ind] = wr->wr_id;
351
352 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
353 }
354
355out:
356 if (likely(nreq)) {
357 hr_qp->rq.head += nreq;
358 /* Memory barrier */
359 wmb();
360
361 rq_db.byte_4 = 0;
362 rq_db.parameter = 0;
363
364 roce_set_field(rq_db.byte_4, V2_DB_BYTE_4_TAG_M,
365 V2_DB_BYTE_4_TAG_S, hr_qp->qpn);
366 roce_set_field(rq_db.byte_4, V2_DB_BYTE_4_CMD_M,
367 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_RQ_DB);
368 roce_set_field(rq_db.parameter, V2_DB_PARAMETER_CONS_IDX_M,
369 V2_DB_PARAMETER_CONS_IDX_S, hr_qp->rq.head);
370
371 hns_roce_write64_k((__be32 *)&rq_db, hr_qp->rq.db_reg_l);
372 }
373 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
374
375 return ret;
376}
377
378static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
379{
380 int ntu = ring->next_to_use;
381 int ntc = ring->next_to_clean;
382 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
383
384 return ring->desc_num - used - 1;
385}
386
387static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
388 struct hns_roce_v2_cmq_ring *ring)
389{
390 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
391
392 ring->desc = kzalloc(size, GFP_KERNEL);
393 if (!ring->desc)
394 return -ENOMEM;
395
396 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
397 DMA_BIDIRECTIONAL);
398 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
399 ring->desc_dma_addr = 0;
400 kfree(ring->desc);
401 ring->desc = NULL;
402 return -ENOMEM;
403 }
404
405 return 0;
406}
407
408static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
409 struct hns_roce_v2_cmq_ring *ring)
410{
411 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
412 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
413 DMA_BIDIRECTIONAL);
414 kfree(ring->desc);
415}
416
417static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
418{
419 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
420 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
421 &priv->cmq.csq : &priv->cmq.crq;
422
423 ring->flag = ring_type;
424 ring->next_to_clean = 0;
425 ring->next_to_use = 0;
426
427 return hns_roce_alloc_cmq_desc(hr_dev, ring);
428}
429
430static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
431{
432 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
433 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
434 &priv->cmq.csq : &priv->cmq.crq;
435 dma_addr_t dma = ring->desc_dma_addr;
436
437 if (ring_type == TYPE_CSQ) {
438 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
439 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
440 upper_32_bits(dma));
441 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
442 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
443 HNS_ROCE_CMQ_ENABLE);
444 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
445 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
446 } else {
447 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
448 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
449 upper_32_bits(dma));
450 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
451 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
452 HNS_ROCE_CMQ_ENABLE);
453 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
454 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
455 }
456}
457
458static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
459{
460 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
461 int ret;
462
463 /* Setup the queue entries for command queue */
464 priv->cmq.csq.desc_num = 1024;
465 priv->cmq.crq.desc_num = 1024;
466
467 /* Setup the lock for command queue */
468 spin_lock_init(&priv->cmq.csq.lock);
469 spin_lock_init(&priv->cmq.crq.lock);
470
471 /* Setup Tx write back timeout */
472 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
473
474 /* Init CSQ */
475 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
476 if (ret) {
477 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
478 return ret;
479 }
480
481 /* Init CRQ */
482 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
483 if (ret) {
484 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
485 goto err_crq;
486 }
487
488 /* Init CSQ REG */
489 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
490
491 /* Init CRQ REG */
492 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
493
494 return 0;
495
496err_crq:
497 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
498
499 return ret;
500}
501
502static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
503{
504 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
505
506 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
507 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
508}
509
510static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
511 enum hns_roce_opcode_type opcode,
512 bool is_read)
513{
514 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
515 desc->opcode = cpu_to_le16(opcode);
516 desc->flag =
517 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
518 if (is_read)
519 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
520 else
521 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
522}
523
524static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
525{
526 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
527 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
528
529 return head == priv->cmq.csq.next_to_use;
530}
531
532static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
533{
534 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
535 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
536 struct hns_roce_cmq_desc *desc;
537 u16 ntc = csq->next_to_clean;
538 u32 head;
539 int clean = 0;
540
541 desc = &csq->desc[ntc];
542 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
543 while (head != ntc) {
544 memset(desc, 0, sizeof(*desc));
545 ntc++;
546 if (ntc == csq->desc_num)
547 ntc = 0;
548 desc = &csq->desc[ntc];
549 clean++;
550 }
551 csq->next_to_clean = ntc;
552
553 return clean;
554}
555
556static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
557 struct hns_roce_cmq_desc *desc, int num)
558{
559 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
560 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
561 struct hns_roce_cmq_desc *desc_to_use;
562 bool complete = false;
563 u32 timeout = 0;
564 int handle = 0;
565 u16 desc_ret;
566 int ret = 0;
567 int ntc;
568
569 spin_lock_bh(&csq->lock);
570
571 if (num > hns_roce_cmq_space(csq)) {
572 spin_unlock_bh(&csq->lock);
573 return -EBUSY;
574 }
575
576 /*
577 * Record the location of desc in the cmq for this time
578 * which will be use for hardware to write back
579 */
580 ntc = csq->next_to_use;
581
582 while (handle < num) {
583 desc_to_use = &csq->desc[csq->next_to_use];
584 *desc_to_use = desc[handle];
585 dev_dbg(hr_dev->dev, "set cmq desc:\n");
586 csq->next_to_use++;
587 if (csq->next_to_use == csq->desc_num)
588 csq->next_to_use = 0;
589 handle++;
590 }
591
592 /* Write to hardware */
593 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
594
595 /*
596 * If the command is sync, wait for the firmware to write back,
597 * if multi descriptors to be sent, use the first one to check
598 */
599 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
600 do {
601 if (hns_roce_cmq_csq_done(hr_dev))
602 break;
603 udelay(1);
604 timeout++;
605 } while (timeout < priv->cmq.tx_timeout);
606 }
607
608 if (hns_roce_cmq_csq_done(hr_dev)) {
609 complete = true;
610 handle = 0;
611 while (handle < num) {
612 /* get the result of hardware write back */
613 desc_to_use = &csq->desc[ntc];
614 desc[handle] = *desc_to_use;
615 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
616 desc_ret = desc[handle].retval;
617 if (desc_ret == CMD_EXEC_SUCCESS)
618 ret = 0;
619 else
620 ret = -EIO;
621 priv->cmq.last_status = desc_ret;
622 ntc++;
623 handle++;
624 if (ntc == csq->desc_num)
625 ntc = 0;
626 }
627 }
628
629 if (!complete)
630 ret = -EAGAIN;
631
632 /* clean the command send queue */
633 handle = hns_roce_cmq_csq_clean(hr_dev);
634 if (handle != num)
635 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
636 handle, num);
637
638 spin_unlock_bh(&csq->lock);
639
640 return ret;
641}
642
643static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
644{
645 struct hns_roce_query_version *resp;
646 struct hns_roce_cmq_desc desc;
647 int ret;
648
649 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
650 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
651 if (ret)
652 return ret;
653
654 resp = (struct hns_roce_query_version *)desc.data;
655 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
656 hr_dev->vendor_id = le32_to_cpu(resp->rocee_vendor_id);
657
658 return 0;
659}
660
661static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
662{
663 struct hns_roce_cfg_global_param *req;
664 struct hns_roce_cmq_desc desc;
665
666 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
667 false);
668
669 req = (struct hns_roce_cfg_global_param *)desc.data;
670 memset(req, 0, sizeof(*req));
671 roce_set_field(req->time_cfg_udp_port,
672 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
673 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
674 roce_set_field(req->time_cfg_udp_port,
675 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
676 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
677
678 return hns_roce_cmq_send(hr_dev, &desc, 1);
679}
680
681static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
682{
683 struct hns_roce_cmq_desc desc[2];
684 struct hns_roce_pf_res *res;
685 int ret;
686 int i;
687
688 for (i = 0; i < 2; i++) {
689 hns_roce_cmq_setup_basic_desc(&desc[i],
690 HNS_ROCE_OPC_QUERY_PF_RES, true);
691
692 if (i == 0)
693 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
694 else
695 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
696 }
697
698 ret = hns_roce_cmq_send(hr_dev, desc, 2);
699 if (ret)
700 return ret;
701
702 res = (struct hns_roce_pf_res *)desc[0].data;
703
704 hr_dev->caps.qpc_bt_num = roce_get_field(res->qpc_bt_idx_num,
705 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
706 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
707 hr_dev->caps.srqc_bt_num = roce_get_field(res->srqc_bt_idx_num,
708 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
709 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
710 hr_dev->caps.cqc_bt_num = roce_get_field(res->cqc_bt_idx_num,
711 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
712 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
713 hr_dev->caps.mpt_bt_num = roce_get_field(res->mpt_bt_idx_num,
714 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
715 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
716
717 return 0;
718}
719
720static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
721{
722 struct hns_roce_cmq_desc desc[2];
723 struct hns_roce_vf_res_a *req_a;
724 struct hns_roce_vf_res_b *req_b;
725 int i;
726
727 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
728 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
729 memset(req_a, 0, sizeof(*req_a));
730 memset(req_b, 0, sizeof(*req_b));
731 for (i = 0; i < 2; i++) {
732 hns_roce_cmq_setup_basic_desc(&desc[i],
733 HNS_ROCE_OPC_ALLOC_VF_RES, false);
734
735 if (i == 0)
736 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
737 else
738 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
739
740 if (i == 0) {
741 roce_set_field(req_a->vf_qpc_bt_idx_num,
742 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
743 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
744 roce_set_field(req_a->vf_qpc_bt_idx_num,
745 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
746 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
747 HNS_ROCE_VF_QPC_BT_NUM);
748
749 roce_set_field(req_a->vf_srqc_bt_idx_num,
750 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
751 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
752 roce_set_field(req_a->vf_srqc_bt_idx_num,
753 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
754 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
755 HNS_ROCE_VF_SRQC_BT_NUM);
756
757 roce_set_field(req_a->vf_cqc_bt_idx_num,
758 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
759 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
760 roce_set_field(req_a->vf_cqc_bt_idx_num,
761 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
762 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
763 HNS_ROCE_VF_CQC_BT_NUM);
764
765 roce_set_field(req_a->vf_mpt_bt_idx_num,
766 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
767 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
768 roce_set_field(req_a->vf_mpt_bt_idx_num,
769 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
770 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
771 HNS_ROCE_VF_MPT_BT_NUM);
772
773 roce_set_field(req_a->vf_eqc_bt_idx_num,
774 VF_RES_A_DATA_5_VF_EQC_IDX_M,
775 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
776 roce_set_field(req_a->vf_eqc_bt_idx_num,
777 VF_RES_A_DATA_5_VF_EQC_NUM_M,
778 VF_RES_A_DATA_5_VF_EQC_NUM_S,
779 HNS_ROCE_VF_EQC_NUM);
780 } else {
781 roce_set_field(req_b->vf_smac_idx_num,
782 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
783 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
784 roce_set_field(req_b->vf_smac_idx_num,
785 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
786 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
787 HNS_ROCE_VF_SMAC_NUM);
788
789 roce_set_field(req_b->vf_sgid_idx_num,
790 VF_RES_B_DATA_2_VF_SGID_IDX_M,
791 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
792 roce_set_field(req_b->vf_sgid_idx_num,
793 VF_RES_B_DATA_2_VF_SGID_NUM_M,
794 VF_RES_B_DATA_2_VF_SGID_NUM_S,
795 HNS_ROCE_VF_SGID_NUM);
796
797 roce_set_field(req_b->vf_qid_idx_sl_num,
798 VF_RES_B_DATA_3_VF_QID_IDX_M,
799 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
800 roce_set_field(req_b->vf_qid_idx_sl_num,
801 VF_RES_B_DATA_3_VF_SL_NUM_M,
802 VF_RES_B_DATA_3_VF_SL_NUM_S,
803 HNS_ROCE_VF_SL_NUM);
804 }
805 }
806
807 return hns_roce_cmq_send(hr_dev, desc, 2);
808}
809
810static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
811{
812 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
813 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
814 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
815 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
816 struct hns_roce_cfg_bt_attr *req;
817 struct hns_roce_cmq_desc desc;
818
819 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
820 req = (struct hns_roce_cfg_bt_attr *)desc.data;
821 memset(req, 0, sizeof(*req));
822
823 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
824 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
825 hr_dev->caps.qpc_ba_pg_sz);
826 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
827 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
828 hr_dev->caps.qpc_buf_pg_sz);
829 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
830 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
831 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
832
833 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
834 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
835 hr_dev->caps.srqc_ba_pg_sz);
836 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
837 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
838 hr_dev->caps.srqc_buf_pg_sz);
839 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
840 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
841 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
842
843 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
844 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
845 hr_dev->caps.cqc_ba_pg_sz);
846 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
847 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
848 hr_dev->caps.cqc_buf_pg_sz);
849 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
850 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
851 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
852
853 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
854 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
855 hr_dev->caps.mpt_ba_pg_sz);
856 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
857 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
858 hr_dev->caps.mpt_buf_pg_sz);
859 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
860 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
861 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
862
863 return hns_roce_cmq_send(hr_dev, &desc, 1);
864}
865
866static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
867{
868 struct hns_roce_caps *caps = &hr_dev->caps;
869 int ret;
870
871 ret = hns_roce_cmq_query_hw_info(hr_dev);
872 if (ret) {
873 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
874 ret);
875 return ret;
876 }
877
878 ret = hns_roce_config_global_param(hr_dev);
879 if (ret) {
880 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
881 ret);
882 }
883
884 /* Get pf resource owned by every pf */
885 ret = hns_roce_query_pf_resource(hr_dev);
886 if (ret) {
887 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
888 ret);
889 return ret;
890 }
891
892 ret = hns_roce_alloc_vf_resource(hr_dev);
893 if (ret) {
894 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
895 ret);
896 return ret;
897 }
898
899 hr_dev->vendor_part_id = 0;
900 hr_dev->sys_image_guid = 0;
901
902 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
903 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
904 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
905 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
906 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
907 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
908 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
909 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
910 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
911 caps->num_aeq_vectors = 1;
912 caps->num_comp_vectors = 63;
913 caps->num_other_vectors = 0;
914 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
915 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
916 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
917 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
918 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
919 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
920 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
921 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
922 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
923 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
924 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
925 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
926 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
927 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
928 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
929 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
930 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
931 caps->reserved_lkey = 0;
932 caps->reserved_pds = 0;
933 caps->reserved_mrws = 1;
934 caps->reserved_uars = 0;
935 caps->reserved_cqs = 0;
936
937 caps->qpc_ba_pg_sz = 0;
938 caps->qpc_buf_pg_sz = 0;
939 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
940 caps->srqc_ba_pg_sz = 0;
941 caps->srqc_buf_pg_sz = 0;
942 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
943 caps->cqc_ba_pg_sz = 0;
944 caps->cqc_buf_pg_sz = 0;
945 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
946 caps->mpt_ba_pg_sz = 0;
947 caps->mpt_buf_pg_sz = 0;
948 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
949 caps->pbl_ba_pg_sz = 0;
950 caps->pbl_buf_pg_sz = 0;
951 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
952 caps->mtt_ba_pg_sz = 0;
953 caps->mtt_buf_pg_sz = 0;
954 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
955 caps->cqe_ba_pg_sz = 0;
956 caps->cqe_buf_pg_sz = 0;
957 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
958 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
959
960 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
961 HNS_ROCE_CAP_FLAG_ROCE_V1_V2;
962 caps->pkey_table_len[0] = 1;
963 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
964 caps->local_ca_ack_delay = 0;
965 caps->max_mtu = IB_MTU_4096;
966
967 ret = hns_roce_v2_set_bt(hr_dev);
968 if (ret)
969 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
970 ret);
971
972 return ret;
973}
974
975static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
976{
977 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
978
979 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
980}
981
982static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
983{
984 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
985
986 return status & HNS_ROCE_HW_MB_STATUS_MASK;
987}
988
989static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
990 u64 out_param, u32 in_modifier, u8 op_modifier,
991 u16 op, u16 token, int event)
992{
993 struct device *dev = hr_dev->dev;
994 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base +
995 ROCEE_VF_MB_CFG0_REG);
996 unsigned long end;
997 u32 val0 = 0;
998 u32 val1 = 0;
999
1000 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1001 while (hns_roce_v2_cmd_pending(hr_dev)) {
1002 if (time_after(jiffies, end)) {
1003 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1004 (int)end);
1005 return -EAGAIN;
1006 }
1007 cond_resched();
1008 }
1009
1010 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK,
1011 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier);
1012 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK,
1013 HNS_ROCE_VF_MB4_CMD_SHIFT, op);
1014 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK,
1015 HNS_ROCE_VF_MB5_EVENT_SHIFT, event);
1016 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK,
1017 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token);
1018
1019 __raw_writeq(cpu_to_le64(in_param), hcr + 0);
1020 __raw_writeq(cpu_to_le64(out_param), hcr + 2);
1021
1022 /* Memory barrier */
1023 wmb();
1024
1025 __raw_writel(cpu_to_le32(val0), hcr + 4);
1026 __raw_writel(cpu_to_le32(val1), hcr + 5);
1027
1028 mmiowb();
1029
1030 return 0;
1031}
1032
1033static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1034 unsigned long timeout)
1035{
1036 struct device *dev = hr_dev->dev;
1037 unsigned long end = 0;
1038 u32 status;
1039
1040 end = msecs_to_jiffies(timeout) + jiffies;
1041 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1042 cond_resched();
1043
1044 if (hns_roce_v2_cmd_pending(hr_dev)) {
1045 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1046 return -ETIMEDOUT;
1047 }
1048
1049 status = hns_roce_v2_cmd_complete(hr_dev);
1050 if (status != 0x1) {
1051 dev_err(dev, "mailbox status 0x%x!\n", status);
1052 return -EBUSY;
1053 }
1054
1055 return 0;
1056}
1057
1058static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1059 int gid_index, union ib_gid *gid,
1060 const struct ib_gid_attr *attr)
1061{
1062 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
1063 u32 *p;
1064 u32 val;
1065
1066 if (!gid || !attr)
1067 return -EINVAL;
1068
1069 if (attr->gid_type == IB_GID_TYPE_ROCE)
1070 sgid_type = GID_TYPE_FLAG_ROCE_V1;
1071
1072 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
1073 if (ipv6_addr_v4mapped((void *)gid))
1074 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
1075 else
1076 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
1077 }
1078
1079 p = (u32 *)&gid->raw[0];
1080 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG0_REG +
1081 0x20 * gid_index);
1082
1083 p = (u32 *)&gid->raw[4];
1084 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG1_REG +
1085 0x20 * gid_index);
1086
1087 p = (u32 *)&gid->raw[8];
1088 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG2_REG +
1089 0x20 * gid_index);
1090
1091 p = (u32 *)&gid->raw[0xc];
1092 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG3_REG +
1093 0x20 * gid_index);
1094
1095 val = roce_read(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index);
1096 roce_set_field(val, ROCEE_VF_SGID_CFG4_SGID_TYPE_M,
1097 ROCEE_VF_SGID_CFG4_SGID_TYPE_S, sgid_type);
1098
1099 roce_write(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index, val);
1100
1101 return 0;
1102}
1103
1104static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1105 u8 *addr)
1106{
1107 u16 reg_smac_h;
1108 u32 reg_smac_l;
1109 u32 val;
1110
1111 reg_smac_l = *(u32 *)(&addr[0]);
1112 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_VF_SMAC_CFG0_REG +
1113 0x08 * phy_port);
1114 val = roce_read(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port);
1115
1116 reg_smac_h = *(u16 *)(&addr[4]);
1117 roce_set_field(val, ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M,
1118 ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S, reg_smac_h);
1119 roce_write(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port, val);
1120
1121 return 0;
1122}
1123
1124static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1125 unsigned long mtpt_idx)
1126{
1127 struct hns_roce_v2_mpt_entry *mpt_entry;
1128 struct scatterlist *sg;
1129 u64 *pages;
1130 int entry;
1131 int i;
1132
1133 mpt_entry = mb_buf;
1134 memset(mpt_entry, 0, sizeof(*mpt_entry));
1135
1136 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1137 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
1138 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1139 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
1140 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
1141 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1142 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
1143 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, mr->pbl_ba_pg_sz);
1144 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1145 V2_MPT_BYTE_4_PD_S, mr->pd);
1146 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
1147
1148 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
1149 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1150 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 0);
1151 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
1152 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1153 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 0);
1154 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1155 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1156 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1157 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1158 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1159 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1160 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en);
1161
1162 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
1163 mr->type == MR_TYPE_MR ? 0 : 1);
1164 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa);
1165
1166 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
1167 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
1168 mpt_entry->lkey = cpu_to_le32(mr->key);
1169 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
1170 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
1171
1172 if (mr->type == MR_TYPE_DMA)
1173 return 0;
1174
1175 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1176
1177 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1178 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1179 V2_MPT_BYTE_48_PBL_BA_H_S,
1180 upper_32_bits(mr->pbl_ba >> 3));
1181 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba);
1182
1183 pages = (u64 *)__get_free_page(GFP_KERNEL);
1184 if (!pages)
1185 return -ENOMEM;
1186
1187 i = 0;
1188 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1189 pages[i] = ((u64)sg_dma_address(sg)) >> 6;
1190
1191 /* Record the first 2 entry directly to MTPT table */
1192 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
1193 break;
1194 i++;
1195 }
1196
1197 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
1198 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
1199 V2_MPT_BYTE_56_PA0_H_S,
1200 upper_32_bits(pages[0]));
1201 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h);
1202
1203 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
1204 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
1205 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
1206
1207 free_page((unsigned long)pages);
1208
1209 roce_set_field(mpt_entry->byte_64_buf_pa1,
1210 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
1211 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, mr->pbl_buf_pg_sz);
1212 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
1213
1214 return 0;
1215}
1216
1217static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
1218 struct hns_roce_mr *mr, int flags,
1219 u32 pdn, int mr_access_flags, u64 iova,
1220 u64 size, void *mb_buf)
1221{
1222 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
1223
1224 if (flags & IB_MR_REREG_PD) {
1225 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1226 V2_MPT_BYTE_4_PD_S, pdn);
1227 mr->pd = pdn;
1228 }
1229
1230 if (flags & IB_MR_REREG_ACCESS) {
1231 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1232 V2_MPT_BYTE_8_BIND_EN_S,
1233 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
1234 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1235 V2_MPT_BYTE_8_ATOMIC_EN_S,
1236 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0));
1237 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1238 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0));
1239 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1240 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1241 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1242 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1243 }
1244
1245 if (flags & IB_MR_REREG_TRANS) {
1246 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
1247 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
1248 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
1249 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
1250
1251 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1252 mpt_entry->pbl_ba_l =
1253 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1254 roce_set_field(mpt_entry->byte_48_mode_ba,
1255 V2_MPT_BYTE_48_PBL_BA_H_M,
1256 V2_MPT_BYTE_48_PBL_BA_H_S,
1257 upper_32_bits(mr->pbl_ba >> 3));
1258 mpt_entry->byte_48_mode_ba =
1259 cpu_to_le32(mpt_entry->byte_48_mode_ba);
1260
1261 mr->iova = iova;
1262 mr->size = size;
1263 }
1264
1265 return 0;
1266}
1267
1268static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1269{
1270 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1271 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
1272}
1273
1274static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1275{
1276 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
1277
1278 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1279 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
1280 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
1281}
1282
1283static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
1284{
1285 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
1286}
1287
1288static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1289{
1290 struct hns_roce_v2_cq_db cq_db;
1291
1292 cq_db.byte_4 = 0;
1293 cq_db.parameter = 0;
1294
1295 roce_set_field(cq_db.byte_4, V2_CQ_DB_BYTE_4_TAG_M,
1296 V2_CQ_DB_BYTE_4_TAG_S, hr_cq->cqn);
1297 roce_set_field(cq_db.byte_4, V2_CQ_DB_BYTE_4_CMD_M,
1298 V2_CQ_DB_BYTE_4_CMD_S, HNS_ROCE_V2_CQ_DB_PTR);
1299
1300 roce_set_field(cq_db.parameter, V2_CQ_DB_PARAMETER_CONS_IDX_M,
1301 V2_CQ_DB_PARAMETER_CONS_IDX_S,
1302 cons_index & ((hr_cq->cq_depth << 1) - 1));
1303 roce_set_field(cq_db.parameter, V2_CQ_DB_PARAMETER_CMD_SN_M,
1304 V2_CQ_DB_PARAMETER_CMD_SN_S, 1);
1305
1306 hns_roce_write64_k((__be32 *)&cq_db, hr_cq->cq_db_l);
1307
1308}
1309
1310static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1311 struct hns_roce_srq *srq)
1312{
1313 struct hns_roce_v2_cqe *cqe, *dest;
1314 u32 prod_index;
1315 int nfreed = 0;
1316 u8 owner_bit;
1317
1318 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
1319 ++prod_index) {
1320 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1321 break;
1322 }
1323
1324 /*
1325 * Now backwards through the CQ, removing CQ entries
1326 * that match our QP by overwriting them with next entries.
1327 */
1328 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1329 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1330 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
1331 V2_CQE_BYTE_16_LCL_QPN_S) &
1332 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
1333 /* In v1 engine, not support SRQ */
1334 ++nfreed;
1335 } else if (nfreed) {
1336 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
1337 hr_cq->ib_cq.cqe);
1338 owner_bit = roce_get_bit(dest->byte_4,
1339 V2_CQE_BYTE_4_OWNER_S);
1340 memcpy(dest, cqe, sizeof(*cqe));
1341 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
1342 owner_bit);
1343 }
1344 }
1345
1346 if (nfreed) {
1347 hr_cq->cons_index += nfreed;
1348 /*
1349 * Make sure update of buffer contents is done before
1350 * updating consumer index.
1351 */
1352 wmb();
1353 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
1354 }
1355}
1356
1357static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1358 struct hns_roce_srq *srq)
1359{
1360 spin_lock_irq(&hr_cq->lock);
1361 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
1362 spin_unlock_irq(&hr_cq->lock);
1363}
1364
1365static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
1366 struct hns_roce_cq *hr_cq, void *mb_buf,
1367 u64 *mtts, dma_addr_t dma_handle, int nent,
1368 u32 vector)
1369{
1370 struct hns_roce_v2_cq_context *cq_context;
1371
1372 cq_context = mb_buf;
1373 memset(cq_context, 0, sizeof(*cq_context));
1374
1375 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
1376 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
1377 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
1378 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
1379 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
1380 V2_CQC_BYTE_4_CEQN_S, vector);
1381 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
1382
1383 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
1384 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
1385
1386 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
1387 cq_context->cqe_cur_blk_addr =
1388 cpu_to_le32(cq_context->cqe_cur_blk_addr);
1389
1390 roce_set_field(cq_context->byte_16_hop_addr,
1391 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
1392 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
1393 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
1394 roce_set_field(cq_context->byte_16_hop_addr,
1395 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
1396 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
1397 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
1398
1399 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
1400 roce_set_field(cq_context->byte_24_pgsz_addr,
1401 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
1402 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
1403 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
1404 roce_set_field(cq_context->byte_24_pgsz_addr,
1405 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
1406 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
1407 hr_dev->caps.cqe_ba_pg_sz);
1408 roce_set_field(cq_context->byte_24_pgsz_addr,
1409 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
1410 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
1411 hr_dev->caps.cqe_buf_pg_sz);
1412
1413 cq_context->cqe_ba = (u32)(dma_handle >> 3);
1414
1415 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
1416 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
1417}
1418
1419static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
1420 enum ib_cq_notify_flags flags)
1421{
1422 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
1423 u32 notification_flag;
1424 u32 doorbell[2];
1425
1426 doorbell[0] = 0;
1427 doorbell[1] = 0;
1428
1429 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
1430 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
1431 /*
1432 * flags = 0; Notification Flag = 1, next
1433 * flags = 1; Notification Flag = 0, solocited
1434 */
1435 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
1436 hr_cq->cqn);
1437 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
1438 HNS_ROCE_V2_CQ_DB_NTR);
1439 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
1440 V2_CQ_DB_PARAMETER_CONS_IDX_S,
1441 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
1442 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
1443 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
1444 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
1445 notification_flag);
1446
1447 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1448
1449 return 0;
1450}
1451
1452static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
1453 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
1454{
1455 struct hns_roce_dev *hr_dev;
1456 struct hns_roce_v2_cqe *cqe;
1457 struct hns_roce_qp *hr_qp;
1458 struct hns_roce_wq *wq;
1459 int is_send;
1460 u16 wqe_ctr;
1461 u32 opcode;
1462 u32 status;
1463 int qpn;
1464
1465 /* Find cqe according to consumer index */
1466 cqe = next_cqe_sw_v2(hr_cq);
1467 if (!cqe)
1468 return -EAGAIN;
1469
1470 ++hr_cq->cons_index;
1471 /* Memory barrier */
1472 rmb();
1473
1474 /* 0->SQ, 1->RQ */
1475 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
1476
1477 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
1478 V2_CQE_BYTE_16_LCL_QPN_S);
1479
1480 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
1481 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
1482 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
1483 if (unlikely(!hr_qp)) {
1484 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
1485 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
1486 return -EINVAL;
1487 }
1488 *cur_qp = hr_qp;
1489 }
1490
1491 wc->qp = &(*cur_qp)->ibqp;
1492 wc->vendor_err = 0;
1493
1494 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
1495 V2_CQE_BYTE_4_STATUS_S);
1496 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
1497 case HNS_ROCE_CQE_V2_SUCCESS:
1498 wc->status = IB_WC_SUCCESS;
1499 break;
1500 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
1501 wc->status = IB_WC_LOC_LEN_ERR;
1502 break;
1503 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
1504 wc->status = IB_WC_LOC_QP_OP_ERR;
1505 break;
1506 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
1507 wc->status = IB_WC_LOC_PROT_ERR;
1508 break;
1509 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
1510 wc->status = IB_WC_WR_FLUSH_ERR;
1511 break;
1512 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
1513 wc->status = IB_WC_MW_BIND_ERR;
1514 break;
1515 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
1516 wc->status = IB_WC_BAD_RESP_ERR;
1517 break;
1518 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
1519 wc->status = IB_WC_LOC_ACCESS_ERR;
1520 break;
1521 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
1522 wc->status = IB_WC_REM_INV_REQ_ERR;
1523 break;
1524 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
1525 wc->status = IB_WC_REM_ACCESS_ERR;
1526 break;
1527 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
1528 wc->status = IB_WC_REM_OP_ERR;
1529 break;
1530 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
1531 wc->status = IB_WC_RETRY_EXC_ERR;
1532 break;
1533 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
1534 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
1535 break;
1536 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
1537 wc->status = IB_WC_REM_ABORT_ERR;
1538 break;
1539 default:
1540 wc->status = IB_WC_GENERAL_ERR;
1541 break;
1542 }
1543
1544 /* CQE status error, directly return */
1545 if (wc->status != IB_WC_SUCCESS)
1546 return 0;
1547
1548 if (is_send) {
1549 wc->wc_flags = 0;
1550 /* SQ corresponding to CQE */
1551 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
1552 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
1553 case HNS_ROCE_SQ_OPCODE_SEND:
1554 wc->opcode = IB_WC_SEND;
1555 break;
1556 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
1557 wc->opcode = IB_WC_SEND;
1558 break;
1559 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
1560 wc->opcode = IB_WC_SEND;
1561 wc->wc_flags |= IB_WC_WITH_IMM;
1562 break;
1563 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
1564 wc->opcode = IB_WC_RDMA_READ;
1565 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
1566 break;
1567 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
1568 wc->opcode = IB_WC_RDMA_WRITE;
1569 break;
1570 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
1571 wc->opcode = IB_WC_RDMA_WRITE;
1572 wc->wc_flags |= IB_WC_WITH_IMM;
1573 break;
1574 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
1575 wc->opcode = IB_WC_LOCAL_INV;
1576 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
1577 break;
1578 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
1579 wc->opcode = IB_WC_COMP_SWAP;
1580 wc->byte_len = 8;
1581 break;
1582 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
1583 wc->opcode = IB_WC_FETCH_ADD;
1584 wc->byte_len = 8;
1585 break;
1586 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
1587 wc->opcode = IB_WC_MASKED_COMP_SWAP;
1588 wc->byte_len = 8;
1589 break;
1590 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
1591 wc->opcode = IB_WC_MASKED_FETCH_ADD;
1592 wc->byte_len = 8;
1593 break;
1594 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
1595 wc->opcode = IB_WC_REG_MR;
1596 break;
1597 case HNS_ROCE_SQ_OPCODE_BIND_MW:
1598 wc->opcode = IB_WC_REG_MR;
1599 break;
1600 default:
1601 wc->status = IB_WC_GENERAL_ERR;
1602 break;
1603 }
1604
1605 wq = &(*cur_qp)->sq;
1606 if ((*cur_qp)->sq_signal_bits) {
1607 /*
1608 * If sg_signal_bit is 1,
1609 * firstly tail pointer updated to wqe
1610 * which current cqe correspond to
1611 */
1612 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
1613 V2_CQE_BYTE_4_WQE_INDX_M,
1614 V2_CQE_BYTE_4_WQE_INDX_S);
1615 wq->tail += (wqe_ctr - (u16)wq->tail) &
1616 (wq->wqe_cnt - 1);
1617 }
1618
1619 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
1620 ++wq->tail;
1621 } else {
1622 /* RQ correspond to CQE */
1623 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
1624
1625 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
1626 V2_CQE_BYTE_4_OPCODE_S);
1627 switch (opcode & 0x1f) {
1628 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
1629 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
1630 wc->wc_flags = IB_WC_WITH_IMM;
1631 wc->ex.imm_data = le32_to_cpu(cqe->rkey_immtdata);
1632 break;
1633 case HNS_ROCE_V2_OPCODE_SEND:
1634 wc->opcode = IB_WC_RECV;
1635 wc->wc_flags = 0;
1636 break;
1637 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
1638 wc->opcode = IB_WC_RECV;
1639 wc->wc_flags = IB_WC_WITH_IMM;
1640 wc->ex.imm_data = le32_to_cpu(cqe->rkey_immtdata);
1641 break;
1642 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
1643 wc->opcode = IB_WC_RECV;
1644 wc->wc_flags = IB_WC_WITH_INVALIDATE;
1645 wc->ex.invalidate_rkey = cqe->rkey_immtdata;
1646 break;
1647 default:
1648 wc->status = IB_WC_GENERAL_ERR;
1649 break;
1650 }
1651
1652 /* Update tail pointer, record wr_id */
1653 wq = &(*cur_qp)->rq;
1654 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
1655 ++wq->tail;
1656
1657 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
1658 V2_CQE_BYTE_32_SL_S);
1659 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
1660 V2_CQE_BYTE_32_RMT_QPN_M,
1661 V2_CQE_BYTE_32_RMT_QPN_S);
1662 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
1663 V2_CQE_BYTE_32_GRH_S) ?
1664 IB_WC_GRH : 0);
1665 }
1666
1667 return 0;
1668}
1669
1670static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
1671 struct ib_wc *wc)
1672{
1673 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
1674 struct hns_roce_qp *cur_qp = NULL;
1675 unsigned long flags;
1676 int npolled;
1677
1678 spin_lock_irqsave(&hr_cq->lock, flags);
1679
1680 for (npolled = 0; npolled < num_entries; ++npolled) {
1681 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
1682 break;
1683 }
1684
1685 if (npolled) {
1686 /* Memory barrier */
1687 wmb();
1688 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
1689 }
1690
1691 spin_unlock_irqrestore(&hr_cq->lock, flags);
1692
1693 return npolled;
1694}
1695
1696static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
1697 struct hns_roce_hem_table *table, int obj,
1698 int step_idx)
1699{
1700 struct device *dev = hr_dev->dev;
1701 struct hns_roce_cmd_mailbox *mailbox;
1702 struct hns_roce_hem_iter iter;
1703 struct hns_roce_hem_mhop mhop;
1704 struct hns_roce_hem *hem;
1705 unsigned long mhop_obj = obj;
1706 int i, j, k;
1707 int ret = 0;
1708 u64 hem_idx = 0;
1709 u64 l1_idx = 0;
1710 u64 bt_ba = 0;
1711 u32 chunk_ba_num;
1712 u32 hop_num;
1713 u16 op = 0xff;
1714
1715 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
1716 return 0;
1717
1718 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
1719 i = mhop.l0_idx;
1720 j = mhop.l1_idx;
1721 k = mhop.l2_idx;
1722 hop_num = mhop.hop_num;
1723 chunk_ba_num = mhop.bt_chunk_size / 8;
1724
1725 if (hop_num == 2) {
1726 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
1727 k;
1728 l1_idx = i * chunk_ba_num + j;
1729 } else if (hop_num == 1) {
1730 hem_idx = i * chunk_ba_num + j;
1731 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
1732 hem_idx = i;
1733 }
1734
1735 switch (table->type) {
1736 case HEM_TYPE_QPC:
1737 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
1738 break;
1739 case HEM_TYPE_MTPT:
1740 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
1741 break;
1742 case HEM_TYPE_CQC:
1743 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
1744 break;
1745 case HEM_TYPE_SRQC:
1746 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
1747 break;
1748 default:
1749 dev_warn(dev, "Table %d not to be written by mailbox!\n",
1750 table->type);
1751 return 0;
1752 }
1753 op += step_idx;
1754
1755 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1756 if (IS_ERR(mailbox))
1757 return PTR_ERR(mailbox);
1758
1759 if (check_whether_last_step(hop_num, step_idx)) {
1760 hem = table->hem[hem_idx];
1761 for (hns_roce_hem_first(hem, &iter);
1762 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
1763 bt_ba = hns_roce_hem_addr(&iter);
1764
1765 /* configure the ba, tag, and op */
1766 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
1767 obj, 0, op,
1768 HNS_ROCE_CMD_TIMEOUT_MSECS);
1769 }
1770 } else {
1771 if (step_idx == 0)
1772 bt_ba = table->bt_l0_dma_addr[i];
1773 else if (step_idx == 1 && hop_num == 2)
1774 bt_ba = table->bt_l1_dma_addr[l1_idx];
1775
1776 /* configure the ba, tag, and op */
1777 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
1778 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
1779 }
1780
1781 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1782 return ret;
1783}
1784
1785static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
1786 struct hns_roce_hem_table *table, int obj,
1787 int step_idx)
1788{
1789 struct device *dev = hr_dev->dev;
1790 struct hns_roce_cmd_mailbox *mailbox;
1791 int ret = 0;
1792 u16 op = 0xff;
1793
1794 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
1795 return 0;
1796
1797 switch (table->type) {
1798 case HEM_TYPE_QPC:
1799 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
1800 break;
1801 case HEM_TYPE_MTPT:
1802 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
1803 break;
1804 case HEM_TYPE_CQC:
1805 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
1806 break;
1807 case HEM_TYPE_SRQC:
1808 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
1809 break;
1810 default:
1811 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
1812 table->type);
1813 return 0;
1814 }
1815 op += step_idx;
1816
1817 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1818 if (IS_ERR(mailbox))
1819 return PTR_ERR(mailbox);
1820
1821 /* configure the tag and op */
1822 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
1823 HNS_ROCE_CMD_TIMEOUT_MSECS);
1824
1825 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1826 return ret;
1827}
1828
1829static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
1830 struct hns_roce_mtt *mtt,
1831 enum ib_qp_state cur_state,
1832 enum ib_qp_state new_state,
1833 struct hns_roce_v2_qp_context *context,
1834 struct hns_roce_qp *hr_qp)
1835{
1836 struct hns_roce_cmd_mailbox *mailbox;
1837 int ret;
1838
1839 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1840 if (IS_ERR(mailbox))
1841 return PTR_ERR(mailbox);
1842
1843 memcpy(mailbox->buf, context, sizeof(*context) * 2);
1844
1845 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
1846 HNS_ROCE_CMD_MODIFY_QPC,
1847 HNS_ROCE_CMD_TIMEOUT_MSECS);
1848
1849 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1850
1851 return ret;
1852}
1853
1854static void modify_qp_reset_to_init(struct ib_qp *ibqp,
1855 const struct ib_qp_attr *attr,
1856 struct hns_roce_v2_qp_context *context,
1857 struct hns_roce_v2_qp_context *qpc_mask)
1858{
1859 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1860
1861 /*
1862 * In v2 engine, software pass context and context mask to hardware
1863 * when modifying qp. If software need modify some fields in context,
1864 * we should set all bits of the relevant fields in context mask to
1865 * 0 at the same time, else set them to 0x1.
1866 */
1867 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
1868 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
1869 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
1870 V2_QPC_BYTE_4_TST_S, 0);
1871
1872 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
1873 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
1874 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
1875 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
1876 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
1877
1878 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
1879 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
1880 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
1881 V2_QPC_BYTE_4_SQPN_S, 0);
1882
1883 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
1884 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
1885 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
1886 V2_QPC_BYTE_16_PD_S, 0);
1887
1888 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
1889 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
1890 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
1891 V2_QPC_BYTE_20_RQWS_S, 0);
1892
1893 roce_set_field(context->byte_20_smac_sgid_idx,
1894 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
1895 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
1896 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
1897 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
1898
1899 roce_set_field(context->byte_20_smac_sgid_idx,
1900 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
1901 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
1902 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
1903 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
1904
1905 /* No VLAN need to set 0xFFF */
1906 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M,
1907 V2_QPC_BYTE_24_VLAN_IDX_S, 0xfff);
1908 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M,
1909 V2_QPC_BYTE_24_VLAN_IDX_S, 0);
1910
1911 /*
1912 * Set some fields in context to zero, Because the default values
1913 * of all fields in context are zero, we need not set them to 0 again.
1914 * but we should set the relevant fields of context mask to 0.
1915 */
1916 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
1917 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
1918 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
1919 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
1920
1921 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M,
1922 V2_QPC_BYTE_60_MAPID_S, 0);
1923
1924 roce_set_bit(qpc_mask->byte_60_qpst_mapid,
1925 V2_QPC_BYTE_60_INNER_MAP_IND_S, 0);
1926 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S,
1927 0);
1928 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S,
1929 0);
1930 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S,
1931 0);
1932 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S,
1933 0);
1934 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S,
1935 0);
1936 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
1937 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
1938
1939 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
1940 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
1941 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
1942
1943 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
1944 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE));
1945 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
1946
1947 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
1948 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC));
1949 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
1950
1951 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
1952
1953 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
1954 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
1955 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
1956 V2_QPC_BYTE_80_RX_CQN_S, 0);
1957 if (ibqp->srq) {
1958 roce_set_field(context->byte_76_srqn_op_en,
1959 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
1960 to_hr_srq(ibqp->srq)->srqn);
1961 roce_set_field(qpc_mask->byte_76_srqn_op_en,
1962 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
1963 roce_set_bit(context->byte_76_srqn_op_en,
1964 V2_QPC_BYTE_76_SRQ_EN_S, 1);
1965 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
1966 V2_QPC_BYTE_76_SRQ_EN_S, 0);
1967 }
1968
1969 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
1970 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
1971 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
1972 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
1973 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
1974 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
1975
1976 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
1977 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
1978
1979 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
1980 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
1981
1982 roce_set_field(qpc_mask->byte_104_rq_sge,
1983 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
1984 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
1985
1986 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
1987 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
1988 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
1989 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
1990 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
1991 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
1992 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
1993
1994 qpc_mask->rq_rnr_timer = 0;
1995 qpc_mask->rx_msg_len = 0;
1996 qpc_mask->rx_rkey_pkt_info = 0;
1997 qpc_mask->rx_va = 0;
1998
1999 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2000 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2001 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2002 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2003
2004 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0);
2005 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
2006 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
2007 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
2008 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
2009
2010 roce_set_field(qpc_mask->byte_144_raq,
2011 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
2012 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
2013 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S,
2014 0);
2015 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
2016 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
2017 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
2018
2019 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
2020 V2_QPC_BYTE_148_RQ_MSN_S, 0);
2021 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
2022 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
2023
2024 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2025 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2026 roce_set_field(qpc_mask->byte_152_raq,
2027 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
2028 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
2029
2030 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
2031 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
2032
2033 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2034 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
2035 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
2036 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2037 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
2038 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
2039
2040 roce_set_field(context->byte_168_irrl_idx,
2041 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2042 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2043 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2044 roce_set_field(qpc_mask->byte_168_irrl_idx,
2045 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2046 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2047
2048 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2049 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
2050 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2051 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
2052 roce_set_field(qpc_mask->byte_168_irrl_idx,
2053 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
2054 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
2055
2056 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2057 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
2058 roce_set_field(qpc_mask->byte_172_sq_psn,
2059 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2060 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
2061
2062 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
2063 0);
2064
2065 roce_set_field(qpc_mask->byte_176_msg_pktn,
2066 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
2067 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
2068 roce_set_field(qpc_mask->byte_176_msg_pktn,
2069 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
2070 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
2071
2072 roce_set_field(qpc_mask->byte_184_irrl_idx,
2073 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
2074 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
2075
2076 qpc_mask->cur_sge_offset = 0;
2077
2078 roce_set_field(qpc_mask->byte_192_ext_sge,
2079 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
2080 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
2081 roce_set_field(qpc_mask->byte_192_ext_sge,
2082 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
2083 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
2084
2085 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2086 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2087
2088 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
2089 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
2090 roce_set_field(qpc_mask->byte_200_sq_max,
2091 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
2092 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
2093
2094 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
2095 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
2096
2097 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2098 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2099
2100 qpc_mask->sq_timer = 0;
2101
2102 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2103 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2104 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2105 roce_set_field(qpc_mask->byte_232_irrl_sge,
2106 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2107 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2108
2109 qpc_mask->irrl_cur_sge_offset = 0;
2110
2111 roce_set_field(qpc_mask->byte_240_irrl_tail,
2112 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2113 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2114 roce_set_field(qpc_mask->byte_240_irrl_tail,
2115 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
2116 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
2117 roce_set_field(qpc_mask->byte_240_irrl_tail,
2118 V2_QPC_BYTE_240_RX_ACK_MSN_M,
2119 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
2120
2121 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
2122 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
2123 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
2124 0);
2125 roce_set_field(qpc_mask->byte_248_ack_psn,
2126 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
2127 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
2128 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
2129 0);
2130 roce_set_bit(qpc_mask->byte_248_ack_psn,
2131 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
2132 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
2133 0);
2134
2135 hr_qp->access_flags = attr->qp_access_flags;
2136 hr_qp->pkey_index = attr->pkey_index;
2137 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2138 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
2139 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2140 V2_QPC_BYTE_252_TX_CQN_S, 0);
2141
2142 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
2143 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
2144
2145 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2146 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
2147 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
2148 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2149 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
2150 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
2151}
2152
2153static void modify_qp_init_to_init(struct ib_qp *ibqp,
2154 const struct ib_qp_attr *attr, int attr_mask,
2155 struct hns_roce_v2_qp_context *context,
2156 struct hns_roce_v2_qp_context *qpc_mask)
2157{
2158 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2159
2160 /*
2161 * In v2 engine, software pass context and context mask to hardware
2162 * when modifying qp. If software need modify some fields in context,
2163 * we should set all bits of the relevant fields in context mask to
2164 * 0 at the same time, else set them to 0x1.
2165 */
2166 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2167 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2168 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2169 V2_QPC_BYTE_4_TST_S, 0);
2170
2171 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2172 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
2173 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2174 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2175 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2176
2177 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2178 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2179 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2180 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2181 0);
2182
2183 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2184 !!(attr->qp_access_flags &
2185 IB_ACCESS_REMOTE_WRITE));
2186 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2187 0);
2188
2189 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2190 !!(attr->qp_access_flags &
2191 IB_ACCESS_REMOTE_ATOMIC));
2192 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2193 0);
2194 } else {
2195 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2196 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
2197 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2198 0);
2199
2200 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2201 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
2202 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2203 0);
2204
2205 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2206 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
2207 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2208 0);
2209 }
2210
2211 roce_set_field(context->byte_20_smac_sgid_idx,
2212 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2213 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2214 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2215 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2216
2217 roce_set_field(context->byte_20_smac_sgid_idx,
2218 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2219 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2220 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2221 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2222
2223 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2224 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2225 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2226 V2_QPC_BYTE_16_PD_S, 0);
2227
2228 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2229 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2230 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2231 V2_QPC_BYTE_80_RX_CQN_S, 0);
2232
2233 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2234 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2235 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2236 V2_QPC_BYTE_252_TX_CQN_S, 0);
2237
2238 if (ibqp->srq) {
2239 roce_set_bit(context->byte_76_srqn_op_en,
2240 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2241 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2242 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2243 roce_set_field(context->byte_76_srqn_op_en,
2244 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2245 to_hr_srq(ibqp->srq)->srqn);
2246 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2247 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2248 }
2249
2250 if (attr_mask & IB_QP_PKEY_INDEX)
2251 context->qkey_xrcd = attr->pkey_index;
2252 else
2253 context->qkey_xrcd = hr_qp->pkey_index;
2254
2255 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2256 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2257 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2258 V2_QPC_BYTE_4_SQPN_S, 0);
2259
2260 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2261 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
2262 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2263 V2_QPC_BYTE_56_DQPN_S, 0);
2264 roce_set_field(context->byte_168_irrl_idx,
2265 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2266 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2267 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2268 roce_set_field(qpc_mask->byte_168_irrl_idx,
2269 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2270 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2271}
2272
2273static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
2274 const struct ib_qp_attr *attr, int attr_mask,
2275 struct hns_roce_v2_qp_context *context,
2276 struct hns_roce_v2_qp_context *qpc_mask)
2277{
2278 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2279 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2280 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2281 struct device *dev = hr_dev->dev;
2282 dma_addr_t dma_handle_3;
2283 dma_addr_t dma_handle_2;
2284 dma_addr_t dma_handle;
2285 u32 page_size;
2286 u8 port_num;
2287 u64 *mtts_3;
2288 u64 *mtts_2;
2289 u64 *mtts;
2290 u8 *dmac;
2291 u8 *smac;
2292 int port;
2293
2294 /* Search qp buf's mtts */
2295 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2296 hr_qp->mtt.first_seg, &dma_handle);
2297 if (!mtts) {
2298 dev_err(dev, "qp buf pa find failed\n");
2299 return -EINVAL;
2300 }
2301
2302 /* Search IRRL's mtts */
2303 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2304 hr_qp->qpn, &dma_handle_2);
2305 if (!mtts_2) {
2306 dev_err(dev, "qp irrl_table find failed\n");
2307 return -EINVAL;
2308 }
2309
2310 /* Search TRRL's mtts */
2311 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
2312 hr_qp->qpn, &dma_handle_3);
2313 if (!mtts_3) {
2314 dev_err(dev, "qp trrl_table find failed\n");
2315 return -EINVAL;
2316 }
2317
2318 if ((attr_mask & IB_QP_ALT_PATH) || (attr_mask & IB_QP_ACCESS_FLAGS) ||
2319 (attr_mask & IB_QP_PKEY_INDEX) || (attr_mask & IB_QP_QKEY)) {
2320 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
2321 return -EINVAL;
2322 }
2323
2324 dmac = (u8 *)attr->ah_attr.roce.dmac;
2325 context->wqe_sge_ba = (u32)(dma_handle >> 3);
2326 qpc_mask->wqe_sge_ba = 0;
2327
2328 /*
2329 * In v2 engine, software pass context and context mask to hardware
2330 * when modifying qp. If software need modify some fields in context,
2331 * we should set all bits of the relevant fields in context mask to
2332 * 0 at the same time, else set them to 0x1.
2333 */
2334 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
2335 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
2336 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
2337 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
2338
2339 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
2340 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
2341 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
2342 0 : hr_dev->caps.mtt_hop_num);
2343 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
2344 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
2345
2346 roce_set_field(context->byte_20_smac_sgid_idx,
2347 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
2348 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
2349 hr_qp->sq.max_gs > 2 ? hr_dev->caps.mtt_hop_num : 0);
2350 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2351 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
2352 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
2353
2354 roce_set_field(context->byte_20_smac_sgid_idx,
2355 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
2356 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
2357 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
2358 0 : hr_dev->caps.mtt_hop_num);
2359 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2360 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
2361 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
2362
2363 roce_set_field(context->byte_16_buf_ba_pg_sz,
2364 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
2365 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
2366 hr_dev->caps.mtt_ba_pg_sz);
2367 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
2368 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
2369 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
2370
2371 roce_set_field(context->byte_16_buf_ba_pg_sz,
2372 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
2373 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
2374 hr_dev->caps.mtt_buf_pg_sz);
2375 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
2376 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
2377 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
2378
2379 roce_set_field(context->byte_80_rnr_rx_cqn,
2380 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
2381 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer);
2382 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
2383 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
2384 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
2385
2386 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
2387 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
2388 >> PAGE_ADDR_SHIFT);
2389 qpc_mask->rq_cur_blk_addr = 0;
2390
2391 roce_set_field(context->byte_92_srq_info,
2392 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
2393 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
2394 mtts[hr_qp->rq.offset / page_size]
2395 >> (32 + PAGE_ADDR_SHIFT));
2396 roce_set_field(qpc_mask->byte_92_srq_info,
2397 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
2398 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
2399
2400 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
2401 >> PAGE_ADDR_SHIFT);
2402 qpc_mask->rq_nxt_blk_addr = 0;
2403
2404 roce_set_field(context->byte_104_rq_sge,
2405 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
2406 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
2407 mtts[hr_qp->rq.offset / page_size + 1]
2408 >> (32 + PAGE_ADDR_SHIFT));
2409 roce_set_field(qpc_mask->byte_104_rq_sge,
2410 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
2411 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
2412
2413 roce_set_field(context->byte_108_rx_reqepsn,
2414 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
2415 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
2416 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2417 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
2418 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
2419
2420 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
2421 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
2422 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
2423 V2_QPC_BYTE_132_TRRL_BA_S, 0);
2424 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
2425 qpc_mask->trrl_ba = 0;
2426 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
2427 V2_QPC_BYTE_140_TRRL_BA_S,
2428 (u32)(dma_handle_3 >> (32 + 16 + 4)));
2429 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
2430 V2_QPC_BYTE_140_TRRL_BA_S, 0);
2431
2432 context->irrl_ba = (u32)(dma_handle_2 >> 6);
2433 qpc_mask->irrl_ba = 0;
2434 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
2435 V2_QPC_BYTE_208_IRRL_BA_S,
2436 dma_handle_2 >> (32 + 6));
2437 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
2438 V2_QPC_BYTE_208_IRRL_BA_S, 0);
2439
2440 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
2441 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
2442
2443 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
2444 hr_qp->sq_signal_bits);
2445 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
2446 0);
2447
2448 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
2449
2450 smac = (u8 *)hr_dev->dev_addr[port];
2451 /* when dmac equals smac or loop_idc is 1, it should loopback */
2452 if (ether_addr_equal_unaligned(dmac, smac) ||
2453 hr_dev->loop_idc == 0x1) {
2454 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
2455 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
2456 }
2457
2458 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
2459 V2_QPC_BYTE_140_RR_MAX_S,
2460 ilog2((unsigned int)attr->max_dest_rd_atomic));
2461 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
2462 V2_QPC_BYTE_140_RR_MAX_S, 0);
2463
2464 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2465 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
2466 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2467 V2_QPC_BYTE_56_DQPN_S, 0);
2468
2469 /* Configure GID index */
2470 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2471 roce_set_field(context->byte_20_smac_sgid_idx,
2472 V2_QPC_BYTE_20_SGID_IDX_M,
2473 V2_QPC_BYTE_20_SGID_IDX_S,
2474 hns_get_gid_index(hr_dev, port_num - 1,
2475 grh->sgid_index));
2476 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2477 V2_QPC_BYTE_20_SGID_IDX_M,
2478 V2_QPC_BYTE_20_SGID_IDX_S, 0);
2479 memcpy(&(context->dmac), dmac, 4);
2480 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
2481 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
2482 qpc_mask->dmac = 0;
2483 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
2484 V2_QPC_BYTE_52_DMAC_S, 0);
2485
2486 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
2487 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
2488 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
2489 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
2490
2491 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
2492 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
2493 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
2494 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
2495
2496 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
2497 V2_QPC_BYTE_28_FL_S, grh->flow_label);
2498 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
2499 V2_QPC_BYTE_28_FL_S, 0);
2500
2501 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
2502 V2_QPC_BYTE_24_TC_S, grh->traffic_class);
2503 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
2504 V2_QPC_BYTE_24_TC_S, 0);
2505
2506 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
2507 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
2508 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
2509 V2_QPC_BYTE_24_MTU_S, 0);
2510
2511 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
2512 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
2513
2514 roce_set_field(context->byte_84_rq_ci_pi,
2515 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2516 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
2517 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2518 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2519 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
2520
2521 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2522 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
2523 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
2524 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2525 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
2526 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
2527 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
2528 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2529 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
2530 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
2531
2532 context->rq_rnr_timer = 0;
2533 qpc_mask->rq_rnr_timer = 0;
2534
2535 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2536 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
2537 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2538 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2539
2540 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2541 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2542 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2543 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2544
2545 roce_set_field(context->byte_168_irrl_idx,
2546 V2_QPC_BYTE_168_LP_SGEN_INI_M,
2547 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
2548 roce_set_field(qpc_mask->byte_168_irrl_idx,
2549 V2_QPC_BYTE_168_LP_SGEN_INI_M,
2550 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
2551
2552 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
2553 V2_QPC_BYTE_208_SR_MAX_S,
2554 ilog2((unsigned int)attr->max_rd_atomic));
2555 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
2556 V2_QPC_BYTE_208_SR_MAX_S, 0);
2557
2558 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
2559 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr));
2560 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
2561 V2_QPC_BYTE_28_SL_S, 0);
2562 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
2563
2564 return 0;
2565}
2566
2567static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
2568 const struct ib_qp_attr *attr, int attr_mask,
2569 struct hns_roce_v2_qp_context *context,
2570 struct hns_roce_v2_qp_context *qpc_mask)
2571{
2572 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2573 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2574 struct device *dev = hr_dev->dev;
2575 dma_addr_t dma_handle;
2576 u32 page_size;
2577 u64 *mtts;
2578
2579 /* Search qp buf's mtts */
2580 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2581 hr_qp->mtt.first_seg, &dma_handle);
2582 if (!mtts) {
2583 dev_err(dev, "qp buf pa find failed\n");
2584 return -EINVAL;
2585 }
2586
2587 /* If exist optional param, return error */
2588 if ((attr_mask & IB_QP_ALT_PATH) || (attr_mask & IB_QP_ACCESS_FLAGS) ||
2589 (attr_mask & IB_QP_QKEY) || (attr_mask & IB_QP_PATH_MIG_STATE) ||
2590 (attr_mask & IB_QP_CUR_STATE) ||
2591 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
2592 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
2593 return -EINVAL;
2594 }
2595
2596 /*
2597 * In v2 engine, software pass context and context mask to hardware
2598 * when modifying qp. If software need modify some fields in context,
2599 * we should set all bits of the relevant fields in context mask to
2600 * 0 at the same time, else set them to 0x1.
2601 */
2602 roce_set_field(context->byte_60_qpst_mapid,
2603 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
2604 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt);
2605 roce_set_field(qpc_mask->byte_60_qpst_mapid,
2606 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
2607 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0);
2608
2609 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2610 roce_set_field(context->byte_168_irrl_idx,
2611 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
2612 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
2613 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
2614 qpc_mask->sq_cur_blk_addr = 0;
2615 roce_set_field(qpc_mask->byte_168_irrl_idx,
2616 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
2617 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
2618
2619 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
2620 context->sq_cur_sge_blk_addr = hr_qp->sq.max_gs > 2 ?
2621 ((u32)(mtts[hr_qp->sge.offset / page_size]
2622 >> PAGE_ADDR_SHIFT)) : 0;
2623 roce_set_field(context->byte_184_irrl_idx,
2624 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
2625 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
2626 hr_qp->sq.max_gs > 2 ?
2627 (mtts[hr_qp->sge.offset / page_size] >>
2628 (32 + PAGE_ADDR_SHIFT)) : 0);
2629 qpc_mask->sq_cur_sge_blk_addr = 0;
2630 roce_set_field(qpc_mask->byte_184_irrl_idx,
2631 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
2632 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
2633
2634 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2635 roce_set_field(context->byte_232_irrl_sge,
2636 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
2637 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
2638 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
2639 qpc_mask->rx_sq_cur_blk_addr = 0;
2640 roce_set_field(qpc_mask->byte_232_irrl_sge,
2641 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
2642 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
2643
2644 /*
2645 * Set some fields in context to zero, Because the default values
2646 * of all fields in context are zero, we need not set them to 0 again.
2647 * but we should set the relevant fields of context mask to 0.
2648 */
2649 roce_set_field(qpc_mask->byte_232_irrl_sge,
2650 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2651 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2652
2653 roce_set_field(qpc_mask->byte_240_irrl_tail,
2654 V2_QPC_BYTE_240_RX_ACK_MSN_M,
2655 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
2656
2657 roce_set_field(context->byte_244_rnr_rxack,
2658 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
2659 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
2660 roce_set_field(qpc_mask->byte_244_rnr_rxack,
2661 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
2662 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
2663
2664 roce_set_field(qpc_mask->byte_248_ack_psn,
2665 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
2666 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
2667 roce_set_bit(qpc_mask->byte_248_ack_psn,
2668 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
2669 roce_set_field(qpc_mask->byte_248_ack_psn,
2670 V2_QPC_BYTE_248_IRRL_PSN_M,
2671 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
2672
2673 roce_set_field(qpc_mask->byte_240_irrl_tail,
2674 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2675 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2676
2677 roce_set_field(context->byte_220_retry_psn_msn,
2678 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
2679 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
2680 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2681 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
2682 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
2683
2684 roce_set_field(context->byte_224_retry_msg,
2685 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
2686 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16);
2687 roce_set_field(qpc_mask->byte_224_retry_msg,
2688 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
2689 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
2690
2691 roce_set_field(context->byte_224_retry_msg,
2692 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
2693 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn);
2694 roce_set_field(qpc_mask->byte_224_retry_msg,
2695 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
2696 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
2697
2698 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2699 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2700 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2701
2702 roce_set_bit(qpc_mask->byte_248_ack_psn,
2703 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
2704
2705 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2706 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2707
2708 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
2709 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
2710 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
2711 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
2712
2713 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
2714 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt);
2715 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
2716 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
2717
2718 roce_set_field(context->byte_244_rnr_rxack,
2719 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
2720 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
2721 roce_set_field(qpc_mask->byte_244_rnr_rxack,
2722 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
2723 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
2724
2725 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
2726 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
2727 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
2728 V2_QPC_BYTE_244_RNR_CNT_S, 0);
2729
2730 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
2731 V2_QPC_BYTE_212_LSN_S, 0x100);
2732 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
2733 V2_QPC_BYTE_212_LSN_S, 0);
2734
2735 if (attr_mask & IB_QP_TIMEOUT) {
2736 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
2737 V2_QPC_BYTE_28_AT_S, attr->timeout);
2738 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
2739 V2_QPC_BYTE_28_AT_S, 0);
2740 }
2741
2742 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
2743 V2_QPC_BYTE_28_SL_S,
2744 rdma_ah_get_sl(&attr->ah_attr));
2745 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
2746 V2_QPC_BYTE_28_SL_S, 0);
2747 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
2748
2749 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
2750 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
2751 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
2752 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
2753
2754 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2755 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2756 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
2757 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
2758 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
2759 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
2760
2761 return 0;
2762}
2763
2764static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
2765 const struct ib_qp_attr *attr,
2766 int attr_mask, enum ib_qp_state cur_state,
2767 enum ib_qp_state new_state)
2768{
2769 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2770 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2771 struct hns_roce_v2_qp_context *context;
2772 struct hns_roce_v2_qp_context *qpc_mask;
2773 struct device *dev = hr_dev->dev;
2774 int ret = -EINVAL;
2775
2776 context = kzalloc(2 * sizeof(*context), GFP_KERNEL);
2777 if (!context)
2778 return -ENOMEM;
2779
2780 qpc_mask = context + 1;
2781 /*
2782 * In v2 engine, software pass context and context mask to hardware
2783 * when modifying qp. If software need modify some fields in context,
2784 * we should set all bits of the relevant fields in context mask to
2785 * 0 at the same time, else set them to 0x1.
2786 */
2787 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
2788 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2789 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask);
2790 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2791 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
2792 qpc_mask);
2793 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2794 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
2795 qpc_mask);
2796 if (ret)
2797 goto out;
2798 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
2799 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
2800 qpc_mask);
2801 if (ret)
2802 goto out;
2803 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) ||
2804 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) ||
2805 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) ||
2806 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) ||
2807 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) ||
2808 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
2809 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
2810 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
2811 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
2812 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
2813 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
2814 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
2815 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) ||
2816 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR)) {
2817 /* Nothing */
2818 ;
2819 } else {
2820 dev_err(dev, "Illegal state for QP!\n");
2821 goto out;
2822 }
2823
2824 /* Every status migrate must change state */
2825 roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
2826 V2_QPC_BYTE_60_QP_ST_S, new_state);
2827 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
2828 V2_QPC_BYTE_60_QP_ST_S, 0);
2829
2830 /* SW pass context to HW */
2831 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
2832 context, hr_qp);
2833 if (ret) {
2834 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
2835 goto out;
2836 }
2837
2838 hr_qp->state = new_state;
2839
2840 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2841 hr_qp->resp_depth = attr->max_dest_rd_atomic;
2842 if (attr_mask & IB_QP_PORT) {
2843 hr_qp->port = attr->port_num - 1;
2844 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
2845 }
2846
2847 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2848 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2849 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2850 if (ibqp->send_cq != ibqp->recv_cq)
2851 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
2852 hr_qp->qpn, NULL);
2853
2854 hr_qp->rq.head = 0;
2855 hr_qp->rq.tail = 0;
2856 hr_qp->sq.head = 0;
2857 hr_qp->sq.tail = 0;
2858 hr_qp->sq_next_wqe = 0;
2859 hr_qp->next_sge = 0;
2860 }
2861
2862out:
2863 kfree(context);
2864 return ret;
2865}
2866
2867static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
2868{
2869 switch (state) {
2870 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
2871 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
2872 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
2873 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
2874 case HNS_ROCE_QP_ST_SQ_DRAINING:
2875 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
2876 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
2877 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
2878 default: return -1;
2879 }
2880}
2881
2882static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
2883 struct hns_roce_qp *hr_qp,
2884 struct hns_roce_v2_qp_context *hr_context)
2885{
2886 struct hns_roce_cmd_mailbox *mailbox;
2887 int ret;
2888
2889 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2890 if (IS_ERR(mailbox))
2891 return PTR_ERR(mailbox);
2892
2893 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
2894 HNS_ROCE_CMD_QUERY_QPC,
2895 HNS_ROCE_CMD_TIMEOUT_MSECS);
2896 if (ret) {
2897 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
2898 goto out;
2899 }
2900
2901 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
2902
2903out:
2904 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2905 return ret;
2906}
2907
2908static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
2909 int qp_attr_mask,
2910 struct ib_qp_init_attr *qp_init_attr)
2911{
2912 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2913 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2914 struct hns_roce_v2_qp_context *context;
2915 struct device *dev = hr_dev->dev;
2916 int tmp_qp_state;
2917 int state;
2918 int ret;
2919
2920 context = kzalloc(sizeof(*context), GFP_KERNEL);
2921 if (!context)
2922 return -ENOMEM;
2923
2924 memset(qp_attr, 0, sizeof(*qp_attr));
2925 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
2926
2927 mutex_lock(&hr_qp->mutex);
2928
2929 if (hr_qp->state == IB_QPS_RESET) {
2930 qp_attr->qp_state = IB_QPS_RESET;
2931 ret = 0;
2932 goto done;
2933 }
2934
2935 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
2936 if (ret) {
2937 dev_err(dev, "query qpc error\n");
2938 ret = -EINVAL;
2939 goto out;
2940 }
2941
2942 state = roce_get_field(context->byte_60_qpst_mapid,
2943 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
2944 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
2945 if (tmp_qp_state == -1) {
2946 dev_err(dev, "Illegal ib_qp_state\n");
2947 ret = -EINVAL;
2948 goto out;
2949 }
2950 hr_qp->state = (u8)tmp_qp_state;
2951 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
2952 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
2953 V2_QPC_BYTE_24_MTU_M,
2954 V2_QPC_BYTE_24_MTU_S);
2955 qp_attr->path_mig_state = IB_MIG_ARMED;
2956 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2957 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
2958 qp_attr->qkey = V2_QKEY_VAL;
2959
2960 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
2961 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
2962 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
2963 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
2964 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
2965 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
2966 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
2967 V2_QPC_BYTE_56_DQPN_M,
2968 V2_QPC_BYTE_56_DQPN_S);
2969 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
2970 V2_QPC_BYTE_76_RRE_S)) << 2) |
2971 ((roce_get_bit(context->byte_76_srqn_op_en,
2972 V2_QPC_BYTE_76_RWE_S)) << 1) |
2973 ((roce_get_bit(context->byte_76_srqn_op_en,
2974 V2_QPC_BYTE_76_ATE_S)) << 3);
2975 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
2976 hr_qp->ibqp.qp_type == IB_QPT_UC) {
2977 struct ib_global_route *grh =
2978 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
2979
2980 rdma_ah_set_sl(&qp_attr->ah_attr,
2981 roce_get_field(context->byte_28_at_fl,
2982 V2_QPC_BYTE_28_SL_M,
2983 V2_QPC_BYTE_28_SL_S));
2984 grh->flow_label = roce_get_field(context->byte_28_at_fl,
2985 V2_QPC_BYTE_28_FL_M,
2986 V2_QPC_BYTE_28_FL_S);
2987 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
2988 V2_QPC_BYTE_20_SGID_IDX_M,
2989 V2_QPC_BYTE_20_SGID_IDX_S);
2990 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
2991 V2_QPC_BYTE_24_HOP_LIMIT_M,
2992 V2_QPC_BYTE_24_HOP_LIMIT_S);
2993 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
2994 V2_QPC_BYTE_24_TC_M,
2995 V2_QPC_BYTE_24_TC_S);
2996
2997 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
2998 }
2999
3000 qp_attr->port_num = hr_qp->port + 1;
3001 qp_attr->sq_draining = 0;
3002 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
3003 V2_QPC_BYTE_208_SR_MAX_M,
3004 V2_QPC_BYTE_208_SR_MAX_S);
3005 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
3006 V2_QPC_BYTE_140_RR_MAX_M,
3007 V2_QPC_BYTE_140_RR_MAX_S);
3008 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
3009 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3010 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
3011 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
3012 V2_QPC_BYTE_28_AT_M,
3013 V2_QPC_BYTE_28_AT_S);
3014 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
3015 V2_QPC_BYTE_212_RETRY_CNT_M,
3016 V2_QPC_BYTE_212_RETRY_CNT_S);
3017 qp_attr->rnr_retry = context->rq_rnr_timer;
3018
3019done:
3020 qp_attr->cur_qp_state = qp_attr->qp_state;
3021 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3022 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3023
3024 if (!ibqp->uobject) {
3025 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3026 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3027 } else {
3028 qp_attr->cap.max_send_wr = 0;
3029 qp_attr->cap.max_send_sge = 0;
3030 }
3031
3032 qp_init_attr->cap = qp_attr->cap;
3033
3034out:
3035 mutex_unlock(&hr_qp->mutex);
3036 kfree(context);
3037 return ret;
3038}
3039
3040static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
3041 struct hns_roce_qp *hr_qp,
3042 int is_user)
3043{
3044 struct hns_roce_cq *send_cq, *recv_cq;
3045 struct device *dev = hr_dev->dev;
3046 int ret;
3047
3048 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
3049 /* Modify qp to reset before destroying qp */
3050 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
3051 hr_qp->state, IB_QPS_RESET);
3052 if (ret) {
3053 dev_err(dev, "modify QP %06lx to ERR failed.\n",
3054 hr_qp->qpn);
3055 return ret;
3056 }
3057 }
3058
3059 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3060 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3061
3062 hns_roce_lock_cqs(send_cq, recv_cq);
3063
3064 if (!is_user) {
3065 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3066 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3067 if (send_cq != recv_cq)
3068 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
3069 }
3070
3071 hns_roce_qp_remove(hr_dev, hr_qp);
3072
3073 hns_roce_unlock_cqs(send_cq, recv_cq);
3074
3075 hns_roce_qp_free(hr_dev, hr_qp);
3076
3077 /* Not special_QP, free their QPN */
3078 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
3079 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
3080 (hr_qp->ibqp.qp_type == IB_QPT_UD))
3081 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3082
3083 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3084
3085 if (is_user) {
3086 ib_umem_release(hr_qp->umem);
3087 } else {
3088 kfree(hr_qp->sq.wrid);
3089 kfree(hr_qp->rq.wrid);
3090 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3091 }
3092
3093 return 0;
3094}
3095
3096static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp)
3097{
3098 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3099 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3100 int ret;
3101
3102 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject);
3103 if (ret) {
3104 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
3105 return ret;
3106 }
3107
3108 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
3109 kfree(hr_to_hr_sqp(hr_qp));
3110 else
3111 kfree(hr_qp);
3112
3113 return 0;
3114}
3115
3116static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
3117{
3118 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
3119 struct hns_roce_v2_cq_context *cq_context;
3120 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
3121 struct hns_roce_v2_cq_context *cqc_mask;
3122 struct hns_roce_cmd_mailbox *mailbox;
3123 int ret;
3124
3125 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3126 if (IS_ERR(mailbox))
3127 return PTR_ERR(mailbox);
3128
3129 cq_context = mailbox->buf;
3130 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
3131
3132 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
3133
3134 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3135 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3136 cq_count);
3137 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
3138 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3139 0);
3140 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3141 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
3142 cq_period);
3143 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
3144 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
3145 0);
3146
3147 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
3148 HNS_ROCE_CMD_MODIFY_CQC,
3149 HNS_ROCE_CMD_TIMEOUT_MSECS);
3150 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3151 if (ret)
3152 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
3153
3154 return ret;
3155}
3156
3157static const struct hns_roce_hw hns_roce_hw_v2 = {
3158 .cmq_init = hns_roce_v2_cmq_init,
3159 .cmq_exit = hns_roce_v2_cmq_exit,
3160 .hw_profile = hns_roce_v2_profile,
3161 .post_mbox = hns_roce_v2_post_mbox,
3162 .chk_mbox = hns_roce_v2_chk_mbox,
3163 .set_gid = hns_roce_v2_set_gid,
3164 .set_mac = hns_roce_v2_set_mac,
3165 .write_mtpt = hns_roce_v2_write_mtpt,
3166 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
3167 .write_cqc = hns_roce_v2_write_cqc,
3168 .set_hem = hns_roce_v2_set_hem,
3169 .clear_hem = hns_roce_v2_clear_hem,
3170 .modify_qp = hns_roce_v2_modify_qp,
3171 .query_qp = hns_roce_v2_query_qp,
3172 .destroy_qp = hns_roce_v2_destroy_qp,
3173 .modify_cq = hns_roce_v2_modify_cq,
3174 .post_send = hns_roce_v2_post_send,
3175 .post_recv = hns_roce_v2_post_recv,
3176 .req_notify_cq = hns_roce_v2_req_notify_cq,
3177 .poll_cq = hns_roce_v2_poll_cq,
3178};
3179
3180static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
3181 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
3182 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
3183 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
3184 /* required last entry */
3185 {0, }
3186};
3187
3188static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
3189 struct hnae3_handle *handle)
3190{
3191 const struct pci_device_id *id;
3192
3193 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
3194 if (!id) {
3195 dev_err(hr_dev->dev, "device is not compatible!\n");
3196 return -ENXIO;
3197 }
3198
3199 hr_dev->hw = &hns_roce_hw_v2;
3200 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
3201 hr_dev->odb_offset = hr_dev->sdb_offset;
3202
3203 /* Get info from NIC driver. */
3204 hr_dev->reg_base = handle->rinfo.roce_io_base;
3205 hr_dev->caps.num_ports = 1;
3206 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
3207 hr_dev->iboe.phy_port[0] = 0;
3208
3209 /* cmd issue mode: 0 is poll, 1 is event */
3210 hr_dev->cmd_mod = 0;
3211 hr_dev->loop_idc = 0;
3212
3213 return 0;
3214}
3215
3216static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
3217{
3218 struct hns_roce_dev *hr_dev;
3219 int ret;
3220
3221 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
3222 if (!hr_dev)
3223 return -ENOMEM;
3224
3225 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
3226 if (!hr_dev->priv) {
3227 ret = -ENOMEM;
3228 goto error_failed_kzalloc;
3229 }
3230
3231 hr_dev->pci_dev = handle->pdev;
3232 hr_dev->dev = &handle->pdev->dev;
3233 handle->priv = hr_dev;
3234
3235 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
3236 if (ret) {
3237 dev_err(hr_dev->dev, "Get Configuration failed!\n");
3238 goto error_failed_get_cfg;
3239 }
3240
3241 ret = hns_roce_init(hr_dev);
3242 if (ret) {
3243 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
3244 goto error_failed_get_cfg;
3245 }
3246
3247 return 0;
3248
3249error_failed_get_cfg:
3250 kfree(hr_dev->priv);
3251
3252error_failed_kzalloc:
3253 ib_dealloc_device(&hr_dev->ib_dev);
3254
3255 return ret;
3256}
3257
3258static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
3259 bool reset)
3260{
3261 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
3262
3263 hns_roce_exit(hr_dev);
3264 kfree(hr_dev->priv);
3265 ib_dealloc_device(&hr_dev->ib_dev);
3266}
3267
3268static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
3269 .init_instance = hns_roce_hw_v2_init_instance,
3270 .uninit_instance = hns_roce_hw_v2_uninit_instance,
3271};
3272
3273static struct hnae3_client hns_roce_hw_v2_client = {
3274 .name = "hns_roce_hw_v2",
3275 .type = HNAE3_CLIENT_ROCE,
3276 .ops = &hns_roce_hw_v2_ops,
3277};
3278
3279static int __init hns_roce_hw_v2_init(void)
3280{
3281 return hnae3_register_client(&hns_roce_hw_v2_client);
3282}
3283
3284static void __exit hns_roce_hw_v2_exit(void)
3285{
3286 hnae3_unregister_client(&hns_roce_hw_v2_client);
3287}
3288
3289module_init(hns_roce_hw_v2_init);
3290module_exit(hns_roce_hw_v2_exit);
3291
3292MODULE_LICENSE("Dual BSD/GPL");
3293MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
3294MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
3295MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
3296MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
new file mode 100644
index 000000000000..04b7a51b8efb
--- /dev/null
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -0,0 +1,1177 @@
1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _HNS_ROCE_HW_V2_H
34#define _HNS_ROCE_HW_V2_H
35
36#include <linux/bitops.h>
37
38#define HNS_ROCE_VF_QPC_BT_NUM 256
39#define HNS_ROCE_VF_SRQC_BT_NUM 64
40#define HNS_ROCE_VF_CQC_BT_NUM 64
41#define HNS_ROCE_VF_MPT_BT_NUM 64
42#define HNS_ROCE_VF_EQC_NUM 64
43#define HNS_ROCE_VF_SMAC_NUM 32
44#define HNS_ROCE_VF_SGID_NUM 32
45#define HNS_ROCE_VF_SL_NUM 8
46
47#define HNS_ROCE_V2_MAX_QP_NUM 0x2000
48#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
49#define HNS_ROCE_V2_MAX_CQ_NUM 0x8000
50#define HNS_ROCE_V2_MAX_CQE_NUM 0x10000
51#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100
52#define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff
53#define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
54#define HNS_ROCE_V2_UAR_NUM 256
55#define HNS_ROCE_V2_PHY_UAR_NUM 1
56#define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000
57#define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
58#define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
59#define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
60#define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
61#define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
62#define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
63#define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
64#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
65#define HNS_ROCE_V2_QPC_ENTRY_SZ 256
66#define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
67#define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
68#define HNS_ROCE_V2_CQC_ENTRY_SZ 64
69#define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
70#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
71#define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
72#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
73#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
74#define HNS_ROCE_INVALID_LKEY 0x100
75#define HNS_ROCE_CMQ_TX_TIMEOUT 200
76
77#define HNS_ROCE_CONTEXT_HOP_NUM 1
78#define HNS_ROCE_MTT_HOP_NUM 1
79#define HNS_ROCE_CQE_HOP_NUM 1
80#define HNS_ROCE_PBL_HOP_NUM 2
81#define HNS_ROCE_V2_GID_INDEX_NUM 256
82
83#define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
84
85#define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
86#define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1
87#define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2
88#define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3
89#define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
90#define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5
91
92#define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
93#define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
94#define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
95#define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
96#define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
97#define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
98
99#define HNS_ROCE_CMQ_DESC_NUM_S 3
100#define HNS_ROCE_CMQ_EN_B 16
101#define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B)
102
103#define check_whether_last_step(hop_num, step_idx) \
104 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
105 (step_idx == 1 && hop_num == 1) || \
106 (step_idx == 2 && hop_num == 2))
107
108#define V2_CQ_DB_REQ_NOT_SOL 0
109#define V2_CQ_DB_REQ_NOT 1
110
111#define V2_CQ_STATE_VALID 1
112#define V2_QKEY_VAL 0x80010000
113
114#define GID_LEN_V2 16
115
116#define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff
117
118enum {
119 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
120 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
121 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
122 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
123 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
124 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
125 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
126 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
127 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
128 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
129 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
130 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
131 HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc,
132 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
133};
134
135enum {
136 HNS_ROCE_SQ_OPCODE_SEND = 0x0,
137 HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1,
138 HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2,
139 HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3,
140 HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4,
141 HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5,
142 HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6,
143 HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7,
144 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8,
145 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9,
146 HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa,
147 HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb,
148 HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc,
149};
150
151enum {
152 /* rq operations */
153 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
154 HNS_ROCE_V2_OPCODE_SEND = 0x1,
155 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
156 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
157};
158
159enum {
160 HNS_ROCE_V2_SQ_DB = 0x0,
161 HNS_ROCE_V2_RQ_DB = 0x1,
162 HNS_ROCE_V2_SRQ_DB = 0x2,
163 HNS_ROCE_V2_CQ_DB_PTR = 0x3,
164 HNS_ROCE_V2_CQ_DB_NTR = 0x4,
165};
166
167enum {
168 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
169 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
170 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
171 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
172 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
173 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
174 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
175 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
176 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
177 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
178 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
179 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
180 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
181 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
182
183 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
184};
185
186/* CMQ command */
187enum hns_roce_opcode_type {
188 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
189 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
190 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
191 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
192 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
193 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
194};
195
196enum {
197 TYPE_CRQ,
198 TYPE_CSQ,
199};
200
201enum hns_roce_cmd_return_status {
202 CMD_EXEC_SUCCESS = 0,
203 CMD_NO_AUTH = 1,
204 CMD_NOT_EXEC = 2,
205 CMD_QUEUE_FULL = 3,
206};
207
208enum hns_roce_sgid_type {
209 GID_TYPE_FLAG_ROCE_V1 = 0,
210 GID_TYPE_FLAG_ROCE_V2_IPV4,
211 GID_TYPE_FLAG_ROCE_V2_IPV6,
212};
213
214struct hns_roce_v2_cq_context {
215 u32 byte_4_pg_ceqn;
216 u32 byte_8_cqn;
217 u32 cqe_cur_blk_addr;
218 u32 byte_16_hop_addr;
219 u32 cqe_nxt_blk_addr;
220 u32 byte_24_pgsz_addr;
221 u32 byte_28_cq_pi;
222 u32 byte_32_cq_ci;
223 u32 cqe_ba;
224 u32 byte_40_cqe_ba;
225 u32 byte_44_db_record;
226 u32 db_record_addr;
227 u32 byte_52_cqe_cnt;
228 u32 byte_56_cqe_period_maxcnt;
229 u32 cqe_report_timer;
230 u32 byte_64_se_cqe_idx;
231};
232#define V2_CQC_BYTE_4_CQ_ST_S 0
233#define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
234
235#define V2_CQC_BYTE_4_POLL_S 2
236
237#define V2_CQC_BYTE_4_SE_S 3
238
239#define V2_CQC_BYTE_4_OVER_IGNORE_S 4
240
241#define V2_CQC_BYTE_4_COALESCE_S 5
242
243#define V2_CQC_BYTE_4_ARM_ST_S 6
244#define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
245
246#define V2_CQC_BYTE_4_SHIFT_S 8
247#define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
248
249#define V2_CQC_BYTE_4_CMD_SN_S 13
250#define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
251
252#define V2_CQC_BYTE_4_CEQN_S 15
253#define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
254
255#define V2_CQC_BYTE_4_PAGE_OFFSET_S 24
256#define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
257
258#define V2_CQC_BYTE_8_CQN_S 0
259#define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
260
261#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
262#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
263
264#define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
265#define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
266
267#define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
268#define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
269
270#define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24
271#define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
272
273#define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28
274#define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
275
276#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
277#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
278
279#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
280#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
281
282#define V2_CQC_BYTE_40_CQE_BA_S 0
283#define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
284
285#define V2_CQC_BYTE_44_DB_RECORD_EN_S 0
286
287#define V2_CQC_BYTE_52_CQE_CNT_S 0
288#define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
289
290#define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
291#define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
292
293#define V2_CQC_BYTE_56_CQ_PERIOD_S 16
294#define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
295
296#define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
297#define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
298
299enum{
300 V2_MPT_ST_VALID = 0x1,
301};
302
303enum hns_roce_v2_qp_state {
304 HNS_ROCE_QP_ST_RST,
305 HNS_ROCE_QP_ST_INIT,
306 HNS_ROCE_QP_ST_RTR,
307 HNS_ROCE_QP_ST_RTS,
308 HNS_ROCE_QP_ST_SQER,
309 HNS_ROCE_QP_ST_SQD,
310 HNS_ROCE_QP_ST_ERR,
311 HNS_ROCE_QP_ST_SQ_DRAINING,
312 HNS_ROCE_QP_NUM_ST
313};
314
315struct hns_roce_v2_qp_context {
316 u32 byte_4_sqpn_tst;
317 u32 wqe_sge_ba;
318 u32 byte_12_sq_hop;
319 u32 byte_16_buf_ba_pg_sz;
320 u32 byte_20_smac_sgid_idx;
321 u32 byte_24_mtu_tc;
322 u32 byte_28_at_fl;
323 u8 dgid[GID_LEN_V2];
324 u32 dmac;
325 u32 byte_52_udpspn_dmac;
326 u32 byte_56_dqpn_err;
327 u32 byte_60_qpst_mapid;
328 u32 qkey_xrcd;
329 u32 byte_68_rq_db;
330 u32 rq_db_record_addr;
331 u32 byte_76_srqn_op_en;
332 u32 byte_80_rnr_rx_cqn;
333 u32 byte_84_rq_ci_pi;
334 u32 rq_cur_blk_addr;
335 u32 byte_92_srq_info;
336 u32 byte_96_rx_reqmsn;
337 u32 rq_nxt_blk_addr;
338 u32 byte_104_rq_sge;
339 u32 byte_108_rx_reqepsn;
340 u32 rq_rnr_timer;
341 u32 rx_msg_len;
342 u32 rx_rkey_pkt_info;
343 u64 rx_va;
344 u32 byte_132_trrl;
345 u32 trrl_ba;
346 u32 byte_140_raq;
347 u32 byte_144_raq;
348 u32 byte_148_raq;
349 u32 byte_152_raq;
350 u32 byte_156_raq;
351 u32 byte_160_sq_ci_pi;
352 u32 sq_cur_blk_addr;
353 u32 byte_168_irrl_idx;
354 u32 byte_172_sq_psn;
355 u32 byte_176_msg_pktn;
356 u32 sq_cur_sge_blk_addr;
357 u32 byte_184_irrl_idx;
358 u32 cur_sge_offset;
359 u32 byte_192_ext_sge;
360 u32 byte_196_sq_psn;
361 u32 byte_200_sq_max;
362 u32 irrl_ba;
363 u32 byte_208_irrl;
364 u32 byte_212_lsn;
365 u32 sq_timer;
366 u32 byte_220_retry_psn_msn;
367 u32 byte_224_retry_msg;
368 u32 rx_sq_cur_blk_addr;
369 u32 byte_232_irrl_sge;
370 u32 irrl_cur_sge_offset;
371 u32 byte_240_irrl_tail;
372 u32 byte_244_rnr_rxack;
373 u32 byte_248_ack_psn;
374 u32 byte_252_err_txcqn;
375 u32 byte_256_sqflush_rqcqe;
376};
377
378#define V2_QPC_BYTE_4_TST_S 0
379#define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
380
381#define V2_QPC_BYTE_4_SGE_SHIFT_S 3
382#define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
383
384#define V2_QPC_BYTE_4_SQPN_S 8
385#define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
386
387#define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
388#define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
389
390#define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
391#define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
392
393#define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
394
395#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
396#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
397
398#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
399#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
400
401#define V2_QPC_BYTE_16_PD_S 8
402#define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
403
404#define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
405#define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
406
407#define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
408#define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
409
410#define V2_QPC_BYTE_20_RQWS_S 4
411#define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
412
413#define V2_QPC_BYTE_20_SQ_SHIFT_S 8
414#define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
415
416#define V2_QPC_BYTE_20_RQ_SHIFT_S 12
417#define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
418
419#define V2_QPC_BYTE_20_SGID_IDX_S 16
420#define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
421
422#define V2_QPC_BYTE_20_SMAC_IDX_S 24
423#define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
424
425#define V2_QPC_BYTE_24_HOP_LIMIT_S 0
426#define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
427
428#define V2_QPC_BYTE_24_TC_S 8
429#define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
430
431#define V2_QPC_BYTE_24_VLAN_IDX_S 16
432#define V2_QPC_BYTE_24_VLAN_IDX_M GENMASK(27, 16)
433
434#define V2_QPC_BYTE_24_MTU_S 28
435#define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
436
437#define V2_QPC_BYTE_28_FL_S 0
438#define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
439
440#define V2_QPC_BYTE_28_SL_S 20
441#define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
442
443#define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
444
445#define V2_QPC_BYTE_28_CE_FLAG_S 25
446
447#define V2_QPC_BYTE_28_LBI_S 26
448
449#define V2_QPC_BYTE_28_AT_S 27
450#define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
451
452#define V2_QPC_BYTE_52_DMAC_S 0
453#define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
454
455#define V2_QPC_BYTE_52_UDPSPN_S 16
456#define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
457
458#define V2_QPC_BYTE_56_DQPN_S 0
459#define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
460
461#define V2_QPC_BYTE_56_SQ_TX_ERR_S 24
462#define V2_QPC_BYTE_56_SQ_RX_ERR_S 25
463#define V2_QPC_BYTE_56_RQ_TX_ERR_S 26
464#define V2_QPC_BYTE_56_RQ_RX_ERR_S 27
465
466#define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
467#define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
468
469#define V2_QPC_BYTE_60_MAPID_S 0
470#define V2_QPC_BYTE_60_MAPID_M GENMASK(12, 0)
471
472#define V2_QPC_BYTE_60_INNER_MAP_IND_S 13
473
474#define V2_QPC_BYTE_60_SQ_MAP_IND_S 14
475
476#define V2_QPC_BYTE_60_RQ_MAP_IND_S 15
477
478#define V2_QPC_BYTE_60_TEMPID_S 16
479#define V2_QPC_BYTE_60_TEMPID_M GENMASK(22, 16)
480
481#define V2_QPC_BYTE_60_EXT_MAP_IND_S 23
482
483#define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S 24
484#define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M GENMASK(26, 24)
485
486#define V2_QPC_BYTE_60_SQ_RLS_IND_S 27
487
488#define V2_QPC_BYTE_60_SQ_EXT_IND_S 28
489
490#define V2_QPC_BYTE_60_QP_ST_S 29
491#define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
492
493#define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
494
495#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
496#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
497
498#define V2_QPC_BYTE_76_SRQN_S 0
499#define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
500
501#define V2_QPC_BYTE_76_SRQ_EN_S 24
502
503#define V2_QPC_BYTE_76_RRE_S 25
504
505#define V2_QPC_BYTE_76_RWE_S 26
506
507#define V2_QPC_BYTE_76_ATE_S 27
508
509#define V2_QPC_BYTE_76_RQIE_S 28
510
511#define V2_QPC_BYTE_80_RX_CQN_S 0
512#define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
513
514#define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
515#define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
516
517#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
518#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
519
520#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
521#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
522
523#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
524#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
525
526#define V2_QPC_BYTE_92_SRQ_INFO_S 20
527#define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
528
529#define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
530#define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
531
532#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
533#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
534
535#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
536#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
537
538#define V2_QPC_BYTE_108_INV_CREDIT_S 0
539
540#define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
541
542#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
543#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
544
545#define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
546
547#define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
548#define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
549
550#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
551#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
552
553#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
554#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
555
556#define V2_QPC_BYTE_132_TRRL_BA_S 16
557#define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
558
559#define V2_QPC_BYTE_140_TRRL_BA_S 0
560#define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
561
562#define V2_QPC_BYTE_140_RR_MAX_S 12
563#define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
564
565#define V2_QPC_BYTE_140_RSVD_RAQ_MAP_S 15
566
567#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
568#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
569
570#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
571#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
572
573#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
574#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
575
576#define V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S 24
577
578#define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
579#define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
580
581#define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
582
583#define V2_QPC_BYTE_148_RQ_MSN_S 0
584#define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
585
586#define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
587#define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
588
589#define V2_QPC_BYTE_152_RAQ_PSN_S 8
590#define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(31, 8)
591
592#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
593#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
594
595#define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
596#define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
597
598#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
599#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
600
601#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
602#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
603
604#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
605#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
606
607#define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
608
609#define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
610
611#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
612#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
613
614#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24
615#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24)
616
617#define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
618#define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
619
620#define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
621#define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
622
623#define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
624
625#define V2_QPC_BYTE_172_FRE_S 7
626
627#define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
628#define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
629
630#define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
631#define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
632
633#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
634#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
635
636#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
637#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
638
639#define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
640#define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
641
642#define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
643#define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
644
645#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
646#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
647
648#define V2_QPC_BYTE_196_IRRL_HEAD_S 0
649#define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
650
651#define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
652#define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
653
654#define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
655#define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
656
657#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
658#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
659
660#define V2_QPC_BYTE_208_IRRL_BA_S 0
661#define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
662
663#define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
664
665#define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
666
667#define V2_QPC_BYTE_208_RMT_E2E_S 28
668
669#define V2_QPC_BYTE_208_SR_MAX_S 29
670#define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
671
672#define V2_QPC_BYTE_212_LSN_S 0
673#define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
674
675#define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
676#define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
677
678#define V2_QPC_BYTE_212_CHECK_FLG_S 27
679#define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
680
681#define V2_QPC_BYTE_212_RETRY_CNT_S 29
682#define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
683
684#define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
685#define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
686
687#define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
688#define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
689
690#define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
691#define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
692
693#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
694#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
695
696#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
697#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
698
699#define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
700#define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
701
702#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
703#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
704
705#define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
706#define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
707
708#define V2_QPC_BYTE_240_RX_ACK_MSN_S 16
709#define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
710
711#define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
712#define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
713
714#define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
715#define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
716
717#define V2_QPC_BYTE_244_RNR_CNT_S 27
718#define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
719
720#define V2_QPC_BYTE_248_IRRL_PSN_S 0
721#define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
722
723#define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
724
725#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
726#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
727
728#define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
729
730#define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
731
732#define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
733
734#define V2_QPC_BYTE_252_TX_CQN_S 0
735#define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
736
737#define V2_QPC_BYTE_252_SIG_TYPE_S 24
738
739#define V2_QPC_BYTE_252_ERR_TYPE_S 25
740#define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
741
742#define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
743#define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
744
745#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
746#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
747
748struct hns_roce_v2_cqe {
749 u32 byte_4;
750 u32 rkey_immtdata;
751 u32 byte_12;
752 u32 byte_16;
753 u32 byte_cnt;
754 u32 smac;
755 u32 byte_28;
756 u32 byte_32;
757};
758
759#define V2_CQE_BYTE_4_OPCODE_S 0
760#define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
761
762#define V2_CQE_BYTE_4_RQ_INLINE_S 5
763
764#define V2_CQE_BYTE_4_S_R_S 6
765
766#define V2_CQE_BYTE_4_OWNER_S 7
767
768#define V2_CQE_BYTE_4_STATUS_S 8
769#define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
770
771#define V2_CQE_BYTE_4_WQE_INDX_S 16
772#define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
773
774#define V2_CQE_BYTE_12_XRC_SRQN_S 0
775#define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
776
777#define V2_CQE_BYTE_16_LCL_QPN_S 0
778#define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
779
780#define V2_CQE_BYTE_16_SUB_STATUS_S 24
781#define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
782
783#define V2_CQE_BYTE_28_SMAC_4_S 0
784#define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0)
785
786#define V2_CQE_BYTE_28_SMAC_5_S 8
787#define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8)
788
789#define V2_CQE_BYTE_28_PORT_TYPE_S 16
790#define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
791
792#define V2_CQE_BYTE_32_RMT_QPN_S 0
793#define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
794
795#define V2_CQE_BYTE_32_SL_S 24
796#define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
797
798#define V2_CQE_BYTE_32_PORTN_S 27
799#define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
800
801#define V2_CQE_BYTE_32_GRH_S 30
802
803#define V2_CQE_BYTE_32_LPK_S 31
804
805struct hns_roce_v2_mpt_entry {
806 __le32 byte_4_pd_hop_st;
807 __le32 byte_8_mw_cnt_en;
808 __le32 byte_12_mw_pa;
809 __le32 bound_lkey;
810 __le32 len_l;
811 __le32 len_h;
812 __le32 lkey;
813 __le32 va_l;
814 __le32 va_h;
815 __le32 pbl_size;
816 __le32 pbl_ba_l;
817 __le32 byte_48_mode_ba;
818 __le32 pa0_l;
819 __le32 byte_56_pa0_h;
820 __le32 pa1_l;
821 __le32 byte_64_buf_pa1;
822};
823
824#define V2_MPT_BYTE_4_MPT_ST_S 0
825#define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
826
827#define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
828#define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
829
830#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
831#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
832
833#define V2_MPT_BYTE_4_PD_S 8
834#define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
835
836#define V2_MPT_BYTE_8_RA_EN_S 0
837
838#define V2_MPT_BYTE_8_R_INV_EN_S 1
839
840#define V2_MPT_BYTE_8_L_INV_EN_S 2
841
842#define V2_MPT_BYTE_8_BIND_EN_S 3
843
844#define V2_MPT_BYTE_8_ATOMIC_EN_S 4
845
846#define V2_MPT_BYTE_8_RR_EN_S 5
847
848#define V2_MPT_BYTE_8_RW_EN_S 6
849
850#define V2_MPT_BYTE_8_LW_EN_S 7
851
852#define V2_MPT_BYTE_12_PA_S 1
853
854#define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
855
856#define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
857#define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
858
859#define V2_MPT_BYTE_48_PBL_BA_H_S 0
860#define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
861
862#define V2_MPT_BYTE_48_BLK_MODE_S 29
863
864#define V2_MPT_BYTE_56_PA0_H_S 0
865#define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
866
867#define V2_MPT_BYTE_64_PA1_H_S 0
868#define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
869
870#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
871#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
872
873#define V2_DB_BYTE_4_TAG_S 0
874#define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
875
876#define V2_DB_BYTE_4_CMD_S 24
877#define V2_DB_BYTE_4_CMD_M GENMASK(27, 24)
878
879#define V2_DB_PARAMETER_CONS_IDX_S 0
880#define V2_DB_PARAMETER_CONS_IDX_M GENMASK(15, 0)
881
882#define V2_DB_PARAMETER_SL_S 16
883#define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
884
885struct hns_roce_v2_cq_db {
886 u32 byte_4;
887 u32 parameter;
888};
889
890#define V2_CQ_DB_BYTE_4_TAG_S 0
891#define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
892
893#define V2_CQ_DB_BYTE_4_CMD_S 24
894#define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24)
895
896#define V2_CQ_DB_PARAMETER_CONS_IDX_S 0
897#define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
898
899#define V2_CQ_DB_PARAMETER_CMD_SN_S 25
900#define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25)
901
902#define V2_CQ_DB_PARAMETER_NOTIFY_S 24
903
904struct hns_roce_v2_rc_send_wqe {
905 u32 byte_4;
906 u32 msg_len;
907 u32 inv_key_immtdata;
908 u32 byte_16;
909 u32 byte_20;
910 u32 rkey;
911 u64 va;
912};
913
914#define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
915#define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
916
917#define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
918
919#define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
920
921#define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
922
923#define V2_RC_SEND_WQE_BYTE_4_SO_S 10
924
925#define V2_RC_SEND_WQE_BYTE_4_SE_S 11
926
927#define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
928
929#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
930#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
931
932#define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
933#define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
934
935#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
936#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
937
938struct hns_roce_v2_wqe_data_seg {
939 __be32 len;
940 __be32 lkey;
941 __be64 addr;
942};
943
944struct hns_roce_v2_db {
945 u32 byte_4;
946 u32 parameter;
947};
948
949struct hns_roce_query_version {
950 __le16 rocee_vendor_id;
951 __le16 rocee_hw_version;
952 __le32 rsv[5];
953};
954
955struct hns_roce_cfg_global_param {
956 __le32 time_cfg_udp_port;
957 __le32 rsv[5];
958};
959
960#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
961#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
962
963#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16
964#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
965
966struct hns_roce_pf_res {
967 __le32 rsv;
968 __le32 qpc_bt_idx_num;
969 __le32 srqc_bt_idx_num;
970 __le32 cqc_bt_idx_num;
971 __le32 mpt_bt_idx_num;
972 __le32 eqc_bt_idx_num;
973};
974
975#define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
976#define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
977
978#define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16
979#define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
980
981#define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
982#define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
983
984#define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16
985#define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
986
987#define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
988#define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
989
990#define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16
991#define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
992
993#define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
994#define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
995
996#define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16
997#define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
998
999#define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
1000#define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
1001
1002#define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16
1003#define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
1004
1005struct hns_roce_vf_res_a {
1006 u32 vf_id;
1007 u32 vf_qpc_bt_idx_num;
1008 u32 vf_srqc_bt_idx_num;
1009 u32 vf_cqc_bt_idx_num;
1010 u32 vf_mpt_bt_idx_num;
1011 u32 vf_eqc_bt_idx_num;
1012};
1013
1014#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
1015#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
1016
1017#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16
1018#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
1019
1020#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
1021#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
1022
1023#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16
1024#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
1025
1026#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
1027#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
1028
1029#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16
1030#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
1031
1032#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
1033#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
1034
1035#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16
1036#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
1037
1038#define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
1039#define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
1040
1041#define VF_RES_A_DATA_5_VF_EQC_NUM_S 16
1042#define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
1043
1044struct hns_roce_vf_res_b {
1045 u32 rsv0;
1046 u32 vf_smac_idx_num;
1047 u32 vf_sgid_idx_num;
1048 u32 vf_qid_idx_sl_num;
1049 u32 rsv[2];
1050};
1051
1052#define VF_RES_B_DATA_0_VF_ID_S 0
1053#define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
1054
1055#define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
1056#define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
1057
1058#define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8
1059#define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
1060
1061#define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
1062#define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
1063
1064#define VF_RES_B_DATA_2_VF_SGID_NUM_S 8
1065#define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
1066
1067#define VF_RES_B_DATA_3_VF_QID_IDX_S 0
1068#define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
1069
1070#define VF_RES_B_DATA_3_VF_SL_NUM_S 16
1071#define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
1072
1073/* Reg field definition */
1074#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S 0
1075#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M GENMASK(15, 0)
1076
1077#define ROCEE_VF_SGID_CFG4_SGID_TYPE_S 0
1078#define ROCEE_VF_SGID_CFG4_SGID_TYPE_M GENMASK(1, 0)
1079
1080struct hns_roce_cfg_bt_attr {
1081 u32 vf_qpc_cfg;
1082 u32 vf_srqc_cfg;
1083 u32 vf_cqc_cfg;
1084 u32 vf_mpt_cfg;
1085 u32 rsv[2];
1086};
1087
1088#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
1089#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
1090
1091#define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4
1092#define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4)
1093
1094#define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8
1095#define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8)
1096
1097#define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0
1098#define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
1099
1100#define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4
1101#define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4)
1102
1103#define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8
1104#define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8)
1105
1106#define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0
1107#define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
1108
1109#define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4
1110#define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4)
1111
1112#define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8
1113#define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8)
1114
1115#define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0
1116#define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
1117
1118#define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4
1119#define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4)
1120
1121#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8
1122#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
1123
1124struct hns_roce_cmq_desc {
1125 u16 opcode;
1126 u16 flag;
1127 u16 retval;
1128 u16 rsv;
1129 u32 data[6];
1130};
1131
1132#define ROCEE_VF_MB_CFG0_REG 0x40
1133#define ROCEE_VF_MB_STATUS_REG 0x58
1134
1135#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1136
1137#define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1138#define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
1139
1140#define HNS_ROCE_VF_MB4_TAG_MASK 0xFFFFFF00
1141#define HNS_ROCE_VF_MB4_TAG_SHIFT 8
1142
1143#define HNS_ROCE_VF_MB4_CMD_MASK 0xFF
1144#define HNS_ROCE_VF_MB4_CMD_SHIFT 0
1145
1146#define HNS_ROCE_VF_MB5_EVENT_MASK 0x10000
1147#define HNS_ROCE_VF_MB5_EVENT_SHIFT 16
1148
1149#define HNS_ROCE_VF_MB5_TOKEN_MASK 0xFFFF
1150#define HNS_ROCE_VF_MB5_TOKEN_SHIFT 0
1151
1152struct hns_roce_v2_cmq_ring {
1153 dma_addr_t desc_dma_addr;
1154 struct hns_roce_cmq_desc *desc;
1155 u32 head;
1156 u32 tail;
1157
1158 u16 buf_size;
1159 u16 desc_num;
1160 int next_to_use;
1161 int next_to_clean;
1162 u8 flag;
1163 spinlock_t lock; /* command queue lock */
1164};
1165
1166struct hns_roce_v2_cmq {
1167 struct hns_roce_v2_cmq_ring csq;
1168 struct hns_roce_v2_cmq_ring crq;
1169 u16 tx_timeout;
1170 u16 last_status;
1171};
1172
1173struct hns_roce_v2_priv {
1174 struct hns_roce_v2_cmq cmq;
1175};
1176
1177#endif
diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c
index d9777b662eba..cf02ac2d3596 100644
--- a/drivers/infiniband/hw/hns/hns_roce_main.c
+++ b/drivers/infiniband/hw/hns/hns_roce_main.c
@@ -57,20 +57,21 @@ int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
57{ 57{
58 return gid_index * hr_dev->caps.num_ports + port; 58 return gid_index * hr_dev->caps.num_ports + port;
59} 59}
60EXPORT_SYMBOL_GPL(hns_get_gid_index);
60 61
61static void hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 62static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
62{ 63{
63 u8 phy_port; 64 u8 phy_port;
64 u32 i = 0; 65 u32 i = 0;
65 66
66 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM)) 67 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
67 return; 68 return 0;
68 69
69 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++) 70 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
70 hr_dev->dev_addr[port][i] = addr[i]; 71 hr_dev->dev_addr[port][i] = addr[i];
71 72
72 phy_port = hr_dev->iboe.phy_port[port]; 73 phy_port = hr_dev->iboe.phy_port[port];
73 hr_dev->hw->set_mac(hr_dev, phy_port, addr); 74 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
74} 75}
75 76
76static int hns_roce_add_gid(struct ib_device *device, u8 port_num, 77static int hns_roce_add_gid(struct ib_device *device, u8 port_num,
@@ -80,17 +81,19 @@ static int hns_roce_add_gid(struct ib_device *device, u8 port_num,
80 struct hns_roce_dev *hr_dev = to_hr_dev(device); 81 struct hns_roce_dev *hr_dev = to_hr_dev(device);
81 u8 port = port_num - 1; 82 u8 port = port_num - 1;
82 unsigned long flags; 83 unsigned long flags;
84 int ret;
83 85
84 if (port >= hr_dev->caps.num_ports) 86 if (port >= hr_dev->caps.num_ports)
85 return -EINVAL; 87 return -EINVAL;
86 88
87 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 89 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
88 90
89 hr_dev->hw->set_gid(hr_dev, port, index, (union ib_gid *)gid); 91 ret = hr_dev->hw->set_gid(hr_dev, port, index, (union ib_gid *)gid,
92 attr);
90 93
91 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 94 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
92 95
93 return 0; 96 return ret;
94} 97}
95 98
96static int hns_roce_del_gid(struct ib_device *device, u8 port_num, 99static int hns_roce_del_gid(struct ib_device *device, u8 port_num,
@@ -100,24 +103,26 @@ static int hns_roce_del_gid(struct ib_device *device, u8 port_num,
100 union ib_gid zgid = { {0} }; 103 union ib_gid zgid = { {0} };
101 u8 port = port_num - 1; 104 u8 port = port_num - 1;
102 unsigned long flags; 105 unsigned long flags;
106 int ret;
103 107
104 if (port >= hr_dev->caps.num_ports) 108 if (port >= hr_dev->caps.num_ports)
105 return -EINVAL; 109 return -EINVAL;
106 110
107 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 111 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
108 112
109 hr_dev->hw->set_gid(hr_dev, port, index, &zgid); 113 ret = hr_dev->hw->set_gid(hr_dev, port, index, &zgid, NULL);
110 114
111 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 115 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
112 116
113 return 0; 117 return ret;
114} 118}
115 119
116static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 120static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
117 unsigned long event) 121 unsigned long event)
118{ 122{
119 struct device *dev = &hr_dev->pdev->dev; 123 struct device *dev = hr_dev->dev;
120 struct net_device *netdev; 124 struct net_device *netdev;
125 int ret = 0;
121 126
122 netdev = hr_dev->iboe.netdevs[port]; 127 netdev = hr_dev->iboe.netdevs[port];
123 if (!netdev) { 128 if (!netdev) {
@@ -130,7 +135,7 @@ static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
130 case NETDEV_CHANGE: 135 case NETDEV_CHANGE:
131 case NETDEV_REGISTER: 136 case NETDEV_REGISTER:
132 case NETDEV_CHANGEADDR: 137 case NETDEV_CHANGEADDR:
133 hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 138 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
134 break; 139 break;
135 case NETDEV_DOWN: 140 case NETDEV_DOWN:
136 /* 141 /*
@@ -142,7 +147,7 @@ static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
142 break; 147 break;
143 } 148 }
144 149
145 return 0; 150 return ret;
146} 151}
147 152
148static int hns_roce_netdev_event(struct notifier_block *self, 153static int hns_roce_netdev_event(struct notifier_block *self,
@@ -171,12 +176,17 @@ static int hns_roce_netdev_event(struct notifier_block *self,
171 176
172static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 177static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
173{ 178{
179 int ret;
174 u8 i; 180 u8 i;
175 181
176 for (i = 0; i < hr_dev->caps.num_ports; i++) { 182 for (i = 0; i < hr_dev->caps.num_ports; i++) {
177 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 183 if (hr_dev->hw->set_mtu)
178 hr_dev->caps.max_mtu); 184 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
179 hns_roce_set_mac(hr_dev, i, hr_dev->iboe.netdevs[i]->dev_addr); 185 hr_dev->caps.max_mtu);
186 ret = hns_roce_set_mac(hr_dev, i,
187 hr_dev->iboe.netdevs[i]->dev_addr);
188 if (ret)
189 return ret;
180 } 190 }
181 191
182 return 0; 192 return 0;
@@ -200,7 +210,7 @@ static int hns_roce_query_device(struct ib_device *ib_dev,
200 props->max_qp_wr = hr_dev->caps.max_wqes; 210 props->max_qp_wr = hr_dev->caps.max_wqes;
201 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 211 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
202 IB_DEVICE_RC_RNR_NAK_GEN; 212 IB_DEVICE_RC_RNR_NAK_GEN;
203 props->max_sge = hr_dev->caps.max_sq_sg; 213 props->max_sge = max(hr_dev->caps.max_sq_sg, hr_dev->caps.max_rq_sg);
204 props->max_sge_rd = 1; 214 props->max_sge_rd = 1;
205 props->max_cq = hr_dev->caps.num_cqs; 215 props->max_cq = hr_dev->caps.num_cqs;
206 props->max_cqe = hr_dev->caps.max_cqes; 216 props->max_cqe = hr_dev->caps.max_cqes;
@@ -238,7 +248,7 @@ static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
238 struct ib_port_attr *props) 248 struct ib_port_attr *props)
239{ 249{
240 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 250 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
241 struct device *dev = &hr_dev->pdev->dev; 251 struct device *dev = hr_dev->dev;
242 struct net_device *net_dev; 252 struct net_device *net_dev;
243 unsigned long flags; 253 unsigned long flags;
244 enum ib_mtu mtu; 254 enum ib_mtu mtu;
@@ -379,7 +389,8 @@ static int hns_roce_mmap(struct ib_ucontext *context,
379 to_hr_ucontext(context)->uar.pfn, 389 to_hr_ucontext(context)->uar.pfn,
380 PAGE_SIZE, vma->vm_page_prot)) 390 PAGE_SIZE, vma->vm_page_prot))
381 return -EAGAIN; 391 return -EAGAIN;
382 } else if (vma->vm_pgoff == 1 && hr_dev->hw_rev == HNS_ROCE_HW_VER1) { 392 } else if (vma->vm_pgoff == 1 && hr_dev->tptr_dma_addr &&
393 hr_dev->tptr_size) {
383 /* vm_pgoff: 1 -- TPTR */ 394 /* vm_pgoff: 1 -- TPTR */
384 if (io_remap_pfn_range(vma, vma->vm_start, 395 if (io_remap_pfn_range(vma, vma->vm_start,
385 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 396 hr_dev->tptr_dma_addr >> PAGE_SHIFT,
@@ -398,8 +409,6 @@ static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
398 struct ib_port_attr attr; 409 struct ib_port_attr attr;
399 int ret; 410 int ret;
400 411
401 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
402
403 ret = ib_query_port(ib_dev, port_num, &attr); 412 ret = ib_query_port(ib_dev, port_num, &attr);
404 if (ret) 413 if (ret)
405 return ret; 414 return ret;
@@ -408,6 +417,9 @@ static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
408 immutable->gid_tbl_len = attr.gid_tbl_len; 417 immutable->gid_tbl_len = attr.gid_tbl_len;
409 418
410 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 419 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
420 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
421 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
422 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
411 423
412 return 0; 424 return 0;
413} 425}
@@ -416,7 +428,6 @@ static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
416{ 428{
417 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 429 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
418 430
419 unregister_inetaddr_notifier(&iboe->nb_inet);
420 unregister_netdevice_notifier(&iboe->nb); 431 unregister_netdevice_notifier(&iboe->nb);
421 ib_unregister_device(&hr_dev->ib_dev); 432 ib_unregister_device(&hr_dev->ib_dev);
422} 433}
@@ -426,7 +437,7 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
426 int ret; 437 int ret;
427 struct hns_roce_ib_iboe *iboe = NULL; 438 struct hns_roce_ib_iboe *iboe = NULL;
428 struct ib_device *ib_dev = NULL; 439 struct ib_device *ib_dev = NULL;
429 struct device *dev = &hr_dev->pdev->dev; 440 struct device *dev = hr_dev->dev;
430 441
431 iboe = &hr_dev->iboe; 442 iboe = &hr_dev->iboe;
432 spin_lock_init(&iboe->lock); 443 spin_lock_init(&iboe->lock);
@@ -492,6 +503,7 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
492 503
493 /* CQ */ 504 /* CQ */
494 ib_dev->create_cq = hns_roce_ib_create_cq; 505 ib_dev->create_cq = hns_roce_ib_create_cq;
506 ib_dev->modify_cq = hr_dev->hw->modify_cq;
495 ib_dev->destroy_cq = hns_roce_ib_destroy_cq; 507 ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
496 ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq; 508 ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
497 ib_dev->poll_cq = hr_dev->hw->poll_cq; 509 ib_dev->poll_cq = hr_dev->hw->poll_cq;
@@ -500,6 +512,10 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
500 ib_dev->get_dma_mr = hns_roce_get_dma_mr; 512 ib_dev->get_dma_mr = hns_roce_get_dma_mr;
501 ib_dev->reg_user_mr = hns_roce_reg_user_mr; 513 ib_dev->reg_user_mr = hns_roce_reg_user_mr;
502 ib_dev->dereg_mr = hns_roce_dereg_mr; 514 ib_dev->dereg_mr = hns_roce_dereg_mr;
515 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
516 ib_dev->rereg_user_mr = hns_roce_rereg_user_mr;
517 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
518 }
503 519
504 /* OTHERS */ 520 /* OTHERS */
505 ib_dev->get_port_immutable = hns_roce_port_immutable; 521 ib_dev->get_port_immutable = hns_roce_port_immutable;
@@ -531,173 +547,10 @@ error_failed_setup_mtu_mac:
531 return ret; 547 return ret;
532} 548}
533 549
534static const struct of_device_id hns_roce_of_match[] = {
535 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
536 {},
537};
538MODULE_DEVICE_TABLE(of, hns_roce_of_match);
539
540static const struct acpi_device_id hns_roce_acpi_match[] = {
541 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
542 {},
543};
544MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
545
546static int hns_roce_node_match(struct device *dev, void *fwnode)
547{
548 return dev->fwnode == fwnode;
549}
550
551static struct
552platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
553{
554 struct device *dev;
555
556 /* get the 'device'corresponding to matching 'fwnode' */
557 dev = bus_find_device(&platform_bus_type, NULL,
558 fwnode, hns_roce_node_match);
559 /* get the platform device */
560 return dev ? to_platform_device(dev) : NULL;
561}
562
563static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
564{
565 int i;
566 int ret;
567 u8 phy_port;
568 int port_cnt = 0;
569 struct device *dev = &hr_dev->pdev->dev;
570 struct device_node *net_node;
571 struct net_device *netdev = NULL;
572 struct platform_device *pdev = NULL;
573 struct resource *res;
574
575 /* check if we are compatible with the underlying SoC */
576 if (dev_of_node(dev)) {
577 const struct of_device_id *of_id;
578
579 of_id = of_match_node(hns_roce_of_match, dev->of_node);
580 if (!of_id) {
581 dev_err(dev, "device is not compatible!\n");
582 return -ENXIO;
583 }
584 hr_dev->hw = (struct hns_roce_hw *)of_id->data;
585 if (!hr_dev->hw) {
586 dev_err(dev, "couldn't get H/W specific DT data!\n");
587 return -ENXIO;
588 }
589 } else if (is_acpi_device_node(dev->fwnode)) {
590 const struct acpi_device_id *acpi_id;
591
592 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
593 if (!acpi_id) {
594 dev_err(dev, "device is not compatible!\n");
595 return -ENXIO;
596 }
597 hr_dev->hw = (struct hns_roce_hw *) acpi_id->driver_data;
598 if (!hr_dev->hw) {
599 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
600 return -ENXIO;
601 }
602 } else {
603 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
604 return -ENXIO;
605 }
606
607 /* get the mapped register base address */
608 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
609 if (!res) {
610 dev_err(dev, "memory resource not found!\n");
611 return -EINVAL;
612 }
613 hr_dev->reg_base = devm_ioremap_resource(dev, res);
614 if (IS_ERR(hr_dev->reg_base))
615 return PTR_ERR(hr_dev->reg_base);
616
617 /* read the node_guid of IB device from the DT or ACPI */
618 ret = device_property_read_u8_array(dev, "node-guid",
619 (u8 *)&hr_dev->ib_dev.node_guid,
620 GUID_LEN);
621 if (ret) {
622 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
623 return ret;
624 }
625
626 /* get the RoCE associated ethernet ports or netdevices */
627 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
628 if (dev_of_node(dev)) {
629 net_node = of_parse_phandle(dev->of_node, "eth-handle",
630 i);
631 if (!net_node)
632 continue;
633 pdev = of_find_device_by_node(net_node);
634 } else if (is_acpi_device_node(dev->fwnode)) {
635 struct acpi_reference_args args;
636 struct fwnode_handle *fwnode;
637
638 ret = acpi_node_get_property_reference(dev->fwnode,
639 "eth-handle",
640 i, &args);
641 if (ret)
642 continue;
643 fwnode = acpi_fwnode_handle(args.adev);
644 pdev = hns_roce_find_pdev(fwnode);
645 } else {
646 dev_err(dev, "cannot read data from DT or ACPI\n");
647 return -ENXIO;
648 }
649
650 if (pdev) {
651 netdev = platform_get_drvdata(pdev);
652 phy_port = (u8)i;
653 if (netdev) {
654 hr_dev->iboe.netdevs[port_cnt] = netdev;
655 hr_dev->iboe.phy_port[port_cnt] = phy_port;
656 } else {
657 dev_err(dev, "no netdev found with pdev %s\n",
658 pdev->name);
659 return -ENODEV;
660 }
661 port_cnt++;
662 }
663 }
664
665 if (port_cnt == 0) {
666 dev_err(dev, "unable to get eth-handle for available ports!\n");
667 return -EINVAL;
668 }
669
670 hr_dev->caps.num_ports = port_cnt;
671
672 /* cmd issue mode: 0 is poll, 1 is event */
673 hr_dev->cmd_mod = 1;
674 hr_dev->loop_idc = 0;
675
676 /* read the interrupt names from the DT or ACPI */
677 ret = device_property_read_string_array(dev, "interrupt-names",
678 hr_dev->irq_names,
679 HNS_ROCE_MAX_IRQ_NUM);
680 if (ret < 0) {
681 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
682 return ret;
683 }
684
685 /* fetch the interrupt numbers */
686 for (i = 0; i < HNS_ROCE_MAX_IRQ_NUM; i++) {
687 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
688 if (hr_dev->irq[i] <= 0) {
689 dev_err(dev, "platform get of irq[=%d] failed!\n", i);
690 return -EINVAL;
691 }
692 }
693
694 return 0;
695}
696
697static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 550static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
698{ 551{
699 int ret; 552 int ret;
700 struct device *dev = &hr_dev->pdev->dev; 553 struct device *dev = hr_dev->dev;
701 554
702 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table, 555 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
703 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz, 556 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
@@ -707,6 +560,17 @@ static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
707 return ret; 560 return ret;
708 } 561 }
709 562
563 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
564 ret = hns_roce_init_hem_table(hr_dev,
565 &hr_dev->mr_table.mtt_cqe_table,
566 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
567 hr_dev->caps.num_cqe_segs, 1);
568 if (ret) {
569 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
570 goto err_unmap_cqe;
571 }
572 }
573
710 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 574 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
711 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 575 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
712 hr_dev->caps.num_mtpts, 1); 576 hr_dev->caps.num_mtpts, 1);
@@ -733,16 +597,35 @@ static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
733 goto err_unmap_qp; 597 goto err_unmap_qp;
734 } 598 }
735 599
600 if (hr_dev->caps.trrl_entry_sz) {
601 ret = hns_roce_init_hem_table(hr_dev,
602 &hr_dev->qp_table.trrl_table,
603 HEM_TYPE_TRRL,
604 hr_dev->caps.trrl_entry_sz *
605 hr_dev->caps.max_qp_dest_rdma,
606 hr_dev->caps.num_qps, 1);
607 if (ret) {
608 dev_err(dev,
609 "Failed to init trrl_table memory, aborting.\n");
610 goto err_unmap_irrl;
611 }
612 }
613
736 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 614 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
737 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 615 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
738 hr_dev->caps.num_cqs, 1); 616 hr_dev->caps.num_cqs, 1);
739 if (ret) { 617 if (ret) {
740 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 618 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
741 goto err_unmap_irrl; 619 goto err_unmap_trrl;
742 } 620 }
743 621
744 return 0; 622 return 0;
745 623
624err_unmap_trrl:
625 if (hr_dev->caps.trrl_entry_sz)
626 hns_roce_cleanup_hem_table(hr_dev,
627 &hr_dev->qp_table.trrl_table);
628
746err_unmap_irrl: 629err_unmap_irrl:
747 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 630 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
748 631
@@ -754,6 +637,12 @@ err_unmap_dmpt:
754 637
755err_unmap_mtt: 638err_unmap_mtt:
756 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table); 639 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
640 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
641 hns_roce_cleanup_hem_table(hr_dev,
642 &hr_dev->mr_table.mtt_cqe_table);
643
644err_unmap_cqe:
645 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
757 646
758 return ret; 647 return ret;
759} 648}
@@ -766,7 +655,7 @@ err_unmap_mtt:
766static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 655static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
767{ 656{
768 int ret; 657 int ret;
769 struct device *dev = &hr_dev->pdev->dev; 658 struct device *dev = hr_dev->dev;
770 659
771 spin_lock_init(&hr_dev->sm_lock); 660 spin_lock_init(&hr_dev->sm_lock);
772 spin_lock_init(&hr_dev->bt_cmd_lock); 661 spin_lock_init(&hr_dev->bt_cmd_lock);
@@ -826,56 +715,45 @@ err_uar_table_free:
826 return ret; 715 return ret;
827} 716}
828 717
829/** 718int hns_roce_init(struct hns_roce_dev *hr_dev)
830 * hns_roce_probe - RoCE driver entrance
831 * @pdev: pointer to platform device
832 * Return : int
833 *
834 */
835static int hns_roce_probe(struct platform_device *pdev)
836{ 719{
837 int ret; 720 int ret;
838 struct hns_roce_dev *hr_dev; 721 struct device *dev = hr_dev->dev;
839 struct device *dev = &pdev->dev;
840
841 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
842 if (!hr_dev)
843 return -ENOMEM;
844
845 hr_dev->pdev = pdev;
846 platform_set_drvdata(pdev, hr_dev);
847 722
848 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) && 723 if (hr_dev->hw->reset) {
849 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) { 724 ret = hr_dev->hw->reset(hr_dev, true);
850 dev_err(dev, "Not usable DMA addressing mode\n"); 725 if (ret) {
851 ret = -EIO; 726 dev_err(dev, "Reset RoCE engine failed!\n");
852 goto error_failed_get_cfg; 727 return ret;
728 }
853 } 729 }
854 730
855 ret = hns_roce_get_cfg(hr_dev); 731 if (hr_dev->hw->cmq_init) {
856 if (ret) { 732 ret = hr_dev->hw->cmq_init(hr_dev);
857 dev_err(dev, "Get Configuration failed!\n"); 733 if (ret) {
858 goto error_failed_get_cfg; 734 dev_err(dev, "Init RoCE Command Queue failed!\n");
735 goto error_failed_cmq_init;
736 }
859 } 737 }
860 738
861 ret = hr_dev->hw->reset(hr_dev, true); 739 ret = hr_dev->hw->hw_profile(hr_dev);
862 if (ret) { 740 if (ret) {
863 dev_err(dev, "Reset RoCE engine failed!\n"); 741 dev_err(dev, "Get RoCE engine profile failed!\n");
864 goto error_failed_get_cfg; 742 goto error_failed_cmd_init;
865 } 743 }
866 744
867 hr_dev->hw->hw_profile(hr_dev);
868
869 ret = hns_roce_cmd_init(hr_dev); 745 ret = hns_roce_cmd_init(hr_dev);
870 if (ret) { 746 if (ret) {
871 dev_err(dev, "cmd init failed!\n"); 747 dev_err(dev, "cmd init failed!\n");
872 goto error_failed_cmd_init; 748 goto error_failed_cmd_init;
873 } 749 }
874 750
875 ret = hns_roce_init_eq_table(hr_dev); 751 if (hr_dev->cmd_mod) {
876 if (ret) { 752 ret = hns_roce_init_eq_table(hr_dev);
877 dev_err(dev, "eq init failed!\n"); 753 if (ret) {
878 goto error_failed_eq_table; 754 dev_err(dev, "eq init failed!\n");
755 goto error_failed_eq_table;
756 }
879 } 757 }
880 758
881 if (hr_dev->cmd_mod) { 759 if (hr_dev->cmd_mod) {
@@ -898,10 +776,12 @@ static int hns_roce_probe(struct platform_device *pdev)
898 goto error_failed_setup_hca; 776 goto error_failed_setup_hca;
899 } 777 }
900 778
901 ret = hr_dev->hw->hw_init(hr_dev); 779 if (hr_dev->hw->hw_init) {
902 if (ret) { 780 ret = hr_dev->hw->hw_init(hr_dev);
903 dev_err(dev, "hw_init failed!\n"); 781 if (ret) {
904 goto error_failed_engine_init; 782 dev_err(dev, "hw_init failed!\n");
783 goto error_failed_engine_init;
784 }
905 } 785 }
906 786
907 ret = hns_roce_register_device(hr_dev); 787 ret = hns_roce_register_device(hr_dev);
@@ -911,7 +791,8 @@ static int hns_roce_probe(struct platform_device *pdev)
911 return 0; 791 return 0;
912 792
913error_failed_register_device: 793error_failed_register_device:
914 hr_dev->hw->hw_exit(hr_dev); 794 if (hr_dev->hw->hw_exit)
795 hr_dev->hw->hw_exit(hr_dev);
915 796
916error_failed_engine_init: 797error_failed_engine_init:
917 hns_roce_cleanup_bitmap(hr_dev); 798 hns_roce_cleanup_bitmap(hr_dev);
@@ -924,58 +805,47 @@ error_failed_init_hem:
924 hns_roce_cmd_use_polling(hr_dev); 805 hns_roce_cmd_use_polling(hr_dev);
925 806
926error_failed_use_event: 807error_failed_use_event:
927 hns_roce_cleanup_eq_table(hr_dev); 808 if (hr_dev->cmd_mod)
809 hns_roce_cleanup_eq_table(hr_dev);
928 810
929error_failed_eq_table: 811error_failed_eq_table:
930 hns_roce_cmd_cleanup(hr_dev); 812 hns_roce_cmd_cleanup(hr_dev);
931 813
932error_failed_cmd_init: 814error_failed_cmd_init:
933 ret = hr_dev->hw->reset(hr_dev, false); 815 if (hr_dev->hw->cmq_exit)
934 if (ret) 816 hr_dev->hw->cmq_exit(hr_dev);
935 dev_err(&hr_dev->pdev->dev, "roce_engine reset fail\n");
936 817
937error_failed_get_cfg: 818error_failed_cmq_init:
938 ib_dealloc_device(&hr_dev->ib_dev); 819 if (hr_dev->hw->reset) {
820 ret = hr_dev->hw->reset(hr_dev, false);
821 if (ret)
822 dev_err(dev, "Dereset RoCE engine failed!\n");
823 }
939 824
940 return ret; 825 return ret;
941} 826}
827EXPORT_SYMBOL_GPL(hns_roce_init);
942 828
943/** 829void hns_roce_exit(struct hns_roce_dev *hr_dev)
944 * hns_roce_remove - remove RoCE device
945 * @pdev: pointer to platform device
946 */
947static int hns_roce_remove(struct platform_device *pdev)
948{ 830{
949 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
950
951 hns_roce_unregister_device(hr_dev); 831 hns_roce_unregister_device(hr_dev);
952 hr_dev->hw->hw_exit(hr_dev); 832 if (hr_dev->hw->hw_exit)
833 hr_dev->hw->hw_exit(hr_dev);
953 hns_roce_cleanup_bitmap(hr_dev); 834 hns_roce_cleanup_bitmap(hr_dev);
954 hns_roce_cleanup_hem(hr_dev); 835 hns_roce_cleanup_hem(hr_dev);
955 836
956 if (hr_dev->cmd_mod) 837 if (hr_dev->cmd_mod)
957 hns_roce_cmd_use_polling(hr_dev); 838 hns_roce_cmd_use_polling(hr_dev);
958 839
959 hns_roce_cleanup_eq_table(hr_dev); 840 if (hr_dev->cmd_mod)
841 hns_roce_cleanup_eq_table(hr_dev);
960 hns_roce_cmd_cleanup(hr_dev); 842 hns_roce_cmd_cleanup(hr_dev);
961 hr_dev->hw->reset(hr_dev, false); 843 if (hr_dev->hw->cmq_exit)
962 844 hr_dev->hw->cmq_exit(hr_dev);
963 ib_dealloc_device(&hr_dev->ib_dev); 845 if (hr_dev->hw->reset)
964 846 hr_dev->hw->reset(hr_dev, false);
965 return 0;
966} 847}
967 848EXPORT_SYMBOL_GPL(hns_roce_exit);
968static struct platform_driver hns_roce_driver = {
969 .probe = hns_roce_probe,
970 .remove = hns_roce_remove,
971 .driver = {
972 .name = DRV_NAME,
973 .of_match_table = hns_roce_of_match,
974 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
975 },
976};
977
978module_platform_driver(hns_roce_driver);
979 849
980MODULE_LICENSE("Dual BSD/GPL"); 850MODULE_LICENSE("Dual BSD/GPL");
981MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 851MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
diff --git a/drivers/infiniband/hw/hns/hns_roce_mr.c b/drivers/infiniband/hw/hns/hns_roce_mr.c
index e387360e3780..da86a8117bd5 100644
--- a/drivers/infiniband/hw/hns/hns_roce_mr.c
+++ b/drivers/infiniband/hw/hns/hns_roce_mr.c
@@ -47,6 +47,7 @@ unsigned long key_to_hw_index(u32 key)
47{ 47{
48 return (key << 24) | (key >> 8); 48 return (key << 24) | (key >> 8);
49} 49}
50EXPORT_SYMBOL_GPL(key_to_hw_index);
50 51
51static int hns_roce_sw2hw_mpt(struct hns_roce_dev *hr_dev, 52static int hns_roce_sw2hw_mpt(struct hns_roce_dev *hr_dev,
52 struct hns_roce_cmd_mailbox *mailbox, 53 struct hns_roce_cmd_mailbox *mailbox,
@@ -65,6 +66,7 @@ int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
65 mpt_index, !mailbox, HNS_ROCE_CMD_HW2SW_MPT, 66 mpt_index, !mailbox, HNS_ROCE_CMD_HW2SW_MPT,
66 HNS_ROCE_CMD_TIMEOUT_MSECS); 67 HNS_ROCE_CMD_TIMEOUT_MSECS);
67} 68}
69EXPORT_SYMBOL_GPL(hns_roce_hw2sw_mpt);
68 70
69static int hns_roce_buddy_alloc(struct hns_roce_buddy *buddy, int order, 71static int hns_roce_buddy_alloc(struct hns_roce_buddy *buddy, int order,
70 unsigned long *seg) 72 unsigned long *seg)
@@ -175,18 +177,28 @@ static void hns_roce_buddy_cleanup(struct hns_roce_buddy *buddy)
175} 177}
176 178
177static int hns_roce_alloc_mtt_range(struct hns_roce_dev *hr_dev, int order, 179static int hns_roce_alloc_mtt_range(struct hns_roce_dev *hr_dev, int order,
178 unsigned long *seg) 180 unsigned long *seg, u32 mtt_type)
179{ 181{
180 struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; 182 struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
181 int ret = 0; 183 struct hns_roce_hem_table *table;
184 struct hns_roce_buddy *buddy;
185 int ret;
186
187 if (mtt_type == MTT_TYPE_WQE) {
188 buddy = &mr_table->mtt_buddy;
189 table = &mr_table->mtt_table;
190 } else {
191 buddy = &mr_table->mtt_cqe_buddy;
192 table = &mr_table->mtt_cqe_table;
193 }
182 194
183 ret = hns_roce_buddy_alloc(&mr_table->mtt_buddy, order, seg); 195 ret = hns_roce_buddy_alloc(buddy, order, seg);
184 if (ret == -1) 196 if (ret == -1)
185 return -1; 197 return -1;
186 198
187 if (hns_roce_table_get_range(hr_dev, &mr_table->mtt_table, *seg, 199 if (hns_roce_table_get_range(hr_dev, table, *seg,
188 *seg + (1 << order) - 1)) { 200 *seg + (1 << order) - 1)) {
189 hns_roce_buddy_free(&mr_table->mtt_buddy, *seg, order); 201 hns_roce_buddy_free(buddy, *seg, order);
190 return -1; 202 return -1;
191 } 203 }
192 204
@@ -196,7 +208,7 @@ static int hns_roce_alloc_mtt_range(struct hns_roce_dev *hr_dev, int order,
196int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift, 208int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
197 struct hns_roce_mtt *mtt) 209 struct hns_roce_mtt *mtt)
198{ 210{
199 int ret = 0; 211 int ret;
200 int i; 212 int i;
201 213
202 /* Page num is zero, correspond to DMA memory register */ 214 /* Page num is zero, correspond to DMA memory register */
@@ -215,7 +227,8 @@ int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
215 ++mtt->order; 227 ++mtt->order;
216 228
217 /* Allocate MTT entry */ 229 /* Allocate MTT entry */
218 ret = hns_roce_alloc_mtt_range(hr_dev, mtt->order, &mtt->first_seg); 230 ret = hns_roce_alloc_mtt_range(hr_dev, mtt->order, &mtt->first_seg,
231 mtt->mtt_type);
219 if (ret == -1) 232 if (ret == -1)
220 return -ENOMEM; 233 return -ENOMEM;
221 234
@@ -229,18 +242,261 @@ void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev, struct hns_roce_mtt *mtt)
229 if (mtt->order < 0) 242 if (mtt->order < 0)
230 return; 243 return;
231 244
232 hns_roce_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order); 245 if (mtt->mtt_type == MTT_TYPE_WQE) {
233 hns_roce_table_put_range(hr_dev, &mr_table->mtt_table, mtt->first_seg, 246 hns_roce_buddy_free(&mr_table->mtt_buddy, mtt->first_seg,
234 mtt->first_seg + (1 << mtt->order) - 1); 247 mtt->order);
248 hns_roce_table_put_range(hr_dev, &mr_table->mtt_table,
249 mtt->first_seg,
250 mtt->first_seg + (1 << mtt->order) - 1);
251 } else {
252 hns_roce_buddy_free(&mr_table->mtt_cqe_buddy, mtt->first_seg,
253 mtt->order);
254 hns_roce_table_put_range(hr_dev, &mr_table->mtt_cqe_table,
255 mtt->first_seg,
256 mtt->first_seg + (1 << mtt->order) - 1);
257 }
258}
259EXPORT_SYMBOL_GPL(hns_roce_mtt_cleanup);
260
261static void hns_roce_loop_free(struct hns_roce_dev *hr_dev,
262 struct hns_roce_mr *mr, int err_loop_index,
263 int loop_i, int loop_j)
264{
265 struct device *dev = hr_dev->dev;
266 u32 mhop_num;
267 u32 pbl_bt_sz;
268 u64 bt_idx;
269 int i, j;
270
271 pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT);
272 mhop_num = hr_dev->caps.pbl_hop_num;
273
274 i = loop_i;
275 if (mhop_num == 3 && err_loop_index == 2) {
276 for (; i >= 0; i--) {
277 dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i],
278 mr->pbl_l1_dma_addr[i]);
279
280 for (j = 0; j < pbl_bt_sz / 8; j++) {
281 if (i == loop_i && j >= loop_j)
282 break;
283
284 bt_idx = i * pbl_bt_sz / 8 + j;
285 dma_free_coherent(dev, pbl_bt_sz,
286 mr->pbl_bt_l2[bt_idx],
287 mr->pbl_l2_dma_addr[bt_idx]);
288 }
289 }
290 } else if (mhop_num == 3 && err_loop_index == 1) {
291 for (i -= 1; i >= 0; i--) {
292 dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i],
293 mr->pbl_l1_dma_addr[i]);
294
295 for (j = 0; j < pbl_bt_sz / 8; j++) {
296 bt_idx = i * pbl_bt_sz / 8 + j;
297 dma_free_coherent(dev, pbl_bt_sz,
298 mr->pbl_bt_l2[bt_idx],
299 mr->pbl_l2_dma_addr[bt_idx]);
300 }
301 }
302 } else if (mhop_num == 2 && err_loop_index == 1) {
303 for (i -= 1; i >= 0; i--)
304 dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i],
305 mr->pbl_l1_dma_addr[i]);
306 } else {
307 dev_warn(dev, "not support: mhop_num=%d, err_loop_index=%d.",
308 mhop_num, err_loop_index);
309 return;
310 }
311
312 dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l0, mr->pbl_l0_dma_addr);
313 mr->pbl_bt_l0 = NULL;
314 mr->pbl_l0_dma_addr = 0;
315}
316
317/* PBL multi hop addressing */
318static int hns_roce_mhop_alloc(struct hns_roce_dev *hr_dev, int npages,
319 struct hns_roce_mr *mr)
320{
321 struct device *dev = hr_dev->dev;
322 int mr_alloc_done = 0;
323 int npages_allocated;
324 int i = 0, j = 0;
325 u32 pbl_bt_sz;
326 u32 mhop_num;
327 u64 pbl_last_bt_num;
328 u64 pbl_bt_cnt = 0;
329 u64 bt_idx;
330 u64 size;
331
332 mhop_num = hr_dev->caps.pbl_hop_num;
333 pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT);
334 pbl_last_bt_num = (npages + pbl_bt_sz / 8 - 1) / (pbl_bt_sz / 8);
335
336 if (mhop_num == HNS_ROCE_HOP_NUM_0)
337 return 0;
338
339 /* hop_num = 1 */
340 if (mhop_num == 1) {
341 if (npages > pbl_bt_sz / 8) {
342 dev_err(dev, "npages %d is larger than buf_pg_sz!",
343 npages);
344 return -EINVAL;
345 }
346 mr->pbl_buf = dma_alloc_coherent(dev, npages * 8,
347 &(mr->pbl_dma_addr),
348 GFP_KERNEL);
349 if (!mr->pbl_buf)
350 return -ENOMEM;
351
352 mr->pbl_size = npages;
353 mr->pbl_ba = mr->pbl_dma_addr;
354 mr->pbl_hop_num = hr_dev->caps.pbl_hop_num;
355 mr->pbl_ba_pg_sz = hr_dev->caps.pbl_ba_pg_sz;
356 mr->pbl_buf_pg_sz = hr_dev->caps.pbl_buf_pg_sz;
357 return 0;
358 }
359
360 mr->pbl_l1_dma_addr = kcalloc(pbl_bt_sz / 8,
361 sizeof(*mr->pbl_l1_dma_addr),
362 GFP_KERNEL);
363 if (!mr->pbl_l1_dma_addr)
364 return -ENOMEM;
365
366 mr->pbl_bt_l1 = kcalloc(pbl_bt_sz / 8, sizeof(*mr->pbl_bt_l1),
367 GFP_KERNEL);
368 if (!mr->pbl_bt_l1)
369 goto err_kcalloc_bt_l1;
370
371 if (mhop_num == 3) {
372 mr->pbl_l2_dma_addr = kcalloc(pbl_last_bt_num,
373 sizeof(*mr->pbl_l2_dma_addr),
374 GFP_KERNEL);
375 if (!mr->pbl_l2_dma_addr)
376 goto err_kcalloc_l2_dma;
377
378 mr->pbl_bt_l2 = kcalloc(pbl_last_bt_num,
379 sizeof(*mr->pbl_bt_l2),
380 GFP_KERNEL);
381 if (!mr->pbl_bt_l2)
382 goto err_kcalloc_bt_l2;
383 }
384
385 /* alloc L0 BT */
386 mr->pbl_bt_l0 = dma_alloc_coherent(dev, pbl_bt_sz,
387 &(mr->pbl_l0_dma_addr),
388 GFP_KERNEL);
389 if (!mr->pbl_bt_l0)
390 goto err_dma_alloc_l0;
391
392 if (mhop_num == 2) {
393 /* alloc L1 BT */
394 for (i = 0; i < pbl_bt_sz / 8; i++) {
395 if (pbl_bt_cnt + 1 < pbl_last_bt_num) {
396 size = pbl_bt_sz;
397 } else {
398 npages_allocated = i * (pbl_bt_sz / 8);
399 size = (npages - npages_allocated) * 8;
400 }
401 mr->pbl_bt_l1[i] = dma_alloc_coherent(dev, size,
402 &(mr->pbl_l1_dma_addr[i]),
403 GFP_KERNEL);
404 if (!mr->pbl_bt_l1[i]) {
405 hns_roce_loop_free(hr_dev, mr, 1, i, 0);
406 goto err_dma_alloc_l0;
407 }
408
409 *(mr->pbl_bt_l0 + i) = mr->pbl_l1_dma_addr[i];
410
411 pbl_bt_cnt++;
412 if (pbl_bt_cnt >= pbl_last_bt_num)
413 break;
414 }
415 } else if (mhop_num == 3) {
416 /* alloc L1, L2 BT */
417 for (i = 0; i < pbl_bt_sz / 8; i++) {
418 mr->pbl_bt_l1[i] = dma_alloc_coherent(dev, pbl_bt_sz,
419 &(mr->pbl_l1_dma_addr[i]),
420 GFP_KERNEL);
421 if (!mr->pbl_bt_l1[i]) {
422 hns_roce_loop_free(hr_dev, mr, 1, i, 0);
423 goto err_dma_alloc_l0;
424 }
425
426 *(mr->pbl_bt_l0 + i) = mr->pbl_l1_dma_addr[i];
427
428 for (j = 0; j < pbl_bt_sz / 8; j++) {
429 bt_idx = i * pbl_bt_sz / 8 + j;
430
431 if (pbl_bt_cnt + 1 < pbl_last_bt_num) {
432 size = pbl_bt_sz;
433 } else {
434 npages_allocated = bt_idx *
435 (pbl_bt_sz / 8);
436 size = (npages - npages_allocated) * 8;
437 }
438 mr->pbl_bt_l2[bt_idx] = dma_alloc_coherent(
439 dev, size,
440 &(mr->pbl_l2_dma_addr[bt_idx]),
441 GFP_KERNEL);
442 if (!mr->pbl_bt_l2[bt_idx]) {
443 hns_roce_loop_free(hr_dev, mr, 2, i, j);
444 goto err_dma_alloc_l0;
445 }
446
447 *(mr->pbl_bt_l1[i] + j) =
448 mr->pbl_l2_dma_addr[bt_idx];
449
450 pbl_bt_cnt++;
451 if (pbl_bt_cnt >= pbl_last_bt_num) {
452 mr_alloc_done = 1;
453 break;
454 }
455 }
456
457 if (mr_alloc_done)
458 break;
459 }
460 }
461
462 mr->l0_chunk_last_num = i + 1;
463 if (mhop_num == 3)
464 mr->l1_chunk_last_num = j + 1;
465
466 mr->pbl_size = npages;
467 mr->pbl_ba = mr->pbl_l0_dma_addr;
468 mr->pbl_hop_num = hr_dev->caps.pbl_hop_num;
469 mr->pbl_ba_pg_sz = hr_dev->caps.pbl_ba_pg_sz;
470 mr->pbl_buf_pg_sz = hr_dev->caps.pbl_buf_pg_sz;
471
472 return 0;
473
474err_dma_alloc_l0:
475 kfree(mr->pbl_bt_l2);
476 mr->pbl_bt_l2 = NULL;
477
478err_kcalloc_bt_l2:
479 kfree(mr->pbl_l2_dma_addr);
480 mr->pbl_l2_dma_addr = NULL;
481
482err_kcalloc_l2_dma:
483 kfree(mr->pbl_bt_l1);
484 mr->pbl_bt_l1 = NULL;
485
486err_kcalloc_bt_l1:
487 kfree(mr->pbl_l1_dma_addr);
488 mr->pbl_l1_dma_addr = NULL;
489
490 return -ENOMEM;
235} 491}
236 492
237static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova, 493static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
238 u64 size, u32 access, int npages, 494 u64 size, u32 access, int npages,
239 struct hns_roce_mr *mr) 495 struct hns_roce_mr *mr)
240{ 496{
497 struct device *dev = hr_dev->dev;
241 unsigned long index = 0; 498 unsigned long index = 0;
242 int ret = 0; 499 int ret = 0;
243 struct device *dev = &hr_dev->pdev->dev;
244 500
245 /* Allocate a key for mr from mr_table */ 501 /* Allocate a key for mr from mr_table */
246 ret = hns_roce_bitmap_alloc(&hr_dev->mr_table.mtpt_bitmap, &index); 502 ret = hns_roce_bitmap_alloc(&hr_dev->mr_table.mtpt_bitmap, &index);
@@ -258,22 +514,117 @@ static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
258 mr->type = MR_TYPE_DMA; 514 mr->type = MR_TYPE_DMA;
259 mr->pbl_buf = NULL; 515 mr->pbl_buf = NULL;
260 mr->pbl_dma_addr = 0; 516 mr->pbl_dma_addr = 0;
517 /* PBL multi-hop addressing parameters */
518 mr->pbl_bt_l2 = NULL;
519 mr->pbl_bt_l1 = NULL;
520 mr->pbl_bt_l0 = NULL;
521 mr->pbl_l2_dma_addr = NULL;
522 mr->pbl_l1_dma_addr = NULL;
523 mr->pbl_l0_dma_addr = 0;
261 } else { 524 } else {
262 mr->type = MR_TYPE_MR; 525 mr->type = MR_TYPE_MR;
263 mr->pbl_buf = dma_alloc_coherent(dev, npages * 8, 526 if (!hr_dev->caps.pbl_hop_num) {
264 &(mr->pbl_dma_addr), 527 mr->pbl_buf = dma_alloc_coherent(dev, npages * 8,
265 GFP_KERNEL); 528 &(mr->pbl_dma_addr),
266 if (!mr->pbl_buf) 529 GFP_KERNEL);
267 return -ENOMEM; 530 if (!mr->pbl_buf)
531 return -ENOMEM;
532 } else {
533 ret = hns_roce_mhop_alloc(hr_dev, npages, mr);
534 }
268 } 535 }
269 536
270 return 0; 537 return ret;
538}
539
540static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev,
541 struct hns_roce_mr *mr)
542{
543 struct device *dev = hr_dev->dev;
544 int npages_allocated;
545 int npages;
546 int i, j;
547 u32 pbl_bt_sz;
548 u32 mhop_num;
549 u64 bt_idx;
550
551 npages = ib_umem_page_count(mr->umem);
552 pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT);
553 mhop_num = hr_dev->caps.pbl_hop_num;
554
555 if (mhop_num == HNS_ROCE_HOP_NUM_0)
556 return;
557
558 /* hop_num = 1 */
559 if (mhop_num == 1) {
560 dma_free_coherent(dev, (unsigned int)(npages * 8),
561 mr->pbl_buf, mr->pbl_dma_addr);
562 return;
563 }
564
565 dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l0,
566 mr->pbl_l0_dma_addr);
567
568 if (mhop_num == 2) {
569 for (i = 0; i < mr->l0_chunk_last_num; i++) {
570 if (i == mr->l0_chunk_last_num - 1) {
571 npages_allocated = i * (pbl_bt_sz / 8);
572
573 dma_free_coherent(dev,
574 (npages - npages_allocated) * 8,
575 mr->pbl_bt_l1[i],
576 mr->pbl_l1_dma_addr[i]);
577
578 break;
579 }
580
581 dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i],
582 mr->pbl_l1_dma_addr[i]);
583 }
584 } else if (mhop_num == 3) {
585 for (i = 0; i < mr->l0_chunk_last_num; i++) {
586 dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i],
587 mr->pbl_l1_dma_addr[i]);
588
589 for (j = 0; j < pbl_bt_sz / 8; j++) {
590 bt_idx = i * (pbl_bt_sz / 8) + j;
591
592 if ((i == mr->l0_chunk_last_num - 1)
593 && j == mr->l1_chunk_last_num - 1) {
594 npages_allocated = bt_idx *
595 (pbl_bt_sz / 8);
596
597 dma_free_coherent(dev,
598 (npages - npages_allocated) * 8,
599 mr->pbl_bt_l2[bt_idx],
600 mr->pbl_l2_dma_addr[bt_idx]);
601
602 break;
603 }
604
605 dma_free_coherent(dev, pbl_bt_sz,
606 mr->pbl_bt_l2[bt_idx],
607 mr->pbl_l2_dma_addr[bt_idx]);
608 }
609 }
610 }
611
612 kfree(mr->pbl_bt_l1);
613 kfree(mr->pbl_l1_dma_addr);
614 mr->pbl_bt_l1 = NULL;
615 mr->pbl_l1_dma_addr = NULL;
616 if (mhop_num == 3) {
617 kfree(mr->pbl_bt_l2);
618 kfree(mr->pbl_l2_dma_addr);
619 mr->pbl_bt_l2 = NULL;
620 mr->pbl_l2_dma_addr = NULL;
621 }
271} 622}
272 623
273static void hns_roce_mr_free(struct hns_roce_dev *hr_dev, 624static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
274 struct hns_roce_mr *mr) 625 struct hns_roce_mr *mr)
275{ 626{
276 struct device *dev = &hr_dev->pdev->dev; 627 struct device *dev = hr_dev->dev;
277 int npages = 0; 628 int npages = 0;
278 int ret; 629 int ret;
279 630
@@ -286,10 +637,18 @@ static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
286 637
287 if (mr->size != ~0ULL) { 638 if (mr->size != ~0ULL) {
288 npages = ib_umem_page_count(mr->umem); 639 npages = ib_umem_page_count(mr->umem);
289 dma_free_coherent(dev, (unsigned int)(npages * 8), mr->pbl_buf, 640
290 mr->pbl_dma_addr); 641 if (!hr_dev->caps.pbl_hop_num)
642 dma_free_coherent(dev, (unsigned int)(npages * 8),
643 mr->pbl_buf, mr->pbl_dma_addr);
644 else
645 hns_roce_mhop_free(hr_dev, mr);
291 } 646 }
292 647
648 if (mr->enabled)
649 hns_roce_table_put(hr_dev, &hr_dev->mr_table.mtpt_table,
650 key_to_hw_index(mr->key));
651
293 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap, 652 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
294 key_to_hw_index(mr->key), BITMAP_NO_RR); 653 key_to_hw_index(mr->key), BITMAP_NO_RR);
295} 654}
@@ -299,7 +658,7 @@ static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
299{ 658{
300 int ret; 659 int ret;
301 unsigned long mtpt_idx = key_to_hw_index(mr->key); 660 unsigned long mtpt_idx = key_to_hw_index(mr->key);
302 struct device *dev = &hr_dev->pdev->dev; 661 struct device *dev = hr_dev->dev;
303 struct hns_roce_cmd_mailbox *mailbox; 662 struct hns_roce_cmd_mailbox *mailbox;
304 struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; 663 struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
305 664
@@ -345,28 +704,44 @@ static int hns_roce_write_mtt_chunk(struct hns_roce_dev *hr_dev,
345 struct hns_roce_mtt *mtt, u32 start_index, 704 struct hns_roce_mtt *mtt, u32 start_index,
346 u32 npages, u64 *page_list) 705 u32 npages, u64 *page_list)
347{ 706{
348 u32 i = 0; 707 struct hns_roce_hem_table *table;
349 __le64 *mtts = NULL;
350 dma_addr_t dma_handle; 708 dma_addr_t dma_handle;
709 __le64 *mtts;
351 u32 s = start_index * sizeof(u64); 710 u32 s = start_index * sizeof(u64);
711 u32 bt_page_size;
712 u32 i;
713
714 if (mtt->mtt_type == MTT_TYPE_WQE)
715 bt_page_size = 1 << (hr_dev->caps.mtt_ba_pg_sz + PAGE_SHIFT);
716 else
717 bt_page_size = 1 << (hr_dev->caps.cqe_ba_pg_sz + PAGE_SHIFT);
352 718
353 /* All MTTs must fit in the same page */ 719 /* All MTTs must fit in the same page */
354 if (start_index / (PAGE_SIZE / sizeof(u64)) != 720 if (start_index / (bt_page_size / sizeof(u64)) !=
355 (start_index + npages - 1) / (PAGE_SIZE / sizeof(u64))) 721 (start_index + npages - 1) / (bt_page_size / sizeof(u64)))
356 return -EINVAL; 722 return -EINVAL;
357 723
358 if (start_index & (HNS_ROCE_MTT_ENTRY_PER_SEG - 1)) 724 if (start_index & (HNS_ROCE_MTT_ENTRY_PER_SEG - 1))
359 return -EINVAL; 725 return -EINVAL;
360 726
361 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table, 727 if (mtt->mtt_type == MTT_TYPE_WQE)
728 table = &hr_dev->mr_table.mtt_table;
729 else
730 table = &hr_dev->mr_table.mtt_cqe_table;
731
732 mtts = hns_roce_table_find(hr_dev, table,
362 mtt->first_seg + s / hr_dev->caps.mtt_entry_sz, 733 mtt->first_seg + s / hr_dev->caps.mtt_entry_sz,
363 &dma_handle); 734 &dma_handle);
364 if (!mtts) 735 if (!mtts)
365 return -ENOMEM; 736 return -ENOMEM;
366 737
367 /* Save page addr, low 12 bits : 0 */ 738 /* Save page addr, low 12 bits : 0 */
368 for (i = 0; i < npages; ++i) 739 for (i = 0; i < npages; ++i) {
369 mtts[i] = (cpu_to_le64(page_list[i])) >> PAGE_ADDR_SHIFT; 740 if (!hr_dev->caps.mtt_hop_num)
741 mtts[i] = cpu_to_le64(page_list[i] >> PAGE_ADDR_SHIFT);
742 else
743 mtts[i] = cpu_to_le64(page_list[i]);
744 }
370 745
371 return 0; 746 return 0;
372} 747}
@@ -377,12 +752,18 @@ static int hns_roce_write_mtt(struct hns_roce_dev *hr_dev,
377{ 752{
378 int chunk; 753 int chunk;
379 int ret; 754 int ret;
755 u32 bt_page_size;
380 756
381 if (mtt->order < 0) 757 if (mtt->order < 0)
382 return -EINVAL; 758 return -EINVAL;
383 759
760 if (mtt->mtt_type == MTT_TYPE_WQE)
761 bt_page_size = 1 << (hr_dev->caps.mtt_ba_pg_sz + PAGE_SHIFT);
762 else
763 bt_page_size = 1 << (hr_dev->caps.cqe_ba_pg_sz + PAGE_SHIFT);
764
384 while (npages > 0) { 765 while (npages > 0) {
385 chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages); 766 chunk = min_t(int, bt_page_size / sizeof(u64), npages);
386 767
387 ret = hns_roce_write_mtt_chunk(hr_dev, mtt, start_index, chunk, 768 ret = hns_roce_write_mtt_chunk(hr_dev, mtt, start_index, chunk,
388 page_list); 769 page_list);
@@ -400,9 +781,9 @@ static int hns_roce_write_mtt(struct hns_roce_dev *hr_dev,
400int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev, 781int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
401 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf) 782 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf)
402{ 783{
403 u32 i = 0; 784 u64 *page_list;
404 int ret = 0; 785 int ret;
405 u64 *page_list = NULL; 786 u32 i;
406 787
407 page_list = kmalloc_array(buf->npages, sizeof(*page_list), GFP_KERNEL); 788 page_list = kmalloc_array(buf->npages, sizeof(*page_list), GFP_KERNEL);
408 if (!page_list) 789 if (!page_list)
@@ -425,7 +806,7 @@ int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
425int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev) 806int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev)
426{ 807{
427 struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; 808 struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
428 int ret = 0; 809 int ret;
429 810
430 ret = hns_roce_bitmap_init(&mr_table->mtpt_bitmap, 811 ret = hns_roce_bitmap_init(&mr_table->mtpt_bitmap,
431 hr_dev->caps.num_mtpts, 812 hr_dev->caps.num_mtpts,
@@ -439,8 +820,17 @@ int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev)
439 if (ret) 820 if (ret)
440 goto err_buddy; 821 goto err_buddy;
441 822
823 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
824 ret = hns_roce_buddy_init(&mr_table->mtt_cqe_buddy,
825 ilog2(hr_dev->caps.num_cqe_segs));
826 if (ret)
827 goto err_buddy_cqe;
828 }
442 return 0; 829 return 0;
443 830
831err_buddy_cqe:
832 hns_roce_buddy_cleanup(&mr_table->mtt_buddy);
833
444err_buddy: 834err_buddy:
445 hns_roce_bitmap_cleanup(&mr_table->mtpt_bitmap); 835 hns_roce_bitmap_cleanup(&mr_table->mtpt_bitmap);
446 return ret; 836 return ret;
@@ -451,13 +841,15 @@ void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev)
451 struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; 841 struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
452 842
453 hns_roce_buddy_cleanup(&mr_table->mtt_buddy); 843 hns_roce_buddy_cleanup(&mr_table->mtt_buddy);
844 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
845 hns_roce_buddy_cleanup(&mr_table->mtt_cqe_buddy);
454 hns_roce_bitmap_cleanup(&mr_table->mtpt_bitmap); 846 hns_roce_bitmap_cleanup(&mr_table->mtpt_bitmap);
455} 847}
456 848
457struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc) 849struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc)
458{ 850{
459 int ret = 0; 851 struct hns_roce_mr *mr;
460 struct hns_roce_mr *mr = NULL; 852 int ret;
461 853
462 mr = kmalloc(sizeof(*mr), GFP_KERNEL); 854 mr = kmalloc(sizeof(*mr), GFP_KERNEL);
463 if (mr == NULL) 855 if (mr == NULL)
@@ -489,25 +881,44 @@ err_free:
489int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev, 881int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
490 struct hns_roce_mtt *mtt, struct ib_umem *umem) 882 struct hns_roce_mtt *mtt, struct ib_umem *umem)
491{ 883{
884 struct device *dev = hr_dev->dev;
492 struct scatterlist *sg; 885 struct scatterlist *sg;
886 unsigned int order;
493 int i, k, entry; 887 int i, k, entry;
888 int npage = 0;
494 int ret = 0; 889 int ret = 0;
890 int len;
891 u64 page_addr;
495 u64 *pages; 892 u64 *pages;
893 u32 bt_page_size;
496 u32 n; 894 u32 n;
497 int len;
498 895
499 pages = (u64 *) __get_free_page(GFP_KERNEL); 896 order = mtt->mtt_type == MTT_TYPE_WQE ? hr_dev->caps.mtt_ba_pg_sz :
897 hr_dev->caps.cqe_ba_pg_sz;
898 bt_page_size = 1 << (order + PAGE_SHIFT);
899
900 pages = (u64 *) __get_free_pages(GFP_KERNEL, order);
500 if (!pages) 901 if (!pages)
501 return -ENOMEM; 902 return -ENOMEM;
502 903
503 i = n = 0; 904 i = n = 0;
504 905
505 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) { 906 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
506 len = sg_dma_len(sg) >> mtt->page_shift; 907 len = sg_dma_len(sg) >> PAGE_SHIFT;
507 for (k = 0; k < len; ++k) { 908 for (k = 0; k < len; ++k) {
508 pages[i++] = sg_dma_address(sg) + 909 page_addr =
509 (k << umem->page_shift); 910 sg_dma_address(sg) + (k << umem->page_shift);
510 if (i == PAGE_SIZE / sizeof(u64)) { 911 if (!(npage % (1 << (mtt->page_shift - PAGE_SHIFT)))) {
912 if (page_addr & ((1 << mtt->page_shift) - 1)) {
913 dev_err(dev, "page_addr 0x%llx is not page_shift %d alignment!\n",
914 page_addr, mtt->page_shift);
915 ret = -EINVAL;
916 goto out;
917 }
918 pages[i++] = page_addr;
919 }
920 npage++;
921 if (i == bt_page_size / sizeof(u64)) {
511 ret = hns_roce_write_mtt(hr_dev, mtt, n, i, 922 ret = hns_roce_write_mtt(hr_dev, mtt, n, i,
512 pages); 923 pages);
513 if (ret) 924 if (ret)
@@ -526,16 +937,44 @@ out:
526 return ret; 937 return ret;
527} 938}
528 939
529static int hns_roce_ib_umem_write_mr(struct hns_roce_mr *mr, 940static int hns_roce_ib_umem_write_mr(struct hns_roce_dev *hr_dev,
941 struct hns_roce_mr *mr,
530 struct ib_umem *umem) 942 struct ib_umem *umem)
531{ 943{
532 int i = 0;
533 int entry;
534 struct scatterlist *sg; 944 struct scatterlist *sg;
945 int i = 0, j = 0, k;
946 int entry;
947 int len;
948 u64 page_addr;
949 u32 pbl_bt_sz;
950
951 if (hr_dev->caps.pbl_hop_num == HNS_ROCE_HOP_NUM_0)
952 return 0;
535 953
954 pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT);
536 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) { 955 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
537 mr->pbl_buf[i] = ((u64)sg_dma_address(sg)) >> 12; 956 len = sg_dma_len(sg) >> PAGE_SHIFT;
538 i++; 957 for (k = 0; k < len; ++k) {
958 page_addr = sg_dma_address(sg) +
959 (k << umem->page_shift);
960
961 if (!hr_dev->caps.pbl_hop_num) {
962 mr->pbl_buf[i++] = page_addr >> 12;
963 } else if (hr_dev->caps.pbl_hop_num == 1) {
964 mr->pbl_buf[i++] = page_addr;
965 } else {
966 if (hr_dev->caps.pbl_hop_num == 2)
967 mr->pbl_bt_l1[i][j] = page_addr;
968 else if (hr_dev->caps.pbl_hop_num == 3)
969 mr->pbl_bt_l2[i][j] = page_addr;
970
971 j++;
972 if (j >= (pbl_bt_sz / 8)) {
973 i++;
974 j = 0;
975 }
976 }
977 }
539 } 978 }
540 979
541 /* Memory barrier */ 980 /* Memory barrier */
@@ -549,10 +988,12 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
549 struct ib_udata *udata) 988 struct ib_udata *udata)
550{ 989{
551 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); 990 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
552 struct device *dev = &hr_dev->pdev->dev; 991 struct device *dev = hr_dev->dev;
553 struct hns_roce_mr *mr = NULL; 992 struct hns_roce_mr *mr;
554 int ret = 0; 993 int bt_size;
555 int n = 0; 994 int ret;
995 int n;
996 int i;
556 997
557 mr = kmalloc(sizeof(*mr), GFP_KERNEL); 998 mr = kmalloc(sizeof(*mr), GFP_KERNEL);
558 if (!mr) 999 if (!mr)
@@ -573,11 +1014,27 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
573 goto err_umem; 1014 goto err_umem;
574 } 1015 }
575 1016
576 if (n > HNS_ROCE_MAX_MTPT_PBL_NUM) { 1017 if (!hr_dev->caps.pbl_hop_num) {
577 dev_err(dev, " MR len %lld err. MR is limited to 4G at most!\n", 1018 if (n > HNS_ROCE_MAX_MTPT_PBL_NUM) {
578 length); 1019 dev_err(dev,
579 ret = -EINVAL; 1020 " MR len %lld err. MR is limited to 4G at most!\n",
580 goto err_umem; 1021 length);
1022 ret = -EINVAL;
1023 goto err_umem;
1024 }
1025 } else {
1026 int pbl_size = 1;
1027
1028 bt_size = (1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT)) / 8;
1029 for (i = 0; i < hr_dev->caps.pbl_hop_num; i++)
1030 pbl_size *= bt_size;
1031 if (n > pbl_size) {
1032 dev_err(dev,
1033 " MR len %lld err. MR page num is limited to %d!\n",
1034 length, pbl_size);
1035 ret = -EINVAL;
1036 goto err_umem;
1037 }
581 } 1038 }
582 1039
583 ret = hns_roce_mr_alloc(hr_dev, to_hr_pd(pd)->pdn, virt_addr, length, 1040 ret = hns_roce_mr_alloc(hr_dev, to_hr_pd(pd)->pdn, virt_addr, length,
@@ -585,7 +1042,7 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
585 if (ret) 1042 if (ret)
586 goto err_umem; 1043 goto err_umem;
587 1044
588 ret = hns_roce_ib_umem_write_mr(mr, mr->umem); 1045 ret = hns_roce_ib_umem_write_mr(hr_dev, mr, mr->umem);
589 if (ret) 1046 if (ret)
590 goto err_mr; 1047 goto err_mr;
591 1048
@@ -608,6 +1065,129 @@ err_free:
608 return ERR_PTR(ret); 1065 return ERR_PTR(ret);
609} 1066}
610 1067
1068int hns_roce_rereg_user_mr(struct ib_mr *ibmr, int flags, u64 start, u64 length,
1069 u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
1070 struct ib_udata *udata)
1071{
1072 struct hns_roce_dev *hr_dev = to_hr_dev(ibmr->device);
1073 struct hns_roce_mr *mr = to_hr_mr(ibmr);
1074 struct hns_roce_cmd_mailbox *mailbox;
1075 struct device *dev = hr_dev->dev;
1076 unsigned long mtpt_idx;
1077 u32 pdn = 0;
1078 int npages;
1079 int ret;
1080
1081 if (!mr->enabled)
1082 return -EINVAL;
1083
1084 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1085 if (IS_ERR(mailbox))
1086 return PTR_ERR(mailbox);
1087
1088 mtpt_idx = key_to_hw_index(mr->key) & (hr_dev->caps.num_mtpts - 1);
1089 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, mtpt_idx, 0,
1090 HNS_ROCE_CMD_QUERY_MPT,
1091 HNS_ROCE_CMD_TIMEOUT_MSECS);
1092 if (ret)
1093 goto free_cmd_mbox;
1094
1095 ret = hns_roce_hw2sw_mpt(hr_dev, NULL, mtpt_idx);
1096 if (ret)
1097 dev_warn(dev, "HW2SW_MPT failed (%d)\n", ret);
1098
1099 mr->enabled = 0;
1100
1101 if (flags & IB_MR_REREG_PD)
1102 pdn = to_hr_pd(pd)->pdn;
1103
1104 if (flags & IB_MR_REREG_TRANS) {
1105 if (mr->size != ~0ULL) {
1106 npages = ib_umem_page_count(mr->umem);
1107
1108 if (hr_dev->caps.pbl_hop_num)
1109 hns_roce_mhop_free(hr_dev, mr);
1110 else
1111 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1112 mr->pbl_dma_addr);
1113 }
1114 ib_umem_release(mr->umem);
1115
1116 mr->umem = ib_umem_get(ibmr->uobject->context, start, length,
1117 mr_access_flags, 0);
1118 if (IS_ERR(mr->umem)) {
1119 ret = PTR_ERR(mr->umem);
1120 mr->umem = NULL;
1121 goto free_cmd_mbox;
1122 }
1123 npages = ib_umem_page_count(mr->umem);
1124
1125 if (hr_dev->caps.pbl_hop_num) {
1126 ret = hns_roce_mhop_alloc(hr_dev, npages, mr);
1127 if (ret)
1128 goto release_umem;
1129 } else {
1130 mr->pbl_buf = dma_alloc_coherent(dev, npages * 8,
1131 &(mr->pbl_dma_addr),
1132 GFP_KERNEL);
1133 if (!mr->pbl_buf) {
1134 ret = -ENOMEM;
1135 goto release_umem;
1136 }
1137 }
1138 }
1139
1140 ret = hr_dev->hw->rereg_write_mtpt(hr_dev, mr, flags, pdn,
1141 mr_access_flags, virt_addr,
1142 length, mailbox->buf);
1143 if (ret) {
1144 if (flags & IB_MR_REREG_TRANS)
1145 goto release_umem;
1146 else
1147 goto free_cmd_mbox;
1148 }
1149
1150 if (flags & IB_MR_REREG_TRANS) {
1151 ret = hns_roce_ib_umem_write_mr(hr_dev, mr, mr->umem);
1152 if (ret) {
1153 if (mr->size != ~0ULL) {
1154 npages = ib_umem_page_count(mr->umem);
1155
1156 if (hr_dev->caps.pbl_hop_num)
1157 hns_roce_mhop_free(hr_dev, mr);
1158 else
1159 dma_free_coherent(dev, npages * 8,
1160 mr->pbl_buf,
1161 mr->pbl_dma_addr);
1162 }
1163
1164 goto release_umem;
1165 }
1166 }
1167
1168 ret = hns_roce_sw2hw_mpt(hr_dev, mailbox, mtpt_idx);
1169 if (ret) {
1170 dev_err(dev, "SW2HW_MPT failed (%d)\n", ret);
1171 goto release_umem;
1172 }
1173
1174 mr->enabled = 1;
1175 if (flags & IB_MR_REREG_ACCESS)
1176 mr->access = mr_access_flags;
1177
1178 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1179
1180 return 0;
1181
1182release_umem:
1183 ib_umem_release(mr->umem);
1184
1185free_cmd_mbox:
1186 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1187
1188 return ret;
1189}
1190
611int hns_roce_dereg_mr(struct ib_mr *ibmr) 1191int hns_roce_dereg_mr(struct ib_mr *ibmr)
612{ 1192{
613 struct hns_roce_dev *hr_dev = to_hr_dev(ibmr->device); 1193 struct hns_roce_dev *hr_dev = to_hr_dev(ibmr->device);
diff --git a/drivers/infiniband/hw/hns/hns_roce_pd.c b/drivers/infiniband/hw/hns/hns_roce_pd.c
index a64500fa1145..bdab2188c04a 100644
--- a/drivers/infiniband/hw/hns/hns_roce_pd.c
+++ b/drivers/infiniband/hw/hns/hns_roce_pd.c
@@ -31,6 +31,7 @@
31 */ 31 */
32 32
33#include <linux/platform_device.h> 33#include <linux/platform_device.h>
34#include <linux/pci.h>
34#include "hns_roce_device.h" 35#include "hns_roce_device.h"
35 36
36static int hns_roce_pd_alloc(struct hns_roce_dev *hr_dev, unsigned long *pdn) 37static int hns_roce_pd_alloc(struct hns_roce_dev *hr_dev, unsigned long *pdn)
@@ -60,7 +61,7 @@ struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
60 struct ib_udata *udata) 61 struct ib_udata *udata)
61{ 62{
62 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 63 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
63 struct device *dev = &hr_dev->pdev->dev; 64 struct device *dev = hr_dev->dev;
64 struct hns_roce_pd *pd; 65 struct hns_roce_pd *pd;
65 int ret; 66 int ret;
66 67
@@ -86,6 +87,7 @@ struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
86 87
87 return &pd->ibpd; 88 return &pd->ibpd;
88} 89}
90EXPORT_SYMBOL_GPL(hns_roce_alloc_pd);
89 91
90int hns_roce_dealloc_pd(struct ib_pd *pd) 92int hns_roce_dealloc_pd(struct ib_pd *pd)
91{ 93{
@@ -94,6 +96,7 @@ int hns_roce_dealloc_pd(struct ib_pd *pd)
94 96
95 return 0; 97 return 0;
96} 98}
99EXPORT_SYMBOL_GPL(hns_roce_dealloc_pd);
97 100
98int hns_roce_uar_alloc(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar) 101int hns_roce_uar_alloc(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar)
99{ 102{
@@ -109,12 +112,17 @@ int hns_roce_uar_alloc(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar)
109 uar->index = (uar->index - 1) % 112 uar->index = (uar->index - 1) %
110 (hr_dev->caps.phy_num_uars - 1) + 1; 113 (hr_dev->caps.phy_num_uars - 1) + 1;
111 114
112 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0); 115 if (!dev_is_pci(hr_dev->dev)) {
113 if (!res) { 116 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
114 dev_err(&hr_dev->pdev->dev, "memory resource not found!\n"); 117 if (!res) {
115 return -EINVAL; 118 dev_err(&hr_dev->pdev->dev, "memory resource not found!\n");
119 return -EINVAL;
120 }
121 uar->pfn = ((res->start) >> PAGE_SHIFT) + uar->index;
122 } else {
123 uar->pfn = ((pci_resource_start(hr_dev->pci_dev, 2))
124 >> PAGE_SHIFT);
116 } 125 }
117 uar->pfn = ((res->start) >> PAGE_SHIFT) + uar->index;
118 126
119 return 0; 127 return 0;
120} 128}
diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c
index f5dd21c2d275..49586ec8126a 100644
--- a/drivers/infiniband/hw/hns/hns_roce_qp.c
+++ b/drivers/infiniband/hw/hns/hns_roce_qp.c
@@ -44,7 +44,7 @@
44void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) 44void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
45{ 45{
46 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 46 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
47 struct device *dev = &hr_dev->pdev->dev; 47 struct device *dev = hr_dev->dev;
48 struct hns_roce_qp *qp; 48 struct hns_roce_qp *qp;
49 49
50 spin_lock(&qp_table->lock); 50 spin_lock(&qp_table->lock);
@@ -136,6 +136,7 @@ enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state)
136 return HNS_ROCE_QP_NUM_STATE; 136 return HNS_ROCE_QP_NUM_STATE;
137 } 137 }
138} 138}
139EXPORT_SYMBOL_GPL(to_hns_roce_state);
139 140
140static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn, 141static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
141 struct hns_roce_qp *hr_qp) 142 struct hns_roce_qp *hr_qp)
@@ -153,7 +154,7 @@ static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
153 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp); 154 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
154 spin_unlock_irq(&qp_table->lock); 155 spin_unlock_irq(&qp_table->lock);
155 if (ret) { 156 if (ret) {
156 dev_err(&hr_dev->pdev->dev, "QPC radix_tree_insert failed\n"); 157 dev_err(hr_dev->dev, "QPC radix_tree_insert failed\n");
157 goto err_put_irrl; 158 goto err_put_irrl;
158 } 159 }
159 160
@@ -171,7 +172,7 @@ static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
171 struct hns_roce_qp *hr_qp) 172 struct hns_roce_qp *hr_qp)
172{ 173{
173 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 174 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
174 struct device *dev = &hr_dev->pdev->dev; 175 struct device *dev = hr_dev->dev;
175 int ret; 176 int ret;
176 177
177 if (!qpn) 178 if (!qpn)
@@ -193,13 +194,23 @@ static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
193 goto err_put_qp; 194 goto err_put_qp;
194 } 195 }
195 196
197 if (hr_dev->caps.trrl_entry_sz) {
198 /* Alloc memory for TRRL */
199 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
200 hr_qp->qpn);
201 if (ret) {
202 dev_err(dev, "TRRL table get failed\n");
203 goto err_put_irrl;
204 }
205 }
206
196 spin_lock_irq(&qp_table->lock); 207 spin_lock_irq(&qp_table->lock);
197 ret = radix_tree_insert(&hr_dev->qp_table_tree, 208 ret = radix_tree_insert(&hr_dev->qp_table_tree,
198 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp); 209 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
199 spin_unlock_irq(&qp_table->lock); 210 spin_unlock_irq(&qp_table->lock);
200 if (ret) { 211 if (ret) {
201 dev_err(dev, "QPC radix_tree_insert failed\n"); 212 dev_err(dev, "QPC radix_tree_insert failed\n");
202 goto err_put_irrl; 213 goto err_put_trrl;
203 } 214 }
204 215
205 atomic_set(&hr_qp->refcount, 1); 216 atomic_set(&hr_qp->refcount, 1);
@@ -207,6 +218,10 @@ static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
207 218
208 return 0; 219 return 0;
209 220
221err_put_trrl:
222 if (hr_dev->caps.trrl_entry_sz)
223 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
224
210err_put_irrl: 225err_put_irrl:
211 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 226 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
212 227
@@ -227,6 +242,7 @@ void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
227 hr_qp->qpn & (hr_dev->caps.num_qps - 1)); 242 hr_qp->qpn & (hr_dev->caps.num_qps - 1));
228 spin_unlock_irqrestore(&qp_table->lock, flags); 243 spin_unlock_irqrestore(&qp_table->lock, flags);
229} 244}
245EXPORT_SYMBOL_GPL(hns_roce_qp_remove);
230 246
231void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 247void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
232{ 248{
@@ -237,10 +253,14 @@ void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
237 wait_for_completion(&hr_qp->free); 253 wait_for_completion(&hr_qp->free);
238 254
239 if ((hr_qp->ibqp.qp_type) != IB_QPT_GSI) { 255 if ((hr_qp->ibqp.qp_type) != IB_QPT_GSI) {
256 if (hr_dev->caps.trrl_entry_sz)
257 hns_roce_table_put(hr_dev, &qp_table->trrl_table,
258 hr_qp->qpn);
240 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 259 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
241 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); 260 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
242 } 261 }
243} 262}
263EXPORT_SYMBOL_GPL(hns_roce_qp_free);
244 264
245void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn, 265void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
246 int cnt) 266 int cnt)
@@ -252,13 +272,14 @@ void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
252 272
253 hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR); 273 hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR);
254} 274}
275EXPORT_SYMBOL_GPL(hns_roce_release_range_qp);
255 276
256static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev, 277static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
257 struct ib_qp_cap *cap, int is_user, int has_srq, 278 struct ib_qp_cap *cap, int is_user, int has_srq,
258 struct hns_roce_qp *hr_qp) 279 struct hns_roce_qp *hr_qp)
259{ 280{
281 struct device *dev = hr_dev->dev;
260 u32 max_cnt; 282 u32 max_cnt;
261 struct device *dev = &hr_dev->pdev->dev;
262 283
263 /* Check the validity of QP support capacity */ 284 /* Check the validity of QP support capacity */
264 if (cap->max_recv_wr > hr_dev->caps.max_wqes || 285 if (cap->max_recv_wr > hr_dev->caps.max_wqes ||
@@ -282,20 +303,27 @@ static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
282 return -EINVAL; 303 return -EINVAL;
283 } 304 }
284 305
285 /* In v1 engine, parameter verification procession */ 306 if (hr_dev->caps.min_wqes)
286 max_cnt = cap->max_recv_wr > HNS_ROCE_MIN_WQE_NUM ? 307 max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes);
287 cap->max_recv_wr : HNS_ROCE_MIN_WQE_NUM; 308 else
309 max_cnt = cap->max_recv_wr;
310
288 hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt); 311 hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt);
289 312
290 if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) { 313 if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) {
291 dev_err(dev, "hns_roce_set_rq_size rq.wqe_cnt too large\n"); 314 dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n");
292 return -EINVAL; 315 return -EINVAL;
293 } 316 }
294 317
295 max_cnt = max(1U, cap->max_recv_sge); 318 max_cnt = max(1U, cap->max_recv_sge);
296 hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt); 319 hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt);
297 /* WQE is fixed for 64B */ 320 if (hr_dev->caps.max_rq_sg <= 2)
298 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz); 321 hr_qp->rq.wqe_shift =
322 ilog2(hr_dev->caps.max_rq_desc_sz);
323 else
324 hr_qp->rq.wqe_shift =
325 ilog2(hr_dev->caps.max_rq_desc_sz
326 * hr_qp->rq.max_gs);
299 } 327 }
300 328
301 cap->max_recv_wr = hr_qp->rq.max_post = hr_qp->rq.wqe_cnt; 329 cap->max_recv_wr = hr_qp->rq.max_post = hr_qp->rq.wqe_cnt;
@@ -305,32 +333,79 @@ static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
305} 333}
306 334
307static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev, 335static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev,
336 struct ib_qp_cap *cap,
308 struct hns_roce_qp *hr_qp, 337 struct hns_roce_qp *hr_qp,
309 struct hns_roce_ib_create_qp *ucmd) 338 struct hns_roce_ib_create_qp *ucmd)
310{ 339{
311 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz); 340 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz);
312 u8 max_sq_stride = ilog2(roundup_sq_stride); 341 u8 max_sq_stride = ilog2(roundup_sq_stride);
342 u32 page_size;
343 u32 max_cnt;
313 344
314 /* Sanity check SQ size before proceeding */ 345 /* Sanity check SQ size before proceeding */
315 if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes || 346 if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes ||
316 ucmd->log_sq_stride > max_sq_stride || 347 ucmd->log_sq_stride > max_sq_stride ||
317 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) { 348 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
318 dev_err(&hr_dev->pdev->dev, "check SQ size error!\n"); 349 dev_err(hr_dev->dev, "check SQ size error!\n");
350 return -EINVAL;
351 }
352
353 if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
354 dev_err(hr_dev->dev, "SQ sge error! max_send_sge=%d\n",
355 cap->max_send_sge);
319 return -EINVAL; 356 return -EINVAL;
320 } 357 }
321 358
322 hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 359 hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
323 hr_qp->sq.wqe_shift = ucmd->log_sq_stride; 360 hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
324 361
362 max_cnt = max(1U, cap->max_send_sge);
363 if (hr_dev->caps.max_sq_sg <= 2)
364 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
365 else
366 hr_qp->sq.max_gs = max_cnt;
367
368 if (hr_qp->sq.max_gs > 2)
369 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
370 (hr_qp->sq.max_gs - 2));
371 hr_qp->sge.sge_shift = 4;
372
325 /* Get buf size, SQ and RQ are aligned to page_szie */ 373 /* Get buf size, SQ and RQ are aligned to page_szie */
326 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << 374 if (hr_dev->caps.max_sq_sg <= 2) {
375 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
327 hr_qp->rq.wqe_shift), PAGE_SIZE) + 376 hr_qp->rq.wqe_shift), PAGE_SIZE) +
328 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 377 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
329 hr_qp->sq.wqe_shift), PAGE_SIZE); 378 hr_qp->sq.wqe_shift), PAGE_SIZE);
330 379
331 hr_qp->sq.offset = 0; 380 hr_qp->sq.offset = 0;
332 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 381 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
333 hr_qp->sq.wqe_shift), PAGE_SIZE); 382 hr_qp->sq.wqe_shift), PAGE_SIZE);
383 } else {
384 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
385 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
386 hr_qp->rq.wqe_shift), page_size) +
387 HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
388 hr_qp->sge.sge_shift), page_size) +
389 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
390 hr_qp->sq.wqe_shift), page_size);
391
392 hr_qp->sq.offset = 0;
393 if (hr_qp->sge.sge_cnt) {
394 hr_qp->sge.offset = HNS_ROCE_ALOGN_UP(
395 (hr_qp->sq.wqe_cnt <<
396 hr_qp->sq.wqe_shift),
397 page_size);
398 hr_qp->rq.offset = hr_qp->sge.offset +
399 HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
400 hr_qp->sge.sge_shift),
401 page_size);
402 } else {
403 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP(
404 (hr_qp->sq.wqe_cnt <<
405 hr_qp->sq.wqe_shift),
406 page_size);
407 }
408 }
334 409
335 return 0; 410 return 0;
336} 411}
@@ -339,13 +414,15 @@ static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev,
339 struct ib_qp_cap *cap, 414 struct ib_qp_cap *cap,
340 struct hns_roce_qp *hr_qp) 415 struct hns_roce_qp *hr_qp)
341{ 416{
342 struct device *dev = &hr_dev->pdev->dev; 417 struct device *dev = hr_dev->dev;
418 u32 page_size;
343 u32 max_cnt; 419 u32 max_cnt;
420 int size;
344 421
345 if (cap->max_send_wr > hr_dev->caps.max_wqes || 422 if (cap->max_send_wr > hr_dev->caps.max_wqes ||
346 cap->max_send_sge > hr_dev->caps.max_sq_sg || 423 cap->max_send_sge > hr_dev->caps.max_sq_sg ||
347 cap->max_inline_data > hr_dev->caps.max_sq_inline) { 424 cap->max_inline_data > hr_dev->caps.max_sq_inline) {
348 dev_err(dev, "hns_roce_set_kernel_sq_size error1\n"); 425 dev_err(dev, "SQ WR or sge or inline data error!\n");
349 return -EINVAL; 426 return -EINVAL;
350 } 427 }
351 428
@@ -353,27 +430,46 @@ static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev,
353 hr_qp->sq_max_wqes_per_wr = 1; 430 hr_qp->sq_max_wqes_per_wr = 1;
354 hr_qp->sq_spare_wqes = 0; 431 hr_qp->sq_spare_wqes = 0;
355 432
356 /* In v1 engine, parameter verification procession */ 433 if (hr_dev->caps.min_wqes)
357 max_cnt = cap->max_send_wr > HNS_ROCE_MIN_WQE_NUM ? 434 max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes);
358 cap->max_send_wr : HNS_ROCE_MIN_WQE_NUM; 435 else
436 max_cnt = cap->max_send_wr;
437
359 hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt); 438 hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt);
360 if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) { 439 if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) {
361 dev_err(dev, "hns_roce_set_kernel_sq_size sq.wqe_cnt too large\n"); 440 dev_err(dev, "while setting kernel sq size, sq.wqe_cnt too large\n");
362 return -EINVAL; 441 return -EINVAL;
363 } 442 }
364 443
365 /* Get data_seg numbers */ 444 /* Get data_seg numbers */
366 max_cnt = max(1U, cap->max_send_sge); 445 max_cnt = max(1U, cap->max_send_sge);
367 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt); 446 if (hr_dev->caps.max_sq_sg <= 2)
447 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
448 else
449 hr_qp->sq.max_gs = max_cnt;
368 450
369 /* Get buf size, SQ and RQ are aligned to page_szie */ 451 if (hr_qp->sq.max_gs > 2) {
370 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << 452 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
371 hr_qp->rq.wqe_shift), PAGE_SIZE) + 453 (hr_qp->sq.max_gs - 2));
372 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 454 hr_qp->sge.sge_shift = 4;
373 hr_qp->sq.wqe_shift), PAGE_SIZE); 455 }
456
457 /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */
458 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
374 hr_qp->sq.offset = 0; 459 hr_qp->sq.offset = 0;
375 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 460 size = HNS_ROCE_ALOGN_UP(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift,
376 hr_qp->sq.wqe_shift), PAGE_SIZE); 461 page_size);
462
463 if (hr_dev->caps.max_sq_sg > 2 && hr_qp->sge.sge_cnt) {
464 hr_qp->sge.offset = size;
465 size += HNS_ROCE_ALOGN_UP(hr_qp->sge.sge_cnt <<
466 hr_qp->sge.sge_shift, page_size);
467 }
468
469 hr_qp->rq.offset = size;
470 size += HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift),
471 page_size);
472 hr_qp->buff_size = size;
377 473
378 /* Get wr and sge number which send */ 474 /* Get wr and sge number which send */
379 cap->max_send_wr = hr_qp->sq.max_post = hr_qp->sq.wqe_cnt; 475 cap->max_send_wr = hr_qp->sq.max_post = hr_qp->sq.wqe_cnt;
@@ -391,10 +487,12 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
391 struct ib_udata *udata, unsigned long sqpn, 487 struct ib_udata *udata, unsigned long sqpn,
392 struct hns_roce_qp *hr_qp) 488 struct hns_roce_qp *hr_qp)
393{ 489{
394 struct device *dev = &hr_dev->pdev->dev; 490 struct device *dev = hr_dev->dev;
395 struct hns_roce_ib_create_qp ucmd; 491 struct hns_roce_ib_create_qp ucmd;
396 unsigned long qpn = 0; 492 unsigned long qpn = 0;
397 int ret = 0; 493 int ret = 0;
494 u32 page_shift;
495 u32 npages;
398 496
399 mutex_init(&hr_qp->mutex); 497 mutex_init(&hr_qp->mutex);
400 spin_lock_init(&hr_qp->sq.lock); 498 spin_lock_init(&hr_qp->sq.lock);
@@ -421,7 +519,8 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
421 goto err_out; 519 goto err_out;
422 } 520 }
423 521
424 ret = hns_roce_set_user_sq_size(hr_dev, hr_qp, &ucmd); 522 ret = hns_roce_set_user_sq_size(hr_dev, &init_attr->cap, hr_qp,
523 &ucmd);
425 if (ret) { 524 if (ret) {
426 dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n"); 525 dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n");
427 goto err_out; 526 goto err_out;
@@ -436,8 +535,21 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
436 goto err_out; 535 goto err_out;
437 } 536 }
438 537
439 ret = hns_roce_mtt_init(hr_dev, ib_umem_page_count(hr_qp->umem), 538 hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
440 hr_qp->umem->page_shift, &hr_qp->mtt); 539 if (hr_dev->caps.mtt_buf_pg_sz) {
540 npages = (ib_umem_page_count(hr_qp->umem) +
541 (1 << hr_dev->caps.mtt_buf_pg_sz) - 1) /
542 (1 << hr_dev->caps.mtt_buf_pg_sz);
543 page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
544 ret = hns_roce_mtt_init(hr_dev, npages,
545 page_shift,
546 &hr_qp->mtt);
547 } else {
548 ret = hns_roce_mtt_init(hr_dev,
549 ib_umem_page_count(hr_qp->umem),
550 hr_qp->umem->page_shift,
551 &hr_qp->mtt);
552 }
441 if (ret) { 553 if (ret) {
442 dev_err(dev, "hns_roce_mtt_init error for create qp\n"); 554 dev_err(dev, "hns_roce_mtt_init error for create qp\n");
443 goto err_buf; 555 goto err_buf;
@@ -472,20 +584,22 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
472 } 584 }
473 585
474 /* QP doorbell register address */ 586 /* QP doorbell register address */
475 hr_qp->sq.db_reg_l = hr_dev->reg_base + ROCEE_DB_SQ_L_0_REG + 587 hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset +
476 DB_REG_OFFSET * hr_dev->priv_uar.index; 588 DB_REG_OFFSET * hr_dev->priv_uar.index;
477 hr_qp->rq.db_reg_l = hr_dev->reg_base + 589 hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset +
478 ROCEE_DB_OTHERS_L_0_REG +
479 DB_REG_OFFSET * hr_dev->priv_uar.index; 590 DB_REG_OFFSET * hr_dev->priv_uar.index;
480 591
481 /* Allocate QP buf */ 592 /* Allocate QP buf */
482 if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size, PAGE_SIZE * 2, 593 page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
483 &hr_qp->hr_buf)) { 594 if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size,
595 (1 << page_shift) * 2,
596 &hr_qp->hr_buf, page_shift)) {
484 dev_err(dev, "hns_roce_buf_alloc error!\n"); 597 dev_err(dev, "hns_roce_buf_alloc error!\n");
485 ret = -ENOMEM; 598 ret = -ENOMEM;
486 goto err_out; 599 goto err_out;
487 } 600 }
488 601
602 hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
489 /* Write MTT */ 603 /* Write MTT */
490 ret = hns_roce_mtt_init(hr_dev, hr_qp->hr_buf.npages, 604 ret = hns_roce_mtt_init(hr_dev, hr_qp->hr_buf.npages,
491 hr_qp->hr_buf.page_shift, &hr_qp->mtt); 605 hr_qp->hr_buf.page_shift, &hr_qp->mtt);
@@ -522,7 +636,9 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
522 } 636 }
523 } 637 }
524 638
525 if ((init_attr->qp_type) == IB_QPT_GSI) { 639 if (init_attr->qp_type == IB_QPT_GSI &&
640 hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
641 /* In v1 engine, GSI QP context in RoCE engine's register */
526 ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp); 642 ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp);
527 if (ret) { 643 if (ret) {
528 dev_err(dev, "hns_roce_qp_alloc failed!\n"); 644 dev_err(dev, "hns_roce_qp_alloc failed!\n");
@@ -571,7 +687,7 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
571 struct ib_udata *udata) 687 struct ib_udata *udata)
572{ 688{
573 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); 689 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
574 struct device *dev = &hr_dev->pdev->dev; 690 struct device *dev = hr_dev->dev;
575 struct hns_roce_sqp *hr_sqp; 691 struct hns_roce_sqp *hr_sqp;
576 struct hns_roce_qp *hr_qp; 692 struct hns_roce_qp *hr_qp;
577 int ret; 693 int ret;
@@ -629,6 +745,7 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
629 745
630 return &hr_qp->ibqp; 746 return &hr_qp->ibqp;
631} 747}
748EXPORT_SYMBOL_GPL(hns_roce_create_qp);
632 749
633int to_hr_qp_type(int qp_type) 750int to_hr_qp_type(int qp_type)
634{ 751{
@@ -647,6 +764,7 @@ int to_hr_qp_type(int qp_type)
647 764
648 return transport_type; 765 return transport_type;
649} 766}
767EXPORT_SYMBOL_GPL(to_hr_qp_type);
650 768
651int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 769int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
652 int attr_mask, struct ib_udata *udata) 770 int attr_mask, struct ib_udata *udata)
@@ -654,7 +772,7 @@ int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
654 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 772 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
655 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 773 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
656 enum ib_qp_state cur_state, new_state; 774 enum ib_qp_state cur_state, new_state;
657 struct device *dev = &hr_dev->pdev->dev; 775 struct device *dev = hr_dev->dev;
658 int ret = -EINVAL; 776 int ret = -EINVAL;
659 int p; 777 int p;
660 enum ib_mtu active_mtu; 778 enum ib_mtu active_mtu;
@@ -692,7 +810,10 @@ int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
692 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 810 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
693 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu); 811 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu);
694 812
695 if (attr->path_mtu > IB_MTU_2048 || 813 if ((hr_dev->caps.max_mtu == IB_MTU_4096 &&
814 attr->path_mtu > IB_MTU_4096) ||
815 (hr_dev->caps.max_mtu == IB_MTU_2048 &&
816 attr->path_mtu > IB_MTU_2048) ||
696 attr->path_mtu < IB_MTU_256 || 817 attr->path_mtu < IB_MTU_256 ||
697 attr->path_mtu > active_mtu) { 818 attr->path_mtu > active_mtu) {
698 dev_err(dev, "attr path_mtu(%d)invalid while modify qp", 819 dev_err(dev, "attr path_mtu(%d)invalid while modify qp",
@@ -716,9 +837,7 @@ int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
716 } 837 }
717 838
718 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 839 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
719 ret = -EPERM; 840 ret = 0;
720 dev_err(dev, "cur_state=%d new_state=%d\n", cur_state,
721 new_state);
722 goto out; 841 goto out;
723 } 842 }
724 843
@@ -745,6 +864,7 @@ void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq)
745 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 864 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
746 } 865 }
747} 866}
867EXPORT_SYMBOL_GPL(hns_roce_lock_cqs);
748 868
749void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 869void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
750 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock) 870 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock)
@@ -761,6 +881,7 @@ void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
761 spin_unlock_irq(&recv_cq->lock); 881 spin_unlock_irq(&recv_cq->lock);
762 } 882 }
763} 883}
884EXPORT_SYMBOL_GPL(hns_roce_unlock_cqs);
764 885
765__be32 send_ieth(struct ib_send_wr *wr) 886__be32 send_ieth(struct ib_send_wr *wr)
766{ 887{
@@ -774,6 +895,7 @@ __be32 send_ieth(struct ib_send_wr *wr)
774 return 0; 895 return 0;
775 } 896 }
776} 897}
898EXPORT_SYMBOL_GPL(send_ieth);
777 899
778static void *get_wqe(struct hns_roce_qp *hr_qp, int offset) 900static void *get_wqe(struct hns_roce_qp *hr_qp, int offset)
779{ 901{
@@ -785,11 +907,20 @@ void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n)
785{ 907{
786 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift)); 908 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
787} 909}
910EXPORT_SYMBOL_GPL(get_recv_wqe);
788 911
789void *get_send_wqe(struct hns_roce_qp *hr_qp, int n) 912void *get_send_wqe(struct hns_roce_qp *hr_qp, int n)
790{ 913{
791 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift)); 914 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
792} 915}
916EXPORT_SYMBOL_GPL(get_send_wqe);
917
918void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n)
919{
920 return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset +
921 (n << hr_qp->sge.sge_shift));
922}
923EXPORT_SYMBOL_GPL(get_send_extend_sge);
793 924
794bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 925bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
795 struct ib_cq *ib_cq) 926 struct ib_cq *ib_cq)
@@ -808,6 +939,7 @@ bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
808 939
809 return cur + nreq >= hr_wq->max_post; 940 return cur + nreq >= hr_wq->max_post;
810} 941}
942EXPORT_SYMBOL_GPL(hns_roce_wq_overflow);
811 943
812int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev) 944int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
813{ 945{
@@ -823,7 +955,7 @@ int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
823 hr_dev->caps.num_qps - 1, SQP_NUM, 955 hr_dev->caps.num_qps - 1, SQP_NUM,
824 reserved_from_top); 956 reserved_from_top);
825 if (ret) { 957 if (ret) {
826 dev_err(&hr_dev->pdev->dev, "qp bitmap init failed!error=%d\n", 958 dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n",
827 ret); 959 ret);
828 return ret; 960 return ret;
829 } 961 }
diff --git a/drivers/infiniband/hw/i40iw/Kconfig b/drivers/infiniband/hw/i40iw/Kconfig
index 6e7d27a14061..f6d20ba88c03 100644
--- a/drivers/infiniband/hw/i40iw/Kconfig
+++ b/drivers/infiniband/hw/i40iw/Kconfig
@@ -1,6 +1,7 @@
1config INFINIBAND_I40IW 1config INFINIBAND_I40IW
2 tristate "Intel(R) Ethernet X722 iWARP Driver" 2 tristate "Intel(R) Ethernet X722 iWARP Driver"
3 depends on INET && I40E 3 depends on INET && I40E
4 depends on PCI
4 select GENERIC_ALLOCATOR 5 select GENERIC_ALLOCATOR
5 ---help--- 6 ---help---
6 Intel(R) Ethernet X722 iWARP Driver 7 Intel(R) Ethernet X722 iWARP Driver
diff --git a/drivers/infiniband/hw/i40iw/i40iw.h b/drivers/infiniband/hw/i40iw/i40iw.h
index a65e4cbdce2f..4ae9131b6350 100644
--- a/drivers/infiniband/hw/i40iw/i40iw.h
+++ b/drivers/infiniband/hw/i40iw/i40iw.h
@@ -119,9 +119,6 @@
119#define I40IW_CQP_COMPL_SQ_WQE_FLUSHED 3 119#define I40IW_CQP_COMPL_SQ_WQE_FLUSHED 3
120#define I40IW_CQP_COMPL_RQ_SQ_WQE_FLUSHED 4 120#define I40IW_CQP_COMPL_RQ_SQ_WQE_FLUSHED 4
121 121
122#define I40IW_MTU_TO_MSS 40
123#define I40IW_DEFAULT_MSS 1460
124
125struct i40iw_cqp_compl_info { 122struct i40iw_cqp_compl_info {
126 u32 op_ret_val; 123 u32 op_ret_val;
127 u16 maj_err_code; 124 u16 maj_err_code;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_cm.c b/drivers/infiniband/hw/i40iw/i40iw_cm.c
index 5230dd3c938c..493d6ef3d2d5 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_cm.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_cm.c
@@ -1188,7 +1188,7 @@ static void i40iw_handle_close_entry(struct i40iw_cm_node *cm_node, u32 rem_node
1188 * i40iw_cm_timer_tick - system's timer expired callback 1188 * i40iw_cm_timer_tick - system's timer expired callback
1189 * @pass: Pointing to cm_core 1189 * @pass: Pointing to cm_core
1190 */ 1190 */
1191static void i40iw_cm_timer_tick(unsigned long pass) 1191static void i40iw_cm_timer_tick(struct timer_list *t)
1192{ 1192{
1193 unsigned long nexttimeout = jiffies + I40IW_LONG_TIME; 1193 unsigned long nexttimeout = jiffies + I40IW_LONG_TIME;
1194 struct i40iw_cm_node *cm_node; 1194 struct i40iw_cm_node *cm_node;
@@ -1196,10 +1196,9 @@ static void i40iw_cm_timer_tick(unsigned long pass)
1196 struct list_head *list_core_temp; 1196 struct list_head *list_core_temp;
1197 struct i40iw_sc_vsi *vsi; 1197 struct i40iw_sc_vsi *vsi;
1198 struct list_head *list_node; 1198 struct list_head *list_node;
1199 struct i40iw_cm_core *cm_core = (struct i40iw_cm_core *)pass; 1199 struct i40iw_cm_core *cm_core = from_timer(cm_core, t, tcp_timer);
1200 u32 settimer = 0; 1200 u32 settimer = 0;
1201 unsigned long timetosend; 1201 unsigned long timetosend;
1202 struct i40iw_sc_dev *dev;
1203 unsigned long flags; 1202 unsigned long flags;
1204 1203
1205 struct list_head timer_list; 1204 struct list_head timer_list;
@@ -1267,13 +1266,15 @@ static void i40iw_cm_timer_tick(unsigned long pass)
1267 spin_lock_irqsave(&cm_node->retrans_list_lock, flags); 1266 spin_lock_irqsave(&cm_node->retrans_list_lock, flags);
1268 goto done; 1267 goto done;
1269 } 1268 }
1270 cm_node->cm_core->stats_pkt_retrans++;
1271 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); 1269 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags);
1272 1270
1273 vsi = &cm_node->iwdev->vsi; 1271 vsi = &cm_node->iwdev->vsi;
1274 dev = cm_node->dev; 1272
1275 atomic_inc(&send_entry->sqbuf->refcount); 1273 if (!cm_node->ack_rcvd) {
1276 i40iw_puda_send_buf(vsi->ilq, send_entry->sqbuf); 1274 atomic_inc(&send_entry->sqbuf->refcount);
1275 i40iw_puda_send_buf(vsi->ilq, send_entry->sqbuf);
1276 cm_node->cm_core->stats_pkt_retrans++;
1277 }
1277 spin_lock_irqsave(&cm_node->retrans_list_lock, flags); 1278 spin_lock_irqsave(&cm_node->retrans_list_lock, flags);
1278 if (send_entry->send_retrans) { 1279 if (send_entry->send_retrans) {
1279 send_entry->retranscount--; 1280 send_entry->retranscount--;
@@ -1524,8 +1525,8 @@ static bool i40iw_port_in_use(struct i40iw_cm_core *cm_core, u16 port, bool acti
1524 break; 1525 break;
1525 } 1526 }
1526 } 1527 }
1527 if (!ret) 1528 if (!ret)
1528 clear_bit(port, cm_core->active_side_ports); 1529 clear_bit(port, cm_core->active_side_ports);
1529 spin_unlock_irqrestore(&cm_core->ht_lock, flags); 1530 spin_unlock_irqrestore(&cm_core->ht_lock, flags);
1530 } else { 1531 } else {
1531 spin_lock_irqsave(&cm_core->listen_list_lock, flags); 1532 spin_lock_irqsave(&cm_core->listen_list_lock, flags);
@@ -2181,6 +2182,7 @@ static struct i40iw_cm_node *i40iw_make_cm_node(
2181 cm_node->cm_id = cm_info->cm_id; 2182 cm_node->cm_id = cm_info->cm_id;
2182 ether_addr_copy(cm_node->loc_mac, netdev->dev_addr); 2183 ether_addr_copy(cm_node->loc_mac, netdev->dev_addr);
2183 spin_lock_init(&cm_node->retrans_list_lock); 2184 spin_lock_init(&cm_node->retrans_list_lock);
2185 cm_node->ack_rcvd = false;
2184 2186
2185 atomic_set(&cm_node->ref_count, 1); 2187 atomic_set(&cm_node->ref_count, 1);
2186 /* associate our parent CM core */ 2188 /* associate our parent CM core */
@@ -2191,7 +2193,8 @@ static struct i40iw_cm_node *i40iw_make_cm_node(
2191 I40IW_CM_DEFAULT_RCV_WND_SCALED >> I40IW_CM_DEFAULT_RCV_WND_SCALE; 2193 I40IW_CM_DEFAULT_RCV_WND_SCALED >> I40IW_CM_DEFAULT_RCV_WND_SCALE;
2192 ts = current_kernel_time(); 2194 ts = current_kernel_time();
2193 cm_node->tcp_cntxt.loc_seq_num = ts.tv_nsec; 2195 cm_node->tcp_cntxt.loc_seq_num = ts.tv_nsec;
2194 cm_node->tcp_cntxt.mss = iwdev->vsi.mss; 2196 cm_node->tcp_cntxt.mss = (cm_node->ipv4) ? (iwdev->vsi.mtu - I40IW_MTU_TO_MSS_IPV4) :
2197 (iwdev->vsi.mtu - I40IW_MTU_TO_MSS_IPV6);
2195 2198
2196 cm_node->iwdev = iwdev; 2199 cm_node->iwdev = iwdev;
2197 cm_node->dev = &iwdev->sc_dev; 2200 cm_node->dev = &iwdev->sc_dev;
@@ -2406,6 +2409,7 @@ static void i40iw_handle_rst_pkt(struct i40iw_cm_node *cm_node,
2406 case I40IW_CM_STATE_FIN_WAIT1: 2409 case I40IW_CM_STATE_FIN_WAIT1:
2407 case I40IW_CM_STATE_LAST_ACK: 2410 case I40IW_CM_STATE_LAST_ACK:
2408 cm_node->cm_id->rem_ref(cm_node->cm_id); 2411 cm_node->cm_id->rem_ref(cm_node->cm_id);
2412 /* fall through */
2409 case I40IW_CM_STATE_TIME_WAIT: 2413 case I40IW_CM_STATE_TIME_WAIT:
2410 cm_node->state = I40IW_CM_STATE_CLOSED; 2414 cm_node->state = I40IW_CM_STATE_CLOSED;
2411 i40iw_rem_ref_cm_node(cm_node); 2415 i40iw_rem_ref_cm_node(cm_node);
@@ -2719,7 +2723,10 @@ static int i40iw_handle_ack_pkt(struct i40iw_cm_node *cm_node,
2719 cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq); 2723 cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq);
2720 if (datasize) { 2724 if (datasize) {
2721 cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize; 2725 cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize;
2726 cm_node->ack_rcvd = false;
2722 i40iw_handle_rcv_mpa(cm_node, rbuf); 2727 i40iw_handle_rcv_mpa(cm_node, rbuf);
2728 } else {
2729 cm_node->ack_rcvd = true;
2723 } 2730 }
2724 break; 2731 break;
2725 case I40IW_CM_STATE_LISTENING: 2732 case I40IW_CM_STATE_LISTENING:
@@ -3195,8 +3202,7 @@ void i40iw_setup_cm_core(struct i40iw_device *iwdev)
3195 INIT_LIST_HEAD(&cm_core->connected_nodes); 3202 INIT_LIST_HEAD(&cm_core->connected_nodes);
3196 INIT_LIST_HEAD(&cm_core->listen_nodes); 3203 INIT_LIST_HEAD(&cm_core->listen_nodes);
3197 3204
3198 setup_timer(&cm_core->tcp_timer, i40iw_cm_timer_tick, 3205 timer_setup(&cm_core->tcp_timer, i40iw_cm_timer_tick, 0);
3199 (unsigned long)cm_core);
3200 3206
3201 spin_lock_init(&cm_core->ht_lock); 3207 spin_lock_init(&cm_core->ht_lock);
3202 spin_lock_init(&cm_core->listen_list_lock); 3208 spin_lock_init(&cm_core->listen_list_lock);
diff --git a/drivers/infiniband/hw/i40iw/i40iw_cm.h b/drivers/infiniband/hw/i40iw/i40iw_cm.h
index 45abef76295b..0d5840d2c4fc 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_cm.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_cm.h
@@ -360,6 +360,7 @@ struct i40iw_cm_node {
360 360
361 u8 pdata_buf[IETF_MAX_PRIV_DATA_LEN]; 361 u8 pdata_buf[IETF_MAX_PRIV_DATA_LEN];
362 struct i40iw_kmem_info mpa_hdr; 362 struct i40iw_kmem_info mpa_hdr;
363 bool ack_rcvd;
363}; 364};
364 365
365/* structure for client or CM to fill when making CM api calls. */ 366/* structure for client or CM to fill when making CM api calls. */
diff --git a/drivers/infiniband/hw/i40iw/i40iw_ctrl.c b/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
index 42ca5346777d..d88c6cf47cf2 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
@@ -348,7 +348,10 @@ void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2pa
348 u16 qs_handle; 348 u16 qs_handle;
349 int i; 349 int i;
350 350
351 vsi->mss = l2params->mss; 351 if (vsi->mtu != l2params->mtu) {
352 vsi->mtu = l2params->mtu;
353 i40iw_reinitialize_ieq(dev);
354 }
352 355
353 i40iw_fill_qos_list(l2params->qs_handle_list); 356 i40iw_fill_qos_list(l2params->qs_handle_list);
354 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) { 357 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
@@ -374,7 +377,7 @@ void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2pa
374 * i40iw_qp_rem_qos - remove qp from qos lists during destroy qp 377 * i40iw_qp_rem_qos - remove qp from qos lists during destroy qp
375 * @qp: qp to be removed from qos 378 * @qp: qp to be removed from qos
376 */ 379 */
377static void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp) 380void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp)
378{ 381{
379 struct i40iw_sc_vsi *vsi = qp->vsi; 382 struct i40iw_sc_vsi *vsi = qp->vsi;
380 unsigned long flags; 383 unsigned long flags;
@@ -479,6 +482,10 @@ static enum i40iw_status_code i40iw_sc_cqp_init(struct i40iw_sc_cqp *cqp,
479 I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size); 482 I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size);
480 cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] = 0; 483 cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] = 0;
481 cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS] = 0; 484 cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS] = 0;
485 INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head); /* for the cqp commands backlog. */
486
487 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPTAIL, 0);
488 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPDB, 0);
482 489
483 i40iw_debug(cqp->dev, I40IW_DEBUG_WQE, 490 i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
484 "%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n", 491 "%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n",
@@ -1774,6 +1781,53 @@ static enum i40iw_status_code i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq *aeq,
1774 info->iwarp_state = (u8)RS_64(temp, I40IW_AEQE_IWSTATE); 1781 info->iwarp_state = (u8)RS_64(temp, I40IW_AEQE_IWSTATE);
1775 info->q2_data_written = (u8)RS_64(temp, I40IW_AEQE_Q2DATA); 1782 info->q2_data_written = (u8)RS_64(temp, I40IW_AEQE_Q2DATA);
1776 info->aeqe_overflow = (bool)RS_64(temp, I40IW_AEQE_OVERFLOW); 1783 info->aeqe_overflow = (bool)RS_64(temp, I40IW_AEQE_OVERFLOW);
1784
1785 switch (info->ae_id) {
1786 case I40IW_AE_PRIV_OPERATION_DENIED:
1787 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
1788 case I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT:
1789 case I40IW_AE_BAD_CLOSE:
1790 case I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE:
1791 case I40IW_AE_RDMA_READ_WHILE_ORD_ZERO:
1792 case I40IW_AE_STAG_ZERO_INVALID:
1793 case I40IW_AE_IB_RREQ_AND_Q1_FULL:
1794 case I40IW_AE_WQE_UNEXPECTED_OPCODE:
1795 case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
1796 case I40IW_AE_DDP_UBE_INVALID_MO:
1797 case I40IW_AE_DDP_UBE_INVALID_QN:
1798 case I40IW_AE_DDP_NO_L_BIT:
1799 case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
1800 case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
1801 case I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST:
1802 case I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
1803 case I40IW_AE_INVALID_ARP_ENTRY:
1804 case I40IW_AE_INVALID_TCP_OPTION_RCVD:
1805 case I40IW_AE_STALE_ARP_ENTRY:
1806 case I40IW_AE_LLP_CLOSE_COMPLETE:
1807 case I40IW_AE_LLP_CONNECTION_RESET:
1808 case I40IW_AE_LLP_FIN_RECEIVED:
1809 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
1810 case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
1811 case I40IW_AE_LLP_SYN_RECEIVED:
1812 case I40IW_AE_LLP_TERMINATE_RECEIVED:
1813 case I40IW_AE_LLP_TOO_MANY_RETRIES:
1814 case I40IW_AE_LLP_DOUBT_REACHABILITY:
1815 case I40IW_AE_RESET_SENT:
1816 case I40IW_AE_TERMINATE_SENT:
1817 case I40IW_AE_RESET_NOT_SENT:
1818 case I40IW_AE_LCE_QP_CATASTROPHIC:
1819 case I40IW_AE_QP_SUSPEND_COMPLETE:
1820 info->qp = true;
1821 info->compl_ctx = compl_ctx;
1822 ae_src = I40IW_AE_SOURCE_RSVD;
1823 break;
1824 case I40IW_AE_LCE_CQ_CATASTROPHIC:
1825 info->cq = true;
1826 info->compl_ctx = LS_64_1(compl_ctx, 1);
1827 ae_src = I40IW_AE_SOURCE_RSVD;
1828 break;
1829 }
1830
1777 switch (ae_src) { 1831 switch (ae_src) {
1778 case I40IW_AE_SOURCE_RQ: 1832 case I40IW_AE_SOURCE_RQ:
1779 case I40IW_AE_SOURCE_RQ_0011: 1833 case I40IW_AE_SOURCE_RQ_0011:
@@ -1807,6 +1861,8 @@ static enum i40iw_status_code i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq *aeq,
1807 info->compl_ctx = compl_ctx; 1861 info->compl_ctx = compl_ctx;
1808 info->out_rdrsp = true; 1862 info->out_rdrsp = true;
1809 break; 1863 break;
1864 case I40IW_AE_SOURCE_RSVD:
1865 /* fallthrough */
1810 default: 1866 default:
1811 break; 1867 break;
1812 } 1868 }
@@ -2357,7 +2413,6 @@ static enum i40iw_status_code i40iw_sc_qp_init(struct i40iw_sc_qp *qp,
2357 qp->rcv_tph_en = info->rcv_tph_en; 2413 qp->rcv_tph_en = info->rcv_tph_en;
2358 qp->xmit_tph_en = info->xmit_tph_en; 2414 qp->xmit_tph_en = info->xmit_tph_en;
2359 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle; 2415 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle;
2360 qp->exception_lan_queue = qp->pd->dev->exception_lan_queue;
2361 2416
2362 return 0; 2417 return 0;
2363} 2418}
@@ -2399,7 +2454,6 @@ static enum i40iw_status_code i40iw_sc_qp_create(
2399 LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) | 2454 LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2400 LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) | 2455 LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
2401 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) | 2456 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2402 LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
2403 LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) | 2457 LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2404 LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) | 2458 LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2405 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); 2459 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
@@ -2462,7 +2516,6 @@ static enum i40iw_status_code i40iw_sc_qp_modify(
2462 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) | 2516 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2463 LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) | 2517 LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) |
2464 LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) | 2518 LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2465 LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
2466 LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) | 2519 LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
2467 LS_64(term_actions, I40IW_CQPSQ_QP_TERMACT) | 2520 LS_64(term_actions, I40IW_CQPSQ_QP_TERMACT) |
2468 LS_64(info->reset_tcp_conn, I40IW_CQPSQ_QP_RESETCON) | 2521 LS_64(info->reset_tcp_conn, I40IW_CQPSQ_QP_RESETCON) |
@@ -2694,7 +2747,7 @@ static enum i40iw_status_code i40iw_sc_qp_setctx(
2694 LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) | 2747 LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) |
2695 LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) | 2748 LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) |
2696 LS_64(qp->qs_handle, I40IWQPC_QSHANDLE) | 2749 LS_64(qp->qs_handle, I40IWQPC_QSHANDLE) |
2697 LS_64(qp->exception_lan_queue, I40IWQPC_EXCEPTION_LAN_QUEUE)); 2750 LS_64(vsi->exception_lan_queue, I40IWQPC_EXCEPTION_LAN_QUEUE));
2698 2751
2699 if (info->iwarp_info_valid) { 2752 if (info->iwarp_info_valid) {
2700 qw0 |= LS_64(iw->ddp_ver, I40IWQPC_DDP_VER) | 2753 qw0 |= LS_64(iw->ddp_ver, I40IWQPC_DDP_VER) |
@@ -4376,10 +4429,6 @@ static int i40iw_bld_terminate_hdr(struct i40iw_sc_qp *qp,
4376 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR, 4429 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4377 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_TO_WRAP); 4430 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_TO_WRAP);
4378 break; 4431 break;
4379 case I40IW_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
4380 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4381 (LAYER_MPA << 4) | DDP_LLP, MPA_MARKER);
4382 break;
4383 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR: 4432 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
4384 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, 4433 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4385 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC); 4434 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC);
@@ -4395,7 +4444,6 @@ static int i40iw_bld_terminate_hdr(struct i40iw_sc_qp *qp,
4395 (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL); 4444 (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL);
4396 break; 4445 break;
4397 case I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN: 4446 case I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN:
4398 case I40IW_AE_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
4399 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR, 4447 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4400 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_RANGE); 4448 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_RANGE);
4401 break; 4449 break;
@@ -4541,7 +4589,8 @@ void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *inf
4541 4589
4542 vsi->dev = info->dev; 4590 vsi->dev = info->dev;
4543 vsi->back_vsi = info->back_vsi; 4591 vsi->back_vsi = info->back_vsi;
4544 vsi->mss = info->params->mss; 4592 vsi->mtu = info->params->mtu;
4593 vsi->exception_lan_queue = info->exception_lan_queue;
4545 i40iw_fill_qos_list(info->params->qs_handle_list); 4594 i40iw_fill_qos_list(info->params->qs_handle_list);
4546 4595
4547 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) { 4596 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
@@ -4873,6 +4922,7 @@ enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40
4873 4922
4874 vsi->pestat = info->pestat; 4923 vsi->pestat = info->pestat;
4875 vsi->pestat->hw = vsi->dev->hw; 4924 vsi->pestat->hw = vsi->dev->hw;
4925 vsi->pestat->vsi = vsi;
4876 4926
4877 if (info->stats_initialize) { 4927 if (info->stats_initialize) {
4878 i40iw_hw_stats_init(vsi->pestat, fcn_id, true); 4928 i40iw_hw_stats_init(vsi->pestat, fcn_id, true);
@@ -5018,14 +5068,12 @@ enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev,
5018 u8 db_size; 5068 u8 db_size;
5019 5069
5020 spin_lock_init(&dev->cqp_lock); 5070 spin_lock_init(&dev->cqp_lock);
5021 INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for the cqp commands backlog. */
5022 5071
5023 i40iw_device_init_uk(&dev->dev_uk); 5072 i40iw_device_init_uk(&dev->dev_uk);
5024 5073
5025 dev->debug_mask = info->debug_mask; 5074 dev->debug_mask = info->debug_mask;
5026 5075
5027 dev->hmc_fn_id = info->hmc_fn_id; 5076 dev->hmc_fn_id = info->hmc_fn_id;
5028 dev->exception_lan_queue = info->exception_lan_queue;
5029 dev->is_pf = info->is_pf; 5077 dev->is_pf = info->is_pf;
5030 5078
5031 dev->fpm_query_buf_pa = info->fpm_query_buf_pa; 5079 dev->fpm_query_buf_pa = info->fpm_query_buf_pa;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_d.h b/drivers/infiniband/hw/i40iw/i40iw_d.h
index 2ebaadbed379..65ec39e3746b 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_d.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_d.h
@@ -73,6 +73,10 @@
73#define I40IW_FIRST_NON_PF_STAT 4 73#define I40IW_FIRST_NON_PF_STAT 4
74 74
75 75
76#define I40IW_MTU_TO_MSS_IPV4 40
77#define I40IW_MTU_TO_MSS_IPV6 60
78#define I40IW_DEFAULT_MTU 1500
79
76#define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits) 80#define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits)
77#define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits) 81#define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits)
78#define LS_32_1(val, bits) (u32)(val << bits) 82#define LS_32_1(val, bits) (u32)(val << bits)
@@ -128,6 +132,7 @@
128 &_ceq->ceqe_base[I40IW_RING_GETCURRENT_TAIL(_ceq->ceq_ring)] \ 132 &_ceq->ceqe_base[I40IW_RING_GETCURRENT_TAIL(_ceq->ceq_ring)] \
129 ) 133 )
130 134
135#define I40IW_AE_SOURCE_RSVD 0x0
131#define I40IW_AE_SOURCE_RQ 0x1 136#define I40IW_AE_SOURCE_RQ 0x1
132#define I40IW_AE_SOURCE_RQ_0011 0x3 137#define I40IW_AE_SOURCE_RQ_0011 0x3
133 138
@@ -539,9 +544,6 @@
539#define I40IW_CQPSQ_QP_MSSCHANGE_SHIFT 52 544#define I40IW_CQPSQ_QP_MSSCHANGE_SHIFT 52
540#define I40IW_CQPSQ_QP_MSSCHANGE_MASK (1ULL << I40IW_CQPSQ_QP_MSSCHANGE_SHIFT) 545#define I40IW_CQPSQ_QP_MSSCHANGE_MASK (1ULL << I40IW_CQPSQ_QP_MSSCHANGE_SHIFT)
541 546
542#define I40IW_CQPSQ_QP_STATRSRC_SHIFT 53
543#define I40IW_CQPSQ_QP_STATRSRC_MASK (1ULL << I40IW_CQPSQ_QP_STATRSRC_SHIFT)
544
545#define I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT 54 547#define I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT 54
546#define I40IW_CQPSQ_QP_IGNOREMWBOUND_MASK \ 548#define I40IW_CQPSQ_QP_IGNOREMWBOUND_MASK \
547 (1ULL << I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT) 549 (1ULL << I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT)
@@ -1105,6 +1107,9 @@
1105#define I40IWQPC_SNDMSS_SHIFT 16 1107#define I40IWQPC_SNDMSS_SHIFT 16
1106#define I40IWQPC_SNDMSS_MASK (0x3fffUL << I40IWQPC_SNDMSS_SHIFT) 1108#define I40IWQPC_SNDMSS_MASK (0x3fffUL << I40IWQPC_SNDMSS_SHIFT)
1107 1109
1110#define I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT 16
1111#define I40IW_UDA_QPC_MAXFRAMESIZE_MASK (0x3fffUL << I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT)
1112
1108#define I40IWQPC_VLANTAG_SHIFT 32 1113#define I40IWQPC_VLANTAG_SHIFT 32
1109#define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT) 1114#define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT)
1110 1115
@@ -1296,8 +1301,13 @@
1296 (0xffffffffULL << I40IWQPC_LOCAL_IPADDR0_SHIFT) 1301 (0xffffffffULL << I40IWQPC_LOCAL_IPADDR0_SHIFT)
1297 1302
1298/* wqe size considering 32 bytes per wqe*/ 1303/* wqe size considering 32 bytes per wqe*/
1299#define I40IWQP_SW_MIN_WQSIZE 4 /* 128 bytes */ 1304#define I40IW_QP_SW_MIN_WQSIZE 4 /*in WRs*/
1300#define I40IWQP_SW_MAX_WQSIZE 2048 /* 2048 bytes */ 1305#define I40IW_SQ_RSVD 2
1306#define I40IW_RQ_RSVD 1
1307#define I40IW_MAX_QUANTAS_PER_WR 2
1308#define I40IW_QP_SW_MAX_SQ_QUANTAS 2048
1309#define I40IW_QP_SW_MAX_RQ_QUANTAS 16384
1310#define I40IW_MAX_QP_WRS ((I40IW_QP_SW_MAX_SQ_QUANTAS / I40IW_MAX_QUANTAS_PER_WR) - 1)
1301 1311
1302#define I40IWQP_OP_RDMA_WRITE 0 1312#define I40IWQP_OP_RDMA_WRITE 0
1303#define I40IWQP_OP_RDMA_READ 1 1313#define I40IWQP_OP_RDMA_READ 1
@@ -1636,7 +1646,8 @@ enum i40iw_alignment {
1636#define I40IW_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119 1646#define I40IW_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119
1637#define I40IW_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a 1647#define I40IW_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a
1638#define I40IW_AE_AMP_MWBIND_BIND_DISABLED 0x011b 1648#define I40IW_AE_AMP_MWBIND_BIND_DISABLED 0x011b
1639#define I40IW_AE_AMP_WQE_INVALID_PARAMETER 0x0130 1649#define I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132
1650#define I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134
1640#define I40IW_AE_BAD_CLOSE 0x0201 1651#define I40IW_AE_BAD_CLOSE 0x0201
1641#define I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202 1652#define I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202
1642#define I40IW_AE_CQ_OPERATION_ERROR 0x0203 1653#define I40IW_AE_CQ_OPERATION_ERROR 0x0203
@@ -1644,12 +1655,10 @@ enum i40iw_alignment {
1644#define I40IW_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205 1655#define I40IW_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205
1645#define I40IW_AE_STAG_ZERO_INVALID 0x0206 1656#define I40IW_AE_STAG_ZERO_INVALID 0x0206
1646#define I40IW_AE_IB_RREQ_AND_Q1_FULL 0x0207 1657#define I40IW_AE_IB_RREQ_AND_Q1_FULL 0x0207
1647#define I40IW_AE_SRQ_LIMIT 0x0209
1648#define I40IW_AE_WQE_UNEXPECTED_OPCODE 0x020a 1658#define I40IW_AE_WQE_UNEXPECTED_OPCODE 0x020a
1649#define I40IW_AE_WQE_INVALID_PARAMETER 0x020b 1659#define I40IW_AE_WQE_INVALID_PARAMETER 0x020b
1650#define I40IW_AE_WQE_LSMM_TOO_LONG 0x0220 1660#define I40IW_AE_WQE_LSMM_TOO_LONG 0x0220
1651#define I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301 1661#define I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301
1652#define I40IW_AE_DDP_INVALID_MSN_RANGE_IS_NOT_VALID 0x0302
1653#define I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303 1662#define I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303
1654#define I40IW_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304 1663#define I40IW_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304
1655#define I40IW_AE_DDP_UBE_INVALID_MO 0x0305 1664#define I40IW_AE_DDP_UBE_INVALID_MO 0x0305
@@ -1663,12 +1672,10 @@ enum i40iw_alignment {
1663#define I40IW_AE_INVALID_ARP_ENTRY 0x0401 1672#define I40IW_AE_INVALID_ARP_ENTRY 0x0401
1664#define I40IW_AE_INVALID_TCP_OPTION_RCVD 0x0402 1673#define I40IW_AE_INVALID_TCP_OPTION_RCVD 0x0402
1665#define I40IW_AE_STALE_ARP_ENTRY 0x0403 1674#define I40IW_AE_STALE_ARP_ENTRY 0x0403
1666#define I40IW_AE_INVALID_WQE_LENGTH 0x0404
1667#define I40IW_AE_INVALID_MAC_ENTRY 0x0405 1675#define I40IW_AE_INVALID_MAC_ENTRY 0x0405
1668#define I40IW_AE_LLP_CLOSE_COMPLETE 0x0501 1676#define I40IW_AE_LLP_CLOSE_COMPLETE 0x0501
1669#define I40IW_AE_LLP_CONNECTION_RESET 0x0502 1677#define I40IW_AE_LLP_CONNECTION_RESET 0x0502
1670#define I40IW_AE_LLP_FIN_RECEIVED 0x0503 1678#define I40IW_AE_LLP_FIN_RECEIVED 0x0503
1671#define I40IW_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504
1672#define I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505 1679#define I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505
1673#define I40IW_AE_LLP_SEGMENT_TOO_LARGE 0x0506 1680#define I40IW_AE_LLP_SEGMENT_TOO_LARGE 0x0506
1674#define I40IW_AE_LLP_SEGMENT_TOO_SMALL 0x0507 1681#define I40IW_AE_LLP_SEGMENT_TOO_SMALL 0x0507
@@ -1685,9 +1692,6 @@ enum i40iw_alignment {
1685#define I40IW_AE_LCE_QP_CATASTROPHIC 0x0700 1692#define I40IW_AE_LCE_QP_CATASTROPHIC 0x0700
1686#define I40IW_AE_LCE_FUNCTION_CATASTROPHIC 0x0701 1693#define I40IW_AE_LCE_FUNCTION_CATASTROPHIC 0x0701
1687#define I40IW_AE_LCE_CQ_CATASTROPHIC 0x0702 1694#define I40IW_AE_LCE_CQ_CATASTROPHIC 0x0702
1688#define I40IW_AE_UDA_XMIT_FRAG_SEQ 0x0800
1689#define I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0801
1690#define I40IW_AE_UDA_XMIT_IPADDR_MISMATCH 0x0802
1691#define I40IW_AE_QP_SUSPEND_COMPLETE 0x0900 1695#define I40IW_AE_QP_SUSPEND_COMPLETE 0x0900
1692 1696
1693#define OP_DELETE_LOCAL_MAC_IPADDR_ENTRY 1 1697#define OP_DELETE_LOCAL_MAC_IPADDR_ENTRY 1
diff --git a/drivers/infiniband/hw/i40iw/i40iw_hw.c b/drivers/infiniband/hw/i40iw/i40iw_hw.c
index 476867a3f584..e96bdafbcbb3 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_hw.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_hw.c
@@ -408,8 +408,9 @@ void i40iw_process_aeq(struct i40iw_device *iwdev)
408 case I40IW_AE_LCE_FUNCTION_CATASTROPHIC: 408 case I40IW_AE_LCE_FUNCTION_CATASTROPHIC:
409 case I40IW_AE_LCE_CQ_CATASTROPHIC: 409 case I40IW_AE_LCE_CQ_CATASTROPHIC:
410 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG: 410 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
411 case I40IW_AE_UDA_XMIT_IPADDR_MISMATCH: 411 case I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT:
412 ctx_info->err_rq_idx_valid = false; 412 ctx_info->err_rq_idx_valid = false;
413 /* fall through */
413 default: 414 default:
414 if (!info->sq && ctx_info->err_rq_idx_valid) { 415 if (!info->sq && ctx_info->err_rq_idx_valid) {
415 ctx_info->err_rq_idx = info->wqe_idx; 416 ctx_info->err_rq_idx = info->wqe_idx;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_main.c b/drivers/infiniband/hw/i40iw/i40iw_main.c
index 27590ae21881..e824296713e2 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_main.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_main.c
@@ -353,6 +353,8 @@ static void i40iw_dele_ceqs(struct i40iw_device *iwdev)
353 i40iw_disable_irq(dev, msix_vec, (void *)iwceq); 353 i40iw_disable_irq(dev, msix_vec, (void *)iwceq);
354 i40iw_destroy_ceq(iwdev, iwceq); 354 i40iw_destroy_ceq(iwdev, iwceq);
355 } 355 }
356
357 iwdev->sc_dev.ceq_valid = false;
356} 358}
357 359
358/** 360/**
@@ -810,17 +812,16 @@ static enum i40iw_status_code i40iw_setup_ceqs(struct i40iw_device *iwdev,
810 i40iw_enable_intr(&iwdev->sc_dev, msix_vec->idx); 812 i40iw_enable_intr(&iwdev->sc_dev, msix_vec->idx);
811 iwdev->ceqs_count++; 813 iwdev->ceqs_count++;
812 } 814 }
813
814exit: 815exit:
815 if (status) { 816 if (status && !iwdev->ceqs_count) {
816 if (!iwdev->ceqs_count) { 817 kfree(iwdev->ceqlist);
817 kfree(iwdev->ceqlist); 818 iwdev->ceqlist = NULL;
818 iwdev->ceqlist = NULL; 819 return status;
819 } else { 820 } else {
820 status = 0; 821 iwdev->sc_dev.ceq_valid = true;
821 } 822 return 0;
822 } 823 }
823 return status; 824
824} 825}
825 826
826/** 827/**
@@ -958,13 +959,13 @@ static enum i40iw_status_code i40iw_initialize_ieq(struct i40iw_device *iwdev)
958 memset(&info, 0, sizeof(info)); 959 memset(&info, 0, sizeof(info));
959 info.type = I40IW_PUDA_RSRC_TYPE_IEQ; 960 info.type = I40IW_PUDA_RSRC_TYPE_IEQ;
960 info.cq_id = 2; 961 info.cq_id = 2;
961 info.qp_id = iwdev->sc_dev.exception_lan_queue; 962 info.qp_id = iwdev->vsi.exception_lan_queue;
962 info.count = 1; 963 info.count = 1;
963 info.pd_id = 2; 964 info.pd_id = 2;
964 info.sq_size = 8192; 965 info.sq_size = 8192;
965 info.rq_size = 8192; 966 info.rq_size = 8192;
966 info.buf_size = 2048; 967 info.buf_size = iwdev->vsi.mtu + VLAN_ETH_HLEN;
967 info.tx_buf_cnt = 16384; 968 info.tx_buf_cnt = 4096;
968 status = i40iw_puda_create_rsrc(&iwdev->vsi, &info); 969 status = i40iw_puda_create_rsrc(&iwdev->vsi, &info);
969 if (status) 970 if (status)
970 i40iw_pr_err("ieq create fail\n"); 971 i40iw_pr_err("ieq create fail\n");
@@ -972,6 +973,21 @@ static enum i40iw_status_code i40iw_initialize_ieq(struct i40iw_device *iwdev)
972} 973}
973 974
974/** 975/**
976 * i40iw_reinitialize_ieq - destroy and re-create ieq
977 * @dev: iwarp device
978 */
979void i40iw_reinitialize_ieq(struct i40iw_sc_dev *dev)
980{
981 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
982
983 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_IEQ, false);
984 if (i40iw_initialize_ieq(iwdev)) {
985 iwdev->reset = true;
986 i40iw_request_reset(iwdev);
987 }
988}
989
990/**
975 * i40iw_hmc_setup - create hmc objects for the device 991 * i40iw_hmc_setup - create hmc objects for the device
976 * @iwdev: iwarp device 992 * @iwdev: iwarp device
977 * 993 *
@@ -1327,8 +1343,8 @@ static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev,
1327 info.bar0 = ldev->hw_addr; 1343 info.bar0 = ldev->hw_addr;
1328 info.hw = &iwdev->hw; 1344 info.hw = &iwdev->hw;
1329 info.debug_mask = debug; 1345 info.debug_mask = debug;
1330 l2params.mss = 1346 l2params.mtu =
1331 (ldev->params.mtu) ? ldev->params.mtu - I40IW_MTU_TO_MSS : I40IW_DEFAULT_MSS; 1347 (ldev->params.mtu) ? ldev->params.mtu : I40IW_DEFAULT_MTU;
1332 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++) { 1348 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++) {
1333 qset = ldev->params.qos.prio_qos[i].qs_handle; 1349 qset = ldev->params.qos.prio_qos[i].qs_handle;
1334 l2params.qs_handle_list[i] = qset; 1350 l2params.qs_handle_list[i] = qset;
@@ -1338,7 +1354,6 @@ static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev,
1338 iwdev->dcb = true; 1354 iwdev->dcb = true;
1339 } 1355 }
1340 i40iw_pr_info("DCB is set/clear = %d\n", iwdev->dcb); 1356 i40iw_pr_info("DCB is set/clear = %d\n", iwdev->dcb);
1341 info.exception_lan_queue = 1;
1342 info.vchnl_send = i40iw_virtchnl_send; 1357 info.vchnl_send = i40iw_virtchnl_send;
1343 status = i40iw_device_init(&iwdev->sc_dev, &info); 1358 status = i40iw_device_init(&iwdev->sc_dev, &info);
1344 1359
@@ -1348,6 +1363,7 @@ static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev,
1348 vsi_info.dev = &iwdev->sc_dev; 1363 vsi_info.dev = &iwdev->sc_dev;
1349 vsi_info.back_vsi = (void *)iwdev; 1364 vsi_info.back_vsi = (void *)iwdev;
1350 vsi_info.params = &l2params; 1365 vsi_info.params = &l2params;
1366 vsi_info.exception_lan_queue = 1;
1351 i40iw_sc_vsi_init(&iwdev->vsi, &vsi_info); 1367 i40iw_sc_vsi_init(&iwdev->vsi, &vsi_info);
1352 1368
1353 if (dev->is_pf) { 1369 if (dev->is_pf) {
@@ -1748,7 +1764,7 @@ static void i40iw_l2param_change(struct i40e_info *ldev, struct i40e_client *cli
1748 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++) 1764 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++)
1749 l2params->qs_handle_list[i] = params->qos.prio_qos[i].qs_handle; 1765 l2params->qs_handle_list[i] = params->qos.prio_qos[i].qs_handle;
1750 1766
1751 l2params->mss = (params->mtu) ? params->mtu - I40IW_MTU_TO_MSS : iwdev->vsi.mss; 1767 l2params->mtu = (params->mtu) ? params->mtu : iwdev->vsi.mtu;
1752 1768
1753 INIT_WORK(&work->work, i40iw_l2params_worker); 1769 INIT_WORK(&work->work, i40iw_l2params_worker);
1754 queue_work(iwdev->param_wq, &work->work); 1770 queue_work(iwdev->param_wq, &work->work);
diff --git a/drivers/infiniband/hw/i40iw/i40iw_p.h b/drivers/infiniband/hw/i40iw/i40iw_p.h
index 5498ad01c280..11d3a2a72100 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_p.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_p.h
@@ -86,7 +86,7 @@ void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *inf
86 86
87void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params); 87void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params);
88void i40iw_qp_add_qos(struct i40iw_sc_qp *qp); 88void i40iw_qp_add_qos(struct i40iw_sc_qp *qp);
89 89void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp);
90void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp); 90void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp);
91 91
92void i40iw_terminate_connection(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info); 92void i40iw_terminate_connection(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info);
@@ -123,5 +123,6 @@ enum i40iw_status_code i40iw_allocate_virt_mem(struct i40iw_hw *hw,
123enum i40iw_status_code i40iw_free_virt_mem(struct i40iw_hw *hw, 123enum i40iw_status_code i40iw_free_virt_mem(struct i40iw_hw *hw,
124 struct i40iw_virt_mem *mem); 124 struct i40iw_virt_mem *mem);
125u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq); 125u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq);
126void i40iw_reinitialize_ieq(struct i40iw_sc_dev *dev);
126 127
127#endif 128#endif
diff --git a/drivers/infiniband/hw/i40iw/i40iw_puda.c b/drivers/infiniband/hw/i40iw/i40iw_puda.c
index 59f70676f0e0..796a815b53fd 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_puda.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_puda.c
@@ -488,7 +488,7 @@ static void i40iw_puda_qp_setctx(struct i40iw_puda_rsrc *rsrc)
488 LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) | 488 LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) |
489 LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE)); 489 LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE));
490 490
491 set_64bit_val(qp_ctx, 48, LS_64(1514, I40IWQPC_SNDMSS)); 491 set_64bit_val(qp_ctx, 48, LS_64(rsrc->buf_size, I40IW_UDA_QPC_MAXFRAMESIZE));
492 set_64bit_val(qp_ctx, 56, 0); 492 set_64bit_val(qp_ctx, 56, 0);
493 set_64bit_val(qp_ctx, 64, 1); 493 set_64bit_val(qp_ctx, 64, 1);
494 494
@@ -611,12 +611,14 @@ static enum i40iw_status_code i40iw_puda_qp_create(struct i40iw_puda_rsrc *rsrc)
611 qp->user_pri = 0; 611 qp->user_pri = 0;
612 i40iw_qp_add_qos(qp); 612 i40iw_qp_add_qos(qp);
613 i40iw_puda_qp_setctx(rsrc); 613 i40iw_puda_qp_setctx(rsrc);
614 if (rsrc->ceq_valid) 614 if (rsrc->dev->ceq_valid)
615 ret = i40iw_cqp_qp_create_cmd(rsrc->dev, qp); 615 ret = i40iw_cqp_qp_create_cmd(rsrc->dev, qp);
616 else 616 else
617 ret = i40iw_puda_qp_wqe(rsrc->dev, qp); 617 ret = i40iw_puda_qp_wqe(rsrc->dev, qp);
618 if (ret) 618 if (ret) {
619 i40iw_qp_rem_qos(qp);
619 i40iw_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem); 620 i40iw_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem);
621 }
620 return ret; 622 return ret;
621} 623}
622 624
@@ -704,7 +706,7 @@ static enum i40iw_status_code i40iw_puda_cq_create(struct i40iw_puda_rsrc *rsrc)
704 ret = dev->iw_priv_cq_ops->cq_init(cq, &info); 706 ret = dev->iw_priv_cq_ops->cq_init(cq, &info);
705 if (ret) 707 if (ret)
706 goto error; 708 goto error;
707 if (rsrc->ceq_valid) 709 if (rsrc->dev->ceq_valid)
708 ret = i40iw_cqp_cq_create_cmd(dev, cq); 710 ret = i40iw_cqp_cq_create_cmd(dev, cq);
709 else 711 else
710 ret = i40iw_puda_cq_wqe(dev, cq); 712 ret = i40iw_puda_cq_wqe(dev, cq);
@@ -724,7 +726,7 @@ static void i40iw_puda_free_qp(struct i40iw_puda_rsrc *rsrc)
724 struct i40iw_ccq_cqe_info compl_info; 726 struct i40iw_ccq_cqe_info compl_info;
725 struct i40iw_sc_dev *dev = rsrc->dev; 727 struct i40iw_sc_dev *dev = rsrc->dev;
726 728
727 if (rsrc->ceq_valid) { 729 if (rsrc->dev->ceq_valid) {
728 i40iw_cqp_qp_destroy_cmd(dev, &rsrc->qp); 730 i40iw_cqp_qp_destroy_cmd(dev, &rsrc->qp);
729 return; 731 return;
730 } 732 }
@@ -757,7 +759,7 @@ static void i40iw_puda_free_cq(struct i40iw_puda_rsrc *rsrc)
757 struct i40iw_ccq_cqe_info compl_info; 759 struct i40iw_ccq_cqe_info compl_info;
758 struct i40iw_sc_dev *dev = rsrc->dev; 760 struct i40iw_sc_dev *dev = rsrc->dev;
759 761
760 if (rsrc->ceq_valid) { 762 if (rsrc->dev->ceq_valid) {
761 i40iw_cqp_cq_destroy_cmd(dev, &rsrc->cq); 763 i40iw_cqp_cq_destroy_cmd(dev, &rsrc->cq);
762 return; 764 return;
763 } 765 }
@@ -813,6 +815,7 @@ void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi,
813 switch (rsrc->completion) { 815 switch (rsrc->completion) {
814 case PUDA_HASH_CRC_COMPLETE: 816 case PUDA_HASH_CRC_COMPLETE:
815 i40iw_free_hash_desc(rsrc->hash_desc); 817 i40iw_free_hash_desc(rsrc->hash_desc);
818 /* fall through */
816 case PUDA_QP_CREATED: 819 case PUDA_QP_CREATED:
817 if (!reset) 820 if (!reset)
818 i40iw_puda_free_qp(rsrc); 821 i40iw_puda_free_qp(rsrc);
@@ -921,7 +924,6 @@ enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi,
921 rsrc->xmit_complete = i40iw_ieq_tx_compl; 924 rsrc->xmit_complete = i40iw_ieq_tx_compl;
922 } 925 }
923 926
924 rsrc->ceq_valid = info->ceq_valid;
925 rsrc->type = info->type; 927 rsrc->type = info->type;
926 rsrc->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)((u8 *)vmem->va + pudasize); 928 rsrc->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)((u8 *)vmem->va + pudasize);
927 rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize); 929 rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize);
@@ -1400,7 +1402,8 @@ static void i40iw_ieq_handle_exception(struct i40iw_puda_rsrc *ieq,
1400 pfpdu->rcv_nxt = fps; 1402 pfpdu->rcv_nxt = fps;
1401 pfpdu->fps = fps; 1403 pfpdu->fps = fps;
1402 pfpdu->mode = true; 1404 pfpdu->mode = true;
1403 pfpdu->max_fpdu_data = ieq->vsi->mss; 1405 pfpdu->max_fpdu_data = (buf->ipv4) ? (ieq->vsi->mtu - I40IW_MTU_TO_MSS_IPV4) :
1406 (ieq->vsi->mtu - I40IW_MTU_TO_MSS_IPV6);
1404 pfpdu->pmode_count++; 1407 pfpdu->pmode_count++;
1405 INIT_LIST_HEAD(rxlist); 1408 INIT_LIST_HEAD(rxlist);
1406 i40iw_ieq_check_first_buf(buf, fps); 1409 i40iw_ieq_check_first_buf(buf, fps);
diff --git a/drivers/infiniband/hw/i40iw/i40iw_puda.h b/drivers/infiniband/hw/i40iw/i40iw_puda.h
index dba05ce7d392..660aa3edae56 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_puda.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_puda.h
@@ -100,7 +100,6 @@ struct i40iw_puda_rsrc_info {
100 enum puda_resource_type type; /* ILQ or IEQ */ 100 enum puda_resource_type type; /* ILQ or IEQ */
101 u32 count; 101 u32 count;
102 u16 pd_id; 102 u16 pd_id;
103 bool ceq_valid;
104 u32 cq_id; 103 u32 cq_id;
105 u32 qp_id; 104 u32 qp_id;
106 u32 sq_size; 105 u32 sq_size;
@@ -125,7 +124,6 @@ struct i40iw_puda_rsrc {
125 enum puda_resource_type type; 124 enum puda_resource_type type;
126 u16 buf_size; /*buffer must be max datalen + tcpip hdr + mac */ 125 u16 buf_size; /*buffer must be max datalen + tcpip hdr + mac */
127 u16 mss; 126 u16 mss;
128 bool ceq_valid;
129 u32 cq_id; 127 u32 cq_id;
130 u32 qp_id; 128 u32 qp_id;
131 u32 sq_size; 129 u32 sq_size;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_type.h b/drivers/infiniband/hw/i40iw/i40iw_type.h
index 63118f6d5ab4..a27d392c92a2 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_type.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_type.h
@@ -250,6 +250,7 @@ struct i40iw_vsi_pestat {
250 struct i40iw_dev_hw_stats last_read_hw_stats; 250 struct i40iw_dev_hw_stats last_read_hw_stats;
251 struct i40iw_dev_hw_stats_offsets hw_stats_offsets; 251 struct i40iw_dev_hw_stats_offsets hw_stats_offsets;
252 struct timer_list stats_timer; 252 struct timer_list stats_timer;
253 struct i40iw_sc_vsi *vsi;
253 spinlock_t lock; /* rdma stats lock */ 254 spinlock_t lock; /* rdma stats lock */
254}; 255};
255 256
@@ -380,7 +381,6 @@ struct i40iw_sc_qp {
380 u8 *q2_buf; 381 u8 *q2_buf;
381 u64 qp_compl_ctx; 382 u64 qp_compl_ctx;
382 u16 qs_handle; 383 u16 qs_handle;
383 u16 exception_lan_queue;
384 u16 push_idx; 384 u16 push_idx;
385 u8 sq_tph_val; 385 u8 sq_tph_val;
386 u8 rq_tph_val; 386 u8 rq_tph_val;
@@ -459,7 +459,8 @@ struct i40iw_sc_vsi {
459 u32 ieq_count; 459 u32 ieq_count;
460 struct i40iw_virt_mem ieq_mem; 460 struct i40iw_virt_mem ieq_mem;
461 struct i40iw_puda_rsrc *ieq; 461 struct i40iw_puda_rsrc *ieq;
462 u16 mss; 462 u16 exception_lan_queue;
463 u16 mtu;
463 u8 fcn_id; 464 u8 fcn_id;
464 bool stats_fcn_id_alloc; 465 bool stats_fcn_id_alloc;
465 struct i40iw_qos qos[I40IW_MAX_USER_PRIORITY]; 466 struct i40iw_qos qos[I40IW_MAX_USER_PRIORITY];
@@ -501,10 +502,10 @@ struct i40iw_sc_dev {
501 502
502 struct i40iw_hmc_fpm_misc hmc_fpm_misc; 503 struct i40iw_hmc_fpm_misc hmc_fpm_misc;
503 u32 debug_mask; 504 u32 debug_mask;
504 u16 exception_lan_queue;
505 u8 hmc_fn_id; 505 u8 hmc_fn_id;
506 bool is_pf; 506 bool is_pf;
507 bool vchnl_up; 507 bool vchnl_up;
508 bool ceq_valid;
508 u8 vf_id; 509 u8 vf_id;
509 wait_queue_head_t vf_reqs; 510 wait_queue_head_t vf_reqs;
510 u64 cqp_cmd_stats[OP_SIZE_CQP_STAT_ARRAY]; 511 u64 cqp_cmd_stats[OP_SIZE_CQP_STAT_ARRAY];
@@ -534,7 +535,6 @@ struct i40iw_create_qp_info {
534 bool ord_valid; 535 bool ord_valid;
535 bool tcp_ctx_valid; 536 bool tcp_ctx_valid;
536 bool cq_num_valid; 537 bool cq_num_valid;
537 bool static_rsrc;
538 bool arp_cache_idx_valid; 538 bool arp_cache_idx_valid;
539}; 539};
540 540
@@ -546,7 +546,6 @@ struct i40iw_modify_qp_info {
546 bool ord_valid; 546 bool ord_valid;
547 bool tcp_ctx_valid; 547 bool tcp_ctx_valid;
548 bool cq_num_valid; 548 bool cq_num_valid;
549 bool static_rsrc;
550 bool arp_cache_idx_valid; 549 bool arp_cache_idx_valid;
551 bool reset_tcp_conn; 550 bool reset_tcp_conn;
552 bool remove_hash_idx; 551 bool remove_hash_idx;
@@ -568,13 +567,14 @@ struct i40iw_ccq_cqe_info {
568 567
569struct i40iw_l2params { 568struct i40iw_l2params {
570 u16 qs_handle_list[I40IW_MAX_USER_PRIORITY]; 569 u16 qs_handle_list[I40IW_MAX_USER_PRIORITY];
571 u16 mss; 570 u16 mtu;
572}; 571};
573 572
574struct i40iw_vsi_init_info { 573struct i40iw_vsi_init_info {
575 struct i40iw_sc_dev *dev; 574 struct i40iw_sc_dev *dev;
576 void *back_vsi; 575 void *back_vsi;
577 struct i40iw_l2params *params; 576 struct i40iw_l2params *params;
577 u16 exception_lan_queue;
578}; 578};
579 579
580struct i40iw_vsi_stats_info { 580struct i40iw_vsi_stats_info {
@@ -592,7 +592,6 @@ struct i40iw_device_init_info {
592 struct i40iw_hw *hw; 592 struct i40iw_hw *hw;
593 void __iomem *bar0; 593 void __iomem *bar0;
594 enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16); 594 enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16);
595 u16 exception_lan_queue;
596 u8 hmc_fn_id; 595 u8 hmc_fn_id;
597 bool is_pf; 596 bool is_pf;
598 u32 debug_mask; 597 u32 debug_mask;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_uk.c b/drivers/infiniband/hw/i40iw/i40iw_uk.c
index 0aadb7a0d1aa..3ec5389a81a1 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_uk.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_uk.c
@@ -821,6 +821,18 @@ static enum i40iw_status_code i40iw_cq_poll_completion(struct i40iw_cq_uk *cq,
821 I40IW_RING_SET_TAIL(qp->rq_ring, array_idx + 1); 821 I40IW_RING_SET_TAIL(qp->rq_ring, array_idx + 1);
822 pring = &qp->rq_ring; 822 pring = &qp->rq_ring;
823 } else { 823 } else {
824 if (qp->first_sq_wq) {
825 qp->first_sq_wq = false;
826 if (!wqe_idx && (qp->sq_ring.head == qp->sq_ring.tail)) {
827 I40IW_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
828 I40IW_RING_MOVE_TAIL(cq->cq_ring);
829 set_64bit_val(cq->shadow_area, 0,
830 I40IW_RING_GETCURRENT_HEAD(cq->cq_ring));
831 memset(info, 0, sizeof(struct i40iw_cq_poll_info));
832 return i40iw_cq_poll_completion(cq, info);
833 }
834 }
835
824 if (info->comp_status != I40IW_COMPL_STATUS_FLUSHED) { 836 if (info->comp_status != I40IW_COMPL_STATUS_FLUSHED) {
825 info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; 837 info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid;
826 info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len; 838 info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len;
@@ -882,8 +894,21 @@ exit:
882} 894}
883 895
884/** 896/**
897 * i40iw_qp_roundup - return round up QP WQ depth
898 * @wqdepth: WQ depth in quantas to round up
899 */
900static int i40iw_qp_round_up(u32 wqdepth)
901{
902 int scount = 1;
903
904 for (wqdepth--; scount <= 16; scount *= 2)
905 wqdepth |= wqdepth >> scount;
906
907 return ++wqdepth;
908}
909
910/**
885 * i40iw_get_wqe_shift - get shift count for maximum wqe size 911 * i40iw_get_wqe_shift - get shift count for maximum wqe size
886 * @wqdepth: depth of wq required.
887 * @sge: Maximum Scatter Gather Elements wqe 912 * @sge: Maximum Scatter Gather Elements wqe
888 * @inline_data: Maximum inline data size 913 * @inline_data: Maximum inline data size
889 * @shift: Returns the shift needed based on sge 914 * @shift: Returns the shift needed based on sge
@@ -893,22 +918,48 @@ exit:
893 * For 2 or 3 SGEs or inline data <= 48, shift = 1 (wqe size of 64 bytes). 918 * For 2 or 3 SGEs or inline data <= 48, shift = 1 (wqe size of 64 bytes).
894 * Shift of 2 otherwise (wqe size of 128 bytes). 919 * Shift of 2 otherwise (wqe size of 128 bytes).
895 */ 920 */
896enum i40iw_status_code i40iw_get_wqe_shift(u32 wqdepth, u32 sge, u32 inline_data, u8 *shift) 921void i40iw_get_wqe_shift(u32 sge, u32 inline_data, u8 *shift)
897{ 922{
898 u32 size;
899
900 *shift = 0; 923 *shift = 0;
901 if (sge > 1 || inline_data > 16) 924 if (sge > 1 || inline_data > 16)
902 *shift = (sge < 4 && inline_data <= 48) ? 1 : 2; 925 *shift = (sge < 4 && inline_data <= 48) ? 1 : 2;
926}
903 927
904 /* check if wqdepth is multiple of 2 or not */ 928/*
929 * i40iw_get_sqdepth - get SQ depth (quantas)
930 * @sq_size: SQ size
931 * @shift: shift which determines size of WQE
932 * @sqdepth: depth of SQ
933 *
934 */
935enum i40iw_status_code i40iw_get_sqdepth(u32 sq_size, u8 shift, u32 *sqdepth)
936{
937 *sqdepth = i40iw_qp_round_up((sq_size << shift) + I40IW_SQ_RSVD);
905 938
906 if ((wqdepth < I40IWQP_SW_MIN_WQSIZE) || (wqdepth & (wqdepth - 1))) 939 if (*sqdepth < (I40IW_QP_SW_MIN_WQSIZE << shift))
940 *sqdepth = I40IW_QP_SW_MIN_WQSIZE << shift;
941 else if (*sqdepth > I40IW_QP_SW_MAX_SQ_QUANTAS)
907 return I40IW_ERR_INVALID_SIZE; 942 return I40IW_ERR_INVALID_SIZE;
908 943
909 size = wqdepth << *shift; /* multiple of 32 bytes count */ 944 return 0;
910 if (size > I40IWQP_SW_MAX_WQSIZE) 945}
946
947/*
948 * i40iw_get_rq_depth - get RQ depth (quantas)
949 * @rq_size: RQ size
950 * @shift: shift which determines size of WQE
951 * @rqdepth: depth of RQ
952 *
953 */
954enum i40iw_status_code i40iw_get_rqdepth(u32 rq_size, u8 shift, u32 *rqdepth)
955{
956 *rqdepth = i40iw_qp_round_up((rq_size << shift) + I40IW_RQ_RSVD);
957
958 if (*rqdepth < (I40IW_QP_SW_MIN_WQSIZE << shift))
959 *rqdepth = I40IW_QP_SW_MIN_WQSIZE << shift;
960 else if (*rqdepth > I40IW_QP_SW_MAX_RQ_QUANTAS)
911 return I40IW_ERR_INVALID_SIZE; 961 return I40IW_ERR_INVALID_SIZE;
962
912 return 0; 963 return 0;
913} 964}
914 965
@@ -962,9 +1013,7 @@ enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
962 1013
963 if (info->max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT) 1014 if (info->max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
964 return I40IW_ERR_INVALID_FRAG_COUNT; 1015 return I40IW_ERR_INVALID_FRAG_COUNT;
965 ret_code = i40iw_get_wqe_shift(info->sq_size, info->max_sq_frag_cnt, info->max_inline_data, &sqshift); 1016 i40iw_get_wqe_shift(info->max_sq_frag_cnt, info->max_inline_data, &sqshift);
966 if (ret_code)
967 return ret_code;
968 1017
969 qp->sq_base = info->sq; 1018 qp->sq_base = info->sq;
970 qp->rq_base = info->rq; 1019 qp->rq_base = info->rq;
@@ -988,6 +1037,7 @@ enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
988 I40IW_RING_MOVE_TAIL(qp->sq_ring); 1037 I40IW_RING_MOVE_TAIL(qp->sq_ring);
989 I40IW_RING_MOVE_HEAD(qp->initial_ring, ret_code); 1038 I40IW_RING_MOVE_HEAD(qp->initial_ring, ret_code);
990 qp->swqe_polarity = 1; 1039 qp->swqe_polarity = 1;
1040 qp->first_sq_wq = true;
991 qp->swqe_polarity_deferred = 1; 1041 qp->swqe_polarity_deferred = 1;
992 qp->rwqe_polarity = 0; 1042 qp->rwqe_polarity = 0;
993 1043
@@ -997,9 +1047,7 @@ enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
997 I40IW_RING_INIT(qp->rq_ring, qp->rq_size); 1047 I40IW_RING_INIT(qp->rq_ring, qp->rq_size);
998 switch (info->abi_ver) { 1048 switch (info->abi_ver) {
999 case 4: 1049 case 4:
1000 ret_code = i40iw_get_wqe_shift(info->rq_size, info->max_rq_frag_cnt, 0, &rqshift); 1050 i40iw_get_wqe_shift(info->max_rq_frag_cnt, 0, &rqshift);
1001 if (ret_code)
1002 return ret_code;
1003 break; 1051 break;
1004 case 5: /* fallthrough until next ABI version */ 1052 case 5: /* fallthrough until next ABI version */
1005 default: 1053 default:
diff --git a/drivers/infiniband/hw/i40iw/i40iw_user.h b/drivers/infiniband/hw/i40iw/i40iw_user.h
index 84be6f13b9c5..e73efc59a0ab 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_user.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_user.h
@@ -204,18 +204,6 @@ struct i40iw_post_inline_send {
204 u32 len; 204 u32 len;
205}; 205};
206 206
207struct i40iw_post_send_w_inv {
208 i40iw_sgl sg_list;
209 u32 num_sges;
210 i40iw_stag remote_stag_to_inv;
211};
212
213struct i40iw_post_inline_send_w_inv {
214 void *data;
215 u32 len;
216 i40iw_stag remote_stag_to_inv;
217};
218
219struct i40iw_rdma_write { 207struct i40iw_rdma_write {
220 i40iw_sgl lo_sg_list; 208 i40iw_sgl lo_sg_list;
221 u32 num_lo_sges; 209 u32 num_lo_sges;
@@ -257,9 +245,6 @@ struct i40iw_post_sq_info {
257 bool defer_flag; 245 bool defer_flag;
258 union { 246 union {
259 struct i40iw_post_send send; 247 struct i40iw_post_send send;
260 struct i40iw_post_send send_w_sol;
261 struct i40iw_post_send_w_inv send_w_inv;
262 struct i40iw_post_send_w_inv send_w_sol_inv;
263 struct i40iw_rdma_write rdma_write; 248 struct i40iw_rdma_write rdma_write;
264 struct i40iw_rdma_read rdma_read; 249 struct i40iw_rdma_read rdma_read;
265 struct i40iw_rdma_read rdma_read_inv; 250 struct i40iw_rdma_read rdma_read_inv;
@@ -267,9 +252,6 @@ struct i40iw_post_sq_info {
267 struct i40iw_inv_local_stag inv_local_stag; 252 struct i40iw_inv_local_stag inv_local_stag;
268 struct i40iw_inline_rdma_write inline_rdma_write; 253 struct i40iw_inline_rdma_write inline_rdma_write;
269 struct i40iw_post_inline_send inline_send; 254 struct i40iw_post_inline_send inline_send;
270 struct i40iw_post_inline_send inline_send_w_sol;
271 struct i40iw_post_inline_send_w_inv inline_send_w_inv;
272 struct i40iw_post_inline_send_w_inv inline_send_w_sol_inv;
273 } op; 255 } op;
274}; 256};
275 257
@@ -376,6 +358,7 @@ struct i40iw_qp_uk {
376 u8 rwqe_polarity; 358 u8 rwqe_polarity;
377 u8 rq_wqe_size; 359 u8 rq_wqe_size;
378 u8 rq_wqe_size_multiplier; 360 u8 rq_wqe_size_multiplier;
361 bool first_sq_wq;
379 bool deferred_flag; 362 bool deferred_flag;
380}; 363};
381 364
@@ -442,5 +425,7 @@ enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u32 frag_cnt, u8 *wqe_size);
442enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size); 425enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size);
443enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size, 426enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
444 u8 *wqe_size); 427 u8 *wqe_size);
445enum i40iw_status_code i40iw_get_wqe_shift(u32 wqdepth, u32 sge, u32 inline_data, u8 *shift); 428void i40iw_get_wqe_shift(u32 sge, u32 inline_data, u8 *shift);
429enum i40iw_status_code i40iw_get_sqdepth(u32 sq_size, u8 shift, u32 *sqdepth);
430enum i40iw_status_code i40iw_get_rqdepth(u32 rq_size, u8 shift, u32 *rqdepth);
446#endif 431#endif
diff --git a/drivers/infiniband/hw/i40iw/i40iw_utils.c b/drivers/infiniband/hw/i40iw/i40iw_utils.c
index e52dbbb4165e..8845dba7c438 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_utils.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_utils.c
@@ -168,11 +168,16 @@ int i40iw_inetaddr_event(struct notifier_block *notifier,
168 if (netdev != event_netdev) 168 if (netdev != event_netdev)
169 return NOTIFY_DONE; 169 return NOTIFY_DONE;
170 170
171 if (upper_dev) 171 if (upper_dev) {
172 local_ipaddr = ntohl( 172 struct in_device *in;
173 ((struct in_device *)upper_dev->ip_ptr)->ifa_list->ifa_address); 173
174 else 174 rcu_read_lock();
175 in = __in_dev_get_rcu(upper_dev);
176 local_ipaddr = ntohl(in->ifa_list->ifa_address);
177 rcu_read_unlock();
178 } else {
175 local_ipaddr = ntohl(ifa->ifa_address); 179 local_ipaddr = ntohl(ifa->ifa_address);
180 }
176 switch (event) { 181 switch (event) {
177 case NETDEV_DOWN: 182 case NETDEV_DOWN:
178 action = I40IW_ARP_DELETE; 183 action = I40IW_ARP_DELETE;
@@ -870,9 +875,9 @@ void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred)
870 * i40iw_terminate_imeout - timeout happened 875 * i40iw_terminate_imeout - timeout happened
871 * @context: points to iwarp qp 876 * @context: points to iwarp qp
872 */ 877 */
873static void i40iw_terminate_timeout(unsigned long context) 878static void i40iw_terminate_timeout(struct timer_list *t)
874{ 879{
875 struct i40iw_qp *iwqp = (struct i40iw_qp *)context; 880 struct i40iw_qp *iwqp = from_timer(iwqp, t, terminate_timer);
876 struct i40iw_sc_qp *qp = (struct i40iw_sc_qp *)&iwqp->sc_qp; 881 struct i40iw_sc_qp *qp = (struct i40iw_sc_qp *)&iwqp->sc_qp;
877 882
878 i40iw_terminate_done(qp, 1); 883 i40iw_terminate_done(qp, 1);
@@ -889,8 +894,7 @@ void i40iw_terminate_start_timer(struct i40iw_sc_qp *qp)
889 894
890 iwqp = (struct i40iw_qp *)qp->back_qp; 895 iwqp = (struct i40iw_qp *)qp->back_qp;
891 i40iw_add_ref(&iwqp->ibqp); 896 i40iw_add_ref(&iwqp->ibqp);
892 setup_timer(&iwqp->terminate_timer, i40iw_terminate_timeout, 897 timer_setup(&iwqp->terminate_timer, i40iw_terminate_timeout, 0);
893 (unsigned long)iwqp);
894 iwqp->terminate_timer.expires = jiffies + HZ; 898 iwqp->terminate_timer.expires = jiffies + HZ;
895 add_timer(&iwqp->terminate_timer); 899 add_timer(&iwqp->terminate_timer);
896} 900}
@@ -1445,11 +1449,12 @@ enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_in
1445 * i40iw_hw_stats_timeout - Stats timer-handler which updates all HW stats 1449 * i40iw_hw_stats_timeout - Stats timer-handler which updates all HW stats
1446 * @vsi: pointer to the vsi structure 1450 * @vsi: pointer to the vsi structure
1447 */ 1451 */
1448static void i40iw_hw_stats_timeout(unsigned long vsi) 1452static void i40iw_hw_stats_timeout(struct timer_list *t)
1449{ 1453{
1450 struct i40iw_sc_vsi *sc_vsi = (struct i40iw_sc_vsi *)vsi; 1454 struct i40iw_vsi_pestat *pf_devstat = from_timer(pf_devstat, t,
1455 stats_timer);
1456 struct i40iw_sc_vsi *sc_vsi = pf_devstat->vsi;
1451 struct i40iw_sc_dev *pf_dev = sc_vsi->dev; 1457 struct i40iw_sc_dev *pf_dev = sc_vsi->dev;
1452 struct i40iw_vsi_pestat *pf_devstat = sc_vsi->pestat;
1453 struct i40iw_vsi_pestat *vf_devstat = NULL; 1458 struct i40iw_vsi_pestat *vf_devstat = NULL;
1454 u16 iw_vf_idx; 1459 u16 iw_vf_idx;
1455 unsigned long flags; 1460 unsigned long flags;
@@ -1480,8 +1485,7 @@ void i40iw_hw_stats_start_timer(struct i40iw_sc_vsi *vsi)
1480{ 1485{
1481 struct i40iw_vsi_pestat *devstat = vsi->pestat; 1486 struct i40iw_vsi_pestat *devstat = vsi->pestat;
1482 1487
1483 setup_timer(&devstat->stats_timer, i40iw_hw_stats_timeout, 1488 timer_setup(&devstat->stats_timer, i40iw_hw_stats_timeout, 0);
1484 (unsigned long)vsi);
1485 mod_timer(&devstat->stats_timer, 1489 mod_timer(&devstat->stats_timer,
1486 jiffies + msecs_to_jiffies(STATS_TIMER_DELAY)); 1490 jiffies + msecs_to_jiffies(STATS_TIMER_DELAY));
1487} 1491}
diff --git a/drivers/infiniband/hw/i40iw/i40iw_verbs.c b/drivers/infiniband/hw/i40iw/i40iw_verbs.c
index 62be0a41ad0b..3c6f3ce88f89 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_verbs.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_verbs.c
@@ -69,7 +69,7 @@ static int i40iw_query_device(struct ib_device *ibdev,
69 props->hw_ver = (u32)iwdev->sc_dev.hw_rev; 69 props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
70 props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE; 70 props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
71 props->max_qp = iwdev->max_qp - iwdev->used_qps; 71 props->max_qp = iwdev->max_qp - iwdev->used_qps;
72 props->max_qp_wr = (I40IW_MAX_WQ_ENTRIES >> 2) - 1; 72 props->max_qp_wr = I40IW_MAX_QP_WRS;
73 props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; 73 props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
74 props->max_cq = iwdev->max_cq - iwdev->used_cqs; 74 props->max_cq = iwdev->max_cq - iwdev->used_cqs;
75 props->max_cqe = iwdev->max_cqe; 75 props->max_cqe = iwdev->max_cqe;
@@ -381,22 +381,6 @@ static int i40iw_dealloc_pd(struct ib_pd *ibpd)
381} 381}
382 382
383/** 383/**
384 * i40iw_qp_roundup - return round up qp ring size
385 * @wr_ring_size: ring size to round up
386 */
387static int i40iw_qp_roundup(u32 wr_ring_size)
388{
389 int scount = 1;
390
391 if (wr_ring_size < I40IWQP_SW_MIN_WQSIZE)
392 wr_ring_size = I40IWQP_SW_MIN_WQSIZE;
393
394 for (wr_ring_size--; scount <= 16; scount *= 2)
395 wr_ring_size |= wr_ring_size >> scount;
396 return ++wr_ring_size;
397}
398
399/**
400 * i40iw_get_pbl - Retrieve pbl from a list given a virtual 384 * i40iw_get_pbl - Retrieve pbl from a list given a virtual
401 * address 385 * address
402 * @va: user virtual address 386 * @va: user virtual address
@@ -515,21 +499,19 @@ static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
515{ 499{
516 struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem; 500 struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
517 u32 sqdepth, rqdepth; 501 u32 sqdepth, rqdepth;
518 u32 sq_size, rq_size;
519 u8 sqshift; 502 u8 sqshift;
520 u32 size; 503 u32 size;
521 enum i40iw_status_code status; 504 enum i40iw_status_code status;
522 struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info; 505 struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
523 506
524 sq_size = i40iw_qp_roundup(ukinfo->sq_size + 1); 507 i40iw_get_wqe_shift(ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
525 rq_size = i40iw_qp_roundup(ukinfo->rq_size + 1); 508 status = i40iw_get_sqdepth(ukinfo->sq_size, sqshift, &sqdepth);
526
527 status = i40iw_get_wqe_shift(sq_size, ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
528 if (status) 509 if (status)
529 return -ENOMEM; 510 return -ENOMEM;
530 511
531 sqdepth = sq_size << sqshift; 512 status = i40iw_get_rqdepth(ukinfo->rq_size, I40IW_MAX_RQ_WQE_SHIFT, &rqdepth);
532 rqdepth = rq_size << I40IW_MAX_RQ_WQE_SHIFT; 513 if (status)
514 return -ENOMEM;
533 515
534 size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3); 516 size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
535 iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL); 517 iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
@@ -559,8 +541,8 @@ static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
559 ukinfo->shadow_area = ukinfo->rq[rqdepth].elem; 541 ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
560 info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE); 542 info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
561 543
562 ukinfo->sq_size = sq_size; 544 ukinfo->sq_size = sqdepth >> sqshift;
563 ukinfo->rq_size = rq_size; 545 ukinfo->rq_size = rqdepth >> I40IW_MAX_RQ_WQE_SHIFT;
564 ukinfo->qp_id = iwqp->ibqp.qp_num; 546 ukinfo->qp_id = iwqp->ibqp.qp_num;
565 return 0; 547 return 0;
566} 548}
@@ -2204,6 +2186,12 @@ static int i40iw_post_send(struct ib_qp *ibqp,
2204 ukqp = &iwqp->sc_qp.qp_uk; 2186 ukqp = &iwqp->sc_qp.qp_uk;
2205 2187
2206 spin_lock_irqsave(&iwqp->lock, flags); 2188 spin_lock_irqsave(&iwqp->lock, flags);
2189
2190 if (iwqp->flush_issued) {
2191 err = -EINVAL;
2192 goto out;
2193 }
2194
2207 while (ib_wr) { 2195 while (ib_wr) {
2208 inv_stag = false; 2196 inv_stag = false;
2209 memset(&info, 0, sizeof(info)); 2197 memset(&info, 0, sizeof(info));
@@ -2346,6 +2334,7 @@ static int i40iw_post_send(struct ib_qp *ibqp,
2346 ib_wr = ib_wr->next; 2334 ib_wr = ib_wr->next;
2347 } 2335 }
2348 2336
2337out:
2349 if (err) 2338 if (err)
2350 *bad_wr = ib_wr; 2339 *bad_wr = ib_wr;
2351 else 2340 else
@@ -2378,6 +2367,12 @@ static int i40iw_post_recv(struct ib_qp *ibqp,
2378 2367
2379 memset(&post_recv, 0, sizeof(post_recv)); 2368 memset(&post_recv, 0, sizeof(post_recv));
2380 spin_lock_irqsave(&iwqp->lock, flags); 2369 spin_lock_irqsave(&iwqp->lock, flags);
2370
2371 if (iwqp->flush_issued) {
2372 err = -EINVAL;
2373 goto out;
2374 }
2375
2381 while (ib_wr) { 2376 while (ib_wr) {
2382 post_recv.num_sges = ib_wr->num_sge; 2377 post_recv.num_sges = ib_wr->num_sge;
2383 post_recv.wr_id = ib_wr->wr_id; 2378 post_recv.wr_id = ib_wr->wr_id;
diff --git a/drivers/infiniband/hw/mlx4/ah.c b/drivers/infiniband/hw/mlx4/ah.c
index 538c46a73248..6dee4fdc5d67 100644
--- a/drivers/infiniband/hw/mlx4/ah.c
+++ b/drivers/infiniband/hw/mlx4/ah.c
@@ -92,12 +92,10 @@ static struct ib_ah *create_iboe_ah(struct ib_pd *pd,
92 int ret; 92 int ret;
93 93
94 memcpy(&in6, grh->dgid.raw, sizeof(in6)); 94 memcpy(&in6, grh->dgid.raw, sizeof(in6));
95 if (rdma_is_multicast_addr(&in6)) { 95 if (rdma_is_multicast_addr(&in6))
96 is_mcast = 1; 96 is_mcast = 1;
97 rdma_get_mcast_mac(&in6, ah->av.eth.mac); 97
98 } else { 98 memcpy(ah->av.eth.mac, ah_attr->roce.dmac, ETH_ALEN);
99 memcpy(ah->av.eth.mac, ah_attr->roce.dmac, ETH_ALEN);
100 }
101 ret = ib_get_cached_gid(pd->device, rdma_ah_get_port_num(ah_attr), 99 ret = ib_get_cached_gid(pd->device, rdma_ah_get_port_num(ah_attr),
102 grh->sgid_index, &sgid, &gid_attr); 100 grh->sgid_index, &sgid, &gid_attr);
103 if (ret) 101 if (ret)
diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c
index cab796341697..bf4f14a1b4fc 100644
--- a/drivers/infiniband/hw/mlx4/cq.c
+++ b/drivers/infiniband/hw/mlx4/cq.c
@@ -140,14 +140,18 @@ static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *cont
140{ 140{
141 int err; 141 int err;
142 int cqe_size = dev->dev->caps.cqe_size; 142 int cqe_size = dev->dev->caps.cqe_size;
143 int shift;
144 int n;
143 145
144 *umem = ib_umem_get(context, buf_addr, cqe * cqe_size, 146 *umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
145 IB_ACCESS_LOCAL_WRITE, 1); 147 IB_ACCESS_LOCAL_WRITE, 1);
146 if (IS_ERR(*umem)) 148 if (IS_ERR(*umem))
147 return PTR_ERR(*umem); 149 return PTR_ERR(*umem);
148 150
149 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem), 151 n = ib_umem_page_count(*umem);
150 (*umem)->page_shift, &buf->mtt); 152 shift = mlx4_ib_umem_calc_optimal_mtt_size(*umem, 0, &n);
153 err = mlx4_mtt_init(dev->dev, n, shift, &buf->mtt);
154
151 if (err) 155 if (err)
152 goto err_buf; 156 goto err_buf;
153 157
@@ -768,11 +772,13 @@ repoll:
768 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 772 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
769 case MLX4_OPCODE_RDMA_WRITE_IMM: 773 case MLX4_OPCODE_RDMA_WRITE_IMM:
770 wc->wc_flags |= IB_WC_WITH_IMM; 774 wc->wc_flags |= IB_WC_WITH_IMM;
775 /* fall through */
771 case MLX4_OPCODE_RDMA_WRITE: 776 case MLX4_OPCODE_RDMA_WRITE:
772 wc->opcode = IB_WC_RDMA_WRITE; 777 wc->opcode = IB_WC_RDMA_WRITE;
773 break; 778 break;
774 case MLX4_OPCODE_SEND_IMM: 779 case MLX4_OPCODE_SEND_IMM:
775 wc->wc_flags |= IB_WC_WITH_IMM; 780 wc->wc_flags |= IB_WC_WITH_IMM;
781 /* fall through */
776 case MLX4_OPCODE_SEND: 782 case MLX4_OPCODE_SEND:
777 case MLX4_OPCODE_SEND_INVAL: 783 case MLX4_OPCODE_SEND_INVAL:
778 wc->opcode = IB_WC_SEND; 784 wc->opcode = IB_WC_SEND;
diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c
index c636842c5be0..8c8a16791a3f 100644
--- a/drivers/infiniband/hw/mlx4/main.c
+++ b/drivers/infiniband/hw/mlx4/main.c
@@ -563,6 +563,9 @@ static int mlx4_ib_query_device(struct ib_device *ibdev,
563 props->max_wq_type_rq = props->max_qp; 563 props->max_wq_type_rq = props->max_qp;
564 } 564 }
565 565
566 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
567 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
568
566 if (!mlx4_is_slave(dev->dev)) 569 if (!mlx4_is_slave(dev->dev))
567 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 570 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
568 571
@@ -581,6 +584,23 @@ static int mlx4_ib_query_device(struct ib_device *ibdev,
581 sizeof(struct mlx4_wqe_data_seg); 584 sizeof(struct mlx4_wqe_data_seg);
582 } 585 }
583 586
587 if (uhw->outlen >= resp.response_length + sizeof(resp.rss_caps)) {
588 resp.response_length += sizeof(resp.rss_caps);
589 if (props->rss_caps.supported_qpts) {
590 resp.rss_caps.rx_hash_function =
591 MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
592 resp.rss_caps.rx_hash_fields_mask =
593 MLX4_IB_RX_HASH_SRC_IPV4 |
594 MLX4_IB_RX_HASH_DST_IPV4 |
595 MLX4_IB_RX_HASH_SRC_IPV6 |
596 MLX4_IB_RX_HASH_DST_IPV6 |
597 MLX4_IB_RX_HASH_SRC_PORT_TCP |
598 MLX4_IB_RX_HASH_DST_PORT_TCP |
599 MLX4_IB_RX_HASH_SRC_PORT_UDP |
600 MLX4_IB_RX_HASH_DST_PORT_UDP;
601 }
602 }
603
584 if (uhw->outlen) { 604 if (uhw->outlen) {
585 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 605 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
586 if (err) 606 if (err)
@@ -2733,6 +2753,9 @@ static void *mlx4_ib_add(struct mlx4_dev *dev)
2733 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; 2753 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
2734 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; 2754 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
2735 2755
2756 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2757 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
2758
2736 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2759 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
2737 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2760 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
2738 IB_LINK_LAYER_ETHERNET) || 2761 IB_LINK_LAYER_ETHERNET) ||
diff --git a/drivers/infiniband/hw/mlx4/mcg.c b/drivers/infiniband/hw/mlx4/mcg.c
index 70eb9f917303..81ffc007e0a1 100644
--- a/drivers/infiniband/hw/mlx4/mcg.c
+++ b/drivers/infiniband/hw/mlx4/mcg.c
@@ -944,6 +944,7 @@ int mlx4_ib_mcg_multiplex_handler(struct ib_device *ibdev, int port,
944 switch (sa_mad->mad_hdr.method) { 944 switch (sa_mad->mad_hdr.method) {
945 case IB_MGMT_METHOD_SET: 945 case IB_MGMT_METHOD_SET:
946 may_create = 1; 946 may_create = 1;
947 /* fall through */
947 case IB_SA_METHOD_DELETE: 948 case IB_SA_METHOD_DELETE:
948 req = kzalloc(sizeof *req, GFP_KERNEL); 949 req = kzalloc(sizeof *req, GFP_KERNEL);
949 if (!req) 950 if (!req)
diff --git a/drivers/infiniband/hw/mlx4/mlx4_ib.h b/drivers/infiniband/hw/mlx4/mlx4_ib.h
index 1fa19820355a..e14919c15b06 100644
--- a/drivers/infiniband/hw/mlx4/mlx4_ib.h
+++ b/drivers/infiniband/hw/mlx4/mlx4_ib.h
@@ -47,6 +47,7 @@
47#include <linux/mlx4/device.h> 47#include <linux/mlx4/device.h>
48#include <linux/mlx4/doorbell.h> 48#include <linux/mlx4/doorbell.h>
49#include <linux/mlx4/qp.h> 49#include <linux/mlx4/qp.h>
50#include <linux/mlx4/cq.h>
50 51
51#define MLX4_IB_DRV_NAME "mlx4_ib" 52#define MLX4_IB_DRV_NAME "mlx4_ib"
52 53
@@ -644,12 +645,18 @@ enum query_device_resp_mask {
644 QUERY_DEVICE_RESP_MASK_TIMESTAMP = 1UL << 0, 645 QUERY_DEVICE_RESP_MASK_TIMESTAMP = 1UL << 0,
645}; 646};
646 647
648struct mlx4_ib_rss_caps {
649 __u64 rx_hash_fields_mask; /* enum mlx4_rx_hash_fields */
650 __u8 rx_hash_function; /* enum mlx4_rx_hash_function_flags */
651 __u8 reserved[7];
652};
653
647struct mlx4_uverbs_ex_query_device_resp { 654struct mlx4_uverbs_ex_query_device_resp {
648 __u32 comp_mask; 655 __u32 comp_mask;
649 __u32 response_length; 656 __u32 response_length;
650 __u64 hca_core_clock_offset; 657 __u64 hca_core_clock_offset;
651 __u32 max_inl_recv_sz; 658 __u32 max_inl_recv_sz;
652 __u32 reserved; 659 struct mlx4_ib_rss_caps rss_caps;
653}; 660};
654 661
655static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev) 662static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev)
@@ -929,5 +936,7 @@ struct ib_rwq_ind_table
929 struct ib_rwq_ind_table_init_attr *init_attr, 936 struct ib_rwq_ind_table_init_attr *init_attr,
930 struct ib_udata *udata); 937 struct ib_udata *udata);
931int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 938int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
939int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, u64 start_va,
940 int *num_of_mtts);
932 941
933#endif /* MLX4_IB_H */ 942#endif /* MLX4_IB_H */
diff --git a/drivers/infiniband/hw/mlx4/mr.c b/drivers/infiniband/hw/mlx4/mr.c
index e6f77f63da75..313bfb9ccb71 100644
--- a/drivers/infiniband/hw/mlx4/mr.c
+++ b/drivers/infiniband/hw/mlx4/mr.c
@@ -87,50 +87,286 @@ err_free:
87 return ERR_PTR(err); 87 return ERR_PTR(err);
88} 88}
89 89
90enum {
91 MLX4_MAX_MTT_SHIFT = 31
92};
93
94static int mlx4_ib_umem_write_mtt_block(struct mlx4_ib_dev *dev,
95 struct mlx4_mtt *mtt,
96 u64 mtt_size, u64 mtt_shift, u64 len,
97 u64 cur_start_addr, u64 *pages,
98 int *start_index, int *npages)
99{
100 u64 cur_end_addr = cur_start_addr + len;
101 u64 cur_end_addr_aligned = 0;
102 u64 mtt_entries;
103 int err = 0;
104 int k;
105
106 len += (cur_start_addr & (mtt_size - 1ULL));
107 cur_end_addr_aligned = round_up(cur_end_addr, mtt_size);
108 len += (cur_end_addr_aligned - cur_end_addr);
109 if (len & (mtt_size - 1ULL)) {
110 pr_warn("write_block: len %llx is not aligned to mtt_size %llx\n",
111 len, mtt_size);
112 return -EINVAL;
113 }
114
115 mtt_entries = (len >> mtt_shift);
116
117 /*
118 * Align the MTT start address to the mtt_size.
119 * Required to handle cases when the MR starts in the middle of an MTT
120 * record. Was not required in old code since the physical addresses
121 * provided by the dma subsystem were page aligned, which was also the
122 * MTT size.
123 */
124 cur_start_addr = round_down(cur_start_addr, mtt_size);
125 /* A new block is started ... */
126 for (k = 0; k < mtt_entries; ++k) {
127 pages[*npages] = cur_start_addr + (mtt_size * k);
128 (*npages)++;
129 /*
130 * Be friendly to mlx4_write_mtt() and pass it chunks of
131 * appropriate size.
132 */
133 if (*npages == PAGE_SIZE / sizeof(u64)) {
134 err = mlx4_write_mtt(dev->dev, mtt, *start_index,
135 *npages, pages);
136 if (err)
137 return err;
138
139 (*start_index) += *npages;
140 *npages = 0;
141 }
142 }
143
144 return 0;
145}
146
147static inline u64 alignment_of(u64 ptr)
148{
149 return ilog2(ptr & (~(ptr - 1)));
150}
151
152static int mlx4_ib_umem_calc_block_mtt(u64 next_block_start,
153 u64 current_block_end,
154 u64 block_shift)
155{
156 /* Check whether the alignment of the new block is aligned as well as
157 * the previous block.
158 * Block address must start with zeros till size of entity_size.
159 */
160 if ((next_block_start & ((1ULL << block_shift) - 1ULL)) != 0)
161 /*
162 * It is not as well aligned as the previous block-reduce the
163 * mtt size accordingly. Here we take the last right bit which
164 * is 1.
165 */
166 block_shift = alignment_of(next_block_start);
167
168 /*
169 * Check whether the alignment of the end of previous block - is it
170 * aligned as well as the start of the block
171 */
172 if (((current_block_end) & ((1ULL << block_shift) - 1ULL)) != 0)
173 /*
174 * It is not as well aligned as the start of the block -
175 * reduce the mtt size accordingly.
176 */
177 block_shift = alignment_of(current_block_end);
178
179 return block_shift;
180}
181
90int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt, 182int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt,
91 struct ib_umem *umem) 183 struct ib_umem *umem)
92{ 184{
93 u64 *pages; 185 u64 *pages;
94 int i, k, entry; 186 u64 len = 0;
95 int n;
96 int len;
97 int err = 0; 187 int err = 0;
188 u64 mtt_size;
189 u64 cur_start_addr = 0;
190 u64 mtt_shift;
191 int start_index = 0;
192 int npages = 0;
98 struct scatterlist *sg; 193 struct scatterlist *sg;
194 int i;
99 195
100 pages = (u64 *) __get_free_page(GFP_KERNEL); 196 pages = (u64 *) __get_free_page(GFP_KERNEL);
101 if (!pages) 197 if (!pages)
102 return -ENOMEM; 198 return -ENOMEM;
103 199
104 i = n = 0; 200 mtt_shift = mtt->page_shift;
201 mtt_size = 1ULL << mtt_shift;
105 202
106 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) { 203 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) {
107 len = sg_dma_len(sg) >> mtt->page_shift; 204 if (cur_start_addr + len == sg_dma_address(sg)) {
108 for (k = 0; k < len; ++k) { 205 /* still the same block */
109 pages[i++] = sg_dma_address(sg) + 206 len += sg_dma_len(sg);
110 (k << umem->page_shift); 207 continue;
111 /*
112 * Be friendly to mlx4_write_mtt() and
113 * pass it chunks of appropriate size.
114 */
115 if (i == PAGE_SIZE / sizeof (u64)) {
116 err = mlx4_write_mtt(dev->dev, mtt, n,
117 i, pages);
118 if (err)
119 goto out;
120 n += i;
121 i = 0;
122 }
123 } 208 }
209 /*
210 * A new block is started ...
211 * If len is malaligned, write an extra mtt entry to cover the
212 * misaligned area (round up the division)
213 */
214 err = mlx4_ib_umem_write_mtt_block(dev, mtt, mtt_size,
215 mtt_shift, len,
216 cur_start_addr,
217 pages, &start_index,
218 &npages);
219 if (err)
220 goto out;
221
222 cur_start_addr = sg_dma_address(sg);
223 len = sg_dma_len(sg);
124 } 224 }
125 225
126 if (i) 226 /* Handle the last block */
127 err = mlx4_write_mtt(dev->dev, mtt, n, i, pages); 227 if (len > 0) {
228 /*
229 * If len is malaligned, write an extra mtt entry to cover
230 * the misaligned area (round up the division)
231 */
232 err = mlx4_ib_umem_write_mtt_block(dev, mtt, mtt_size,
233 mtt_shift, len,
234 cur_start_addr, pages,
235 &start_index, &npages);
236 if (err)
237 goto out;
238 }
239
240 if (npages)
241 err = mlx4_write_mtt(dev->dev, mtt, start_index, npages, pages);
128 242
129out: 243out:
130 free_page((unsigned long) pages); 244 free_page((unsigned long) pages);
131 return err; 245 return err;
132} 246}
133 247
248/*
249 * Calculate optimal mtt size based on contiguous pages.
250 * Function will return also the number of pages that are not aligned to the
251 * calculated mtt_size to be added to total number of pages. For that we should
252 * check the first chunk length & last chunk length and if not aligned to
253 * mtt_size we should increment the non_aligned_pages number. All chunks in the
254 * middle already handled as part of mtt shift calculation for both their start
255 * & end addresses.
256 */
257int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, u64 start_va,
258 int *num_of_mtts)
259{
260 u64 block_shift = MLX4_MAX_MTT_SHIFT;
261 u64 min_shift = umem->page_shift;
262 u64 last_block_aligned_end = 0;
263 u64 current_block_start = 0;
264 u64 first_block_start = 0;
265 u64 current_block_len = 0;
266 u64 last_block_end = 0;
267 struct scatterlist *sg;
268 u64 current_block_end;
269 u64 misalignment_bits;
270 u64 next_block_start;
271 u64 total_len = 0;
272 int i;
273
274 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) {
275 /*
276 * Initialization - save the first chunk start as the
277 * current_block_start - block means contiguous pages.
278 */
279 if (current_block_len == 0 && current_block_start == 0) {
280 current_block_start = sg_dma_address(sg);
281 first_block_start = current_block_start;
282 /*
283 * Find the bits that are different between the physical
284 * address and the virtual address for the start of the
285 * MR.
286 * umem_get aligned the start_va to a page boundary.
287 * Therefore, we need to align the start va to the same
288 * boundary.
289 * misalignment_bits is needed to handle the case of a
290 * single memory region. In this case, the rest of the
291 * logic will not reduce the block size. If we use a
292 * block size which is bigger than the alignment of the
293 * misalignment bits, we might use the virtual page
294 * number instead of the physical page number, resulting
295 * in access to the wrong data.
296 */
297 misalignment_bits =
298 (start_va & (~(((u64)(BIT(umem->page_shift))) - 1ULL)))
299 ^ current_block_start;
300 block_shift = min(alignment_of(misalignment_bits),
301 block_shift);
302 }
303
304 /*
305 * Go over the scatter entries and check if they continue the
306 * previous scatter entry.
307 */
308 next_block_start = sg_dma_address(sg);
309 current_block_end = current_block_start + current_block_len;
310 /* If we have a split (non-contig.) between two blocks */
311 if (current_block_end != next_block_start) {
312 block_shift = mlx4_ib_umem_calc_block_mtt
313 (next_block_start,
314 current_block_end,
315 block_shift);
316
317 /*
318 * If we reached the minimum shift for 4k page we stop
319 * the loop.
320 */
321 if (block_shift <= min_shift)
322 goto end;
323
324 /*
325 * If not saved yet we are in first block - we save the
326 * length of first block to calculate the
327 * non_aligned_pages number at the end.
328 */
329 total_len += current_block_len;
330
331 /* Start a new block */
332 current_block_start = next_block_start;
333 current_block_len = sg_dma_len(sg);
334 continue;
335 }
336 /* The scatter entry is another part of the current block,
337 * increase the block size.
338 * An entry in the scatter can be larger than 4k (page) as of
339 * dma mapping which merge some blocks together.
340 */
341 current_block_len += sg_dma_len(sg);
342 }
343
344 /* Account for the last block in the total len */
345 total_len += current_block_len;
346 /* Add to the first block the misalignment that it suffers from. */
347 total_len += (first_block_start & ((1ULL << block_shift) - 1ULL));
348 last_block_end = current_block_start + current_block_len;
349 last_block_aligned_end = round_up(last_block_end, 1 << block_shift);
350 total_len += (last_block_aligned_end - last_block_end);
351
352 if (total_len & ((1ULL << block_shift) - 1ULL))
353 pr_warn("misaligned total length detected (%llu, %llu)!",
354 total_len, block_shift);
355
356 *num_of_mtts = total_len >> block_shift;
357end:
358 if (block_shift < min_shift) {
359 /*
360 * If shift is less than the min we set a warning and return the
361 * min shift.
362 */
363 pr_warn("umem_calc_optimal_mtt_size - unexpected shift %lld\n", block_shift);
364
365 block_shift = min_shift;
366 }
367 return block_shift;
368}
369
134struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 370struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
135 u64 virt_addr, int access_flags, 371 u64 virt_addr, int access_flags,
136 struct ib_udata *udata) 372 struct ib_udata *udata)
@@ -155,7 +391,7 @@ struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
155 } 391 }
156 392
157 n = ib_umem_page_count(mr->umem); 393 n = ib_umem_page_count(mr->umem);
158 shift = mr->umem->page_shift; 394 shift = mlx4_ib_umem_calc_optimal_mtt_size(mr->umem, start, &n);
159 395
160 err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, virt_addr, length, 396 err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, virt_addr, length,
161 convert_access(access_flags), n, shift, &mr->mmr); 397 convert_access(access_flags), n, shift, &mr->mmr);
diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c
index b6b33d99b0b4..013049bcdb53 100644
--- a/drivers/infiniband/hw/mlx4/qp.c
+++ b/drivers/infiniband/hw/mlx4/qp.c
@@ -1038,6 +1038,8 @@ static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
1038 struct mlx4_ib_create_wq wq; 1038 struct mlx4_ib_create_wq wq;
1039 } ucmd; 1039 } ucmd;
1040 size_t copy_len; 1040 size_t copy_len;
1041 int shift;
1042 int n;
1041 1043
1042 copy_len = (src == MLX4_IB_QP_SRC) ? 1044 copy_len = (src == MLX4_IB_QP_SRC) ?
1043 sizeof(struct mlx4_ib_create_qp) : 1045 sizeof(struct mlx4_ib_create_qp) :
@@ -1100,8 +1102,10 @@ static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
1100 goto err; 1102 goto err;
1101 } 1103 }
1102 1104
1103 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem), 1105 n = ib_umem_page_count(qp->umem);
1104 qp->umem->page_shift, &qp->mtt); 1106 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1107 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1108
1105 if (err) 1109 if (err)
1106 goto err_buf; 1110 goto err_buf;
1107 1111
@@ -2182,11 +2186,6 @@ static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2182 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2186 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2183 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2187 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2184 2188
2185 if (rwq_ind_tbl) {
2186 fill_qp_rss_context(context, qp);
2187 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2188 }
2189
2190 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2189 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2191 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2190 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2192 else { 2191 else {
@@ -2216,7 +2215,7 @@ static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2216 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2215 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2217 ilog2(dev->dev->caps.max_gso_sz); 2216 ilog2(dev->dev->caps.max_gso_sz);
2218 else 2217 else
2219 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2218 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2220 } else if (attr_mask & IB_QP_PATH_MTU) { 2219 } else if (attr_mask & IB_QP_PATH_MTU) {
2221 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2220 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2222 pr_err("path MTU (%u) is invalid\n", 2221 pr_err("path MTU (%u) is invalid\n",
@@ -2387,6 +2386,7 @@ static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2387 context->pd = cpu_to_be32(pd->pdn); 2386 context->pd = cpu_to_be32(pd->pdn);
2388 2387
2389 if (!rwq_ind_tbl) { 2388 if (!rwq_ind_tbl) {
2389 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2390 get_cqs(qp, src_type, &send_cq, &recv_cq); 2390 get_cqs(qp, src_type, &send_cq, &recv_cq);
2391 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2391 } else { /* Set dummy CQs to be compatible with HV and PRM */
2392 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2392 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
@@ -2394,7 +2394,6 @@ static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2394 } 2394 }
2395 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2395 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2396 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2396 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2397 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2398 2397
2399 /* Set "fast registration enabled" for all kernel QPs */ 2398 /* Set "fast registration enabled" for all kernel QPs */
2400 if (!ibuobject) 2399 if (!ibuobject)
@@ -2513,7 +2512,7 @@ static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2513 MLX4_IB_LINK_TYPE_ETH; 2512 MLX4_IB_LINK_TYPE_ETH;
2514 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2513 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2515 /* set QP to receive both tunneled & non-tunneled packets */ 2514 /* set QP to receive both tunneled & non-tunneled packets */
2516 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET))) 2515 if (!rwq_ind_tbl)
2517 context->srqn = cpu_to_be32(7 << 28); 2516 context->srqn = cpu_to_be32(7 << 28);
2518 } 2517 }
2519 } 2518 }
@@ -2562,6 +2561,13 @@ static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2562 } 2561 }
2563 } 2562 }
2564 2563
2564 if (rwq_ind_tbl &&
2565 cur_state == IB_QPS_RESET &&
2566 new_state == IB_QPS_INIT) {
2567 fill_qp_rss_context(context, qp);
2568 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2569 }
2570
2565 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2571 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2566 to_mlx4_state(new_state), context, optpar, 2572 to_mlx4_state(new_state), context, optpar,
2567 sqd_event, &qp->mqp); 2573 sqd_event, &qp->mqp);
diff --git a/drivers/infiniband/hw/mlx5/ah.c b/drivers/infiniband/hw/mlx5/ah.c
index 3363e29157f6..fe269f680103 100644
--- a/drivers/infiniband/hw/mlx5/ah.c
+++ b/drivers/infiniband/hw/mlx5/ah.c
@@ -89,10 +89,6 @@ struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr,
89 89
90 resp.response_length = min_resp_len; 90 resp.response_length = min_resp_len;
91 91
92 err = ib_resolve_eth_dmac(pd->device, ah_attr);
93 if (err)
94 return ERR_PTR(err);
95
96 memcpy(resp.dmac, ah_attr->roce.dmac, ETH_ALEN); 92 memcpy(resp.dmac, ah_attr->roce.dmac, ETH_ALEN);
97 err = ib_copy_to_udata(udata, &resp, resp.response_length); 93 err = ib_copy_to_udata(udata, &resp, resp.response_length);
98 if (err) 94 if (err)
diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c
index 2aa53f427685..18705cbcdc8c 100644
--- a/drivers/infiniband/hw/mlx5/cq.c
+++ b/drivers/infiniband/hw/mlx5/cq.c
@@ -124,11 +124,13 @@ static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
124 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) { 124 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
125 case MLX5_OPCODE_RDMA_WRITE_IMM: 125 case MLX5_OPCODE_RDMA_WRITE_IMM:
126 wc->wc_flags |= IB_WC_WITH_IMM; 126 wc->wc_flags |= IB_WC_WITH_IMM;
127 /* fall through */
127 case MLX5_OPCODE_RDMA_WRITE: 128 case MLX5_OPCODE_RDMA_WRITE:
128 wc->opcode = IB_WC_RDMA_WRITE; 129 wc->opcode = IB_WC_RDMA_WRITE;
129 break; 130 break;
130 case MLX5_OPCODE_SEND_IMM: 131 case MLX5_OPCODE_SEND_IMM:
131 wc->wc_flags |= IB_WC_WITH_IMM; 132 wc->wc_flags |= IB_WC_WITH_IMM;
133 /* fall through */
132 case MLX5_OPCODE_SEND: 134 case MLX5_OPCODE_SEND:
133 case MLX5_OPCODE_SEND_INVAL: 135 case MLX5_OPCODE_SEND_INVAL:
134 wc->opcode = IB_WC_SEND; 136 wc->opcode = IB_WC_SEND;
@@ -752,13 +754,13 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
752 int err; 754 int err;
753 755
754 ucmdlen = udata->inlen < sizeof(ucmd) ? 756 ucmdlen = udata->inlen < sizeof(ucmd) ?
755 (sizeof(ucmd) - sizeof(ucmd.reserved)) : sizeof(ucmd); 757 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
756 758
757 if (ib_copy_from_udata(&ucmd, udata, ucmdlen)) 759 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
758 return -EFAULT; 760 return -EFAULT;
759 761
760 if (ucmdlen == sizeof(ucmd) && 762 if (ucmdlen == sizeof(ucmd) &&
761 ucmd.reserved != 0) 763 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
762 return -EINVAL; 764 return -EINVAL;
763 765
764 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128) 766 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
@@ -802,8 +804,10 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
802 *index = to_mucontext(context)->bfregi.sys_pages[0]; 804 *index = to_mucontext(context)->bfregi.sys_pages[0];
803 805
804 if (ucmd.cqe_comp_en == 1) { 806 if (ucmd.cqe_comp_en == 1) {
805 if (unlikely((*cqe_size != 64) || 807 if (!((*cqe_size == 128 &&
806 !MLX5_CAP_GEN(dev->mdev, cqe_compression))) { 808 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
809 (*cqe_size == 64 &&
810 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
807 err = -EOPNOTSUPP; 811 err = -EOPNOTSUPP;
808 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n", 812 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
809 *cqe_size); 813 *cqe_size);
@@ -826,6 +830,19 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
826 ilog2(ucmd.cqe_comp_res_format)); 830 ilog2(ucmd.cqe_comp_res_format));
827 } 831 }
828 832
833 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
834 if (*cqe_size != 128 ||
835 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
836 err = -EOPNOTSUPP;
837 mlx5_ib_warn(dev,
838 "CQE padding is not supported for CQE size of %dB!\n",
839 *cqe_size);
840 goto err_cqb;
841 }
842
843 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
844 }
845
829 return 0; 846 return 0;
830 847
831err_cqb: 848err_cqb:
@@ -985,7 +1002,10 @@ struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
985 cq->cqe_size = cqe_size; 1002 cq->cqe_size = cqe_size;
986 1003
987 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context); 1004 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
988 MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size)); 1005 MLX5_SET(cqc, cqc, cqe_sz,
1006 cqe_sz_to_mlx_sz(cqe_size,
1007 cq->private_flags &
1008 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
989 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1009 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
990 MLX5_SET(cqc, cqc, uar_page, index); 1010 MLX5_SET(cqc, cqc, uar_page, index);
991 MLX5_SET(cqc, cqc, c_eqn, eqn); 1011 MLX5_SET(cqc, cqc, c_eqn, eqn);
@@ -1129,6 +1149,9 @@ int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1129 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) 1149 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1130 return -ENOSYS; 1150 return -ENOSYS;
1131 1151
1152 if (cq_period > MLX5_MAX_CQ_PERIOD)
1153 return -EINVAL;
1154
1132 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq, 1155 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1133 cq_period, cq_count); 1156 cq_period, cq_count);
1134 if (err) 1157 if (err)
@@ -1335,7 +1358,10 @@ int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1335 1358
1336 MLX5_SET(cqc, cqc, log_page_size, 1359 MLX5_SET(cqc, cqc, log_page_size,
1337 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1360 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1338 MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size)); 1361 MLX5_SET(cqc, cqc, cqe_sz,
1362 cqe_sz_to_mlx_sz(cqe_size,
1363 cq->private_flags &
1364 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1339 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1365 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1340 1366
1341 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE); 1367 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c
index 552f7bd4ecc3..543d0a4c8bf3 100644
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@ -715,6 +715,9 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
717 717
718 if (MLX5_CAP_GEN(mdev, end_pad))
719 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
720
718 props->vendor_part_id = mdev->pdev->device; 721 props->vendor_part_id = mdev->pdev->device;
719 props->hw_ver = mdev->pdev->revision; 722 props->hw_ver = mdev->pdev->revision;
720 723
@@ -787,6 +790,13 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
787 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 790 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
788 } 791 }
789 792
793 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
794 props->cq_caps.max_cq_moderation_count =
795 MLX5_MAX_CQ_COUNT;
796 props->cq_caps.max_cq_moderation_period =
797 MLX5_MAX_CQ_PERIOD;
798 }
799
790 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 800 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
791 resp.cqe_comp_caps.max_num = 801 resp.cqe_comp_caps.max_num =
792 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 802 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
@@ -824,8 +834,16 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
824 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 834 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
825 } 835 }
826 836
827 if (field_avail(typeof(resp), reserved, uhw->outlen)) 837 if (field_avail(typeof(resp), flags, uhw->outlen)) {
828 resp.response_length += sizeof(resp.reserved); 838 resp.response_length += sizeof(resp.flags);
839
840 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
841 resp.flags |=
842 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
843
844 if (MLX5_CAP_GEN(mdev, cqe_128_always))
845 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
846 }
829 847
830 if (field_avail(typeof(resp), sw_parsing_caps, 848 if (field_avail(typeof(resp), sw_parsing_caps,
831 uhw->outlen)) { 849 uhw->outlen)) {
@@ -848,6 +866,36 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
848 } 866 }
849 } 867 }
850 868
869 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) {
870 resp.response_length += sizeof(resp.striding_rq_caps);
871 if (MLX5_CAP_GEN(mdev, striding_rq)) {
872 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
873 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
874 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
875 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
876 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
877 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
878 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
879 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
880 resp.striding_rq_caps.supported_qpts =
881 BIT(IB_QPT_RAW_PACKET);
882 }
883 }
884
885 if (field_avail(typeof(resp), tunnel_offloads_caps,
886 uhw->outlen)) {
887 resp.response_length += sizeof(resp.tunnel_offloads_caps);
888 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
889 resp.tunnel_offloads_caps |=
890 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
891 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
892 resp.tunnel_offloads_caps |=
893 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
894 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
895 resp.tunnel_offloads_caps |=
896 MLX5_IB_TUNNELED_OFFLOADS_GRE;
897 }
898
851 if (uhw->outlen) { 899 if (uhw->outlen) {
852 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 900 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
853 901
@@ -3097,6 +3145,8 @@ static int create_umr_res(struct mlx5_ib_dev *dev)
3097 qp->real_qp = qp; 3145 qp->real_qp = qp;
3098 qp->uobject = NULL; 3146 qp->uobject = NULL;
3099 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3147 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3148 qp->send_cq = init_attr->send_cq;
3149 qp->recv_cq = init_attr->recv_cq;
3100 3150
3101 attr->qp_state = IB_QPS_INIT; 3151 attr->qp_state = IB_QPS_INIT;
3102 attr->port_num = 1; 3152 attr->port_num = 1;
@@ -3979,7 +4029,8 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3979 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 4029 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3980 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 4030 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3981 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 4031 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3982 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 4032 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
4033 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
3983 4034
3984 dev->ib_dev.query_device = mlx5_ib_query_device; 4035 dev->ib_dev.query_device = mlx5_ib_query_device;
3985 dev->ib_dev.query_port = mlx5_ib_query_port; 4036 dev->ib_dev.query_port = mlx5_ib_query_port;
diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h
index 189e80cd6b2f..6dd8cac78de2 100644
--- a/drivers/infiniband/hw/mlx5/mlx5_ib.h
+++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h
@@ -228,6 +228,7 @@ struct wr_list {
228 228
229enum mlx5_ib_rq_flags { 229enum mlx5_ib_rq_flags {
230 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 230 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
231 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
231}; 232};
232 233
233struct mlx5_ib_wq { 234struct mlx5_ib_wq {
@@ -254,8 +255,14 @@ struct mlx5_ib_wq {
254 255
255enum mlx5_ib_wq_flags { 256enum mlx5_ib_wq_flags {
256 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 257 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
258 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
257}; 259};
258 260
261#define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
262#define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
263#define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
264#define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
265
259struct mlx5_ib_rwq { 266struct mlx5_ib_rwq {
260 struct ib_wq ibwq; 267 struct ib_wq ibwq;
261 struct mlx5_core_qp core_qp; 268 struct mlx5_core_qp core_qp;
@@ -264,6 +271,9 @@ struct mlx5_ib_rwq {
264 u32 log_rq_size; 271 u32 log_rq_size;
265 u32 rq_page_offset; 272 u32 rq_page_offset;
266 u32 log_page_size; 273 u32 log_page_size;
274 u32 log_num_strides;
275 u32 two_byte_shift_en;
276 u32 single_stride_log_num_of_bytes;
267 struct ib_umem *umem; 277 struct ib_umem *umem;
268 size_t buf_size; 278 size_t buf_size;
269 unsigned int page_shift; 279 unsigned int page_shift;
@@ -389,6 +399,7 @@ struct mlx5_ib_qp {
389 struct list_head cq_send_list; 399 struct list_head cq_send_list;
390 u32 rate_limit; 400 u32 rate_limit;
391 u32 underlay_qpn; 401 u32 underlay_qpn;
402 bool tunnel_offload_en;
392}; 403};
393 404
394struct mlx5_ib_cq_buf { 405struct mlx5_ib_cq_buf {
@@ -411,6 +422,8 @@ enum mlx5_ib_qp_flags {
411 MLX5_IB_QP_RSS = 1 << 8, 422 MLX5_IB_QP_RSS = 1 << 8,
412 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 423 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9,
413 MLX5_IB_QP_UNDERLAY = 1 << 10, 424 MLX5_IB_QP_UNDERLAY = 1 << 10,
425 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11,
426 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12,
414}; 427};
415 428
416struct mlx5_umr_wr { 429struct mlx5_umr_wr {
@@ -435,6 +448,10 @@ struct mlx5_shared_mr_info {
435 struct ib_umem *umem; 448 struct ib_umem *umem;
436}; 449};
437 450
451enum mlx5_ib_cq_pr_flags {
452 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
453};
454
438struct mlx5_ib_cq { 455struct mlx5_ib_cq {
439 struct ib_cq ibcq; 456 struct ib_cq ibcq;
440 struct mlx5_core_cq mcq; 457 struct mlx5_core_cq mcq;
@@ -457,6 +474,7 @@ struct mlx5_ib_cq {
457 struct list_head wc_list; 474 struct list_head wc_list;
458 enum ib_cq_notify_flags notify_flags; 475 enum ib_cq_notify_flags notify_flags;
459 struct work_struct notify_work; 476 struct work_struct notify_work;
477 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
460}; 478};
461 479
462struct mlx5_ib_wc { 480struct mlx5_ib_wc {
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index 37bbc543847a..9beee9cef137 100644
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -1230,13 +1230,13 @@ struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1230 mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont, 1230 mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont,
1231 page_shift, order, access_flags); 1231 page_shift, order, access_flags);
1232 if (PTR_ERR(mr) == -EAGAIN) { 1232 if (PTR_ERR(mr) == -EAGAIN) {
1233 mlx5_ib_dbg(dev, "cache empty for order %d", order); 1233 mlx5_ib_dbg(dev, "cache empty for order %d\n", order);
1234 mr = NULL; 1234 mr = NULL;
1235 } 1235 }
1236 } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { 1236 } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) {
1237 if (access_flags & IB_ACCESS_ON_DEMAND) { 1237 if (access_flags & IB_ACCESS_ON_DEMAND) {
1238 err = -EINVAL; 1238 err = -EINVAL;
1239 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB"); 1239 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n");
1240 goto error; 1240 goto error;
1241 } 1241 }
1242 use_umr = false; 1242 use_umr = false;
diff --git a/drivers/infiniband/hw/mlx5/odp.c b/drivers/infiniband/hw/mlx5/odp.c
index 3d701c7a4c91..e2197bdda89c 100644
--- a/drivers/infiniband/hw/mlx5/odp.c
+++ b/drivers/infiniband/hw/mlx5/odp.c
@@ -32,6 +32,7 @@
32 32
33#include <rdma/ib_umem.h> 33#include <rdma/ib_umem.h>
34#include <rdma/ib_umem_odp.h> 34#include <rdma/ib_umem_odp.h>
35#include <linux/kernel.h>
35 36
36#include "mlx5_ib.h" 37#include "mlx5_ib.h"
37#include "cmd.h" 38#include "cmd.h"
@@ -929,9 +930,8 @@ static int mlx5_ib_mr_initiator_pfault_handler(
929 return -EFAULT; 930 return -EFAULT;
930 } 931 }
931 932
932 if (unlikely(opcode >= sizeof(mlx5_ib_odp_opcode_cap) / 933 if (unlikely(opcode >= ARRAY_SIZE(mlx5_ib_odp_opcode_cap) ||
933 sizeof(mlx5_ib_odp_opcode_cap[0]) || 934 !(transport_caps & mlx5_ib_odp_opcode_cap[opcode]))) {
934 !(transport_caps & mlx5_ib_odp_opcode_cap[opcode]))) {
935 mlx5_ib_err(dev, "ODP fault on QP of an unsupported opcode 0x%x\n", 935 mlx5_ib_err(dev, "ODP fault on QP of an unsupported opcode 0x%x\n",
936 opcode); 936 opcode);
937 return -EFAULT; 937 return -EFAULT;
diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c
index acb79d3a4f1d..31ad28853efa 100644
--- a/drivers/infiniband/hw/mlx5/qp.c
+++ b/drivers/infiniband/hw/mlx5/qp.c
@@ -1178,8 +1178,8 @@ static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1178 1178
1179 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1179 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1181 MLX5_SET(wq, wq, end_padding_mode, 1181 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1182 MLX5_GET(qpc, qpc, end_padding_mode)); 1182 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
@@ -1204,8 +1204,16 @@ static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1205} 1205}
1206 1206
1207static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1208{
1209 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1210 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1211 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1212}
1213
1207static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1214static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1208 struct mlx5_ib_rq *rq, u32 tdn) 1215 struct mlx5_ib_rq *rq, u32 tdn,
1216 bool tunnel_offload_en)
1209{ 1217{
1210 u32 *in; 1218 u32 *in;
1211 void *tirc; 1219 void *tirc;
@@ -1221,6 +1229,8 @@ static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1221 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1229 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1222 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1230 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1223 MLX5_SET(tirc, tirc, transport_domain, tdn); 1231 MLX5_SET(tirc, tirc, transport_domain, tdn);
1232 if (tunnel_offload_en)
1233 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1224 1234
1225 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1235 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1226 1236
@@ -1266,12 +1276,15 @@ static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1266 1276
1267 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1277 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1268 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1278 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1279 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1280 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1269 err = create_raw_packet_qp_rq(dev, rq, in); 1281 err = create_raw_packet_qp_rq(dev, rq, in);
1270 if (err) 1282 if (err)
1271 goto err_destroy_sq; 1283 goto err_destroy_sq;
1272 1284
1273 1285
1274 err = create_raw_packet_qp_tir(dev, rq, tdn); 1286 err = create_raw_packet_qp_tir(dev, rq, tdn,
1287 qp->tunnel_offload_en);
1275 if (err) 1288 if (err)
1276 goto err_destroy_rq; 1289 goto err_destroy_rq;
1277 } 1290 }
@@ -1358,7 +1371,7 @@ static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1358 if (udata->outlen < min_resp_len) 1371 if (udata->outlen < min_resp_len)
1359 return -EINVAL; 1372 return -EINVAL;
1360 1373
1361 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1374 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1362 if (udata->inlen < required_cmd_sz) { 1375 if (udata->inlen < required_cmd_sz) {
1363 mlx5_ib_dbg(dev, "invalid inlen\n"); 1376 mlx5_ib_dbg(dev, "invalid inlen\n");
1364 return -EINVAL; 1377 return -EINVAL;
@@ -1381,8 +1394,20 @@ static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1381 return -EOPNOTSUPP; 1394 return -EOPNOTSUPP;
1382 } 1395 }
1383 1396
1384 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1397 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1385 mlx5_ib_dbg(dev, "invalid reserved\n"); 1398 mlx5_ib_dbg(dev, "invalid flags\n");
1399 return -EOPNOTSUPP;
1400 }
1401
1402 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1403 !tunnel_offload_supported(dev->mdev)) {
1404 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1405 return -EOPNOTSUPP;
1406 }
1407
1408 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1409 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1410 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1386 return -EOPNOTSUPP; 1411 return -EOPNOTSUPP;
1387 } 1412 }
1388 1413
@@ -1405,6 +1430,15 @@ static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1405 MLX5_SET(tirc, tirc, transport_domain, tdn); 1430 MLX5_SET(tirc, tirc, transport_domain, tdn);
1406 1431
1407 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1432 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1433
1434 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1435 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1436
1437 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1438 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1439 else
1440 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1441
1408 switch (ucmd.rx_hash_function) { 1442 switch (ucmd.rx_hash_function) {
1409 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1443 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1410 { 1444 {
@@ -1604,6 +1638,14 @@ static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1604 1638
1605 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1639 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1606 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1640 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1641 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1642 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1643 !tunnel_offload_supported(mdev)) {
1644 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1645 return -EOPNOTSUPP;
1646 }
1647 qp->tunnel_offload_en = true;
1648 }
1607 1649
1608 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1650 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1609 if (init_attr->qp_type != IB_QPT_UD || 1651 if (init_attr->qp_type != IB_QPT_UD ||
@@ -1781,6 +1823,19 @@ static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1781 qp->flags |= MLX5_IB_QP_LSO; 1823 qp->flags |= MLX5_IB_QP_LSO;
1782 } 1824 }
1783 1825
1826 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1827 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1828 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1829 err = -EOPNOTSUPP;
1830 goto err;
1831 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1832 MLX5_SET(qpc, qpc, end_padding_mode,
1833 MLX5_WQ_END_PAD_MODE_ALIGN);
1834 } else {
1835 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1836 }
1837 }
1838
1784 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1839 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1785 qp->flags & MLX5_IB_QP_UNDERLAY) { 1840 qp->flags & MLX5_IB_QP_UNDERLAY) {
1786 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1841 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
@@ -1825,6 +1880,7 @@ err_create:
1825 else if (qp->create_type == MLX5_QP_KERNEL) 1880 else if (qp->create_type == MLX5_QP_KERNEL)
1826 destroy_qp_kernel(dev, qp); 1881 destroy_qp_kernel(dev, qp);
1827 1882
1883err:
1828 kvfree(in); 1884 kvfree(in);
1829 return err; 1885 return err;
1830} 1886}
@@ -2283,8 +2339,12 @@ static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2283 if (err) 2339 if (err)
2284 return err; 2340 return err;
2285 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2341 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2286 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2342 if (qp->ibqp.qp_type == IB_QPT_RC ||
2287 grh->sgid_index); 2343 qp->ibqp.qp_type == IB_QPT_UC ||
2344 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2345 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2346 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2347 grh->sgid_index);
2288 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2348 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2289 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2349 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2290 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2350 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
@@ -3858,7 +3918,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3858 unsigned long flags; 3918 unsigned long flags;
3859 unsigned idx; 3919 unsigned idx;
3860 int err = 0; 3920 int err = 0;
3861 int inl = 0;
3862 int num_sge; 3921 int num_sge;
3863 void *seg; 3922 void *seg;
3864 int nreq; 3923 int nreq;
@@ -4053,6 +4112,7 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4053 *bad_wr = wr; 4112 *bad_wr = wr;
4054 goto out; 4113 goto out;
4055 } 4114 }
4115 /* fall through */
4056 case MLX5_IB_QPT_HW_GSI: 4116 case MLX5_IB_QPT_HW_GSI:
4057 set_datagram_seg(seg, wr); 4117 set_datagram_seg(seg, wr);
4058 seg += sizeof(struct mlx5_wqe_datagram_seg); 4118 seg += sizeof(struct mlx5_wqe_datagram_seg);
@@ -4116,7 +4176,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4116 *bad_wr = wr; 4176 *bad_wr = wr;
4117 goto out; 4177 goto out;
4118 } 4178 }
4119 inl = 1;
4120 size += sz; 4179 size += sz;
4121 } else { 4180 } else {
4122 dpseg = seg; 4181 dpseg = seg;
@@ -4707,9 +4766,27 @@ static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4707 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4766 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4708 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4767 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4709 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4768 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4710 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4769 MLX5_SET(wq, wq, wq_type,
4711 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4770 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4771 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4772 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4773 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4774 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4775 err = -EOPNOTSUPP;
4776 goto out;
4777 } else {
4778 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4779 }
4780 }
4712 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4781 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4782 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4783 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4784 MLX5_SET(wq, wq, log_wqe_stride_size,
4785 rwq->single_stride_log_num_of_bytes -
4786 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4787 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
4788 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
4789 }
4713 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4790 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4714 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4791 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4715 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4792 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
@@ -4791,7 +4868,8 @@ static int prepare_user_rq(struct ib_pd *pd,
4791 int err; 4868 int err;
4792 size_t required_cmd_sz; 4869 size_t required_cmd_sz;
4793 4870
4794 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4871 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4872 + sizeof(ucmd.single_stride_log_num_of_bytes);
4795 if (udata->inlen < required_cmd_sz) { 4873 if (udata->inlen < required_cmd_sz) {
4796 mlx5_ib_dbg(dev, "invalid inlen\n"); 4874 mlx5_ib_dbg(dev, "invalid inlen\n");
4797 return -EINVAL; 4875 return -EINVAL;
@@ -4809,14 +4887,39 @@ static int prepare_user_rq(struct ib_pd *pd,
4809 return -EFAULT; 4887 return -EFAULT;
4810 } 4888 }
4811 4889
4812 if (ucmd.comp_mask) { 4890 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
4813 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4891 mlx5_ib_dbg(dev, "invalid comp mask\n");
4814 return -EOPNOTSUPP; 4892 return -EOPNOTSUPP;
4815 } 4893 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4816 4894 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4817 if (ucmd.reserved) { 4895 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4818 mlx5_ib_dbg(dev, "invalid reserved\n"); 4896 return -EOPNOTSUPP;
4819 return -EOPNOTSUPP; 4897 }
4898 if ((ucmd.single_stride_log_num_of_bytes <
4899 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4900 (ucmd.single_stride_log_num_of_bytes >
4901 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4902 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4903 ucmd.single_stride_log_num_of_bytes,
4904 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4905 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4906 return -EINVAL;
4907 }
4908 if ((ucmd.single_wqe_log_num_of_strides >
4909 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4910 (ucmd.single_wqe_log_num_of_strides <
4911 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
4912 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
4913 ucmd.single_wqe_log_num_of_strides,
4914 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4915 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
4916 return -EINVAL;
4917 }
4918 rwq->single_stride_log_num_of_bytes =
4919 ucmd.single_stride_log_num_of_bytes;
4920 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4921 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4922 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
4820 } 4923 }
4821 4924
4822 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4925 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
@@ -5054,6 +5157,12 @@ int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5054 MLX5_SET(rqc, rqc, vsd, 5157 MLX5_SET(rqc, rqc, vsd,
5055 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5158 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5056 } 5159 }
5160
5161 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5162 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5163 err = -EOPNOTSUPP;
5164 goto out;
5165 }
5057 } 5166 }
5058 5167
5059 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5168 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
diff --git a/drivers/infiniband/hw/mthca/mthca_main.c b/drivers/infiniband/hw/mthca/mthca_main.c
index e36a9bc52268..f3e80dec1334 100644
--- a/drivers/infiniband/hw/mthca/mthca_main.c
+++ b/drivers/infiniband/hw/mthca/mthca_main.c
@@ -473,11 +473,11 @@ static int mthca_init_icm(struct mthca_dev *mdev,
473 goto err_unmap_eqp; 473 goto err_unmap_eqp;
474 } 474 }
475 475
476 mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base, 476 mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
477 dev_lim->cqc_entry_sz, 477 dev_lim->cqc_entry_sz,
478 mdev->limits.num_cqs, 478 mdev->limits.num_cqs,
479 mdev->limits.reserved_cqs, 479 mdev->limits.reserved_cqs,
480 0, 0); 480 0, 0);
481 if (!mdev->cq_table.table) { 481 if (!mdev->cq_table.table) {
482 mthca_err(mdev, "Failed to map CQ context memory, aborting.\n"); 482 mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
483 err = -ENOMEM; 483 err = -ENOMEM;
diff --git a/drivers/infiniband/hw/nes/nes.c b/drivers/infiniband/hw/nes/nes.c
index 942ca84713c9..42b68aa999fc 100644
--- a/drivers/infiniband/hw/nes/nes.c
+++ b/drivers/infiniband/hw/nes/nes.c
@@ -178,11 +178,16 @@ static int nes_inetaddr_event(struct notifier_block *notifier,
178 /* fall through */ 178 /* fall through */
179 case NETDEV_CHANGEADDR: 179 case NETDEV_CHANGEADDR:
180 /* Add the address to the IP table */ 180 /* Add the address to the IP table */
181 if (upper_dev) 181 if (upper_dev) {
182 nesvnic->local_ipaddr = 182 struct in_device *in;
183 ((struct in_device *)upper_dev->ip_ptr)->ifa_list->ifa_address; 183
184 else 184 rcu_read_lock();
185 in = __in_dev_get_rcu(upper_dev);
186 nesvnic->local_ipaddr = in->ifa_list->ifa_address;
187 rcu_read_unlock();
188 } else {
185 nesvnic->local_ipaddr = ifa->ifa_address; 189 nesvnic->local_ipaddr = ifa->ifa_address;
190 }
186 191
187 nes_write_indexed(nesdev, 192 nes_write_indexed(nesdev,
188 NES_IDX_DST_IP_ADDR+(0x10*PCI_FUNC(nesdev->pcidev->devfn)), 193 NES_IDX_DST_IP_ADDR+(0x10*PCI_FUNC(nesdev->pcidev->devfn)),
@@ -757,18 +762,18 @@ static void nes_remove(struct pci_dev *pcidev)
757 int netdev_index = 0; 762 int netdev_index = 0;
758 unsigned long flags; 763 unsigned long flags;
759 764
760 if (nesdev->netdev_count) { 765 if (nesdev->netdev_count) {
761 netdev = nesdev->netdev[netdev_index]; 766 netdev = nesdev->netdev[netdev_index];
762 if (netdev) { 767 if (netdev) {
763 netif_stop_queue(netdev); 768 netif_stop_queue(netdev);
764 unregister_netdev(netdev); 769 unregister_netdev(netdev);
765 nes_netdev_destroy(netdev); 770 nes_netdev_destroy(netdev);
766 771
767 nesdev->netdev[netdev_index] = NULL; 772 nesdev->netdev[netdev_index] = NULL;
768 nesdev->netdev_count--; 773 nesdev->netdev_count--;
769 nesdev->nesadapter->netdev_count--; 774 nesdev->nesadapter->netdev_count--;
770 }
771 } 775 }
776 }
772 777
773 nes_notifiers_registered--; 778 nes_notifiers_registered--;
774 if (nes_notifiers_registered == 0) { 779 if (nes_notifiers_registered == 0) {
diff --git a/drivers/infiniband/hw/nes/nes.h b/drivers/infiniband/hw/nes/nes.h
index 3f9e56e8b379..00c27291dc26 100644
--- a/drivers/infiniband/hw/nes/nes.h
+++ b/drivers/infiniband/hw/nes/nes.h
@@ -536,7 +536,7 @@ void nes_iwarp_ce_handler(struct nes_device *, struct nes_hw_cq *);
536int nes_destroy_cqp(struct nes_device *); 536int nes_destroy_cqp(struct nes_device *);
537int nes_nic_cm_xmit(struct sk_buff *, struct net_device *); 537int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
538void nes_recheck_link_status(struct work_struct *work); 538void nes_recheck_link_status(struct work_struct *work);
539void nes_terminate_timeout(unsigned long context); 539void nes_terminate_timeout(struct timer_list *t);
540 540
541/* nes_nic.c */ 541/* nes_nic.c */
542struct net_device *nes_netdev_init(struct nes_device *, void __iomem *); 542struct net_device *nes_netdev_init(struct nes_device *, void __iomem *);
@@ -575,8 +575,8 @@ void nes_put_cqp_request(struct nes_device *nesdev,
575 struct nes_cqp_request *cqp_request); 575 struct nes_cqp_request *cqp_request);
576void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *); 576void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *);
577int nes_arp_table(struct nes_device *, u32, u8 *, u32); 577int nes_arp_table(struct nes_device *, u32, u8 *, u32);
578void nes_mh_fix(unsigned long); 578void nes_mh_fix(struct timer_list *t);
579void nes_clc(unsigned long); 579void nes_clc(struct timer_list *t);
580void nes_dump_mem(unsigned int, void *, int); 580void nes_dump_mem(unsigned int, void *, int);
581u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32); 581u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32);
582 582
diff --git a/drivers/infiniband/hw/nes/nes_cm.c b/drivers/infiniband/hw/nes/nes_cm.c
index de4025deaa4a..c56ca2a74df5 100644
--- a/drivers/infiniband/hw/nes/nes_cm.c
+++ b/drivers/infiniband/hw/nes/nes_cm.c
@@ -840,7 +840,7 @@ static void handle_recv_entry(struct nes_cm_node *cm_node, u32 rem_node)
840/** 840/**
841 * nes_cm_timer_tick 841 * nes_cm_timer_tick
842 */ 842 */
843static void nes_cm_timer_tick(unsigned long pass) 843static void nes_cm_timer_tick(struct timer_list *unused)
844{ 844{
845 unsigned long flags; 845 unsigned long flags;
846 unsigned long nexttimeout = jiffies + NES_LONG_TIME; 846 unsigned long nexttimeout = jiffies + NES_LONG_TIME;
@@ -1389,7 +1389,6 @@ static int nes_addr_resolve_neigh(struct nes_vnic *nesvnic, u32 dst_ip, int arpi
1389 struct rtable *rt; 1389 struct rtable *rt;
1390 struct neighbour *neigh; 1390 struct neighbour *neigh;
1391 int rc = arpindex; 1391 int rc = arpindex;
1392 struct net_device *netdev;
1393 struct nes_adapter *nesadapter = nesvnic->nesdev->nesadapter; 1392 struct nes_adapter *nesadapter = nesvnic->nesdev->nesadapter;
1394 __be32 dst_ipaddr = htonl(dst_ip); 1393 __be32 dst_ipaddr = htonl(dst_ip);
1395 1394
@@ -1400,11 +1399,6 @@ static int nes_addr_resolve_neigh(struct nes_vnic *nesvnic, u32 dst_ip, int arpi
1400 return rc; 1399 return rc;
1401 } 1400 }
1402 1401
1403 if (netif_is_bond_slave(nesvnic->netdev))
1404 netdev = netdev_master_upper_dev_get(nesvnic->netdev);
1405 else
1406 netdev = nesvnic->netdev;
1407
1408 neigh = dst_neigh_lookup(&rt->dst, &dst_ipaddr); 1402 neigh = dst_neigh_lookup(&rt->dst, &dst_ipaddr);
1409 1403
1410 rcu_read_lock(); 1404 rcu_read_lock();
@@ -1768,6 +1762,7 @@ static void handle_rst_pkt(struct nes_cm_node *cm_node, struct sk_buff *skb,
1768 case NES_CM_STATE_FIN_WAIT1: 1762 case NES_CM_STATE_FIN_WAIT1:
1769 case NES_CM_STATE_LAST_ACK: 1763 case NES_CM_STATE_LAST_ACK:
1770 cm_node->cm_id->rem_ref(cm_node->cm_id); 1764 cm_node->cm_id->rem_ref(cm_node->cm_id);
1765 /* fall through */
1771 case NES_CM_STATE_TIME_WAIT: 1766 case NES_CM_STATE_TIME_WAIT:
1772 cm_node->state = NES_CM_STATE_CLOSED; 1767 cm_node->state = NES_CM_STATE_CLOSED;
1773 rem_ref_cm_node(cm_node->cm_core, cm_node); 1768 rem_ref_cm_node(cm_node->cm_core, cm_node);
@@ -2670,8 +2665,7 @@ static struct nes_cm_core *nes_cm_alloc_core(void)
2670 return NULL; 2665 return NULL;
2671 2666
2672 INIT_LIST_HEAD(&cm_core->connected_nodes); 2667 INIT_LIST_HEAD(&cm_core->connected_nodes);
2673 init_timer(&cm_core->tcp_timer); 2668 timer_setup(&cm_core->tcp_timer, nes_cm_timer_tick, 0);
2674 cm_core->tcp_timer.function = nes_cm_timer_tick;
2675 2669
2676 cm_core->mtu = NES_CM_DEFAULT_MTU; 2670 cm_core->mtu = NES_CM_DEFAULT_MTU;
2677 cm_core->state = NES_CM_STATE_INITED; 2671 cm_core->state = NES_CM_STATE_INITED;
@@ -3074,7 +3068,6 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3074 u32 crc_value; 3068 u32 crc_value;
3075 int ret; 3069 int ret;
3076 int passive_state; 3070 int passive_state;
3077 struct nes_ib_device *nesibdev;
3078 struct ib_mr *ibmr = NULL; 3071 struct ib_mr *ibmr = NULL;
3079 struct nes_pd *nespd; 3072 struct nes_pd *nespd;
3080 u64 tagged_offset; 3073 u64 tagged_offset;
@@ -3157,7 +3150,6 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3157 3150
3158 if (raddr->sin_addr.s_addr != laddr->sin_addr.s_addr) { 3151 if (raddr->sin_addr.s_addr != laddr->sin_addr.s_addr) {
3159 u64temp = (unsigned long)nesqp; 3152 u64temp = (unsigned long)nesqp;
3160 nesibdev = nesvnic->nesibdev;
3161 nespd = nesqp->nespd; 3153 nespd = nesqp->nespd;
3162 tagged_offset = (u64)(unsigned long)*start_buff; 3154 tagged_offset = (u64)(unsigned long)*start_buff;
3163 ibmr = nes_reg_phys_mr(&nespd->ibpd, 3155 ibmr = nes_reg_phys_mr(&nespd->ibpd,
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c
index b0adf65e4bdb..18a7de1c3923 100644
--- a/drivers/infiniband/hw/nes/nes_hw.c
+++ b/drivers/infiniband/hw/nes/nes_hw.c
@@ -381,6 +381,7 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
381 sizeof nesadapter->pft_mcast_map); 381 sizeof nesadapter->pft_mcast_map);
382 382
383 /* populate the new nesadapter */ 383 /* populate the new nesadapter */
384 nesadapter->nesdev = nesdev;
384 nesadapter->devfn = nesdev->pcidev->devfn; 385 nesadapter->devfn = nesdev->pcidev->devfn;
385 nesadapter->bus_number = nesdev->pcidev->bus->number; 386 nesadapter->bus_number = nesdev->pcidev->bus->number;
386 nesadapter->ref_count = 1; 387 nesadapter->ref_count = 1;
@@ -598,19 +599,15 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
598 } 599 }
599 600
600 if (nesadapter->hw_rev == NE020_REV) { 601 if (nesadapter->hw_rev == NE020_REV) {
601 init_timer(&nesadapter->mh_timer); 602 timer_setup(&nesadapter->mh_timer, nes_mh_fix, 0);
602 nesadapter->mh_timer.function = nes_mh_fix;
603 nesadapter->mh_timer.expires = jiffies + (HZ/5); /* 1 second */ 603 nesadapter->mh_timer.expires = jiffies + (HZ/5); /* 1 second */
604 nesadapter->mh_timer.data = (unsigned long)nesdev;
605 add_timer(&nesadapter->mh_timer); 604 add_timer(&nesadapter->mh_timer);
606 } else { 605 } else {
607 nes_write32(nesdev->regs+NES_INTF_INT_STAT, 0x0f000000); 606 nes_write32(nesdev->regs+NES_INTF_INT_STAT, 0x0f000000);
608 } 607 }
609 608
610 init_timer(&nesadapter->lc_timer); 609 timer_setup(&nesadapter->lc_timer, nes_clc, 0);
611 nesadapter->lc_timer.function = nes_clc;
612 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */ 610 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
613 nesadapter->lc_timer.data = (unsigned long)nesdev;
614 add_timer(&nesadapter->lc_timer); 611 add_timer(&nesadapter->lc_timer);
615 612
616 list_add_tail(&nesadapter->list, &nes_adapter_list); 613 list_add_tail(&nesadapter->list, &nes_adapter_list);
@@ -1623,9 +1620,9 @@ static void nes_replenish_nic_rq(struct nes_vnic *nesvnic)
1623/** 1620/**
1624 * nes_rq_wqes_timeout 1621 * nes_rq_wqes_timeout
1625 */ 1622 */
1626static void nes_rq_wqes_timeout(unsigned long parm) 1623static void nes_rq_wqes_timeout(struct timer_list *t)
1627{ 1624{
1628 struct nes_vnic *nesvnic = (struct nes_vnic *)parm; 1625 struct nes_vnic *nesvnic = from_timer(nesvnic, t, rq_wqes_timer);
1629 printk("%s: Timer fired.\n", __func__); 1626 printk("%s: Timer fired.\n", __func__);
1630 atomic_set(&nesvnic->rx_skb_timer_running, 0); 1627 atomic_set(&nesvnic->rx_skb_timer_running, 0);
1631 if (atomic_read(&nesvnic->rx_skbs_needed)) 1628 if (atomic_read(&nesvnic->rx_skbs_needed))
@@ -1849,8 +1846,7 @@ int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
1849 wqe_count -= counter; 1846 wqe_count -= counter;
1850 nes_write32(nesdev->regs+NES_WQE_ALLOC, (counter << 24) | nesvnic->nic.qp_id); 1847 nes_write32(nesdev->regs+NES_WQE_ALLOC, (counter << 24) | nesvnic->nic.qp_id);
1851 } while (wqe_count); 1848 } while (wqe_count);
1852 setup_timer(&nesvnic->rq_wqes_timer, nes_rq_wqes_timeout, 1849 timer_setup(&nesvnic->rq_wqes_timer, nes_rq_wqes_timeout, 0);
1853 (unsigned long)nesvnic);
1854 nes_debug(NES_DBG_INIT, "NAPI support Enabled\n"); 1850 nes_debug(NES_DBG_INIT, "NAPI support Enabled\n");
1855 if (nesdev->nesadapter->et_use_adaptive_rx_coalesce) 1851 if (nesdev->nesadapter->et_use_adaptive_rx_coalesce)
1856 { 1852 {
@@ -1861,8 +1857,9 @@ int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
1861 } 1857 }
1862 if ((nesdev->nesadapter->allow_unaligned_fpdus) && 1858 if ((nesdev->nesadapter->allow_unaligned_fpdus) &&
1863 (nes_init_mgt_qp(nesdev, netdev, nesvnic))) { 1859 (nes_init_mgt_qp(nesdev, netdev, nesvnic))) {
1864 nes_debug(NES_DBG_INIT, "%s: Out of memory for pau nic\n", netdev->name); 1860 nes_debug(NES_DBG_INIT, "%s: Out of memory for pau nic\n",
1865 nes_destroy_nic_qp(nesvnic); 1861 netdev->name);
1862 nes_destroy_nic_qp(nesvnic);
1866 return -ENOMEM; 1863 return -ENOMEM;
1867 } 1864 }
1868 1865
@@ -3474,9 +3471,9 @@ static void nes_terminate_received(struct nes_device *nesdev,
3474} 3471}
3475 3472
3476/* Timeout routine in case terminate fails to complete */ 3473/* Timeout routine in case terminate fails to complete */
3477void nes_terminate_timeout(unsigned long context) 3474void nes_terminate_timeout(struct timer_list *t)
3478{ 3475{
3479 struct nes_qp *nesqp = (struct nes_qp *)(unsigned long)context; 3476 struct nes_qp *nesqp = from_timer(nesqp, t, terminate_timer);
3480 3477
3481 nes_terminate_done(nesqp, 1); 3478 nes_terminate_done(nesqp, 1);
3482} 3479}
@@ -3631,7 +3628,7 @@ static void nes_process_iwarp_aeqe(struct nes_device *nesdev,
3631 aeq_info |= NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE; 3628 aeq_info |= NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE;
3632 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = cpu_to_le32(aeq_info); 3629 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = cpu_to_le32(aeq_info);
3633 } 3630 }
3634 3631 /* fall through */
3635 case NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE: 3632 case NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE:
3636 case NES_AEQE_AEID_LLP_TOO_MANY_RETRIES: 3633 case NES_AEQE_AEID_LLP_TOO_MANY_RETRIES:
3637 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE: 3634 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h
index 1b66ef1e9937..3c56470816a8 100644
--- a/drivers/infiniband/hw/nes/nes_hw.h
+++ b/drivers/infiniband/hw/nes/nes_hw.h
@@ -1164,6 +1164,7 @@ struct nes_adapter {
1164 u8 log_port; 1164 u8 log_port;
1165 1165
1166 /* PCI information */ 1166 /* PCI information */
1167 struct nes_device *nesdev;
1167 unsigned int devfn; 1168 unsigned int devfn;
1168 unsigned char bus_number; 1169 unsigned char bus_number;
1169 unsigned char OneG_Mode; 1170 unsigned char OneG_Mode;
diff --git a/drivers/infiniband/hw/nes/nes_mgt.c b/drivers/infiniband/hw/nes/nes_mgt.c
index 77226cf4ea02..21e0ebd39a05 100644
--- a/drivers/infiniband/hw/nes/nes_mgt.c
+++ b/drivers/infiniband/hw/nes/nes_mgt.c
@@ -122,9 +122,10 @@ static void nes_replenish_mgt_rq(struct nes_vnic_mgt *mgtvnic)
122/** 122/**
123 * nes_mgt_rq_wqes_timeout 123 * nes_mgt_rq_wqes_timeout
124 */ 124 */
125static void nes_mgt_rq_wqes_timeout(unsigned long parm) 125static void nes_mgt_rq_wqes_timeout(struct timer_list *t)
126{ 126{
127 struct nes_vnic_mgt *mgtvnic = (struct nes_vnic_mgt *)parm; 127 struct nes_vnic_mgt *mgtvnic = from_timer(mgtvnic, t,
128 rq_wqes_timer);
128 129
129 atomic_set(&mgtvnic->rx_skb_timer_running, 0); 130 atomic_set(&mgtvnic->rx_skb_timer_running, 0);
130 if (atomic_read(&mgtvnic->rx_skbs_needed)) 131 if (atomic_read(&mgtvnic->rx_skbs_needed))
@@ -1040,8 +1041,8 @@ int nes_init_mgt_qp(struct nes_device *nesdev, struct net_device *netdev, struct
1040 mgtvnic->mgt.rx_skb[counter] = skb; 1041 mgtvnic->mgt.rx_skb[counter] = skb;
1041 } 1042 }
1042 1043
1043 setup_timer(&mgtvnic->rq_wqes_timer, nes_mgt_rq_wqes_timeout, 1044 timer_setup(&mgtvnic->rq_wqes_timer, nes_mgt_rq_wqes_timeout,
1044 (unsigned long)mgtvnic); 1045 0);
1045 1046
1046 wqe_count = NES_MGT_WQ_COUNT - 1; 1047 wqe_count = NES_MGT_WQ_COUNT - 1;
1047 mgtvnic->mgt.rq_head = wqe_count; 1048 mgtvnic->mgt.rq_head = wqe_count;
diff --git a/drivers/infiniband/hw/nes/nes_nic.c b/drivers/infiniband/hw/nes/nes_nic.c
index 5921ea3d50ae..0a75164cedea 100644
--- a/drivers/infiniband/hw/nes/nes_nic.c
+++ b/drivers/infiniband/hw/nes/nes_nic.c
@@ -926,11 +926,10 @@ static void nes_netdev_set_multicast_list(struct net_device *netdev)
926 nesadapter->pft_mcast_map[mc_index] != 926 nesadapter->pft_mcast_map[mc_index] !=
927 nesvnic->nic_index && 927 nesvnic->nic_index &&
928 mc_index < max_pft_entries_avaiable) { 928 mc_index < max_pft_entries_avaiable) {
929 nes_debug(NES_DBG_NIC_RX, 929 nes_debug(NES_DBG_NIC_RX,
930 "mc_index=%d skipping nic_index=%d, " 930 "mc_index=%d skipping nic_index=%d, used for=%d\n",
931 "used for=%d \n", mc_index, 931 mc_index, nesvnic->nic_index,
932 nesvnic->nic_index, 932 nesadapter->pft_mcast_map[mc_index]);
933 nesadapter->pft_mcast_map[mc_index]);
934 mc_index++; 933 mc_index++;
935 } 934 }
936 if (mc_index >= max_pft_entries_avaiable) 935 if (mc_index >= max_pft_entries_avaiable)
@@ -1746,8 +1745,7 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev,
1746 nesvnic->rdma_enabled = 0; 1745 nesvnic->rdma_enabled = 0;
1747 } 1746 }
1748 nesvnic->nic_cq.cq_number = nesvnic->nic.qp_id; 1747 nesvnic->nic_cq.cq_number = nesvnic->nic.qp_id;
1749 init_timer(&nesvnic->event_timer); 1748 timer_setup(&nesvnic->event_timer, NULL, 0);
1750 nesvnic->event_timer.function = NULL;
1751 spin_lock_init(&nesvnic->tx_lock); 1749 spin_lock_init(&nesvnic->tx_lock);
1752 spin_lock_init(&nesvnic->port_ibevent_lock); 1750 spin_lock_init(&nesvnic->port_ibevent_lock);
1753 nesdev->netdev[nesdev->netdev_count] = netdev; 1751 nesdev->netdev[nesdev->netdev_count] = netdev;
diff --git a/drivers/infiniband/hw/nes/nes_utils.c b/drivers/infiniband/hw/nes/nes_utils.c
index 37331e2fdc5f..21b4a8373acf 100644
--- a/drivers/infiniband/hw/nes/nes_utils.c
+++ b/drivers/infiniband/hw/nes/nes_utils.c
@@ -740,11 +740,11 @@ int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 acti
740/** 740/**
741 * nes_mh_fix 741 * nes_mh_fix
742 */ 742 */
743void nes_mh_fix(unsigned long parm) 743void nes_mh_fix(struct timer_list *t)
744{ 744{
745 struct nes_adapter *nesadapter = from_timer(nesadapter, t, mh_timer);
746 struct nes_device *nesdev = nesadapter->nesdev;
745 unsigned long flags; 747 unsigned long flags;
746 struct nes_device *nesdev = (struct nes_device *)parm;
747 struct nes_adapter *nesadapter = nesdev->nesadapter;
748 struct nes_vnic *nesvnic; 748 struct nes_vnic *nesvnic;
749 u32 used_chunks_tx; 749 u32 used_chunks_tx;
750 u32 temp_used_chunks_tx; 750 u32 temp_used_chunks_tx;
@@ -753,7 +753,6 @@ void nes_mh_fix(unsigned long parm)
753 u32 mac_tx_frames_low; 753 u32 mac_tx_frames_low;
754 u32 mac_tx_frames_high; 754 u32 mac_tx_frames_high;
755 u32 mac_tx_pauses; 755 u32 mac_tx_pauses;
756 u32 serdes_status;
757 u32 reset_value; 756 u32 reset_value;
758 u32 tx_control; 757 u32 tx_control;
759 u32 tx_config; 758 u32 tx_config;
@@ -846,7 +845,7 @@ void nes_mh_fix(unsigned long parm)
846 } 845 }
847 846
848 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008); 847 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
849 serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0); 848 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
850 849
851 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7); 850 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
852 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000); 851 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
@@ -859,7 +858,7 @@ void nes_mh_fix(unsigned long parm)
859 } else { 858 } else {
860 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222); 859 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
861 } 860 }
862 serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0); 861 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
863 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff); 862 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
864 863
865 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control); 864 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
@@ -881,17 +880,16 @@ no_mh_work:
881/** 880/**
882 * nes_clc 881 * nes_clc
883 */ 882 */
884void nes_clc(unsigned long parm) 883void nes_clc(struct timer_list *t)
885{ 884{
885 struct nes_adapter *nesadapter = from_timer(nesadapter, t, lc_timer);
886 unsigned long flags; 886 unsigned long flags;
887 struct nes_device *nesdev = (struct nes_device *)parm;
888 struct nes_adapter *nesadapter = nesdev->nesadapter;
889 887
890 spin_lock_irqsave(&nesadapter->phy_lock, flags); 888 spin_lock_irqsave(&nesadapter->phy_lock, flags);
891 nesadapter->link_interrupt_count[0] = 0; 889 nesadapter->link_interrupt_count[0] = 0;
892 nesadapter->link_interrupt_count[1] = 0; 890 nesadapter->link_interrupt_count[1] = 0;
893 nesadapter->link_interrupt_count[2] = 0; 891 nesadapter->link_interrupt_count[2] = 0;
894 nesadapter->link_interrupt_count[3] = 0; 892 nesadapter->link_interrupt_count[3] = 0;
895 spin_unlock_irqrestore(&nesadapter->phy_lock, flags); 893 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
896 894
897 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */ 895 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c
index 442b9bdc0f03..db46b7b53fb4 100644
--- a/drivers/infiniband/hw/nes/nes_verbs.c
+++ b/drivers/infiniband/hw/nes/nes_verbs.c
@@ -1304,8 +1304,7 @@ static struct ib_qp *nes_create_qp(struct ib_pd *ibpd,
1304 init_completion(&nesqp->rq_drained); 1304 init_completion(&nesqp->rq_drained);
1305 1305
1306 nesqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR); 1306 nesqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR);
1307 setup_timer(&nesqp->terminate_timer, nes_terminate_timeout, 1307 timer_setup(&nesqp->terminate_timer, nes_terminate_timeout, 0);
1308 (unsigned long)nesqp);
1309 1308
1310 /* update the QP table */ 1309 /* update the QP table */
1311 nesdev->nesadapter->qp_table[nesqp->hwqp.qp_id-NES_FIRST_QPN] = nesqp; 1310 nesdev->nesadapter->qp_table[nesqp->hwqp.qp_id-NES_FIRST_QPN] = nesqp;
@@ -2865,11 +2864,11 @@ int nes_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2865 2864
2866 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR; 2865 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR;
2867 /* next_iwarp_state = (NES_CQP_QP_IWARP_STATE_TERMINATE | 0x02000000); */ 2866 /* next_iwarp_state = (NES_CQP_QP_IWARP_STATE_TERMINATE | 0x02000000); */
2868 if (nesqp->hte_added) { 2867 if (nesqp->hte_added) {
2869 nes_debug(NES_DBG_MOD_QP, "set CQP_QP_DEL_HTE\n"); 2868 nes_debug(NES_DBG_MOD_QP, "set CQP_QP_DEL_HTE\n");
2870 next_iwarp_state |= NES_CQP_QP_DEL_HTE; 2869 next_iwarp_state |= NES_CQP_QP_DEL_HTE;
2871 nesqp->hte_added = 0; 2870 nesqp->hte_added = 0;
2872 } 2871 }
2873 if ((nesqp->hw_tcp_state > NES_AEQE_TCP_STATE_CLOSED) && 2872 if ((nesqp->hw_tcp_state > NES_AEQE_TCP_STATE_CLOSED) &&
2874 (nesdev->iw_status) && 2873 (nesdev->iw_status) &&
2875 (nesqp->hw_tcp_state != NES_AEQE_TCP_STATE_TIME_WAIT)) { 2874 (nesqp->hw_tcp_state != NES_AEQE_TCP_STATE_TIME_WAIT)) {
@@ -3560,7 +3559,7 @@ static int nes_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *entry)
3560 entry->byte_len = le32_to_cpu(cqe.cqe_words[NES_CQE_PAYLOAD_LENGTH_IDX]); 3559 entry->byte_len = le32_to_cpu(cqe.cqe_words[NES_CQE_PAYLOAD_LENGTH_IDX]);
3561 wrid = ((u64)(le32_to_cpu(nesqp->hwqp.rq_vbase[wqe_index].wqe_words[NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX]))) | 3560 wrid = ((u64)(le32_to_cpu(nesqp->hwqp.rq_vbase[wqe_index].wqe_words[NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX]))) |
3562 ((u64)(le32_to_cpu(nesqp->hwqp.rq_vbase[wqe_index].wqe_words[NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX]))<<32); 3561 ((u64)(le32_to_cpu(nesqp->hwqp.rq_vbase[wqe_index].wqe_words[NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX]))<<32);
3563 entry->opcode = IB_WC_RECV; 3562 entry->opcode = IB_WC_RECV;
3564 3563
3565 nesqp->hwqp.rq_tail = (wqe_index+1)&(nesqp->hwqp.rq_size - 1); 3564 nesqp->hwqp.rq_tail = (wqe_index+1)&(nesqp->hwqp.rq_size - 1);
3566 if ((entry->status != IB_WC_SUCCESS) && (nesqp->hwqp.rq_tail != nesqp->hwqp.rq_head)) { 3565 if ((entry->status != IB_WC_SUCCESS) && (nesqp->hwqp.rq_tail != nesqp->hwqp.rq_head)) {
@@ -3788,9 +3787,9 @@ struct nes_ib_device *nes_init_ofa_device(struct net_device *netdev)
3788/** 3787/**
3789 * nes_handle_delayed_event 3788 * nes_handle_delayed_event
3790 */ 3789 */
3791static void nes_handle_delayed_event(unsigned long data) 3790static void nes_handle_delayed_event(struct timer_list *t)
3792{ 3791{
3793 struct nes_vnic *nesvnic = (void *) data; 3792 struct nes_vnic *nesvnic = from_timer(nesvnic, t, event_timer);
3794 3793
3795 if (nesvnic->delayed_event != nesvnic->last_dispatched_event) { 3794 if (nesvnic->delayed_event != nesvnic->last_dispatched_event) {
3796 struct ib_event event; 3795 struct ib_event event;
@@ -3820,8 +3819,7 @@ void nes_port_ibevent(struct nes_vnic *nesvnic)
3820 if (!nesvnic->event_timer.function) { 3819 if (!nesvnic->event_timer.function) {
3821 ib_dispatch_event(&event); 3820 ib_dispatch_event(&event);
3822 nesvnic->last_dispatched_event = event.event; 3821 nesvnic->last_dispatched_event = event.event;
3823 nesvnic->event_timer.function = nes_handle_delayed_event; 3822 nesvnic->event_timer.function = (TIMER_FUNC_TYPE)nes_handle_delayed_event;
3824 nesvnic->event_timer.data = (unsigned long) nesvnic;
3825 nesvnic->event_timer.expires = jiffies + NES_EVENT_DELAY; 3823 nesvnic->event_timer.expires = jiffies + NES_EVENT_DELAY;
3826 add_timer(&nesvnic->event_timer); 3824 add_timer(&nesvnic->event_timer);
3827 } else { 3825 } else {
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_ah.c b/drivers/infiniband/hw/ocrdma/ocrdma_ah.c
index d0249e463338..dec650930ca6 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_ah.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_ah.c
@@ -201,21 +201,6 @@ struct ib_ah *ocrdma_create_ah(struct ib_pd *ibpd, struct rdma_ah_attr *attr,
201 /* Get network header type for this GID */ 201 /* Get network header type for this GID */
202 ah->hdr_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid); 202 ah->hdr_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
203 203
204 if ((pd->uctx) &&
205 (!rdma_is_multicast_addr((struct in6_addr *)grh->dgid.raw)) &&
206 (!rdma_link_local_addr((struct in6_addr *)grh->dgid.raw))) {
207 status = rdma_addr_find_l2_eth_by_grh(&sgid, &grh->dgid,
208 attr->roce.dmac,
209 &vlan_tag,
210 &sgid_attr.ndev->ifindex,
211 NULL);
212 if (status) {
213 pr_err("%s(): Failed to resolve dmac from gid."
214 "status = %d\n", __func__, status);
215 goto av_conf_err;
216 }
217 }
218
219 status = set_av_attr(dev, ah, attr, &sgid, pd->id, &isvlan, vlan_tag); 204 status = set_av_attr(dev, ah, attr, &sgid, pd->id, &isvlan, vlan_tag);
220 if (status) 205 if (status)
221 goto av_conf_err; 206 goto av_conf_err;
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_hw.c b/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
index 65b166cc7437..0ba695a88b62 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
@@ -1093,7 +1093,7 @@ static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
1093 rsp = &mqe->u.rsp; 1093 rsp = &mqe->u.rsp;
1094 1094
1095 if (cqe_status || ext_status) { 1095 if (cqe_status || ext_status) {
1096 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,", 1096 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,\n",
1097 __func__, cqe_status, ext_status); 1097 __func__, cqe_status, ext_status);
1098 if (rsp) { 1098 if (rsp) {
1099 /* This is for embedded cmds. */ 1099 /* This is for embedded cmds. */
@@ -1947,7 +1947,7 @@ mbx_err:
1947 1947
1948int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey) 1948int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1949{ 1949{
1950 int status = -ENOMEM; 1950 int status;
1951 struct ocrdma_dealloc_lkey *cmd; 1951 struct ocrdma_dealloc_lkey *cmd;
1952 1952
1953 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd)); 1953 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
@@ -1956,9 +1956,7 @@ int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1956 cmd->lkey = lkey; 1956 cmd->lkey = lkey;
1957 cmd->rsvd_frmr = fr_mr ? 1 : 0; 1957 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1958 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); 1958 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1959 if (status) 1959
1960 goto mbx_err;
1961mbx_err:
1962 kfree(cmd); 1960 kfree(cmd);
1963 return status; 1961 return status;
1964} 1962}
@@ -3186,8 +3184,8 @@ void ocrdma_eqd_set_task(struct work_struct *work)
3186{ 3184{
3187 struct ocrdma_dev *dev = 3185 struct ocrdma_dev *dev =
3188 container_of(work, struct ocrdma_dev, eqd_work.work); 3186 container_of(work, struct ocrdma_dev, eqd_work.work);
3189 struct ocrdma_eq *eq = 0; 3187 struct ocrdma_eq *eq = NULL;
3190 int i, num = 0, status = -EINVAL; 3188 int i, num = 0;
3191 u64 eq_intr; 3189 u64 eq_intr;
3192 3190
3193 for (i = 0; i < dev->eq_cnt; i++) { 3191 for (i = 0; i < dev->eq_cnt; i++) {
@@ -3209,7 +3207,7 @@ void ocrdma_eqd_set_task(struct work_struct *work)
3209 } 3207 }
3210 3208
3211 if (num) 3209 if (num)
3212 status = ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num); 3210 ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num);
3213 schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000)); 3211 schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000));
3214} 3212}
3215 3213
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_stats.c b/drivers/infiniband/hw/ocrdma/ocrdma_stats.c
index 66056f9a9700..e528d7acb7f6 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_stats.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_stats.c
@@ -658,7 +658,7 @@ static ssize_t ocrdma_dbgfs_ops_write(struct file *filp,
658 if (reset) { 658 if (reset) {
659 status = ocrdma_mbx_rdma_stats(dev, true); 659 status = ocrdma_mbx_rdma_stats(dev, true);
660 if (status) { 660 if (status) {
661 pr_err("Failed to reset stats = %d", status); 661 pr_err("Failed to reset stats = %d\n", status);
662 goto err; 662 goto err;
663 } 663 }
664 } 664 }
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_verbs.c b/drivers/infiniband/hw/ocrdma/ocrdma_verbs.c
index 27d5e8d9f08d..7866fd8051f6 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_verbs.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_verbs.c
@@ -66,9 +66,7 @@ int ocrdma_query_gid(struct ib_device *ibdev, u8 port,
66 int index, union ib_gid *sgid) 66 int index, union ib_gid *sgid)
67{ 67{
68 int ret; 68 int ret;
69 struct ocrdma_dev *dev;
70 69
71 dev = get_ocrdma_dev(ibdev);
72 memset(sgid, 0, sizeof(*sgid)); 70 memset(sgid, 0, sizeof(*sgid));
73 if (index >= OCRDMA_MAX_SGID) 71 if (index >= OCRDMA_MAX_SGID)
74 return -EINVAL; 72 return -EINVAL;
@@ -2247,6 +2245,7 @@ int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2247 case IB_WR_SEND_WITH_IMM: 2245 case IB_WR_SEND_WITH_IMM:
2248 hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT); 2246 hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
2249 hdr->immdt = ntohl(wr->ex.imm_data); 2247 hdr->immdt = ntohl(wr->ex.imm_data);
2248 /* fall through */
2250 case IB_WR_SEND: 2249 case IB_WR_SEND:
2251 hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT); 2250 hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
2252 ocrdma_build_send(qp, hdr, wr); 2251 ocrdma_build_send(qp, hdr, wr);
@@ -2260,6 +2259,7 @@ int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2260 case IB_WR_RDMA_WRITE_WITH_IMM: 2259 case IB_WR_RDMA_WRITE_WITH_IMM:
2261 hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT); 2260 hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
2262 hdr->immdt = ntohl(wr->ex.imm_data); 2261 hdr->immdt = ntohl(wr->ex.imm_data);
2262 /* fall through */
2263 case IB_WR_RDMA_WRITE: 2263 case IB_WR_RDMA_WRITE:
2264 hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT); 2264 hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
2265 status = ocrdma_build_write(qp, hdr, wr); 2265 status = ocrdma_build_write(qp, hdr, wr);
diff --git a/drivers/infiniband/hw/qedr/Kconfig b/drivers/infiniband/hw/qedr/Kconfig
index 60e867d80b88..9b9e3b1d2705 100644
--- a/drivers/infiniband/hw/qedr/Kconfig
+++ b/drivers/infiniband/hw/qedr/Kconfig
@@ -1,6 +1,7 @@
1config INFINIBAND_QEDR 1config INFINIBAND_QEDR
2 tristate "QLogic RoCE driver" 2 tristate "QLogic RoCE driver"
3 depends on 64BIT && QEDE 3 depends on 64BIT && QEDE
4 depends on PCI
4 select QED_LL2 5 select QED_LL2
5 select QED_OOO 6 select QED_OOO
6 select QED_RDMA 7 select QED_RDMA
diff --git a/drivers/infiniband/hw/qedr/Makefile b/drivers/infiniband/hw/qedr/Makefile
index ba7067c77f2f..1c0bc4f78550 100644
--- a/drivers/infiniband/hw/qedr/Makefile
+++ b/drivers/infiniband/hw/qedr/Makefile
@@ -1,3 +1,3 @@
1obj-$(CONFIG_INFINIBAND_QEDR) := qedr.o 1obj-$(CONFIG_INFINIBAND_QEDR) := qedr.o
2 2
3qedr-y := main.o verbs.o qedr_cm.o 3qedr-y := main.o verbs.o qedr_roce_cm.o qedr_iw_cm.o
diff --git a/drivers/infiniband/hw/qedr/main.c b/drivers/infiniband/hw/qedr/main.c
index 97d033f51dc9..50812b33291b 100644
--- a/drivers/infiniband/hw/qedr/main.c
+++ b/drivers/infiniband/hw/qedr/main.c
@@ -33,16 +33,20 @@
33#include <rdma/ib_verbs.h> 33#include <rdma/ib_verbs.h>
34#include <rdma/ib_addr.h> 34#include <rdma/ib_addr.h>
35#include <rdma/ib_user_verbs.h> 35#include <rdma/ib_user_verbs.h>
36#include <rdma/iw_cm.h>
37#include <rdma/ib_mad.h>
36#include <linux/netdevice.h> 38#include <linux/netdevice.h>
37#include <linux/iommu.h> 39#include <linux/iommu.h>
38#include <linux/pci.h> 40#include <linux/pci.h>
39#include <net/addrconf.h> 41#include <net/addrconf.h>
42#include <linux/idr.h>
40 43
41#include <linux/qed/qed_chain.h> 44#include <linux/qed/qed_chain.h>
42#include <linux/qed/qed_if.h> 45#include <linux/qed/qed_if.h>
43#include "qedr.h" 46#include "qedr.h"
44#include "verbs.h" 47#include "verbs.h"
45#include <rdma/qedr-abi.h> 48#include <rdma/qedr-abi.h>
49#include "qedr_iw_cm.h"
46 50
47MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver"); 51MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
48MODULE_AUTHOR("QLogic Corporation"); 52MODULE_AUTHOR("QLogic Corporation");
@@ -50,8 +54,8 @@ MODULE_LICENSE("Dual BSD/GPL");
50 54
51#define QEDR_WQ_MULTIPLIER_DFT (3) 55#define QEDR_WQ_MULTIPLIER_DFT (3)
52 56
53void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num, 57static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
54 enum ib_event_type type) 58 enum ib_event_type type)
55{ 59{
56 struct ib_event ibev; 60 struct ib_event ibev;
57 61
@@ -92,8 +96,84 @@ static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num)
92 return qdev->ndev; 96 return qdev->ndev;
93} 97}
94 98
99static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
100 struct ib_port_immutable *immutable)
101{
102 struct ib_port_attr attr;
103 int err;
104
105 err = qedr_query_port(ibdev, port_num, &attr);
106 if (err)
107 return err;
108
109 immutable->pkey_tbl_len = attr.pkey_tbl_len;
110 immutable->gid_tbl_len = attr.gid_tbl_len;
111 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
112 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
113 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
114
115 return 0;
116}
117
118static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
119 struct ib_port_immutable *immutable)
120{
121 struct ib_port_attr attr;
122 int err;
123
124 err = qedr_query_port(ibdev, port_num, &attr);
125 if (err)
126 return err;
127
128 immutable->pkey_tbl_len = 1;
129 immutable->gid_tbl_len = 1;
130 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
131 immutable->max_mad_size = 0;
132
133 return 0;
134}
135
136static int qedr_iw_register_device(struct qedr_dev *dev)
137{
138 dev->ibdev.node_type = RDMA_NODE_RNIC;
139 dev->ibdev.query_gid = qedr_iw_query_gid;
140
141 dev->ibdev.get_port_immutable = qedr_iw_port_immutable;
142
143 dev->ibdev.iwcm = kzalloc(sizeof(*dev->ibdev.iwcm), GFP_KERNEL);
144 if (!dev->ibdev.iwcm)
145 return -ENOMEM;
146
147 dev->ibdev.iwcm->connect = qedr_iw_connect;
148 dev->ibdev.iwcm->accept = qedr_iw_accept;
149 dev->ibdev.iwcm->reject = qedr_iw_reject;
150 dev->ibdev.iwcm->create_listen = qedr_iw_create_listen;
151 dev->ibdev.iwcm->destroy_listen = qedr_iw_destroy_listen;
152 dev->ibdev.iwcm->add_ref = qedr_iw_qp_add_ref;
153 dev->ibdev.iwcm->rem_ref = qedr_iw_qp_rem_ref;
154 dev->ibdev.iwcm->get_qp = qedr_iw_get_qp;
155
156 memcpy(dev->ibdev.iwcm->ifname,
157 dev->ndev->name, sizeof(dev->ibdev.iwcm->ifname));
158
159 return 0;
160}
161
162static void qedr_roce_register_device(struct qedr_dev *dev)
163{
164 dev->ibdev.node_type = RDMA_NODE_IB_CA;
165 dev->ibdev.query_gid = qedr_query_gid;
166
167 dev->ibdev.add_gid = qedr_add_gid;
168 dev->ibdev.del_gid = qedr_del_gid;
169
170 dev->ibdev.get_port_immutable = qedr_roce_port_immutable;
171}
172
95static int qedr_register_device(struct qedr_dev *dev) 173static int qedr_register_device(struct qedr_dev *dev)
96{ 174{
175 int rc;
176
97 strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX); 177 strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
98 178
99 dev->ibdev.node_guid = dev->attr.node_guid; 179 dev->ibdev.node_guid = dev->attr.node_guid;
@@ -121,18 +201,21 @@ static int qedr_register_device(struct qedr_dev *dev)
121 QEDR_UVERBS(POST_SEND) | 201 QEDR_UVERBS(POST_SEND) |
122 QEDR_UVERBS(POST_RECV); 202 QEDR_UVERBS(POST_RECV);
123 203
204 if (IS_IWARP(dev)) {
205 rc = qedr_iw_register_device(dev);
206 if (rc)
207 return rc;
208 } else {
209 qedr_roce_register_device(dev);
210 }
211
124 dev->ibdev.phys_port_cnt = 1; 212 dev->ibdev.phys_port_cnt = 1;
125 dev->ibdev.num_comp_vectors = dev->num_cnq; 213 dev->ibdev.num_comp_vectors = dev->num_cnq;
126 dev->ibdev.node_type = RDMA_NODE_IB_CA;
127 214
128 dev->ibdev.query_device = qedr_query_device; 215 dev->ibdev.query_device = qedr_query_device;
129 dev->ibdev.query_port = qedr_query_port; 216 dev->ibdev.query_port = qedr_query_port;
130 dev->ibdev.modify_port = qedr_modify_port; 217 dev->ibdev.modify_port = qedr_modify_port;
131 218
132 dev->ibdev.query_gid = qedr_query_gid;
133 dev->ibdev.add_gid = qedr_add_gid;
134 dev->ibdev.del_gid = qedr_del_gid;
135
136 dev->ibdev.alloc_ucontext = qedr_alloc_ucontext; 219 dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
137 dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext; 220 dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
138 dev->ibdev.mmap = qedr_mmap; 221 dev->ibdev.mmap = qedr_mmap;
@@ -166,7 +249,7 @@ static int qedr_register_device(struct qedr_dev *dev)
166 dev->ibdev.post_recv = qedr_post_recv; 249 dev->ibdev.post_recv = qedr_post_recv;
167 250
168 dev->ibdev.process_mad = qedr_process_mad; 251 dev->ibdev.process_mad = qedr_process_mad;
169 dev->ibdev.get_port_immutable = qedr_port_immutable; 252
170 dev->ibdev.get_netdev = qedr_get_netdev; 253 dev->ibdev.get_netdev = qedr_get_netdev;
171 254
172 dev->ibdev.dev.parent = &dev->pdev->dev; 255 dev->ibdev.dev.parent = &dev->pdev->dev;
@@ -217,6 +300,9 @@ static void qedr_free_resources(struct qedr_dev *dev)
217{ 300{
218 int i; 301 int i;
219 302
303 if (IS_IWARP(dev))
304 destroy_workqueue(dev->iwarp_wq);
305
220 for (i = 0; i < dev->num_cnq; i++) { 306 for (i = 0; i < dev->num_cnq; i++) {
221 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i); 307 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
222 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl); 308 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
@@ -241,6 +327,12 @@ static int qedr_alloc_resources(struct qedr_dev *dev)
241 327
242 spin_lock_init(&dev->sgid_lock); 328 spin_lock_init(&dev->sgid_lock);
243 329
330 if (IS_IWARP(dev)) {
331 spin_lock_init(&dev->idr_lock);
332 idr_init(&dev->qpidr);
333 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
334 }
335
244 /* Allocate Status blocks for CNQ */ 336 /* Allocate Status blocks for CNQ */
245 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array), 337 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
246 GFP_KERNEL); 338 GFP_KERNEL);
@@ -597,12 +689,12 @@ static int qedr_set_device_attr(struct qedr_dev *dev)
597 return 0; 689 return 0;
598} 690}
599 691
600void qedr_unaffiliated_event(void *context, u8 event_code) 692static void qedr_unaffiliated_event(void *context, u8 event_code)
601{ 693{
602 pr_err("unaffiliated event not implemented yet\n"); 694 pr_err("unaffiliated event not implemented yet\n");
603} 695}
604 696
605void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle) 697static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
606{ 698{
607#define EVENT_TYPE_NOT_DEFINED 0 699#define EVENT_TYPE_NOT_DEFINED 0
608#define EVENT_TYPE_CQ 1 700#define EVENT_TYPE_CQ 1
@@ -716,6 +808,7 @@ static int qedr_init_hw(struct qedr_dev *dev)
716 in_params->events = &events; 808 in_params->events = &events;
717 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS; 809 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
718 in_params->max_mtu = dev->ndev->mtu; 810 in_params->max_mtu = dev->ndev->mtu;
811 dev->iwarp_max_mtu = dev->ndev->mtu;
719 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr); 812 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
720 813
721 rc = dev->ops->rdma_init(dev->cdev, in_params); 814 rc = dev->ops->rdma_init(dev->cdev, in_params);
@@ -726,7 +819,7 @@ static int qedr_init_hw(struct qedr_dev *dev)
726 if (rc) 819 if (rc)
727 goto out; 820 goto out;
728 821
729 dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr; 822 dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr;
730 dev->db_phys_addr = out_params.dpi_phys_addr; 823 dev->db_phys_addr = out_params.dpi_phys_addr;
731 dev->db_size = out_params.dpi_size; 824 dev->db_size = out_params.dpi_size;
732 dev->dpi = out_params.dpi; 825 dev->dpi = out_params.dpi;
@@ -740,7 +833,7 @@ out:
740 return rc; 833 return rc;
741} 834}
742 835
743void qedr_stop_hw(struct qedr_dev *dev) 836static void qedr_stop_hw(struct qedr_dev *dev)
744{ 837{
745 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi); 838 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
746 dev->ops->rdma_stop(dev->rdma_ctx); 839 dev->ops->rdma_stop(dev->rdma_ctx);
@@ -777,6 +870,7 @@ static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
777 goto init_err; 870 goto init_err;
778 871
779 dev->user_dpm_enabled = dev_info.user_dpm_enabled; 872 dev->user_dpm_enabled = dev_info.user_dpm_enabled;
873 dev->rdma_type = dev_info.rdma_type;
780 dev->num_hwfns = dev_info.common.num_hwfns; 874 dev->num_hwfns = dev_info.common.num_hwfns;
781 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev); 875 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
782 876
diff --git a/drivers/infiniband/hw/qedr/qedr.h b/drivers/infiniband/hw/qedr/qedr.h
index 254083b524bd..86d4511e0d75 100644
--- a/drivers/infiniband/hw/qedr/qedr.h
+++ b/drivers/infiniband/hw/qedr/qedr.h
@@ -33,6 +33,7 @@
33#define __QEDR_H__ 33#define __QEDR_H__
34 34
35#include <linux/pci.h> 35#include <linux/pci.h>
36#include <linux/idr.h>
36#include <rdma/ib_addr.h> 37#include <rdma/ib_addr.h>
37#include <linux/qed/qed_if.h> 38#include <linux/qed/qed_if.h>
38#include <linux/qed/qed_chain.h> 39#include <linux/qed/qed_chain.h>
@@ -43,6 +44,8 @@
43 44
44#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" 45#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
45#define DP_NAME(dev) ((dev)->ibdev.name) 46#define DP_NAME(dev) ((dev)->ibdev.name)
47#define IS_IWARP(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_IWARP)
48#define IS_ROCE(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_ROCE)
46 49
47#define DP_DEBUG(dev, module, fmt, ...) \ 50#define DP_DEBUG(dev, module, fmt, ...) \
48 pr_debug("(%s) " module ": " fmt, \ 51 pr_debug("(%s) " module ": " fmt, \
@@ -56,6 +59,7 @@
56#define QEDR_MSG_SQ " SQ" 59#define QEDR_MSG_SQ " SQ"
57#define QEDR_MSG_QP " QP" 60#define QEDR_MSG_QP " QP"
58#define QEDR_MSG_GSI " GSI" 61#define QEDR_MSG_GSI " GSI"
62#define QEDR_MSG_IWARP " IW"
59 63
60#define QEDR_CQ_MAGIC_NUMBER (0x11223344) 64#define QEDR_CQ_MAGIC_NUMBER (0x11223344)
61 65
@@ -160,6 +164,11 @@ struct qedr_dev {
160 struct qedr_cq *gsi_sqcq; 164 struct qedr_cq *gsi_sqcq;
161 struct qedr_cq *gsi_rqcq; 165 struct qedr_cq *gsi_rqcq;
162 struct qedr_qp *gsi_qp; 166 struct qedr_qp *gsi_qp;
167 enum qed_rdma_type rdma_type;
168 spinlock_t idr_lock; /* Protect qpidr data-structure */
169 struct idr qpidr;
170 struct workqueue_struct *iwarp_wq;
171 u16 iwarp_max_mtu;
163 172
164 unsigned long enet_state; 173 unsigned long enet_state;
165 174
@@ -317,6 +326,9 @@ struct qedr_qp_hwq_info {
317 /* DB */ 326 /* DB */
318 void __iomem *db; 327 void __iomem *db;
319 union db_prod32 db_data; 328 union db_prod32 db_data;
329
330 void __iomem *iwarp_db2;
331 union db_prod32 iwarp_db2_data;
320}; 332};
321 333
322#define QEDR_INC_SW_IDX(p_info, index) \ 334#define QEDR_INC_SW_IDX(p_info, index) \
@@ -337,7 +349,7 @@ enum qedr_qp_err_bitmap {
337struct qedr_qp { 349struct qedr_qp {
338 struct ib_qp ibqp; /* must be first */ 350 struct ib_qp ibqp; /* must be first */
339 struct qedr_dev *dev; 351 struct qedr_dev *dev;
340 352 struct qedr_iw_ep *ep;
341 struct qedr_qp_hwq_info sq; 353 struct qedr_qp_hwq_info sq;
342 struct qedr_qp_hwq_info rq; 354 struct qedr_qp_hwq_info rq;
343 355
@@ -394,6 +406,8 @@ struct qedr_qp {
394 /* Relevant to qps created from user space only (applications) */ 406 /* Relevant to qps created from user space only (applications) */
395 struct qedr_userq usq; 407 struct qedr_userq usq;
396 struct qedr_userq urq; 408 struct qedr_userq urq;
409 atomic_t refcnt;
410 bool destroyed;
397}; 411};
398 412
399struct qedr_ah { 413struct qedr_ah {
@@ -474,6 +488,21 @@ static inline int qedr_get_dmac(struct qedr_dev *dev,
474 return 0; 488 return 0;
475} 489}
476 490
491struct qedr_iw_listener {
492 struct qedr_dev *dev;
493 struct iw_cm_id *cm_id;
494 int backlog;
495 void *qed_handle;
496};
497
498struct qedr_iw_ep {
499 struct qedr_dev *dev;
500 struct iw_cm_id *cm_id;
501 struct qedr_qp *qp;
502 void *qed_context;
503 u8 during_connect;
504};
505
477static inline 506static inline
478struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) 507struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
479{ 508{
diff --git a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
index 5c98d2055cad..b7587f10e7de 100644
--- a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
+++ b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
@@ -655,8 +655,10 @@ struct rdma_sq_rdma_wqe_1st {
655#define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT 4 655#define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT 4
656#define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1 656#define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1
657#define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_SHIFT 5 657#define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_SHIFT 5
658#define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x3 658#define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_MASK 0x1
659#define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT 6 659#define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_SHIFT 6
660#define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x1
661#define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT 7
660 u8 wqe_size; 662 u8 wqe_size;
661 u8 prev_wqe_size; 663 u8 prev_wqe_size;
662}; 664};
diff --git a/drivers/infiniband/hw/qedr/qedr_iw_cm.c b/drivers/infiniband/hw/qedr/qedr_iw_cm.c
new file mode 100644
index 000000000000..478b7317b80a
--- /dev/null
+++ b/drivers/infiniband/hw/qedr/qedr_iw_cm.c
@@ -0,0 +1,749 @@
1/* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <net/ip.h>
33#include <net/ipv6.h>
34#include <net/udp.h>
35#include <net/addrconf.h>
36#include <net/route.h>
37#include <net/ip6_route.h>
38#include <net/flow.h>
39#include "qedr.h"
40#include "qedr_iw_cm.h"
41
42static inline void
43qedr_fill_sockaddr4(const struct qed_iwarp_cm_info *cm_info,
44 struct iw_cm_event *event)
45{
46 struct sockaddr_in *laddr = (struct sockaddr_in *)&event->local_addr;
47 struct sockaddr_in *raddr = (struct sockaddr_in *)&event->remote_addr;
48
49 laddr->sin_family = AF_INET;
50 raddr->sin_family = AF_INET;
51
52 laddr->sin_port = htons(cm_info->local_port);
53 raddr->sin_port = htons(cm_info->remote_port);
54
55 laddr->sin_addr.s_addr = htonl(cm_info->local_ip[0]);
56 raddr->sin_addr.s_addr = htonl(cm_info->remote_ip[0]);
57}
58
59static inline void
60qedr_fill_sockaddr6(const struct qed_iwarp_cm_info *cm_info,
61 struct iw_cm_event *event)
62{
63 struct sockaddr_in6 *laddr6 = (struct sockaddr_in6 *)&event->local_addr;
64 struct sockaddr_in6 *raddr6 =
65 (struct sockaddr_in6 *)&event->remote_addr;
66 int i;
67
68 laddr6->sin6_family = AF_INET6;
69 raddr6->sin6_family = AF_INET6;
70
71 laddr6->sin6_port = htons(cm_info->local_port);
72 raddr6->sin6_port = htons(cm_info->remote_port);
73
74 for (i = 0; i < 4; i++) {
75 laddr6->sin6_addr.in6_u.u6_addr32[i] =
76 htonl(cm_info->local_ip[i]);
77 raddr6->sin6_addr.in6_u.u6_addr32[i] =
78 htonl(cm_info->remote_ip[i]);
79 }
80}
81
82static void
83qedr_iw_mpa_request(void *context, struct qed_iwarp_cm_event_params *params)
84{
85 struct qedr_iw_listener *listener = (struct qedr_iw_listener *)context;
86 struct qedr_dev *dev = listener->dev;
87 struct iw_cm_event event;
88 struct qedr_iw_ep *ep;
89
90 ep = kzalloc(sizeof(*ep), GFP_ATOMIC);
91 if (!ep)
92 return;
93
94 ep->dev = dev;
95 ep->qed_context = params->ep_context;
96
97 memset(&event, 0, sizeof(event));
98 event.event = IW_CM_EVENT_CONNECT_REQUEST;
99 event.status = params->status;
100
101 if (!IS_ENABLED(CONFIG_IPV6) ||
102 params->cm_info->ip_version == QED_TCP_IPV4)
103 qedr_fill_sockaddr4(params->cm_info, &event);
104 else
105 qedr_fill_sockaddr6(params->cm_info, &event);
106
107 event.provider_data = (void *)ep;
108 event.private_data = (void *)params->cm_info->private_data;
109 event.private_data_len = (u8)params->cm_info->private_data_len;
110 event.ord = params->cm_info->ord;
111 event.ird = params->cm_info->ird;
112
113 listener->cm_id->event_handler(listener->cm_id, &event);
114}
115
116static void
117qedr_iw_issue_event(void *context,
118 struct qed_iwarp_cm_event_params *params,
119 enum iw_cm_event_type event_type)
120{
121 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)context;
122 struct iw_cm_event event;
123
124 memset(&event, 0, sizeof(event));
125 event.status = params->status;
126 event.event = event_type;
127
128 if (params->cm_info) {
129 event.ird = params->cm_info->ird;
130 event.ord = params->cm_info->ord;
131 event.private_data_len = params->cm_info->private_data_len;
132 event.private_data = (void *)params->cm_info->private_data;
133 }
134
135 if (ep->cm_id)
136 ep->cm_id->event_handler(ep->cm_id, &event);
137}
138
139static void
140qedr_iw_close_event(void *context, struct qed_iwarp_cm_event_params *params)
141{
142 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)context;
143
144 if (ep->cm_id) {
145 qedr_iw_issue_event(context, params, IW_CM_EVENT_CLOSE);
146
147 ep->cm_id->rem_ref(ep->cm_id);
148 ep->cm_id = NULL;
149 }
150}
151
152static void
153qedr_iw_qp_event(void *context,
154 struct qed_iwarp_cm_event_params *params,
155 enum ib_event_type ib_event, char *str)
156{
157 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)context;
158 struct qedr_dev *dev = ep->dev;
159 struct ib_qp *ibqp = &ep->qp->ibqp;
160 struct ib_event event;
161
162 DP_NOTICE(dev, "QP error received: %s\n", str);
163
164 if (ibqp->event_handler) {
165 event.event = ib_event;
166 event.device = ibqp->device;
167 event.element.qp = ibqp;
168 ibqp->event_handler(&event, ibqp->qp_context);
169 }
170}
171
172struct qedr_discon_work {
173 struct work_struct work;
174 struct qedr_iw_ep *ep;
175 enum qed_iwarp_event_type event;
176 int status;
177};
178
179static void qedr_iw_disconnect_worker(struct work_struct *work)
180{
181 struct qedr_discon_work *dwork =
182 container_of(work, struct qedr_discon_work, work);
183 struct qed_rdma_modify_qp_in_params qp_params = { 0 };
184 struct qedr_iw_ep *ep = dwork->ep;
185 struct qedr_dev *dev = ep->dev;
186 struct qedr_qp *qp = ep->qp;
187 struct iw_cm_event event;
188
189 if (qp->destroyed) {
190 kfree(dwork);
191 qedr_iw_qp_rem_ref(&qp->ibqp);
192 return;
193 }
194
195 memset(&event, 0, sizeof(event));
196 event.status = dwork->status;
197 event.event = IW_CM_EVENT_DISCONNECT;
198
199 /* Success means graceful disconnect was requested. modifying
200 * to SQD is translated to graceful disconnect. O/w reset is sent
201 */
202 if (dwork->status)
203 qp_params.new_state = QED_ROCE_QP_STATE_ERR;
204 else
205 qp_params.new_state = QED_ROCE_QP_STATE_SQD;
206
207 kfree(dwork);
208
209 if (ep->cm_id)
210 ep->cm_id->event_handler(ep->cm_id, &event);
211
212 SET_FIELD(qp_params.modify_flags,
213 QED_RDMA_MODIFY_QP_VALID_NEW_STATE, 1);
214
215 dev->ops->rdma_modify_qp(dev->rdma_ctx, qp->qed_qp, &qp_params);
216
217 qedr_iw_qp_rem_ref(&qp->ibqp);
218}
219
220static void
221qedr_iw_disconnect_event(void *context,
222 struct qed_iwarp_cm_event_params *params)
223{
224 struct qedr_discon_work *work;
225 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)context;
226 struct qedr_dev *dev = ep->dev;
227 struct qedr_qp *qp = ep->qp;
228
229 work = kzalloc(sizeof(*work), GFP_ATOMIC);
230 if (!work)
231 return;
232
233 qedr_iw_qp_add_ref(&qp->ibqp);
234 work->ep = ep;
235 work->event = params->event;
236 work->status = params->status;
237
238 INIT_WORK(&work->work, qedr_iw_disconnect_worker);
239 queue_work(dev->iwarp_wq, &work->work);
240}
241
242static void
243qedr_iw_passive_complete(void *context,
244 struct qed_iwarp_cm_event_params *params)
245{
246 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)context;
247 struct qedr_dev *dev = ep->dev;
248
249 /* We will only reach the following state if MPA_REJECT was called on
250 * passive. In this case there will be no associated QP.
251 */
252 if ((params->status == -ECONNREFUSED) && (!ep->qp)) {
253 DP_DEBUG(dev, QEDR_MSG_IWARP,
254 "PASSIVE connection refused releasing ep...\n");
255 kfree(ep);
256 return;
257 }
258
259 qedr_iw_issue_event(context, params, IW_CM_EVENT_ESTABLISHED);
260
261 if (params->status < 0)
262 qedr_iw_close_event(context, params);
263}
264
265static int
266qedr_iw_mpa_reply(void *context, struct qed_iwarp_cm_event_params *params)
267{
268 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)context;
269 struct qedr_dev *dev = ep->dev;
270 struct qed_iwarp_send_rtr_in rtr_in;
271
272 rtr_in.ep_context = params->ep_context;
273
274 return dev->ops->iwarp_send_rtr(dev->rdma_ctx, &rtr_in);
275}
276
277static int
278qedr_iw_event_handler(void *context, struct qed_iwarp_cm_event_params *params)
279{
280 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)context;
281 struct qedr_dev *dev = ep->dev;
282
283 switch (params->event) {
284 case QED_IWARP_EVENT_MPA_REQUEST:
285 qedr_iw_mpa_request(context, params);
286 break;
287 case QED_IWARP_EVENT_ACTIVE_MPA_REPLY:
288 qedr_iw_mpa_reply(context, params);
289 break;
290 case QED_IWARP_EVENT_PASSIVE_COMPLETE:
291 ep->during_connect = 0;
292 qedr_iw_passive_complete(context, params);
293 break;
294
295 case QED_IWARP_EVENT_ACTIVE_COMPLETE:
296 ep->during_connect = 0;
297 qedr_iw_issue_event(context,
298 params,
299 IW_CM_EVENT_CONNECT_REPLY);
300 if (params->status < 0) {
301 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)context;
302
303 ep->cm_id->rem_ref(ep->cm_id);
304 ep->cm_id = NULL;
305 }
306 break;
307 case QED_IWARP_EVENT_DISCONNECT:
308 qedr_iw_disconnect_event(context, params);
309 break;
310 case QED_IWARP_EVENT_CLOSE:
311 ep->during_connect = 0;
312 qedr_iw_close_event(context, params);
313 break;
314 case QED_IWARP_EVENT_RQ_EMPTY:
315 qedr_iw_qp_event(context, params, IB_EVENT_QP_FATAL,
316 "QED_IWARP_EVENT_RQ_EMPTY");
317 break;
318 case QED_IWARP_EVENT_IRQ_FULL:
319 qedr_iw_qp_event(context, params, IB_EVENT_QP_FATAL,
320 "QED_IWARP_EVENT_IRQ_FULL");
321 break;
322 case QED_IWARP_EVENT_LLP_TIMEOUT:
323 qedr_iw_qp_event(context, params, IB_EVENT_QP_FATAL,
324 "QED_IWARP_EVENT_LLP_TIMEOUT");
325 break;
326 case QED_IWARP_EVENT_REMOTE_PROTECTION_ERROR:
327 qedr_iw_qp_event(context, params, IB_EVENT_QP_ACCESS_ERR,
328 "QED_IWARP_EVENT_REMOTE_PROTECTION_ERROR");
329 break;
330 case QED_IWARP_EVENT_CQ_OVERFLOW:
331 qedr_iw_qp_event(context, params, IB_EVENT_QP_FATAL,
332 "QED_IWARP_EVENT_CQ_OVERFLOW");
333 break;
334 case QED_IWARP_EVENT_QP_CATASTROPHIC:
335 qedr_iw_qp_event(context, params, IB_EVENT_QP_FATAL,
336 "QED_IWARP_EVENT_QP_CATASTROPHIC");
337 break;
338 case QED_IWARP_EVENT_LOCAL_ACCESS_ERROR:
339 qedr_iw_qp_event(context, params, IB_EVENT_QP_ACCESS_ERR,
340 "QED_IWARP_EVENT_LOCAL_ACCESS_ERROR");
341 break;
342 case QED_IWARP_EVENT_REMOTE_OPERATION_ERROR:
343 qedr_iw_qp_event(context, params, IB_EVENT_QP_FATAL,
344 "QED_IWARP_EVENT_REMOTE_OPERATION_ERROR");
345 break;
346 case QED_IWARP_EVENT_TERMINATE_RECEIVED:
347 DP_NOTICE(dev, "Got terminate message\n");
348 break;
349 default:
350 DP_NOTICE(dev, "Unknown event received %d\n", params->event);
351 break;
352 };
353 return 0;
354}
355
356static u16 qedr_iw_get_vlan_ipv4(struct qedr_dev *dev, u32 *addr)
357{
358 struct net_device *ndev;
359 u16 vlan_id = 0;
360
361 ndev = ip_dev_find(&init_net, htonl(addr[0]));
362
363 if (ndev) {
364 vlan_id = rdma_vlan_dev_vlan_id(ndev);
365 dev_put(ndev);
366 }
367 if (vlan_id == 0xffff)
368 vlan_id = 0;
369 return vlan_id;
370}
371
372static u16 qedr_iw_get_vlan_ipv6(u32 *addr)
373{
374 struct net_device *ndev = NULL;
375 struct in6_addr laddr6;
376 u16 vlan_id = 0;
377 int i;
378
379 if (!IS_ENABLED(CONFIG_IPV6))
380 return vlan_id;
381
382 for (i = 0; i < 4; i++)
383 laddr6.in6_u.u6_addr32[i] = htonl(addr[i]);
384
385 rcu_read_lock();
386 for_each_netdev_rcu(&init_net, ndev) {
387 if (ipv6_chk_addr(&init_net, &laddr6, ndev, 1)) {
388 vlan_id = rdma_vlan_dev_vlan_id(ndev);
389 break;
390 }
391 }
392
393 rcu_read_unlock();
394 if (vlan_id == 0xffff)
395 vlan_id = 0;
396
397 return vlan_id;
398}
399
400static int
401qedr_addr4_resolve(struct qedr_dev *dev,
402 struct sockaddr_in *src_in,
403 struct sockaddr_in *dst_in, u8 *dst_mac)
404{
405 __be32 src_ip = src_in->sin_addr.s_addr;
406 __be32 dst_ip = dst_in->sin_addr.s_addr;
407 struct neighbour *neigh = NULL;
408 struct rtable *rt = NULL;
409 int rc = 0;
410
411 rt = ip_route_output(&init_net, dst_ip, src_ip, 0, 0);
412 if (IS_ERR(rt)) {
413 DP_ERR(dev, "ip_route_output returned error\n");
414 return -EINVAL;
415 }
416
417 neigh = dst_neigh_lookup(&rt->dst, &dst_ip);
418
419 if (neigh) {
420 rcu_read_lock();
421 if (neigh->nud_state & NUD_VALID) {
422 ether_addr_copy(dst_mac, neigh->ha);
423 DP_DEBUG(dev, QEDR_MSG_QP, "mac_addr=[%pM]\n", dst_mac);
424 } else {
425 neigh_event_send(neigh, NULL);
426 }
427 rcu_read_unlock();
428 neigh_release(neigh);
429 }
430
431 ip_rt_put(rt);
432
433 return rc;
434}
435
436static int
437qedr_addr6_resolve(struct qedr_dev *dev,
438 struct sockaddr_in6 *src_in,
439 struct sockaddr_in6 *dst_in, u8 *dst_mac)
440{
441 struct neighbour *neigh = NULL;
442 struct dst_entry *dst;
443 struct flowi6 fl6;
444 int rc = 0;
445
446 memset(&fl6, 0, sizeof(fl6));
447 fl6.daddr = dst_in->sin6_addr;
448 fl6.saddr = src_in->sin6_addr;
449
450 dst = ip6_route_output(&init_net, NULL, &fl6);
451
452 if ((!dst) || dst->error) {
453 if (dst) {
454 dst_release(dst);
455 DP_ERR(dev,
456 "ip6_route_output returned dst->error = %d\n",
457 dst->error);
458 }
459 return -EINVAL;
460 }
461 neigh = dst_neigh_lookup(dst, &dst_in);
462
463 if (neigh) {
464 rcu_read_lock();
465 if (neigh->nud_state & NUD_VALID) {
466 ether_addr_copy(dst_mac, neigh->ha);
467 DP_DEBUG(dev, QEDR_MSG_QP, "mac_addr=[%pM]\n", dst_mac);
468 } else {
469 neigh_event_send(neigh, NULL);
470 }
471 rcu_read_unlock();
472 neigh_release(neigh);
473 }
474
475 dst_release(dst);
476
477 return rc;
478}
479
480int qedr_iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
481{
482 struct qedr_dev *dev = get_qedr_dev(cm_id->device);
483 struct qed_iwarp_connect_out out_params;
484 struct qed_iwarp_connect_in in_params;
485 struct qed_iwarp_cm_info *cm_info;
486 struct sockaddr_in6 *laddr6;
487 struct sockaddr_in6 *raddr6;
488 struct sockaddr_in *laddr;
489 struct sockaddr_in *raddr;
490 struct qedr_iw_ep *ep;
491 struct qedr_qp *qp;
492 int rc = 0;
493 int i;
494
495 qp = idr_find(&dev->qpidr, conn_param->qpn);
496
497 laddr = (struct sockaddr_in *)&cm_id->local_addr;
498 raddr = (struct sockaddr_in *)&cm_id->remote_addr;
499 laddr6 = (struct sockaddr_in6 *)&cm_id->local_addr;
500 raddr6 = (struct sockaddr_in6 *)&cm_id->remote_addr;
501
502 DP_DEBUG(dev, QEDR_MSG_IWARP,
503 "Connect source address: %pISpc, remote address: %pISpc\n",
504 &cm_id->local_addr, &cm_id->remote_addr);
505
506 if (!laddr->sin_port || !raddr->sin_port)
507 return -EINVAL;
508
509 ep = kzalloc(sizeof(*ep), GFP_KERNEL);
510 if (!ep)
511 return -ENOMEM;
512
513 ep->dev = dev;
514 ep->qp = qp;
515 qp->ep = ep;
516 cm_id->add_ref(cm_id);
517 ep->cm_id = cm_id;
518
519 in_params.event_cb = qedr_iw_event_handler;
520 in_params.cb_context = ep;
521
522 cm_info = &in_params.cm_info;
523 memset(cm_info->local_ip, 0, sizeof(cm_info->local_ip));
524 memset(cm_info->remote_ip, 0, sizeof(cm_info->remote_ip));
525
526 if (!IS_ENABLED(CONFIG_IPV6) ||
527 cm_id->remote_addr.ss_family == AF_INET) {
528 cm_info->ip_version = QED_TCP_IPV4;
529
530 cm_info->remote_ip[0] = ntohl(raddr->sin_addr.s_addr);
531 cm_info->local_ip[0] = ntohl(laddr->sin_addr.s_addr);
532 cm_info->remote_port = ntohs(raddr->sin_port);
533 cm_info->local_port = ntohs(laddr->sin_port);
534 cm_info->vlan = qedr_iw_get_vlan_ipv4(dev, cm_info->local_ip);
535
536 rc = qedr_addr4_resolve(dev, laddr, raddr,
537 (u8 *)in_params.remote_mac_addr);
538
539 in_params.mss = dev->iwarp_max_mtu -
540 (sizeof(struct iphdr) + sizeof(struct tcphdr));
541
542 } else {
543 in_params.cm_info.ip_version = QED_TCP_IPV6;
544
545 for (i = 0; i < 4; i++) {
546 cm_info->remote_ip[i] =
547 ntohl(raddr6->sin6_addr.in6_u.u6_addr32[i]);
548 cm_info->local_ip[i] =
549 ntohl(laddr6->sin6_addr.in6_u.u6_addr32[i]);
550 }
551
552 cm_info->local_port = ntohs(laddr6->sin6_port);
553 cm_info->remote_port = ntohs(raddr6->sin6_port);
554
555 in_params.mss = dev->iwarp_max_mtu -
556 (sizeof(struct ipv6hdr) + sizeof(struct tcphdr));
557
558 cm_info->vlan = qedr_iw_get_vlan_ipv6(cm_info->local_ip);
559
560 rc = qedr_addr6_resolve(dev, laddr6, raddr6,
561 (u8 *)in_params.remote_mac_addr);
562 }
563 if (rc)
564 goto err;
565
566 DP_DEBUG(dev, QEDR_MSG_IWARP,
567 "ord = %d ird=%d private_data=%p private_data_len=%d rq_psn=%d\n",
568 conn_param->ord, conn_param->ird, conn_param->private_data,
569 conn_param->private_data_len, qp->rq_psn);
570
571 cm_info->ord = conn_param->ord;
572 cm_info->ird = conn_param->ird;
573 cm_info->private_data = conn_param->private_data;
574 cm_info->private_data_len = conn_param->private_data_len;
575 in_params.qp = qp->qed_qp;
576 memcpy(in_params.local_mac_addr, dev->ndev->dev_addr, ETH_ALEN);
577
578 ep->during_connect = 1;
579 rc = dev->ops->iwarp_connect(dev->rdma_ctx, &in_params, &out_params);
580 if (rc)
581 goto err;
582
583 return rc;
584
585err:
586 cm_id->rem_ref(cm_id);
587 kfree(ep);
588 return rc;
589}
590
591int qedr_iw_create_listen(struct iw_cm_id *cm_id, int backlog)
592{
593 struct qedr_dev *dev = get_qedr_dev(cm_id->device);
594 struct qedr_iw_listener *listener;
595 struct qed_iwarp_listen_in iparams;
596 struct qed_iwarp_listen_out oparams;
597 struct sockaddr_in *laddr;
598 struct sockaddr_in6 *laddr6;
599 int rc;
600 int i;
601
602 laddr = (struct sockaddr_in *)&cm_id->local_addr;
603 laddr6 = (struct sockaddr_in6 *)&cm_id->local_addr;
604
605 DP_DEBUG(dev, QEDR_MSG_IWARP,
606 "Create Listener address: %pISpc\n", &cm_id->local_addr);
607
608 listener = kzalloc(sizeof(*listener), GFP_KERNEL);
609 if (!listener)
610 return -ENOMEM;
611
612 listener->dev = dev;
613 cm_id->add_ref(cm_id);
614 listener->cm_id = cm_id;
615 listener->backlog = backlog;
616
617 iparams.cb_context = listener;
618 iparams.event_cb = qedr_iw_event_handler;
619 iparams.max_backlog = backlog;
620
621 if (!IS_ENABLED(CONFIG_IPV6) ||
622 cm_id->local_addr.ss_family == AF_INET) {
623 iparams.ip_version = QED_TCP_IPV4;
624 memset(iparams.ip_addr, 0, sizeof(iparams.ip_addr));
625
626 iparams.ip_addr[0] = ntohl(laddr->sin_addr.s_addr);
627 iparams.port = ntohs(laddr->sin_port);
628 iparams.vlan = qedr_iw_get_vlan_ipv4(dev, iparams.ip_addr);
629 } else {
630 iparams.ip_version = QED_TCP_IPV6;
631
632 for (i = 0; i < 4; i++) {
633 iparams.ip_addr[i] =
634 ntohl(laddr6->sin6_addr.in6_u.u6_addr32[i]);
635 }
636
637 iparams.port = ntohs(laddr6->sin6_port);
638
639 iparams.vlan = qedr_iw_get_vlan_ipv6(iparams.ip_addr);
640 }
641 rc = dev->ops->iwarp_create_listen(dev->rdma_ctx, &iparams, &oparams);
642 if (rc)
643 goto err;
644
645 listener->qed_handle = oparams.handle;
646 cm_id->provider_data = listener;
647 return rc;
648
649err:
650 cm_id->rem_ref(cm_id);
651 kfree(listener);
652 return rc;
653}
654
655int qedr_iw_destroy_listen(struct iw_cm_id *cm_id)
656{
657 struct qedr_iw_listener *listener = cm_id->provider_data;
658 struct qedr_dev *dev = get_qedr_dev(cm_id->device);
659 int rc = 0;
660
661 if (listener->qed_handle)
662 rc = dev->ops->iwarp_destroy_listen(dev->rdma_ctx,
663 listener->qed_handle);
664
665 cm_id->rem_ref(cm_id);
666 return rc;
667}
668
669int qedr_iw_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
670{
671 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)cm_id->provider_data;
672 struct qedr_dev *dev = ep->dev;
673 struct qedr_qp *qp;
674 struct qed_iwarp_accept_in params;
675 int rc;
676
677 DP_DEBUG(dev, QEDR_MSG_IWARP, "Accept on qpid=%d\n", conn_param->qpn);
678
679 qp = idr_find(&dev->qpidr, conn_param->qpn);
680 if (!qp) {
681 DP_ERR(dev, "Invalid QP number %d\n", conn_param->qpn);
682 return -EINVAL;
683 }
684
685 ep->qp = qp;
686 qp->ep = ep;
687 cm_id->add_ref(cm_id);
688 ep->cm_id = cm_id;
689
690 params.ep_context = ep->qed_context;
691 params.cb_context = ep;
692 params.qp = ep->qp->qed_qp;
693 params.private_data = conn_param->private_data;
694 params.private_data_len = conn_param->private_data_len;
695 params.ird = conn_param->ird;
696 params.ord = conn_param->ord;
697
698 ep->during_connect = 1;
699 rc = dev->ops->iwarp_accept(dev->rdma_ctx, &params);
700 if (rc)
701 goto err;
702
703 return rc;
704err:
705 ep->during_connect = 0;
706 cm_id->rem_ref(cm_id);
707 return rc;
708}
709
710int qedr_iw_reject(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len)
711{
712 struct qedr_iw_ep *ep = (struct qedr_iw_ep *)cm_id->provider_data;
713 struct qedr_dev *dev = ep->dev;
714 struct qed_iwarp_reject_in params;
715
716 params.ep_context = ep->qed_context;
717 params.cb_context = ep;
718 params.private_data = pdata;
719 params.private_data_len = pdata_len;
720 ep->qp = NULL;
721
722 return dev->ops->iwarp_reject(dev->rdma_ctx, &params);
723}
724
725void qedr_iw_qp_add_ref(struct ib_qp *ibqp)
726{
727 struct qedr_qp *qp = get_qedr_qp(ibqp);
728
729 atomic_inc(&qp->refcnt);
730}
731
732void qedr_iw_qp_rem_ref(struct ib_qp *ibqp)
733{
734 struct qedr_qp *qp = get_qedr_qp(ibqp);
735
736 if (atomic_dec_and_test(&qp->refcnt)) {
737 spin_lock_irq(&qp->dev->idr_lock);
738 idr_remove(&qp->dev->qpidr, qp->qp_id);
739 spin_unlock_irq(&qp->dev->idr_lock);
740 kfree(qp);
741 }
742}
743
744struct ib_qp *qedr_iw_get_qp(struct ib_device *ibdev, int qpn)
745{
746 struct qedr_dev *dev = get_qedr_dev(ibdev);
747
748 return idr_find(&dev->qpidr, qpn);
749}
diff --git a/drivers/infiniband/hw/qedr/qedr_iw_cm.h b/drivers/infiniband/hw/qedr/qedr_iw_cm.h
new file mode 100644
index 000000000000..08f4b1067e6c
--- /dev/null
+++ b/drivers/infiniband/hw/qedr/qedr_iw_cm.h
@@ -0,0 +1,49 @@
1/* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <rdma/iw_cm.h>
33
34int qedr_iw_connect(struct iw_cm_id *cm_id,
35 struct iw_cm_conn_param *conn_param);
36
37int qedr_iw_create_listen(struct iw_cm_id *cm_id, int backlog);
38
39int qedr_iw_destroy_listen(struct iw_cm_id *cm_id);
40
41int qedr_iw_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
42
43int qedr_iw_reject(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
44
45void qedr_iw_qp_add_ref(struct ib_qp *qp);
46
47void qedr_iw_qp_rem_ref(struct ib_qp *qp);
48
49struct ib_qp *qedr_iw_get_qp(struct ib_device *dev, int qpn);
diff --git a/drivers/infiniband/hw/qedr/qedr_cm.c b/drivers/infiniband/hw/qedr/qedr_roce_cm.c
index ad8965397cf7..2bdbb12bfc69 100644
--- a/drivers/infiniband/hw/qedr/qedr_cm.c
+++ b/drivers/infiniband/hw/qedr/qedr_roce_cm.c
@@ -48,7 +48,7 @@
48#include "qedr.h" 48#include "qedr.h"
49#include "verbs.h" 49#include "verbs.h"
50#include <rdma/qedr-abi.h> 50#include <rdma/qedr-abi.h>
51#include "qedr_cm.h" 51#include "qedr_roce_cm.h"
52 52
53void qedr_inc_sw_gsi_cons(struct qedr_qp_hwq_info *info) 53void qedr_inc_sw_gsi_cons(struct qedr_qp_hwq_info *info)
54{ 54{
@@ -64,11 +64,11 @@ void qedr_store_gsi_qp_cq(struct qedr_dev *dev, struct qedr_qp *qp,
64 dev->gsi_qp = qp; 64 dev->gsi_qp = qp;
65} 65}
66 66
67void qedr_ll2_complete_tx_packet(void *cxt, 67static void qedr_ll2_complete_tx_packet(void *cxt, u8 connection_handle,
68 u8 connection_handle, 68 void *cookie,
69 void *cookie, 69 dma_addr_t first_frag_addr,
70 dma_addr_t first_frag_addr, 70 bool b_last_fragment,
71 bool b_last_fragment, bool b_last_packet) 71 bool b_last_packet)
72{ 72{
73 struct qedr_dev *dev = (struct qedr_dev *)cxt; 73 struct qedr_dev *dev = (struct qedr_dev *)cxt;
74 struct qed_roce_ll2_packet *pkt = cookie; 74 struct qed_roce_ll2_packet *pkt = cookie;
@@ -93,8 +93,8 @@ void qedr_ll2_complete_tx_packet(void *cxt,
93 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context); 93 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
94} 94}
95 95
96void qedr_ll2_complete_rx_packet(void *cxt, 96static void qedr_ll2_complete_rx_packet(void *cxt,
97 struct qed_ll2_comp_rx_data *data) 97 struct qed_ll2_comp_rx_data *data)
98{ 98{
99 struct qedr_dev *dev = (struct qedr_dev *)cxt; 99 struct qedr_dev *dev = (struct qedr_dev *)cxt;
100 struct qedr_cq *cq = dev->gsi_rqcq; 100 struct qedr_cq *cq = dev->gsi_rqcq;
@@ -122,10 +122,9 @@ void qedr_ll2_complete_rx_packet(void *cxt,
122 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context); 122 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
123} 123}
124 124
125void qedr_ll2_release_rx_packet(void *cxt, 125static void qedr_ll2_release_rx_packet(void *cxt, u8 connection_handle,
126 u8 connection_handle, 126 void *cookie, dma_addr_t rx_buf_addr,
127 void *cookie, 127 bool b_last_packet)
128 dma_addr_t rx_buf_addr, bool b_last_packet)
129{ 128{
130 /* Do nothing... */ 129 /* Do nothing... */
131} 130}
@@ -237,7 +236,7 @@ static int qedr_ll2_post_tx(struct qedr_dev *dev,
237 return 0; 236 return 0;
238} 237}
239 238
240int qedr_ll2_stop(struct qedr_dev *dev) 239static int qedr_ll2_stop(struct qedr_dev *dev)
241{ 240{
242 int rc; 241 int rc;
243 242
@@ -260,8 +259,8 @@ int qedr_ll2_stop(struct qedr_dev *dev)
260 return rc; 259 return rc;
261} 260}
262 261
263int qedr_ll2_start(struct qedr_dev *dev, 262static int qedr_ll2_start(struct qedr_dev *dev,
264 struct ib_qp_init_attr *attrs, struct qedr_qp *qp) 263 struct ib_qp_init_attr *attrs, struct qedr_qp *qp)
265{ 264{
266 struct qed_ll2_acquire_data data; 265 struct qed_ll2_acquire_data data;
267 struct qed_ll2_cbs cbs; 266 struct qed_ll2_cbs cbs;
@@ -660,7 +659,7 @@ int qedr_gsi_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
660 dev->gsi_ll2_handle, 659 dev->gsi_ll2_handle,
661 wr->sg_list[0].addr, 660 wr->sg_list[0].addr,
662 wr->sg_list[0].length, 661 wr->sg_list[0].length,
663 0 /* cookie */, 662 NULL /* cookie */,
664 1 /* notify_fw */); 663 1 /* notify_fw */);
665 if (rc) { 664 if (rc) {
666 DP_ERR(dev, 665 DP_ERR(dev,
diff --git a/drivers/infiniband/hw/qedr/qedr_cm.h b/drivers/infiniband/hw/qedr/qedr_roce_cm.h
index a55916323ea9..a55916323ea9 100644
--- a/drivers/infiniband/hw/qedr/qedr_cm.h
+++ b/drivers/infiniband/hw/qedr/qedr_roce_cm.h
diff --git a/drivers/infiniband/hw/qedr/verbs.c b/drivers/infiniband/hw/qedr/verbs.c
index 769ac07c3c8e..b26aa88dab48 100644
--- a/drivers/infiniband/hw/qedr/verbs.c
+++ b/drivers/infiniband/hw/qedr/verbs.c
@@ -49,7 +49,7 @@
49#include "qedr.h" 49#include "qedr.h"
50#include "verbs.h" 50#include "verbs.h"
51#include <rdma/qedr-abi.h> 51#include <rdma/qedr-abi.h>
52#include "qedr_cm.h" 52#include "qedr_roce_cm.h"
53 53
54#define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT) 54#define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
55 55
@@ -70,6 +70,20 @@ int qedr_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
70 return 0; 70 return 0;
71} 71}
72 72
73int qedr_iw_query_gid(struct ib_device *ibdev, u8 port,
74 int index, union ib_gid *sgid)
75{
76 struct qedr_dev *dev = get_qedr_dev(ibdev);
77
78 memset(sgid->raw, 0, sizeof(sgid->raw));
79 ether_addr_copy(sgid->raw, dev->ndev->dev_addr);
80
81 DP_DEBUG(dev, QEDR_MSG_INIT, "QUERY sgid[%d]=%llx:%llx\n", index,
82 sgid->global.interface_id, sgid->global.subnet_prefix);
83
84 return 0;
85}
86
73int qedr_query_gid(struct ib_device *ibdev, u8 port, int index, 87int qedr_query_gid(struct ib_device *ibdev, u8 port, int index,
74 union ib_gid *sgid) 88 union ib_gid *sgid)
75{ 89{
@@ -263,8 +277,13 @@ int qedr_query_port(struct ib_device *ibdev, u8 port, struct ib_port_attr *attr)
263 attr->sm_lid = 0; 277 attr->sm_lid = 0;
264 attr->sm_sl = 0; 278 attr->sm_sl = 0;
265 attr->port_cap_flags = IB_PORT_IP_BASED_GIDS; 279 attr->port_cap_flags = IB_PORT_IP_BASED_GIDS;
266 attr->gid_tbl_len = QEDR_MAX_SGID; 280 if (rdma_protocol_iwarp(&dev->ibdev, 1)) {
267 attr->pkey_tbl_len = QEDR_ROCE_PKEY_TABLE_LEN; 281 attr->gid_tbl_len = 1;
282 attr->pkey_tbl_len = 1;
283 } else {
284 attr->gid_tbl_len = QEDR_MAX_SGID;
285 attr->pkey_tbl_len = QEDR_ROCE_PKEY_TABLE_LEN;
286 }
268 attr->bad_pkey_cntr = rdma_port->pkey_bad_counter; 287 attr->bad_pkey_cntr = rdma_port->pkey_bad_counter;
269 attr->qkey_viol_cntr = 0; 288 attr->qkey_viol_cntr = 0;
270 get_link_speed_and_width(rdma_port->link_speed, 289 get_link_speed_and_width(rdma_port->link_speed,
@@ -770,7 +789,8 @@ static inline int qedr_init_user_queue(struct ib_ucontext *ib_ctx,
770 struct qedr_dev *dev, 789 struct qedr_dev *dev,
771 struct qedr_userq *q, 790 struct qedr_userq *q,
772 u64 buf_addr, size_t buf_len, 791 u64 buf_addr, size_t buf_len,
773 int access, int dmasync) 792 int access, int dmasync,
793 int alloc_and_init)
774{ 794{
775 u32 fw_pages; 795 u32 fw_pages;
776 int rc; 796 int rc;
@@ -791,19 +811,27 @@ static inline int qedr_init_user_queue(struct ib_ucontext *ib_ctx,
791 if (rc) 811 if (rc)
792 goto err0; 812 goto err0;
793 813
794 q->pbl_tbl = qedr_alloc_pbl_tbl(dev, &q->pbl_info, GFP_KERNEL); 814 if (alloc_and_init) {
795 if (IS_ERR(q->pbl_tbl)) { 815 q->pbl_tbl = qedr_alloc_pbl_tbl(dev, &q->pbl_info, GFP_KERNEL);
796 rc = PTR_ERR(q->pbl_tbl); 816 if (IS_ERR(q->pbl_tbl)) {
797 goto err0; 817 rc = PTR_ERR(q->pbl_tbl);
798 } 818 goto err0;
799 819 }
800 qedr_populate_pbls(dev, q->umem, q->pbl_tbl, &q->pbl_info, 820 qedr_populate_pbls(dev, q->umem, q->pbl_tbl, &q->pbl_info,
801 FW_PAGE_SHIFT); 821 FW_PAGE_SHIFT);
822 } else {
823 q->pbl_tbl = kzalloc(sizeof(*q->pbl_tbl), GFP_KERNEL);
824 if (!q->pbl_tbl) {
825 rc = -ENOMEM;
826 goto err0;
827 }
828 }
802 829
803 return 0; 830 return 0;
804 831
805err0: 832err0:
806 ib_umem_release(q->umem); 833 ib_umem_release(q->umem);
834 q->umem = NULL;
807 835
808 return rc; 836 return rc;
809} 837}
@@ -929,7 +957,8 @@ struct ib_cq *qedr_create_cq(struct ib_device *ibdev,
929 cq->cq_type = QEDR_CQ_TYPE_USER; 957 cq->cq_type = QEDR_CQ_TYPE_USER;
930 958
931 rc = qedr_init_user_queue(ib_ctx, dev, &cq->q, ureq.addr, 959 rc = qedr_init_user_queue(ib_ctx, dev, &cq->q, ureq.addr,
932 ureq.len, IB_ACCESS_LOCAL_WRITE, 1); 960 ureq.len, IB_ACCESS_LOCAL_WRITE,
961 1, 1);
933 if (rc) 962 if (rc)
934 goto err0; 963 goto err0;
935 964
@@ -1222,18 +1251,34 @@ static int qedr_check_qp_attrs(struct ib_pd *ibpd, struct qedr_dev *dev,
1222 return 0; 1251 return 0;
1223} 1252}
1224 1253
1225static void qedr_copy_rq_uresp(struct qedr_create_qp_uresp *uresp, 1254static void qedr_copy_rq_uresp(struct qedr_dev *dev,
1255 struct qedr_create_qp_uresp *uresp,
1226 struct qedr_qp *qp) 1256 struct qedr_qp *qp)
1227{ 1257{
1228 uresp->rq_db_offset = DB_ADDR_SHIFT(DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD); 1258 /* iWARP requires two doorbells per RQ. */
1259 if (rdma_protocol_iwarp(&dev->ibdev, 1)) {
1260 uresp->rq_db_offset =
1261 DB_ADDR_SHIFT(DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD);
1262 uresp->rq_db2_offset = DB_ADDR_SHIFT(DQ_PWM_OFFSET_TCM_FLAGS);
1263 } else {
1264 uresp->rq_db_offset =
1265 DB_ADDR_SHIFT(DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD);
1266 }
1267
1229 uresp->rq_icid = qp->icid; 1268 uresp->rq_icid = qp->icid;
1230} 1269}
1231 1270
1232static void qedr_copy_sq_uresp(struct qedr_create_qp_uresp *uresp, 1271static void qedr_copy_sq_uresp(struct qedr_dev *dev,
1272 struct qedr_create_qp_uresp *uresp,
1233 struct qedr_qp *qp) 1273 struct qedr_qp *qp)
1234{ 1274{
1235 uresp->sq_db_offset = DB_ADDR_SHIFT(DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD); 1275 uresp->sq_db_offset = DB_ADDR_SHIFT(DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD);
1236 uresp->sq_icid = qp->icid + 1; 1276
1277 /* iWARP uses the same cid for rq and sq */
1278 if (rdma_protocol_iwarp(&dev->ibdev, 1))
1279 uresp->sq_icid = qp->icid;
1280 else
1281 uresp->sq_icid = qp->icid + 1;
1237} 1282}
1238 1283
1239static int qedr_copy_qp_uresp(struct qedr_dev *dev, 1284static int qedr_copy_qp_uresp(struct qedr_dev *dev,
@@ -1243,8 +1288,8 @@ static int qedr_copy_qp_uresp(struct qedr_dev *dev,
1243 int rc; 1288 int rc;
1244 1289
1245 memset(&uresp, 0, sizeof(uresp)); 1290 memset(&uresp, 0, sizeof(uresp));
1246 qedr_copy_sq_uresp(&uresp, qp); 1291 qedr_copy_sq_uresp(dev, &uresp, qp);
1247 qedr_copy_rq_uresp(&uresp, qp); 1292 qedr_copy_rq_uresp(dev, &uresp, qp);
1248 1293
1249 uresp.atomic_supported = dev->atomic_cap != IB_ATOMIC_NONE; 1294 uresp.atomic_supported = dev->atomic_cap != IB_ATOMIC_NONE;
1250 uresp.qp_id = qp->qp_id; 1295 uresp.qp_id = qp->qp_id;
@@ -1264,6 +1309,7 @@ static void qedr_set_common_qp_params(struct qedr_dev *dev,
1264 struct ib_qp_init_attr *attrs) 1309 struct ib_qp_init_attr *attrs)
1265{ 1310{
1266 spin_lock_init(&qp->q_lock); 1311 spin_lock_init(&qp->q_lock);
1312 atomic_set(&qp->refcnt, 1);
1267 qp->pd = pd; 1313 qp->pd = pd;
1268 qp->qp_type = attrs->qp_type; 1314 qp->qp_type = attrs->qp_type;
1269 qp->max_inline_data = attrs->cap.max_inline_data; 1315 qp->max_inline_data = attrs->cap.max_inline_data;
@@ -1334,6 +1380,52 @@ static inline void qedr_qp_user_print(struct qedr_dev *dev, struct qedr_qp *qp)
1334 qp->usq.buf_len, qp->urq.buf_addr, qp->urq.buf_len); 1380 qp->usq.buf_len, qp->urq.buf_addr, qp->urq.buf_len);
1335} 1381}
1336 1382
1383static int qedr_idr_add(struct qedr_dev *dev, void *ptr, u32 id)
1384{
1385 int rc;
1386
1387 if (!rdma_protocol_iwarp(&dev->ibdev, 1))
1388 return 0;
1389
1390 idr_preload(GFP_KERNEL);
1391 spin_lock_irq(&dev->idr_lock);
1392
1393 rc = idr_alloc(&dev->qpidr, ptr, id, id + 1, GFP_ATOMIC);
1394
1395 spin_unlock_irq(&dev->idr_lock);
1396 idr_preload_end();
1397
1398 return rc < 0 ? rc : 0;
1399}
1400
1401static void qedr_idr_remove(struct qedr_dev *dev, u32 id)
1402{
1403 if (!rdma_protocol_iwarp(&dev->ibdev, 1))
1404 return;
1405
1406 spin_lock_irq(&dev->idr_lock);
1407 idr_remove(&dev->qpidr, id);
1408 spin_unlock_irq(&dev->idr_lock);
1409}
1410
1411static inline void
1412qedr_iwarp_populate_user_qp(struct qedr_dev *dev,
1413 struct qedr_qp *qp,
1414 struct qed_rdma_create_qp_out_params *out_params)
1415{
1416 qp->usq.pbl_tbl->va = out_params->sq_pbl_virt;
1417 qp->usq.pbl_tbl->pa = out_params->sq_pbl_phys;
1418
1419 qedr_populate_pbls(dev, qp->usq.umem, qp->usq.pbl_tbl,
1420 &qp->usq.pbl_info, FW_PAGE_SHIFT);
1421
1422 qp->urq.pbl_tbl->va = out_params->rq_pbl_virt;
1423 qp->urq.pbl_tbl->pa = out_params->rq_pbl_phys;
1424
1425 qedr_populate_pbls(dev, qp->urq.umem, qp->urq.pbl_tbl,
1426 &qp->urq.pbl_info, FW_PAGE_SHIFT);
1427}
1428
1337static void qedr_cleanup_user(struct qedr_dev *dev, struct qedr_qp *qp) 1429static void qedr_cleanup_user(struct qedr_dev *dev, struct qedr_qp *qp)
1338{ 1430{
1339 if (qp->usq.umem) 1431 if (qp->usq.umem)
@@ -1355,12 +1447,11 @@ static int qedr_create_user_qp(struct qedr_dev *dev,
1355 struct qed_rdma_create_qp_out_params out_params; 1447 struct qed_rdma_create_qp_out_params out_params;
1356 struct qedr_pd *pd = get_qedr_pd(ibpd); 1448 struct qedr_pd *pd = get_qedr_pd(ibpd);
1357 struct ib_ucontext *ib_ctx = NULL; 1449 struct ib_ucontext *ib_ctx = NULL;
1358 struct qedr_ucontext *ctx = NULL;
1359 struct qedr_create_qp_ureq ureq; 1450 struct qedr_create_qp_ureq ureq;
1451 int alloc_and_init = rdma_protocol_roce(&dev->ibdev, 1);
1360 int rc = -EINVAL; 1452 int rc = -EINVAL;
1361 1453
1362 ib_ctx = ibpd->uobject->context; 1454 ib_ctx = ibpd->uobject->context;
1363 ctx = get_qedr_ucontext(ib_ctx);
1364 1455
1365 memset(&ureq, 0, sizeof(ureq)); 1456 memset(&ureq, 0, sizeof(ureq));
1366 rc = ib_copy_from_udata(&ureq, udata, sizeof(ureq)); 1457 rc = ib_copy_from_udata(&ureq, udata, sizeof(ureq));
@@ -1371,14 +1462,13 @@ static int qedr_create_user_qp(struct qedr_dev *dev,
1371 1462
1372 /* SQ - read access only (0), dma sync not required (0) */ 1463 /* SQ - read access only (0), dma sync not required (0) */
1373 rc = qedr_init_user_queue(ib_ctx, dev, &qp->usq, ureq.sq_addr, 1464 rc = qedr_init_user_queue(ib_ctx, dev, &qp->usq, ureq.sq_addr,
1374 ureq.sq_len, 0, 0); 1465 ureq.sq_len, 0, 0, alloc_and_init);
1375 if (rc) 1466 if (rc)
1376 return rc; 1467 return rc;
1377 1468
1378 /* RQ - read access only (0), dma sync not required (0) */ 1469 /* RQ - read access only (0), dma sync not required (0) */
1379 rc = qedr_init_user_queue(ib_ctx, dev, &qp->urq, ureq.rq_addr, 1470 rc = qedr_init_user_queue(ib_ctx, dev, &qp->urq, ureq.rq_addr,
1380 ureq.rq_len, 0, 0); 1471 ureq.rq_len, 0, 0, alloc_and_init);
1381
1382 if (rc) 1472 if (rc)
1383 return rc; 1473 return rc;
1384 1474
@@ -1399,6 +1489,9 @@ static int qedr_create_user_qp(struct qedr_dev *dev,
1399 goto err1; 1489 goto err1;
1400 } 1490 }
1401 1491
1492 if (rdma_protocol_iwarp(&dev->ibdev, 1))
1493 qedr_iwarp_populate_user_qp(dev, qp, &out_params);
1494
1402 qp->qp_id = out_params.qp_id; 1495 qp->qp_id = out_params.qp_id;
1403 qp->icid = out_params.icid; 1496 qp->icid = out_params.icid;
1404 1497
@@ -1419,6 +1512,21 @@ err1:
1419 return rc; 1512 return rc;
1420} 1513}
1421 1514
1515static void qedr_set_iwarp_db_info(struct qedr_dev *dev, struct qedr_qp *qp)
1516{
1517 qp->sq.db = dev->db_addr +
1518 DB_ADDR_SHIFT(DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD);
1519 qp->sq.db_data.data.icid = qp->icid;
1520
1521 qp->rq.db = dev->db_addr +
1522 DB_ADDR_SHIFT(DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD);
1523 qp->rq.db_data.data.icid = qp->icid;
1524 qp->rq.iwarp_db2 = dev->db_addr +
1525 DB_ADDR_SHIFT(DQ_PWM_OFFSET_TCM_FLAGS);
1526 qp->rq.iwarp_db2_data.data.icid = qp->icid;
1527 qp->rq.iwarp_db2_data.data.value = DQ_TCM_IWARP_POST_RQ_CF_CMD;
1528}
1529
1422static int 1530static int
1423qedr_roce_create_kernel_qp(struct qedr_dev *dev, 1531qedr_roce_create_kernel_qp(struct qedr_dev *dev,
1424 struct qedr_qp *qp, 1532 struct qedr_qp *qp,
@@ -1465,8 +1573,71 @@ qedr_roce_create_kernel_qp(struct qedr_dev *dev,
1465 qp->icid = out_params.icid; 1573 qp->icid = out_params.icid;
1466 1574
1467 qedr_set_roce_db_info(dev, qp); 1575 qedr_set_roce_db_info(dev, qp);
1576 return rc;
1577}
1468 1578
1469 return 0; 1579static int
1580qedr_iwarp_create_kernel_qp(struct qedr_dev *dev,
1581 struct qedr_qp *qp,
1582 struct qed_rdma_create_qp_in_params *in_params,
1583 u32 n_sq_elems, u32 n_rq_elems)
1584{
1585 struct qed_rdma_create_qp_out_params out_params;
1586 struct qed_chain_ext_pbl ext_pbl;
1587 int rc;
1588
1589 in_params->sq_num_pages = QED_CHAIN_PAGE_CNT(n_sq_elems,
1590 QEDR_SQE_ELEMENT_SIZE,
1591 QED_CHAIN_MODE_PBL);
1592 in_params->rq_num_pages = QED_CHAIN_PAGE_CNT(n_rq_elems,
1593 QEDR_RQE_ELEMENT_SIZE,
1594 QED_CHAIN_MODE_PBL);
1595
1596 qp->qed_qp = dev->ops->rdma_create_qp(dev->rdma_ctx,
1597 in_params, &out_params);
1598
1599 if (!qp->qed_qp)
1600 return -EINVAL;
1601
1602 /* Now we allocate the chain */
1603 ext_pbl.p_pbl_virt = out_params.sq_pbl_virt;
1604 ext_pbl.p_pbl_phys = out_params.sq_pbl_phys;
1605
1606 rc = dev->ops->common->chain_alloc(dev->cdev,
1607 QED_CHAIN_USE_TO_PRODUCE,
1608 QED_CHAIN_MODE_PBL,
1609 QED_CHAIN_CNT_TYPE_U32,
1610 n_sq_elems,
1611 QEDR_SQE_ELEMENT_SIZE,
1612 &qp->sq.pbl, &ext_pbl);
1613
1614 if (rc)
1615 goto err;
1616
1617 ext_pbl.p_pbl_virt = out_params.rq_pbl_virt;
1618 ext_pbl.p_pbl_phys = out_params.rq_pbl_phys;
1619
1620 rc = dev->ops->common->chain_alloc(dev->cdev,
1621 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1622 QED_CHAIN_MODE_PBL,
1623 QED_CHAIN_CNT_TYPE_U32,
1624 n_rq_elems,
1625 QEDR_RQE_ELEMENT_SIZE,
1626 &qp->rq.pbl, &ext_pbl);
1627
1628 if (rc)
1629 goto err;
1630
1631 qp->qp_id = out_params.qp_id;
1632 qp->icid = out_params.icid;
1633
1634 qedr_set_iwarp_db_info(dev, qp);
1635 return rc;
1636
1637err:
1638 dev->ops->rdma_destroy_qp(dev->rdma_ctx, qp->qed_qp);
1639
1640 return rc;
1470} 1641}
1471 1642
1472static void qedr_cleanup_kernel(struct qedr_dev *dev, struct qedr_qp *qp) 1643static void qedr_cleanup_kernel(struct qedr_dev *dev, struct qedr_qp *qp)
@@ -1541,8 +1712,12 @@ static int qedr_create_kernel_qp(struct qedr_dev *dev,
1541 1712
1542 n_rq_elems = qp->rq.max_wr * QEDR_MAX_RQE_ELEMENTS_PER_RQE; 1713 n_rq_elems = qp->rq.max_wr * QEDR_MAX_RQE_ELEMENTS_PER_RQE;
1543 1714
1544 rc = qedr_roce_create_kernel_qp(dev, qp, &in_params, 1715 if (rdma_protocol_iwarp(&dev->ibdev, 1))
1545 n_sq_elems, n_rq_elems); 1716 rc = qedr_iwarp_create_kernel_qp(dev, qp, &in_params,
1717 n_sq_elems, n_rq_elems);
1718 else
1719 rc = qedr_roce_create_kernel_qp(dev, qp, &in_params,
1720 n_sq_elems, n_rq_elems);
1546 if (rc) 1721 if (rc)
1547 qedr_cleanup_kernel(dev, qp); 1722 qedr_cleanup_kernel(dev, qp);
1548 1723
@@ -1602,6 +1777,10 @@ struct ib_qp *qedr_create_qp(struct ib_pd *ibpd,
1602 1777
1603 qp->ibqp.qp_num = qp->qp_id; 1778 qp->ibqp.qp_num = qp->qp_id;
1604 1779
1780 rc = qedr_idr_add(dev, qp, qp->qp_id);
1781 if (rc)
1782 goto err;
1783
1605 return &qp->ibqp; 1784 return &qp->ibqp;
1606 1785
1607err: 1786err:
@@ -1689,10 +1868,13 @@ static int qedr_update_qp_state(struct qedr_dev *dev,
1689 /* Update doorbell (in case post_recv was 1868 /* Update doorbell (in case post_recv was
1690 * done before move to RTR) 1869 * done before move to RTR)
1691 */ 1870 */
1692 wmb(); 1871
1693 writel(qp->rq.db_data.raw, qp->rq.db); 1872 if (rdma_protocol_roce(&dev->ibdev, 1)) {
1694 /* Make sure write takes effect */ 1873 wmb();
1695 mmiowb(); 1874 writel(qp->rq.db_data.raw, qp->rq.db);
1875 /* Make sure write takes effect */
1876 mmiowb();
1877 }
1696 break; 1878 break;
1697 case QED_ROCE_QP_STATE_ERR: 1879 case QED_ROCE_QP_STATE_ERR:
1698 break; 1880 break;
@@ -1786,16 +1968,18 @@ int qedr_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1786 else 1968 else
1787 new_qp_state = old_qp_state; 1969 new_qp_state = old_qp_state;
1788 1970
1789 if (!ib_modify_qp_is_ok 1971 if (rdma_protocol_roce(&dev->ibdev, 1)) {
1790 (old_qp_state, new_qp_state, ibqp->qp_type, attr_mask, 1972 if (!ib_modify_qp_is_ok(old_qp_state, new_qp_state,
1791 IB_LINK_LAYER_ETHERNET)) { 1973 ibqp->qp_type, attr_mask,
1792 DP_ERR(dev, 1974 IB_LINK_LAYER_ETHERNET)) {
1793 "modify qp: invalid attribute mask=0x%x specified for\n" 1975 DP_ERR(dev,
1794 "qpn=0x%x of type=0x%x old_qp_state=0x%x, new_qp_state=0x%x\n", 1976 "modify qp: invalid attribute mask=0x%x specified for\n"
1795 attr_mask, qp->qp_id, ibqp->qp_type, old_qp_state, 1977 "qpn=0x%x of type=0x%x old_qp_state=0x%x, new_qp_state=0x%x\n",
1796 new_qp_state); 1978 attr_mask, qp->qp_id, ibqp->qp_type,
1797 rc = -EINVAL; 1979 old_qp_state, new_qp_state);
1798 goto err; 1980 rc = -EINVAL;
1981 goto err;
1982 }
1799 } 1983 }
1800 1984
1801 /* Translate the masks... */ 1985 /* Translate the masks... */
@@ -2082,7 +2266,7 @@ err:
2082 return rc; 2266 return rc;
2083} 2267}
2084 2268
2085int qedr_free_qp_resources(struct qedr_dev *dev, struct qedr_qp *qp) 2269static int qedr_free_qp_resources(struct qedr_dev *dev, struct qedr_qp *qp)
2086{ 2270{
2087 int rc = 0; 2271 int rc = 0;
2088 2272
@@ -2111,15 +2295,34 @@ int qedr_destroy_qp(struct ib_qp *ibqp)
2111 DP_DEBUG(dev, QEDR_MSG_QP, "destroy qp: destroying %p, qp type=%d\n", 2295 DP_DEBUG(dev, QEDR_MSG_QP, "destroy qp: destroying %p, qp type=%d\n",
2112 qp, qp->qp_type); 2296 qp, qp->qp_type);
2113 2297
2114 if ((qp->state != QED_ROCE_QP_STATE_RESET) && 2298 if (rdma_protocol_roce(&dev->ibdev, 1)) {
2115 (qp->state != QED_ROCE_QP_STATE_ERR) && 2299 if ((qp->state != QED_ROCE_QP_STATE_RESET) &&
2116 (qp->state != QED_ROCE_QP_STATE_INIT)) { 2300 (qp->state != QED_ROCE_QP_STATE_ERR) &&
2301 (qp->state != QED_ROCE_QP_STATE_INIT)) {
2117 2302
2118 attr.qp_state = IB_QPS_ERR; 2303 attr.qp_state = IB_QPS_ERR;
2119 attr_mask |= IB_QP_STATE; 2304 attr_mask |= IB_QP_STATE;
2120 2305
2121 /* Change the QP state to ERROR */ 2306 /* Change the QP state to ERROR */
2122 qedr_modify_qp(ibqp, &attr, attr_mask, NULL); 2307 qedr_modify_qp(ibqp, &attr, attr_mask, NULL);
2308 }
2309 } else {
2310 /* Wait for the connect/accept to complete */
2311 if (qp->ep) {
2312 int wait_count = 1;
2313
2314 while (qp->ep->during_connect) {
2315 DP_DEBUG(dev, QEDR_MSG_QP,
2316 "Still in during connect/accept\n");
2317
2318 msleep(100);
2319 if (wait_count++ > 200) {
2320 DP_NOTICE(dev,
2321 "during connect timeout\n");
2322 break;
2323 }
2324 }
2325 }
2123 } 2326 }
2124 2327
2125 if (qp->qp_type == IB_QPT_GSI) 2328 if (qp->qp_type == IB_QPT_GSI)
@@ -2127,8 +2330,10 @@ int qedr_destroy_qp(struct ib_qp *ibqp)
2127 2330
2128 qedr_free_qp_resources(dev, qp); 2331 qedr_free_qp_resources(dev, qp);
2129 2332
2130 kfree(qp); 2333 if (atomic_dec_and_test(&qp->refcnt)) {
2131 2334 qedr_idr_remove(dev, qp->qp_id);
2335 kfree(qp);
2336 }
2132 return rc; 2337 return rc;
2133} 2338}
2134 2339
@@ -2395,7 +2600,6 @@ err0:
2395struct ib_mr *qedr_alloc_mr(struct ib_pd *ibpd, 2600struct ib_mr *qedr_alloc_mr(struct ib_pd *ibpd,
2396 enum ib_mr_type mr_type, u32 max_num_sg) 2601 enum ib_mr_type mr_type, u32 max_num_sg)
2397{ 2602{
2398 struct qedr_dev *dev;
2399 struct qedr_mr *mr; 2603 struct qedr_mr *mr;
2400 2604
2401 if (mr_type != IB_MR_TYPE_MEM_REG) 2605 if (mr_type != IB_MR_TYPE_MEM_REG)
@@ -2406,8 +2610,6 @@ struct ib_mr *qedr_alloc_mr(struct ib_pd *ibpd,
2406 if (IS_ERR(mr)) 2610 if (IS_ERR(mr))
2407 return ERR_PTR(-EINVAL); 2611 return ERR_PTR(-EINVAL);
2408 2612
2409 dev = mr->dev;
2410
2411 return &mr->ibmr; 2613 return &mr->ibmr;
2412} 2614}
2413 2615
@@ -2740,6 +2942,7 @@ static enum ib_wc_opcode qedr_ib_to_wc_opcode(enum ib_wr_opcode opcode)
2740 case IB_WR_SEND_WITH_INV: 2942 case IB_WR_SEND_WITH_INV:
2741 return IB_WC_SEND; 2943 return IB_WC_SEND;
2742 case IB_WR_RDMA_READ: 2944 case IB_WR_RDMA_READ:
2945 case IB_WR_RDMA_READ_WITH_INV:
2743 return IB_WC_RDMA_READ; 2946 return IB_WC_RDMA_READ;
2744 case IB_WR_ATOMIC_CMP_AND_SWP: 2947 case IB_WR_ATOMIC_CMP_AND_SWP:
2745 return IB_WC_COMP_SWAP; 2948 return IB_WC_COMP_SWAP;
@@ -2900,11 +3103,8 @@ static int __qedr_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2900 qp->wqe_wr_id[qp->sq.prod].bytes_len = rwqe->length; 3103 qp->wqe_wr_id[qp->sq.prod].bytes_len = rwqe->length;
2901 break; 3104 break;
2902 case IB_WR_RDMA_READ_WITH_INV: 3105 case IB_WR_RDMA_READ_WITH_INV:
2903 DP_ERR(dev, 3106 SET_FIELD2(wqe->flags, RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG, 1);
2904 "RDMA READ WITH INVALIDATE not supported\n"); 3107 /* fallthrough -- same is identical to RDMA READ */
2905 *bad_wr = wr;
2906 rc = -EINVAL;
2907 break;
2908 3108
2909 case IB_WR_RDMA_READ: 3109 case IB_WR_RDMA_READ:
2910 wqe->req_type = RDMA_SQ_REQ_TYPE_RDMA_RD; 3110 wqe->req_type = RDMA_SQ_REQ_TYPE_RDMA_RD;
@@ -3014,15 +3214,17 @@ int qedr_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3014 3214
3015 spin_lock_irqsave(&qp->q_lock, flags); 3215 spin_lock_irqsave(&qp->q_lock, flags);
3016 3216
3017 if ((qp->state != QED_ROCE_QP_STATE_RTS) && 3217 if (rdma_protocol_roce(&dev->ibdev, 1)) {
3018 (qp->state != QED_ROCE_QP_STATE_ERR) && 3218 if ((qp->state != QED_ROCE_QP_STATE_RTS) &&
3019 (qp->state != QED_ROCE_QP_STATE_SQD)) { 3219 (qp->state != QED_ROCE_QP_STATE_ERR) &&
3020 spin_unlock_irqrestore(&qp->q_lock, flags); 3220 (qp->state != QED_ROCE_QP_STATE_SQD)) {
3021 *bad_wr = wr; 3221 spin_unlock_irqrestore(&qp->q_lock, flags);
3022 DP_DEBUG(dev, QEDR_MSG_CQ, 3222 *bad_wr = wr;
3023 "QP in wrong state! QP icid=0x%x state %d\n", 3223 DP_DEBUG(dev, QEDR_MSG_CQ,
3024 qp->icid, qp->state); 3224 "QP in wrong state! QP icid=0x%x state %d\n",
3025 return -EINVAL; 3225 qp->icid, qp->state);
3226 return -EINVAL;
3227 }
3026 } 3228 }
3027 3229
3028 while (wr) { 3230 while (wr) {
@@ -3142,6 +3344,11 @@ int qedr_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3142 /* Make sure write sticks */ 3344 /* Make sure write sticks */
3143 mmiowb(); 3345 mmiowb();
3144 3346
3347 if (rdma_protocol_iwarp(&dev->ibdev, 1)) {
3348 writel(qp->rq.iwarp_db2_data.raw, qp->rq.iwarp_db2);
3349 mmiowb(); /* for second doorbell */
3350 }
3351
3145 wr = wr->next; 3352 wr = wr->next;
3146 } 3353 }
3147 3354
@@ -3603,23 +3810,3 @@ int qedr_process_mad(struct ib_device *ibdev, int process_mad_flags,
3603 mad_hdr->method, mad_hdr->mgmt_class, mad_hdr->status); 3810 mad_hdr->method, mad_hdr->mgmt_class, mad_hdr->status);
3604 return IB_MAD_RESULT_SUCCESS; 3811 return IB_MAD_RESULT_SUCCESS;
3605} 3812}
3606
3607int qedr_port_immutable(struct ib_device *ibdev, u8 port_num,
3608 struct ib_port_immutable *immutable)
3609{
3610 struct ib_port_attr attr;
3611 int err;
3612
3613 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
3614 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3615
3616 err = ib_query_port(ibdev, port_num, &attr);
3617 if (err)
3618 return err;
3619
3620 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3621 immutable->gid_tbl_len = attr.gid_tbl_len;
3622 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3623
3624 return 0;
3625}
diff --git a/drivers/infiniband/hw/qedr/verbs.h b/drivers/infiniband/hw/qedr/verbs.h
index 0f8ab49d5a1a..1a94425dea33 100644
--- a/drivers/infiniband/hw/qedr/verbs.h
+++ b/drivers/infiniband/hw/qedr/verbs.h
@@ -39,6 +39,8 @@ int qedr_modify_port(struct ib_device *, u8 port, int mask,
39 struct ib_port_modify *props); 39 struct ib_port_modify *props);
40 40
41int qedr_query_gid(struct ib_device *, u8 port, int index, union ib_gid *gid); 41int qedr_query_gid(struct ib_device *, u8 port, int index, union ib_gid *gid);
42int qedr_iw_query_gid(struct ib_device *ibdev, u8 port,
43 int index, union ib_gid *gid);
42 44
43int qedr_query_pkey(struct ib_device *, u8 port, u16 index, u16 *pkey); 45int qedr_query_pkey(struct ib_device *, u8 port, u16 index, u16 *pkey);
44 46
diff --git a/drivers/infiniband/hw/qib/Kconfig b/drivers/infiniband/hw/qib/Kconfig
index e0fdb9201423..cb06314a2ae2 100644
--- a/drivers/infiniband/hw/qib/Kconfig
+++ b/drivers/infiniband/hw/qib/Kconfig
@@ -1,6 +1,7 @@
1config INFINIBAND_QIB 1config INFINIBAND_QIB
2 tristate "Intel PCIe HCA support" 2 tristate "Intel PCIe HCA support"
3 depends on 64BIT && INFINIBAND_RDMAVT 3 depends on 64BIT && INFINIBAND_RDMAVT
4 depends on PCI
4 ---help--- 5 ---help---
5 This is a low-level driver for Intel PCIe QLE InfiniBand host 6 This is a low-level driver for Intel PCIe QLE InfiniBand host
6 channel adapters. This driver does not support the Intel 7 channel adapters. This driver does not support the Intel
diff --git a/drivers/infiniband/hw/qib/qib.h b/drivers/infiniband/hw/qib/qib.h
index f9e1c69603a5..092ed8103842 100644
--- a/drivers/infiniband/hw/qib/qib.h
+++ b/drivers/infiniband/hw/qib/qib.h
@@ -102,18 +102,6 @@ extern const struct pci_error_handlers qib_pci_err_handler;
102#define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000) 102#define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
103 103
104/* 104/*
105 * Struct used to indicate which errors are logged in each of the
106 * error-counters that are logged to EEPROM. A counter is incremented
107 * _once_ (saturating at 255) for each event with any bits set in
108 * the error or hwerror register masks below.
109 */
110#define QIB_EEP_LOG_CNT (4)
111struct qib_eep_log_mask {
112 u64 errs_to_log;
113 u64 hwerrs_to_log;
114};
115
116/*
117 * Below contains all data related to a single context (formerly called port). 105 * Below contains all data related to a single context (formerly called port).
118 */ 106 */
119 107
@@ -443,14 +431,12 @@ struct qib_irq_notify;
443#endif 431#endif
444 432
445struct qib_msix_entry { 433struct qib_msix_entry {
446 int irq;
447 void *arg; 434 void *arg;
448#ifdef CONFIG_INFINIBAND_QIB_DCA 435#ifdef CONFIG_INFINIBAND_QIB_DCA
449 int dca; 436 int dca;
450 int rcv; 437 int rcv;
451 struct qib_irq_notify *notifier; 438 struct qib_irq_notify *notifier;
452#endif 439#endif
453 char name[MAX_NAME_SIZE];
454 cpumask_var_t mask; 440 cpumask_var_t mask;
455}; 441};
456 442
@@ -1081,11 +1067,6 @@ struct qib_devdata {
1081 /* control high-level access to EEPROM */ 1067 /* control high-level access to EEPROM */
1082 struct mutex eep_lock; 1068 struct mutex eep_lock;
1083 uint64_t traffic_wds; 1069 uint64_t traffic_wds;
1084 /*
1085 * masks for which bits of errs, hwerrs that cause
1086 * each of the counters to increment.
1087 */
1088 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1089 struct qib_diag_client *diag_client; 1070 struct qib_diag_client *diag_client;
1090 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */ 1071 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */
1091 struct diag_observer_list_elt *diag_observer_list; 1072 struct diag_observer_list_elt *diag_observer_list;
@@ -1188,7 +1169,7 @@ int qib_set_lid(struct qib_pportdata *, u32, u8);
1188void qib_hol_down(struct qib_pportdata *); 1169void qib_hol_down(struct qib_pportdata *);
1189void qib_hol_init(struct qib_pportdata *); 1170void qib_hol_init(struct qib_pportdata *);
1190void qib_hol_up(struct qib_pportdata *); 1171void qib_hol_up(struct qib_pportdata *);
1191void qib_hol_event(unsigned long); 1172void qib_hol_event(struct timer_list *);
1192void qib_disable_after_error(struct qib_devdata *); 1173void qib_disable_after_error(struct qib_devdata *);
1193int qib_set_uevent_bits(struct qib_pportdata *, const int); 1174int qib_set_uevent_bits(struct qib_pportdata *, const int);
1194 1175
@@ -1299,10 +1280,9 @@ int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1299int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr, 1280int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1300 const void *buffer, int len); 1281 const void *buffer, int len);
1301void qib_get_eeprom_info(struct qib_devdata *); 1282void qib_get_eeprom_info(struct qib_devdata *);
1302#define qib_inc_eeprom_err(dd, eidx, incr)
1303void qib_dump_lookup_output_queue(struct qib_devdata *); 1283void qib_dump_lookup_output_queue(struct qib_devdata *);
1304void qib_force_pio_avail_update(struct qib_devdata *); 1284void qib_force_pio_avail_update(struct qib_devdata *);
1305void qib_clear_symerror_on_linkup(unsigned long opaque); 1285void qib_clear_symerror_on_linkup(struct timer_list *t);
1306 1286
1307/* 1287/*
1308 * Set LED override, only the two LSBs have "public" meaning, but 1288 * Set LED override, only the two LSBs have "public" meaning, but
@@ -1434,10 +1414,8 @@ int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1434 const struct pci_device_id *); 1414 const struct pci_device_id *);
1435void qib_pcie_ddcleanup(struct qib_devdata *); 1415void qib_pcie_ddcleanup(struct qib_devdata *);
1436int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent); 1416int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent);
1437int qib_reinit_intr(struct qib_devdata *); 1417void qib_free_irq(struct qib_devdata *dd);
1438void qib_enable_intx(struct qib_devdata *dd); 1418int qib_reinit_intr(struct qib_devdata *dd);
1439void qib_nomsi(struct qib_devdata *);
1440void qib_nomsix(struct qib_devdata *);
1441void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *); 1419void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1442void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8); 1420void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1443/* interrupts for device */ 1421/* interrupts for device */
diff --git a/drivers/infiniband/hw/qib/qib_7220.h b/drivers/infiniband/hw/qib/qib_7220.h
index a5356cb4252e..9ecaab6232e3 100644
--- a/drivers/infiniband/hw/qib/qib_7220.h
+++ b/drivers/infiniband/hw/qib/qib_7220.h
@@ -67,7 +67,6 @@ struct qib_chip_specific {
67 u32 lastbuf_for_pio; 67 u32 lastbuf_for_pio;
68 u32 updthresh; /* current AvailUpdThld */ 68 u32 updthresh; /* current AvailUpdThld */
69 u32 updthresh_dflt; /* default AvailUpdThld */ 69 u32 updthresh_dflt; /* default AvailUpdThld */
70 int irq;
71 u8 presets_needed; 70 u8 presets_needed;
72 u8 relock_timer_active; 71 u8 relock_timer_active;
73 char emsgbuf[128]; 72 char emsgbuf[128];
@@ -75,6 +74,7 @@ struct qib_chip_specific {
75 char bitsmsgbuf[64]; 74 char bitsmsgbuf[64];
76 struct timer_list relock_timer; 75 struct timer_list relock_timer;
77 unsigned int relock_interval; /* in jiffies */ 76 unsigned int relock_interval; /* in jiffies */
77 struct qib_devdata *dd;
78}; 78};
79 79
80struct qib_chippport_specific { 80struct qib_chippport_specific {
diff --git a/drivers/infiniband/hw/qib/qib_diag.c b/drivers/infiniband/hw/qib/qib_diag.c
index 775018b32b0d..a9377eee8734 100644
--- a/drivers/infiniband/hw/qib/qib_diag.c
+++ b/drivers/infiniband/hw/qib/qib_diag.c
@@ -761,7 +761,6 @@ static ssize_t qib_diag_read(struct file *fp, char __user *data,
761{ 761{
762 struct qib_diag_client *dc = fp->private_data; 762 struct qib_diag_client *dc = fp->private_data;
763 struct qib_devdata *dd = dc->dd; 763 struct qib_devdata *dd = dc->dd;
764 void __iomem *kreg_base;
765 ssize_t ret; 764 ssize_t ret;
766 765
767 if (dc->pid != current->pid) { 766 if (dc->pid != current->pid) {
@@ -769,8 +768,6 @@ static ssize_t qib_diag_read(struct file *fp, char __user *data,
769 goto bail; 768 goto bail;
770 } 769 }
771 770
772 kreg_base = dd->kregbase;
773
774 if (count == 0) 771 if (count == 0)
775 ret = 0; 772 ret = 0;
776 else if ((count % 4) || (*off % 4)) 773 else if ((count % 4) || (*off % 4))
@@ -838,7 +835,6 @@ static ssize_t qib_diag_write(struct file *fp, const char __user *data,
838{ 835{
839 struct qib_diag_client *dc = fp->private_data; 836 struct qib_diag_client *dc = fp->private_data;
840 struct qib_devdata *dd = dc->dd; 837 struct qib_devdata *dd = dc->dd;
841 void __iomem *kreg_base;
842 ssize_t ret; 838 ssize_t ret;
843 839
844 if (dc->pid != current->pid) { 840 if (dc->pid != current->pid) {
@@ -846,8 +842,6 @@ static ssize_t qib_diag_write(struct file *fp, const char __user *data,
846 goto bail; 842 goto bail;
847 } 843 }
848 844
849 kreg_base = dd->kregbase;
850
851 if (count == 0) 845 if (count == 0)
852 ret = 0; 846 ret = 0;
853 else if ((count % 4) || (*off % 4)) 847 else if ((count % 4) || (*off % 4))
diff --git a/drivers/infiniband/hw/qib/qib_driver.c b/drivers/infiniband/hw/qib/qib_driver.c
index 719906a9fd51..33d3335385e8 100644
--- a/drivers/infiniband/hw/qib/qib_driver.c
+++ b/drivers/infiniband/hw/qib/qib_driver.c
@@ -682,9 +682,10 @@ int qib_set_lid(struct qib_pportdata *ppd, u32 lid, u8 lmc)
682/* Below is "non-zero" to force override, but both actual LEDs are off */ 682/* Below is "non-zero" to force override, but both actual LEDs are off */
683#define LED_OVER_BOTH_OFF (8) 683#define LED_OVER_BOTH_OFF (8)
684 684
685static void qib_run_led_override(unsigned long opaque) 685static void qib_run_led_override(struct timer_list *t)
686{ 686{
687 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 687 struct qib_pportdata *ppd = from_timer(ppd, t,
688 led_override_timer);
688 struct qib_devdata *dd = ppd->dd; 689 struct qib_devdata *dd = ppd->dd;
689 int timeoff; 690 int timeoff;
690 int ph_idx; 691 int ph_idx;
@@ -735,9 +736,7 @@ void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val)
735 */ 736 */
736 if (atomic_inc_return(&ppd->led_override_timer_active) == 1) { 737 if (atomic_inc_return(&ppd->led_override_timer_active) == 1) {
737 /* Need to start timer */ 738 /* Need to start timer */
738 init_timer(&ppd->led_override_timer); 739 timer_setup(&ppd->led_override_timer, qib_run_led_override, 0);
739 ppd->led_override_timer.function = qib_run_led_override;
740 ppd->led_override_timer.data = (unsigned long) ppd;
741 ppd->led_override_timer.expires = jiffies + 1; 740 ppd->led_override_timer.expires = jiffies + 1;
742 add_timer(&ppd->led_override_timer); 741 add_timer(&ppd->led_override_timer);
743 } else { 742 } else {
diff --git a/drivers/infiniband/hw/qib/qib_file_ops.c b/drivers/infiniband/hw/qib/qib_file_ops.c
index 9396c1807cc3..2d6a191afec0 100644
--- a/drivers/infiniband/hw/qib/qib_file_ops.c
+++ b/drivers/infiniband/hw/qib/qib_file_ops.c
@@ -696,15 +696,8 @@ static void qib_clean_part_key(struct qib_ctxtdata *rcd,
696 struct qib_devdata *dd) 696 struct qib_devdata *dd)
697{ 697{
698 int i, j, pchanged = 0; 698 int i, j, pchanged = 0;
699 u64 oldpkey;
700 struct qib_pportdata *ppd = rcd->ppd; 699 struct qib_pportdata *ppd = rcd->ppd;
701 700
702 /* for debugging only */
703 oldpkey = (u64) ppd->pkeys[0] |
704 ((u64) ppd->pkeys[1] << 16) |
705 ((u64) ppd->pkeys[2] << 32) |
706 ((u64) ppd->pkeys[3] << 48);
707
708 for (i = 0; i < ARRAY_SIZE(rcd->pkeys); i++) { 701 for (i = 0; i < ARRAY_SIZE(rcd->pkeys); i++) {
709 if (!rcd->pkeys[i]) 702 if (!rcd->pkeys[i])
710 continue; 703 continue;
@@ -1817,7 +1810,6 @@ static int qib_close(struct inode *in, struct file *fp)
1817 struct qib_devdata *dd; 1810 struct qib_devdata *dd;
1818 unsigned long flags; 1811 unsigned long flags;
1819 unsigned ctxt; 1812 unsigned ctxt;
1820 pid_t pid;
1821 1813
1822 mutex_lock(&qib_mutex); 1814 mutex_lock(&qib_mutex);
1823 1815
@@ -1859,7 +1851,6 @@ static int qib_close(struct inode *in, struct file *fp)
1859 spin_lock_irqsave(&dd->uctxt_lock, flags); 1851 spin_lock_irqsave(&dd->uctxt_lock, flags);
1860 ctxt = rcd->ctxt; 1852 ctxt = rcd->ctxt;
1861 dd->rcd[ctxt] = NULL; 1853 dd->rcd[ctxt] = NULL;
1862 pid = rcd->pid;
1863 rcd->pid = 0; 1854 rcd->pid = 0;
1864 spin_unlock_irqrestore(&dd->uctxt_lock, flags); 1855 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1865 1856
diff --git a/drivers/infiniband/hw/qib/qib_iba6120.c b/drivers/infiniband/hw/qib/qib_iba6120.c
index 3259a60e4f4f..8a15e5c7dd91 100644
--- a/drivers/infiniband/hw/qib/qib_iba6120.c
+++ b/drivers/infiniband/hw/qib/qib_iba6120.c
@@ -245,7 +245,6 @@ struct qib_chip_specific {
245 u64 iblnkerrsnap; 245 u64 iblnkerrsnap;
246 u64 ibcctrl; /* shadow for kr_ibcctrl */ 246 u64 ibcctrl; /* shadow for kr_ibcctrl */
247 u32 lastlinkrecov; /* link recovery issue */ 247 u32 lastlinkrecov; /* link recovery issue */
248 int irq;
249 u32 cntrnamelen; 248 u32 cntrnamelen;
250 u32 portcntrnamelen; 249 u32 portcntrnamelen;
251 u32 ncntrs; 250 u32 ncntrs;
@@ -266,6 +265,7 @@ struct qib_chip_specific {
266 u64 rpkts; /* total packets received (sample result) */ 265 u64 rpkts; /* total packets received (sample result) */
267 u64 xmit_wait; /* # of ticks no data sent (sample result) */ 266 u64 xmit_wait; /* # of ticks no data sent (sample result) */
268 struct timer_list pma_timer; 267 struct timer_list pma_timer;
268 struct qib_pportdata *ppd;
269 char emsgbuf[128]; 269 char emsgbuf[128];
270 char bitsmsgbuf[64]; 270 char bitsmsgbuf[64];
271 u8 pma_sample_status; 271 u8 pma_sample_status;
@@ -749,7 +749,6 @@ static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg,
749 u32 bits, ctrl; 749 u32 bits, ctrl;
750 int isfatal = 0; 750 int isfatal = 0;
751 char *bitsmsg; 751 char *bitsmsg;
752 int log_idx;
753 752
754 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); 753 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
755 if (!hwerrs) 754 if (!hwerrs)
@@ -771,11 +770,6 @@ static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg,
771 770
772 hwerrs &= dd->cspec->hwerrmask; 771 hwerrs &= dd->cspec->hwerrmask;
773 772
774 /* We log some errors to EEPROM, check if we have any of those. */
775 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
776 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
777 qib_inc_eeprom_err(dd, log_idx, 1);
778
779 /* 773 /*
780 * Make sure we get this much out, unless told to be quiet, 774 * Make sure we get this much out, unless told to be quiet,
781 * or it's occurred within the last 5 seconds. 775 * or it's occurred within the last 5 seconds.
@@ -1005,7 +999,6 @@ static void handle_6120_errors(struct qib_devdata *dd, u64 errs)
1005 char *msg; 999 char *msg;
1006 u64 ignore_this_time = 0; 1000 u64 ignore_this_time = 0;
1007 u64 iserr = 0; 1001 u64 iserr = 0;
1008 int log_idx;
1009 struct qib_pportdata *ppd = dd->pport; 1002 struct qib_pportdata *ppd = dd->pport;
1010 u64 mask; 1003 u64 mask;
1011 1004
@@ -1016,10 +1009,6 @@ static void handle_6120_errors(struct qib_devdata *dd, u64 errs)
1016 /* do these first, they are most important */ 1009 /* do these first, they are most important */
1017 if (errs & ERR_MASK(HardwareErr)) 1010 if (errs & ERR_MASK(HardwareErr))
1018 qib_handle_6120_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); 1011 qib_handle_6120_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1019 else
1020 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1021 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1022 qib_inc_eeprom_err(dd, log_idx, 1);
1023 1012
1024 if (errs & ~IB_E_BITSEXTANT) 1013 if (errs & ~IB_E_BITSEXTANT)
1025 qib_dev_err(dd, 1014 qib_dev_err(dd,
@@ -1485,15 +1474,6 @@ static void qib_6120_setup_setextled(struct qib_pportdata *ppd, u32 on)
1485 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 1474 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1486} 1475}
1487 1476
1488static void qib_6120_free_irq(struct qib_devdata *dd)
1489{
1490 if (dd->cspec->irq) {
1491 free_irq(dd->cspec->irq, dd);
1492 dd->cspec->irq = 0;
1493 }
1494 qib_nomsi(dd);
1495}
1496
1497/** 1477/**
1498 * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff 1478 * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff
1499 * @dd: the qlogic_ib device 1479 * @dd: the qlogic_ib device
@@ -1502,7 +1482,7 @@ static void qib_6120_free_irq(struct qib_devdata *dd)
1502*/ 1482*/
1503static void qib_6120_setup_cleanup(struct qib_devdata *dd) 1483static void qib_6120_setup_cleanup(struct qib_devdata *dd)
1504{ 1484{
1505 qib_6120_free_irq(dd); 1485 qib_free_irq(dd);
1506 kfree(dd->cspec->cntrs); 1486 kfree(dd->cspec->cntrs);
1507 kfree(dd->cspec->portcntrs); 1487 kfree(dd->cspec->portcntrs);
1508 if (dd->cspec->dummy_hdrq) { 1488 if (dd->cspec->dummy_hdrq) {
@@ -1706,6 +1686,8 @@ bail:
1706 */ 1686 */
1707static void qib_setup_6120_interrupt(struct qib_devdata *dd) 1687static void qib_setup_6120_interrupt(struct qib_devdata *dd)
1708{ 1688{
1689 int ret;
1690
1709 /* 1691 /*
1710 * If the chip supports added error indication via GPIO pins, 1692 * If the chip supports added error indication via GPIO pins,
1711 * enable interrupts on those bits so the interrupt routine 1693 * enable interrupts on those bits so the interrupt routine
@@ -1719,19 +1701,12 @@ static void qib_setup_6120_interrupt(struct qib_devdata *dd)
1719 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 1701 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1720 } 1702 }
1721 1703
1722 if (!dd->cspec->irq) 1704 ret = pci_request_irq(dd->pcidev, 0, qib_6120intr, NULL, dd,
1705 QIB_DRV_NAME);
1706 if (ret)
1723 qib_dev_err(dd, 1707 qib_dev_err(dd,
1724 "irq is 0, BIOS error? Interrupts won't work\n"); 1708 "Couldn't setup interrupt (irq=%d): %d\n",
1725 else { 1709 pci_irq_vector(dd->pcidev, 0), ret);
1726 int ret;
1727
1728 ret = request_irq(dd->cspec->irq, qib_6120intr, 0,
1729 QIB_DRV_NAME, dd);
1730 if (ret)
1731 qib_dev_err(dd,
1732 "Couldn't setup interrupt (irq=%d): %d\n",
1733 dd->cspec->irq, ret);
1734 }
1735} 1710}
1736 1711
1737/** 1712/**
@@ -1929,7 +1904,6 @@ static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr,
1929 u32 type, unsigned long pa) 1904 u32 type, unsigned long pa)
1930{ 1905{
1931 u32 __iomem *tidp32 = (u32 __iomem *)tidptr; 1906 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1932 u32 tidx;
1933 1907
1934 if (!dd->kregbase) 1908 if (!dd->kregbase)
1935 return; 1909 return;
@@ -1953,7 +1927,6 @@ static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr,
1953 else /* for now, always full 4KB page */ 1927 else /* for now, always full 4KB page */
1954 pa |= 2 << 29; 1928 pa |= 2 << 29;
1955 } 1929 }
1956 tidx = tidptr - dd->egrtidbase;
1957 writel(pa, tidp32); 1930 writel(pa, tidp32);
1958 mmiowb(); 1931 mmiowb();
1959} 1932}
@@ -2647,9 +2620,9 @@ static void qib_chk_6120_errormask(struct qib_devdata *dd)
2647 * need traffic_wds done the way it is 2620 * need traffic_wds done the way it is
2648 * called from add_timer 2621 * called from add_timer
2649 */ 2622 */
2650static void qib_get_6120_faststats(unsigned long opaque) 2623static void qib_get_6120_faststats(struct timer_list *t)
2651{ 2624{
2652 struct qib_devdata *dd = (struct qib_devdata *) opaque; 2625 struct qib_devdata *dd = from_timer(dd, t, stats_timer);
2653 struct qib_pportdata *ppd = dd->pport; 2626 struct qib_pportdata *ppd = dd->pport;
2654 unsigned long flags; 2627 unsigned long flags;
2655 u64 traffic_wds; 2628 u64 traffic_wds;
@@ -2937,10 +2910,10 @@ static int qib_6120_set_loopback(struct qib_pportdata *ppd, const char *what)
2937 return ret; 2910 return ret;
2938} 2911}
2939 2912
2940static void pma_6120_timer(unsigned long data) 2913static void pma_6120_timer(struct timer_list *t)
2941{ 2914{
2942 struct qib_pportdata *ppd = (struct qib_pportdata *)data; 2915 struct qib_chip_specific *cs = from_timer(cs, t, pma_timer);
2943 struct qib_chip_specific *cs = ppd->dd->cspec; 2916 struct qib_pportdata *ppd = cs->ppd;
2944 struct qib_ibport *ibp = &ppd->ibport_data; 2917 struct qib_ibport *ibp = &ppd->ibport_data;
2945 unsigned long flags; 2918 unsigned long flags;
2946 2919
@@ -3205,6 +3178,7 @@ static int init_6120_variables(struct qib_devdata *dd)
3205 dd->num_pports = 1; 3178 dd->num_pports = 1;
3206 3179
3207 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports); 3180 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports);
3181 dd->cspec->ppd = ppd;
3208 ppd->cpspec = NULL; /* not used in this chip */ 3182 ppd->cpspec = NULL; /* not used in this chip */
3209 3183
3210 spin_lock_init(&dd->cspec->kernel_tid_lock); 3184 spin_lock_init(&dd->cspec->kernel_tid_lock);
@@ -3242,20 +3216,6 @@ static int init_6120_variables(struct qib_devdata *dd)
3242 if (qib_unordered_wc()) 3216 if (qib_unordered_wc())
3243 dd->flags |= QIB_PIO_FLUSH_WC; 3217 dd->flags |= QIB_PIO_FLUSH_WC;
3244 3218
3245 /*
3246 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
3247 * 2 is Some Misc, 3 is reserved for future.
3248 */
3249 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
3250
3251 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
3252 if (qib_unordered_wc())
3253 dd->eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
3254
3255 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
3256
3257 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
3258
3259 ret = qib_init_pportdata(ppd, dd, 0, 1); 3219 ret = qib_init_pportdata(ppd, dd, 0, 1);
3260 if (ret) 3220 if (ret)
3261 goto bail; 3221 goto bail;
@@ -3289,11 +3249,8 @@ static int init_6120_variables(struct qib_devdata *dd)
3289 dd->rhdrhead_intr_off = 1ULL << 32; 3249 dd->rhdrhead_intr_off = 1ULL << 32;
3290 3250
3291 /* setup the stats timer; the add_timer is done at end of init */ 3251 /* setup the stats timer; the add_timer is done at end of init */
3292 setup_timer(&dd->stats_timer, qib_get_6120_faststats, 3252 timer_setup(&dd->stats_timer, qib_get_6120_faststats, 0);
3293 (unsigned long)dd); 3253 timer_setup(&dd->cspec->pma_timer, pma_6120_timer, 0);
3294
3295 setup_timer(&dd->cspec->pma_timer, pma_6120_timer,
3296 (unsigned long)ppd);
3297 3254
3298 dd->ureg_align = qib_read_kreg32(dd, kr_palign); 3255 dd->ureg_align = qib_read_kreg32(dd, kr_palign);
3299 3256
@@ -3490,7 +3447,7 @@ struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev,
3490 dd->f_bringup_serdes = qib_6120_bringup_serdes; 3447 dd->f_bringup_serdes = qib_6120_bringup_serdes;
3491 dd->f_cleanup = qib_6120_setup_cleanup; 3448 dd->f_cleanup = qib_6120_setup_cleanup;
3492 dd->f_clear_tids = qib_6120_clear_tids; 3449 dd->f_clear_tids = qib_6120_clear_tids;
3493 dd->f_free_irq = qib_6120_free_irq; 3450 dd->f_free_irq = qib_free_irq;
3494 dd->f_get_base_info = qib_6120_get_base_info; 3451 dd->f_get_base_info = qib_6120_get_base_info;
3495 dd->f_get_msgheader = qib_6120_get_msgheader; 3452 dd->f_get_msgheader = qib_6120_get_msgheader;
3496 dd->f_getsendbuf = qib_6120_getsendbuf; 3453 dd->f_getsendbuf = qib_6120_getsendbuf;
@@ -3559,8 +3516,6 @@ struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev,
3559 if (qib_pcie_params(dd, 8, NULL)) 3516 if (qib_pcie_params(dd, 8, NULL))
3560 qib_dev_err(dd, 3517 qib_dev_err(dd,
3561 "Failed to setup PCIe or interrupts; continuing anyway\n"); 3518 "Failed to setup PCIe or interrupts; continuing anyway\n");
3562 dd->cspec->irq = pdev->irq; /* save IRQ */
3563
3564 /* clear diagctrl register, in case diags were running and crashed */ 3519 /* clear diagctrl register, in case diags were running and crashed */
3565 qib_write_kreg(dd, kr_hwdiagctrl, 0); 3520 qib_write_kreg(dd, kr_hwdiagctrl, 0);
3566 3521
diff --git a/drivers/infiniband/hw/qib/qib_iba7220.c b/drivers/infiniband/hw/qib/qib_iba7220.c
index 04bdd3d487b1..bdff2326731e 100644
--- a/drivers/infiniband/hw/qib/qib_iba7220.c
+++ b/drivers/infiniband/hw/qib/qib_iba7220.c
@@ -1042,9 +1042,11 @@ done:
1042 return iserr; 1042 return iserr;
1043} 1043}
1044 1044
1045static void reenable_7220_chase(unsigned long opaque) 1045static void reenable_7220_chase(struct timer_list *t)
1046{ 1046{
1047 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 1047 struct qib_chippport_specific *cpspec = from_timer(cpspec, t,
1048 chase_timer);
1049 struct qib_pportdata *ppd = &cpspec->pportdata;
1048 1050
1049 ppd->cpspec->chase_timer.expires = 0; 1051 ppd->cpspec->chase_timer.expires = 0;
1050 qib_set_ib_7220_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, 1052 qib_set_ib_7220_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
@@ -1094,7 +1096,6 @@ static void handle_7220_errors(struct qib_devdata *dd, u64 errs)
1094 char *msg; 1096 char *msg;
1095 u64 ignore_this_time = 0; 1097 u64 ignore_this_time = 0;
1096 u64 iserr = 0; 1098 u64 iserr = 0;
1097 int log_idx;
1098 struct qib_pportdata *ppd = dd->pport; 1099 struct qib_pportdata *ppd = dd->pport;
1099 u64 mask; 1100 u64 mask;
1100 1101
@@ -1105,10 +1106,6 @@ static void handle_7220_errors(struct qib_devdata *dd, u64 errs)
1105 /* do these first, they are most important */ 1106 /* do these first, they are most important */
1106 if (errs & ERR_MASK(HardwareErr)) 1107 if (errs & ERR_MASK(HardwareErr))
1107 qib_7220_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); 1108 qib_7220_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1108 else
1109 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1110 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1111 qib_inc_eeprom_err(dd, log_idx, 1);
1112 1109
1113 if (errs & QLOGIC_IB_E_SDMAERRS) 1110 if (errs & QLOGIC_IB_E_SDMAERRS)
1114 sdma_7220_errors(ppd, errs); 1111 sdma_7220_errors(ppd, errs);
@@ -1302,7 +1299,6 @@ static void qib_7220_handle_hwerrors(struct qib_devdata *dd, char *msg,
1302 u32 bits, ctrl; 1299 u32 bits, ctrl;
1303 int isfatal = 0; 1300 int isfatal = 0;
1304 char *bitsmsg; 1301 char *bitsmsg;
1305 int log_idx;
1306 1302
1307 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); 1303 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
1308 if (!hwerrs) 1304 if (!hwerrs)
@@ -1326,10 +1322,6 @@ static void qib_7220_handle_hwerrors(struct qib_devdata *dd, char *msg,
1326 1322
1327 hwerrs &= dd->cspec->hwerrmask; 1323 hwerrs &= dd->cspec->hwerrmask;
1328 1324
1329 /* We log some errors to EEPROM, check if we have any of those. */
1330 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1331 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
1332 qib_inc_eeprom_err(dd, log_idx, 1);
1333 if (hwerrs & ~(TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC | 1325 if (hwerrs & ~(TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC |
1334 RXE_PARITY)) 1326 RXE_PARITY))
1335 qib_devinfo(dd->pcidev, 1327 qib_devinfo(dd->pcidev,
@@ -1663,7 +1655,7 @@ static void qib_7220_quiet_serdes(struct qib_pportdata *ppd)
1663 dd->control | QLOGIC_IB_C_FREEZEMODE); 1655 dd->control | QLOGIC_IB_C_FREEZEMODE);
1664 1656
1665 ppd->cpspec->chase_end = 0; 1657 ppd->cpspec->chase_end = 0;
1666 if (ppd->cpspec->chase_timer.data) /* if initted */ 1658 if (ppd->cpspec->chase_timer.function) /* if initted */
1667 del_timer_sync(&ppd->cpspec->chase_timer); 1659 del_timer_sync(&ppd->cpspec->chase_timer);
1668 1660
1669 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta || 1661 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
@@ -1780,15 +1772,6 @@ static void qib_setup_7220_setextled(struct qib_pportdata *ppd, u32 on)
1780 qib_write_kreg(dd, kr_rcvpktledcnt, ledblink); 1772 qib_write_kreg(dd, kr_rcvpktledcnt, ledblink);
1781} 1773}
1782 1774
1783static void qib_7220_free_irq(struct qib_devdata *dd)
1784{
1785 if (dd->cspec->irq) {
1786 free_irq(dd->cspec->irq, dd);
1787 dd->cspec->irq = 0;
1788 }
1789 qib_nomsi(dd);
1790}
1791
1792/* 1775/*
1793 * qib_setup_7220_cleanup - clean up any per-chip chip-specific stuff 1776 * qib_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1794 * @dd: the qlogic_ib device 1777 * @dd: the qlogic_ib device
@@ -1798,7 +1781,7 @@ static void qib_7220_free_irq(struct qib_devdata *dd)
1798 */ 1781 */
1799static void qib_setup_7220_cleanup(struct qib_devdata *dd) 1782static void qib_setup_7220_cleanup(struct qib_devdata *dd)
1800{ 1783{
1801 qib_7220_free_irq(dd); 1784 qib_free_irq(dd);
1802 kfree(dd->cspec->cntrs); 1785 kfree(dd->cspec->cntrs);
1803 kfree(dd->cspec->portcntrs); 1786 kfree(dd->cspec->portcntrs);
1804} 1787}
@@ -2026,20 +2009,14 @@ bail:
2026 */ 2009 */
2027static void qib_setup_7220_interrupt(struct qib_devdata *dd) 2010static void qib_setup_7220_interrupt(struct qib_devdata *dd)
2028{ 2011{
2029 if (!dd->cspec->irq) 2012 int ret;
2030 qib_dev_err(dd,
2031 "irq is 0, BIOS error? Interrupts won't work\n");
2032 else {
2033 int ret = request_irq(dd->cspec->irq, qib_7220intr,
2034 dd->msi_lo ? 0 : IRQF_SHARED,
2035 QIB_DRV_NAME, dd);
2036 2013
2037 if (ret) 2014 ret = pci_request_irq(dd->pcidev, 0, qib_7220intr, NULL, dd,
2038 qib_dev_err(dd, 2015 QIB_DRV_NAME);
2039 "Couldn't setup %s interrupt (irq=%d): %d\n", 2016 if (ret)
2040 dd->msi_lo ? "MSI" : "INTx", 2017 qib_dev_err(dd, "Couldn't setup %s interrupt (irq=%d): %d\n",
2041 dd->cspec->irq, ret); 2018 dd->pcidev->msi_enabled ? "MSI" : "INTx",
2042 } 2019 pci_irq_vector(dd->pcidev, 0), ret);
2043} 2020}
2044 2021
2045/** 2022/**
@@ -3263,9 +3240,9 @@ done:
3263 * need traffic_wds done the way it is 3240 * need traffic_wds done the way it is
3264 * called from add_timer 3241 * called from add_timer
3265 */ 3242 */
3266static void qib_get_7220_faststats(unsigned long opaque) 3243static void qib_get_7220_faststats(struct timer_list *t)
3267{ 3244{
3268 struct qib_devdata *dd = (struct qib_devdata *) opaque; 3245 struct qib_devdata *dd = from_timer(dd, t, stats_timer);
3269 struct qib_pportdata *ppd = dd->pport; 3246 struct qib_pportdata *ppd = dd->pport;
3270 unsigned long flags; 3247 unsigned long flags;
3271 u64 traffic_wds; 3248 u64 traffic_wds;
@@ -3302,16 +3279,12 @@ static int qib_7220_intr_fallback(struct qib_devdata *dd)
3302 return 0; 3279 return 0;
3303 3280
3304 qib_devinfo(dd->pcidev, 3281 qib_devinfo(dd->pcidev,
3305 "MSI interrupt not detected, trying INTx interrupts\n"); 3282 "MSI interrupt not detected, trying INTx interrupts\n");
3306 qib_7220_free_irq(dd); 3283
3307 qib_enable_intx(dd); 3284 qib_free_irq(dd);
3308 /* 3285 dd->msi_lo = 0;
3309 * Some newer kernels require free_irq before disable_msi, 3286 if (pci_alloc_irq_vectors(dd->pcidev, 1, 1, PCI_IRQ_LEGACY) < 0)
3310 * and irq can be changed during disable and INTx enable 3287 qib_dev_err(dd, "Failed to enable INTx\n");
3311 * and we need to therefore use the pcidev->irq value,
3312 * not our saved MSI value.
3313 */
3314 dd->cspec->irq = dd->pcidev->irq;
3315 qib_setup_7220_interrupt(dd); 3288 qib_setup_7220_interrupt(dd);
3316 return 1; 3289 return 1;
3317} 3290}
@@ -3543,7 +3516,6 @@ static void autoneg_7220_work(struct work_struct *work)
3543{ 3516{
3544 struct qib_pportdata *ppd; 3517 struct qib_pportdata *ppd;
3545 struct qib_devdata *dd; 3518 struct qib_devdata *dd;
3546 u64 startms;
3547 u32 i; 3519 u32 i;
3548 unsigned long flags; 3520 unsigned long flags;
3549 3521
@@ -3551,8 +3523,6 @@ static void autoneg_7220_work(struct work_struct *work)
3551 autoneg_work.work)->pportdata; 3523 autoneg_work.work)->pportdata;
3552 dd = ppd->dd; 3524 dd = ppd->dd;
3553 3525
3554 startms = jiffies_to_msecs(jiffies);
3555
3556 /* 3526 /*
3557 * Busy wait for this first part, it should be at most a 3527 * Busy wait for this first part, it should be at most a
3558 * few hundred usec, since we scheduled ourselves for 2msec. 3528 * few hundred usec, since we scheduled ourselves for 2msec.
@@ -3997,6 +3967,7 @@ static int qib_init_7220_variables(struct qib_devdata *dd)
3997 dd->num_pports = 1; 3967 dd->num_pports = 1;
3998 3968
3999 dd->cspec = (struct qib_chip_specific *)(cpspec + dd->num_pports); 3969 dd->cspec = (struct qib_chip_specific *)(cpspec + dd->num_pports);
3970 dd->cspec->dd = dd;
4000 ppd->cpspec = cpspec; 3971 ppd->cpspec = cpspec;
4001 3972
4002 spin_lock_init(&dd->cspec->sdepb_lock); 3973 spin_lock_init(&dd->cspec->sdepb_lock);
@@ -4035,16 +4006,6 @@ static int qib_init_7220_variables(struct qib_devdata *dd)
4035 dd->flags |= qib_special_trigger ? 4006 dd->flags |= qib_special_trigger ?
4036 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA; 4007 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
4037 4008
4038 /*
4039 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
4040 * 2 is Some Misc, 3 is reserved for future.
4041 */
4042 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
4043
4044 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
4045
4046 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
4047
4048 init_waitqueue_head(&cpspec->autoneg_wait); 4009 init_waitqueue_head(&cpspec->autoneg_wait);
4049 INIT_DELAYED_WORK(&cpspec->autoneg_work, autoneg_7220_work); 4010 INIT_DELAYED_WORK(&cpspec->autoneg_work, autoneg_7220_work);
4050 4011
@@ -4069,8 +4030,7 @@ static int qib_init_7220_variables(struct qib_devdata *dd)
4069 if (!qib_mini_init) 4030 if (!qib_mini_init)
4070 qib_write_kreg(dd, kr_rcvbthqp, QIB_KD_QP); 4031 qib_write_kreg(dd, kr_rcvbthqp, QIB_KD_QP);
4071 4032
4072 setup_timer(&ppd->cpspec->chase_timer, reenable_7220_chase, 4033 timer_setup(&ppd->cpspec->chase_timer, reenable_7220_chase, 0);
4073 (unsigned long)ppd);
4074 4034
4075 qib_num_cfg_vls = 1; /* if any 7220's, only one VL */ 4035 qib_num_cfg_vls = 1; /* if any 7220's, only one VL */
4076 4036
@@ -4095,9 +4055,7 @@ static int qib_init_7220_variables(struct qib_devdata *dd)
4095 dd->rhdrhead_intr_off = 1ULL << 32; 4055 dd->rhdrhead_intr_off = 1ULL << 32;
4096 4056
4097 /* setup the stats timer; the add_timer is done at end of init */ 4057 /* setup the stats timer; the add_timer is done at end of init */
4098 init_timer(&dd->stats_timer); 4058 timer_setup(&dd->stats_timer, qib_get_7220_faststats, 0);
4099 dd->stats_timer.function = qib_get_7220_faststats;
4100 dd->stats_timer.data = (unsigned long) dd;
4101 dd->stats_timer.expires = jiffies + ACTIVITY_TIMER * HZ; 4059 dd->stats_timer.expires = jiffies + ACTIVITY_TIMER * HZ;
4102 4060
4103 /* 4061 /*
@@ -4535,7 +4493,7 @@ struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *pdev,
4535 dd->f_bringup_serdes = qib_7220_bringup_serdes; 4493 dd->f_bringup_serdes = qib_7220_bringup_serdes;
4536 dd->f_cleanup = qib_setup_7220_cleanup; 4494 dd->f_cleanup = qib_setup_7220_cleanup;
4537 dd->f_clear_tids = qib_7220_clear_tids; 4495 dd->f_clear_tids = qib_7220_clear_tids;
4538 dd->f_free_irq = qib_7220_free_irq; 4496 dd->f_free_irq = qib_free_irq;
4539 dd->f_get_base_info = qib_7220_get_base_info; 4497 dd->f_get_base_info = qib_7220_get_base_info;
4540 dd->f_get_msgheader = qib_7220_get_msgheader; 4498 dd->f_get_msgheader = qib_7220_get_msgheader;
4541 dd->f_getsendbuf = qib_7220_getsendbuf; 4499 dd->f_getsendbuf = qib_7220_getsendbuf;
@@ -4618,9 +4576,6 @@ struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *pdev,
4618 qib_dev_err(dd, 4576 qib_dev_err(dd,
4619 "Failed to setup PCIe or interrupts; continuing anyway\n"); 4577 "Failed to setup PCIe or interrupts; continuing anyway\n");
4620 4578
4621 /* save IRQ for possible later use */
4622 dd->cspec->irq = pdev->irq;
4623
4624 if (qib_read_kreg64(dd, kr_hwerrstatus) & 4579 if (qib_read_kreg64(dd, kr_hwerrstatus) &
4625 QLOGIC_IB_HWE_SERDESPLLFAILED) 4580 QLOGIC_IB_HWE_SERDESPLLFAILED)
4626 qib_write_kreg(dd, kr_hwerrclear, 4581 qib_write_kreg(dd, kr_hwerrclear,
diff --git a/drivers/infiniband/hw/qib/qib_iba7322.c b/drivers/infiniband/hw/qib/qib_iba7322.c
index a45e46098914..6265dac415fc 100644
--- a/drivers/infiniband/hw/qib/qib_iba7322.c
+++ b/drivers/infiniband/hw/qib/qib_iba7322.c
@@ -553,7 +553,6 @@ struct qib_chip_specific {
553 u32 updthresh; /* current AvailUpdThld */ 553 u32 updthresh; /* current AvailUpdThld */
554 u32 updthresh_dflt; /* default AvailUpdThld */ 554 u32 updthresh_dflt; /* default AvailUpdThld */
555 u32 r1; 555 u32 r1;
556 int irq;
557 u32 num_msix_entries; 556 u32 num_msix_entries;
558 u32 sdmabufcnt; 557 u32 sdmabufcnt;
559 u32 lastbuf_for_pio; 558 u32 lastbuf_for_pio;
@@ -756,10 +755,8 @@ static void check_7322_rxe_status(struct qib_pportdata *);
756static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *); 755static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
757#ifdef CONFIG_INFINIBAND_QIB_DCA 756#ifdef CONFIG_INFINIBAND_QIB_DCA
758static void qib_setup_dca(struct qib_devdata *dd); 757static void qib_setup_dca(struct qib_devdata *dd);
759static void setup_dca_notifier(struct qib_devdata *dd, 758static void setup_dca_notifier(struct qib_devdata *dd, int msixnum);
760 struct qib_msix_entry *m); 759static void reset_dca_notifier(struct qib_devdata *dd, int msixnum);
761static void reset_dca_notifier(struct qib_devdata *dd,
762 struct qib_msix_entry *m);
763#endif 760#endif
764 761
765/** 762/**
@@ -1647,7 +1644,6 @@ static noinline void handle_7322_errors(struct qib_devdata *dd)
1647 u64 iserr = 0; 1644 u64 iserr = 0;
1648 u64 errs; 1645 u64 errs;
1649 u64 mask; 1646 u64 mask;
1650 int log_idx;
1651 1647
1652 qib_stats.sps_errints++; 1648 qib_stats.sps_errints++;
1653 errs = qib_read_kreg64(dd, kr_errstatus); 1649 errs = qib_read_kreg64(dd, kr_errstatus);
@@ -1665,10 +1661,7 @@ static noinline void handle_7322_errors(struct qib_devdata *dd)
1665 if (errs & QIB_E_HARDWARE) { 1661 if (errs & QIB_E_HARDWARE) {
1666 *msg = '\0'; 1662 *msg = '\0';
1667 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); 1663 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1668 } else 1664 }
1669 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1670 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1671 qib_inc_eeprom_err(dd, log_idx, 1);
1672 1665
1673 if (errs & QIB_E_SPKTERRS) { 1666 if (errs & QIB_E_SPKTERRS) {
1674 qib_disarm_7322_senderrbufs(dd->pport); 1667 qib_disarm_7322_senderrbufs(dd->pport);
@@ -1739,9 +1732,10 @@ static void qib_error_tasklet(unsigned long data)
1739 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 1732 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1740} 1733}
1741 1734
1742static void reenable_chase(unsigned long opaque) 1735static void reenable_chase(struct timer_list *t)
1743{ 1736{
1744 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 1737 struct qib_chippport_specific *cp = from_timer(cp, t, chase_timer);
1738 struct qib_pportdata *ppd = cp->ppd;
1745 1739
1746 ppd->cpspec->chase_timer.expires = 0; 1740 ppd->cpspec->chase_timer.expires = 0;
1747 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, 1741 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
@@ -2531,7 +2525,7 @@ static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2531 cancel_delayed_work_sync(&ppd->cpspec->ipg_work); 2525 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2532 2526
2533 ppd->cpspec->chase_end = 0; 2527 ppd->cpspec->chase_end = 0;
2534 if (ppd->cpspec->chase_timer.data) /* if initted */ 2528 if (ppd->cpspec->chase_timer.function) /* if initted */
2535 del_timer_sync(&ppd->cpspec->chase_timer); 2529 del_timer_sync(&ppd->cpspec->chase_timer);
2536 2530
2537 /* 2531 /*
@@ -2778,7 +2772,7 @@ static void qib_setup_dca(struct qib_devdata *dd)
2778 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i, 2772 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i,
2779 cspec->dca_rcvhdr_ctrl[i]); 2773 cspec->dca_rcvhdr_ctrl[i]);
2780 for (i = 0; i < cspec->num_msix_entries; i++) 2774 for (i = 0; i < cspec->num_msix_entries; i++)
2781 setup_dca_notifier(dd, &cspec->msix_entries[i]); 2775 setup_dca_notifier(dd, i);
2782} 2776}
2783 2777
2784static void qib_irq_notifier_notify(struct irq_affinity_notify *notify, 2778static void qib_irq_notifier_notify(struct irq_affinity_notify *notify,
@@ -2820,49 +2814,41 @@ static void qib_irq_notifier_release(struct kref *ref)
2820} 2814}
2821#endif 2815#endif
2822 2816
2823/* 2817static void qib_7322_free_irq(struct qib_devdata *dd)
2824 * Disable MSIx interrupt if enabled, call generic MSIx code
2825 * to cleanup, and clear pending MSIx interrupts.
2826 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2827 */
2828static void qib_7322_nomsix(struct qib_devdata *dd)
2829{ 2818{
2830 u64 intgranted; 2819 u64 intgranted;
2831 int n; 2820 int i;
2832 2821
2833 dd->cspec->main_int_mask = ~0ULL; 2822 dd->cspec->main_int_mask = ~0ULL;
2834 n = dd->cspec->num_msix_entries;
2835 if (n) {
2836 int i;
2837 2823
2838 dd->cspec->num_msix_entries = 0; 2824 for (i = 0; i < dd->cspec->num_msix_entries; i++) {
2839 for (i = 0; i < n; i++) { 2825 /* only free IRQs that were allocated */
2826 if (dd->cspec->msix_entries[i].arg) {
2840#ifdef CONFIG_INFINIBAND_QIB_DCA 2827#ifdef CONFIG_INFINIBAND_QIB_DCA
2841 reset_dca_notifier(dd, &dd->cspec->msix_entries[i]); 2828 reset_dca_notifier(dd, i);
2842#endif 2829#endif
2843 irq_set_affinity_hint( 2830 irq_set_affinity_hint(pci_irq_vector(dd->pcidev, i),
2844 dd->cspec->msix_entries[i].irq, NULL); 2831 NULL);
2845 free_cpumask_var(dd->cspec->msix_entries[i].mask); 2832 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2846 free_irq(dd->cspec->msix_entries[i].irq, 2833 pci_free_irq(dd->pcidev, i,
2847 dd->cspec->msix_entries[i].arg); 2834 dd->cspec->msix_entries[i].arg);
2848 } 2835 }
2849 qib_nomsix(dd);
2850 } 2836 }
2837
2838 /* If num_msix_entries was 0, disable the INTx IRQ */
2839 if (!dd->cspec->num_msix_entries)
2840 pci_free_irq(dd->pcidev, 0, dd);
2841 else
2842 dd->cspec->num_msix_entries = 0;
2843
2844 pci_free_irq_vectors(dd->pcidev);
2845
2851 /* make sure no MSIx interrupts are left pending */ 2846 /* make sure no MSIx interrupts are left pending */
2852 intgranted = qib_read_kreg64(dd, kr_intgranted); 2847 intgranted = qib_read_kreg64(dd, kr_intgranted);
2853 if (intgranted) 2848 if (intgranted)
2854 qib_write_kreg(dd, kr_intgranted, intgranted); 2849 qib_write_kreg(dd, kr_intgranted, intgranted);
2855} 2850}
2856 2851
2857static void qib_7322_free_irq(struct qib_devdata *dd)
2858{
2859 if (dd->cspec->irq) {
2860 free_irq(dd->cspec->irq, dd);
2861 dd->cspec->irq = 0;
2862 }
2863 qib_7322_nomsix(dd);
2864}
2865
2866static void qib_setup_7322_cleanup(struct qib_devdata *dd) 2852static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2867{ 2853{
2868 int i; 2854 int i;
@@ -3329,22 +3315,20 @@ static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3329 3315
3330#ifdef CONFIG_INFINIBAND_QIB_DCA 3316#ifdef CONFIG_INFINIBAND_QIB_DCA
3331 3317
3332static void reset_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m) 3318static void reset_dca_notifier(struct qib_devdata *dd, int msixnum)
3333{ 3319{
3334 if (!m->dca) 3320 if (!dd->cspec->msix_entries[msixnum].dca)
3335 return; 3321 return;
3336 qib_devinfo(dd->pcidev, 3322
3337 "Disabling notifier on HCA %d irq %d\n", 3323 qib_devinfo(dd->pcidev, "Disabling notifier on HCA %d irq %d\n",
3338 dd->unit, 3324 dd->unit, pci_irq_vector(dd->pcidev, msixnum));
3339 m->irq); 3325 irq_set_affinity_notifier(pci_irq_vector(dd->pcidev, msixnum), NULL);
3340 irq_set_affinity_notifier( 3326 dd->cspec->msix_entries[msixnum].notifier = NULL;
3341 m->irq,
3342 NULL);
3343 m->notifier = NULL;
3344} 3327}
3345 3328
3346static void setup_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m) 3329static void setup_dca_notifier(struct qib_devdata *dd, int msixnum)
3347{ 3330{
3331 struct qib_msix_entry *m = &dd->cspec->msix_entries[msixnum];
3348 struct qib_irq_notify *n; 3332 struct qib_irq_notify *n;
3349 3333
3350 if (!m->dca) 3334 if (!m->dca)
@@ -3354,7 +3338,7 @@ static void setup_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3354 int ret; 3338 int ret;
3355 3339
3356 m->notifier = n; 3340 m->notifier = n;
3357 n->notify.irq = m->irq; 3341 n->notify.irq = pci_irq_vector(dd->pcidev, msixnum);
3358 n->notify.notify = qib_irq_notifier_notify; 3342 n->notify.notify = qib_irq_notifier_notify;
3359 n->notify.release = qib_irq_notifier_release; 3343 n->notify.release = qib_irq_notifier_release;
3360 n->arg = m->arg; 3344 n->arg = m->arg;
@@ -3415,22 +3399,17 @@ static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3415 if (!dd->cspec->num_msix_entries) { 3399 if (!dd->cspec->num_msix_entries) {
3416 /* Try to get INTx interrupt */ 3400 /* Try to get INTx interrupt */
3417try_intx: 3401try_intx:
3418 if (!dd->pcidev->irq) { 3402 ret = pci_request_irq(dd->pcidev, 0, qib_7322intr, NULL, dd,
3419 qib_dev_err(dd, 3403 QIB_DRV_NAME);
3420 "irq is 0, BIOS error? Interrupts won't work\n");
3421 goto bail;
3422 }
3423 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3424 IRQF_SHARED, QIB_DRV_NAME, dd);
3425 if (ret) { 3404 if (ret) {
3426 qib_dev_err(dd, 3405 qib_dev_err(
3406 dd,
3427 "Couldn't setup INTx interrupt (irq=%d): %d\n", 3407 "Couldn't setup INTx interrupt (irq=%d): %d\n",
3428 dd->pcidev->irq, ret); 3408 pci_irq_vector(dd->pcidev, 0), ret);
3429 goto bail; 3409 return;
3430 } 3410 }
3431 dd->cspec->irq = dd->pcidev->irq;
3432 dd->cspec->main_int_mask = ~0ULL; 3411 dd->cspec->main_int_mask = ~0ULL;
3433 goto bail; 3412 return;
3434 } 3413 }
3435 3414
3436 /* Try to get MSIx interrupts */ 3415 /* Try to get MSIx interrupts */
@@ -3453,15 +3432,10 @@ try_intx:
3453 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { 3432 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3454 irq_handler_t handler; 3433 irq_handler_t handler;
3455 void *arg; 3434 void *arg;
3456 u64 val;
3457 int lsb, reg, sh; 3435 int lsb, reg, sh;
3458#ifdef CONFIG_INFINIBAND_QIB_DCA 3436#ifdef CONFIG_INFINIBAND_QIB_DCA
3459 int dca = 0; 3437 int dca = 0;
3460#endif 3438#endif
3461
3462 dd->cspec->msix_entries[msixnum].
3463 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1]
3464 = '\0';
3465 if (i < ARRAY_SIZE(irq_table)) { 3439 if (i < ARRAY_SIZE(irq_table)) {
3466 if (irq_table[i].port) { 3440 if (irq_table[i].port) {
3467 /* skip if for a non-configured port */ 3441 /* skip if for a non-configured port */
@@ -3475,11 +3449,10 @@ try_intx:
3475#endif 3449#endif
3476 lsb = irq_table[i].lsb; 3450 lsb = irq_table[i].lsb;
3477 handler = irq_table[i].handler; 3451 handler = irq_table[i].handler;
3478 snprintf(dd->cspec->msix_entries[msixnum].name, 3452 ret = pci_request_irq(dd->pcidev, msixnum, handler,
3479 sizeof(dd->cspec->msix_entries[msixnum].name) 3453 NULL, arg, QIB_DRV_NAME "%d%s",
3480 - 1, 3454 dd->unit,
3481 QIB_DRV_NAME "%d%s", dd->unit, 3455 irq_table[i].name);
3482 irq_table[i].name);
3483 } else { 3456 } else {
3484 unsigned ctxt; 3457 unsigned ctxt;
3485 3458
@@ -3495,37 +3468,25 @@ try_intx:
3495#endif 3468#endif
3496 lsb = QIB_I_RCVAVAIL_LSB + ctxt; 3469 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3497 handler = qib_7322pintr; 3470 handler = qib_7322pintr;
3498 snprintf(dd->cspec->msix_entries[msixnum].name, 3471 ret = pci_request_irq(dd->pcidev, msixnum, handler,
3499 sizeof(dd->cspec->msix_entries[msixnum].name) 3472 NULL, arg,
3500 - 1, 3473 QIB_DRV_NAME "%d (kctx)",
3501 QIB_DRV_NAME "%d (kctx)", dd->unit); 3474 dd->unit);
3502 } 3475 }
3503 3476
3504 dd->cspec->msix_entries[msixnum].irq = pci_irq_vector(
3505 dd->pcidev, msixnum);
3506 if (dd->cspec->msix_entries[msixnum].irq < 0) {
3507 qib_dev_err(dd,
3508 "Couldn't get MSIx irq (vec=%d): %d\n",
3509 msixnum,
3510 dd->cspec->msix_entries[msixnum].irq);
3511 qib_7322_nomsix(dd);
3512 goto try_intx;
3513 }
3514 ret = request_irq(dd->cspec->msix_entries[msixnum].irq,
3515 handler, 0,
3516 dd->cspec->msix_entries[msixnum].name,
3517 arg);
3518 if (ret) { 3477 if (ret) {
3519 /* 3478 /*
3520 * Shouldn't happen since the enable said we could 3479 * Shouldn't happen since the enable said we could
3521 * have as many as we are trying to setup here. 3480 * have as many as we are trying to setup here.
3522 */ 3481 */
3523 qib_dev_err(dd, 3482 qib_dev_err(dd,
3524 "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n", 3483 "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n",
3525 msixnum, 3484 msixnum,
3526 dd->cspec->msix_entries[msixnum].irq, 3485 pci_irq_vector(dd->pcidev, msixnum),
3527 ret); 3486 ret);
3528 qib_7322_nomsix(dd); 3487 qib_7322_free_irq(dd);
3488 pci_alloc_irq_vectors(dd->pcidev, 1, 1,
3489 PCI_IRQ_LEGACY);
3529 goto try_intx; 3490 goto try_intx;
3530 } 3491 }
3531 dd->cspec->msix_entries[msixnum].arg = arg; 3492 dd->cspec->msix_entries[msixnum].arg = arg;
@@ -3541,8 +3502,8 @@ try_intx:
3541 mask &= ~(1ULL << lsb); 3502 mask &= ~(1ULL << lsb);
3542 redirect[reg] |= ((u64) msixnum) << sh; 3503 redirect[reg] |= ((u64) msixnum) << sh;
3543 } 3504 }
3544 val = qib_read_kreg64(dd, 2 * msixnum + 1 + 3505 qib_read_kreg64(dd, 2 * msixnum + 1 +
3545 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3506 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3546 if (firstcpu < nr_cpu_ids && 3507 if (firstcpu < nr_cpu_ids &&
3547 zalloc_cpumask_var( 3508 zalloc_cpumask_var(
3548 &dd->cspec->msix_entries[msixnum].mask, 3509 &dd->cspec->msix_entries[msixnum].mask,
@@ -3559,7 +3520,7 @@ try_intx:
3559 dd->cspec->msix_entries[msixnum].mask); 3520 dd->cspec->msix_entries[msixnum].mask);
3560 } 3521 }
3561 irq_set_affinity_hint( 3522 irq_set_affinity_hint(
3562 dd->cspec->msix_entries[msixnum].irq, 3523 pci_irq_vector(dd->pcidev, msixnum),
3563 dd->cspec->msix_entries[msixnum].mask); 3524 dd->cspec->msix_entries[msixnum].mask);
3564 } 3525 }
3565 msixnum++; 3526 msixnum++;
@@ -3570,7 +3531,6 @@ try_intx:
3570 dd->cspec->main_int_mask = mask; 3531 dd->cspec->main_int_mask = mask;
3571 tasklet_init(&dd->error_tasklet, qib_error_tasklet, 3532 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3572 (unsigned long)dd); 3533 (unsigned long)dd);
3573bail:;
3574} 3534}
3575 3535
3576/** 3536/**
@@ -3674,8 +3634,9 @@ static int qib_do_7322_reset(struct qib_devdata *dd)
3674 /* no interrupts till re-initted */ 3634 /* no interrupts till re-initted */
3675 qib_7322_set_intr_state(dd, 0); 3635 qib_7322_set_intr_state(dd, 0);
3676 3636
3637 qib_7322_free_irq(dd);
3638
3677 if (msix_entries) { 3639 if (msix_entries) {
3678 qib_7322_nomsix(dd);
3679 /* can be up to 512 bytes, too big for stack */ 3640 /* can be up to 512 bytes, too big for stack */
3680 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries * 3641 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3681 sizeof(u64), GFP_KERNEL); 3642 sizeof(u64), GFP_KERNEL);
@@ -3765,11 +3726,11 @@ static int qib_do_7322_reset(struct qib_devdata *dd)
3765 write_7322_init_portregs(&dd->pport[i]); 3726 write_7322_init_portregs(&dd->pport[i]);
3766 write_7322_initregs(dd); 3727 write_7322_initregs(dd);
3767 3728
3768 if (qib_pcie_params(dd, dd->lbus_width, 3729 if (qib_pcie_params(dd, dd->lbus_width, &msix_entries))
3769 &dd->cspec->num_msix_entries))
3770 qib_dev_err(dd, 3730 qib_dev_err(dd,
3771 "Reset failed to setup PCIe or interrupts; continuing anyway\n"); 3731 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
3772 3732
3733 dd->cspec->num_msix_entries = msix_entries;
3773 qib_setup_7322_interrupt(dd, 1); 3734 qib_setup_7322_interrupt(dd, 1);
3774 3735
3775 for (i = 0; i < dd->num_pports; ++i) { 3736 for (i = 0; i < dd->num_pports; ++i) {
@@ -5138,9 +5099,9 @@ done:
5138 * 5099 *
5139 * called from add_timer 5100 * called from add_timer
5140 */ 5101 */
5141static void qib_get_7322_faststats(unsigned long opaque) 5102static void qib_get_7322_faststats(struct timer_list *t)
5142{ 5103{
5143 struct qib_devdata *dd = (struct qib_devdata *) opaque; 5104 struct qib_devdata *dd = from_timer(dd, t, stats_timer);
5144 struct qib_pportdata *ppd; 5105 struct qib_pportdata *ppd;
5145 unsigned long flags; 5106 unsigned long flags;
5146 u64 traffic_wds; 5107 u64 traffic_wds;
@@ -5197,8 +5158,9 @@ static int qib_7322_intr_fallback(struct qib_devdata *dd)
5197 5158
5198 qib_devinfo(dd->pcidev, 5159 qib_devinfo(dd->pcidev,
5199 "MSIx interrupt not detected, trying INTx interrupts\n"); 5160 "MSIx interrupt not detected, trying INTx interrupts\n");
5200 qib_7322_nomsix(dd); 5161 qib_7322_free_irq(dd);
5201 qib_enable_intx(dd); 5162 if (pci_alloc_irq_vectors(dd->pcidev, 1, 1, PCI_IRQ_LEGACY) < 0)
5163 qib_dev_err(dd, "Failed to enable INTx\n");
5202 qib_setup_7322_interrupt(dd, 0); 5164 qib_setup_7322_interrupt(dd, 0);
5203 return 1; 5165 return 1;
5204} 5166}
@@ -5396,16 +5358,11 @@ static void try_7322_autoneg(struct qib_pportdata *ppd)
5396static void autoneg_7322_work(struct work_struct *work) 5358static void autoneg_7322_work(struct work_struct *work)
5397{ 5359{
5398 struct qib_pportdata *ppd; 5360 struct qib_pportdata *ppd;
5399 struct qib_devdata *dd;
5400 u64 startms;
5401 u32 i; 5361 u32 i;
5402 unsigned long flags; 5362 unsigned long flags;
5403 5363
5404 ppd = container_of(work, struct qib_chippport_specific, 5364 ppd = container_of(work, struct qib_chippport_specific,
5405 autoneg_work.work)->ppd; 5365 autoneg_work.work)->ppd;
5406 dd = ppd->dd;
5407
5408 startms = jiffies_to_msecs(jiffies);
5409 5366
5410 /* 5367 /*
5411 * Busy wait for this first part, it should be at most a 5368 * Busy wait for this first part, it should be at most a
@@ -6614,8 +6571,7 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
6614 if (!qib_mini_init) 6571 if (!qib_mini_init)
6615 write_7322_init_portregs(ppd); 6572 write_7322_init_portregs(ppd);
6616 6573
6617 setup_timer(&cp->chase_timer, reenable_chase, 6574 timer_setup(&cp->chase_timer, reenable_chase, 0);
6618 (unsigned long)ppd);
6619 6575
6620 ppd++; 6576 ppd++;
6621 } 6577 }
@@ -6641,8 +6597,7 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
6641 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT; 6597 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6642 6598
6643 /* setup the stats timer; the add_timer is done at end of init */ 6599 /* setup the stats timer; the add_timer is done at end of init */
6644 setup_timer(&dd->stats_timer, qib_get_7322_faststats, 6600 timer_setup(&dd->stats_timer, qib_get_7322_faststats, 0);
6645 (unsigned long)dd);
6646 6601
6647 dd->ureg_align = 0x10000; /* 64KB alignment */ 6602 dd->ureg_align = 0x10000; /* 64KB alignment */
6648 6603
@@ -7845,13 +7800,12 @@ static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7845{ 7800{
7846 struct qib_devdata *dd = ppd->dd; 7801 struct qib_devdata *dd = ppd->dd;
7847 int chan; 7802 int chan;
7848 u32 rbc;
7849 7803
7850 for (chan = 0; chan < SERDES_CHANS; ++chan) { 7804 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7851 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, 7805 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7852 data, mask); 7806 data, mask);
7853 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7807 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7854 addr, 0, 0); 7808 0, 0);
7855 } 7809 }
7856} 7810}
7857 7811
diff --git a/drivers/infiniband/hw/qib/qib_init.c b/drivers/infiniband/hw/qib/qib_init.c
index c5a4c65636d6..5243ad30dfc0 100644
--- a/drivers/infiniband/hw/qib/qib_init.c
+++ b/drivers/infiniband/hw/qib/qib_init.c
@@ -93,7 +93,7 @@ unsigned qib_cc_table_size;
93module_param_named(cc_table_size, qib_cc_table_size, uint, S_IRUGO); 93module_param_named(cc_table_size, qib_cc_table_size, uint, S_IRUGO);
94MODULE_PARM_DESC(cc_table_size, "Congestion control table entries 0 (CCA disabled - default), min = 128, max = 1984"); 94MODULE_PARM_DESC(cc_table_size, "Congestion control table entries 0 (CCA disabled - default), min = 128, max = 1984");
95 95
96static void verify_interrupt(unsigned long); 96static void verify_interrupt(struct timer_list *);
97 97
98static struct idr qib_unit_table; 98static struct idr qib_unit_table;
99u32 qib_cpulist_count; 99u32 qib_cpulist_count;
@@ -233,8 +233,7 @@ int qib_init_pportdata(struct qib_pportdata *ppd, struct qib_devdata *dd,
233 spin_lock_init(&ppd->cc_shadow_lock); 233 spin_lock_init(&ppd->cc_shadow_lock);
234 init_waitqueue_head(&ppd->state_wait); 234 init_waitqueue_head(&ppd->state_wait);
235 235
236 setup_timer(&ppd->symerr_clear_timer, qib_clear_symerror_on_linkup, 236 timer_setup(&ppd->symerr_clear_timer, qib_clear_symerror_on_linkup, 0);
237 (unsigned long)ppd);
238 237
239 ppd->qib_wq = NULL; 238 ppd->qib_wq = NULL;
240 ppd->ibport_data.pmastats = 239 ppd->ibport_data.pmastats =
@@ -428,8 +427,7 @@ static int loadtime_init(struct qib_devdata *dd)
428 qib_get_eeprom_info(dd); 427 qib_get_eeprom_info(dd);
429 428
430 /* setup time (don't start yet) to verify we got interrupt */ 429 /* setup time (don't start yet) to verify we got interrupt */
431 setup_timer(&dd->intrchk_timer, verify_interrupt, 430 timer_setup(&dd->intrchk_timer, verify_interrupt, 0);
432 (unsigned long)dd);
433done: 431done:
434 return ret; 432 return ret;
435} 433}
@@ -493,9 +491,9 @@ static void enable_chip(struct qib_devdata *dd)
493 } 491 }
494} 492}
495 493
496static void verify_interrupt(unsigned long opaque) 494static void verify_interrupt(struct timer_list *t)
497{ 495{
498 struct qib_devdata *dd = (struct qib_devdata *) opaque; 496 struct qib_devdata *dd = from_timer(dd, t, intrchk_timer);
499 u64 int_counter; 497 u64 int_counter;
500 498
501 if (!dd) 499 if (!dd)
@@ -753,8 +751,7 @@ done:
753 continue; 751 continue;
754 if (dd->flags & QIB_HAS_SEND_DMA) 752 if (dd->flags & QIB_HAS_SEND_DMA)
755 ret = qib_setup_sdma(ppd); 753 ret = qib_setup_sdma(ppd);
756 setup_timer(&ppd->hol_timer, qib_hol_event, 754 timer_setup(&ppd->hol_timer, qib_hol_event, 0);
757 (unsigned long)ppd);
758 ppd->hol_state = QIB_HOL_UP; 755 ppd->hol_state = QIB_HOL_UP;
759 } 756 }
760 757
@@ -815,23 +812,19 @@ static void qib_stop_timers(struct qib_devdata *dd)
815 struct qib_pportdata *ppd; 812 struct qib_pportdata *ppd;
816 int pidx; 813 int pidx;
817 814
818 if (dd->stats_timer.data) { 815 if (dd->stats_timer.function)
819 del_timer_sync(&dd->stats_timer); 816 del_timer_sync(&dd->stats_timer);
820 dd->stats_timer.data = 0; 817 if (dd->intrchk_timer.function)
821 }
822 if (dd->intrchk_timer.data) {
823 del_timer_sync(&dd->intrchk_timer); 818 del_timer_sync(&dd->intrchk_timer);
824 dd->intrchk_timer.data = 0;
825 }
826 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 819 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
827 ppd = dd->pport + pidx; 820 ppd = dd->pport + pidx;
828 if (ppd->hol_timer.data) 821 if (ppd->hol_timer.function)
829 del_timer_sync(&ppd->hol_timer); 822 del_timer_sync(&ppd->hol_timer);
830 if (ppd->led_override_timer.data) { 823 if (ppd->led_override_timer.function) {
831 del_timer_sync(&ppd->led_override_timer); 824 del_timer_sync(&ppd->led_override_timer);
832 atomic_set(&ppd->led_override_timer_active, 0); 825 atomic_set(&ppd->led_override_timer_active, 0);
833 } 826 }
834 if (ppd->symerr_clear_timer.data) 827 if (ppd->symerr_clear_timer.function)
835 del_timer_sync(&ppd->symerr_clear_timer); 828 del_timer_sync(&ppd->symerr_clear_timer);
836 } 829 }
837} 830}
diff --git a/drivers/infiniband/hw/qib/qib_intr.c b/drivers/infiniband/hw/qib/qib_intr.c
index a014fd4cd076..65c3b964ad1b 100644
--- a/drivers/infiniband/hw/qib/qib_intr.c
+++ b/drivers/infiniband/hw/qib/qib_intr.c
@@ -141,7 +141,7 @@ void qib_handle_e_ibstatuschanged(struct qib_pportdata *ppd, u64 ibcs)
141 qib_hol_up(ppd); /* useful only for 6120 now */ 141 qib_hol_up(ppd); /* useful only for 6120 now */
142 *ppd->statusp |= 142 *ppd->statusp |=
143 QIB_STATUS_IB_READY | QIB_STATUS_IB_CONF; 143 QIB_STATUS_IB_READY | QIB_STATUS_IB_CONF;
144 qib_clear_symerror_on_linkup((unsigned long)ppd); 144 qib_clear_symerror_on_linkup(&ppd->symerr_clear_timer);
145 spin_lock_irqsave(&ppd->lflags_lock, flags); 145 spin_lock_irqsave(&ppd->lflags_lock, flags);
146 ppd->lflags |= QIBL_LINKACTIVE | QIBL_LINKV; 146 ppd->lflags |= QIBL_LINKACTIVE | QIBL_LINKV;
147 ppd->lflags &= ~(QIBL_LINKINIT | 147 ppd->lflags &= ~(QIBL_LINKINIT |
@@ -170,9 +170,9 @@ skip_ibchange:
170 signal_ib_event(ppd, ev); 170 signal_ib_event(ppd, ev);
171} 171}
172 172
173void qib_clear_symerror_on_linkup(unsigned long opaque) 173void qib_clear_symerror_on_linkup(struct timer_list *t)
174{ 174{
175 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 175 struct qib_pportdata *ppd = from_timer(ppd, t, symerr_clear_timer);
176 176
177 if (ppd->lflags & QIBL_LINKACTIVE) 177 if (ppd->lflags & QIBL_LINKACTIVE)
178 return; 178 return;
diff --git a/drivers/infiniband/hw/qib/qib_mad.c b/drivers/infiniband/hw/qib/qib_mad.c
index 82d9da9b6997..4845d000c22f 100644
--- a/drivers/infiniband/hw/qib/qib_mad.c
+++ b/drivers/infiniband/hw/qib/qib_mad.c
@@ -280,7 +280,7 @@ static int subn_get_nodeinfo(struct ib_smp *smp, struct ib_device *ibdev,
280{ 280{
281 struct ib_node_info *nip = (struct ib_node_info *)&smp->data; 281 struct ib_node_info *nip = (struct ib_node_info *)&smp->data;
282 struct qib_devdata *dd = dd_from_ibdev(ibdev); 282 struct qib_devdata *dd = dd_from_ibdev(ibdev);
283 u32 vendor, majrev, minrev; 283 u32 majrev, minrev;
284 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 284 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
285 285
286 /* GUID 0 is illegal */ 286 /* GUID 0 is illegal */
@@ -303,7 +303,6 @@ static int subn_get_nodeinfo(struct ib_smp *smp, struct ib_device *ibdev,
303 minrev = dd->minrev; 303 minrev = dd->minrev;
304 nip->revision = cpu_to_be32((majrev << 16) | minrev); 304 nip->revision = cpu_to_be32((majrev << 16) | minrev);
305 nip->local_port_num = port; 305 nip->local_port_num = port;
306 vendor = dd->vendorid;
307 nip->vendor_id[0] = QIB_SRC_OUI_1; 306 nip->vendor_id[0] = QIB_SRC_OUI_1;
308 nip->vendor_id[1] = QIB_SRC_OUI_2; 307 nip->vendor_id[1] = QIB_SRC_OUI_2;
309 nip->vendor_id[2] = QIB_SRC_OUI_3; 308 nip->vendor_id[2] = QIB_SRC_OUI_3;
@@ -434,6 +433,7 @@ static int check_mkey(struct qib_ibport *ibp, struct ib_smp *smp, int mad_flags)
434 /* Bad mkey not a violation below level 2 */ 433 /* Bad mkey not a violation below level 2 */
435 if (ibp->rvp.mkeyprot < 2) 434 if (ibp->rvp.mkeyprot < 2)
436 break; 435 break;
436 /* fall through */
437 case IB_MGMT_METHOD_SET: 437 case IB_MGMT_METHOD_SET:
438 case IB_MGMT_METHOD_TRAP_REPRESS: 438 case IB_MGMT_METHOD_TRAP_REPRESS:
439 if (ibp->rvp.mkey_violations != 0xFFFF) 439 if (ibp->rvp.mkey_violations != 0xFFFF)
@@ -2446,9 +2446,9 @@ bail:
2446 return ret; 2446 return ret;
2447} 2447}
2448 2448
2449static void xmit_wait_timer_func(unsigned long opaque) 2449static void xmit_wait_timer_func(struct timer_list *t)
2450{ 2450{
2451 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 2451 struct qib_pportdata *ppd = from_timer(ppd, t, cong_stats.timer);
2452 struct qib_devdata *dd = dd_from_ppd(ppd); 2452 struct qib_devdata *dd = dd_from_ppd(ppd);
2453 unsigned long flags; 2453 unsigned long flags;
2454 u8 status; 2454 u8 status;
@@ -2478,10 +2478,8 @@ void qib_notify_create_mad_agent(struct rvt_dev_info *rdi, int port_idx)
2478 2478
2479 /* Initialize xmit_wait structure */ 2479 /* Initialize xmit_wait structure */
2480 dd->pport[port_idx].cong_stats.counter = 0; 2480 dd->pport[port_idx].cong_stats.counter = 0;
2481 init_timer(&dd->pport[port_idx].cong_stats.timer); 2481 timer_setup(&dd->pport[port_idx].cong_stats.timer,
2482 dd->pport[port_idx].cong_stats.timer.function = xmit_wait_timer_func; 2482 xmit_wait_timer_func, 0);
2483 dd->pport[port_idx].cong_stats.timer.data =
2484 (unsigned long)(&dd->pport[port_idx]);
2485 dd->pport[port_idx].cong_stats.timer.expires = 0; 2483 dd->pport[port_idx].cong_stats.timer.expires = 0;
2486 add_timer(&dd->pport[port_idx].cong_stats.timer); 2484 add_timer(&dd->pport[port_idx].cong_stats.timer);
2487} 2485}
@@ -2492,7 +2490,7 @@ void qib_notify_free_mad_agent(struct rvt_dev_info *rdi, int port_idx)
2492 struct qib_devdata *dd = container_of(ibdev, 2490 struct qib_devdata *dd = container_of(ibdev,
2493 struct qib_devdata, verbs_dev); 2491 struct qib_devdata, verbs_dev);
2494 2492
2495 if (dd->pport[port_idx].cong_stats.timer.data) 2493 if (dd->pport[port_idx].cong_stats.timer.function)
2496 del_timer_sync(&dd->pport[port_idx].cong_stats.timer); 2494 del_timer_sync(&dd->pport[port_idx].cong_stats.timer);
2497 2495
2498 if (dd->pport[port_idx].ibport_data.smi_ah) 2496 if (dd->pport[port_idx].ibport_data.smi_ah)
diff --git a/drivers/infiniband/hw/qib/qib_pcie.c b/drivers/infiniband/hw/qib/qib_pcie.c
index d90403e31a9d..5ac7b31c346b 100644
--- a/drivers/infiniband/hw/qib/qib_pcie.c
+++ b/drivers/infiniband/hw/qib/qib_pcie.c
@@ -193,7 +193,7 @@ void qib_pcie_ddcleanup(struct qib_devdata *dd)
193 * chip reset (the kernel PCI infrastructure doesn't yet handle that 193 * chip reset (the kernel PCI infrastructure doesn't yet handle that
194 * correctly. 194 * correctly.
195 */ 195 */
196static void qib_msi_setup(struct qib_devdata *dd, int pos) 196static void qib_cache_msi_info(struct qib_devdata *dd, int pos)
197{ 197{
198 struct pci_dev *pdev = dd->pcidev; 198 struct pci_dev *pdev = dd->pcidev;
199 u16 control; 199 u16 control;
@@ -208,64 +208,39 @@ static void qib_msi_setup(struct qib_devdata *dd, int pos)
208 &dd->msi_data); 208 &dd->msi_data);
209} 209}
210 210
211static int qib_allocate_irqs(struct qib_devdata *dd, u32 maxvec)
212{
213 unsigned int flags = PCI_IRQ_LEGACY;
214
215 /* Check our capabilities */
216 if (dd->pcidev->msix_cap) {
217 flags |= PCI_IRQ_MSIX;
218 } else {
219 if (dd->pcidev->msi_cap) {
220 flags |= PCI_IRQ_MSI;
221 /* Get msi_lo and msi_hi */
222 qib_msi_setup(dd, dd->pcidev->msi_cap);
223 }
224 }
225
226 if (!(flags & (PCI_IRQ_MSIX | PCI_IRQ_MSI)))
227 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n");
228
229 return pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags);
230}
231
232int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent) 211int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent)
233{ 212{
234 u16 linkstat, speed; 213 u16 linkstat, speed;
235 int nvec; 214 int nvec;
236 int maxvec; 215 int maxvec;
237 int ret = 0; 216 unsigned int flags = PCI_IRQ_MSIX | PCI_IRQ_MSI;
238 217
239 if (!pci_is_pcie(dd->pcidev)) { 218 if (!pci_is_pcie(dd->pcidev)) {
240 qib_dev_err(dd, "Can't find PCI Express capability!\n"); 219 qib_dev_err(dd, "Can't find PCI Express capability!\n");
241 /* set up something... */ 220 /* set up something... */
242 dd->lbus_width = 1; 221 dd->lbus_width = 1;
243 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 222 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
244 ret = -1; 223 nvec = -1;
245 goto bail; 224 goto bail;
246 } 225 }
247 226
227 if (dd->flags & QIB_HAS_INTX)
228 flags |= PCI_IRQ_LEGACY;
248 maxvec = (nent && *nent) ? *nent : 1; 229 maxvec = (nent && *nent) ? *nent : 1;
249 nvec = qib_allocate_irqs(dd, maxvec); 230 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags);
250 if (nvec < 0) { 231 if (nvec < 0)
251 ret = nvec;
252 goto bail; 232 goto bail;
253 }
254 233
255 /* 234 /*
256 * If nent exists, make sure to record how many vectors were allocated 235 * If nent exists, make sure to record how many vectors were allocated.
236 * If msix_enabled is false, return 0 so the fallback code works
237 * correctly.
257 */ 238 */
258 if (nent) { 239 if (nent)
259 *nent = nvec; 240 *nent = !dd->pcidev->msix_enabled ? 0 : nvec;
260 241
261 /* 242 if (dd->pcidev->msi_enabled)
262 * If we requested (nent) MSIX, but msix_enabled is not set, 243 qib_cache_msi_info(dd, dd->pcidev->msi_cap);
263 * pci_alloc_irq_vectors() enabled INTx.
264 */
265 if (!dd->pcidev->msix_enabled)
266 qib_dev_err(dd,
267 "no msix vectors allocated, using INTx\n");
268 }
269 244
270 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 245 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
271 /* 246 /*
@@ -306,7 +281,21 @@ bail:
306 /* fill in string, even on errors */ 281 /* fill in string, even on errors */
307 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 282 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
308 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width); 283 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
309 return ret; 284 return nvec < 0 ? nvec : 0;
285}
286
287/**
288 * qib_free_irq - Cleanup INTx and MSI interrupts
289 * @dd: valid pointer to qib dev data
290 *
291 * Since cleanup for INTx and MSI interrupts is trivial, have a common
292 * routine.
293 *
294 */
295void qib_free_irq(struct qib_devdata *dd)
296{
297 pci_free_irq(dd->pcidev, 0, dd);
298 pci_free_irq_vectors(dd->pcidev);
310} 299}
311 300
312/* 301/*
@@ -351,10 +340,10 @@ int qib_reinit_intr(struct qib_devdata *dd)
351 dd->msi_data); 340 dd->msi_data);
352 ret = 1; 341 ret = 1;
353bail: 342bail:
354 if (!ret && (dd->flags & QIB_HAS_INTX)) { 343 qib_free_irq(dd);
355 qib_enable_intx(dd); 344
345 if (!ret && (dd->flags & QIB_HAS_INTX))
356 ret = 1; 346 ret = 1;
357 }
358 347
359 /* and now set the pci master bit again */ 348 /* and now set the pci master bit again */
360 pci_set_master(dd->pcidev); 349 pci_set_master(dd->pcidev);
@@ -363,56 +352,6 @@ bail:
363} 352}
364 353
365/* 354/*
366 * Disable msi interrupt if enabled, and clear msi_lo.
367 * This is used primarily for the fallback to INTx, but
368 * is also used in reinit after reset, and during cleanup.
369 */
370void qib_nomsi(struct qib_devdata *dd)
371{
372 dd->msi_lo = 0;
373 pci_free_irq_vectors(dd->pcidev);
374}
375
376/*
377 * Same as qib_nosmi, but for MSIx.
378 */
379void qib_nomsix(struct qib_devdata *dd)
380{
381 pci_free_irq_vectors(dd->pcidev);
382}
383
384/*
385 * Similar to pci_intx(pdev, 1), except that we make sure
386 * msi(x) is off.
387 */
388void qib_enable_intx(struct qib_devdata *dd)
389{
390 u16 cw, new;
391 int pos;
392 struct pci_dev *pdev = dd->pcidev;
393
394 if (pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY) < 0)
395 qib_dev_err(dd, "Failed to enable INTx\n");
396
397 pos = pdev->msi_cap;
398 if (pos) {
399 /* then turn off MSI */
400 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
401 new = cw & ~PCI_MSI_FLAGS_ENABLE;
402 if (new != cw)
403 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
404 }
405 pos = pdev->msix_cap;
406 if (pos) {
407 /* then turn off MSIx */
408 pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw);
409 new = cw & ~PCI_MSIX_FLAGS_ENABLE;
410 if (new != cw)
411 pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new);
412 }
413}
414
415/*
416 * These two routines are helper routines for the device reset code 355 * These two routines are helper routines for the device reset code
417 * to move all the pcie code out of the chip-specific driver code. 356 * to move all the pcie code out of the chip-specific driver code.
418 */ 357 */
@@ -458,7 +397,6 @@ MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets");
458 */ 397 */
459static void qib_tune_pcie_coalesce(struct qib_devdata *dd) 398static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
460{ 399{
461 int r;
462 struct pci_dev *parent; 400 struct pci_dev *parent;
463 u16 devid; 401 u16 devid;
464 u32 mask, bits, val; 402 u32 mask, bits, val;
@@ -513,7 +451,7 @@ static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
513 pci_read_config_dword(parent, 0x48, &val); 451 pci_read_config_dword(parent, 0x48, &val);
514 val &= ~mask; 452 val &= ~mask;
515 val |= bits; 453 val |= bits;
516 r = pci_write_config_dword(parent, 0x48, val); 454 pci_write_config_dword(parent, 0x48, val);
517} 455}
518 456
519/* 457/*
diff --git a/drivers/infiniband/hw/qib/qib_rc.c b/drivers/infiniband/hw/qib/qib_rc.c
index e9a91736b12d..8f5754fb8579 100644
--- a/drivers/infiniband/hw/qib/qib_rc.c
+++ b/drivers/infiniband/hw/qib/qib_rc.c
@@ -1869,7 +1869,7 @@ send_middle:
1869 qp->r_rcv_len = 0; 1869 qp->r_rcv_len = 0;
1870 if (opcode == OP(SEND_ONLY)) 1870 if (opcode == OP(SEND_ONLY))
1871 goto no_immediate_data; 1871 goto no_immediate_data;
1872 /* FALLTHROUGH for SEND_ONLY_WITH_IMMEDIATE */ 1872 /* fall through -- for SEND_ONLY_WITH_IMMEDIATE */
1873 case OP(SEND_LAST_WITH_IMMEDIATE): 1873 case OP(SEND_LAST_WITH_IMMEDIATE):
1874send_last_imm: 1874send_last_imm:
1875 wc.ex.imm_data = ohdr->u.imm_data; 1875 wc.ex.imm_data = ohdr->u.imm_data;
diff --git a/drivers/infiniband/hw/qib/qib_sd7220.c b/drivers/infiniband/hw/qib/qib_sd7220.c
index c72775f27212..12caf3db8c34 100644
--- a/drivers/infiniband/hw/qib/qib_sd7220.c
+++ b/drivers/infiniband/hw/qib/qib_sd7220.c
@@ -755,7 +755,6 @@ static int qib_sd7220_ram_xfer(struct qib_devdata *dd, int sdnum, u32 loc,
755 int addr; 755 int addr;
756 int ret; 756 int ret;
757 unsigned long flags; 757 unsigned long flags;
758 const char *op;
759 758
760 /* Pick appropriate transaction reg and "Chip select" for this serdes */ 759 /* Pick appropriate transaction reg and "Chip select" for this serdes */
761 switch (sdnum) { 760 switch (sdnum) {
@@ -775,7 +774,6 @@ static int qib_sd7220_ram_xfer(struct qib_devdata *dd, int sdnum, u32 loc,
775 return -1; 774 return -1;
776 } 775 }
777 776
778 op = rd_notwr ? "Rd" : "Wr";
779 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags); 777 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
780 778
781 owned = epb_access(dd, sdnum, 1); 779 owned = epb_access(dd, sdnum, 1);
@@ -1390,11 +1388,11 @@ module_param_named(relock_by_timer, qib_relock_by_timer, uint,
1390 S_IWUSR | S_IRUGO); 1388 S_IWUSR | S_IRUGO);
1391MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up"); 1389MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up");
1392 1390
1393static void qib_run_relock(unsigned long opaque) 1391static void qib_run_relock(struct timer_list *t)
1394{ 1392{
1395 struct qib_devdata *dd = (struct qib_devdata *)opaque; 1393 struct qib_chip_specific *cs = from_timer(cs, t, relock_timer);
1394 struct qib_devdata *dd = cs->dd;
1396 struct qib_pportdata *ppd = dd->pport; 1395 struct qib_pportdata *ppd = dd->pport;
1397 struct qib_chip_specific *cs = dd->cspec;
1398 int timeoff; 1396 int timeoff;
1399 1397
1400 /* 1398 /*
@@ -1440,9 +1438,7 @@ void set_7220_relock_poll(struct qib_devdata *dd, int ibup)
1440 /* If timer has not yet been started, do so. */ 1438 /* If timer has not yet been started, do so. */
1441 if (!cs->relock_timer_active) { 1439 if (!cs->relock_timer_active) {
1442 cs->relock_timer_active = 1; 1440 cs->relock_timer_active = 1;
1443 init_timer(&cs->relock_timer); 1441 timer_setup(&cs->relock_timer, qib_run_relock, 0);
1444 cs->relock_timer.function = qib_run_relock;
1445 cs->relock_timer.data = (unsigned long) dd;
1446 cs->relock_interval = timeout; 1442 cs->relock_interval = timeout;
1447 cs->relock_timer.expires = jiffies + timeout; 1443 cs->relock_timer.expires = jiffies + timeout;
1448 add_timer(&cs->relock_timer); 1444 add_timer(&cs->relock_timer);
diff --git a/drivers/infiniband/hw/qib/qib_sdma.c b/drivers/infiniband/hw/qib/qib_sdma.c
index 891873b38a1e..c3690bd51582 100644
--- a/drivers/infiniband/hw/qib/qib_sdma.c
+++ b/drivers/infiniband/hw/qib/qib_sdma.c
@@ -808,7 +808,7 @@ void __qib_sdma_process_event(struct qib_pportdata *ppd,
808 * bringing the link up with traffic active on 808 * bringing the link up with traffic active on
809 * 7220, e.g. */ 809 * 7220, e.g. */
810 ss->go_s99_running = 1; 810 ss->go_s99_running = 1;
811 /* fall through and start dma engine */ 811 /* fall through -- and start dma engine */
812 case qib_sdma_event_e10_go_hw_start: 812 case qib_sdma_event_e10_go_hw_start:
813 /* This reference means the state machine is started */ 813 /* This reference means the state machine is started */
814 sdma_get(&ppd->sdma_state); 814 sdma_get(&ppd->sdma_state);
diff --git a/drivers/infiniband/hw/qib/qib_tx.c b/drivers/infiniband/hw/qib/qib_tx.c
index eface3b3dacf..29785eb84646 100644
--- a/drivers/infiniband/hw/qib/qib_tx.c
+++ b/drivers/infiniband/hw/qib/qib_tx.c
@@ -179,8 +179,6 @@ void qib_disarm_piobufs_set(struct qib_devdata *dd, unsigned long *mask,
179 pppd[i] = NULL; 179 pppd[i] = NULL;
180 180
181 for (i = 0; i < cnt; i++) { 181 for (i = 0; i < cnt; i++) {
182 int which;
183
184 if (!test_bit(i, mask)) 182 if (!test_bit(i, mask))
185 continue; 183 continue;
186 /* 184 /*
@@ -201,9 +199,7 @@ void qib_disarm_piobufs_set(struct qib_devdata *dd, unsigned long *mask,
201 (!test_bit(i << 1, dd->pioavailkernel) && 199 (!test_bit(i << 1, dd->pioavailkernel) &&
202 find_ctxt(dd, i))) { 200 find_ctxt(dd, i))) {
203 __set_bit(i, dd->pio_need_disarm); 201 __set_bit(i, dd->pio_need_disarm);
204 which = 0;
205 } else { 202 } else {
206 which = 1;
207 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(i)); 203 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(i));
208 } 204 }
209 spin_unlock_irqrestore(&dd->pioavail_lock, flags); 205 spin_unlock_irqrestore(&dd->pioavail_lock, flags);
@@ -552,9 +548,9 @@ void qib_hol_up(struct qib_pportdata *ppd)
552/* 548/*
553 * This is only called via the timer. 549 * This is only called via the timer.
554 */ 550 */
555void qib_hol_event(unsigned long opaque) 551void qib_hol_event(struct timer_list *t)
556{ 552{
557 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 553 struct qib_pportdata *ppd = from_timer(ppd, t, hol_timer);
558 554
559 /* If hardware error, etc, skip. */ 555 /* If hardware error, etc, skip. */
560 if (!(ppd->dd->flags & QIB_INITTED)) 556 if (!(ppd->dd->flags & QIB_INITTED))
diff --git a/drivers/infiniband/hw/qib/qib_verbs.c b/drivers/infiniband/hw/qib/qib_verbs.c
index 9d92aeb8d9a1..c55000501582 100644
--- a/drivers/infiniband/hw/qib/qib_verbs.c
+++ b/drivers/infiniband/hw/qib/qib_verbs.c
@@ -389,9 +389,9 @@ drop:
389 * This is called from a timer to check for QPs 389 * This is called from a timer to check for QPs
390 * which need kernel memory in order to send a packet. 390 * which need kernel memory in order to send a packet.
391 */ 391 */
392static void mem_timer(unsigned long data) 392static void mem_timer(struct timer_list *t)
393{ 393{
394 struct qib_ibdev *dev = (struct qib_ibdev *) data; 394 struct qib_ibdev *dev = from_timer(dev, t, mem_timer);
395 struct list_head *list = &dev->memwait; 395 struct list_head *list = &dev->memwait;
396 struct rvt_qp *qp = NULL; 396 struct rvt_qp *qp = NULL;
397 struct qib_qp_priv *priv = NULL; 397 struct qib_qp_priv *priv = NULL;
@@ -701,7 +701,7 @@ void qib_put_txreq(struct qib_verbs_txreq *tx)
701 */ 701 */
702void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail) 702void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
703{ 703{
704 struct rvt_qp *qp, *nqp; 704 struct rvt_qp *qp;
705 struct qib_qp_priv *qpp, *nqpp; 705 struct qib_qp_priv *qpp, *nqpp;
706 struct rvt_qp *qps[20]; 706 struct rvt_qp *qps[20];
707 struct qib_ibdev *dev; 707 struct qib_ibdev *dev;
@@ -714,7 +714,6 @@ void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
714 /* Search wait list for first QP wanting DMA descriptors. */ 714 /* Search wait list for first QP wanting DMA descriptors. */
715 list_for_each_entry_safe(qpp, nqpp, &dev->dmawait, iowait) { 715 list_for_each_entry_safe(qpp, nqpp, &dev->dmawait, iowait) {
716 qp = qpp->owner; 716 qp = qpp->owner;
717 nqp = nqpp->owner;
718 if (qp->port_num != ppd->port) 717 if (qp->port_num != ppd->port)
719 continue; 718 continue;
720 if (n == ARRAY_SIZE(qps)) 719 if (n == ARRAY_SIZE(qps))
@@ -1532,7 +1531,7 @@ int qib_register_ib_device(struct qib_devdata *dd)
1532 init_ibport(ppd + i); 1531 init_ibport(ppd + i);
1533 1532
1534 /* Only need to initialize non-zero fields. */ 1533 /* Only need to initialize non-zero fields. */
1535 setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev); 1534 timer_setup(&dev->mem_timer, mem_timer, 0);
1536 1535
1537 INIT_LIST_HEAD(&dev->piowait); 1536 INIT_LIST_HEAD(&dev->piowait);
1538 INIT_LIST_HEAD(&dev->dmawait); 1537 INIT_LIST_HEAD(&dev->dmawait);
diff --git a/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c b/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c
index 092d4e11a633..912d8ef04352 100644
--- a/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c
+++ b/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c
@@ -392,14 +392,12 @@ int usnic_ib_qp_grp_modify(struct usnic_ib_qp_grp *qp_grp,
392 void *data) 392 void *data)
393{ 393{
394 int status = 0; 394 int status = 0;
395 int vnic_idx;
396 struct ib_event ib_event; 395 struct ib_event ib_event;
397 enum ib_qp_state old_state; 396 enum ib_qp_state old_state;
398 struct usnic_transport_spec *trans_spec; 397 struct usnic_transport_spec *trans_spec;
399 struct usnic_ib_qp_grp_flow *qp_flow; 398 struct usnic_ib_qp_grp_flow *qp_flow;
400 399
401 old_state = qp_grp->state; 400 old_state = qp_grp->state;
402 vnic_idx = usnic_vnic_get_index(qp_grp->vf->vnic);
403 trans_spec = (struct usnic_transport_spec *) data; 401 trans_spec = (struct usnic_transport_spec *) data;
404 402
405 spin_lock(&qp_grp->lock); 403 spin_lock(&qp_grp->lock);
diff --git a/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.h b/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.h
index b1458be1d402..a8a2314c9531 100644
--- a/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.h
+++ b/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.h
@@ -84,30 +84,7 @@ struct usnic_ib_qp_grp_flow {
84 char dentry_name[32]; 84 char dentry_name[32];
85}; 85};
86 86
87static const struct 87extern const struct usnic_vnic_res_spec min_transport_spec[USNIC_TRANSPORT_MAX];
88usnic_vnic_res_spec min_transport_spec[USNIC_TRANSPORT_MAX] = {
89 { /*USNIC_TRANSPORT_UNKNOWN*/
90 .resources = {
91 {.type = USNIC_VNIC_RES_TYPE_EOL, .cnt = 0,},
92 },
93 },
94 { /*USNIC_TRANSPORT_ROCE_CUSTOM*/
95 .resources = {
96 {.type = USNIC_VNIC_RES_TYPE_WQ, .cnt = 1,},
97 {.type = USNIC_VNIC_RES_TYPE_RQ, .cnt = 1,},
98 {.type = USNIC_VNIC_RES_TYPE_CQ, .cnt = 1,},
99 {.type = USNIC_VNIC_RES_TYPE_EOL, .cnt = 0,},
100 },
101 },
102 { /*USNIC_TRANSPORT_IPV4_UDP*/
103 .resources = {
104 {.type = USNIC_VNIC_RES_TYPE_WQ, .cnt = 1,},
105 {.type = USNIC_VNIC_RES_TYPE_RQ, .cnt = 1,},
106 {.type = USNIC_VNIC_RES_TYPE_CQ, .cnt = 1,},
107 {.type = USNIC_VNIC_RES_TYPE_EOL, .cnt = 0,},
108 },
109 },
110};
111 88
112const char *usnic_ib_qp_grp_state_to_string(enum ib_qp_state state); 89const char *usnic_ib_qp_grp_state_to_string(enum ib_qp_state state);
113int usnic_ib_qp_grp_dump_hdr(char *buf, int buf_sz); 90int usnic_ib_qp_grp_dump_hdr(char *buf, int buf_sz);
diff --git a/drivers/infiniband/hw/usnic/usnic_ib_sysfs.c b/drivers/infiniband/hw/usnic/usnic_ib_sysfs.c
index 32956f9f5715..685ef2293cb8 100644
--- a/drivers/infiniband/hw/usnic/usnic_ib_sysfs.c
+++ b/drivers/infiniband/hw/usnic/usnic_ib_sysfs.c
@@ -43,6 +43,7 @@
43#include "usnic_ib_qp_grp.h" 43#include "usnic_ib_qp_grp.h"
44#include "usnic_vnic.h" 44#include "usnic_vnic.h"
45#include "usnic_ib_verbs.h" 45#include "usnic_ib_verbs.h"
46#include "usnic_ib_sysfs.h"
46#include "usnic_log.h" 47#include "usnic_log.h"
47#include "usnic_ib_sysfs.h" 48#include "usnic_ib_sysfs.h"
48 49
diff --git a/drivers/infiniband/hw/usnic/usnic_ib_verbs.c b/drivers/infiniband/hw/usnic/usnic_ib_verbs.c
index e4113ef09315..aa2456a4f9bd 100644
--- a/drivers/infiniband/hw/usnic/usnic_ib_verbs.c
+++ b/drivers/infiniband/hw/usnic/usnic_ib_verbs.c
@@ -42,6 +42,7 @@
42#include "usnic_ib.h" 42#include "usnic_ib.h"
43#include "usnic_common_util.h" 43#include "usnic_common_util.h"
44#include "usnic_ib_qp_grp.h" 44#include "usnic_ib_qp_grp.h"
45#include "usnic_ib_verbs.h"
45#include "usnic_fwd.h" 46#include "usnic_fwd.h"
46#include "usnic_log.h" 47#include "usnic_log.h"
47#include "usnic_uiom.h" 48#include "usnic_uiom.h"
@@ -50,6 +51,30 @@
50 51
51#define USNIC_DEFAULT_TRANSPORT USNIC_TRANSPORT_ROCE_CUSTOM 52#define USNIC_DEFAULT_TRANSPORT USNIC_TRANSPORT_ROCE_CUSTOM
52 53
54const struct usnic_vnic_res_spec min_transport_spec[USNIC_TRANSPORT_MAX] = {
55 { /*USNIC_TRANSPORT_UNKNOWN*/
56 .resources = {
57 {.type = USNIC_VNIC_RES_TYPE_EOL, .cnt = 0,},
58 },
59 },
60 { /*USNIC_TRANSPORT_ROCE_CUSTOM*/
61 .resources = {
62 {.type = USNIC_VNIC_RES_TYPE_WQ, .cnt = 1,},
63 {.type = USNIC_VNIC_RES_TYPE_RQ, .cnt = 1,},
64 {.type = USNIC_VNIC_RES_TYPE_CQ, .cnt = 1,},
65 {.type = USNIC_VNIC_RES_TYPE_EOL, .cnt = 0,},
66 },
67 },
68 { /*USNIC_TRANSPORT_IPV4_UDP*/
69 .resources = {
70 {.type = USNIC_VNIC_RES_TYPE_WQ, .cnt = 1,},
71 {.type = USNIC_VNIC_RES_TYPE_RQ, .cnt = 1,},
72 {.type = USNIC_VNIC_RES_TYPE_CQ, .cnt = 1,},
73 {.type = USNIC_VNIC_RES_TYPE_EOL, .cnt = 0,},
74 },
75 },
76};
77
53static void usnic_ib_fw_string_to_u64(char *fw_ver_str, u64 *fw_ver) 78static void usnic_ib_fw_string_to_u64(char *fw_ver_str, u64 *fw_ver)
54{ 79{
55 *fw_ver = *((u64 *)fw_ver_str); 80 *fw_ver = *((u64 *)fw_ver_str);
diff --git a/drivers/infiniband/hw/vmw_pvrdma/Makefile b/drivers/infiniband/hw/vmw_pvrdma/Makefile
index 0194ed19f542..2f52e0a044a0 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/Makefile
+++ b/drivers/infiniband/hw/vmw_pvrdma/Makefile
@@ -1,3 +1,3 @@
1obj-$(CONFIG_INFINIBAND_VMWARE_PVRDMA) += vmw_pvrdma.o 1obj-$(CONFIG_INFINIBAND_VMWARE_PVRDMA) += vmw_pvrdma.o
2 2
3vmw_pvrdma-y := pvrdma_cmd.o pvrdma_cq.o pvrdma_doorbell.o pvrdma_main.o pvrdma_misc.o pvrdma_mr.o pvrdma_qp.o pvrdma_verbs.o 3vmw_pvrdma-y := pvrdma_cmd.o pvrdma_cq.o pvrdma_doorbell.o pvrdma_main.o pvrdma_misc.o pvrdma_mr.o pvrdma_qp.o pvrdma_srq.o pvrdma_verbs.o
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma.h b/drivers/infiniband/hw/vmw_pvrdma/pvrdma.h
index 984aa3484928..63bc2efc34eb 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma.h
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma.h
@@ -162,6 +162,22 @@ struct pvrdma_ah {
162 struct pvrdma_av av; 162 struct pvrdma_av av;
163}; 163};
164 164
165struct pvrdma_srq {
166 struct ib_srq ibsrq;
167 int offset;
168 spinlock_t lock; /* SRQ lock. */
169 int wqe_cnt;
170 int wqe_size;
171 int max_gs;
172 struct ib_umem *umem;
173 struct pvrdma_ring_state *ring;
174 struct pvrdma_page_dir pdir;
175 u32 srq_handle;
176 int npages;
177 refcount_t refcnt;
178 wait_queue_head_t wait;
179};
180
165struct pvrdma_qp { 181struct pvrdma_qp {
166 struct ib_qp ibqp; 182 struct ib_qp ibqp;
167 u32 qp_handle; 183 u32 qp_handle;
@@ -171,6 +187,7 @@ struct pvrdma_qp {
171 struct ib_umem *rumem; 187 struct ib_umem *rumem;
172 struct ib_umem *sumem; 188 struct ib_umem *sumem;
173 struct pvrdma_page_dir pdir; 189 struct pvrdma_page_dir pdir;
190 struct pvrdma_srq *srq;
174 int npages; 191 int npages;
175 int npages_send; 192 int npages_send;
176 int npages_recv; 193 int npages_recv;
@@ -210,6 +227,8 @@ struct pvrdma_dev {
210 struct pvrdma_page_dir cq_pdir; 227 struct pvrdma_page_dir cq_pdir;
211 struct pvrdma_cq **cq_tbl; 228 struct pvrdma_cq **cq_tbl;
212 spinlock_t cq_tbl_lock; 229 spinlock_t cq_tbl_lock;
230 struct pvrdma_srq **srq_tbl;
231 spinlock_t srq_tbl_lock;
213 struct pvrdma_qp **qp_tbl; 232 struct pvrdma_qp **qp_tbl;
214 spinlock_t qp_tbl_lock; 233 spinlock_t qp_tbl_lock;
215 struct pvrdma_uar_table uar_table; 234 struct pvrdma_uar_table uar_table;
@@ -221,6 +240,7 @@ struct pvrdma_dev {
221 bool ib_active; 240 bool ib_active;
222 atomic_t num_qps; 241 atomic_t num_qps;
223 atomic_t num_cqs; 242 atomic_t num_cqs;
243 atomic_t num_srqs;
224 atomic_t num_pds; 244 atomic_t num_pds;
225 atomic_t num_ahs; 245 atomic_t num_ahs;
226 246
@@ -256,6 +276,11 @@ static inline struct pvrdma_cq *to_vcq(struct ib_cq *ibcq)
256 return container_of(ibcq, struct pvrdma_cq, ibcq); 276 return container_of(ibcq, struct pvrdma_cq, ibcq);
257} 277}
258 278
279static inline struct pvrdma_srq *to_vsrq(struct ib_srq *ibsrq)
280{
281 return container_of(ibsrq, struct pvrdma_srq, ibsrq);
282}
283
259static inline struct pvrdma_user_mr *to_vmr(struct ib_mr *ibmr) 284static inline struct pvrdma_user_mr *to_vmr(struct ib_mr *ibmr)
260{ 285{
261 return container_of(ibmr, struct pvrdma_user_mr, ibmr); 286 return container_of(ibmr, struct pvrdma_user_mr, ibmr);
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
index df0a6b525021..6fd5a8f4e2f6 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
@@ -339,6 +339,10 @@ enum {
339 PVRDMA_CMD_DESTROY_UC, 339 PVRDMA_CMD_DESTROY_UC,
340 PVRDMA_CMD_CREATE_BIND, 340 PVRDMA_CMD_CREATE_BIND,
341 PVRDMA_CMD_DESTROY_BIND, 341 PVRDMA_CMD_DESTROY_BIND,
342 PVRDMA_CMD_CREATE_SRQ,
343 PVRDMA_CMD_MODIFY_SRQ,
344 PVRDMA_CMD_QUERY_SRQ,
345 PVRDMA_CMD_DESTROY_SRQ,
342 PVRDMA_CMD_MAX, 346 PVRDMA_CMD_MAX,
343}; 347};
344 348
@@ -361,6 +365,10 @@ enum {
361 PVRDMA_CMD_DESTROY_UC_RESP_NOOP, 365 PVRDMA_CMD_DESTROY_UC_RESP_NOOP,
362 PVRDMA_CMD_CREATE_BIND_RESP_NOOP, 366 PVRDMA_CMD_CREATE_BIND_RESP_NOOP,
363 PVRDMA_CMD_DESTROY_BIND_RESP_NOOP, 367 PVRDMA_CMD_DESTROY_BIND_RESP_NOOP,
368 PVRDMA_CMD_CREATE_SRQ_RESP,
369 PVRDMA_CMD_MODIFY_SRQ_RESP,
370 PVRDMA_CMD_QUERY_SRQ_RESP,
371 PVRDMA_CMD_DESTROY_SRQ_RESP,
364 PVRDMA_CMD_MAX_RESP, 372 PVRDMA_CMD_MAX_RESP,
365}; 373};
366 374
@@ -495,6 +503,46 @@ struct pvrdma_cmd_destroy_cq {
495 u8 reserved[4]; 503 u8 reserved[4];
496}; 504};
497 505
506struct pvrdma_cmd_create_srq {
507 struct pvrdma_cmd_hdr hdr;
508 u64 pdir_dma;
509 u32 pd_handle;
510 u32 nchunks;
511 struct pvrdma_srq_attr attrs;
512 u8 srq_type;
513 u8 reserved[7];
514};
515
516struct pvrdma_cmd_create_srq_resp {
517 struct pvrdma_cmd_resp_hdr hdr;
518 u32 srqn;
519 u8 reserved[4];
520};
521
522struct pvrdma_cmd_modify_srq {
523 struct pvrdma_cmd_hdr hdr;
524 u32 srq_handle;
525 u32 attr_mask;
526 struct pvrdma_srq_attr attrs;
527};
528
529struct pvrdma_cmd_query_srq {
530 struct pvrdma_cmd_hdr hdr;
531 u32 srq_handle;
532 u8 reserved[4];
533};
534
535struct pvrdma_cmd_query_srq_resp {
536 struct pvrdma_cmd_resp_hdr hdr;
537 struct pvrdma_srq_attr attrs;
538};
539
540struct pvrdma_cmd_destroy_srq {
541 struct pvrdma_cmd_hdr hdr;
542 u32 srq_handle;
543 u8 reserved[4];
544};
545
498struct pvrdma_cmd_create_qp { 546struct pvrdma_cmd_create_qp {
499 struct pvrdma_cmd_hdr hdr; 547 struct pvrdma_cmd_hdr hdr;
500 u64 pdir_dma; 548 u64 pdir_dma;
@@ -594,6 +642,10 @@ union pvrdma_cmd_req {
594 struct pvrdma_cmd_destroy_qp destroy_qp; 642 struct pvrdma_cmd_destroy_qp destroy_qp;
595 struct pvrdma_cmd_create_bind create_bind; 643 struct pvrdma_cmd_create_bind create_bind;
596 struct pvrdma_cmd_destroy_bind destroy_bind; 644 struct pvrdma_cmd_destroy_bind destroy_bind;
645 struct pvrdma_cmd_create_srq create_srq;
646 struct pvrdma_cmd_modify_srq modify_srq;
647 struct pvrdma_cmd_query_srq query_srq;
648 struct pvrdma_cmd_destroy_srq destroy_srq;
597}; 649};
598 650
599union pvrdma_cmd_resp { 651union pvrdma_cmd_resp {
@@ -608,6 +660,8 @@ union pvrdma_cmd_resp {
608 struct pvrdma_cmd_create_qp_resp create_qp_resp; 660 struct pvrdma_cmd_create_qp_resp create_qp_resp;
609 struct pvrdma_cmd_query_qp_resp query_qp_resp; 661 struct pvrdma_cmd_query_qp_resp query_qp_resp;
610 struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp; 662 struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
663 struct pvrdma_cmd_create_srq_resp create_srq_resp;
664 struct pvrdma_cmd_query_srq_resp query_srq_resp;
611}; 665};
612 666
613#endif /* __PVRDMA_DEV_API_H__ */ 667#endif /* __PVRDMA_DEV_API_H__ */
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c
index 6ce709a67959..1f4e18717a00 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c
@@ -118,6 +118,7 @@ static int pvrdma_init_device(struct pvrdma_dev *dev)
118 spin_lock_init(&dev->cmd_lock); 118 spin_lock_init(&dev->cmd_lock);
119 sema_init(&dev->cmd_sema, 1); 119 sema_init(&dev->cmd_sema, 1);
120 atomic_set(&dev->num_qps, 0); 120 atomic_set(&dev->num_qps, 0);
121 atomic_set(&dev->num_srqs, 0);
121 atomic_set(&dev->num_cqs, 0); 122 atomic_set(&dev->num_cqs, 0);
122 atomic_set(&dev->num_pds, 0); 123 atomic_set(&dev->num_pds, 0);
123 atomic_set(&dev->num_ahs, 0); 124 atomic_set(&dev->num_ahs, 0);
@@ -254,9 +255,32 @@ static int pvrdma_register_device(struct pvrdma_dev *dev)
254 goto err_cq_free; 255 goto err_cq_free;
255 spin_lock_init(&dev->qp_tbl_lock); 256 spin_lock_init(&dev->qp_tbl_lock);
256 257
258 /* Check if SRQ is supported by backend */
259 if (dev->dsr->caps.max_srq) {
260 dev->ib_dev.uverbs_cmd_mask |=
261 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
262 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
263 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
264 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
265 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
266
267 dev->ib_dev.create_srq = pvrdma_create_srq;
268 dev->ib_dev.modify_srq = pvrdma_modify_srq;
269 dev->ib_dev.query_srq = pvrdma_query_srq;
270 dev->ib_dev.destroy_srq = pvrdma_destroy_srq;
271 dev->ib_dev.post_srq_recv = pvrdma_post_srq_recv;
272
273 dev->srq_tbl = kcalloc(dev->dsr->caps.max_srq,
274 sizeof(struct pvrdma_srq *),
275 GFP_KERNEL);
276 if (!dev->srq_tbl)
277 goto err_qp_free;
278 }
279 spin_lock_init(&dev->srq_tbl_lock);
280
257 ret = ib_register_device(&dev->ib_dev, NULL); 281 ret = ib_register_device(&dev->ib_dev, NULL);
258 if (ret) 282 if (ret)
259 goto err_qp_free; 283 goto err_srq_free;
260 284
261 for (i = 0; i < ARRAY_SIZE(pvrdma_class_attributes); ++i) { 285 for (i = 0; i < ARRAY_SIZE(pvrdma_class_attributes); ++i) {
262 ret = device_create_file(&dev->ib_dev.dev, 286 ret = device_create_file(&dev->ib_dev.dev,
@@ -271,6 +295,8 @@ static int pvrdma_register_device(struct pvrdma_dev *dev)
271 295
272err_class: 296err_class:
273 ib_unregister_device(&dev->ib_dev); 297 ib_unregister_device(&dev->ib_dev);
298err_srq_free:
299 kfree(dev->srq_tbl);
274err_qp_free: 300err_qp_free:
275 kfree(dev->qp_tbl); 301 kfree(dev->qp_tbl);
276err_cq_free: 302err_cq_free:
@@ -353,6 +379,35 @@ static void pvrdma_cq_event(struct pvrdma_dev *dev, u32 cqn, int type)
353 } 379 }
354} 380}
355 381
382static void pvrdma_srq_event(struct pvrdma_dev *dev, u32 srqn, int type)
383{
384 struct pvrdma_srq *srq;
385 unsigned long flags;
386
387 spin_lock_irqsave(&dev->srq_tbl_lock, flags);
388 if (dev->srq_tbl)
389 srq = dev->srq_tbl[srqn % dev->dsr->caps.max_srq];
390 else
391 srq = NULL;
392 if (srq)
393 refcount_inc(&srq->refcnt);
394 spin_unlock_irqrestore(&dev->srq_tbl_lock, flags);
395
396 if (srq && srq->ibsrq.event_handler) {
397 struct ib_srq *ibsrq = &srq->ibsrq;
398 struct ib_event e;
399
400 e.device = ibsrq->device;
401 e.element.srq = ibsrq;
402 e.event = type; /* 1:1 mapping for now. */
403 ibsrq->event_handler(&e, ibsrq->srq_context);
404 }
405 if (srq) {
406 if (refcount_dec_and_test(&srq->refcnt))
407 wake_up(&srq->wait);
408 }
409}
410
356static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port, 411static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port,
357 enum ib_event_type event) 412 enum ib_event_type event)
358{ 413{
@@ -423,6 +478,7 @@ static irqreturn_t pvrdma_intr1_handler(int irq, void *dev_id)
423 478
424 case PVRDMA_EVENT_SRQ_ERR: 479 case PVRDMA_EVENT_SRQ_ERR:
425 case PVRDMA_EVENT_SRQ_LIMIT_REACHED: 480 case PVRDMA_EVENT_SRQ_LIMIT_REACHED:
481 pvrdma_srq_event(dev, eqe->info, eqe->type);
426 break; 482 break;
427 483
428 case PVRDMA_EVENT_PORT_ACTIVE: 484 case PVRDMA_EVENT_PORT_ACTIVE:
@@ -1059,6 +1115,7 @@ static void pvrdma_pci_remove(struct pci_dev *pdev)
1059 iounmap(dev->regs); 1115 iounmap(dev->regs);
1060 kfree(dev->sgid_tbl); 1116 kfree(dev->sgid_tbl);
1061 kfree(dev->cq_tbl); 1117 kfree(dev->cq_tbl);
1118 kfree(dev->srq_tbl);
1062 kfree(dev->qp_tbl); 1119 kfree(dev->qp_tbl);
1063 pvrdma_uar_table_cleanup(dev); 1120 pvrdma_uar_table_cleanup(dev);
1064 iounmap(dev->driver_uar.map); 1121 iounmap(dev->driver_uar.map);
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c
index ed34d5a581fa..10420a18d02f 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c
@@ -198,6 +198,7 @@ struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
198 struct pvrdma_create_qp ucmd; 198 struct pvrdma_create_qp ucmd;
199 unsigned long flags; 199 unsigned long flags;
200 int ret; 200 int ret;
201 bool is_srq = !!init_attr->srq;
201 202
202 if (init_attr->create_flags) { 203 if (init_attr->create_flags) {
203 dev_warn(&dev->pdev->dev, 204 dev_warn(&dev->pdev->dev,
@@ -214,6 +215,12 @@ struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
214 return ERR_PTR(-EINVAL); 215 return ERR_PTR(-EINVAL);
215 } 216 }
216 217
218 if (is_srq && !dev->dsr->caps.max_srq) {
219 dev_warn(&dev->pdev->dev,
220 "SRQs not supported by device\n");
221 return ERR_PTR(-EINVAL);
222 }
223
217 if (!atomic_add_unless(&dev->num_qps, 1, dev->dsr->caps.max_qp)) 224 if (!atomic_add_unless(&dev->num_qps, 1, dev->dsr->caps.max_qp))
218 return ERR_PTR(-ENOMEM); 225 return ERR_PTR(-ENOMEM);
219 226
@@ -252,26 +259,36 @@ struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
252 goto err_qp; 259 goto err_qp;
253 } 260 }
254 261
255 /* set qp->sq.wqe_cnt, shift, buf_size.. */ 262 if (!is_srq) {
256 qp->rumem = ib_umem_get(pd->uobject->context, 263 /* set qp->sq.wqe_cnt, shift, buf_size.. */
257 ucmd.rbuf_addr, 264 qp->rumem = ib_umem_get(pd->uobject->context,
258 ucmd.rbuf_size, 0, 0); 265 ucmd.rbuf_addr,
259 if (IS_ERR(qp->rumem)) { 266 ucmd.rbuf_size, 0, 0);
260 ret = PTR_ERR(qp->rumem); 267 if (IS_ERR(qp->rumem)) {
261 goto err_qp; 268 ret = PTR_ERR(qp->rumem);
269 goto err_qp;
270 }
271 qp->srq = NULL;
272 } else {
273 qp->rumem = NULL;
274 qp->srq = to_vsrq(init_attr->srq);
262 } 275 }
263 276
264 qp->sumem = ib_umem_get(pd->uobject->context, 277 qp->sumem = ib_umem_get(pd->uobject->context,
265 ucmd.sbuf_addr, 278 ucmd.sbuf_addr,
266 ucmd.sbuf_size, 0, 0); 279 ucmd.sbuf_size, 0, 0);
267 if (IS_ERR(qp->sumem)) { 280 if (IS_ERR(qp->sumem)) {
268 ib_umem_release(qp->rumem); 281 if (!is_srq)
282 ib_umem_release(qp->rumem);
269 ret = PTR_ERR(qp->sumem); 283 ret = PTR_ERR(qp->sumem);
270 goto err_qp; 284 goto err_qp;
271 } 285 }
272 286
273 qp->npages_send = ib_umem_page_count(qp->sumem); 287 qp->npages_send = ib_umem_page_count(qp->sumem);
274 qp->npages_recv = ib_umem_page_count(qp->rumem); 288 if (!is_srq)
289 qp->npages_recv = ib_umem_page_count(qp->rumem);
290 else
291 qp->npages_recv = 0;
275 qp->npages = qp->npages_send + qp->npages_recv; 292 qp->npages = qp->npages_send + qp->npages_recv;
276 } else { 293 } else {
277 qp->is_kernel = true; 294 qp->is_kernel = true;
@@ -312,12 +329,14 @@ struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
312 329
313 if (!qp->is_kernel) { 330 if (!qp->is_kernel) {
314 pvrdma_page_dir_insert_umem(&qp->pdir, qp->sumem, 0); 331 pvrdma_page_dir_insert_umem(&qp->pdir, qp->sumem, 0);
315 pvrdma_page_dir_insert_umem(&qp->pdir, qp->rumem, 332 if (!is_srq)
316 qp->npages_send); 333 pvrdma_page_dir_insert_umem(&qp->pdir,
334 qp->rumem,
335 qp->npages_send);
317 } else { 336 } else {
318 /* Ring state is always the first page. */ 337 /* Ring state is always the first page. */
319 qp->sq.ring = qp->pdir.pages[0]; 338 qp->sq.ring = qp->pdir.pages[0];
320 qp->rq.ring = &qp->sq.ring[1]; 339 qp->rq.ring = is_srq ? NULL : &qp->sq.ring[1];
321 } 340 }
322 break; 341 break;
323 default: 342 default:
@@ -333,6 +352,10 @@ struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
333 cmd->pd_handle = to_vpd(pd)->pd_handle; 352 cmd->pd_handle = to_vpd(pd)->pd_handle;
334 cmd->send_cq_handle = to_vcq(init_attr->send_cq)->cq_handle; 353 cmd->send_cq_handle = to_vcq(init_attr->send_cq)->cq_handle;
335 cmd->recv_cq_handle = to_vcq(init_attr->recv_cq)->cq_handle; 354 cmd->recv_cq_handle = to_vcq(init_attr->recv_cq)->cq_handle;
355 if (is_srq)
356 cmd->srq_handle = to_vsrq(init_attr->srq)->srq_handle;
357 else
358 cmd->srq_handle = 0;
336 cmd->max_send_wr = init_attr->cap.max_send_wr; 359 cmd->max_send_wr = init_attr->cap.max_send_wr;
337 cmd->max_recv_wr = init_attr->cap.max_recv_wr; 360 cmd->max_recv_wr = init_attr->cap.max_recv_wr;
338 cmd->max_send_sge = init_attr->cap.max_send_sge; 361 cmd->max_send_sge = init_attr->cap.max_send_sge;
@@ -340,6 +363,8 @@ struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
340 cmd->max_inline_data = init_attr->cap.max_inline_data; 363 cmd->max_inline_data = init_attr->cap.max_inline_data;
341 cmd->sq_sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0; 364 cmd->sq_sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
342 cmd->qp_type = ib_qp_type_to_pvrdma(init_attr->qp_type); 365 cmd->qp_type = ib_qp_type_to_pvrdma(init_attr->qp_type);
366 cmd->is_srq = is_srq;
367 cmd->lkey = 0;
343 cmd->access_flags = IB_ACCESS_LOCAL_WRITE; 368 cmd->access_flags = IB_ACCESS_LOCAL_WRITE;
344 cmd->total_chunks = qp->npages; 369 cmd->total_chunks = qp->npages;
345 cmd->send_chunks = qp->npages_send - PVRDMA_QP_NUM_HEADER_PAGES; 370 cmd->send_chunks = qp->npages_send - PVRDMA_QP_NUM_HEADER_PAGES;
@@ -815,6 +840,12 @@ int pvrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
815 return -EINVAL; 840 return -EINVAL;
816 } 841 }
817 842
843 if (qp->srq) {
844 dev_warn(&dev->pdev->dev, "QP associated with SRQ\n");
845 *bad_wr = wr;
846 return -EINVAL;
847 }
848
818 spin_lock_irqsave(&qp->rq.lock, flags); 849 spin_lock_irqsave(&qp->rq.lock, flags);
819 850
820 while (wr) { 851 while (wr) {
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c
new file mode 100644
index 000000000000..826ccb864596
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c
@@ -0,0 +1,319 @@
1/*
2 * Copyright (c) 2016-2017 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <asm/page.h>
47#include <linux/io.h>
48#include <linux/wait.h>
49#include <rdma/ib_addr.h>
50#include <rdma/ib_smi.h>
51#include <rdma/ib_user_verbs.h>
52
53#include "pvrdma.h"
54
55int pvrdma_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
56 struct ib_recv_wr **bad_wr)
57{
58 /* No support for kernel clients. */
59 return -EOPNOTSUPP;
60}
61
62/**
63 * pvrdma_query_srq - query shared receive queue
64 * @ibsrq: the shared receive queue to query
65 * @srq_attr: attributes to query and return to client
66 *
67 * @return: 0 for success, otherwise returns an errno.
68 */
69int pvrdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
70{
71 struct pvrdma_dev *dev = to_vdev(ibsrq->device);
72 struct pvrdma_srq *srq = to_vsrq(ibsrq);
73 union pvrdma_cmd_req req;
74 union pvrdma_cmd_resp rsp;
75 struct pvrdma_cmd_query_srq *cmd = &req.query_srq;
76 struct pvrdma_cmd_query_srq_resp *resp = &rsp.query_srq_resp;
77 int ret;
78
79 memset(cmd, 0, sizeof(*cmd));
80 cmd->hdr.cmd = PVRDMA_CMD_QUERY_SRQ;
81 cmd->srq_handle = srq->srq_handle;
82
83 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_QUERY_SRQ_RESP);
84 if (ret < 0) {
85 dev_warn(&dev->pdev->dev,
86 "could not query shared receive queue, error: %d\n",
87 ret);
88 return -EINVAL;
89 }
90
91 srq_attr->srq_limit = resp->attrs.srq_limit;
92 srq_attr->max_wr = resp->attrs.max_wr;
93 srq_attr->max_sge = resp->attrs.max_sge;
94
95 return 0;
96}
97
98/**
99 * pvrdma_create_srq - create shared receive queue
100 * @pd: protection domain
101 * @init_attr: shared receive queue attributes
102 * @udata: user data
103 *
104 * @return: the ib_srq pointer on success, otherwise returns an errno.
105 */
106struct ib_srq *pvrdma_create_srq(struct ib_pd *pd,
107 struct ib_srq_init_attr *init_attr,
108 struct ib_udata *udata)
109{
110 struct pvrdma_srq *srq = NULL;
111 struct pvrdma_dev *dev = to_vdev(pd->device);
112 union pvrdma_cmd_req req;
113 union pvrdma_cmd_resp rsp;
114 struct pvrdma_cmd_create_srq *cmd = &req.create_srq;
115 struct pvrdma_cmd_create_srq_resp *resp = &rsp.create_srq_resp;
116 struct pvrdma_create_srq ucmd;
117 unsigned long flags;
118 int ret;
119
120 if (!(pd->uobject && udata)) {
121 /* No support for kernel clients. */
122 dev_warn(&dev->pdev->dev,
123 "no shared receive queue support for kernel client\n");
124 return ERR_PTR(-EOPNOTSUPP);
125 }
126
127 if (init_attr->srq_type != IB_SRQT_BASIC) {
128 dev_warn(&dev->pdev->dev,
129 "shared receive queue type %d not supported\n",
130 init_attr->srq_type);
131 return ERR_PTR(-EINVAL);
132 }
133
134 if (init_attr->attr.max_wr > dev->dsr->caps.max_srq_wr ||
135 init_attr->attr.max_sge > dev->dsr->caps.max_srq_sge) {
136 dev_warn(&dev->pdev->dev,
137 "shared receive queue size invalid\n");
138 return ERR_PTR(-EINVAL);
139 }
140
141 if (!atomic_add_unless(&dev->num_srqs, 1, dev->dsr->caps.max_srq))
142 return ERR_PTR(-ENOMEM);
143
144 srq = kmalloc(sizeof(*srq), GFP_KERNEL);
145 if (!srq) {
146 ret = -ENOMEM;
147 goto err_srq;
148 }
149
150 spin_lock_init(&srq->lock);
151 refcount_set(&srq->refcnt, 1);
152 init_waitqueue_head(&srq->wait);
153
154 dev_dbg(&dev->pdev->dev,
155 "create shared receive queue from user space\n");
156
157 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
158 ret = -EFAULT;
159 goto err_srq;
160 }
161
162 srq->umem = ib_umem_get(pd->uobject->context,
163 ucmd.buf_addr,
164 ucmd.buf_size, 0, 0);
165 if (IS_ERR(srq->umem)) {
166 ret = PTR_ERR(srq->umem);
167 goto err_srq;
168 }
169
170 srq->npages = ib_umem_page_count(srq->umem);
171
172 if (srq->npages < 0 || srq->npages > PVRDMA_PAGE_DIR_MAX_PAGES) {
173 dev_warn(&dev->pdev->dev,
174 "overflow pages in shared receive queue\n");
175 ret = -EINVAL;
176 goto err_umem;
177 }
178
179 ret = pvrdma_page_dir_init(dev, &srq->pdir, srq->npages, false);
180 if (ret) {
181 dev_warn(&dev->pdev->dev,
182 "could not allocate page directory\n");
183 goto err_umem;
184 }
185
186 pvrdma_page_dir_insert_umem(&srq->pdir, srq->umem, 0);
187
188 memset(cmd, 0, sizeof(*cmd));
189 cmd->hdr.cmd = PVRDMA_CMD_CREATE_SRQ;
190 cmd->srq_type = init_attr->srq_type;
191 cmd->nchunks = srq->npages;
192 cmd->pd_handle = to_vpd(pd)->pd_handle;
193 cmd->attrs.max_wr = init_attr->attr.max_wr;
194 cmd->attrs.max_sge = init_attr->attr.max_sge;
195 cmd->attrs.srq_limit = init_attr->attr.srq_limit;
196 cmd->pdir_dma = srq->pdir.dir_dma;
197
198 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_CREATE_SRQ_RESP);
199 if (ret < 0) {
200 dev_warn(&dev->pdev->dev,
201 "could not create shared receive queue, error: %d\n",
202 ret);
203 goto err_page_dir;
204 }
205
206 srq->srq_handle = resp->srqn;
207 spin_lock_irqsave(&dev->srq_tbl_lock, flags);
208 dev->srq_tbl[srq->srq_handle % dev->dsr->caps.max_srq] = srq;
209 spin_unlock_irqrestore(&dev->srq_tbl_lock, flags);
210
211 /* Copy udata back. */
212 if (ib_copy_to_udata(udata, &srq->srq_handle, sizeof(__u32))) {
213 dev_warn(&dev->pdev->dev, "failed to copy back udata\n");
214 pvrdma_destroy_srq(&srq->ibsrq);
215 return ERR_PTR(-EINVAL);
216 }
217
218 return &srq->ibsrq;
219
220err_page_dir:
221 pvrdma_page_dir_cleanup(dev, &srq->pdir);
222err_umem:
223 ib_umem_release(srq->umem);
224err_srq:
225 kfree(srq);
226 atomic_dec(&dev->num_srqs);
227
228 return ERR_PTR(ret);
229}
230
231static void pvrdma_free_srq(struct pvrdma_dev *dev, struct pvrdma_srq *srq)
232{
233 unsigned long flags;
234
235 spin_lock_irqsave(&dev->srq_tbl_lock, flags);
236 dev->srq_tbl[srq->srq_handle] = NULL;
237 spin_unlock_irqrestore(&dev->srq_tbl_lock, flags);
238
239 refcount_dec(&srq->refcnt);
240 wait_event(srq->wait, !refcount_read(&srq->refcnt));
241
242 /* There is no support for kernel clients, so this is safe. */
243 ib_umem_release(srq->umem);
244
245 pvrdma_page_dir_cleanup(dev, &srq->pdir);
246
247 kfree(srq);
248
249 atomic_dec(&dev->num_srqs);
250}
251
252/**
253 * pvrdma_destroy_srq - destroy shared receive queue
254 * @srq: the shared receive queue to destroy
255 *
256 * @return: 0 for success.
257 */
258int pvrdma_destroy_srq(struct ib_srq *srq)
259{
260 struct pvrdma_srq *vsrq = to_vsrq(srq);
261 union pvrdma_cmd_req req;
262 struct pvrdma_cmd_destroy_srq *cmd = &req.destroy_srq;
263 struct pvrdma_dev *dev = to_vdev(srq->device);
264 int ret;
265
266 memset(cmd, 0, sizeof(*cmd));
267 cmd->hdr.cmd = PVRDMA_CMD_DESTROY_SRQ;
268 cmd->srq_handle = vsrq->srq_handle;
269
270 ret = pvrdma_cmd_post(dev, &req, NULL, 0);
271 if (ret < 0)
272 dev_warn(&dev->pdev->dev,
273 "destroy shared receive queue failed, error: %d\n",
274 ret);
275
276 pvrdma_free_srq(dev, vsrq);
277
278 return 0;
279}
280
281/**
282 * pvrdma_modify_srq - modify shared receive queue attributes
283 * @ibsrq: the shared receive queue to modify
284 * @attr: the shared receive queue's new attributes
285 * @attr_mask: attributes mask
286 * @udata: user data
287 *
288 * @returns 0 on success, otherwise returns an errno.
289 */
290int pvrdma_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
291 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
292{
293 struct pvrdma_srq *vsrq = to_vsrq(ibsrq);
294 union pvrdma_cmd_req req;
295 struct pvrdma_cmd_modify_srq *cmd = &req.modify_srq;
296 struct pvrdma_dev *dev = to_vdev(ibsrq->device);
297 int ret;
298
299 /* Only support SRQ limit. */
300 if (!(attr_mask & IB_SRQ_LIMIT))
301 return -EINVAL;
302
303 memset(cmd, 0, sizeof(*cmd));
304 cmd->hdr.cmd = PVRDMA_CMD_MODIFY_SRQ;
305 cmd->srq_handle = vsrq->srq_handle;
306 cmd->attrs.srq_limit = attr->srq_limit;
307 cmd->attr_mask = attr_mask;
308
309 ret = pvrdma_cmd_post(dev, &req, NULL, 0);
310 if (ret < 0) {
311 dev_warn(&dev->pdev->dev,
312 "could not modify shared receive queue, error: %d\n",
313 ret);
314
315 return -EINVAL;
316 }
317
318 return ret;
319}
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c
index 48776f5ffb0e..16b96616ef7e 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c
@@ -85,6 +85,9 @@ int pvrdma_query_device(struct ib_device *ibdev,
85 props->max_sge = dev->dsr->caps.max_sge; 85 props->max_sge = dev->dsr->caps.max_sge;
86 props->max_sge_rd = PVRDMA_GET_CAP(dev, dev->dsr->caps.max_sge, 86 props->max_sge_rd = PVRDMA_GET_CAP(dev, dev->dsr->caps.max_sge,
87 dev->dsr->caps.max_sge_rd); 87 dev->dsr->caps.max_sge_rd);
88 props->max_srq = dev->dsr->caps.max_srq;
89 props->max_srq_wr = dev->dsr->caps.max_srq_wr;
90 props->max_srq_sge = dev->dsr->caps.max_srq_sge;
88 props->max_cq = dev->dsr->caps.max_cq; 91 props->max_cq = dev->dsr->caps.max_cq;
89 props->max_cqe = dev->dsr->caps.max_cqe; 92 props->max_cqe = dev->dsr->caps.max_cqe;
90 props->max_mr = dev->dsr->caps.max_mr; 93 props->max_mr = dev->dsr->caps.max_mr;
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
index 002a9b066e70..b7b25728a7e5 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
@@ -324,6 +324,13 @@ enum pvrdma_mw_type {
324 PVRDMA_MW_TYPE_2 = 2, 324 PVRDMA_MW_TYPE_2 = 2,
325}; 325};
326 326
327struct pvrdma_srq_attr {
328 u32 max_wr;
329 u32 max_sge;
330 u32 srq_limit;
331 u32 reserved;
332};
333
327struct pvrdma_qp_attr { 334struct pvrdma_qp_attr {
328 enum pvrdma_qp_state qp_state; 335 enum pvrdma_qp_state qp_state;
329 enum pvrdma_qp_state cur_qp_state; 336 enum pvrdma_qp_state cur_qp_state;
@@ -420,6 +427,17 @@ int pvrdma_req_notify_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
420struct ib_ah *pvrdma_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, 427struct ib_ah *pvrdma_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr,
421 struct ib_udata *udata); 428 struct ib_udata *udata);
422int pvrdma_destroy_ah(struct ib_ah *ah); 429int pvrdma_destroy_ah(struct ib_ah *ah);
430
431struct ib_srq *pvrdma_create_srq(struct ib_pd *pd,
432 struct ib_srq_init_attr *init_attr,
433 struct ib_udata *udata);
434int pvrdma_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
435 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
436int pvrdma_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
437int pvrdma_destroy_srq(struct ib_srq *srq);
438int pvrdma_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
439 struct ib_recv_wr **bad_wr);
440
423struct ib_qp *pvrdma_create_qp(struct ib_pd *pd, 441struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
424 struct ib_qp_init_attr *init_attr, 442 struct ib_qp_init_attr *init_attr,
425 struct ib_udata *udata); 443 struct ib_udata *udata);
diff --git a/drivers/infiniband/sw/rdmavt/Kconfig b/drivers/infiniband/sw/rdmavt/Kconfig
index fdd001ce13d8..2b5513da7e83 100644
--- a/drivers/infiniband/sw/rdmavt/Kconfig
+++ b/drivers/infiniband/sw/rdmavt/Kconfig
@@ -1,6 +1,7 @@
1config INFINIBAND_RDMAVT 1config INFINIBAND_RDMAVT
2 tristate "RDMA verbs transport library" 2 tristate "RDMA verbs transport library"
3 depends on 64BIT 3 depends on 64BIT
4 depends on PCI
4 select DMA_VIRT_OPS 5 select DMA_VIRT_OPS
5 ---help--- 6 ---help---
6 This is a common software verbs provider for RDMA networks. 7 This is a common software verbs provider for RDMA networks.
diff --git a/drivers/infiniband/sw/rdmavt/mcast.c b/drivers/infiniband/sw/rdmavt/mcast.c
index 1f12b69a0d07..b3a38c5e4cad 100644
--- a/drivers/infiniband/sw/rdmavt/mcast.c
+++ b/drivers/infiniband/sw/rdmavt/mcast.c
@@ -351,7 +351,7 @@ int rvt_detach_mcast(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
351 int last = 0; 351 int last = 0;
352 int ret = 0; 352 int ret = 0;
353 353
354 if (ibqp->qp_num <= 1 || qp->state == IB_QPS_RESET) 354 if (ibqp->qp_num <= 1)
355 return -EINVAL; 355 return -EINVAL;
356 356
357 spin_lock_irq(&ibp->lock); 357 spin_lock_irq(&ibp->lock);
diff --git a/drivers/infiniband/sw/rdmavt/qp.c b/drivers/infiniband/sw/rdmavt/qp.c
index b670cb9d2006..410025a19729 100644
--- a/drivers/infiniband/sw/rdmavt/qp.c
+++ b/drivers/infiniband/sw/rdmavt/qp.c
@@ -57,7 +57,7 @@
57#include "vt.h" 57#include "vt.h"
58#include "trace.h" 58#include "trace.h"
59 59
60static void rvt_rc_timeout(unsigned long arg); 60static void rvt_rc_timeout(struct timer_list *t);
61 61
62/* 62/*
63 * Convert the AETH RNR timeout code into the number of microseconds. 63 * Convert the AETH RNR timeout code into the number of microseconds.
@@ -717,7 +717,6 @@ static void rvt_reset_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp,
717 717
718 /* take qp out the hash and wait for it to be unused */ 718 /* take qp out the hash and wait for it to be unused */
719 rvt_remove_qp(rdi, qp); 719 rvt_remove_qp(rdi, qp);
720 wait_event(qp->wait, !atomic_read(&qp->refcount));
721 720
722 /* grab the lock b/c it was locked at call time */ 721 /* grab the lock b/c it was locked at call time */
723 spin_lock_irq(&qp->r_lock); 722 spin_lock_irq(&qp->r_lock);
@@ -807,6 +806,7 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd,
807 if (init_attr->port_num == 0 || 806 if (init_attr->port_num == 0 ||
808 init_attr->port_num > ibpd->device->phys_port_cnt) 807 init_attr->port_num > ibpd->device->phys_port_cnt)
809 return ERR_PTR(-EINVAL); 808 return ERR_PTR(-EINVAL);
809 /* fall through */
810 case IB_QPT_UC: 810 case IB_QPT_UC:
811 case IB_QPT_RC: 811 case IB_QPT_RC:
812 case IB_QPT_UD: 812 case IB_QPT_UD:
@@ -845,7 +845,7 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd,
845 goto bail_qp; 845 goto bail_qp;
846 } 846 }
847 /* initialize timers needed for rc qp */ 847 /* initialize timers needed for rc qp */
848 setup_timer(&qp->s_timer, rvt_rc_timeout, (unsigned long)qp); 848 timer_setup(&qp->s_timer, rvt_rc_timeout, 0);
849 hrtimer_init(&qp->s_rnr_timer, CLOCK_MONOTONIC, 849 hrtimer_init(&qp->s_rnr_timer, CLOCK_MONOTONIC,
850 HRTIMER_MODE_REL); 850 HRTIMER_MODE_REL);
851 qp->s_rnr_timer.function = rvt_rc_rnr_retry; 851 qp->s_rnr_timer.function = rvt_rc_rnr_retry;
@@ -894,8 +894,6 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd,
894 atomic_set(&qp->refcount, 0); 894 atomic_set(&qp->refcount, 0);
895 atomic_set(&qp->local_ops_pending, 0); 895 atomic_set(&qp->local_ops_pending, 0);
896 init_waitqueue_head(&qp->wait); 896 init_waitqueue_head(&qp->wait);
897 init_timer(&qp->s_timer);
898 qp->s_timer.data = (unsigned long)qp;
899 INIT_LIST_HEAD(&qp->rspwait); 897 INIT_LIST_HEAD(&qp->rspwait);
900 qp->state = IB_QPS_RESET; 898 qp->state = IB_QPS_RESET;
901 qp->s_wq = swq; 899 qp->s_wq = swq;
@@ -1443,6 +1441,7 @@ int rvt_destroy_qp(struct ib_qp *ibqp)
1443 spin_unlock(&qp->s_hlock); 1441 spin_unlock(&qp->s_hlock);
1444 spin_unlock_irq(&qp->r_lock); 1442 spin_unlock_irq(&qp->r_lock);
1445 1443
1444 wait_event(qp->wait, !atomic_read(&qp->refcount));
1446 /* qpn is now available for use again */ 1445 /* qpn is now available for use again */
1447 rvt_free_qpn(&rdi->qp_dev->qpn_table, qp->ibqp.qp_num); 1446 rvt_free_qpn(&rdi->qp_dev->qpn_table, qp->ibqp.qp_num);
1448 1447
@@ -2132,9 +2131,9 @@ EXPORT_SYMBOL(rvt_del_timers_sync);
2132/** 2131/**
2133 * This is called from s_timer for missing responses. 2132 * This is called from s_timer for missing responses.
2134 */ 2133 */
2135static void rvt_rc_timeout(unsigned long arg) 2134static void rvt_rc_timeout(struct timer_list *t)
2136{ 2135{
2137 struct rvt_qp *qp = (struct rvt_qp *)arg; 2136 struct rvt_qp *qp = from_timer(qp, t, s_timer);
2138 struct rvt_dev_info *rdi = ib_to_rvt(qp->ibqp.device); 2137 struct rvt_dev_info *rdi = ib_to_rvt(qp->ibqp.device);
2139 unsigned long flags; 2138 unsigned long flags;
2140 2139
diff --git a/drivers/infiniband/sw/rxe/rxe_comp.c b/drivers/infiniband/sw/rxe/rxe_comp.c
index 9eb12c2e3c74..6cdc40ed8a9f 100644
--- a/drivers/infiniband/sw/rxe/rxe_comp.c
+++ b/drivers/infiniband/sw/rxe/rxe_comp.c
@@ -136,9 +136,9 @@ static enum ib_wc_opcode wr_to_wc_opcode(enum ib_wr_opcode opcode)
136 } 136 }
137} 137}
138 138
139void retransmit_timer(unsigned long data) 139void retransmit_timer(struct timer_list *t)
140{ 140{
141 struct rxe_qp *qp = (struct rxe_qp *)data; 141 struct rxe_qp *qp = from_timer(qp, t, retrans_timer);
142 142
143 if (qp->valid) { 143 if (qp->valid) {
144 qp->comp.timeout = 1; 144 qp->comp.timeout = 1;
@@ -270,8 +270,8 @@ static inline enum comp_state check_ack(struct rxe_qp *qp,
270 if ((syn & AETH_TYPE_MASK) != AETH_ACK) 270 if ((syn & AETH_TYPE_MASK) != AETH_ACK)
271 return COMPST_ERROR; 271 return COMPST_ERROR;
272 272
273 /* Fall through (IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE 273 /* fall through */
274 * doesn't have an AETH) 274 /* (IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE doesn't have an AETH)
275 */ 275 */
276 case IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE: 276 case IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE:
277 if (wqe->wr.opcode != IB_WR_RDMA_READ && 277 if (wqe->wr.opcode != IB_WR_RDMA_READ &&
diff --git a/drivers/infiniband/sw/rxe/rxe_loc.h b/drivers/infiniband/sw/rxe/rxe_loc.h
index 77b3ed0df936..d7472a442a2c 100644
--- a/drivers/infiniband/sw/rxe/rxe_loc.h
+++ b/drivers/infiniband/sw/rxe/rxe_loc.h
@@ -218,8 +218,8 @@ static inline void rxe_advance_resp_resource(struct rxe_qp *qp)
218 qp->resp.res_head = 0; 218 qp->resp.res_head = 0;
219} 219}
220 220
221void retransmit_timer(unsigned long data); 221void retransmit_timer(struct timer_list *t);
222void rnr_nak_timer(unsigned long data); 222void rnr_nak_timer(struct timer_list *t);
223 223
224/* rxe_srq.c */ 224/* rxe_srq.c */
225#define IB_SRQ_INIT_MASK (~IB_SRQ_LIMIT) 225#define IB_SRQ_INIT_MASK (~IB_SRQ_LIMIT)
diff --git a/drivers/infiniband/sw/rxe/rxe_pool.c b/drivers/infiniband/sw/rxe/rxe_pool.c
index c1b5f38f31a5..b4a8acc7bb7d 100644
--- a/drivers/infiniband/sw/rxe/rxe_pool.c
+++ b/drivers/infiniband/sw/rxe/rxe_pool.c
@@ -394,21 +394,25 @@ void *rxe_alloc(struct rxe_pool *pool)
394 394
395 kref_get(&pool->rxe->ref_cnt); 395 kref_get(&pool->rxe->ref_cnt);
396 396
397 if (atomic_inc_return(&pool->num_elem) > pool->max_elem) { 397 if (atomic_inc_return(&pool->num_elem) > pool->max_elem)
398 atomic_dec(&pool->num_elem); 398 goto out_put_pool;
399 rxe_dev_put(pool->rxe);
400 rxe_pool_put(pool);
401 return NULL;
402 }
403 399
404 elem = kmem_cache_zalloc(pool_cache(pool), 400 elem = kmem_cache_zalloc(pool_cache(pool),
405 (pool->flags & RXE_POOL_ATOMIC) ? 401 (pool->flags & RXE_POOL_ATOMIC) ?
406 GFP_ATOMIC : GFP_KERNEL); 402 GFP_ATOMIC : GFP_KERNEL);
403 if (!elem)
404 goto out_put_pool;
407 405
408 elem->pool = pool; 406 elem->pool = pool;
409 kref_init(&elem->ref_cnt); 407 kref_init(&elem->ref_cnt);
410 408
411 return elem; 409 return elem;
410
411out_put_pool:
412 atomic_dec(&pool->num_elem);
413 rxe_dev_put(pool->rxe);
414 rxe_pool_put(pool);
415 return NULL;
412} 416}
413 417
414void rxe_elem_release(struct kref *kref) 418void rxe_elem_release(struct kref *kref)
diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c
index 00bda9380a2e..4469592b839d 100644
--- a/drivers/infiniband/sw/rxe/rxe_qp.c
+++ b/drivers/infiniband/sw/rxe/rxe_qp.c
@@ -275,8 +275,8 @@ static int rxe_qp_init_req(struct rxe_dev *rxe, struct rxe_qp *qp,
275 275
276 qp->qp_timeout_jiffies = 0; /* Can't be set for UD/UC in modify_qp */ 276 qp->qp_timeout_jiffies = 0; /* Can't be set for UD/UC in modify_qp */
277 if (init->qp_type == IB_QPT_RC) { 277 if (init->qp_type == IB_QPT_RC) {
278 setup_timer(&qp->rnr_nak_timer, rnr_nak_timer, (unsigned long)qp); 278 timer_setup(&qp->rnr_nak_timer, rnr_nak_timer, 0);
279 setup_timer(&qp->retrans_timer, retransmit_timer, (unsigned long)qp); 279 timer_setup(&qp->retrans_timer, retransmit_timer, 0);
280 } 280 }
281 return 0; 281 return 0;
282} 282}
diff --git a/drivers/infiniband/sw/rxe/rxe_req.c b/drivers/infiniband/sw/rxe/rxe_req.c
index d84222f9d5d2..26a7f923045b 100644
--- a/drivers/infiniband/sw/rxe/rxe_req.c
+++ b/drivers/infiniband/sw/rxe/rxe_req.c
@@ -118,9 +118,9 @@ static void req_retry(struct rxe_qp *qp)
118 } 118 }
119} 119}
120 120
121void rnr_nak_timer(unsigned long data) 121void rnr_nak_timer(struct timer_list *t)
122{ 122{
123 struct rxe_qp *qp = (struct rxe_qp *)data; 123 struct rxe_qp *qp = from_timer(qp, t, rnr_nak_timer);
124 124
125 pr_debug("qp#%d rnr nak timer fired\n", qp_num(qp)); 125 pr_debug("qp#%d rnr nak timer fired\n", qp_num(qp));
126 rxe_run_task(&qp->req.task, 1); 126 rxe_run_task(&qp->req.task, 1);
diff --git a/drivers/infiniband/sw/rxe/rxe_task.c b/drivers/infiniband/sw/rxe/rxe_task.c
index ea3810b29273..08f05ac5f5d5 100644
--- a/drivers/infiniband/sw/rxe/rxe_task.c
+++ b/drivers/infiniband/sw/rxe/rxe_task.c
@@ -71,7 +71,7 @@ void rxe_do_task(unsigned long data)
71 71
72 case TASK_STATE_BUSY: 72 case TASK_STATE_BUSY:
73 task->state = TASK_STATE_ARMED; 73 task->state = TASK_STATE_ARMED;
74 /* fall through to */ 74 /* fall through */
75 case TASK_STATE_ARMED: 75 case TASK_STATE_ARMED:
76 spin_unlock_irqrestore(&task->state_lock, flags); 76 spin_unlock_irqrestore(&task->state_lock, flags);
77 return; 77 return;
diff --git a/drivers/infiniband/sw/rxe/rxe_verbs.c b/drivers/infiniband/sw/rxe/rxe_verbs.c
index 0b362f49a10a..d03002b9d84d 100644
--- a/drivers/infiniband/sw/rxe/rxe_verbs.c
+++ b/drivers/infiniband/sw/rxe/rxe_verbs.c
@@ -644,6 +644,7 @@ static void init_send_wr(struct rxe_qp *qp, struct rxe_send_wr *wr,
644 switch (wr->opcode) { 644 switch (wr->opcode) {
645 case IB_WR_RDMA_WRITE_WITH_IMM: 645 case IB_WR_RDMA_WRITE_WITH_IMM:
646 wr->ex.imm_data = ibwr->ex.imm_data; 646 wr->ex.imm_data = ibwr->ex.imm_data;
647 /* fall through */
647 case IB_WR_RDMA_READ: 648 case IB_WR_RDMA_READ:
648 case IB_WR_RDMA_WRITE: 649 case IB_WR_RDMA_WRITE:
649 wr->wr.rdma.remote_addr = rdma_wr(ibwr)->remote_addr; 650 wr->wr.rdma.remote_addr = rdma_wr(ibwr)->remote_addr;
@@ -1191,6 +1192,7 @@ int rxe_register_device(struct rxe_dev *rxe)
1191 int err; 1192 int err;
1192 int i; 1193 int i;
1193 struct ib_device *dev = &rxe->ib_dev; 1194 struct ib_device *dev = &rxe->ib_dev;
1195 struct crypto_shash *tfm;
1194 1196
1195 strlcpy(dev->name, "rxe%d", IB_DEVICE_NAME_MAX); 1197 strlcpy(dev->name, "rxe%d", IB_DEVICE_NAME_MAX);
1196 strlcpy(dev->node_desc, "rxe", sizeof(dev->node_desc)); 1198 strlcpy(dev->node_desc, "rxe", sizeof(dev->node_desc));
@@ -1288,12 +1290,13 @@ int rxe_register_device(struct rxe_dev *rxe)
1288 dev->get_hw_stats = rxe_ib_get_hw_stats; 1290 dev->get_hw_stats = rxe_ib_get_hw_stats;
1289 dev->alloc_hw_stats = rxe_ib_alloc_hw_stats; 1291 dev->alloc_hw_stats = rxe_ib_alloc_hw_stats;
1290 1292
1291 rxe->tfm = crypto_alloc_shash("crc32", 0, 0); 1293 tfm = crypto_alloc_shash("crc32", 0, 0);
1292 if (IS_ERR(rxe->tfm)) { 1294 if (IS_ERR(tfm)) {
1293 pr_err("failed to allocate crc algorithm err:%ld\n", 1295 pr_err("failed to allocate crc algorithm err:%ld\n",
1294 PTR_ERR(rxe->tfm)); 1296 PTR_ERR(tfm));
1295 return PTR_ERR(rxe->tfm); 1297 return PTR_ERR(tfm);
1296 } 1298 }
1299 rxe->tfm = tfm;
1297 1300
1298 err = ib_register_device(dev, NULL); 1301 err = ib_register_device(dev, NULL);
1299 if (err) { 1302 if (err) {
diff --git a/drivers/infiniband/ulp/ipoib/ipoib.h b/drivers/infiniband/ulp/ipoib/ipoib.h
index 4a5c7a07a631..8033a006277f 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib.h
+++ b/drivers/infiniband/ulp/ipoib/ipoib.h
@@ -111,7 +111,7 @@ enum {
111 IPOIB_MCAST_FLAG_BUSY = 2, 111 IPOIB_MCAST_FLAG_BUSY = 2,
112 IPOIB_MCAST_FLAG_ATTACHED = 3, 112 IPOIB_MCAST_FLAG_ATTACHED = 3,
113 113
114 MAX_SEND_CQE = 16, 114 MAX_SEND_CQE = 64,
115 IPOIB_CM_COPYBREAK = 256, 115 IPOIB_CM_COPYBREAK = 256,
116 116
117 IPOIB_NON_CHILD = 0, 117 IPOIB_NON_CHILD = 0,
@@ -331,7 +331,8 @@ struct ipoib_dev_priv {
331 331
332 struct net_device *dev; 332 struct net_device *dev;
333 333
334 struct napi_struct napi; 334 struct napi_struct send_napi;
335 struct napi_struct recv_napi;
335 336
336 unsigned long flags; 337 unsigned long flags;
337 338
@@ -381,7 +382,6 @@ struct ipoib_dev_priv {
381 unsigned tx_tail; 382 unsigned tx_tail;
382 struct ib_sge tx_sge[MAX_SKB_FRAGS + 1]; 383 struct ib_sge tx_sge[MAX_SKB_FRAGS + 1];
383 struct ib_ud_wr tx_wr; 384 struct ib_ud_wr tx_wr;
384 unsigned tx_outstanding;
385 struct ib_wc send_wc[MAX_SEND_CQE]; 385 struct ib_wc send_wc[MAX_SEND_CQE];
386 386
387 struct ib_recv_wr rx_wr; 387 struct ib_recv_wr rx_wr;
@@ -409,7 +409,6 @@ struct ipoib_dev_priv {
409#endif 409#endif
410 u64 hca_caps; 410 u64 hca_caps;
411 struct ipoib_ethtool_st ethtool; 411 struct ipoib_ethtool_st ethtool;
412 struct timer_list poll_timer;
413 unsigned max_send_sge; 412 unsigned max_send_sge;
414 bool sm_fullmember_sendonly_support; 413 bool sm_fullmember_sendonly_support;
415 const struct net_device_ops *rn_ops; 414 const struct net_device_ops *rn_ops;
@@ -476,9 +475,10 @@ extern struct workqueue_struct *ipoib_workqueue;
476 475
477/* functions */ 476/* functions */
478 477
479int ipoib_poll(struct napi_struct *napi, int budget); 478int ipoib_rx_poll(struct napi_struct *napi, int budget);
480void ipoib_ib_completion(struct ib_cq *cq, void *dev_ptr); 479int ipoib_tx_poll(struct napi_struct *napi, int budget);
481void ipoib_send_comp_handler(struct ib_cq *cq, void *dev_ptr); 480void ipoib_ib_rx_completion(struct ib_cq *cq, void *ctx_ptr);
481void ipoib_ib_tx_completion(struct ib_cq *cq, void *ctx_ptr);
482 482
483struct ipoib_ah *ipoib_create_ah(struct net_device *dev, 483struct ipoib_ah *ipoib_create_ah(struct net_device *dev,
484 struct ib_pd *pd, struct rdma_ah_attr *attr); 484 struct ib_pd *pd, struct rdma_ah_attr *attr);
@@ -500,7 +500,7 @@ void ipoib_mark_paths_invalid(struct net_device *dev);
500void ipoib_flush_paths(struct net_device *dev); 500void ipoib_flush_paths(struct net_device *dev);
501struct ipoib_dev_priv *ipoib_intf_alloc(struct ib_device *hca, u8 port, 501struct ipoib_dev_priv *ipoib_intf_alloc(struct ib_device *hca, u8 port,
502 const char *format); 502 const char *format);
503void ipoib_ib_tx_timer_func(unsigned long ctx); 503void ipoib_ib_tx_timer_func(struct timer_list *t);
504void ipoib_ib_dev_flush_light(struct work_struct *work); 504void ipoib_ib_dev_flush_light(struct work_struct *work);
505void ipoib_ib_dev_flush_normal(struct work_struct *work); 505void ipoib_ib_dev_flush_normal(struct work_struct *work);
506void ipoib_ib_dev_flush_heavy(struct work_struct *work); 506void ipoib_ib_dev_flush_heavy(struct work_struct *work);
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c
index 7774654c2ccb..87f4bd99cdf7 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c
@@ -594,9 +594,9 @@ void ipoib_cm_handle_rx_wc(struct net_device *dev, struct ib_wc *wc)
594 skb = rx_ring[wr_id].skb; 594 skb = rx_ring[wr_id].skb;
595 595
596 if (unlikely(wc->status != IB_WC_SUCCESS)) { 596 if (unlikely(wc->status != IB_WC_SUCCESS)) {
597 ipoib_dbg(priv, "cm recv error " 597 ipoib_dbg(priv,
598 "(status=%d, wrid=%d vend_err %x)\n", 598 "cm recv error (status=%d, wrid=%d vend_err %#x)\n",
599 wc->status, wr_id, wc->vendor_err); 599 wc->status, wr_id, wc->vendor_err);
600 ++dev->stats.rx_dropped; 600 ++dev->stats.rx_dropped;
601 if (has_srq) 601 if (has_srq)
602 goto repost; 602 goto repost;
@@ -757,30 +757,35 @@ void ipoib_cm_send(struct net_device *dev, struct sk_buff *skb, struct ipoib_cm_
757 return; 757 return;
758 } 758 }
759 759
760 if ((priv->tx_head - priv->tx_tail) == ipoib_sendq_size - 1) {
761 ipoib_dbg(priv, "TX ring 0x%x full, stopping kernel net queue\n",
762 tx->qp->qp_num);
763 netif_stop_queue(dev);
764 }
765
760 skb_orphan(skb); 766 skb_orphan(skb);
761 skb_dst_drop(skb); 767 skb_dst_drop(skb);
762 768
769 if (netif_queue_stopped(dev))
770 if (ib_req_notify_cq(priv->send_cq, IB_CQ_NEXT_COMP |
771 IB_CQ_REPORT_MISSED_EVENTS)) {
772 ipoib_warn(priv, "IPoIB/CM:request notify on send CQ failed\n");
773 napi_schedule(&priv->send_napi);
774 }
775
763 rc = post_send(priv, tx, tx->tx_head & (ipoib_sendq_size - 1), tx_req); 776 rc = post_send(priv, tx, tx->tx_head & (ipoib_sendq_size - 1), tx_req);
764 if (unlikely(rc)) { 777 if (unlikely(rc)) {
765 ipoib_warn(priv, "post_send failed, error %d\n", rc); 778 ipoib_warn(priv, "IPoIB/CM:post_send failed, error %d\n", rc);
766 ++dev->stats.tx_errors; 779 ++dev->stats.tx_errors;
767 ipoib_dma_unmap_tx(priv, tx_req); 780 ipoib_dma_unmap_tx(priv, tx_req);
768 dev_kfree_skb_any(skb); 781 dev_kfree_skb_any(skb);
782
783 if (netif_queue_stopped(dev))
784 netif_wake_queue(dev);
769 } else { 785 } else {
770 netif_trans_update(dev); 786 netif_trans_update(dev);
771 ++tx->tx_head; 787 ++tx->tx_head;
772 788 ++priv->tx_head;
773 if (++priv->tx_outstanding == ipoib_sendq_size) {
774 ipoib_dbg(priv, "TX ring 0x%x full, stopping kernel net queue\n",
775 tx->qp->qp_num);
776 netif_stop_queue(dev);
777 rc = ib_req_notify_cq(priv->send_cq,
778 IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
779 if (rc < 0)
780 ipoib_warn(priv, "request notify on send CQ failed\n");
781 else if (rc)
782 ipoib_send_comp_handler(priv->send_cq, dev);
783 }
784 } 789 }
785} 790}
786 791
@@ -814,9 +819,11 @@ void ipoib_cm_handle_tx_wc(struct net_device *dev, struct ib_wc *wc)
814 netif_tx_lock(dev); 819 netif_tx_lock(dev);
815 820
816 ++tx->tx_tail; 821 ++tx->tx_tail;
817 if (unlikely(--priv->tx_outstanding == ipoib_sendq_size >> 1) && 822 ++priv->tx_tail;
818 netif_queue_stopped(dev) && 823
819 test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)) 824 if (unlikely(netif_queue_stopped(dev) &&
825 (priv->tx_head - priv->tx_tail) <= ipoib_sendq_size >> 1 &&
826 test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)))
820 netif_wake_queue(dev); 827 netif_wake_queue(dev);
821 828
822 if (wc->status != IB_WC_SUCCESS && 829 if (wc->status != IB_WC_SUCCESS &&
@@ -829,11 +836,11 @@ void ipoib_cm_handle_tx_wc(struct net_device *dev, struct ib_wc *wc)
829 if (wc->status == IB_WC_RNR_RETRY_EXC_ERR || 836 if (wc->status == IB_WC_RNR_RETRY_EXC_ERR ||
830 wc->status == IB_WC_RETRY_EXC_ERR) 837 wc->status == IB_WC_RETRY_EXC_ERR)
831 ipoib_dbg(priv, 838 ipoib_dbg(priv,
832 "%s: failed cm send event (status=%d, wrid=%d vend_err 0x%x)\n", 839 "%s: failed cm send event (status=%d, wrid=%d vend_err %#x)\n",
833 __func__, wc->status, wr_id, wc->vendor_err); 840 __func__, wc->status, wr_id, wc->vendor_err);
834 else 841 else
835 ipoib_warn(priv, 842 ipoib_warn(priv,
836 "%s: failed cm send event (status=%d, wrid=%d vend_err 0x%x)\n", 843 "%s: failed cm send event (status=%d, wrid=%d vend_err %#x)\n",
837 __func__, wc->status, wr_id, wc->vendor_err); 844 __func__, wc->status, wr_id, wc->vendor_err);
838 845
839 spin_lock_irqsave(&priv->lock, flags); 846 spin_lock_irqsave(&priv->lock, flags);
@@ -1045,7 +1052,7 @@ static struct ib_qp *ipoib_cm_create_tx_qp(struct net_device *dev, struct ipoib_
1045{ 1052{
1046 struct ipoib_dev_priv *priv = ipoib_priv(dev); 1053 struct ipoib_dev_priv *priv = ipoib_priv(dev);
1047 struct ib_qp_init_attr attr = { 1054 struct ib_qp_init_attr attr = {
1048 .send_cq = priv->recv_cq, 1055 .send_cq = priv->send_cq,
1049 .recv_cq = priv->recv_cq, 1056 .recv_cq = priv->recv_cq,
1050 .srq = priv->cm.srq, 1057 .srq = priv->cm.srq,
1051 .cap.max_send_wr = ipoib_sendq_size, 1058 .cap.max_send_wr = ipoib_sendq_size,
@@ -1219,9 +1226,10 @@ timeout:
1219 tx_req = &p->tx_ring[p->tx_tail & (ipoib_sendq_size - 1)]; 1226 tx_req = &p->tx_ring[p->tx_tail & (ipoib_sendq_size - 1)];
1220 ipoib_dma_unmap_tx(priv, tx_req); 1227 ipoib_dma_unmap_tx(priv, tx_req);
1221 dev_kfree_skb_any(tx_req->skb); 1228 dev_kfree_skb_any(tx_req->skb);
1222 ++p->tx_tail;
1223 netif_tx_lock_bh(p->dev); 1229 netif_tx_lock_bh(p->dev);
1224 if (unlikely(--priv->tx_outstanding == ipoib_sendq_size >> 1) && 1230 ++p->tx_tail;
1231 ++priv->tx_tail;
1232 if (unlikely(priv->tx_head - priv->tx_tail == ipoib_sendq_size >> 1) &&
1225 netif_queue_stopped(p->dev) && 1233 netif_queue_stopped(p->dev) &&
1226 test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)) 1234 test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags))
1227 netif_wake_queue(p->dev); 1235 netif_wake_queue(p->dev);
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_ethtool.c b/drivers/infiniband/ulp/ipoib/ipoib_ethtool.c
index 8dc1e6225cc8..2706bf26cbac 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_ethtool.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_ethtool.c
@@ -99,8 +99,9 @@ static int ipoib_set_coalesce(struct net_device *dev,
99 coal->rx_max_coalesced_frames > 0xffff) 99 coal->rx_max_coalesced_frames > 0xffff)
100 return -EINVAL; 100 return -EINVAL;
101 101
102 ret = ib_modify_cq(priv->recv_cq, coal->rx_max_coalesced_frames, 102 ret = rdma_set_cq_moderation(priv->recv_cq,
103 coal->rx_coalesce_usecs); 103 coal->rx_max_coalesced_frames,
104 coal->rx_coalesce_usecs);
104 if (ret && ret != -ENOSYS) { 105 if (ret && ret != -ENOSYS) {
105 ipoib_warn(priv, "failed modifying CQ (%d)\n", ret); 106 ipoib_warn(priv, "failed modifying CQ (%d)\n", ret);
106 return ret; 107 return ret;
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_ib.c b/drivers/infiniband/ulp/ipoib/ipoib_ib.c
index fe690f82af29..3b96cdaf9a83 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_ib.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_ib.c
@@ -192,8 +192,8 @@ static void ipoib_ib_handle_rx_wc(struct net_device *dev, struct ib_wc *wc)
192 192
193 if (unlikely(wc->status != IB_WC_SUCCESS)) { 193 if (unlikely(wc->status != IB_WC_SUCCESS)) {
194 if (wc->status != IB_WC_WR_FLUSH_ERR) 194 if (wc->status != IB_WC_WR_FLUSH_ERR)
195 ipoib_warn(priv, "failed recv event " 195 ipoib_warn(priv,
196 "(status=%d, wrid=%d vend_err %x)\n", 196 "failed recv event (status=%d, wrid=%d vend_err %#x)\n",
197 wc->status, wr_id, wc->vendor_err); 197 wc->status, wr_id, wc->vendor_err);
198 ipoib_ud_dma_unmap_rx(priv, priv->rx_ring[wr_id].mapping); 198 ipoib_ud_dma_unmap_rx(priv, priv->rx_ring[wr_id].mapping);
199 dev_kfree_skb_any(skb); 199 dev_kfree_skb_any(skb);
@@ -264,7 +264,7 @@ static void ipoib_ib_handle_rx_wc(struct net_device *dev, struct ib_wc *wc)
264 likely(wc->wc_flags & IB_WC_IP_CSUM_OK)) 264 likely(wc->wc_flags & IB_WC_IP_CSUM_OK))
265 skb->ip_summed = CHECKSUM_UNNECESSARY; 265 skb->ip_summed = CHECKSUM_UNNECESSARY;
266 266
267 napi_gro_receive(&priv->napi, skb); 267 napi_gro_receive(&priv->recv_napi, skb);
268 268
269repost: 269repost:
270 if (unlikely(ipoib_ib_post_receive(dev, wr_id))) 270 if (unlikely(ipoib_ib_post_receive(dev, wr_id)))
@@ -406,16 +406,17 @@ static void ipoib_ib_handle_tx_wc(struct net_device *dev, struct ib_wc *wc)
406 dev_kfree_skb_any(tx_req->skb); 406 dev_kfree_skb_any(tx_req->skb);
407 407
408 ++priv->tx_tail; 408 ++priv->tx_tail;
409 if (unlikely(--priv->tx_outstanding == ipoib_sendq_size >> 1) && 409
410 netif_queue_stopped(dev) && 410 if (unlikely(netif_queue_stopped(dev) &&
411 test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)) 411 ((priv->tx_head - priv->tx_tail) <= ipoib_sendq_size >> 1) &&
412 test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)))
412 netif_wake_queue(dev); 413 netif_wake_queue(dev);
413 414
414 if (wc->status != IB_WC_SUCCESS && 415 if (wc->status != IB_WC_SUCCESS &&
415 wc->status != IB_WC_WR_FLUSH_ERR) { 416 wc->status != IB_WC_WR_FLUSH_ERR) {
416 struct ipoib_qp_state_validate *qp_work; 417 struct ipoib_qp_state_validate *qp_work;
417 ipoib_warn(priv, "failed send event " 418 ipoib_warn(priv,
418 "(status=%d, wrid=%d vend_err %x)\n", 419 "failed send event (status=%d, wrid=%d vend_err %#x)\n",
419 wc->status, wr_id, wc->vendor_err); 420 wc->status, wr_id, wc->vendor_err);
420 qp_work = kzalloc(sizeof(*qp_work), GFP_ATOMIC); 421 qp_work = kzalloc(sizeof(*qp_work), GFP_ATOMIC);
421 if (!qp_work) 422 if (!qp_work)
@@ -430,17 +431,23 @@ static void ipoib_ib_handle_tx_wc(struct net_device *dev, struct ib_wc *wc)
430static int poll_tx(struct ipoib_dev_priv *priv) 431static int poll_tx(struct ipoib_dev_priv *priv)
431{ 432{
432 int n, i; 433 int n, i;
434 struct ib_wc *wc;
433 435
434 n = ib_poll_cq(priv->send_cq, MAX_SEND_CQE, priv->send_wc); 436 n = ib_poll_cq(priv->send_cq, MAX_SEND_CQE, priv->send_wc);
435 for (i = 0; i < n; ++i) 437 for (i = 0; i < n; ++i) {
436 ipoib_ib_handle_tx_wc(priv->dev, priv->send_wc + i); 438 wc = priv->send_wc + i;
437 439 if (wc->wr_id & IPOIB_OP_CM)
440 ipoib_cm_handle_tx_wc(priv->dev, priv->send_wc + i);
441 else
442 ipoib_ib_handle_tx_wc(priv->dev, priv->send_wc + i);
443 }
438 return n == MAX_SEND_CQE; 444 return n == MAX_SEND_CQE;
439} 445}
440 446
441int ipoib_poll(struct napi_struct *napi, int budget) 447int ipoib_rx_poll(struct napi_struct *napi, int budget)
442{ 448{
443 struct ipoib_dev_priv *priv = container_of(napi, struct ipoib_dev_priv, napi); 449 struct ipoib_dev_priv *priv =
450 container_of(napi, struct ipoib_dev_priv, recv_napi);
444 struct net_device *dev = priv->dev; 451 struct net_device *dev = priv->dev;
445 int done; 452 int done;
446 int t; 453 int t;
@@ -464,8 +471,9 @@ poll_more:
464 ipoib_cm_handle_rx_wc(dev, wc); 471 ipoib_cm_handle_rx_wc(dev, wc);
465 else 472 else
466 ipoib_ib_handle_rx_wc(dev, wc); 473 ipoib_ib_handle_rx_wc(dev, wc);
467 } else 474 } else {
468 ipoib_cm_handle_tx_wc(priv->dev, wc); 475 pr_warn("%s: Got unexpected wqe id\n", __func__);
476 }
469 } 477 }
470 478
471 if (n != t) 479 if (n != t)
@@ -484,33 +492,47 @@ poll_more:
484 return done; 492 return done;
485} 493}
486 494
487void ipoib_ib_completion(struct ib_cq *cq, void *dev_ptr) 495int ipoib_tx_poll(struct napi_struct *napi, int budget)
488{ 496{
489 struct net_device *dev = dev_ptr; 497 struct ipoib_dev_priv *priv = container_of(napi, struct ipoib_dev_priv,
490 struct ipoib_dev_priv *priv = ipoib_priv(dev); 498 send_napi);
499 struct net_device *dev = priv->dev;
500 int n, i;
501 struct ib_wc *wc;
491 502
492 napi_schedule(&priv->napi); 503poll_more:
493} 504 n = ib_poll_cq(priv->send_cq, MAX_SEND_CQE, priv->send_wc);
494 505
495static void drain_tx_cq(struct net_device *dev) 506 for (i = 0; i < n; i++) {
496{ 507 wc = priv->send_wc + i;
497 struct ipoib_dev_priv *priv = ipoib_priv(dev); 508 if (wc->wr_id & IPOIB_OP_CM)
509 ipoib_cm_handle_tx_wc(dev, wc);
510 else
511 ipoib_ib_handle_tx_wc(dev, wc);
512 }
498 513
499 netif_tx_lock(dev); 514 if (n < budget) {
500 while (poll_tx(priv)) 515 napi_complete(napi);
501 ; /* nothing */ 516 if (unlikely(ib_req_notify_cq(priv->send_cq, IB_CQ_NEXT_COMP |
517 IB_CQ_REPORT_MISSED_EVENTS)) &&
518 napi_reschedule(napi))
519 goto poll_more;
520 }
521 return n < 0 ? 0 : n;
522}
502 523
503 if (netif_queue_stopped(dev)) 524void ipoib_ib_rx_completion(struct ib_cq *cq, void *ctx_ptr)
504 mod_timer(&priv->poll_timer, jiffies + 1); 525{
526 struct ipoib_dev_priv *priv = ctx_ptr;
505 527
506 netif_tx_unlock(dev); 528 napi_schedule(&priv->recv_napi);
507} 529}
508 530
509void ipoib_send_comp_handler(struct ib_cq *cq, void *dev_ptr) 531void ipoib_ib_tx_completion(struct ib_cq *cq, void *ctx_ptr)
510{ 532{
511 struct ipoib_dev_priv *priv = ipoib_priv(dev_ptr); 533 struct ipoib_dev_priv *priv = ctx_ptr;
512 534
513 mod_timer(&priv->poll_timer, jiffies); 535 napi_schedule(&priv->send_napi);
514} 536}
515 537
516static inline int post_send(struct ipoib_dev_priv *priv, 538static inline int post_send(struct ipoib_dev_priv *priv,
@@ -611,23 +633,25 @@ int ipoib_send(struct net_device *dev, struct sk_buff *skb,
611 priv->tx_wr.wr.send_flags |= IB_SEND_IP_CSUM; 633 priv->tx_wr.wr.send_flags |= IB_SEND_IP_CSUM;
612 else 634 else
613 priv->tx_wr.wr.send_flags &= ~IB_SEND_IP_CSUM; 635 priv->tx_wr.wr.send_flags &= ~IB_SEND_IP_CSUM;
614 636 /* increase the tx_head after send success, but use it for queue state */
615 if (++priv->tx_outstanding == ipoib_sendq_size) { 637 if (priv->tx_head - priv->tx_tail == ipoib_sendq_size - 1) {
616 ipoib_dbg(priv, "TX ring full, stopping kernel net queue\n"); 638 ipoib_dbg(priv, "TX ring full, stopping kernel net queue\n");
617 if (ib_req_notify_cq(priv->send_cq, IB_CQ_NEXT_COMP))
618 ipoib_warn(priv, "request notify on send CQ failed\n");
619 netif_stop_queue(dev); 639 netif_stop_queue(dev);
620 } 640 }
621 641
622 skb_orphan(skb); 642 skb_orphan(skb);
623 skb_dst_drop(skb); 643 skb_dst_drop(skb);
624 644
645 if (netif_queue_stopped(dev))
646 if (ib_req_notify_cq(priv->send_cq, IB_CQ_NEXT_COMP |
647 IB_CQ_REPORT_MISSED_EVENTS))
648 ipoib_warn(priv, "request notify on send CQ failed\n");
649
625 rc = post_send(priv, priv->tx_head & (ipoib_sendq_size - 1), 650 rc = post_send(priv, priv->tx_head & (ipoib_sendq_size - 1),
626 address, dqpn, tx_req, phead, hlen); 651 address, dqpn, tx_req, phead, hlen);
627 if (unlikely(rc)) { 652 if (unlikely(rc)) {
628 ipoib_warn(priv, "post_send failed, error %d\n", rc); 653 ipoib_warn(priv, "post_send failed, error %d\n", rc);
629 ++dev->stats.tx_errors; 654 ++dev->stats.tx_errors;
630 --priv->tx_outstanding;
631 ipoib_dma_unmap_tx(priv, tx_req); 655 ipoib_dma_unmap_tx(priv, tx_req);
632 dev_kfree_skb_any(skb); 656 dev_kfree_skb_any(skb);
633 if (netif_queue_stopped(dev)) 657 if (netif_queue_stopped(dev))
@@ -639,11 +663,6 @@ int ipoib_send(struct net_device *dev, struct sk_buff *skb,
639 rc = priv->tx_head; 663 rc = priv->tx_head;
640 ++priv->tx_head; 664 ++priv->tx_head;
641 } 665 }
642
643 if (unlikely(priv->tx_outstanding > MAX_SEND_CQE))
644 while (poll_tx(priv))
645 ; /* nothing */
646
647 return rc; 666 return rc;
648} 667}
649 668
@@ -732,6 +751,22 @@ static void check_qp_movement_and_print(struct ipoib_dev_priv *priv,
732 new_state, qp_attr.qp_state); 751 new_state, qp_attr.qp_state);
733} 752}
734 753
754static void ipoib_napi_enable(struct net_device *dev)
755{
756 struct ipoib_dev_priv *priv = ipoib_priv(dev);
757
758 napi_enable(&priv->recv_napi);
759 napi_enable(&priv->send_napi);
760}
761
762static void ipoib_napi_disable(struct net_device *dev)
763{
764 struct ipoib_dev_priv *priv = ipoib_priv(dev);
765
766 napi_disable(&priv->recv_napi);
767 napi_disable(&priv->send_napi);
768}
769
735int ipoib_ib_dev_stop_default(struct net_device *dev) 770int ipoib_ib_dev_stop_default(struct net_device *dev)
736{ 771{
737 struct ipoib_dev_priv *priv = ipoib_priv(dev); 772 struct ipoib_dev_priv *priv = ipoib_priv(dev);
@@ -741,7 +776,7 @@ int ipoib_ib_dev_stop_default(struct net_device *dev)
741 int i; 776 int i;
742 777
743 if (test_bit(IPOIB_FLAG_INITIALIZED, &priv->flags)) 778 if (test_bit(IPOIB_FLAG_INITIALIZED, &priv->flags))
744 napi_disable(&priv->napi); 779 ipoib_napi_disable(dev);
745 780
746 ipoib_cm_dev_stop(dev); 781 ipoib_cm_dev_stop(dev);
747 782
@@ -773,7 +808,6 @@ int ipoib_ib_dev_stop_default(struct net_device *dev)
773 ipoib_dma_unmap_tx(priv, tx_req); 808 ipoib_dma_unmap_tx(priv, tx_req);
774 dev_kfree_skb_any(tx_req->skb); 809 dev_kfree_skb_any(tx_req->skb);
775 ++priv->tx_tail; 810 ++priv->tx_tail;
776 --priv->tx_outstanding;
777 } 811 }
778 812
779 for (i = 0; i < ipoib_recvq_size; ++i) { 813 for (i = 0; i < ipoib_recvq_size; ++i) {
@@ -799,7 +833,6 @@ int ipoib_ib_dev_stop_default(struct net_device *dev)
799 ipoib_dbg(priv, "All sends and receives done.\n"); 833 ipoib_dbg(priv, "All sends and receives done.\n");
800 834
801timeout: 835timeout:
802 del_timer_sync(&priv->poll_timer);
803 qp_attr.qp_state = IB_QPS_RESET; 836 qp_attr.qp_state = IB_QPS_RESET;
804 if (ib_modify_qp(priv->qp, &qp_attr, IB_QP_STATE)) 837 if (ib_modify_qp(priv->qp, &qp_attr, IB_QP_STATE))
805 ipoib_warn(priv, "Failed to modify QP to RESET state\n"); 838 ipoib_warn(priv, "Failed to modify QP to RESET state\n");
@@ -821,11 +854,6 @@ int ipoib_ib_dev_stop(struct net_device *dev)
821 return 0; 854 return 0;
822} 855}
823 856
824void ipoib_ib_tx_timer_func(unsigned long ctx)
825{
826 drain_tx_cq((struct net_device *)ctx);
827}
828
829int ipoib_ib_dev_open_default(struct net_device *dev) 857int ipoib_ib_dev_open_default(struct net_device *dev)
830{ 858{
831 struct ipoib_dev_priv *priv = ipoib_priv(dev); 859 struct ipoib_dev_priv *priv = ipoib_priv(dev);
@@ -850,7 +878,7 @@ int ipoib_ib_dev_open_default(struct net_device *dev)
850 } 878 }
851 879
852 if (!test_bit(IPOIB_FLAG_INITIALIZED, &priv->flags)) 880 if (!test_bit(IPOIB_FLAG_INITIALIZED, &priv->flags))
853 napi_enable(&priv->napi); 881 ipoib_napi_enable(dev);
854 882
855 return 0; 883 return 0;
856out: 884out:
@@ -965,8 +993,9 @@ void ipoib_drain_cq(struct net_device *dev)
965 ipoib_cm_handle_rx_wc(dev, priv->ibwc + i); 993 ipoib_cm_handle_rx_wc(dev, priv->ibwc + i);
966 else 994 else
967 ipoib_ib_handle_rx_wc(dev, priv->ibwc + i); 995 ipoib_ib_handle_rx_wc(dev, priv->ibwc + i);
968 } else 996 } else {
969 ipoib_cm_handle_tx_wc(dev, priv->ibwc + i); 997 pr_warn("%s: Got unexpected wqe id\n", __func__);
998 }
970 } 999 }
971 } while (n == IPOIB_NUM_WC); 1000 } while (n == IPOIB_NUM_WC);
972 1001
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
index dcc77014018d..12b7f911f0e5 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_main.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
@@ -51,7 +51,6 @@
51#include <net/addrconf.h> 51#include <net/addrconf.h>
52#include <linux/inetdevice.h> 52#include <linux/inetdevice.h>
53#include <rdma/ib_cache.h> 53#include <rdma/ib_cache.h>
54#include <linux/pci.h>
55 54
56#define DRV_VERSION "1.0.0" 55#define DRV_VERSION "1.0.0"
57 56
@@ -1617,13 +1616,29 @@ static void ipoib_neigh_hash_uninit(struct net_device *dev)
1617 wait_for_completion(&priv->ntbl.deleted); 1616 wait_for_completion(&priv->ntbl.deleted);
1618} 1617}
1619 1618
1619static void ipoib_napi_add(struct net_device *dev)
1620{
1621 struct ipoib_dev_priv *priv = ipoib_priv(dev);
1622
1623 netif_napi_add(dev, &priv->recv_napi, ipoib_rx_poll, IPOIB_NUM_WC);
1624 netif_napi_add(dev, &priv->send_napi, ipoib_tx_poll, MAX_SEND_CQE);
1625}
1626
1627static void ipoib_napi_del(struct net_device *dev)
1628{
1629 struct ipoib_dev_priv *priv = ipoib_priv(dev);
1630
1631 netif_napi_del(&priv->recv_napi);
1632 netif_napi_del(&priv->send_napi);
1633}
1634
1620static void ipoib_dev_uninit_default(struct net_device *dev) 1635static void ipoib_dev_uninit_default(struct net_device *dev)
1621{ 1636{
1622 struct ipoib_dev_priv *priv = ipoib_priv(dev); 1637 struct ipoib_dev_priv *priv = ipoib_priv(dev);
1623 1638
1624 ipoib_transport_dev_cleanup(dev); 1639 ipoib_transport_dev_cleanup(dev);
1625 1640
1626 netif_napi_del(&priv->napi); 1641 ipoib_napi_del(dev);
1627 1642
1628 ipoib_cm_dev_cleanup(dev); 1643 ipoib_cm_dev_cleanup(dev);
1629 1644
@@ -1638,7 +1653,7 @@ static int ipoib_dev_init_default(struct net_device *dev)
1638{ 1653{
1639 struct ipoib_dev_priv *priv = ipoib_priv(dev); 1654 struct ipoib_dev_priv *priv = ipoib_priv(dev);
1640 1655
1641 netif_napi_add(dev, &priv->napi, ipoib_poll, NAPI_POLL_WEIGHT); 1656 ipoib_napi_add(dev);
1642 1657
1643 /* Allocate RX/TX "rings" to hold queued skbs */ 1658 /* Allocate RX/TX "rings" to hold queued skbs */
1644 priv->rx_ring = kzalloc(ipoib_recvq_size * sizeof *priv->rx_ring, 1659 priv->rx_ring = kzalloc(ipoib_recvq_size * sizeof *priv->rx_ring,
@@ -1666,9 +1681,6 @@ static int ipoib_dev_init_default(struct net_device *dev)
1666 priv->dev->dev_addr[2] = (priv->qp->qp_num >> 8) & 0xff; 1681 priv->dev->dev_addr[2] = (priv->qp->qp_num >> 8) & 0xff;
1667 priv->dev->dev_addr[3] = (priv->qp->qp_num) & 0xff; 1682 priv->dev->dev_addr[3] = (priv->qp->qp_num) & 0xff;
1668 1683
1669 setup_timer(&priv->poll_timer, ipoib_ib_tx_timer_func,
1670 (unsigned long)dev);
1671
1672 return 0; 1684 return 0;
1673 1685
1674out_tx_ring_cleanup: 1686out_tx_ring_cleanup:
@@ -1678,7 +1690,7 @@ out_rx_ring_cleanup:
1678 kfree(priv->rx_ring); 1690 kfree(priv->rx_ring);
1679 1691
1680out: 1692out:
1681 netif_napi_del(&priv->napi); 1693 ipoib_napi_del(dev);
1682 return -ENOMEM; 1694 return -ENOMEM;
1683} 1695}
1684 1696
@@ -2314,7 +2326,8 @@ static void ipoib_add_one(struct ib_device *device)
2314 } 2326 }
2315 2327
2316 if (!count) { 2328 if (!count) {
2317 kfree(dev_list); 2329 pr_err("Failed to init port, removing it\n");
2330 ipoib_remove_one(device, dev_list);
2318 return; 2331 return;
2319 } 2332 }
2320 2333
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_verbs.c b/drivers/infiniband/ulp/ipoib/ipoib_verbs.c
index bb64baf25309..a1ed25422b72 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_verbs.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_verbs.c
@@ -156,7 +156,7 @@ int ipoib_transport_dev_init(struct net_device *dev, struct ib_device *ca)
156 }; 156 };
157 struct ib_cq_init_attr cq_attr = {}; 157 struct ib_cq_init_attr cq_attr = {};
158 158
159 int ret, size; 159 int ret, size, req_vec;
160 int i; 160 int i;
161 161
162 size = ipoib_recvq_size + 1; 162 size = ipoib_recvq_size + 1;
@@ -171,17 +171,21 @@ int ipoib_transport_dev_init(struct net_device *dev, struct ib_device *ca)
171 if (ret != -ENOSYS) 171 if (ret != -ENOSYS)
172 return -ENODEV; 172 return -ENODEV;
173 173
174 req_vec = (priv->port - 1) * 2;
175
174 cq_attr.cqe = size; 176 cq_attr.cqe = size;
175 priv->recv_cq = ib_create_cq(priv->ca, ipoib_ib_completion, NULL, 177 cq_attr.comp_vector = req_vec % priv->ca->num_comp_vectors;
176 dev, &cq_attr); 178 priv->recv_cq = ib_create_cq(priv->ca, ipoib_ib_rx_completion, NULL,
179 priv, &cq_attr);
177 if (IS_ERR(priv->recv_cq)) { 180 if (IS_ERR(priv->recv_cq)) {
178 printk(KERN_WARNING "%s: failed to create receive CQ\n", ca->name); 181 printk(KERN_WARNING "%s: failed to create receive CQ\n", ca->name);
179 goto out_cm_dev_cleanup; 182 goto out_cm_dev_cleanup;
180 } 183 }
181 184
182 cq_attr.cqe = ipoib_sendq_size; 185 cq_attr.cqe = ipoib_sendq_size;
183 priv->send_cq = ib_create_cq(priv->ca, ipoib_send_comp_handler, NULL, 186 cq_attr.comp_vector = (req_vec + 1) % priv->ca->num_comp_vectors;
184 dev, &cq_attr); 187 priv->send_cq = ib_create_cq(priv->ca, ipoib_ib_tx_completion, NULL,
188 priv, &cq_attr);
185 if (IS_ERR(priv->send_cq)) { 189 if (IS_ERR(priv->send_cq)) {
186 printk(KERN_WARNING "%s: failed to create send CQ\n", ca->name); 190 printk(KERN_WARNING "%s: failed to create send CQ\n", ca->name);
187 goto out_free_recv_cq; 191 goto out_free_recv_cq;
@@ -208,6 +212,9 @@ int ipoib_transport_dev_init(struct net_device *dev, struct ib_device *ca)
208 goto out_free_send_cq; 212 goto out_free_send_cq;
209 } 213 }
210 214
215 if (ib_req_notify_cq(priv->send_cq, IB_CQ_NEXT_COMP))
216 goto out_free_send_cq;
217
211 for (i = 0; i < MAX_SKB_FRAGS + 1; ++i) 218 for (i = 0; i < MAX_SKB_FRAGS + 1; ++i)
212 priv->tx_sge[i].lkey = priv->pd->local_dma_lkey; 219 priv->tx_sge[i].lkey = priv->pd->local_dma_lkey;
213 220
diff --git a/drivers/infiniband/ulp/iser/iser_verbs.c b/drivers/infiniband/ulp/iser/iser_verbs.c
index 55a73b0ed4c6..56b7240a3fc3 100644
--- a/drivers/infiniband/ulp/iser/iser_verbs.c
+++ b/drivers/infiniband/ulp/iser/iser_verbs.c
@@ -1146,7 +1146,7 @@ void iser_err_comp(struct ib_wc *wc, const char *type)
1146 if (wc->status != IB_WC_WR_FLUSH_ERR) { 1146 if (wc->status != IB_WC_WR_FLUSH_ERR) {
1147 struct iser_conn *iser_conn = to_iser_conn(wc->qp->qp_context); 1147 struct iser_conn *iser_conn = to_iser_conn(wc->qp->qp_context);
1148 1148
1149 iser_err("%s failure: %s (%d) vend_err %x\n", type, 1149 iser_err("%s failure: %s (%d) vend_err %#x\n", type,
1150 ib_wc_status_msg(wc->status), wc->status, 1150 ib_wc_status_msg(wc->status), wc->status,
1151 wc->vendor_err); 1151 wc->vendor_err);
1152 1152
diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c
index ceabdb85df8b..720dfb3a1ac2 100644
--- a/drivers/infiniband/ulp/isert/ib_isert.c
+++ b/drivers/infiniband/ulp/isert/ib_isert.c
@@ -788,10 +788,11 @@ isert_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event)
788 * the rdma cm id 788 * the rdma cm id
789 */ 789 */
790 return 1; 790 return 1;
791 case RDMA_CM_EVENT_REJECTED: /* FALLTHRU */ 791 case RDMA_CM_EVENT_REJECTED:
792 isert_info("Connection rejected: %s\n", 792 isert_info("Connection rejected: %s\n",
793 rdma_reject_msg(cma_id, event->status)); 793 rdma_reject_msg(cma_id, event->status));
794 case RDMA_CM_EVENT_UNREACHABLE: /* FALLTHRU */ 794 /* fall through */
795 case RDMA_CM_EVENT_UNREACHABLE:
795 case RDMA_CM_EVENT_CONNECT_ERROR: 796 case RDMA_CM_EVENT_CONNECT_ERROR:
796 ret = isert_connect_error(cma_id); 797 ret = isert_connect_error(cma_id);
797 break; 798 break;
@@ -1569,9 +1570,7 @@ isert_put_cmd(struct isert_cmd *isert_cmd, bool comp_err)
1569 transport_generic_free_cmd(&cmd->se_cmd, 0); 1570 transport_generic_free_cmd(&cmd->se_cmd, 0);
1570 break; 1571 break;
1571 } 1572 }
1572 /* 1573 /* fall through */
1573 * Fall-through
1574 */
1575 default: 1574 default:
1576 iscsit_release_cmd(cmd); 1575 iscsit_release_cmd(cmd);
1577 break; 1576 break;
@@ -1749,8 +1748,9 @@ isert_do_control_comp(struct work_struct *work)
1749 switch (cmd->i_state) { 1748 switch (cmd->i_state) {
1750 case ISTATE_SEND_TASKMGTRSP: 1749 case ISTATE_SEND_TASKMGTRSP:
1751 iscsit_tmr_post_handler(cmd, cmd->conn); 1750 iscsit_tmr_post_handler(cmd, cmd->conn);
1752 case ISTATE_SEND_REJECT: /* FALLTHRU */ 1751 /* fall through */
1753 case ISTATE_SEND_TEXTRSP: /* FALLTHRU */ 1752 case ISTATE_SEND_REJECT:
1753 case ISTATE_SEND_TEXTRSP:
1754 cmd->i_state = ISTATE_SENT_STATUS; 1754 cmd->i_state = ISTATE_SENT_STATUS;
1755 isert_completion_put(&isert_cmd->tx_desc, isert_cmd, 1755 isert_completion_put(&isert_cmd->tx_desc, isert_cmd,
1756 ib_dev, false); 1756 ib_dev, false);
diff --git a/drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c b/drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c
index afa938bd26d6..4be3aef40bd2 100644
--- a/drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c
+++ b/drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.c
@@ -139,6 +139,7 @@ void opa_vnic_release_mac_tbl(struct opa_vnic_adapter *adapter)
139 rcu_assign_pointer(adapter->mactbl, NULL); 139 rcu_assign_pointer(adapter->mactbl, NULL);
140 synchronize_rcu(); 140 synchronize_rcu();
141 opa_vnic_free_mac_tbl(mactbl); 141 opa_vnic_free_mac_tbl(mactbl);
142 adapter->info.vport.mac_tbl_digest = 0;
142 mutex_unlock(&adapter->mactbl_lock); 143 mutex_unlock(&adapter->mactbl_lock);
143} 144}
144 145
@@ -405,6 +406,42 @@ u8 opa_vnic_get_vl(struct opa_vnic_adapter *adapter, struct sk_buff *skb)
405 return vl; 406 return vl;
406} 407}
407 408
409/* opa_vnic_get_rc - return the routing control */
410static u8 opa_vnic_get_rc(struct __opa_veswport_info *info,
411 struct sk_buff *skb)
412{
413 u8 proto, rout_ctrl;
414
415 switch (vlan_get_protocol(skb)) {
416 case htons(ETH_P_IPV6):
417 proto = ipv6_hdr(skb)->nexthdr;
418 if (proto == IPPROTO_TCP)
419 rout_ctrl = OPA_VNIC_ENCAP_RC_EXT(info->vesw.rc,
420 IPV6_TCP);
421 else if (proto == IPPROTO_UDP)
422 rout_ctrl = OPA_VNIC_ENCAP_RC_EXT(info->vesw.rc,
423 IPV6_UDP);
424 else
425 rout_ctrl = OPA_VNIC_ENCAP_RC_EXT(info->vesw.rc, IPV6);
426 break;
427 case htons(ETH_P_IP):
428 proto = ip_hdr(skb)->protocol;
429 if (proto == IPPROTO_TCP)
430 rout_ctrl = OPA_VNIC_ENCAP_RC_EXT(info->vesw.rc,
431 IPV4_TCP);
432 else if (proto == IPPROTO_UDP)
433 rout_ctrl = OPA_VNIC_ENCAP_RC_EXT(info->vesw.rc,
434 IPV4_UDP);
435 else
436 rout_ctrl = OPA_VNIC_ENCAP_RC_EXT(info->vesw.rc, IPV4);
437 break;
438 default:
439 rout_ctrl = OPA_VNIC_ENCAP_RC_EXT(info->vesw.rc, DEFAULT);
440 }
441
442 return rout_ctrl;
443}
444
408/* opa_vnic_calc_entropy - calculate the packet entropy */ 445/* opa_vnic_calc_entropy - calculate the packet entropy */
409u8 opa_vnic_calc_entropy(struct opa_vnic_adapter *adapter, struct sk_buff *skb) 446u8 opa_vnic_calc_entropy(struct opa_vnic_adapter *adapter, struct sk_buff *skb)
410{ 447{
@@ -447,7 +484,7 @@ void opa_vnic_encap_skb(struct opa_vnic_adapter *adapter, struct sk_buff *skb)
447{ 484{
448 struct __opa_veswport_info *info = &adapter->info; 485 struct __opa_veswport_info *info = &adapter->info;
449 struct opa_vnic_skb_mdata *mdata; 486 struct opa_vnic_skb_mdata *mdata;
450 u8 def_port, sc, entropy, *hdr; 487 u8 def_port, sc, rc, entropy, *hdr;
451 u16 len, l4_hdr; 488 u16 len, l4_hdr;
452 u32 dlid; 489 u32 dlid;
453 490
@@ -458,6 +495,7 @@ void opa_vnic_encap_skb(struct opa_vnic_adapter *adapter, struct sk_buff *skb)
458 len = opa_vnic_wire_length(skb); 495 len = opa_vnic_wire_length(skb);
459 dlid = opa_vnic_get_dlid(adapter, skb, def_port); 496 dlid = opa_vnic_get_dlid(adapter, skb, def_port);
460 sc = opa_vnic_get_sc(info, skb); 497 sc = opa_vnic_get_sc(info, skb);
498 rc = opa_vnic_get_rc(info, skb);
461 l4_hdr = info->vesw.vesw_id; 499 l4_hdr = info->vesw.vesw_id;
462 500
463 mdata = skb_push(skb, sizeof(*mdata)); 501 mdata = skb_push(skb, sizeof(*mdata));
@@ -470,6 +508,6 @@ void opa_vnic_encap_skb(struct opa_vnic_adapter *adapter, struct sk_buff *skb)
470 } 508 }
471 509
472 opa_vnic_make_header(hdr, info->vport.encap_slid, dlid, len, 510 opa_vnic_make_header(hdr, info->vport.encap_slid, dlid, len,
473 info->vesw.pkey, entropy, sc, 0, 511 info->vesw.pkey, entropy, sc, rc,
474 OPA_VNIC_L4_ETHR, l4_hdr); 512 OPA_VNIC_L4_ETHR, l4_hdr);
475} 513}
diff --git a/drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.h b/drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.h
index 4c434b9dd84c..e4c9bf2ef7e2 100644
--- a/drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.h
+++ b/drivers/infiniband/ulp/opa_vnic/opa_vnic_encap.h
@@ -103,6 +103,17 @@
103#define OPA_VNIC_ETH_LINK_UP 1 103#define OPA_VNIC_ETH_LINK_UP 1
104#define OPA_VNIC_ETH_LINK_DOWN 2 104#define OPA_VNIC_ETH_LINK_DOWN 2
105 105
106/* routing control */
107#define OPA_VNIC_ENCAP_RC_DEFAULT 0
108#define OPA_VNIC_ENCAP_RC_IPV4 4
109#define OPA_VNIC_ENCAP_RC_IPV4_UDP 8
110#define OPA_VNIC_ENCAP_RC_IPV4_TCP 12
111#define OPA_VNIC_ENCAP_RC_IPV6 16
112#define OPA_VNIC_ENCAP_RC_IPV6_TCP 20
113#define OPA_VNIC_ENCAP_RC_IPV6_UDP 24
114
115#define OPA_VNIC_ENCAP_RC_EXT(w, b) (((w) >> OPA_VNIC_ENCAP_RC_ ## b) & 0x7)
116
106/** 117/**
107 * struct opa_vesw_info - OPA vnic switch information 118 * struct opa_vesw_info - OPA vnic switch information
108 * @fabric_id: 10-bit fabric id 119 * @fabric_id: 10-bit fabric id
@@ -111,8 +122,8 @@
111 * @pkey: partition key 122 * @pkey: partition key
112 * @u_mcast_dlid: unknown multicast dlid 123 * @u_mcast_dlid: unknown multicast dlid
113 * @u_ucast_dlid: array of unknown unicast dlids 124 * @u_ucast_dlid: array of unknown unicast dlids
114 * @eth_mtu: MTUs for each vlan PCP 125 * @rc: routing control
115 * @eth_mtu_non_vlan: MTU for non vlan packets 126 * @eth_mtu: Ethernet MTU
116 */ 127 */
117struct opa_vesw_info { 128struct opa_vesw_info {
118 __be16 fabric_id; 129 __be16 fabric_id;
@@ -128,9 +139,10 @@ struct opa_vesw_info {
128 __be32 u_mcast_dlid; 139 __be32 u_mcast_dlid;
129 __be32 u_ucast_dlid[OPA_VESW_MAX_NUM_DEF_PORT]; 140 __be32 u_ucast_dlid[OPA_VESW_MAX_NUM_DEF_PORT];
130 141
131 u8 rsvd3[44]; 142 __be32 rc;
132 __be16 eth_mtu[OPA_VNIC_MAX_NUM_PCP]; 143
133 __be16 eth_mtu_non_vlan; 144 u8 rsvd3[56];
145 __be16 eth_mtu;
134 u8 rsvd4[2]; 146 u8 rsvd4[2];
135} __packed; 147} __packed;
136 148
diff --git a/drivers/infiniband/ulp/opa_vnic/opa_vnic_internal.h b/drivers/infiniband/ulp/opa_vnic/opa_vnic_internal.h
index ca29e6d5aedc..afd95f432262 100644
--- a/drivers/infiniband/ulp/opa_vnic/opa_vnic_internal.h
+++ b/drivers/infiniband/ulp/opa_vnic/opa_vnic_internal.h
@@ -89,9 +89,10 @@ struct __opa_vesw_info {
89 u32 u_mcast_dlid; 89 u32 u_mcast_dlid;
90 u32 u_ucast_dlid[OPA_VESW_MAX_NUM_DEF_PORT]; 90 u32 u_ucast_dlid[OPA_VESW_MAX_NUM_DEF_PORT];
91 91
92 u8 rsvd3[44]; 92 u32 rc;
93 u16 eth_mtu[OPA_VNIC_MAX_NUM_PCP]; 93
94 u16 eth_mtu_non_vlan; 94 u8 rsvd3[56];
95 u16 eth_mtu;
95 u8 rsvd4[2]; 96 u8 rsvd4[2];
96} __packed; 97} __packed;
97 98
diff --git a/drivers/infiniband/ulp/opa_vnic/opa_vnic_netdev.c b/drivers/infiniband/ulp/opa_vnic/opa_vnic_netdev.c
index 1a3c25364b64..ce57e0f10289 100644
--- a/drivers/infiniband/ulp/opa_vnic/opa_vnic_netdev.c
+++ b/drivers/infiniband/ulp/opa_vnic/opa_vnic_netdev.c
@@ -112,6 +112,27 @@ static u16 opa_vnic_select_queue(struct net_device *netdev, struct sk_buff *skb,
112 return rc; 112 return rc;
113} 113}
114 114
115static void opa_vnic_update_state(struct opa_vnic_adapter *adapter, bool up)
116{
117 struct __opa_veswport_info *info = &adapter->info;
118
119 mutex_lock(&adapter->lock);
120 /* Operational state can only be DROP_ALL or FORWARDING */
121 if ((info->vport.config_state == OPA_VNIC_STATE_FORWARDING) && up) {
122 info->vport.oper_state = OPA_VNIC_STATE_FORWARDING;
123 info->vport.eth_link_status = OPA_VNIC_ETH_LINK_UP;
124 } else {
125 info->vport.oper_state = OPA_VNIC_STATE_DROP_ALL;
126 info->vport.eth_link_status = OPA_VNIC_ETH_LINK_DOWN;
127 }
128
129 if (info->vport.config_state == OPA_VNIC_STATE_FORWARDING)
130 netif_dormant_off(adapter->netdev);
131 else
132 netif_dormant_on(adapter->netdev);
133 mutex_unlock(&adapter->lock);
134}
135
115/* opa_vnic_process_vema_config - process vema configuration updates */ 136/* opa_vnic_process_vema_config - process vema configuration updates */
116void opa_vnic_process_vema_config(struct opa_vnic_adapter *adapter) 137void opa_vnic_process_vema_config(struct opa_vnic_adapter *adapter)
117{ 138{
@@ -130,7 +151,7 @@ void opa_vnic_process_vema_config(struct opa_vnic_adapter *adapter)
130 memcpy(saddr.sa_data, info->vport.base_mac_addr, 151 memcpy(saddr.sa_data, info->vport.base_mac_addr,
131 ARRAY_SIZE(info->vport.base_mac_addr)); 152 ARRAY_SIZE(info->vport.base_mac_addr));
132 mutex_lock(&adapter->lock); 153 mutex_lock(&adapter->lock);
133 eth_mac_addr(netdev, &saddr); 154 eth_commit_mac_addr_change(netdev, &saddr);
134 memcpy(adapter->vema_mac_addr, 155 memcpy(adapter->vema_mac_addr,
135 info->vport.base_mac_addr, ETH_ALEN); 156 info->vport.base_mac_addr, ETH_ALEN);
136 mutex_unlock(&adapter->lock); 157 mutex_unlock(&adapter->lock);
@@ -140,7 +161,7 @@ void opa_vnic_process_vema_config(struct opa_vnic_adapter *adapter)
140 161
141 /* Handle MTU limit change */ 162 /* Handle MTU limit change */
142 rtnl_lock(); 163 rtnl_lock();
143 netdev->max_mtu = max_t(unsigned int, info->vesw.eth_mtu_non_vlan, 164 netdev->max_mtu = max_t(unsigned int, info->vesw.eth_mtu,
144 netdev->min_mtu); 165 netdev->min_mtu);
145 if (netdev->mtu > netdev->max_mtu) 166 if (netdev->mtu > netdev->max_mtu)
146 dev_set_mtu(netdev, netdev->max_mtu); 167 dev_set_mtu(netdev, netdev->max_mtu);
@@ -164,14 +185,8 @@ void opa_vnic_process_vema_config(struct opa_vnic_adapter *adapter)
164 adapter->flow_tbl[i] = port_count ? port_num[i % port_count] : 185 adapter->flow_tbl[i] = port_count ? port_num[i % port_count] :
165 OPA_VNIC_INVALID_PORT; 186 OPA_VNIC_INVALID_PORT;
166 187
167 /* Operational state can only be DROP_ALL or FORWARDING */ 188 /* update state */
168 if (info->vport.config_state == OPA_VNIC_STATE_FORWARDING) { 189 opa_vnic_update_state(adapter, !!(netdev->flags & IFF_UP));
169 info->vport.oper_state = OPA_VNIC_STATE_FORWARDING;
170 netif_dormant_off(netdev);
171 } else {
172 info->vport.oper_state = OPA_VNIC_STATE_DROP_ALL;
173 netif_dormant_on(netdev);
174 }
175} 190}
176 191
177/* 192/*
@@ -183,6 +198,7 @@ static inline void opa_vnic_set_pod_values(struct opa_vnic_adapter *adapter)
183 adapter->info.vport.max_smac_ent = OPA_VNIC_MAX_SMAC_LIMIT; 198 adapter->info.vport.max_smac_ent = OPA_VNIC_MAX_SMAC_LIMIT;
184 adapter->info.vport.config_state = OPA_VNIC_STATE_DROP_ALL; 199 adapter->info.vport.config_state = OPA_VNIC_STATE_DROP_ALL;
185 adapter->info.vport.eth_link_status = OPA_VNIC_ETH_LINK_DOWN; 200 adapter->info.vport.eth_link_status = OPA_VNIC_ETH_LINK_DOWN;
201 adapter->info.vesw.eth_mtu = ETH_DATA_LEN;
186} 202}
187 203
188/* opa_vnic_set_mac_addr - change mac address */ 204/* opa_vnic_set_mac_addr - change mac address */
@@ -268,8 +284,8 @@ static int opa_netdev_open(struct net_device *netdev)
268 return rc; 284 return rc;
269 } 285 }
270 286
271 /* Update eth link status and send trap */ 287 /* Update status and send trap */
272 adapter->info.vport.eth_link_status = OPA_VNIC_ETH_LINK_UP; 288 opa_vnic_update_state(adapter, true);
273 opa_vnic_vema_report_event(adapter, 289 opa_vnic_vema_report_event(adapter,
274 OPA_VESWPORT_TRAP_ETH_LINK_STATUS_CHANGE); 290 OPA_VESWPORT_TRAP_ETH_LINK_STATUS_CHANGE);
275 return 0; 291 return 0;
@@ -287,8 +303,8 @@ static int opa_netdev_close(struct net_device *netdev)
287 return rc; 303 return rc;
288 } 304 }
289 305
290 /* Update eth link status and send trap */ 306 /* Update status and send trap */
291 adapter->info.vport.eth_link_status = OPA_VNIC_ETH_LINK_DOWN; 307 opa_vnic_update_state(adapter, false);
292 opa_vnic_vema_report_event(adapter, 308 opa_vnic_vema_report_event(adapter,
293 OPA_VESWPORT_TRAP_ETH_LINK_STATUS_CHANGE); 309 OPA_VESWPORT_TRAP_ETH_LINK_STATUS_CHANGE);
294 return 0; 310 return 0;
diff --git a/drivers/infiniband/ulp/opa_vnic/opa_vnic_vema.c b/drivers/infiniband/ulp/opa_vnic/opa_vnic_vema.c
index 21f0b481edcc..4b615c1451e7 100644
--- a/drivers/infiniband/ulp/opa_vnic/opa_vnic_vema.c
+++ b/drivers/infiniband/ulp/opa_vnic/opa_vnic_vema.c
@@ -186,6 +186,7 @@ static inline void vema_get_pod_values(struct opa_veswport_info *port_info)
186 cpu_to_be16(OPA_VNIC_MAX_SMAC_LIMIT); 186 cpu_to_be16(OPA_VNIC_MAX_SMAC_LIMIT);
187 port_info->vport.oper_state = OPA_VNIC_STATE_DROP_ALL; 187 port_info->vport.oper_state = OPA_VNIC_STATE_DROP_ALL;
188 port_info->vport.config_state = OPA_VNIC_STATE_DROP_ALL; 188 port_info->vport.config_state = OPA_VNIC_STATE_DROP_ALL;
189 port_info->vesw.eth_mtu = cpu_to_be16(ETH_DATA_LEN);
189} 190}
190 191
191/** 192/**
diff --git a/drivers/infiniband/ulp/opa_vnic/opa_vnic_vema_iface.c b/drivers/infiniband/ulp/opa_vnic/opa_vnic_vema_iface.c
index c2733964379c..868b5aec1537 100644
--- a/drivers/infiniband/ulp/opa_vnic/opa_vnic_vema_iface.c
+++ b/drivers/infiniband/ulp/opa_vnic/opa_vnic_vema_iface.c
@@ -176,11 +176,10 @@ void opa_vnic_get_vesw_info(struct opa_vnic_adapter *adapter,
176 for (i = 0; i < OPA_VESW_MAX_NUM_DEF_PORT; i++) 176 for (i = 0; i < OPA_VESW_MAX_NUM_DEF_PORT; i++)
177 info->u_ucast_dlid[i] = cpu_to_be32(src->u_ucast_dlid[i]); 177 info->u_ucast_dlid[i] = cpu_to_be32(src->u_ucast_dlid[i]);
178 178
179 memcpy(info->rsvd3, src->rsvd3, ARRAY_SIZE(src->rsvd3)); 179 info->rc = cpu_to_be32(src->rc);
180 for (i = 0; i < OPA_VNIC_MAX_NUM_PCP; i++)
181 info->eth_mtu[i] = cpu_to_be16(src->eth_mtu[i]);
182 180
183 info->eth_mtu_non_vlan = cpu_to_be16(src->eth_mtu_non_vlan); 181 memcpy(info->rsvd3, src->rsvd3, ARRAY_SIZE(src->rsvd3));
182 info->eth_mtu = cpu_to_be16(src->eth_mtu);
184 memcpy(info->rsvd4, src->rsvd4, ARRAY_SIZE(src->rsvd4)); 183 memcpy(info->rsvd4, src->rsvd4, ARRAY_SIZE(src->rsvd4));
185} 184}
186 185
@@ -211,11 +210,10 @@ void opa_vnic_set_vesw_info(struct opa_vnic_adapter *adapter,
211 for (i = 0; i < OPA_VESW_MAX_NUM_DEF_PORT; i++) 210 for (i = 0; i < OPA_VESW_MAX_NUM_DEF_PORT; i++)
212 dst->u_ucast_dlid[i] = be32_to_cpu(info->u_ucast_dlid[i]); 211 dst->u_ucast_dlid[i] = be32_to_cpu(info->u_ucast_dlid[i]);
213 212
214 memcpy(dst->rsvd3, info->rsvd3, ARRAY_SIZE(info->rsvd3)); 213 dst->rc = be32_to_cpu(info->rc);
215 for (i = 0; i < OPA_VNIC_MAX_NUM_PCP; i++)
216 dst->eth_mtu[i] = be16_to_cpu(info->eth_mtu[i]);
217 214
218 dst->eth_mtu_non_vlan = be16_to_cpu(info->eth_mtu_non_vlan); 215 memcpy(dst->rsvd3, info->rsvd3, ARRAY_SIZE(info->rsvd3));
216 dst->eth_mtu = be16_to_cpu(info->eth_mtu);
219 memcpy(dst->rsvd4, info->rsvd4, ARRAY_SIZE(info->rsvd4)); 217 memcpy(dst->rsvd4, info->rsvd4, ARRAY_SIZE(info->rsvd4));
220} 218}
221 219
@@ -348,7 +346,7 @@ void opa_vnic_query_mcast_macs(struct opa_vnic_adapter *adapter,
348void opa_vnic_query_ucast_macs(struct opa_vnic_adapter *adapter, 346void opa_vnic_query_ucast_macs(struct opa_vnic_adapter *adapter,
349 struct opa_veswport_iface_macs *macs) 347 struct opa_veswport_iface_macs *macs)
350{ 348{
351 u16 start_idx, tot_macs, num_macs, idx = 0, count = 0; 349 u16 start_idx, tot_macs, num_macs, idx = 0, count = 0, em_macs = 0;
352 struct netdev_hw_addr *ha; 350 struct netdev_hw_addr *ha;
353 351
354 start_idx = be16_to_cpu(macs->start_idx); 352 start_idx = be16_to_cpu(macs->start_idx);
@@ -359,8 +357,10 @@ void opa_vnic_query_ucast_macs(struct opa_vnic_adapter *adapter,
359 357
360 /* Do not include EM specified MAC address */ 358 /* Do not include EM specified MAC address */
361 if (!memcmp(adapter->info.vport.base_mac_addr, ha->addr, 359 if (!memcmp(adapter->info.vport.base_mac_addr, ha->addr,
362 ARRAY_SIZE(adapter->info.vport.base_mac_addr))) 360 ARRAY_SIZE(adapter->info.vport.base_mac_addr))) {
361 em_macs++;
363 continue; 362 continue;
363 }
364 364
365 if (start_idx > idx++) 365 if (start_idx > idx++)
366 continue; 366 continue;
@@ -383,7 +383,7 @@ void opa_vnic_query_ucast_macs(struct opa_vnic_adapter *adapter,
383 } 383 }
384 384
385 tot_macs = netdev_hw_addr_list_count(&adapter->netdev->dev_addrs) + 385 tot_macs = netdev_hw_addr_list_count(&adapter->netdev->dev_addrs) +
386 netdev_uc_count(adapter->netdev); 386 netdev_uc_count(adapter->netdev) - em_macs;
387 macs->tot_macs_in_lst = cpu_to_be16(tot_macs); 387 macs->tot_macs_in_lst = cpu_to_be16(tot_macs);
388 macs->num_macs_in_msg = cpu_to_be16(count); 388 macs->num_macs_in_msg = cpu_to_be16(count);
389 macs->gen_count = cpu_to_be16(adapter->info.vport.uc_macs_gen_count); 389 macs->gen_count = cpu_to_be16(adapter->info.vport.uc_macs_gen_count);
diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
index fa5ccdb3bb2a..972d4b3c5223 100644
--- a/drivers/infiniband/ulp/srp/ib_srp.c
+++ b/drivers/infiniband/ulp/srp/ib_srp.c
@@ -464,20 +464,20 @@ static struct srp_fr_pool *srp_alloc_fr_pool(struct srp_target_port *target)
464 464
465/** 465/**
466 * srp_destroy_qp() - destroy an RDMA queue pair 466 * srp_destroy_qp() - destroy an RDMA queue pair
467 * @qp: RDMA queue pair. 467 * @ch: SRP RDMA channel.
468 * 468 *
469 * Drain the qp before destroying it. This avoids that the receive 469 * Drain the qp before destroying it. This avoids that the receive
470 * completion handler can access the queue pair while it is 470 * completion handler can access the queue pair while it is
471 * being destroyed. 471 * being destroyed.
472 */ 472 */
473static void srp_destroy_qp(struct srp_rdma_ch *ch, struct ib_qp *qp) 473static void srp_destroy_qp(struct srp_rdma_ch *ch)
474{ 474{
475 spin_lock_irq(&ch->lock); 475 spin_lock_irq(&ch->lock);
476 ib_process_cq_direct(ch->send_cq, -1); 476 ib_process_cq_direct(ch->send_cq, -1);
477 spin_unlock_irq(&ch->lock); 477 spin_unlock_irq(&ch->lock);
478 478
479 ib_drain_qp(qp); 479 ib_drain_qp(ch->qp);
480 ib_destroy_qp(qp); 480 ib_destroy_qp(ch->qp);
481} 481}
482 482
483static int srp_create_ch_ib(struct srp_rdma_ch *ch) 483static int srp_create_ch_ib(struct srp_rdma_ch *ch)
@@ -550,7 +550,7 @@ static int srp_create_ch_ib(struct srp_rdma_ch *ch)
550 } 550 }
551 551
552 if (ch->qp) 552 if (ch->qp)
553 srp_destroy_qp(ch, ch->qp); 553 srp_destroy_qp(ch);
554 if (ch->recv_cq) 554 if (ch->recv_cq)
555 ib_free_cq(ch->recv_cq); 555 ib_free_cq(ch->recv_cq);
556 if (ch->send_cq) 556 if (ch->send_cq)
@@ -617,7 +617,7 @@ static void srp_free_ch_ib(struct srp_target_port *target,
617 ib_destroy_fmr_pool(ch->fmr_pool); 617 ib_destroy_fmr_pool(ch->fmr_pool);
618 } 618 }
619 619
620 srp_destroy_qp(ch, ch->qp); 620 srp_destroy_qp(ch);
621 ib_free_cq(ch->send_cq); 621 ib_free_cq(ch->send_cq);
622 ib_free_cq(ch->recv_cq); 622 ib_free_cq(ch->recv_cq);
623 623
@@ -665,12 +665,19 @@ static void srp_path_rec_completion(int status,
665static int srp_lookup_path(struct srp_rdma_ch *ch) 665static int srp_lookup_path(struct srp_rdma_ch *ch)
666{ 666{
667 struct srp_target_port *target = ch->target; 667 struct srp_target_port *target = ch->target;
668 int ret; 668 int ret = -ENODEV;
669 669
670 ch->path.numb_path = 1; 670 ch->path.numb_path = 1;
671 671
672 init_completion(&ch->done); 672 init_completion(&ch->done);
673 673
674 /*
675 * Avoid that the SCSI host can be removed by srp_remove_target()
676 * before srp_path_rec_completion() is called.
677 */
678 if (!scsi_host_get(target->scsi_host))
679 goto out;
680
674 ch->path_query_id = ib_sa_path_rec_get(&srp_sa_client, 681 ch->path_query_id = ib_sa_path_rec_get(&srp_sa_client,
675 target->srp_host->srp_dev->dev, 682 target->srp_host->srp_dev->dev,
676 target->srp_host->port, 683 target->srp_host->port,
@@ -684,18 +691,41 @@ static int srp_lookup_path(struct srp_rdma_ch *ch)
684 GFP_KERNEL, 691 GFP_KERNEL,
685 srp_path_rec_completion, 692 srp_path_rec_completion,
686 ch, &ch->path_query); 693 ch, &ch->path_query);
687 if (ch->path_query_id < 0) 694 ret = ch->path_query_id;
688 return ch->path_query_id; 695 if (ret < 0)
696 goto put;
689 697
690 ret = wait_for_completion_interruptible(&ch->done); 698 ret = wait_for_completion_interruptible(&ch->done);
691 if (ret < 0) 699 if (ret < 0)
692 return ret; 700 goto put;
693 701
694 if (ch->status < 0) 702 ret = ch->status;
703 if (ret < 0)
695 shost_printk(KERN_WARNING, target->scsi_host, 704 shost_printk(KERN_WARNING, target->scsi_host,
696 PFX "Path record query failed\n"); 705 PFX "Path record query failed\n");
697 706
698 return ch->status; 707put:
708 scsi_host_put(target->scsi_host);
709
710out:
711 return ret;
712}
713
714static u8 srp_get_subnet_timeout(struct srp_host *host)
715{
716 struct ib_port_attr attr;
717 int ret;
718 u8 subnet_timeout = 18;
719
720 ret = ib_query_port(host->srp_dev->dev, host->port, &attr);
721 if (ret == 0)
722 subnet_timeout = attr.subnet_timeout;
723
724 if (unlikely(subnet_timeout < 15))
725 pr_warn("%s: subnet timeout %d may cause SRP login to fail.\n",
726 dev_name(&host->srp_dev->dev->dev), subnet_timeout);
727
728 return subnet_timeout;
699} 729}
700 730
701static int srp_send_req(struct srp_rdma_ch *ch, bool multich) 731static int srp_send_req(struct srp_rdma_ch *ch, bool multich)
@@ -706,6 +736,9 @@ static int srp_send_req(struct srp_rdma_ch *ch, bool multich)
706 struct srp_login_req priv; 736 struct srp_login_req priv;
707 } *req = NULL; 737 } *req = NULL;
708 int status; 738 int status;
739 u8 subnet_timeout;
740
741 subnet_timeout = srp_get_subnet_timeout(target->srp_host);
709 742
710 req = kzalloc(sizeof *req, GFP_KERNEL); 743 req = kzalloc(sizeof *req, GFP_KERNEL);
711 if (!req) 744 if (!req)
@@ -728,8 +761,8 @@ static int srp_send_req(struct srp_rdma_ch *ch, bool multich)
728 * module parameters if anyone cared about setting them. 761 * module parameters if anyone cared about setting them.
729 */ 762 */
730 req->param.responder_resources = 4; 763 req->param.responder_resources = 4;
731 req->param.remote_cm_response_timeout = 20; 764 req->param.remote_cm_response_timeout = subnet_timeout + 2;
732 req->param.local_cm_response_timeout = 20; 765 req->param.local_cm_response_timeout = subnet_timeout + 2;
733 req->param.retry_count = target->tl_retry_count; 766 req->param.retry_count = target->tl_retry_count;
734 req->param.rnr_retry_count = 7; 767 req->param.rnr_retry_count = 7;
735 req->param.max_cm_retries = 15; 768 req->param.max_cm_retries = 15;
@@ -1279,7 +1312,6 @@ static int srp_map_finish_fmr(struct srp_map_state *state,
1279{ 1312{
1280 struct srp_target_port *target = ch->target; 1313 struct srp_target_port *target = ch->target;
1281 struct srp_device *dev = target->srp_host->srp_dev; 1314 struct srp_device *dev = target->srp_host->srp_dev;
1282 struct ib_pd *pd = target->pd;
1283 struct ib_pool_fmr *fmr; 1315 struct ib_pool_fmr *fmr;
1284 u64 io_addr = 0; 1316 u64 io_addr = 0;
1285 1317
@@ -1295,9 +1327,9 @@ static int srp_map_finish_fmr(struct srp_map_state *state,
1295 if (state->npages == 0) 1327 if (state->npages == 0)
1296 return 0; 1328 return 0;
1297 1329
1298 if (state->npages == 1 && (pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY)) { 1330 if (state->npages == 1 && target->global_rkey) {
1299 srp_map_desc(state, state->base_dma_addr, state->dma_len, 1331 srp_map_desc(state, state->base_dma_addr, state->dma_len,
1300 pd->unsafe_global_rkey); 1332 target->global_rkey);
1301 goto reset_state; 1333 goto reset_state;
1302 } 1334 }
1303 1335
@@ -1337,7 +1369,6 @@ static int srp_map_finish_fr(struct srp_map_state *state,
1337{ 1369{
1338 struct srp_target_port *target = ch->target; 1370 struct srp_target_port *target = ch->target;
1339 struct srp_device *dev = target->srp_host->srp_dev; 1371 struct srp_device *dev = target->srp_host->srp_dev;
1340 struct ib_pd *pd = target->pd;
1341 struct ib_send_wr *bad_wr; 1372 struct ib_send_wr *bad_wr;
1342 struct ib_reg_wr wr; 1373 struct ib_reg_wr wr;
1343 struct srp_fr_desc *desc; 1374 struct srp_fr_desc *desc;
@@ -1353,12 +1384,12 @@ static int srp_map_finish_fr(struct srp_map_state *state,
1353 1384
1354 WARN_ON_ONCE(!dev->use_fast_reg); 1385 WARN_ON_ONCE(!dev->use_fast_reg);
1355 1386
1356 if (sg_nents == 1 && (pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY)) { 1387 if (sg_nents == 1 && target->global_rkey) {
1357 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; 1388 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0;
1358 1389
1359 srp_map_desc(state, sg_dma_address(state->sg) + sg_offset, 1390 srp_map_desc(state, sg_dma_address(state->sg) + sg_offset,
1360 sg_dma_len(state->sg) - sg_offset, 1391 sg_dma_len(state->sg) - sg_offset,
1361 pd->unsafe_global_rkey); 1392 target->global_rkey);
1362 if (sg_offset_p) 1393 if (sg_offset_p)
1363 *sg_offset_p = 0; 1394 *sg_offset_p = 0;
1364 return 1; 1395 return 1;
@@ -1520,7 +1551,7 @@ static int srp_map_sg_dma(struct srp_map_state *state, struct srp_rdma_ch *ch,
1520 for_each_sg(scat, sg, count, i) { 1551 for_each_sg(scat, sg, count, i) {
1521 srp_map_desc(state, ib_sg_dma_address(dev->dev, sg), 1552 srp_map_desc(state, ib_sg_dma_address(dev->dev, sg),
1522 ib_sg_dma_len(dev->dev, sg), 1553 ib_sg_dma_len(dev->dev, sg),
1523 target->pd->unsafe_global_rkey); 1554 target->global_rkey);
1524 } 1555 }
1525 1556
1526 return 0; 1557 return 0;
@@ -1618,7 +1649,6 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_rdma_ch *ch,
1618 struct srp_request *req) 1649 struct srp_request *req)
1619{ 1650{
1620 struct srp_target_port *target = ch->target; 1651 struct srp_target_port *target = ch->target;
1621 struct ib_pd *pd = target->pd;
1622 struct scatterlist *scat; 1652 struct scatterlist *scat;
1623 struct srp_cmd *cmd = req->cmd->buf; 1653 struct srp_cmd *cmd = req->cmd->buf;
1624 int len, nents, count, ret; 1654 int len, nents, count, ret;
@@ -1654,7 +1684,7 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_rdma_ch *ch,
1654 fmt = SRP_DATA_DESC_DIRECT; 1684 fmt = SRP_DATA_DESC_DIRECT;
1655 len = sizeof (struct srp_cmd) + sizeof (struct srp_direct_buf); 1685 len = sizeof (struct srp_cmd) + sizeof (struct srp_direct_buf);
1656 1686
1657 if (count == 1 && (pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY)) { 1687 if (count == 1 && target->global_rkey) {
1658 /* 1688 /*
1659 * The midlayer only generated a single gather/scatter 1689 * The midlayer only generated a single gather/scatter
1660 * entry, or DMA mapping coalesced everything to a 1690 * entry, or DMA mapping coalesced everything to a
@@ -1664,7 +1694,7 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_rdma_ch *ch,
1664 struct srp_direct_buf *buf = (void *) cmd->add_data; 1694 struct srp_direct_buf *buf = (void *) cmd->add_data;
1665 1695
1666 buf->va = cpu_to_be64(ib_sg_dma_address(ibdev, scat)); 1696 buf->va = cpu_to_be64(ib_sg_dma_address(ibdev, scat));
1667 buf->key = cpu_to_be32(pd->unsafe_global_rkey); 1697 buf->key = cpu_to_be32(target->global_rkey);
1668 buf->len = cpu_to_be32(ib_sg_dma_len(ibdev, scat)); 1698 buf->len = cpu_to_be32(ib_sg_dma_len(ibdev, scat));
1669 1699
1670 req->nmdesc = 0; 1700 req->nmdesc = 0;
@@ -1735,14 +1765,14 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_rdma_ch *ch,
1735 memcpy(indirect_hdr->desc_list, req->indirect_desc, 1765 memcpy(indirect_hdr->desc_list, req->indirect_desc,
1736 count * sizeof (struct srp_direct_buf)); 1766 count * sizeof (struct srp_direct_buf));
1737 1767
1738 if (!(pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY)) { 1768 if (!target->global_rkey) {
1739 ret = srp_map_idb(ch, req, state.gen.next, state.gen.end, 1769 ret = srp_map_idb(ch, req, state.gen.next, state.gen.end,
1740 idb_len, &idb_rkey); 1770 idb_len, &idb_rkey);
1741 if (ret < 0) 1771 if (ret < 0)
1742 goto unmap; 1772 goto unmap;
1743 req->nmdesc++; 1773 req->nmdesc++;
1744 } else { 1774 } else {
1745 idb_rkey = cpu_to_be32(pd->unsafe_global_rkey); 1775 idb_rkey = cpu_to_be32(target->global_rkey);
1746 } 1776 }
1747 1777
1748 indirect_hdr->table_desc.va = cpu_to_be64(req->indirect_dma_addr); 1778 indirect_hdr->table_desc.va = cpu_to_be64(req->indirect_dma_addr);
@@ -2403,7 +2433,7 @@ static void srp_cm_rej_handler(struct ib_cm_id *cm_id,
2403 switch (event->param.rej_rcvd.reason) { 2433 switch (event->param.rej_rcvd.reason) {
2404 case IB_CM_REJ_PORT_CM_REDIRECT: 2434 case IB_CM_REJ_PORT_CM_REDIRECT:
2405 cpi = event->param.rej_rcvd.ari; 2435 cpi = event->param.rej_rcvd.ari;
2406 sa_path_set_dlid(&ch->path, htonl(ntohs(cpi->redirect_lid))); 2436 sa_path_set_dlid(&ch->path, ntohs(cpi->redirect_lid));
2407 ch->path.pkey = cpi->redirect_pkey; 2437 ch->path.pkey = cpi->redirect_pkey;
2408 cm_id->remote_cm_qpn = be32_to_cpu(cpi->redirect_qp) & 0x00ffffff; 2438 cm_id->remote_cm_qpn = be32_to_cpu(cpi->redirect_qp) & 0x00ffffff;
2409 memcpy(ch->path.dgid.raw, cpi->redirect_gid, 16); 2439 memcpy(ch->path.dgid.raw, cpi->redirect_gid, 16);
@@ -3318,8 +3348,8 @@ static ssize_t srp_create_target(struct device *dev,
3318 target->io_class = SRP_REV16A_IB_IO_CLASS; 3348 target->io_class = SRP_REV16A_IB_IO_CLASS;
3319 target->scsi_host = target_host; 3349 target->scsi_host = target_host;
3320 target->srp_host = host; 3350 target->srp_host = host;
3321 target->pd = host->srp_dev->pd;
3322 target->lkey = host->srp_dev->pd->local_dma_lkey; 3351 target->lkey = host->srp_dev->pd->local_dma_lkey;
3352 target->global_rkey = host->srp_dev->global_rkey;
3323 target->cmd_sg_cnt = cmd_sg_entries; 3353 target->cmd_sg_cnt = cmd_sg_entries;
3324 target->sg_tablesize = indirect_sg_entries ? : cmd_sg_entries; 3354 target->sg_tablesize = indirect_sg_entries ? : cmd_sg_entries;
3325 target->allow_ext_sg = allow_ext_sg; 3355 target->allow_ext_sg = allow_ext_sg;
@@ -3638,6 +3668,10 @@ static void srp_add_one(struct ib_device *device)
3638 if (IS_ERR(srp_dev->pd)) 3668 if (IS_ERR(srp_dev->pd))
3639 goto free_dev; 3669 goto free_dev;
3640 3670
3671 if (flags & IB_PD_UNSAFE_GLOBAL_RKEY) {
3672 srp_dev->global_rkey = srp_dev->pd->unsafe_global_rkey;
3673 WARN_ON_ONCE(srp_dev->global_rkey == 0);
3674 }
3641 3675
3642 for (p = rdma_start_port(device); p <= rdma_end_port(device); ++p) { 3676 for (p = rdma_start_port(device); p <= rdma_end_port(device); ++p) {
3643 host = srp_add_port(srp_dev, p); 3677 host = srp_add_port(srp_dev, p);
diff --git a/drivers/infiniband/ulp/srp/ib_srp.h b/drivers/infiniband/ulp/srp/ib_srp.h
index ab9077b81d5a..a814f5ef16f9 100644
--- a/drivers/infiniband/ulp/srp/ib_srp.h
+++ b/drivers/infiniband/ulp/srp/ib_srp.h
@@ -90,6 +90,7 @@ struct srp_device {
90 struct list_head dev_list; 90 struct list_head dev_list;
91 struct ib_device *dev; 91 struct ib_device *dev;
92 struct ib_pd *pd; 92 struct ib_pd *pd;
93 u32 global_rkey;
93 u64 mr_page_mask; 94 u64 mr_page_mask;
94 int mr_page_size; 95 int mr_page_size;
95 int mr_max_size; 96 int mr_max_size;
@@ -179,7 +180,7 @@ struct srp_target_port {
179 spinlock_t lock; 180 spinlock_t lock;
180 181
181 /* read only in the hot path */ 182 /* read only in the hot path */
182 struct ib_pd *pd; 183 u32 global_rkey;
183 struct srp_rdma_ch *ch; 184 struct srp_rdma_ch *ch;
184 u32 ch_count; 185 u32 ch_count;
185 u32 lkey; 186 u32 lkey;
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c
index 9612e5bdfb00..8a1bd354b1cc 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.c
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.c
@@ -295,6 +295,7 @@ static void srpt_get_ioc(struct srpt_port *sport, u32 slot,
295{ 295{
296 struct srpt_device *sdev = sport->sdev; 296 struct srpt_device *sdev = sport->sdev;
297 struct ib_dm_ioc_profile *iocp; 297 struct ib_dm_ioc_profile *iocp;
298 int send_queue_depth;
298 299
299 iocp = (struct ib_dm_ioc_profile *)mad->data; 300 iocp = (struct ib_dm_ioc_profile *)mad->data;
300 301
@@ -310,6 +311,12 @@ static void srpt_get_ioc(struct srpt_port *sport, u32 slot,
310 return; 311 return;
311 } 312 }
312 313
314 if (sdev->use_srq)
315 send_queue_depth = sdev->srq_size;
316 else
317 send_queue_depth = min(SRPT_RQ_SIZE,
318 sdev->device->attrs.max_qp_wr);
319
313 memset(iocp, 0, sizeof(*iocp)); 320 memset(iocp, 0, sizeof(*iocp));
314 strcpy(iocp->id_string, SRPT_ID_STRING); 321 strcpy(iocp->id_string, SRPT_ID_STRING);
315 iocp->guid = cpu_to_be64(srpt_service_guid); 322 iocp->guid = cpu_to_be64(srpt_service_guid);
@@ -322,7 +329,7 @@ static void srpt_get_ioc(struct srpt_port *sport, u32 slot,
322 iocp->io_subclass = cpu_to_be16(SRP_IO_SUBCLASS); 329 iocp->io_subclass = cpu_to_be16(SRP_IO_SUBCLASS);
323 iocp->protocol = cpu_to_be16(SRP_PROTOCOL); 330 iocp->protocol = cpu_to_be16(SRP_PROTOCOL);
324 iocp->protocol_version = cpu_to_be16(SRP_PROTOCOL_VERSION); 331 iocp->protocol_version = cpu_to_be16(SRP_PROTOCOL_VERSION);
325 iocp->send_queue_depth = cpu_to_be16(sdev->srq_size); 332 iocp->send_queue_depth = cpu_to_be16(send_queue_depth);
326 iocp->rdma_read_depth = 4; 333 iocp->rdma_read_depth = 4;
327 iocp->send_size = cpu_to_be32(srp_max_req_size); 334 iocp->send_size = cpu_to_be32(srp_max_req_size);
328 iocp->rdma_size = cpu_to_be32(min(sport->port_attrib.srp_max_rdma_size, 335 iocp->rdma_size = cpu_to_be32(min(sport->port_attrib.srp_max_rdma_size,
@@ -686,6 +693,9 @@ static void srpt_free_ioctx_ring(struct srpt_ioctx **ioctx_ring,
686{ 693{
687 int i; 694 int i;
688 695
696 if (!ioctx_ring)
697 return;
698
689 for (i = 0; i < ring_size; ++i) 699 for (i = 0; i < ring_size; ++i)
690 srpt_free_ioctx(sdev, ioctx_ring[i], dma_size, dir); 700 srpt_free_ioctx(sdev, ioctx_ring[i], dma_size, dir);
691 kfree(ioctx_ring); 701 kfree(ioctx_ring);
@@ -757,7 +767,7 @@ static bool srpt_test_and_set_cmd_state(struct srpt_send_ioctx *ioctx,
757/** 767/**
758 * srpt_post_recv() - Post an IB receive request. 768 * srpt_post_recv() - Post an IB receive request.
759 */ 769 */
760static int srpt_post_recv(struct srpt_device *sdev, 770static int srpt_post_recv(struct srpt_device *sdev, struct srpt_rdma_ch *ch,
761 struct srpt_recv_ioctx *ioctx) 771 struct srpt_recv_ioctx *ioctx)
762{ 772{
763 struct ib_sge list; 773 struct ib_sge list;
@@ -766,7 +776,7 @@ static int srpt_post_recv(struct srpt_device *sdev,
766 BUG_ON(!sdev); 776 BUG_ON(!sdev);
767 list.addr = ioctx->ioctx.dma; 777 list.addr = ioctx->ioctx.dma;
768 list.length = srp_max_req_size; 778 list.length = srp_max_req_size;
769 list.lkey = sdev->pd->local_dma_lkey; 779 list.lkey = sdev->lkey;
770 780
771 ioctx->ioctx.cqe.done = srpt_recv_done; 781 ioctx->ioctx.cqe.done = srpt_recv_done;
772 wr.wr_cqe = &ioctx->ioctx.cqe; 782 wr.wr_cqe = &ioctx->ioctx.cqe;
@@ -774,7 +784,10 @@ static int srpt_post_recv(struct srpt_device *sdev,
774 wr.sg_list = &list; 784 wr.sg_list = &list;
775 wr.num_sge = 1; 785 wr.num_sge = 1;
776 786
777 return ib_post_srq_recv(sdev->srq, &wr, &bad_wr); 787 if (sdev->use_srq)
788 return ib_post_srq_recv(sdev->srq, &wr, &bad_wr);
789 else
790 return ib_post_recv(ch->qp, &wr, &bad_wr);
778} 791}
779 792
780/** 793/**
@@ -1517,7 +1530,7 @@ static void srpt_handle_new_iu(struct srpt_rdma_ch *ch,
1517 break; 1530 break;
1518 } 1531 }
1519 1532
1520 srpt_post_recv(ch->sport->sdev, recv_ioctx); 1533 srpt_post_recv(ch->sport->sdev, ch, recv_ioctx);
1521 return; 1534 return;
1522 1535
1523out_wait: 1536out_wait:
@@ -1616,7 +1629,7 @@ static int srpt_create_ch_ib(struct srpt_rdma_ch *ch)
1616 struct srpt_device *sdev = sport->sdev; 1629 struct srpt_device *sdev = sport->sdev;
1617 const struct ib_device_attr *attrs = &sdev->device->attrs; 1630 const struct ib_device_attr *attrs = &sdev->device->attrs;
1618 u32 srp_sq_size = sport->port_attrib.srp_sq_size; 1631 u32 srp_sq_size = sport->port_attrib.srp_sq_size;
1619 int ret; 1632 int i, ret;
1620 1633
1621 WARN_ON(ch->rq_size < 1); 1634 WARN_ON(ch->rq_size < 1);
1622 1635
@@ -1640,7 +1653,6 @@ retry:
1640 = (void(*)(struct ib_event *, void*))srpt_qp_event; 1653 = (void(*)(struct ib_event *, void*))srpt_qp_event;
1641 qp_init->send_cq = ch->cq; 1654 qp_init->send_cq = ch->cq;
1642 qp_init->recv_cq = ch->cq; 1655 qp_init->recv_cq = ch->cq;
1643 qp_init->srq = sdev->srq;
1644 qp_init->sq_sig_type = IB_SIGNAL_REQ_WR; 1656 qp_init->sq_sig_type = IB_SIGNAL_REQ_WR;
1645 qp_init->qp_type = IB_QPT_RC; 1657 qp_init->qp_type = IB_QPT_RC;
1646 /* 1658 /*
@@ -1650,10 +1662,16 @@ retry:
1650 * both both, as RDMA contexts will also post completions for the 1662 * both both, as RDMA contexts will also post completions for the
1651 * RDMA READ case. 1663 * RDMA READ case.
1652 */ 1664 */
1653 qp_init->cap.max_send_wr = srp_sq_size / 2; 1665 qp_init->cap.max_send_wr = min(srp_sq_size / 2, attrs->max_qp_wr + 0U);
1654 qp_init->cap.max_rdma_ctxs = srp_sq_size / 2; 1666 qp_init->cap.max_rdma_ctxs = srp_sq_size / 2;
1655 qp_init->cap.max_send_sge = min(attrs->max_sge, SRPT_MAX_SG_PER_WQE); 1667 qp_init->cap.max_send_sge = min(attrs->max_sge, SRPT_MAX_SG_PER_WQE);
1656 qp_init->port_num = ch->sport->port; 1668 qp_init->port_num = ch->sport->port;
1669 if (sdev->use_srq) {
1670 qp_init->srq = sdev->srq;
1671 } else {
1672 qp_init->cap.max_recv_wr = ch->rq_size;
1673 qp_init->cap.max_recv_sge = qp_init->cap.max_send_sge;
1674 }
1657 1675
1658 ch->qp = ib_create_qp(sdev->pd, qp_init); 1676 ch->qp = ib_create_qp(sdev->pd, qp_init);
1659 if (IS_ERR(ch->qp)) { 1677 if (IS_ERR(ch->qp)) {
@@ -1679,6 +1697,10 @@ retry:
1679 if (ret) 1697 if (ret)
1680 goto err_destroy_qp; 1698 goto err_destroy_qp;
1681 1699
1700 if (!sdev->use_srq)
1701 for (i = 0; i < ch->rq_size; i++)
1702 srpt_post_recv(sdev, ch, ch->ioctx_recv_ring[i]);
1703
1682out: 1704out:
1683 kfree(qp_init); 1705 kfree(qp_init);
1684 return ret; 1706 return ret;
@@ -1765,19 +1787,65 @@ static int srpt_disconnect_ch(struct srpt_rdma_ch *ch)
1765 return ret; 1787 return ret;
1766} 1788}
1767 1789
1768static void __srpt_close_all_ch(struct srpt_device *sdev) 1790/*
1791 * Send DREQ and wait for DREP. Return true if and only if this function
1792 * changed the state of @ch.
1793 */
1794static bool srpt_disconnect_ch_sync(struct srpt_rdma_ch *ch)
1795 __must_hold(&sdev->mutex)
1769{ 1796{
1797 DECLARE_COMPLETION_ONSTACK(release_done);
1798 struct srpt_device *sdev = ch->sport->sdev;
1799 bool wait;
1800
1801 lockdep_assert_held(&sdev->mutex);
1802
1803 pr_debug("ch %s-%d state %d\n", ch->sess_name, ch->qp->qp_num,
1804 ch->state);
1805
1806 WARN_ON(ch->release_done);
1807 ch->release_done = &release_done;
1808 wait = !list_empty(&ch->list);
1809 srpt_disconnect_ch(ch);
1810 mutex_unlock(&sdev->mutex);
1811
1812 if (!wait)
1813 goto out;
1814
1815 while (wait_for_completion_timeout(&release_done, 180 * HZ) == 0)
1816 pr_info("%s(%s-%d state %d): still waiting ...\n", __func__,
1817 ch->sess_name, ch->qp->qp_num, ch->state);
1818
1819out:
1820 mutex_lock(&sdev->mutex);
1821 return wait;
1822}
1823
1824static void srpt_set_enabled(struct srpt_port *sport, bool enabled)
1825 __must_hold(&sdev->mutex)
1826{
1827 struct srpt_device *sdev = sport->sdev;
1770 struct srpt_rdma_ch *ch; 1828 struct srpt_rdma_ch *ch;
1771 1829
1772 lockdep_assert_held(&sdev->mutex); 1830 lockdep_assert_held(&sdev->mutex);
1773 1831
1832 if (sport->enabled == enabled)
1833 return;
1834 sport->enabled = enabled;
1835 if (sport->enabled)
1836 return;
1837
1838again:
1774 list_for_each_entry(ch, &sdev->rch_list, list) { 1839 list_for_each_entry(ch, &sdev->rch_list, list) {
1775 if (srpt_disconnect_ch(ch) >= 0) 1840 if (ch->sport == sport) {
1776 pr_info("Closing channel %s-%d because target %s has been disabled\n", 1841 pr_info("%s: closing channel %s-%d\n",
1777 ch->sess_name, ch->qp->qp_num, 1842 sdev->device->name, ch->sess_name,
1778 sdev->device->name); 1843 ch->qp->qp_num);
1779 srpt_close_ch(ch); 1844 if (srpt_disconnect_ch_sync(ch))
1845 goto again;
1846 }
1780 } 1847 }
1848
1781} 1849}
1782 1850
1783static void srpt_free_ch(struct kref *kref) 1851static void srpt_free_ch(struct kref *kref)
@@ -1818,6 +1886,10 @@ static void srpt_release_channel_work(struct work_struct *w)
1818 ch->sport->sdev, ch->rq_size, 1886 ch->sport->sdev, ch->rq_size,
1819 ch->rsp_size, DMA_TO_DEVICE); 1887 ch->rsp_size, DMA_TO_DEVICE);
1820 1888
1889 srpt_free_ioctx_ring((struct srpt_ioctx **)ch->ioctx_recv_ring,
1890 sdev, ch->rq_size,
1891 srp_max_req_size, DMA_FROM_DEVICE);
1892
1821 mutex_lock(&sdev->mutex); 1893 mutex_lock(&sdev->mutex);
1822 list_del_init(&ch->list); 1894 list_del_init(&ch->list);
1823 if (ch->release_done) 1895 if (ch->release_done)
@@ -1953,10 +2025,11 @@ static int srpt_cm_req_recv(struct ib_cm_id *cm_id,
1953 ch->cm_id = cm_id; 2025 ch->cm_id = cm_id;
1954 cm_id->context = ch; 2026 cm_id->context = ch;
1955 /* 2027 /*
1956 * Avoid QUEUE_FULL conditions by limiting the number of buffers used 2028 * ch->rq_size should be at least as large as the initiator queue
1957 * for the SRP protocol to the command queue size. 2029 * depth to avoid that the initiator driver has to report QUEUE_FULL
2030 * to the SCSI mid-layer.
1958 */ 2031 */
1959 ch->rq_size = SRPT_RQ_SIZE; 2032 ch->rq_size = min(SRPT_RQ_SIZE, sdev->device->attrs.max_qp_wr);
1960 spin_lock_init(&ch->spinlock); 2033 spin_lock_init(&ch->spinlock);
1961 ch->state = CH_CONNECTING; 2034 ch->state = CH_CONNECTING;
1962 INIT_LIST_HEAD(&ch->cmd_wait_list); 2035 INIT_LIST_HEAD(&ch->cmd_wait_list);
@@ -1974,6 +2047,19 @@ static int srpt_cm_req_recv(struct ib_cm_id *cm_id,
1974 ch->ioctx_ring[i]->ch = ch; 2047 ch->ioctx_ring[i]->ch = ch;
1975 list_add_tail(&ch->ioctx_ring[i]->free_list, &ch->free_list); 2048 list_add_tail(&ch->ioctx_ring[i]->free_list, &ch->free_list);
1976 } 2049 }
2050 if (!sdev->use_srq) {
2051 ch->ioctx_recv_ring = (struct srpt_recv_ioctx **)
2052 srpt_alloc_ioctx_ring(ch->sport->sdev, ch->rq_size,
2053 sizeof(*ch->ioctx_recv_ring[0]),
2054 srp_max_req_size,
2055 DMA_FROM_DEVICE);
2056 if (!ch->ioctx_recv_ring) {
2057 pr_err("rejected SRP_LOGIN_REQ because creating a new QP RQ ring failed.\n");
2058 rej->reason =
2059 cpu_to_be32(SRP_LOGIN_REJ_INSUFFICIENT_RESOURCES);
2060 goto free_ring;
2061 }
2062 }
1977 2063
1978 ret = srpt_create_ch_ib(ch); 2064 ret = srpt_create_ch_ib(ch);
1979 if (ret) { 2065 if (ret) {
@@ -1981,7 +2067,7 @@ static int srpt_cm_req_recv(struct ib_cm_id *cm_id,
1981 SRP_LOGIN_REJ_INSUFFICIENT_RESOURCES); 2067 SRP_LOGIN_REJ_INSUFFICIENT_RESOURCES);
1982 pr_err("rejected SRP_LOGIN_REQ because creating" 2068 pr_err("rejected SRP_LOGIN_REQ because creating"
1983 " a new RDMA channel failed.\n"); 2069 " a new RDMA channel failed.\n");
1984 goto free_ring; 2070 goto free_recv_ring;
1985 } 2071 }
1986 2072
1987 ret = srpt_ch_qp_rtr(ch, ch->qp); 2073 ret = srpt_ch_qp_rtr(ch, ch->qp);
@@ -2072,6 +2158,11 @@ release_channel:
2072destroy_ib: 2158destroy_ib:
2073 srpt_destroy_ch_ib(ch); 2159 srpt_destroy_ch_ib(ch);
2074 2160
2161free_recv_ring:
2162 srpt_free_ioctx_ring((struct srpt_ioctx **)ch->ioctx_recv_ring,
2163 ch->sport->sdev, ch->rq_size,
2164 srp_max_req_size, DMA_FROM_DEVICE);
2165
2075free_ring: 2166free_ring:
2076 srpt_free_ioctx_ring((struct srpt_ioctx **)ch->ioctx_ring, 2167 srpt_free_ioctx_ring((struct srpt_ioctx **)ch->ioctx_ring,
2077 ch->sport->sdev, ch->rq_size, 2168 ch->sport->sdev, ch->rq_size,
@@ -2342,7 +2433,7 @@ static void srpt_queue_response(struct se_cmd *cmd)
2342 2433
2343 sge.addr = ioctx->ioctx.dma; 2434 sge.addr = ioctx->ioctx.dma;
2344 sge.length = resp_len; 2435 sge.length = resp_len;
2345 sge.lkey = sdev->pd->local_dma_lkey; 2436 sge.lkey = sdev->lkey;
2346 2437
2347 ioctx->ioctx.cqe.done = srpt_send_done; 2438 ioctx->ioctx.cqe.done = srpt_send_done;
2348 send_wr.next = NULL; 2439 send_wr.next = NULL;
@@ -2417,8 +2508,7 @@ static int srpt_release_sdev(struct srpt_device *sdev)
2417 2508
2418 mutex_lock(&sdev->mutex); 2509 mutex_lock(&sdev->mutex);
2419 for (i = 0; i < ARRAY_SIZE(sdev->port); i++) 2510 for (i = 0; i < ARRAY_SIZE(sdev->port); i++)
2420 sdev->port[i].enabled = false; 2511 srpt_set_enabled(&sdev->port[i], false);
2421 __srpt_close_all_ch(sdev);
2422 mutex_unlock(&sdev->mutex); 2512 mutex_unlock(&sdev->mutex);
2423 2513
2424 res = wait_event_interruptible(sdev->ch_releaseQ, 2514 res = wait_event_interruptible(sdev->ch_releaseQ,
@@ -2465,6 +2555,74 @@ static struct se_wwn *srpt_lookup_wwn(const char *name)
2465 return wwn; 2555 return wwn;
2466} 2556}
2467 2557
2558static void srpt_free_srq(struct srpt_device *sdev)
2559{
2560 if (!sdev->srq)
2561 return;
2562
2563 ib_destroy_srq(sdev->srq);
2564 srpt_free_ioctx_ring((struct srpt_ioctx **)sdev->ioctx_ring, sdev,
2565 sdev->srq_size, srp_max_req_size, DMA_FROM_DEVICE);
2566 sdev->srq = NULL;
2567}
2568
2569static int srpt_alloc_srq(struct srpt_device *sdev)
2570{
2571 struct ib_srq_init_attr srq_attr = {
2572 .event_handler = srpt_srq_event,
2573 .srq_context = (void *)sdev,
2574 .attr.max_wr = sdev->srq_size,
2575 .attr.max_sge = 1,
2576 .srq_type = IB_SRQT_BASIC,
2577 };
2578 struct ib_device *device = sdev->device;
2579 struct ib_srq *srq;
2580 int i;
2581
2582 WARN_ON_ONCE(sdev->srq);
2583 srq = ib_create_srq(sdev->pd, &srq_attr);
2584 if (IS_ERR(srq)) {
2585 pr_debug("ib_create_srq() failed: %ld\n", PTR_ERR(srq));
2586 return PTR_ERR(srq);
2587 }
2588
2589 pr_debug("create SRQ #wr= %d max_allow=%d dev= %s\n", sdev->srq_size,
2590 sdev->device->attrs.max_srq_wr, device->name);
2591
2592 sdev->ioctx_ring = (struct srpt_recv_ioctx **)
2593 srpt_alloc_ioctx_ring(sdev, sdev->srq_size,
2594 sizeof(*sdev->ioctx_ring[0]),
2595 srp_max_req_size, DMA_FROM_DEVICE);
2596 if (!sdev->ioctx_ring) {
2597 ib_destroy_srq(srq);
2598 return -ENOMEM;
2599 }
2600
2601 sdev->use_srq = true;
2602 sdev->srq = srq;
2603
2604 for (i = 0; i < sdev->srq_size; ++i)
2605 srpt_post_recv(sdev, NULL, sdev->ioctx_ring[i]);
2606
2607 return 0;
2608}
2609
2610static int srpt_use_srq(struct srpt_device *sdev, bool use_srq)
2611{
2612 struct ib_device *device = sdev->device;
2613 int ret = 0;
2614
2615 if (!use_srq) {
2616 srpt_free_srq(sdev);
2617 sdev->use_srq = false;
2618 } else if (use_srq && !sdev->srq) {
2619 ret = srpt_alloc_srq(sdev);
2620 }
2621 pr_debug("%s(%s): use_srq = %d; ret = %d\n", __func__, device->name,
2622 sdev->use_srq, ret);
2623 return ret;
2624}
2625
2468/** 2626/**
2469 * srpt_add_one() - Infiniband device addition callback function. 2627 * srpt_add_one() - Infiniband device addition callback function.
2470 */ 2628 */
@@ -2472,7 +2630,6 @@ static void srpt_add_one(struct ib_device *device)
2472{ 2630{
2473 struct srpt_device *sdev; 2631 struct srpt_device *sdev;
2474 struct srpt_port *sport; 2632 struct srpt_port *sport;
2475 struct ib_srq_init_attr srq_attr;
2476 int i; 2633 int i;
2477 2634
2478 pr_debug("device = %p\n", device); 2635 pr_debug("device = %p\n", device);
@@ -2490,29 +2647,18 @@ static void srpt_add_one(struct ib_device *device)
2490 if (IS_ERR(sdev->pd)) 2647 if (IS_ERR(sdev->pd))
2491 goto free_dev; 2648 goto free_dev;
2492 2649
2493 sdev->srq_size = min(srpt_srq_size, sdev->device->attrs.max_srq_wr); 2650 sdev->lkey = sdev->pd->local_dma_lkey;
2494
2495 srq_attr.event_handler = srpt_srq_event;
2496 srq_attr.srq_context = (void *)sdev;
2497 srq_attr.attr.max_wr = sdev->srq_size;
2498 srq_attr.attr.max_sge = 1;
2499 srq_attr.attr.srq_limit = 0;
2500 srq_attr.srq_type = IB_SRQT_BASIC;
2501 2651
2502 sdev->srq = ib_create_srq(sdev->pd, &srq_attr); 2652 sdev->srq_size = min(srpt_srq_size, sdev->device->attrs.max_srq_wr);
2503 if (IS_ERR(sdev->srq))
2504 goto err_pd;
2505 2653
2506 pr_debug("%s: create SRQ #wr= %d max_allow=%d dev= %s\n", 2654 srpt_use_srq(sdev, sdev->port[0].port_attrib.use_srq);
2507 __func__, sdev->srq_size, sdev->device->attrs.max_srq_wr,
2508 device->name);
2509 2655
2510 if (!srpt_service_guid) 2656 if (!srpt_service_guid)
2511 srpt_service_guid = be64_to_cpu(device->node_guid); 2657 srpt_service_guid = be64_to_cpu(device->node_guid);
2512 2658
2513 sdev->cm_id = ib_create_cm_id(device, srpt_cm_handler, sdev); 2659 sdev->cm_id = ib_create_cm_id(device, srpt_cm_handler, sdev);
2514 if (IS_ERR(sdev->cm_id)) 2660 if (IS_ERR(sdev->cm_id))
2515 goto err_srq; 2661 goto err_ring;
2516 2662
2517 /* print out target login information */ 2663 /* print out target login information */
2518 pr_debug("Target login info: id_ext=%016llx,ioc_guid=%016llx," 2664 pr_debug("Target login info: id_ext=%016llx,ioc_guid=%016llx,"
@@ -2532,16 +2678,6 @@ static void srpt_add_one(struct ib_device *device)
2532 srpt_event_handler); 2678 srpt_event_handler);
2533 ib_register_event_handler(&sdev->event_handler); 2679 ib_register_event_handler(&sdev->event_handler);
2534 2680
2535 sdev->ioctx_ring = (struct srpt_recv_ioctx **)
2536 srpt_alloc_ioctx_ring(sdev, sdev->srq_size,
2537 sizeof(*sdev->ioctx_ring[0]),
2538 srp_max_req_size, DMA_FROM_DEVICE);
2539 if (!sdev->ioctx_ring)
2540 goto err_event;
2541
2542 for (i = 0; i < sdev->srq_size; ++i)
2543 srpt_post_recv(sdev, sdev->ioctx_ring[i]);
2544
2545 WARN_ON(sdev->device->phys_port_cnt > ARRAY_SIZE(sdev->port)); 2681 WARN_ON(sdev->device->phys_port_cnt > ARRAY_SIZE(sdev->port));
2546 2682
2547 for (i = 1; i <= sdev->device->phys_port_cnt; i++) { 2683 for (i = 1; i <= sdev->device->phys_port_cnt; i++) {
@@ -2551,12 +2687,13 @@ static void srpt_add_one(struct ib_device *device)
2551 sport->port_attrib.srp_max_rdma_size = DEFAULT_MAX_RDMA_SIZE; 2687 sport->port_attrib.srp_max_rdma_size = DEFAULT_MAX_RDMA_SIZE;
2552 sport->port_attrib.srp_max_rsp_size = DEFAULT_MAX_RSP_SIZE; 2688 sport->port_attrib.srp_max_rsp_size = DEFAULT_MAX_RSP_SIZE;
2553 sport->port_attrib.srp_sq_size = DEF_SRPT_SQ_SIZE; 2689 sport->port_attrib.srp_sq_size = DEF_SRPT_SQ_SIZE;
2690 sport->port_attrib.use_srq = false;
2554 INIT_WORK(&sport->work, srpt_refresh_port_work); 2691 INIT_WORK(&sport->work, srpt_refresh_port_work);
2555 2692
2556 if (srpt_refresh_port(sport)) { 2693 if (srpt_refresh_port(sport)) {
2557 pr_err("MAD registration failed for %s-%d.\n", 2694 pr_err("MAD registration failed for %s-%d.\n",
2558 sdev->device->name, i); 2695 sdev->device->name, i);
2559 goto err_ring; 2696 goto err_event;
2560 } 2697 }
2561 } 2698 }
2562 2699
@@ -2569,17 +2706,12 @@ out:
2569 pr_debug("added %s.\n", device->name); 2706 pr_debug("added %s.\n", device->name);
2570 return; 2707 return;
2571 2708
2572err_ring:
2573 srpt_free_ioctx_ring((struct srpt_ioctx **)sdev->ioctx_ring, sdev,
2574 sdev->srq_size, srp_max_req_size,
2575 DMA_FROM_DEVICE);
2576err_event: 2709err_event:
2577 ib_unregister_event_handler(&sdev->event_handler); 2710 ib_unregister_event_handler(&sdev->event_handler);
2578err_cm: 2711err_cm:
2579 ib_destroy_cm_id(sdev->cm_id); 2712 ib_destroy_cm_id(sdev->cm_id);
2580err_srq: 2713err_ring:
2581 ib_destroy_srq(sdev->srq); 2714 srpt_free_srq(sdev);
2582err_pd:
2583 ib_dealloc_pd(sdev->pd); 2715 ib_dealloc_pd(sdev->pd);
2584free_dev: 2716free_dev:
2585 kfree(sdev); 2717 kfree(sdev);
@@ -2622,12 +2754,10 @@ static void srpt_remove_one(struct ib_device *device, void *client_data)
2622 spin_unlock(&srpt_dev_lock); 2754 spin_unlock(&srpt_dev_lock);
2623 srpt_release_sdev(sdev); 2755 srpt_release_sdev(sdev);
2624 2756
2625 ib_destroy_srq(sdev->srq); 2757 srpt_free_srq(sdev);
2758
2626 ib_dealloc_pd(sdev->pd); 2759 ib_dealloc_pd(sdev->pd);
2627 2760
2628 srpt_free_ioctx_ring((struct srpt_ioctx **)sdev->ioctx_ring, sdev,
2629 sdev->srq_size, srp_max_req_size, DMA_FROM_DEVICE);
2630 sdev->ioctx_ring = NULL;
2631 kfree(sdev); 2761 kfree(sdev);
2632} 2762}
2633 2763
@@ -2706,27 +2836,12 @@ static void srpt_release_cmd(struct se_cmd *se_cmd)
2706 */ 2836 */
2707static void srpt_close_session(struct se_session *se_sess) 2837static void srpt_close_session(struct se_session *se_sess)
2708{ 2838{
2709 DECLARE_COMPLETION_ONSTACK(release_done);
2710 struct srpt_rdma_ch *ch = se_sess->fabric_sess_ptr; 2839 struct srpt_rdma_ch *ch = se_sess->fabric_sess_ptr;
2711 struct srpt_device *sdev = ch->sport->sdev; 2840 struct srpt_device *sdev = ch->sport->sdev;
2712 bool wait;
2713
2714 pr_debug("ch %s-%d state %d\n", ch->sess_name, ch->qp->qp_num,
2715 ch->state);
2716 2841
2717 mutex_lock(&sdev->mutex); 2842 mutex_lock(&sdev->mutex);
2718 BUG_ON(ch->release_done); 2843 srpt_disconnect_ch_sync(ch);
2719 ch->release_done = &release_done;
2720 wait = !list_empty(&ch->list);
2721 srpt_disconnect_ch(ch);
2722 mutex_unlock(&sdev->mutex); 2844 mutex_unlock(&sdev->mutex);
2723
2724 if (!wait)
2725 return;
2726
2727 while (wait_for_completion_timeout(&release_done, 180 * HZ) == 0)
2728 pr_info("%s(%s-%d state %d): still waiting ...\n", __func__,
2729 ch->sess_name, ch->qp->qp_num, ch->state);
2730} 2845}
2731 2846
2732/** 2847/**
@@ -2777,7 +2892,7 @@ static int srpt_parse_i_port_id(u8 i_port_id[16], const char *name)
2777{ 2892{
2778 const char *p; 2893 const char *p;
2779 unsigned len, count, leading_zero_bytes; 2894 unsigned len, count, leading_zero_bytes;
2780 int ret, rc; 2895 int ret;
2781 2896
2782 p = name; 2897 p = name;
2783 if (strncasecmp(p, "0x", 2) == 0) 2898 if (strncasecmp(p, "0x", 2) == 0)
@@ -2789,10 +2904,9 @@ static int srpt_parse_i_port_id(u8 i_port_id[16], const char *name)
2789 count = min(len / 2, 16U); 2904 count = min(len / 2, 16U);
2790 leading_zero_bytes = 16 - count; 2905 leading_zero_bytes = 16 - count;
2791 memset(i_port_id, 0, leading_zero_bytes); 2906 memset(i_port_id, 0, leading_zero_bytes);
2792 rc = hex2bin(i_port_id + leading_zero_bytes, p, count); 2907 ret = hex2bin(i_port_id + leading_zero_bytes, p, count);
2793 if (rc < 0) 2908 if (ret < 0)
2794 pr_debug("hex2bin failed for srpt_parse_i_port_id: %d\n", rc); 2909 pr_debug("hex2bin failed for srpt_parse_i_port_id: %d\n", ret);
2795 ret = 0;
2796out: 2910out:
2797 return ret; 2911 return ret;
2798} 2912}
@@ -2926,14 +3040,55 @@ static ssize_t srpt_tpg_attrib_srp_sq_size_store(struct config_item *item,
2926 return count; 3040 return count;
2927} 3041}
2928 3042
3043static ssize_t srpt_tpg_attrib_use_srq_show(struct config_item *item,
3044 char *page)
3045{
3046 struct se_portal_group *se_tpg = attrib_to_tpg(item);
3047 struct srpt_port *sport = srpt_tpg_to_sport(se_tpg);
3048
3049 return sprintf(page, "%d\n", sport->port_attrib.use_srq);
3050}
3051
3052static ssize_t srpt_tpg_attrib_use_srq_store(struct config_item *item,
3053 const char *page, size_t count)
3054{
3055 struct se_portal_group *se_tpg = attrib_to_tpg(item);
3056 struct srpt_port *sport = srpt_tpg_to_sport(se_tpg);
3057 struct srpt_device *sdev = sport->sdev;
3058 unsigned long val;
3059 bool enabled;
3060 int ret;
3061
3062 ret = kstrtoul(page, 0, &val);
3063 if (ret < 0)
3064 return ret;
3065 if (val != !!val)
3066 return -EINVAL;
3067
3068 ret = mutex_lock_interruptible(&sdev->mutex);
3069 if (ret < 0)
3070 return ret;
3071 enabled = sport->enabled;
3072 /* Log out all initiator systems before changing 'use_srq'. */
3073 srpt_set_enabled(sport, false);
3074 sport->port_attrib.use_srq = val;
3075 srpt_use_srq(sdev, sport->port_attrib.use_srq);
3076 srpt_set_enabled(sport, enabled);
3077 mutex_unlock(&sdev->mutex);
3078
3079 return count;
3080}
3081
2929CONFIGFS_ATTR(srpt_tpg_attrib_, srp_max_rdma_size); 3082CONFIGFS_ATTR(srpt_tpg_attrib_, srp_max_rdma_size);
2930CONFIGFS_ATTR(srpt_tpg_attrib_, srp_max_rsp_size); 3083CONFIGFS_ATTR(srpt_tpg_attrib_, srp_max_rsp_size);
2931CONFIGFS_ATTR(srpt_tpg_attrib_, srp_sq_size); 3084CONFIGFS_ATTR(srpt_tpg_attrib_, srp_sq_size);
3085CONFIGFS_ATTR(srpt_tpg_attrib_, use_srq);
2932 3086
2933static struct configfs_attribute *srpt_tpg_attrib_attrs[] = { 3087static struct configfs_attribute *srpt_tpg_attrib_attrs[] = {
2934 &srpt_tpg_attrib_attr_srp_max_rdma_size, 3088 &srpt_tpg_attrib_attr_srp_max_rdma_size,
2935 &srpt_tpg_attrib_attr_srp_max_rsp_size, 3089 &srpt_tpg_attrib_attr_srp_max_rsp_size,
2936 &srpt_tpg_attrib_attr_srp_sq_size, 3090 &srpt_tpg_attrib_attr_srp_sq_size,
3091 &srpt_tpg_attrib_attr_use_srq,
2937 NULL, 3092 NULL,
2938}; 3093};
2939 3094
@@ -2951,7 +3106,6 @@ static ssize_t srpt_tpg_enable_store(struct config_item *item,
2951 struct se_portal_group *se_tpg = to_tpg(item); 3106 struct se_portal_group *se_tpg = to_tpg(item);
2952 struct srpt_port *sport = srpt_tpg_to_sport(se_tpg); 3107 struct srpt_port *sport = srpt_tpg_to_sport(se_tpg);
2953 struct srpt_device *sdev = sport->sdev; 3108 struct srpt_device *sdev = sport->sdev;
2954 struct srpt_rdma_ch *ch;
2955 unsigned long tmp; 3109 unsigned long tmp;
2956 int ret; 3110 int ret;
2957 3111
@@ -2965,24 +3119,11 @@ static ssize_t srpt_tpg_enable_store(struct config_item *item,
2965 pr_err("Illegal value for srpt_tpg_store_enable: %lu\n", tmp); 3119 pr_err("Illegal value for srpt_tpg_store_enable: %lu\n", tmp);
2966 return -EINVAL; 3120 return -EINVAL;
2967 } 3121 }
2968 if (sport->enabled == tmp)
2969 goto out;
2970 sport->enabled = tmp;
2971 if (sport->enabled)
2972 goto out;
2973 3122
2974 mutex_lock(&sdev->mutex); 3123 mutex_lock(&sdev->mutex);
2975 list_for_each_entry(ch, &sdev->rch_list, list) { 3124 srpt_set_enabled(sport, tmp);
2976 if (ch->sport == sport) {
2977 pr_debug("%s: ch %p %s-%d\n", __func__, ch,
2978 ch->sess_name, ch->qp->qp_num);
2979 srpt_disconnect_ch(ch);
2980 srpt_close_ch(ch);
2981 }
2982 }
2983 mutex_unlock(&sdev->mutex); 3125 mutex_unlock(&sdev->mutex);
2984 3126
2985out:
2986 return count; 3127 return count;
2987} 3128}
2988 3129
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.h b/drivers/infiniband/ulp/srpt/ib_srpt.h
index 1b817e51b84b..673387d365a3 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.h
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.h
@@ -252,6 +252,7 @@ enum rdma_ch_state {
252 * @free_list: Head of list with free send I/O contexts. 252 * @free_list: Head of list with free send I/O contexts.
253 * @state: channel state. See also enum rdma_ch_state. 253 * @state: channel state. See also enum rdma_ch_state.
254 * @ioctx_ring: Send ring. 254 * @ioctx_ring: Send ring.
255 * @ioctx_recv_ring: Receive I/O context ring.
255 * @list: Node for insertion in the srpt_device.rch_list list. 256 * @list: Node for insertion in the srpt_device.rch_list list.
256 * @cmd_wait_list: List of SCSI commands that arrived before the RTU event. This 257 * @cmd_wait_list: List of SCSI commands that arrived before the RTU event. This
257 * list contains struct srpt_ioctx elements and is protected 258 * list contains struct srpt_ioctx elements and is protected
@@ -281,6 +282,7 @@ struct srpt_rdma_ch {
281 struct list_head free_list; 282 struct list_head free_list;
282 enum rdma_ch_state state; 283 enum rdma_ch_state state;
283 struct srpt_send_ioctx **ioctx_ring; 284 struct srpt_send_ioctx **ioctx_ring;
285 struct srpt_recv_ioctx **ioctx_recv_ring;
284 struct list_head list; 286 struct list_head list;
285 struct list_head cmd_wait_list; 287 struct list_head cmd_wait_list;
286 struct se_session *sess; 288 struct se_session *sess;
@@ -295,11 +297,13 @@ struct srpt_rdma_ch {
295 * @srp_max_rdma_size: Maximum size of SRP RDMA transfers for new connections. 297 * @srp_max_rdma_size: Maximum size of SRP RDMA transfers for new connections.
296 * @srp_max_rsp_size: Maximum size of SRP response messages in bytes. 298 * @srp_max_rsp_size: Maximum size of SRP response messages in bytes.
297 * @srp_sq_size: Shared receive queue (SRQ) size. 299 * @srp_sq_size: Shared receive queue (SRQ) size.
300 * @use_srq: Whether or not to use SRQ.
298 */ 301 */
299struct srpt_port_attrib { 302struct srpt_port_attrib {
300 u32 srp_max_rdma_size; 303 u32 srp_max_rdma_size;
301 u32 srp_max_rsp_size; 304 u32 srp_max_rsp_size;
302 u32 srp_sq_size; 305 u32 srp_sq_size;
306 bool use_srq;
303}; 307};
304 308
305/** 309/**
@@ -343,10 +347,11 @@ struct srpt_port {
343 * struct srpt_device - Information associated by SRPT with a single HCA. 347 * struct srpt_device - Information associated by SRPT with a single HCA.
344 * @device: Backpointer to the struct ib_device managed by the IB core. 348 * @device: Backpointer to the struct ib_device managed by the IB core.
345 * @pd: IB protection domain. 349 * @pd: IB protection domain.
346 * @mr: L_Key (local key) with write access to all local memory. 350 * @lkey: L_Key (local key) with write access to all local memory.
347 * @srq: Per-HCA SRQ (shared receive queue). 351 * @srq: Per-HCA SRQ (shared receive queue).
348 * @cm_id: Connection identifier. 352 * @cm_id: Connection identifier.
349 * @srq_size: SRQ size. 353 * @srq_size: SRQ size.
354 * @use_srq: Whether or not to use SRQ.
350 * @ioctx_ring: Per-HCA SRQ. 355 * @ioctx_ring: Per-HCA SRQ.
351 * @rch_list: Per-device channel list -- see also srpt_rdma_ch.list. 356 * @rch_list: Per-device channel list -- see also srpt_rdma_ch.list.
352 * @ch_releaseQ: Enables waiting for removal from rch_list. 357 * @ch_releaseQ: Enables waiting for removal from rch_list.
@@ -358,9 +363,11 @@ struct srpt_port {
358struct srpt_device { 363struct srpt_device {
359 struct ib_device *device; 364 struct ib_device *device;
360 struct ib_pd *pd; 365 struct ib_pd *pd;
366 u32 lkey;
361 struct ib_srq *srq; 367 struct ib_srq *srq;
362 struct ib_cm_id *cm_id; 368 struct ib_cm_id *cm_id;
363 int srq_size; 369 int srq_size;
370 bool use_srq;
364 struct srpt_recv_ioctx **ioctx_ring; 371 struct srpt_recv_ioctx **ioctx_ring;
365 struct list_head rch_list; 372 struct list_head rch_list;
366 wait_queue_head_t ch_releaseQ; 373 wait_queue_head_t ch_releaseQ;
diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3cdev.h b/drivers/net/ethernet/chelsio/cxgb3/t3cdev.h
index 705713b56636..3c3e6cf6aca6 100644
--- a/drivers/net/ethernet/chelsio/cxgb3/t3cdev.h
+++ b/drivers/net/ethernet/chelsio/cxgb3/t3cdev.h
@@ -60,7 +60,7 @@ struct t3cdev {
60 int (*ctl)(struct t3cdev *dev, unsigned int req, void *data); 60 int (*ctl)(struct t3cdev *dev, unsigned int req, void *data);
61 void (*neigh_update)(struct t3cdev *dev, struct neighbour *neigh); 61 void (*neigh_update)(struct t3cdev *dev, struct neighbour *neigh);
62 void *priv; /* driver private data */ 62 void *priv; /* driver private data */
63 void *l2opt; /* optional layer 2 data */ 63 void __rcu *l2opt; /* optional layer 2 data */
64 void *l3opt; /* optional layer 3 data */ 64 void *l3opt; /* optional layer 3 data */
65 void *l4opt; /* optional layer 4 data */ 65 void *l4opt; /* optional layer 4 data */
66 void *ulp; /* ulp stuff */ 66 void *ulp; /* ulp stuff */
diff --git a/drivers/net/ethernet/mellanox/mlx4/catas.c b/drivers/net/ethernet/mellanox/mlx4/catas.c
index de0f9e5e42ec..e2b6b0cac1ac 100644
--- a/drivers/net/ethernet/mellanox/mlx4/catas.c
+++ b/drivers/net/ethernet/mellanox/mlx4/catas.c
@@ -231,10 +231,10 @@ static void dump_err_buf(struct mlx4_dev *dev)
231 i, swab32(readl(priv->catas_err.map + i))); 231 i, swab32(readl(priv->catas_err.map + i)));
232} 232}
233 233
234static void poll_catas(unsigned long dev_ptr) 234static void poll_catas(struct timer_list *t)
235{ 235{
236 struct mlx4_dev *dev = (struct mlx4_dev *) dev_ptr; 236 struct mlx4_priv *priv = from_timer(priv, t, catas_err.timer);
237 struct mlx4_priv *priv = mlx4_priv(dev); 237 struct mlx4_dev *dev = &priv->dev;
238 u32 slave_read; 238 u32 slave_read;
239 239
240 if (mlx4_is_slave(dev)) { 240 if (mlx4_is_slave(dev)) {
@@ -277,7 +277,7 @@ void mlx4_start_catas_poll(struct mlx4_dev *dev)
277 phys_addr_t addr; 277 phys_addr_t addr;
278 278
279 INIT_LIST_HEAD(&priv->catas_err.list); 279 INIT_LIST_HEAD(&priv->catas_err.list);
280 setup_timer(&priv->catas_err.timer, poll_catas, (unsigned long)dev); 280 timer_setup(&priv->catas_err.timer, poll_catas, 0);
281 priv->catas_err.map = NULL; 281 priv->catas_err.map = NULL;
282 282
283 if (!mlx4_is_slave(dev)) { 283 if (!mlx4_is_slave(dev)) {
diff --git a/drivers/staging/lustre/lnet/Kconfig b/drivers/staging/lustre/lnet/Kconfig
index 2b5930150cda..6bcb53d0c6f4 100644
--- a/drivers/staging/lustre/lnet/Kconfig
+++ b/drivers/staging/lustre/lnet/Kconfig
@@ -34,7 +34,7 @@ config LNET_SELFTEST
34 34
35config LNET_XPRT_IB 35config LNET_XPRT_IB
36 tristate "LNET infiniband support" 36 tristate "LNET infiniband support"
37 depends on LNET && INFINIBAND && INFINIBAND_ADDR_TRANS 37 depends on LNET && PCI && INFINIBAND && INFINIBAND_ADDR_TRANS
38 default LNET && INFINIBAND 38 default LNET && INFINIBAND
39 help 39 help
40 This option allows the LNET users to use infiniband as an 40 This option allows the LNET users to use infiniband as an
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 09cebe528488..508e8cc5ee86 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -136,6 +136,9 @@ enum {
136 MLX4_CQE_BAD_FCS = 1 << 4, 136 MLX4_CQE_BAD_FCS = 1 << 4,
137}; 137};
138 138
139#define MLX4_MAX_CQ_PERIOD (BIT(16) - 1)
140#define MLX4_MAX_CQ_COUNT (BIT(16) - 1)
141
139static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, 142static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
140 void __iomem *uar_page, 143 void __iomem *uar_page,
141 spinlock_t *doorbell_lock) 144 spinlock_t *doorbell_lock)
diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h
index 6a57ec2f1ef7..48c181a2acc9 100644
--- a/include/linux/mlx5/cq.h
+++ b/include/linux/mlx5/cq.h
@@ -125,11 +125,16 @@ struct mlx5_cq_modify_params {
125enum { 125enum {
126 CQE_SIZE_64 = 0, 126 CQE_SIZE_64 = 0,
127 CQE_SIZE_128 = 1, 127 CQE_SIZE_128 = 1,
128 CQE_SIZE_128_PAD = 2,
128}; 129};
129 130
130static inline int cqe_sz_to_mlx_sz(u8 size) 131#define MLX5_MAX_CQ_PERIOD (BIT(__mlx5_bit_sz(cqc, cq_period)) - 1)
132#define MLX5_MAX_CQ_COUNT (BIT(__mlx5_bit_sz(cqc, cq_max_count)) - 1)
133
134static inline int cqe_sz_to_mlx_sz(u8 size, int padding_128_en)
131{ 135{
132 return size == 64 ? CQE_SIZE_64 : CQE_SIZE_128; 136 return padding_128_en ? CQE_SIZE_128_PAD :
137 size == 64 ? CQE_SIZE_64 : CQE_SIZE_128;
133} 138}
134 139
135static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq) 140static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq)
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 3e5363f760dd..38a7577a9ce7 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -614,7 +614,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
614 u8 swp[0x1]; 614 u8 swp[0x1];
615 u8 swp_csum[0x1]; 615 u8 swp_csum[0x1];
616 u8 swp_lso[0x1]; 616 u8 swp_lso[0x1];
617 u8 reserved_at_23[0x1d]; 617 u8 reserved_at_23[0x1b];
618 u8 max_geneve_opt_len[0x1];
619 u8 tunnel_stateless_geneve_rx[0x1];
618 620
619 u8 reserved_at_40[0x10]; 621 u8 reserved_at_40[0x10];
620 u8 lro_min_mss_size[0x10]; 622 u8 lro_min_mss_size[0x10];
@@ -744,6 +746,7 @@ enum {
744 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 746 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
745 MLX5_WQ_TYPE_CYCLIC = 0x1, 747 MLX5_WQ_TYPE_CYCLIC = 0x1,
746 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 748 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
749 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
747}; 750};
748 751
749enum { 752enum {
@@ -1047,7 +1050,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
1047 u8 num_of_uars_per_page[0x20]; 1050 u8 num_of_uars_per_page[0x20];
1048 u8 reserved_at_540[0x40]; 1051 u8 reserved_at_540[0x40];
1049 1052
1050 u8 reserved_at_580[0x3f]; 1053 u8 reserved_at_580[0x3d];
1054 u8 cqe_128_always[0x1];
1055 u8 cqe_compression_128[0x1];
1051 u8 cqe_compression[0x1]; 1056 u8 cqe_compression[0x1];
1052 1057
1053 u8 cqe_compression_timeout[0x10]; 1058 u8 cqe_compression_timeout[0x10];
diff --git a/include/rdma/ib_addr.h b/include/rdma/ib_addr.h
index ec5008cf5d51..18c564f60e93 100644
--- a/include/rdma/ib_addr.h
+++ b/include/rdma/ib_addr.h
@@ -125,8 +125,9 @@ int rdma_resolve_ip_route(struct sockaddr *src_addr,
125 125
126void rdma_addr_cancel(struct rdma_dev_addr *addr); 126void rdma_addr_cancel(struct rdma_dev_addr *addr);
127 127
128int rdma_copy_addr(struct rdma_dev_addr *dev_addr, struct net_device *dev, 128void rdma_copy_addr(struct rdma_dev_addr *dev_addr,
129 const unsigned char *dst_dev_addr); 129 const struct net_device *dev,
130 const unsigned char *dst_dev_addr);
130 131
131int rdma_addr_size(struct sockaddr *addr); 132int rdma_addr_size(struct sockaddr *addr);
132 133
@@ -245,10 +246,11 @@ static inline void rdma_addr_set_dgid(struct rdma_dev_addr *dev_addr, union ib_g
245static inline enum ib_mtu iboe_get_mtu(int mtu) 246static inline enum ib_mtu iboe_get_mtu(int mtu)
246{ 247{
247 /* 248 /*
248 * reduce IB headers from effective IBoE MTU. 28 stands for 249 * Reduce IB headers from effective IBoE MTU.
249 * atomic header which is the biggest possible header after BTH
250 */ 250 */
251 mtu = mtu - IB_GRH_BYTES - IB_BTH_BYTES - 28; 251 mtu = mtu - (IB_GRH_BYTES + IB_UDP_BYTES + IB_BTH_BYTES +
252 IB_EXT_XRC_BYTES + IB_EXT_ATOMICETH_BYTES +
253 IB_ICRC_BYTES);
252 254
253 if (mtu >= ib_mtu_enum_to_int(IB_MTU_4096)) 255 if (mtu >= ib_mtu_enum_to_int(IB_MTU_4096))
254 return IB_MTU_4096; 256 return IB_MTU_4096;
@@ -305,12 +307,12 @@ static inline void rdma_get_ll_mac(struct in6_addr *addr, u8 *mac)
305 307
306static inline int rdma_is_multicast_addr(struct in6_addr *addr) 308static inline int rdma_is_multicast_addr(struct in6_addr *addr)
307{ 309{
308 u32 ipv4_addr; 310 __be32 ipv4_addr;
309 311
310 if (addr->s6_addr[0] == 0xff) 312 if (addr->s6_addr[0] == 0xff)
311 return 1; 313 return 1;
312 314
313 memcpy(&ipv4_addr, addr->s6_addr + 12, 4); 315 ipv4_addr = addr->s6_addr32[3];
314 return (ipv6_addr_v4mapped(addr) && ipv4_is_multicast(ipv4_addr)); 316 return (ipv6_addr_v4mapped(addr) && ipv4_is_multicast(ipv4_addr));
315} 317}
316 318
diff --git a/include/rdma/ib_pack.h b/include/rdma/ib_pack.h
index 36655899ee02..7ea1382ad0e5 100644
--- a/include/rdma/ib_pack.h
+++ b/include/rdma/ib_pack.h
@@ -37,14 +37,17 @@
37#include <uapi/linux/if_ether.h> 37#include <uapi/linux/if_ether.h>
38 38
39enum { 39enum {
40 IB_LRH_BYTES = 8, 40 IB_LRH_BYTES = 8,
41 IB_ETH_BYTES = 14, 41 IB_ETH_BYTES = 14,
42 IB_VLAN_BYTES = 4, 42 IB_VLAN_BYTES = 4,
43 IB_GRH_BYTES = 40, 43 IB_GRH_BYTES = 40,
44 IB_IP4_BYTES = 20, 44 IB_IP4_BYTES = 20,
45 IB_UDP_BYTES = 8, 45 IB_UDP_BYTES = 8,
46 IB_BTH_BYTES = 12, 46 IB_BTH_BYTES = 12,
47 IB_DETH_BYTES = 8 47 IB_DETH_BYTES = 8,
48 IB_EXT_ATOMICETH_BYTES = 28,
49 IB_EXT_XRC_BYTES = 4,
50 IB_ICRC_BYTES = 4
48}; 51};
49 52
50struct ib_field { 53struct ib_field {
diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h
index 355b81f4242d..1f7f604db5aa 100644
--- a/include/rdma/ib_sa.h
+++ b/include/rdma/ib_sa.h
@@ -590,20 +590,20 @@ static inline bool sa_path_is_roce(struct sa_path_rec *rec)
590 (rec->rec_type == SA_PATH_REC_TYPE_ROCE_V2)); 590 (rec->rec_type == SA_PATH_REC_TYPE_ROCE_V2));
591} 591}
592 592
593static inline void sa_path_set_slid(struct sa_path_rec *rec, __be32 slid) 593static inline void sa_path_set_slid(struct sa_path_rec *rec, u32 slid)
594{ 594{
595 if (rec->rec_type == SA_PATH_REC_TYPE_IB) 595 if (rec->rec_type == SA_PATH_REC_TYPE_IB)
596 rec->ib.slid = htons(ntohl(slid)); 596 rec->ib.slid = cpu_to_be16(slid);
597 else if (rec->rec_type == SA_PATH_REC_TYPE_OPA) 597 else if (rec->rec_type == SA_PATH_REC_TYPE_OPA)
598 rec->opa.slid = slid; 598 rec->opa.slid = cpu_to_be32(slid);
599} 599}
600 600
601static inline void sa_path_set_dlid(struct sa_path_rec *rec, __be32 dlid) 601static inline void sa_path_set_dlid(struct sa_path_rec *rec, u32 dlid)
602{ 602{
603 if (rec->rec_type == SA_PATH_REC_TYPE_IB) 603 if (rec->rec_type == SA_PATH_REC_TYPE_IB)
604 rec->ib.dlid = htons(ntohl(dlid)); 604 rec->ib.dlid = cpu_to_be16(dlid);
605 else if (rec->rec_type == SA_PATH_REC_TYPE_OPA) 605 else if (rec->rec_type == SA_PATH_REC_TYPE_OPA)
606 rec->opa.dlid = dlid; 606 rec->opa.dlid = cpu_to_be32(dlid);
607} 607}
608 608
609static inline void sa_path_set_raw_traffic(struct sa_path_rec *rec, 609static inline void sa_path_set_raw_traffic(struct sa_path_rec *rec,
diff --git a/include/rdma/ib_umem_odp.h b/include/rdma/ib_umem_odp.h
index 5eb7f5bc8248..6a17f856f841 100644
--- a/include/rdma/ib_umem_odp.h
+++ b/include/rdma/ib_umem_odp.h
@@ -111,10 +111,6 @@ int ib_umem_odp_map_dma_pages(struct ib_umem *umem, u64 start_offset, u64 bcnt,
111void ib_umem_odp_unmap_dma_pages(struct ib_umem *umem, u64 start_offset, 111void ib_umem_odp_unmap_dma_pages(struct ib_umem *umem, u64 start_offset,
112 u64 bound); 112 u64 bound);
113 113
114void rbt_ib_umem_insert(struct umem_odp_node *node,
115 struct rb_root_cached *root);
116void rbt_ib_umem_remove(struct umem_odp_node *node,
117 struct rb_root_cached *root);
118typedef int (*umem_call_back)(struct ib_umem *item, u64 start, u64 end, 114typedef int (*umem_call_back)(struct ib_umem *item, u64 start, u64 end,
119 void *cookie); 115 void *cookie);
120/* 116/*
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
index e8608b2dc844..fd84cda5ed7c 100644
--- a/include/rdma/ib_verbs.h
+++ b/include/rdma/ib_verbs.h
@@ -229,6 +229,8 @@ enum ib_device_cap_flags {
229 /* Deprecated. Please use IB_RAW_PACKET_CAP_SCATTER_FCS. */ 229 /* Deprecated. Please use IB_RAW_PACKET_CAP_SCATTER_FCS. */
230 IB_DEVICE_RAW_SCATTER_FCS = (1ULL << 34), 230 IB_DEVICE_RAW_SCATTER_FCS = (1ULL << 34),
231 IB_DEVICE_RDMA_NETDEV_OPA_VNIC = (1ULL << 35), 231 IB_DEVICE_RDMA_NETDEV_OPA_VNIC = (1ULL << 35),
232 /* The device supports padding incoming writes to cacheline. */
233 IB_DEVICE_PCI_WRITE_END_PADDING = (1ULL << 36),
232}; 234};
233 235
234enum ib_signature_prot_cap { 236enum ib_signature_prot_cap {
@@ -309,6 +311,15 @@ struct ib_cq_init_attr {
309 u32 flags; 311 u32 flags;
310}; 312};
311 313
314enum ib_cq_attr_mask {
315 IB_CQ_MODERATE = 1 << 0,
316};
317
318struct ib_cq_caps {
319 u16 max_cq_moderation_count;
320 u16 max_cq_moderation_period;
321};
322
312struct ib_device_attr { 323struct ib_device_attr {
313 u64 fw_ver; 324 u64 fw_ver;
314 __be64 sys_image_guid; 325 __be64 sys_image_guid;
@@ -359,6 +370,7 @@ struct ib_device_attr {
359 u32 max_wq_type_rq; 370 u32 max_wq_type_rq;
360 u32 raw_packet_caps; /* Use ib_raw_packet_caps enum */ 371 u32 raw_packet_caps; /* Use ib_raw_packet_caps enum */
361 struct ib_tm_caps tm_caps; 372 struct ib_tm_caps tm_caps;
373 struct ib_cq_caps cq_caps;
362}; 374};
363 375
364enum ib_mtu { 376enum ib_mtu {
@@ -1098,6 +1110,7 @@ enum ib_qp_create_flags {
1098 IB_QP_CREATE_SCATTER_FCS = 1 << 8, 1110 IB_QP_CREATE_SCATTER_FCS = 1 << 8,
1099 IB_QP_CREATE_CVLAN_STRIPPING = 1 << 9, 1111 IB_QP_CREATE_CVLAN_STRIPPING = 1 << 9,
1100 IB_QP_CREATE_SOURCE_QPN = 1 << 10, 1112 IB_QP_CREATE_SOURCE_QPN = 1 << 10,
1113 IB_QP_CREATE_PCI_WRITE_END_PADDING = 1 << 11,
1101 /* reserve bits 26-31 for low level drivers' internal use */ 1114 /* reserve bits 26-31 for low level drivers' internal use */
1102 IB_QP_CREATE_RESERVED_START = 1 << 26, 1115 IB_QP_CREATE_RESERVED_START = 1 << 26,
1103 IB_QP_CREATE_RESERVED_END = 1 << 31, 1116 IB_QP_CREATE_RESERVED_END = 1 << 31,
@@ -1621,6 +1634,7 @@ enum ib_wq_flags {
1621 IB_WQ_FLAGS_CVLAN_STRIPPING = 1 << 0, 1634 IB_WQ_FLAGS_CVLAN_STRIPPING = 1 << 0,
1622 IB_WQ_FLAGS_SCATTER_FCS = 1 << 1, 1635 IB_WQ_FLAGS_SCATTER_FCS = 1 << 1,
1623 IB_WQ_FLAGS_DELAY_DROP = 1 << 2, 1636 IB_WQ_FLAGS_DELAY_DROP = 1 << 2,
1637 IB_WQ_FLAGS_PCI_WRITE_END_PADDING = 1 << 3,
1624}; 1638};
1625 1639
1626struct ib_wq_init_attr { 1640struct ib_wq_init_attr {
@@ -2858,6 +2872,21 @@ void ib_dealloc_pd(struct ib_pd *pd);
2858struct ib_ah *rdma_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr); 2872struct ib_ah *rdma_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr);
2859 2873
2860/** 2874/**
2875 * rdma_create_user_ah - Creates an address handle for the given address vector.
2876 * It resolves destination mac address for ah attribute of RoCE type.
2877 * @pd: The protection domain associated with the address handle.
2878 * @ah_attr: The attributes of the address vector.
2879 * @udata: pointer to user's input output buffer information need by
2880 * provider driver.
2881 *
2882 * It returns 0 on success and returns appropriate error code on error.
2883 * The address handle is used to reference a local or global destination
2884 * in all UD QP post sends.
2885 */
2886struct ib_ah *rdma_create_user_ah(struct ib_pd *pd,
2887 struct rdma_ah_attr *ah_attr,
2888 struct ib_udata *udata);
2889/**
2861 * ib_get_gids_from_rdma_hdr - Get sgid and dgid from GRH or IPv4 header 2890 * ib_get_gids_from_rdma_hdr - Get sgid and dgid from GRH or IPv4 header
2862 * work completion. 2891 * work completion.
2863 * @hdr: the L3 header to parse 2892 * @hdr: the L3 header to parse
@@ -3140,13 +3169,13 @@ struct ib_cq *ib_create_cq(struct ib_device *device,
3140int ib_resize_cq(struct ib_cq *cq, int cqe); 3169int ib_resize_cq(struct ib_cq *cq, int cqe);
3141 3170
3142/** 3171/**
3143 * ib_modify_cq - Modifies moderation params of the CQ 3172 * rdma_set_cq_moderation - Modifies moderation params of the CQ
3144 * @cq: The CQ to modify. 3173 * @cq: The CQ to modify.
3145 * @cq_count: number of CQEs that will trigger an event 3174 * @cq_count: number of CQEs that will trigger an event
3146 * @cq_period: max period of time in usec before triggering an event 3175 * @cq_period: max period of time in usec before triggering an event
3147 * 3176 *
3148 */ 3177 */
3149int ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 3178int rdma_set_cq_moderation(struct ib_cq *cq, u16 cq_count, u16 cq_period);
3150 3179
3151/** 3180/**
3152 * ib_destroy_cq - Destroys the specified CQ. 3181 * ib_destroy_cq - Destroys the specified CQ.
@@ -3607,8 +3636,6 @@ void ib_drain_rq(struct ib_qp *qp);
3607void ib_drain_sq(struct ib_qp *qp); 3636void ib_drain_sq(struct ib_qp *qp);
3608void ib_drain_qp(struct ib_qp *qp); 3637void ib_drain_qp(struct ib_qp *qp);
3609 3638
3610int ib_resolve_eth_dmac(struct ib_device *device,
3611 struct rdma_ah_attr *ah_attr);
3612int ib_get_eth_speed(struct ib_device *dev, u8 port_num, u8 *speed, u8 *width); 3639int ib_get_eth_speed(struct ib_device *dev, u8 port_num, u8 *speed, u8 *width);
3613 3640
3614static inline u8 *rdma_ah_retrieve_dmac(struct rdma_ah_attr *attr) 3641static inline u8 *rdma_ah_retrieve_dmac(struct rdma_ah_attr *attr)
diff --git a/include/rdma/opa_addr.h b/include/rdma/opa_addr.h
index e6e90f18e6d5..f68fca296631 100644
--- a/include/rdma/opa_addr.h
+++ b/include/rdma/opa_addr.h
@@ -97,15 +97,15 @@ static inline u32 opa_get_lid_from_gid(const union ib_gid *gid)
97 * @dlid: The DLID 97 * @dlid: The DLID
98 * @slid: The SLID 98 * @slid: The SLID
99 */ 99 */
100static inline bool opa_is_extended_lid(u32 dlid, u32 slid) 100static inline bool opa_is_extended_lid(__be32 dlid, __be32 slid)
101{ 101{
102 if ((be32_to_cpu(dlid) >= 102 if ((be32_to_cpu(dlid) >=
103 be16_to_cpu(IB_MULTICAST_LID_BASE)) || 103 be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
104 (be32_to_cpu(slid) >= 104 (be32_to_cpu(slid) >=
105 be16_to_cpu(IB_MULTICAST_LID_BASE))) 105 be16_to_cpu(IB_MULTICAST_LID_BASE)))
106 return true; 106 return true;
107 else 107
108 return false; 108 return false;
109} 109}
110 110
111/* Get multicast lid base */ 111/* Get multicast lid base */
diff --git a/include/rdma/rdmavt_qp.h b/include/rdma/rdmavt_qp.h
index 0eed3d8752fa..89ab88c342b6 100644
--- a/include/rdma/rdmavt_qp.h
+++ b/include/rdma/rdmavt_qp.h
@@ -282,7 +282,6 @@ struct rvt_qp {
282 u32 remote_qpn; 282 u32 remote_qpn;
283 u32 qkey; /* QKEY for this QP (for UD or RD) */ 283 u32 qkey; /* QKEY for this QP (for UD or RD) */
284 u32 s_size; /* send work queue size */ 284 u32 s_size; /* send work queue size */
285 u32 s_ahgpsn; /* set to the psn in the copy of the header */
286 285
287 u16 pmtu; /* decoded from path_mtu */ 286 u16 pmtu; /* decoded from path_mtu */
288 u8 log_pmtu; /* shift for pmtu */ 287 u8 log_pmtu; /* shift for pmtu */
@@ -344,7 +343,6 @@ struct rvt_qp {
344 struct rvt_swqe *s_wqe; 343 struct rvt_swqe *s_wqe;
345 struct rvt_sge_state s_sge; /* current send request data */ 344 struct rvt_sge_state s_sge; /* current send request data */
346 struct rvt_mregion *s_rdma_mr; 345 struct rvt_mregion *s_rdma_mr;
347 u32 s_cur_size; /* size of send packet in bytes */
348 u32 s_len; /* total length of s_sge */ 346 u32 s_len; /* total length of s_sge */
349 u32 s_rdma_read_len; /* total length of s_rdma_read_sge */ 347 u32 s_rdma_read_len; /* total length of s_rdma_read_sge */
350 u32 s_last_psn; /* last response PSN processed */ 348 u32 s_last_psn; /* last response PSN processed */
@@ -358,8 +356,10 @@ struct rvt_qp {
358 u32 s_acked; /* last un-ACK'ed entry */ 356 u32 s_acked; /* last un-ACK'ed entry */
359 u32 s_last; /* last completed entry */ 357 u32 s_last; /* last completed entry */
360 u32 s_lsn; /* limit sequence number (credit) */ 358 u32 s_lsn; /* limit sequence number (credit) */
361 u16 s_hdrwords; /* size of s_hdr in 32 bit words */ 359 u32 s_ahgpsn; /* set to the psn in the copy of the header */
360 u16 s_cur_size; /* size of send packet in bytes */
362 u16 s_rdma_ack_cnt; 361 u16 s_rdma_ack_cnt;
362 u8 s_hdrwords; /* size of s_hdr in 32 bit words */
363 s8 s_ahgidx; 363 s8 s_ahgidx;
364 u8 s_state; /* opcode of last packet sent */ 364 u8 s_state; /* opcode of last packet sent */
365 u8 s_ack_state; /* opcode of packet to ACK */ 365 u8 s_ack_state; /* opcode of packet to ACK */
diff --git a/include/uapi/rdma/ib_user_verbs.h b/include/uapi/rdma/ib_user_verbs.h
index e0e83a105953..7e11bb8651b6 100644
--- a/include/uapi/rdma/ib_user_verbs.h
+++ b/include/uapi/rdma/ib_user_verbs.h
@@ -101,7 +101,8 @@ enum {
101 IB_USER_VERBS_EX_CMD_MODIFY_WQ, 101 IB_USER_VERBS_EX_CMD_MODIFY_WQ,
102 IB_USER_VERBS_EX_CMD_DESTROY_WQ, 102 IB_USER_VERBS_EX_CMD_DESTROY_WQ,
103 IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL, 103 IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL,
104 IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL 104 IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL,
105 IB_USER_VERBS_EX_CMD_MODIFY_CQ
105}; 106};
106 107
107/* 108/*
@@ -125,6 +126,12 @@ struct ib_uverbs_comp_event_desc {
125 __u64 cq_handle; 126 __u64 cq_handle;
126}; 127};
127 128
129struct ib_uverbs_cq_moderation_caps {
130 __u16 max_cq_moderation_count;
131 __u16 max_cq_moderation_period;
132 __u32 reserved;
133};
134
128/* 135/*
129 * All commands from userspace should start with a __u32 command field 136 * All commands from userspace should start with a __u32 command field
130 * followed by __u16 in_words and out_words fields (which give the 137 * followed by __u16 in_words and out_words fields (which give the
@@ -263,6 +270,7 @@ struct ib_uverbs_ex_query_device_resp {
263 __u32 max_wq_type_rq; 270 __u32 max_wq_type_rq;
264 __u32 raw_packet_caps; 271 __u32 raw_packet_caps;
265 struct ib_uverbs_tm_caps tm_caps; 272 struct ib_uverbs_tm_caps tm_caps;
273 struct ib_uverbs_cq_moderation_caps cq_moderation_caps;
266}; 274};
267 275
268struct ib_uverbs_query_port { 276struct ib_uverbs_query_port {
@@ -1151,6 +1159,18 @@ struct ib_uverbs_ex_destroy_rwq_ind_table {
1151 __u32 ind_tbl_handle; 1159 __u32 ind_tbl_handle;
1152}; 1160};
1153 1161
1162struct ib_uverbs_cq_moderation {
1163 __u16 cq_count;
1164 __u16 cq_period;
1165};
1166
1167struct ib_uverbs_ex_modify_cq {
1168 __u32 cq_handle;
1169 __u32 attr_mask;
1170 struct ib_uverbs_cq_moderation attr;
1171 __u32 reserved;
1172};
1173
1154#define IB_DEVICE_NAME_MAX 64 1174#define IB_DEVICE_NAME_MAX 64
1155 1175
1156#endif /* IB_USER_VERBS_H */ 1176#endif /* IB_USER_VERBS_H */
diff --git a/include/uapi/rdma/mlx5-abi.h b/include/uapi/rdma/mlx5-abi.h
index 23dba2d40907..a33e0517d3fd 100644
--- a/include/uapi/rdma/mlx5-abi.h
+++ b/include/uapi/rdma/mlx5-abi.h
@@ -40,6 +40,7 @@
40enum { 40enum {
41 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 41 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
43 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
43}; 44};
44 45
45enum { 46enum {
@@ -191,6 +192,32 @@ struct mlx5_ib_sw_parsing_caps {
191 __u32 supported_qpts; 192 __u32 supported_qpts;
192}; 193};
193 194
195struct mlx5_ib_striding_rq_caps {
196 __u32 min_single_stride_log_num_of_bytes;
197 __u32 max_single_stride_log_num_of_bytes;
198 __u32 min_single_wqe_log_num_of_strides;
199 __u32 max_single_wqe_log_num_of_strides;
200
201 /* Corresponding bit will be set if qp type from
202 * 'enum ib_qp_type' is supported, e.g.
203 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
204 */
205 __u32 supported_qpts;
206 __u32 reserved;
207};
208
209enum mlx5_ib_query_dev_resp_flags {
210 /* Support 128B CQE compression */
211 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
212 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
213};
214
215enum mlx5_ib_tunnel_offloads {
216 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
217 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
218 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
219};
220
194struct mlx5_ib_query_device_resp { 221struct mlx5_ib_query_device_resp {
195 __u32 comp_mask; 222 __u32 comp_mask;
196 __u32 response_length; 223 __u32 response_length;
@@ -199,8 +226,15 @@ struct mlx5_ib_query_device_resp {
199 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 226 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
200 struct mlx5_packet_pacing_caps packet_pacing_caps; 227 struct mlx5_packet_pacing_caps packet_pacing_caps;
201 __u32 mlx5_ib_support_multi_pkt_send_wqes; 228 __u32 mlx5_ib_support_multi_pkt_send_wqes;
202 __u32 reserved; 229 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
203 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 230 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
231 struct mlx5_ib_striding_rq_caps striding_rq_caps;
232 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
233 __u32 reserved;
234};
235
236enum mlx5_ib_create_cq_flags {
237 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
204}; 238};
205 239
206struct mlx5_ib_create_cq { 240struct mlx5_ib_create_cq {
@@ -209,7 +243,7 @@ struct mlx5_ib_create_cq {
209 __u32 cqe_size; 243 __u32 cqe_size;
210 __u8 cqe_comp_en; 244 __u8 cqe_comp_en;
211 __u8 cqe_comp_res_format; 245 __u8 cqe_comp_res_format;
212 __u16 reserved; /* explicit padding (optional on i386) */ 246 __u16 flags;
213}; 247};
214 248
215struct mlx5_ib_create_cq_resp { 249struct mlx5_ib_create_cq_resp {
@@ -271,7 +305,9 @@ enum mlx5_rx_hash_fields {
271 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 305 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
272 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 306 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
273 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 307 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
274 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 308 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
309 /* Save bits for future fields */
310 MLX5_RX_HASH_INNER = 1 << 31
275}; 311};
276 312
277struct mlx5_ib_create_qp_rss { 313struct mlx5_ib_create_qp_rss {
@@ -281,7 +317,7 @@ struct mlx5_ib_create_qp_rss {
281 __u8 reserved[6]; 317 __u8 reserved[6];
282 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 318 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
283 __u32 comp_mask; 319 __u32 comp_mask;
284 __u32 reserved1; 320 __u32 flags;
285}; 321};
286 322
287struct mlx5_ib_create_qp_resp { 323struct mlx5_ib_create_qp_resp {
@@ -295,6 +331,10 @@ struct mlx5_ib_alloc_mw {
295 __u16 reserved2; 331 __u16 reserved2;
296}; 332};
297 333
334enum mlx5_ib_create_wq_mask {
335 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
336};
337
298struct mlx5_ib_create_wq { 338struct mlx5_ib_create_wq {
299 __u64 buf_addr; 339 __u64 buf_addr;
300 __u64 db_addr; 340 __u64 db_addr;
@@ -303,7 +343,9 @@ struct mlx5_ib_create_wq {
303 __u32 user_index; 343 __u32 user_index;
304 __u32 flags; 344 __u32 flags;
305 __u32 comp_mask; 345 __u32 comp_mask;
306 __u32 reserved; 346 __u32 single_stride_log_num_of_bytes;
347 __u32 single_wqe_log_num_of_strides;
348 __u32 two_byte_shift_en;
307}; 349};
308 350
309struct mlx5_ib_create_ah_resp { 351struct mlx5_ib_create_ah_resp {
diff --git a/include/uapi/rdma/vmw_pvrdma-abi.h b/include/uapi/rdma/vmw_pvrdma-abi.h
index 912ea1556a0b..aaa352f2f110 100644
--- a/include/uapi/rdma/vmw_pvrdma-abi.h
+++ b/include/uapi/rdma/vmw_pvrdma-abi.h
@@ -159,6 +159,8 @@ struct pvrdma_resize_cq {
159 159
160struct pvrdma_create_srq { 160struct pvrdma_create_srq {
161 __u64 buf_addr; 161 __u64 buf_addr;
162 __u32 buf_size;
163 __u32 reserved;
162}; 164};
163 165
164struct pvrdma_create_srq_resp { 166struct pvrdma_create_srq_resp {