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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-12-11 09:05:12 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-12-19 02:14:05 -0500
commitac991dce6498b5fc6396c7ac6f6a27b5585ef0f3 (patch)
treed9608676d6376abe8f0ffd39ac811d3127ba8ef1
parent7e429989b68533ee3896c96264a1cce99b95d218 (diff)
ARM: shmobile: r8a7790: Add clock index macros for DT sources
Add macros usable by device tree sources to reference r8a7790 clocks by index. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h100
1 files changed, 100 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644
index 000000000000..420f0b00ae1e
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -0,0 +1,100 @@
1/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
11#define __DT_BINDINGS_CLOCK_R8A7790_H__
12
13/* CPG */
14#define R8A7790_CLK_MAIN 0
15#define R8A7790_CLK_PLL0 1
16#define R8A7790_CLK_PLL1 2
17#define R8A7790_CLK_PLL3 3
18#define R8A7790_CLK_LB 4
19#define R8A7790_CLK_QSPI 5
20#define R8A7790_CLK_SDH 6
21#define R8A7790_CLK_SD0 7
22#define R8A7790_CLK_SD1 8
23#define R8A7790_CLK_Z 9
24
25/* MSTP1 */
26#define R8A7790_CLK_TMU1 11
27#define R8A7790_CLK_TMU3 21
28#define R8A7790_CLK_TMU2 22
29#define R8A7790_CLK_CMT0 24
30#define R8A7790_CLK_TMU0 25
31#define R8A7790_CLK_VSP1_DU1 27
32#define R8A7790_CLK_VSP1_DU0 28
33#define R8A7790_CLK_VSP1_RT 30
34#define R8A7790_CLK_VSP1_SY 31
35
36/* MSTP2 */
37#define R8A7790_CLK_SCIFA2 2
38#define R8A7790_CLK_SCIFA1 3
39#define R8A7790_CLK_SCIFA0 4
40#define R8A7790_CLK_SCIFB0 6
41#define R8A7790_CLK_SCIFB1 7
42#define R8A7790_CLK_SCIFB2 16
43#define R8A7790_CLK_SYS_DMAC0 18
44#define R8A7790_CLK_SYS_DMAC1 19
45
46/* MSTP3 */
47#define R8A7790_CLK_TPU0 4
48#define R8A7790_CLK_MMCIF1 5
49#define R8A7790_CLK_SDHI3 11
50#define R8A7790_CLK_SDHI2 12
51#define R8A7790_CLK_SDHI1 13
52#define R8A7790_CLK_SDHI0 14
53#define R8A7790_CLK_MMCIF0 15
54#define R8A7790_CLK_SSUSB 28
55#define R8A7790_CLK_CMT1 29
56#define R8A7790_CLK_USBDMAC0 30
57#define R8A7790_CLK_USBDMAC1 31
58
59/* MSTP5 */
60#define R8A7790_CLK_THERMAL 22
61#define R8A7790_CLK_PWM 23
62
63/* MSTP7 */
64#define R8A7790_CLK_EHCI 3
65#define R8A7790_CLK_HSUSB 4
66#define R8A7790_CLK_HSCIF1 16
67#define R8A7790_CLK_HSCIF0 17
68#define R8A7790_CLK_SCIF1 20
69#define R8A7790_CLK_SCIF0 21
70#define R8A7790_CLK_DU2 22
71#define R8A7790_CLK_DU1 23
72#define R8A7790_CLK_DU0 24
73#define R8A7790_CLK_LVDS1 25
74#define R8A7790_CLK_LVDS0 26
75
76/* MSTP8 */
77#define R8A7790_CLK_VIN3 8
78#define R8A7790_CLK_VIN2 9
79#define R8A7790_CLK_VIN1 10
80#define R8A7790_CLK_VIN0 11
81#define R8A7790_CLK_ETHER 13
82#define R8A7790_CLK_SATA1 14
83#define R8A7790_CLK_SATA0 15
84
85/* MSTP9 */
86#define R8A7790_CLK_GPIO5 7
87#define R8A7790_CLK_GPIO4 8
88#define R8A7790_CLK_GPIO3 9
89#define R8A7790_CLK_GPIO2 10
90#define R8A7790_CLK_GPIO1 11
91#define R8A7790_CLK_GPIO0 12
92#define R8A7790_CLK_RCAN1 15
93#define R8A7790_CLK_RCAN0 16
94#define R8A7790_CLK_IICDVFS 26
95#define R8A7790_CLK_I2C3 28
96#define R8A7790_CLK_I2C2 29
97#define R8A7790_CLK_I2C1 30
98#define R8A7790_CLK_I2C0 31
99
100#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */