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authorCédric Le Goater <clg@kaod.org>2017-08-30 15:46:16 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2017-09-02 07:02:38 -0400
commitac5e5a5402d64acd48af3287718e24ff8ba9fa21 (patch)
tree2e8e36d8f5e94a3c80db0c89a653352e21bbd138
parentbed81ee181dd6b21171cffbb80472cc5b774c24d (diff)
powerpc/xive: add XIVE Exploitation Mode to CAS
On POWER9, the Client Architecture Support (CAS) negotiation process determines whether the guest operates in XIVE Legacy compatibility or in XIVE exploitation mode. Now that we have initial guest support for the XIVE interrupt controller, let's inform the hypervisor what we can do. The platform advertises the XIVE Exploitation Mode support using the property "ibm,arch-vec-5-platform-support-vec-5", byte 23 bits 0-1 : - 0b00 XIVE legacy mode Only - 0b01 XIVE exploitation mode Only - 0b10 XIVE legacy or exploitation mode The OS asks for XIVE Exploitation Mode support using the property "ibm,architecture-vec-5", byte 23 bits 0-1: - 0b00 XIVE legacy mode Only - 0b01 XIVE exploitation mode Only Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r--arch/powerpc/include/asm/prom.h5
-rw-r--r--arch/powerpc/kernel/prom_init.c34
2 files changed, 37 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 35c00d7a0cf8..825bd5998701 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -159,7 +159,10 @@ struct of_drconf_cell {
159#define OV5_PFO_HW_842 0x1140 /* PFO Compression Accelerator */ 159#define OV5_PFO_HW_842 0x1140 /* PFO Compression Accelerator */
160#define OV5_PFO_HW_ENCR 0x1120 /* PFO Encryption Accelerator */ 160#define OV5_PFO_HW_ENCR 0x1120 /* PFO Encryption Accelerator */
161#define OV5_SUB_PROCESSORS 0x1501 /* 1,2,or 4 Sub-Processors supported */ 161#define OV5_SUB_PROCESSORS 0x1501 /* 1,2,or 4 Sub-Processors supported */
162#define OV5_XIVE_EXPLOIT 0x1701 /* XIVE exploitation supported */ 162#define OV5_XIVE_SUPPORT 0x17C0 /* XIVE Exploitation Support Mask */
163#define OV5_XIVE_LEGACY 0x1700 /* XIVE legacy mode Only */
164#define OV5_XIVE_EXPLOIT 0x1740 /* XIVE exploitation mode Only */
165#define OV5_XIVE_EITHER 0x1780 /* XIVE legacy or exploitation mode */
163/* MMU Base Architecture */ 166/* MMU Base Architecture */
164#define OV5_MMU_SUPPORT 0x18C0 /* MMU Mode Support Mask */ 167#define OV5_MMU_SUPPORT 0x18C0 /* MMU Mode Support Mask */
165#define OV5_MMU_HASH 0x1800 /* Hash MMU Only */ 168#define OV5_MMU_HASH 0x1800 /* Hash MMU Only */
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 613f79f03877..02190e90c7ae 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -177,6 +177,7 @@ struct platform_support {
177 bool hash_mmu; 177 bool hash_mmu;
178 bool radix_mmu; 178 bool radix_mmu;
179 bool radix_gtse; 179 bool radix_gtse;
180 bool xive;
180}; 181};
181 182
182/* Platforms codes are now obsolete in the kernel. Now only used within this 183/* Platforms codes are now obsolete in the kernel. Now only used within this
@@ -1041,6 +1042,27 @@ static void __init prom_parse_mmu_model(u8 val,
1041 } 1042 }
1042} 1043}
1043 1044
1045static void __init prom_parse_xive_model(u8 val,
1046 struct platform_support *support)
1047{
1048 switch (val) {
1049 case OV5_FEAT(OV5_XIVE_EITHER): /* Either Available */
1050 prom_debug("XIVE - either mode supported\n");
1051 support->xive = true;
1052 break;
1053 case OV5_FEAT(OV5_XIVE_EXPLOIT): /* Only Exploitation mode */
1054 prom_debug("XIVE - exploitation mode supported\n");
1055 support->xive = true;
1056 break;
1057 case OV5_FEAT(OV5_XIVE_LEGACY): /* Only Legacy mode */
1058 prom_debug("XIVE - legacy mode supported\n");
1059 break;
1060 default:
1061 prom_debug("Unknown xive support option: 0x%x\n", val);
1062 break;
1063 }
1064}
1065
1044static void __init prom_parse_platform_support(u8 index, u8 val, 1066static void __init prom_parse_platform_support(u8 index, u8 val,
1045 struct platform_support *support) 1067 struct platform_support *support)
1046{ 1068{
@@ -1054,6 +1076,10 @@ static void __init prom_parse_platform_support(u8 index, u8 val,
1054 support->radix_gtse = true; 1076 support->radix_gtse = true;
1055 } 1077 }
1056 break; 1078 break;
1079 case OV5_INDX(OV5_XIVE_SUPPORT): /* Interrupt mode */
1080 prom_parse_xive_model(val & OV5_FEAT(OV5_XIVE_SUPPORT),
1081 support);
1082 break;
1057 } 1083 }
1058} 1084}
1059 1085
@@ -1062,7 +1088,8 @@ static void __init prom_check_platform_support(void)
1062 struct platform_support supported = { 1088 struct platform_support supported = {
1063 .hash_mmu = false, 1089 .hash_mmu = false,
1064 .radix_mmu = false, 1090 .radix_mmu = false,
1065 .radix_gtse = false 1091 .radix_gtse = false,
1092 .xive = false
1066 }; 1093 };
1067 int prop_len = prom_getproplen(prom.chosen, 1094 int prop_len = prom_getproplen(prom.chosen,
1068 "ibm,arch-vec-5-platform-support"); 1095 "ibm,arch-vec-5-platform-support");
@@ -1095,6 +1122,11 @@ static void __init prom_check_platform_support(void)
1095 /* We're probably on a legacy hypervisor */ 1122 /* We're probably on a legacy hypervisor */
1096 prom_debug("Assuming legacy hash support\n"); 1123 prom_debug("Assuming legacy hash support\n");
1097 } 1124 }
1125
1126 if (supported.xive) {
1127 prom_debug("Asking for XIVE\n");
1128 ibm_architecture_vec.vec5.intarch = OV5_FEAT(OV5_XIVE_EXPLOIT);
1129 }
1098} 1130}
1099 1131
1100static void __init prom_send_capabilities(void) 1132static void __init prom_send_capabilities(void)