Merge branch 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next

1. Further PLL parameter fixes.
2. Fixes for HPD on DP
3. Could of different PM fixes
4. Disabling DPM on RV770

* 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux:
  drm/radeon: don't allow runpm=1 on systems with out ATPX
  drm/radeon: fix ATPX detection on non-VGA GPUs
  drm/radeon/pm: don't walk the crtc list before it has been initialized (v2)
  drm/radeon: properly unregister hwmon interface (v2)
  drm/radeon: fix count in cik_sdma_ring_test()
  drm/radeon/aux: fix hpd assignment for aux bus
  drm/radeon: improve PLL limit handling in post div calculation
  drm/radeon: use fixed PPL ref divider if needed
  drm/radeon: disable dpm on rv770 by default

7 files changed, 120 insertions, 68 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 15936524f226..bc0119fb6c12 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -209,6 +209,7 @@ void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 {
         int ret;
 
+        radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
         radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
         ret = drm_dp_aux_register_i2c_bus(&radeon_connector->ddc_bus->aux);
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 89b4afa5041c..f7e46cf682af 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -597,7 +597,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
         tmp = 0xCAFEDEAD;
         writel(tmp, ptr);
 
-        r = radeon_ring_lock(rdev, ring, 4);
+        r = radeon_ring_lock(rdev, ring, 5);
         if (r) {
                 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
                 return r;
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index cbf7e3269f84..9c61b74ef441 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -158,16 +158,18 @@ u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
         u32 line_time_us, vblank_lines;
         u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
 
-        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-                radeon_crtc = to_radeon_crtc(crtc);
-                if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
-                        line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) /
-                                radeon_crtc->hw_mode.clock;
-                        vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end -
-                                radeon_crtc->hw_mode.crtc_vdisplay +
-                                (radeon_crtc->v_border * 2);
-                        vblank_time_us = vblank_lines * line_time_us;
-                        break;
+        if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
+                list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                        radeon_crtc = to_radeon_crtc(crtc);
+                        if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
+                                line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) /
+                                        radeon_crtc->hw_mode.clock;
+                                vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end -
+                                        radeon_crtc->hw_mode.crtc_vdisplay +
+                                        (radeon_crtc->v_border * 2);
+                                vblank_time_us = vblank_lines * line_time_us;
+                                break;
+                        }
                 }
         }
 
@@ -181,14 +183,15 @@ u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
         struct radeon_crtc *radeon_crtc;
         u32 vrefresh = 0;
 
-        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-                radeon_crtc = to_radeon_crtc(crtc);
-                if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
-                        vrefresh = radeon_crtc->hw_mode.vrefresh;
-                        break;
+        if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
+                list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                        radeon_crtc = to_radeon_crtc(crtc);
+                        if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
+                                vrefresh = radeon_crtc->hw_mode.vrefresh;
+                                break;
+                        }
                 }
         }
-
         return vrefresh;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index dedea72f48c4..a9fb0d016d38 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -528,6 +528,13 @@ static bool radeon_atpx_detect(void)
                 has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
         }
 
+        /* some newer PX laptops mark the dGPU as a non-VGA display device */
+        while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
+                vga_count++;
+
+                has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
+        }
+
         if (has_atpx && vga_count == 2) {
                 acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
                 printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n",
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 2f7cbb901fb1..8d99d5ee8014 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -840,6 +840,38 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 }
 
 /**
+ * avivo_get_fb_ref_div - feedback and ref divider calculation
+ *
+ * @nom: nominator
+ * @den: denominator
+ * @post_div: post divider
+ * @fb_div_max: feedback divider maximum
+ * @ref_div_max: reference divider maximum
+ * @fb_div: resulting feedback divider
+ * @ref_div: resulting reference divider
+ *
+ * Calculate feedback and reference divider for a given post divider. Makes
+ * sure we stay within the limits.
+ */
+static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
+                                 unsigned fb_div_max, unsigned ref_div_max,
+                                 unsigned *fb_div, unsigned *ref_div)
+{
+        /* limit reference * post divider to a maximum */
+        ref_div_max = min(210 / post_div, ref_div_max);
+
+        /* get matching reference and feedback divider */
+        *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
+        *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
+
+        /* limit fb divider to its maximum */
+        if (*fb_div > fb_div_max) {
+                *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
+                *fb_div = fb_div_max;
+        }
+}
+
+/**
  * radeon_compute_pll_avivo - compute PLL paramaters
  *
  * @pll: information about the PLL
@@ -860,6 +892,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
                               u32 *ref_div_p,
                               u32 *post_div_p)
 {
+        unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
+                freq : freq / 10;
+
         unsigned fb_div_min, fb_div_max, fb_div;
         unsigned post_div_min, post_div_max, post_div;
         unsigned ref_div_min, ref_div_max, ref_div;
@@ -880,14 +915,18 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
                 ref_div_min = pll->reference_div;
         else
                 ref_div_min = pll->min_ref_div;
-        ref_div_max = pll->max_ref_div;
+
+        if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
+            pll->flags & RADEON_PLL_USE_REF_DIV)
+                ref_div_max = pll->reference_div;
+        else
+                ref_div_max = pll->max_ref_div;
 
         /* determine allowed post divider range */
         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
                 post_div_min = pll->post_div;
                 post_div_max = pll->post_div;
         } else {
-                unsigned target_clock = freq / 10;
                 unsigned vco_min, vco_max;
 
                 if (pll->flags & RADEON_PLL_IS_LCD) {
@@ -898,6 +937,11 @@ void radeon_compute_pl