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authorBaruch Siach <baruch@tkos.co.il>2016-09-05 15:00:10 -0400
committerGregory CLEMENT <gregory.clement@free-electrons.com>2016-09-14 10:24:17 -0400
commitab48eb533270e23aef28f572c6838c1c760ad8df (patch)
treeb9cc2460dabbcbc43e856da97ef4a644ba67682c
parenta305cc2fce217510dd255356d783e2c01cbc3a8f (diff)
dt-binding: mrvl-gpio: remove orion-gpio description
The Orion GPIO controller binding description in mrvl-gpio.txt is obsolete, and duplicates the description in gpio-mvebu.txt. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-rw-r--r--Documentation/devicetree/bindings/gpio/mrvl-gpio.txt23
1 files changed, 0 insertions, 23 deletions
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index 98d198396956..c3d016532d8e 100644
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -44,26 +44,3 @@ Example for a PXA3xx platform:
44 interrupt-controller; 44 interrupt-controller;
45 #interrupt-cells = <0x2>; 45 #interrupt-cells = <0x2>;
46 }; 46 };
47
48* Marvell Orion GPIO Controller
49
50Required properties:
51- compatible : Should be "marvell,orion-gpio"
52- reg : Address and length of the register set for controller.
53- gpio-controller : So we know this is a gpio controller.
54- ngpio : How many gpios this controller has.
55- interrupts : Up to 4 Interrupts for the controller.
56
57Optional properties:
58- mask-offset : For SMP Orions, offset for Nth CPU
59
60Example:
61
62 gpio0: gpio@10100 {
63 compatible = "marvell,orion-gpio";
64 #gpio-cells = <2>;
65 gpio-controller;
66 reg = <0x10100 0x40>;
67 ngpio = <32>;
68 interrupts = <35>, <36>, <37>, <38>;
69 };