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authorJanakarajan Natarajan <Janakarajan.Natarajan@amd.com>2017-06-14 12:26:58 -0400
committerIngo Molnar <mingo@kernel.org>2017-08-10 06:08:39 -0400
commitab027620e95987b5f0145013090a109b4152d23b (patch)
tree7ae9276dad75d580645bdefb3f39c706a0c10465
parent910448bbed066ab1082b510eef1ae61bb792d854 (diff)
perf/x86/amd/uncore: Get correct number of cores sharing last level cache
In Family 17h, the number of cores sharing a cache level is obtained from the Cache Properties CPUID leaf (0x8000001d) by passing in the cache level in ECX. In prior families, a cache level of 2 was used to determine this information. To get the right information, irrespective of Family, iterate over the cache levels using CPUID 0x8000001d. The last level cache is the last value to return a non-zero value in EAX. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/5ab569025b39cdfaeca55b571d78c0fc800bdb69.1497452002.git.Janakarajan.Natarajan@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/events/amd/uncore.c19
1 files changed, 16 insertions, 3 deletions
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index e34f8a6b4440..f5cbbba99283 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -400,11 +400,24 @@ static int amd_uncore_cpu_starting(unsigned int cpu)
400 400
401 if (amd_uncore_llc) { 401 if (amd_uncore_llc) {
402 unsigned int apicid = cpu_data(cpu).apicid; 402 unsigned int apicid = cpu_data(cpu).apicid;
403 unsigned int nshared; 403 unsigned int nshared, subleaf, prev_eax = 0;
404 404
405 uncore = *per_cpu_ptr(amd_uncore_llc, cpu); 405 uncore = *per_cpu_ptr(amd_uncore_llc, cpu);
406 cpuid_count(0x8000001d, 2, &eax, &ebx, &ecx, &edx); 406 /*
407 nshared = ((eax >> 14) & 0xfff) + 1; 407 * Iterate over Cache Topology Definition leaves until no
408 * more cache descriptions are available.
409 */
410 for (subleaf = 0; subleaf < 5; subleaf++) {
411 cpuid_count(0x8000001d, subleaf, &eax, &ebx, &ecx, &edx);
412
413 /* EAX[0:4] gives type of cache */
414 if (!(eax & 0x1f))
415 break;
416
417 prev_eax = eax;
418 }
419 nshared = ((prev_eax >> 14) & 0xfff) + 1;
420
408 uncore->id = apicid - (apicid % nshared); 421 uncore->id = apicid - (apicid % nshared);
409 422
410 uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc); 423 uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc);