diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-09-25 09:38:56 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-09-30 04:20:09 -0400 |
commit | aad941d53f7aa2b642a798e6b3de520c19ba2e46 (patch) | |
tree | 505a1d49c04d11ed1165f9d1300e40b36a79a03d | |
parent | 5e7234c9ccf88c427448fbe147839b4dca82efde (diff) |
drm/i915: Always use crtc_ timings when dealing with adjustead_mode
The adjustead_mode crtc_ timings are what we will program into the hardware,
so it's those timings we should be looking practically everywhere.
The normal and crtc_ timings should differ only when stere doubling is
used. In that case the normal timings are the orignal non-doubled
timigns, and crtc_ timings are the doubled timings used by the hardware.
The only case where we continue to look at the normal timings is when we
pass the adjusted_mode to drm_match_{cea,hdmi}_mode() to find the VIC.
drm_edid keeps the modes aronund in the non-double form only, so it
needs the non-double timings to match against.
Done with sed
's/adjusted_mode->\([vhVH]\)/adjusted_mode->crtc_\1/g'
's/adjusted_mode->clock/adjusted_mode->crtc_clock/g'
with a manual s/VDisplay/vdisplay/ within the comment in intel_dvo.c
v2: Update due to intel_dsi.c changes
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/dvo_ivch.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_audio.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp_mst.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_dsi.c | 30 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_dvo.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_panel.c | 58 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_sdvo.c | 4 |
8 files changed, 59 insertions, 59 deletions
diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c index 732ce8785945..e082f75317a0 100644 --- a/drivers/gpu/drm/i915/dvo_ivch.c +++ b/drivers/gpu/drm/i915/dvo_ivch.c | |||
@@ -414,16 +414,16 @@ static void ivch_mode_set(struct intel_dvo_device *dvo, | |||
414 | vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | | 414 | vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | |
415 | VR40_HORIZONTAL_INTERP_ENABLE); | 415 | VR40_HORIZONTAL_INTERP_ENABLE); |
416 | 416 | ||
417 | if (mode->hdisplay != adjusted_mode->hdisplay || | 417 | if (mode->hdisplay != adjusted_mode->crtc_hdisplay || |
418 | mode->vdisplay != adjusted_mode->vdisplay) { | 418 | mode->vdisplay != adjusted_mode->crtc_vdisplay) { |
419 | uint16_t x_ratio, y_ratio; | 419 | uint16_t x_ratio, y_ratio; |
420 | 420 | ||
421 | vr01 |= VR01_PANEL_FIT_ENABLE; | 421 | vr01 |= VR01_PANEL_FIT_ENABLE; |
422 | vr40 |= VR40_CLOCK_GATING_ENABLE; | 422 | vr40 |= VR40_CLOCK_GATING_ENABLE; |
423 | x_ratio = (((mode->hdisplay - 1) << 16) / | 423 | x_ratio = (((mode->hdisplay - 1) << 16) / |
424 | (adjusted_mode->hdisplay - 1)) >> 2; | 424 | (adjusted_mode->crtc_hdisplay - 1)) >> 2; |
425 | y_ratio = (((mode->vdisplay - 1) << 16) / | 425 | y_ratio = (((mode->vdisplay - 1) << 16) / |
426 | (adjusted_mode->vdisplay - 1)) >> 2; | 426 | (adjusted_mode->crtc_vdisplay - 1)) >> 2; |
427 | ivch_write(dvo, VR42, x_ratio); | 427 | ivch_write(dvo, VR42, x_ratio); |
428 | ivch_write(dvo, VR41, y_ratio); | 428 | ivch_write(dvo, VR41, y_ratio); |
429 | } else { | 429 | } else { |
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 779f90c1ce69..e4c30e8c2674 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c | |||
@@ -74,13 +74,13 @@ static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted | |||
74 | int i; | 74 | int i; |
75 | 75 | ||
76 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | 76 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
77 | if (adjusted_mode->clock == hdmi_audio_clock[i].clock) | 77 | if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) |
78 | break; | 78 | break; |
79 | } | 79 | } |
80 | 80 | ||
81 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | 81 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
82 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", | 82 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", |
83 | adjusted_mode->clock); | 83 | adjusted_mode->crtc_clock); |
84 | i = 1; | 84 | i = 1; |
85 | } | 85 | } |
86 | 86 | ||
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 036c704f3067..5105e09b65cc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -4400,7 +4400,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state) | |||
4400 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, | 4400 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
4401 | &state->scaler_state.scaler_id, DRM_ROTATE_0, | 4401 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4402 | state->pipe_src_w, state->pipe_src_h, | 4402 | state->pipe_src_w, state->pipe_src_h, |
4403 | adjusted_mode->hdisplay, adjusted_mode->vdisplay); | 4403 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
4404 | } | 4404 | } |
4405 | 4405 | ||
4406 | /** | 4406 | /** |
@@ -6593,7 +6593,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, | |||
6593 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | 6593 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
6594 | */ | 6594 | */ |
6595 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | 6595 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
6596 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | 6596 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
6597 | return -EINVAL; | 6597 | return -EINVAL; |
6598 | 6598 | ||
6599 | if (HAS_IPS(dev)) | 6599 | if (HAS_IPS(dev)) |
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index ff8ba55853be..cccf014d55c1 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c | |||
@@ -78,7 +78,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |||
78 | return false; | 78 | return false; |
79 | } | 79 | } |
80 | 80 | ||
81 | mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp); | 81 | mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp); |
82 | 82 | ||
83 | pipe_config->pbn = mst_pbn; | 83 | pipe_config->pbn = mst_pbn; |
84 | slots = drm_dp_find_vcpi_slots(&intel_dp->mst_mgr, mst_pbn); | 84 | slots = drm_dp_find_vcpi_slots(&intel_dp->mst_mgr, mst_pbn); |
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index b4d5213f0abb..4fb97c07bbc2 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c | |||
@@ -710,10 +710,10 @@ static void set_dsi_timings(struct drm_encoder *encoder, | |||
710 | 710 | ||
711 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | 711 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
712 | 712 | ||
713 | hactive = adjusted_mode->hdisplay; | 713 | hactive = adjusted_mode->crtc_hdisplay; |
714 | hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay; | 714 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; |
715 | hsync = adjusted_mode->hsync_end - adjusted_mode->hsync_start; | 715 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
716 | hbp = adjusted_mode->htotal - adjusted_mode->hsync_end; | 716 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; |
717 | 717 | ||
718 | if (intel_dsi->dual_link) { | 718 | if (intel_dsi->dual_link) { |
719 | hactive /= 2; | 719 | hactive /= 2; |
@@ -724,9 +724,9 @@ static void set_dsi_timings(struct drm_encoder *encoder, | |||
724 | hbp /= 2; | 724 | hbp /= 2; |
725 | } | 725 | } |
726 | 726 | ||
727 | vfp = adjusted_mode->vsync_start - adjusted_mode->vdisplay; | 727 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
728 | vsync = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | 728 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
729 | vbp = adjusted_mode->vtotal - adjusted_mode->vsync_end; | 729 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; |
730 | 730 | ||
731 | /* horizontal values are in terms of high speed byte clock */ | 731 | /* horizontal values are in terms of high speed byte clock */ |
732 | hactive = txbyteclkhs(hactive, bpp, lane_count, | 732 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
@@ -745,11 +745,11 @@ static void set_dsi_timings(struct drm_encoder *encoder, | |||
745 | * whereas these values should be based on resolution. | 745 | * whereas these values should be based on resolution. |
746 | */ | 746 | */ |
747 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | 747 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), |
748 | adjusted_mode->hdisplay); | 748 | adjusted_mode->crtc_hdisplay); |
749 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), | 749 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
750 | adjusted_mode->vdisplay); | 750 | adjusted_mode->crtc_vdisplay); |
751 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), | 751 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
752 | adjusted_mode->vtotal); | 752 | adjusted_mode->crtc_vtotal); |
753 | } | 753 | } |
754 | 754 | ||
755 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); | 755 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
@@ -782,7 +782,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) | |||
782 | 782 | ||
783 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); | 783 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
784 | 784 | ||
785 | mode_hdisplay = adjusted_mode->hdisplay; | 785 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
786 | 786 | ||
787 | if (intel_dsi->dual_link) { | 787 | if (intel_dsi->dual_link) { |
788 | mode_hdisplay /= 2; | 788 | mode_hdisplay /= 2; |
@@ -832,7 +832,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) | |||
832 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | 832 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); |
833 | 833 | ||
834 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | 834 | I915_WRITE(MIPI_DPI_RESOLUTION(port), |
835 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | | 835 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
836 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); | 836 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
837 | } | 837 | } |
838 | 838 | ||
@@ -878,13 +878,13 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) | |||
878 | if (is_vid_mode(intel_dsi) && | 878 | if (is_vid_mode(intel_dsi) && |
879 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | 879 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
880 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | 880 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
881 | txbyteclkhs(adjusted_mode->htotal, bpp, | 881 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
882 | intel_dsi->lane_count, | 882 | intel_dsi->lane_count, |
883 | intel_dsi->burst_mode_ratio) + 1); | 883 | intel_dsi->burst_mode_ratio) + 1); |
884 | } else { | 884 | } else { |
885 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | 885 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
886 | txbyteclkhs(adjusted_mode->vtotal * | 886 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
887 | adjusted_mode->htotal, | 887 | adjusted_mode->crtc_htotal, |
888 | bpp, intel_dsi->lane_count, | 888 | bpp, intel_dsi->lane_count, |
889 | intel_dsi->burst_mode_ratio) + 1); | 889 | intel_dsi->burst_mode_ratio) + 1); |
890 | } | 890 | } |
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 0bc8aa8b81c7..555afbcb6043 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c | |||
@@ -285,11 +285,11 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder) | |||
285 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; | 285 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; |
286 | 286 | ||
287 | /*I915_WRITE(DVOB_SRCDIM, | 287 | /*I915_WRITE(DVOB_SRCDIM, |
288 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | | 288 | (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
289 | (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ | 289 | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ |
290 | I915_WRITE(dvo_srcdim_reg, | 290 | I915_WRITE(dvo_srcdim_reg, |
291 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | | 291 | (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
292 | (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); | 292 | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); |
293 | /*I915_WRITE(DVOB, dvo_val);*/ | 293 | /*I915_WRITE(DVOB, dvo_val);*/ |
294 | I915_WRITE(dvo_reg, dvo_val); | 294 | I915_WRITE(dvo_reg, dvo_val); |
295 | } | 295 | } |
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 4294f605fe00..2806049e3a62 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c | |||
@@ -113,51 +113,51 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc, | |||
113 | x = y = width = height = 0; | 113 | x = y = width = height = 0; |
114 | 114 | ||
115 | /* Native modes don't need fitting */ | 115 | /* Native modes don't need fitting */ |
116 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && | 116 | if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && |
117 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) | 117 | adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) |
118 | goto done; | 118 | goto done; |
119 | 119 | ||
120 | switch (fitting_mode) { | 120 | switch (fitting_mode) { |
121 | case DRM_MODE_SCALE_CENTER: | 121 | case DRM_MODE_SCALE_CENTER: |
122 | width = pipe_config->pipe_src_w; | 122 | width = pipe_config->pipe_src_w; |
123 | height = pipe_config->pipe_src_h; | 123 | height = pipe_config->pipe_src_h; |
124 | x = (adjusted_mode->hdisplay - width + 1)/2; | 124 | x = (adjusted_mode->crtc_hdisplay - width + 1)/2; |
125 | y = (adjusted_mode->vdisplay - height + 1)/2; | 125 | y = (adjusted_mode->crtc_vdisplay - height + 1)/2; |
126 | break; | 126 | break; |
127 | 127 | ||
128 | case DRM_MODE_SCALE_ASPECT: | 128 | case DRM_MODE_SCALE_ASPECT: |
129 | /* Scale but preserve the aspect ratio */ | 129 | /* Scale but preserve the aspect ratio */ |
130 | { | 130 | { |
131 | u32 scaled_width = adjusted_mode->hdisplay | 131 | u32 scaled_width = adjusted_mode->crtc_hdisplay |
132 | * pipe_config->pipe_src_h; | 132 | * pipe_config->pipe_src_h; |
133 | u32 scaled_height = pipe_config->pipe_src_w | 133 | u32 scaled_height = pipe_config->pipe_src_w |
134 | * adjusted_mode->vdisplay; | 134 | * adjusted_mode->crtc_vdisplay; |
135 | if (scaled_width > scaled_height) { /* pillar */ | 135 | if (scaled_width > scaled_height) { /* pillar */ |
136 | width = scaled_height / pipe_config->pipe_src_h; | 136 | width = scaled_height / pipe_config->pipe_src_h; |
137 | if (width & 1) | 137 | if (width & 1) |
138 | width++; | 138 | width++; |
139 | x = (adjusted_mode->hdisplay - width + 1) / 2; | 139 | x = (adjusted_mode->crtc_hdisplay - width + 1) / 2; |
140 | y = 0; | 140 | y = 0; |
141 | height = adjusted_mode->vdisplay; | 141 | height = adjusted_mode->crtc_vdisplay; |
142 | } else if (scaled_width < scaled_height) { /* letter */ | 142 | } else if (scaled_width < scaled_height) { /* letter */ |
143 | height = scaled_width / pipe_config->pipe_src_w; | 143 | height = scaled_width / pipe_config->pipe_src_w; |
144 | if (height & 1) | 144 | if (height & 1) |
145 | height++; | 145 | height++; |
146 | y = (adjusted_mode->vdisplay - height + 1) / 2; | 146 | y = (adjusted_mode->crtc_vdisplay - height + 1) / 2; |
147 | x = 0; | 147 | x = 0; |
148 | width = adjusted_mode->hdisplay; | 148 | width = adjusted_mode->crtc_hdisplay; |
149 | } else { | 149 | } else { |
150 | x = y = 0; | 150 | x = y = 0; |
151 | width = adjusted_mode->hdisplay; | 151 | width = adjusted_mode->crtc_hdisplay; |
152 | height = adjusted_mode->vdisplay; | 152 | height = adjusted_mode->crtc_vdisplay; |
153 | } | 153 | } |
154 | } | 154 | } |
155 | break; | 155 | break; |
156 | 156 | ||
157 | case DRM_MODE_SCALE_FULLSCREEN: | 157 | case DRM_MODE_SCALE_FULLSCREEN: |
158 | x = y = 0; | 158 | x = y = 0; |
159 | width = adjusted_mode->hdisplay; | 159 | width = adjusted_mode->crtc_hdisplay; |
160 | height = adjusted_mode->vdisplay; | 160 | height = adjusted_mode->crtc_vdisplay; |
161 | break; | 161 | break; |
162 | 162 | ||
163 | default: | 163 | default: |
@@ -182,7 +182,7 @@ centre_horizontally(struct drm_display_mode *adjusted_mode, | |||
182 | blank_width = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; | 182 | blank_width = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; |
183 | sync_pos = (blank_width - sync_width + 1) / 2; | 183 | sync_pos = (blank_width - sync_width + 1) / 2; |
184 | 184 | ||
185 | border = (adjusted_mode->hdisplay - width + 1) / 2; | 185 | border = (adjusted_mode->crtc_hdisplay - width + 1) / 2; |
186 | border += border & 1; /* make the border even */ | 186 | border += border & 1; /* make the border even */ |
187 | 187 | ||
188 | adjusted_mode->crtc_hdisplay = width; | 188 | adjusted_mode->crtc_hdisplay = width; |
@@ -204,7 +204,7 @@ centre_vertically(struct drm_display_mode *adjusted_mode, | |||
204 | blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start; | 204 | blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start; |
205 | sync_pos = (blank_width - sync_width + 1) / 2; | 205 | sync_pos = (blank_width - sync_width + 1) / 2; |
206 | 206 | ||
207 | border = (adjusted_mode->vdisplay - height + 1) / 2; | 207 | border = (adjusted_mode->crtc_vdisplay - height + 1) / 2; |
208 | 208 | ||
209 | adjusted_mode->crtc_vdisplay = height; | 209 | adjusted_mode->crtc_vdisplay = height; |
210 | adjusted_mode->crtc_vblank_start = height + border; | 210 | adjusted_mode->crtc_vblank_start = height + border; |
@@ -231,10 +231,10 @@ static void i965_scale_aspect(struct intel_crtc_state *pipe_config, | |||
231 | u32 *pfit_control) | 231 | u32 *pfit_control) |
232 | { | 232 | { |
233 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | 233 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
234 | u32 scaled_width = adjusted_mode->hdisplay * | 234 | u32 scaled_width = adjusted_mode->crtc_hdisplay * |
235 | pipe_config->pipe_src_h; | 235 | pipe_config->pipe_src_h; |
236 | u32 scaled_height = pipe_config->pipe_src_w * | 236 | u32 scaled_height = pipe_config->pipe_src_w * |
237 | adjusted_mode->vdisplay; | 237 | adjusted_mode->crtc_vdisplay; |
238 | 238 | ||
239 | /* 965+ is easy, it does everything in hw */ | 239 | /* 965+ is easy, it does everything in hw */ |
240 | if (scaled_width > scaled_height) | 240 | if (scaled_width > scaled_height) |
@@ -243,7 +243,7 @@ static void i965_scale_aspect(struct intel_crtc_state *pipe_config, | |||
243 | else if (scaled_width < scaled_height) | 243 | else if (scaled_width < scaled_height) |
244 | *pfit_control |= PFIT_ENABLE | | 244 | *pfit_control |= PFIT_ENABLE | |
245 | PFIT_SCALING_LETTER; | 245 | PFIT_SCALING_LETTER; |
246 | else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w) | 246 | else if (adjusted_mode->crtc_hdisplay != pipe_config->pipe_src_w) |
247 | *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | 247 | *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; |
248 | } | 248 | } |
249 | 249 | ||
@@ -252,10 +252,10 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config, | |||
252 | u32 *border) | 252 | u32 *border) |
253 | { | 253 | { |
254 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | 254 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
255 | u32 scaled_width = adjusted_mode->hdisplay * | 255 | u32 scaled_width = adjusted_mode->crtc_hdisplay * |
256 | pipe_config->pipe_src_h; | 256 | pipe_config->pipe_src_h; |
257 | u32 scaled_height = pipe_config->pipe_src_w * | 257 | u32 scaled_height = pipe_config->pipe_src_w * |
258 | adjusted_mode->vdisplay; | 258 | adjusted_mode->crtc_vdisplay; |
259 | u32 bits; | 259 | u32 bits; |
260 | 260 | ||
261 | /* | 261 | /* |
@@ -269,9 +269,9 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config, | |||
269 | pipe_config->pipe_src_h); | 269 | pipe_config->pipe_src_h); |
270 | 270 | ||
271 | *border = LVDS_BORDER_ENABLE; | 271 | *border = LVDS_BORDER_ENABLE; |
272 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) { | 272 | if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay) { |
273 | bits = panel_fitter_scaling(pipe_config->pipe_src_h, | 273 | bits = panel_fitter_scaling(pipe_config->pipe_src_h, |
274 | adjusted_mode->vdisplay); | 274 | adjusted_mode->crtc_vdisplay); |
275 | 275 | ||
276 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | 276 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | |
277 | bits << PFIT_VERT_SCALE_SHIFT); | 277 | bits << PFIT_VERT_SCALE_SHIFT); |
@@ -285,9 +285,9 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config, | |||
285 | pipe_config->pipe_src_w); | 285 | pipe_config->pipe_src_w); |
286 | 286 | ||
287 | *border = LVDS_BORDER_ENABLE; | 287 | *border = LVDS_BORDER_ENABLE; |
288 | if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) { | 288 | if (pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { |
289 | bits = panel_fitter_scaling(pipe_config->pipe_src_w, | 289 | bits = panel_fitter_scaling(pipe_config->pipe_src_w, |
290 | adjusted_mode->hdisplay); | 290 | adjusted_mode->crtc_hdisplay); |
291 | 291 | ||
292 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | 292 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | |
293 | bits << PFIT_VERT_SCALE_SHIFT); | 293 | bits << PFIT_VERT_SCALE_SHIFT); |
@@ -315,8 +315,8 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, | |||
315 | adjusted_mode = &pipe_config->base.adjusted_mode; | 315 | adjusted_mode = &pipe_config->base.adjusted_mode; |
316 | 316 | ||
317 | /* Native modes don't need fitting */ | 317 | /* Native modes don't need fitting */ |
318 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && | 318 | if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && |
319 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) | 319 | adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) |
320 | goto out; | 320 | goto out; |
321 | 321 | ||
322 | switch (fitting_mode) { | 322 | switch (fitting_mode) { |
@@ -342,8 +342,8 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, | |||
342 | * Full scaling, even if it changes the aspect ratio. | 342 | * Full scaling, even if it changes the aspect ratio. |
343 | * Fortunately this is all done for us in hw. | 343 | * Fortunately this is all done for us in hw. |
344 | */ | 344 | */ |
345 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay || | 345 | if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay || |
346 | pipe_config->pipe_src_w != adjusted_mode->hdisplay) { | 346 | pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { |
347 | pfit_control |= PFIT_ENABLE; | 347 | pfit_control |= PFIT_ENABLE; |
348 | if (INTEL_INFO(dev)->gen >= 4) | 348 | if (INTEL_INFO(dev)->gen >= 4) |
349 | pfit_control |= PFIT_SCALING_AUTO; | 349 | pfit_control |= PFIT_SCALING_AUTO; |
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index ab75b6146e84..9df6bbd1872c 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
@@ -605,9 +605,9 @@ log_fail: | |||
605 | 605 | ||
606 | static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) | 606 | static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) |
607 | { | 607 | { |
608 | if (adjusted_mode->clock >= 100000) | 608 | if (adjusted_mode->crtc_clock >= 100000) |
609 | return 1; | 609 | return 1; |
610 | else if (adjusted_mode->clock >= 50000) | 610 | else if (adjusted_mode->crtc_clock >= 50000) |
611 | return 2; | 611 | return 2; |
612 | else | 612 | else |
613 | return 4; | 613 | return 4; |