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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2017-02-01 16:41:50 -0500
committerAlexandre Belloni <alexandre.belloni@free-electrons.com>2017-03-31 14:36:08 -0400
commitaab02d611f814c8f129860d87719a90a4d88b386 (patch)
treed5e62c9a301e64dcc1b4056cfbc3423bdcd28632
parent56387634b7604c141b8645d2377980164e18da0d (diff)
ARM: at91: pm: Tie the memory controller type to the ramc id
Instead of relying on the SoC type to select the memory controller type, use the device tree ids as they are parsed anyway. Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
-rw-r--r--arch/arm/mach-at91/pm.c30
1 files changed, 20 insertions, 10 deletions
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 488549bc2bed..ddf62a006635 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -329,11 +329,23 @@ static void at91sam9_sdram_standby(void)
329 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 329 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
330} 330}
331 331
332struct ramc_info {
333 void (*idle)(void);
334 unsigned int memctrl;
335};
336
337static const struct ramc_info ramc_infos[] __initconst = {
338 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
339 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
340 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
341 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
342};
343
332static const struct of_device_id const ramc_ids[] __initconst = { 344static const struct of_device_id const ramc_ids[] __initconst = {
333 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, 345 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
334 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, 346 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
335 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, 347 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
336 { .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby }, 348 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
337 { /*sentinel*/ } 349 { /*sentinel*/ }
338}; 350};
339 351
@@ -343,14 +355,17 @@ static __init void at91_dt_ramc(void)
343 const struct of_device_id *of_id; 355 const struct of_device_id *of_id;
344 int idx = 0; 356 int idx = 0;
345 const void *standby = NULL; 357 const void *standby = NULL;
358 const struct ramc_info *ramc;
346 359
347 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 360 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
348 pm_data.ramc[idx] = of_iomap(np, 0); 361 pm_data.ramc[idx] = of_iomap(np, 0);
349 if (!pm_data.ramc[idx]) 362 if (!pm_data.ramc[idx])
350 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 363 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
351 364
365 ramc = of_id->data;
352 if (!standby) 366 if (!standby)
353 standby = of_id->data; 367 standby = ramc->idle;
368 pm_data.memctrl = ramc->memctrl;
354 369
355 idx++; 370 idx++;
356 } 371 }
@@ -473,7 +488,6 @@ void __init at91rm9200_pm_init(void)
473 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 488 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
474 489
475 pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; 490 pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
476 pm_data.memctrl = AT91_MEMCTRL_MC;
477 491
478 at91_pm_init(at91rm9200_idle); 492 at91_pm_init(at91rm9200_idle);
479} 493}
@@ -481,7 +495,6 @@ void __init at91rm9200_pm_init(void)
481void __init at91sam9260_pm_init(void) 495void __init at91sam9260_pm_init(void)
482{ 496{
483 at91_dt_ramc(); 497 at91_dt_ramc();
484 pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
485 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 498 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
486 at91_pm_init(at91sam9_idle); 499 at91_pm_init(at91sam9_idle);
487} 500}
@@ -490,7 +503,6 @@ void __init at91sam9g45_pm_init(void)
490{ 503{
491 at91_dt_ramc(); 504 at91_dt_ramc();
492 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP; 505 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
493 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
494 at91_pm_init(at91sam9_idle); 506 at91_pm_init(at91sam9_idle);
495} 507}
496 508
@@ -498,7 +510,6 @@ void __init at91sam9x5_pm_init(void)
498{ 510{
499 at91_dt_ramc(); 511 at91_dt_ramc();
500 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 512 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
501 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
502 at91_pm_init(at91sam9_idle); 513 at91_pm_init(at91sam9_idle);
503} 514}
504 515
@@ -506,6 +517,5 @@ void __init sama5_pm_init(void)
506{ 517{
507 at91_dt_ramc(); 518 at91_dt_ramc();
508 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 519 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
509 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
510 at91_pm_init(NULL); 520 at91_pm_init(NULL);
511} 521}