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authorCQ Tang <cq.tang@intel.com>2017-01-30 12:39:52 -0500
committerJoerg Roedel <jroedel@suse.de>2017-01-31 06:50:05 -0500
commitaaa59306b0b7e0ca4ba92cc04c5db101cbb1c096 (patch)
tree7b1ab089a2ef01fdfd2f1b524993a65e4a2b2e08
parent566cf877a1fcb6d6dc0126b076aad062054c2637 (diff)
iommu/vt-d: Fix some macros that are incorrectly specified in intel-iommu
Some of the macros are incorrect with wrong bit-shifts resulting in picking the incorrect invalidation granularity. Incorrect Source-ID in extended devtlb invalidation caused device side errors. To: Joerg Roedel <joro@8bytes.org> To: David Woodhouse <dwmw2@infradead.org> Cc: iommu@lists.linux-foundation.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org Cc: CQ Tang <cq.tang@intel.com> Cc: Ashok Raj <ashok.raj@intel.com> Fixes: 2f26e0a9 ("iommu/vt-d: Add basic SVM PASID support") Signed-off-by: CQ Tang <cq.tang@intel.com> Signed-off-by: Ashok Raj <ashok.raj@intel.com> Tested-by: CQ Tang <cq.tang@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
-rw-r--r--include/linux/intel-iommu.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index d49e26c6cdc7..23e129ef6726 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -153,8 +153,8 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
153#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) 153#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
154#define DMA_TLB_DSI_FLUSH (((u64)2) << 60) 154#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
155#define DMA_TLB_PSI_FLUSH (((u64)3) << 60) 155#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
156#define DMA_TLB_IIRG(type) ((type >> 60) & 7) 156#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
157#define DMA_TLB_IAIG(val) (((val) >> 57) & 7) 157#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
158#define DMA_TLB_READ_DRAIN (((u64)1) << 49) 158#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
159#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) 159#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
160#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) 160#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
@@ -164,9 +164,9 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
164 164
165/* INVALID_DESC */ 165/* INVALID_DESC */
166#define DMA_CCMD_INVL_GRANU_OFFSET 61 166#define DMA_CCMD_INVL_GRANU_OFFSET 61
167#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3) 167#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
168#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3) 168#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
169#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3) 169#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
170#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) 170#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
171#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) 171#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
172#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) 172#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
@@ -316,8 +316,8 @@ enum {
316#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) 316#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
317#define QI_DEV_EIOTLB_GLOB(g) ((u64)g) 317#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
318#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) 318#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
319#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) 319#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
320#define QI_DEV_EIOTLB_QDEP(qd) (((qd) & 0x1f) << 16) 320#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
321#define QI_DEV_EIOTLB_MAX_INVS 32 321#define QI_DEV_EIOTLB_MAX_INVS 32
322 322
323#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55) 323#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)