x86/umip: Enable User-Mode Instruction Prevention at runtime

User-Mode Instruction Prevention (UMIP) is enabled by setting/clearing a
bit in %cr4.

It makes sense to enable UMIP at some point while booting, before user
spaces come up. Like SMAP and SMEP, is not critical to have it enabled
very early during boot. This is because UMIP is relevant only when there is
a user space to be protected from. Given these similarities, UMIP can be
enabled along with SMAP and SMEP.

At the moment, UMIP is disabled by default at build time. It can be enabled
at build time by selecting CONFIG_X86_INTEL_UMIP. If enabled at build time,
it can be disabled at run time by adding clearcpuid=514 to the kernel
parameters.

Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Borislav Petkov <bp@suse.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Chen Yucong <slaoub@gmail.com>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Huang Rui <ray.huang@amd.com>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
Cc: Shuah Khan <shuah@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: ricardo.neri@intel.com
Link: http://lkml.kernel.org/r/1509935277-22138-10-git-send-email-ricardo.neri-calderon@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

2 files changed, 34 insertions, 1 deletions

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 4ae940a0ed3b..e19fa9f7079a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1802,6 +1802,16 @@ config X86_SMAP
 
           If unsure, say Y.
 
+config X86_INTEL_UMIP
+        def_bool n
+        depends on CPU_SUP_INTEL
+        prompt "Intel User Mode Instruction Prevention" if EXPERT
+        ---help---
+          The User Mode Instruction Prevention (UMIP) is a security
+          feature in newer Intel processors. If enabled, a general
+          protection fault is issued if the instructions SGDT, SLDT,
+          SIDT, SMSW and STR are executed in user mode.
+
 config X86_INTEL_MPX
         prompt "Intel MPX (Memory Protection Extensions)"
         def_bool n
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index cdf79ab628c2..47f8a85be11c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -329,6 +329,28 @@ static __always_inline void setup_smap(struct cpuinfo_x86 *c)
         }
 }
 
+static __always_inline void setup_umip(struct cpuinfo_x86 *c)
+{
+        /* Check the boot processor, plus build option for UMIP. */
+        if (!cpu_feature_enabled(X86_FEATURE_UMIP))
+                goto out;
+
+        /* Check the current processor's cpuid bits. */
+        if (!cpu_has(c, X86_FEATURE_UMIP))
+                goto out;
+
+        cr4_set_bits(X86_CR4_UMIP);
+
+        return;
+
+out:
+        /*
+         * Make sure UMIP is disabled in case it was enabled in a
+         * previous boot (e.g., via kexec).
+         */
+        cr4_clear_bits(X86_CR4_UMIP);
+}
+
 /*
  * Protection Keys are not available in 32-bit mode.
  */
@@ -1147,9 +1169,10 @@ static void identify_cpu(struct cpuinfo_x86 *c)
         /* Disable the PN if appropriate */
         squash_the_stupid_serial_number(c);
 
-        /* Set up SMEP/SMAP */
+        /* Set up SMEP/SMAP/UMIP */
         setup_smep(c);
         setup_smap(c);
+        setup_umip(c);
 
         /*
          * The vendor-specific functions might have changed features.