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authorArnd Bergmann <arnd@arndb.de>2018-03-09 11:37:54 -0500
committerArnd Bergmann <arnd@arndb.de>2018-03-26 09:57:12 -0400
commita9762b704f5d5e167bbc261573621782b90efbc4 (patch)
tree28bfb99ac7c73aa508701c4d9b361998e87f439b
parent03f4c9abd73284193f70e64da1a266d393650530 (diff)
usb: musb: remove blackfin port
The blackfin architecture is getting removed, so we can clean up all the special cases in the musb driver. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Aaron Wu <aaron.wu@analog.com> Acked-by: Bin Liu <b-liu@ti.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> [arnd: adding in fixups from Aaron and Stephen] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/driver-api/usb/writing_musb_glue_layer.rst3
-rw-r--r--drivers/usb/musb/Kconfig12
-rw-r--r--drivers/usb/musb/Makefile1
-rw-r--r--drivers/usb/musb/blackfin.c623
-rw-r--r--drivers/usb/musb/blackfin.h81
-rw-r--r--drivers/usb/musb/musb_core.c7
-rw-r--r--drivers/usb/musb/musb_core.h43
-rw-r--r--drivers/usb/musb/musb_debugfs.c2
-rw-r--r--drivers/usb/musb/musb_dma.h11
-rw-r--r--drivers/usb/musb/musb_gadget.c56
-rw-r--r--drivers/usb/musb/musb_host.c12
-rw-r--r--drivers/usb/musb/musb_regs.h182
-rw-r--r--drivers/usb/musb/musbhsdma.c5
-rw-r--r--drivers/usb/musb/musbhsdma.h64
-rw-r--r--include/linux/usb/musb.h7
15 files changed, 13 insertions, 1096 deletions
diff --git a/Documentation/driver-api/usb/writing_musb_glue_layer.rst b/Documentation/driver-api/usb/writing_musb_glue_layer.rst
index e90e8fa95600..5bf7152fd76f 100644
--- a/Documentation/driver-api/usb/writing_musb_glue_layer.rst
+++ b/Documentation/driver-api/usb/writing_musb_glue_layer.rst
@@ -718,6 +718,3 @@ http://www.maximintegrated.com/app-notes/index.mvp/id/1822
718 718
719Texas Instruments USB Configuration Wiki Page: 719Texas Instruments USB Configuration Wiki Page:
720http://processors.wiki.ti.com/index.php/Usbgeneralpage 720http://processors.wiki.ti.com/index.php/Usbgeneralpage
721
722Analog Devices Blackfin MUSB Configuration:
723http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:musb
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index e757afc1cfd0..ad08895e78f9 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -5,7 +5,7 @@
5 5
6# (M)HDRC = (Multipoint) Highspeed Dual-Role Controller 6# (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
7config USB_MUSB_HDRC 7config USB_MUSB_HDRC
8 tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, AW, ...)' 8 tristate 'Inventra Highspeed Dual Role Controller'
9 depends on (USB || USB_GADGET) 9 depends on (USB || USB_GADGET)
10 depends on HAS_IOMEM 10 depends on HAS_IOMEM
11 help 11 help
@@ -18,9 +18,6 @@ config USB_MUSB_HDRC
18 Texas Instruments families using this IP include DaVinci 18 Texas Instruments families using this IP include DaVinci
19 (35x, 644x ...), OMAP 243x, OMAP 3, and TUSB 6010. 19 (35x, 644x ...), OMAP 243x, OMAP 3, and TUSB 6010.
20 20
21 Analog Devices parts using this IP include Blackfin BF54x,
22 BF525 and BF527.
23
24 Allwinner SoCs using this IP include A10, A13, A20, ... 21 Allwinner SoCs using this IP include A10, A13, A20, ...
25 22
26 If you do not know what this is, please say N. 23 If you do not know what this is, please say N.
@@ -107,11 +104,6 @@ config USB_MUSB_DSPS
107 depends on ARCH_OMAP2PLUS || COMPILE_TEST 104 depends on ARCH_OMAP2PLUS || COMPILE_TEST
108 depends on OF_IRQ 105 depends on OF_IRQ
109 106
110config USB_MUSB_BLACKFIN
111 tristate "Blackfin"
112 depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
113 depends on NOP_USB_XCEIV
114
115config USB_MUSB_UX500 107config USB_MUSB_UX500
116 tristate "Ux500 platforms" 108 tristate "Ux500 platforms"
117 depends on ARCH_U8500 || COMPILE_TEST 109 depends on ARCH_U8500 || COMPILE_TEST
@@ -149,7 +141,7 @@ config USB_UX500_DMA
149 141
150config USB_INVENTRA_DMA 142config USB_INVENTRA_DMA
151 bool 'Inventra' 143 bool 'Inventra'
152 depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN 144 depends on USB_MUSB_OMAP2PLUS
153 help 145 help
154 Enable DMA transfers using Mentor's engine. 146 Enable DMA transfers using Mentor's engine.
155 147
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 79d4d5439164..3a88c79e650c 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
21obj-$(CONFIG_USB_MUSB_TUSB6010) += tusb6010.o 21obj-$(CONFIG_USB_MUSB_TUSB6010) += tusb6010.o
22obj-$(CONFIG_USB_MUSB_DAVINCI) += davinci.o 22obj-$(CONFIG_USB_MUSB_DAVINCI) += davinci.o
23obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o 23obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
24obj-$(CONFIG_USB_MUSB_BLACKFIN) += blackfin.o
25obj-$(CONFIG_USB_MUSB_UX500) += ux500.o 24obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
26obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o 25obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o
27obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o 26obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
deleted file mode 100644
index 0a98dcd66d19..000000000000
--- a/drivers/usb/musb/blackfin.c
+++ /dev/null
@@ -1,623 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * MUSB OTG controller driver for Blackfin Processors
4 *
5 * Copyright 2006-2008 Analog Devices Inc.
6 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 */
9
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/sched.h>
13#include <linux/list.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/prefetch.h>
20#include <linux/usb/usb_phy_generic.h>
21
22#include <asm/cacheflush.h>
23
24#include "musb_core.h"
25#include "musbhsdma.h"
26#include "blackfin.h"
27
28struct bfin_glue {
29 struct device *dev;
30 struct platform_device *musb;
31 struct platform_device *phy;
32};
33#define glue_to_musb(g) platform_get_drvdata(g->musb)
34
35static u32 bfin_fifo_offset(u8 epnum)
36{
37 return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
38}
39
40static u8 bfin_readb(const void __iomem *addr, unsigned offset)
41{
42 return (u8)(bfin_read16(addr + offset));
43}
44
45static u16 bfin_readw(const void __iomem *addr, unsigned offset)
46{
47 return bfin_read16(addr + offset);
48}
49
50static u32 bfin_readl(const void __iomem *addr, unsigned offset)
51{
52 return (u32)(bfin_read16(addr + offset));
53}
54
55static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
56{
57 bfin_write16(addr + offset, (u16)data);
58}
59
60static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
61{
62 bfin_write16(addr + offset, data);
63}
64
65static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
66{
67 bfin_write16(addr + offset, (u16)data);
68}
69
70/*
71 * Load an endpoint's FIFO
72 */
73static void bfin_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
74{
75 struct musb *musb = hw_ep->musb;
76 void __iomem *fifo = hw_ep->fifo;
77 void __iomem *epio = hw_ep->regs;
78 u8 epnum = hw_ep->epnum;
79
80 prefetch((u8 *)src);
81
82 musb_writew(epio, MUSB_TXCOUNT, len);
83
84 dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
85 hw_ep->epnum, fifo, len, src, epio);
86
87 dump_fifo_data(src, len);
88
89 if (!ANOMALY_05000380 && epnum != 0) {
90 u16 dma_reg;
91
92 flush_dcache_range((unsigned long)src,
93 (unsigned long)(src + len));
94
95 /* Setup DMA address register */
96 dma_reg = (u32)src;
97 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
98 SSYNC();
99
100 dma_reg = (u32)src >> 16;
101 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
102 SSYNC();
103
104 /* Setup DMA count register */
105 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
106 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
107 SSYNC();
108
109 /* Enable the DMA */
110 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
111 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
112 SSYNC();
113
114 /* Wait for complete */
115 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
116 cpu_relax();
117
118 /* acknowledge dma interrupt */
119 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
120 SSYNC();
121
122 /* Reset DMA */
123 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
124 SSYNC();
125 } else {
126 SSYNC();
127
128 if (unlikely((unsigned long)src & 0x01))
129 outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
130 else
131 outsw((unsigned long)fifo, src, (len + 1) >> 1);
132 }
133}
134/*
135 * Unload an endpoint's FIFO
136 */
137static void bfin_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
138{
139 struct musb *musb = hw_ep->musb;
140 void __iomem *fifo = hw_ep->fifo;
141 u8 epnum = hw_ep->epnum;
142
143 if (ANOMALY_05000467 && epnum != 0) {
144 u16 dma_reg;
145
146 invalidate_dcache_range((unsigned long)dst,
147 (unsigned long)(dst + len));
148
149 /* Setup DMA address register */
150 dma_reg = (u32)dst;
151 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
152 SSYNC();
153
154 dma_reg = (u32)dst >> 16;
155 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
156 SSYNC();
157
158 /* Setup DMA count register */
159 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
160 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
161 SSYNC();
162
163 /* Enable the DMA */
164 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
165 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
166 SSYNC();
167
168 /* Wait for complete */
169 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
170 cpu_relax();
171
172 /* acknowledge dma interrupt */
173 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
174 SSYNC();
175
176 /* Reset DMA */
177 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
178 SSYNC();
179 } else {
180 SSYNC();
181 /* Read the last byte of packet with odd size from address fifo + 4
182 * to trigger 1 byte access to EP0 FIFO.
183 */
184 if (len == 1)
185 *dst = (u8)inw((unsigned long)fifo + 4);
186 else {
187 if (unlikely((unsigned long)dst & 0x01))
188 insw_8((unsigned long)fifo, dst, len >> 1);
189 else
190 insw((unsigned long)fifo, dst, len >> 1);
191
192 if (len & 0x01)
193 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
194 }
195 }
196 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
197 'R', hw_ep->epnum, fifo, len, dst);
198
199 dump_fifo_data(dst, len);
200}
201
202static irqreturn_t blackfin_interrupt(int irq, void *__hci)
203{
204 unsigned long flags;
205 irqreturn_t retval = IRQ_NONE;
206 struct musb *musb = __hci;
207
208 spin_lock_irqsave(&musb->lock, flags);
209
210 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
211 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
212 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
213
214 if (musb->int_usb || musb->int_tx || musb->int_rx) {
215 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
216 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
217 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
218 retval = musb_interrupt(musb);
219 }
220
221 /* Start sampling ID pin, when plug is removed from MUSB */
222 if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
223 || musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
224 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
225 mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
226 musb->a_wait_bcon = TIMER_DELAY;
227 }
228
229 spin_unlock_irqrestore(&musb->lock, flags);
230
231 return retval;
232}
233
234static void musb_conn_timer_handler(struct timer_list *t)
235{
236 struct musb *musb = from_timer(musb, t, dev_timer);
237 unsigned long flags;
238 u16 val;
239 static u8 toggle;
240
241 spin_lock_irqsave(&musb->lock, flags);
242 switch (musb->xceiv->otg->state) {
243 case OTG_STATE_A_IDLE:
244 case OTG_STATE_A_WAIT_BCON:
245 /* Start a new session */
246 val = musb_readw(musb->mregs, MUSB_DEVCTL);
247 val &= ~MUSB_DEVCTL_SESSION;
248 musb_writew(musb->mregs, MUSB_DEVCTL, val);
249 val |= MUSB_DEVCTL_SESSION;
250 musb_writew(musb->mregs, MUSB_DEVCTL, val);
251 /* Check if musb is host or peripheral. */
252 val = musb_readw(musb->mregs, MUSB_DEVCTL);
253
254 if (!(val & MUSB_DEVCTL_BDEVICE)) {
255 gpio_set_value(musb->config->gpio_vrsel, 1);
256 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
257 } else {
258 gpio_set_value(musb->config->gpio_vrsel, 0);
259 /* Ignore VBUSERROR and SUSPEND IRQ */
260 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
261 val &= ~MUSB_INTR_VBUSERROR;
262 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
263
264 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
265 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
266 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
267 }
268 mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
269 break;
270 case OTG_STATE_B_IDLE:
271 /*
272 * Start a new session. It seems that MUSB needs taking
273 * some time to recognize the type of the plug inserted?
274 */
275 val = musb_readw(musb->mregs, MUSB_DEVCTL);
276 val |= MUSB_DEVCTL_SESSION;
277 musb_writew(musb->mregs, MUSB_DEVCTL, val);
278 val = musb_readw(musb->mregs, MUSB_DEVCTL);
279
280 if (!(val & MUSB_DEVCTL_BDEVICE)) {
281 gpio_set_value(musb->config->gpio_vrsel, 1);
282 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
283 } else {
284 gpio_set_value(musb->config->gpio_vrsel, 0);
285
286 /* Ignore VBUSERROR and SUSPEND IRQ */
287 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
288 val &= ~MUSB_INTR_VBUSERROR;
289 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
290
291 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
292 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
293
294 /* Toggle the Soft Conn bit, so that we can response to
295 * the inserting of either A-plug or B-plug.
296 */
297 if (toggle) {
298 val = musb_readb(musb->mregs, MUSB_POWER);
299 val &= ~MUSB_POWER_SOFTCONN;
300 musb_writeb(musb->mregs, MUSB_POWER, val);
301 toggle = 0;
302 } else {
303 val = musb_readb(musb->mregs, MUSB_POWER);
304 val |= MUSB_POWER_SOFTCONN;
305 musb_writeb(musb->mregs, MUSB_POWER, val);
306 toggle = 1;
307 }
308 /* The delay time is set to 1/4 second by default,
309 * shortening it, if accelerating A-plug detection
310 * is needed in OTG mode.
311 */
312 mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY / 4);
313 }
314 break;
315 default:
316 dev_dbg(musb->controller, "%s state not handled\n",
317 usb_otg_state_string(musb->xceiv->otg->state));
318 break;
319 }
320 spin_unlock_irqrestore(&musb->lock, flags);
321
322 dev_dbg(musb->controller, "state is %s\n",
323 usb_otg_state_string(musb->xceiv->otg->state));
324}
325
326static void bfin_musb_enable(struct musb *musb)
327{
328 /* REVISIT is this really correct ? */
329}
330
331static void bfin_musb_disable(struct musb *musb)
332{
333}
334
335static void bfin_musb_set_vbus(struct musb *musb, int is_on)
336{
337 int value = musb->config->gpio_vrsel_active;
338 if (!is_on)
339 value = !value;
340 gpio_set_value(musb->config->gpio_vrsel, value);
341
342 dev_dbg(musb->controller, "VBUS %s, devctl %02x "
343 /* otg %3x conf %08x prcm %08x */ "\n",
344 usb_otg_state_string(musb->xceiv->otg->state),
345 musb_readb(musb->mregs, MUSB_DEVCTL));
346}
347
348static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
349{
350 return 0;
351}
352
353static int bfin_musb_vbus_status(struct musb *musb)
354{
355 return 0;
356}
357
358static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
359{
360 return -EIO;
361}
362
363static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
364 u16 packet_sz, u8 *mode,
365 dma_addr_t *dma_addr, u32 *len)
366{
367 struct musb_dma_channel *musb_channel = channel->private_data;
368
369 /*
370 * Anomaly 05000450 might cause data corruption when using DMA
371 * MODE 1 transmits with short packet. So to work around this,
372 * we truncate all MODE 1 transfers down to a multiple of the
373 * max packet size, and then do the last short packet transfer
374 * (if there is any) using MODE 0.
375 */
376 if (ANOMALY_05000450) {
377 if (musb_channel->transmit && *mode == 1)
378 *len = *len - (*len % packet_sz);
379 }
380
381 return 0;
382}
383
384static void bfin_musb_reg_init(struct musb *musb)
385{
386 if (ANOMALY_05000346) {
387 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
388 SSYNC();
389 }
390
391 if (ANOMALY_05000347) {
392 bfin_write_USB_APHY_CNTRL(0x0);
393 SSYNC();
394 }
395
396 /* Configure PLL oscillator register */
397 bfin_write_USB_PLLOSC_CTRL(0x3080 |
398 ((480/musb->config->clkin) << 1));
399 SSYNC();
400
401 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
402 SSYNC();
403
404 bfin_write_USB_EP_NI0_RXMAXP(64);
405 SSYNC();
406
407 bfin_write_USB_EP_NI0_TXMAXP(64);
408 SSYNC();
409
410 /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
411 bfin_write_USB_GLOBINTR(0x7);
412 SSYNC();
413
414 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
415 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
416 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
417 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
418 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
419 SSYNC();
420}
421
422static int bfin_musb_init(struct musb *musb)
423{
424
425 /*
426 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
427 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
428 * be low for DEVICE mode and high for HOST mode. We set it high
429 * here because we are in host mode
430 */
431
432 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
433 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
434 musb->config->gpio_vrsel);
435 return -ENODEV;
436 }
437 gpio_direction_output(musb->config->gpio_vrsel, 0);
438
439 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
440 if (IS_ERR_OR_NULL(musb->xceiv)) {
441 gpio_free(musb->config->gpio_vrsel);
442 return -EPROBE_DEFER;
443 }
444
445 bfin_musb_reg_init(musb);
446
447 timer_setup(&musb->dev_timer, musb_conn_timer_handler, 0);
448
449 musb->xceiv->set_power = bfin_musb_set_power;
450
451 musb->isr = blackfin_interrupt;
452 musb->double_buffer_not_ok = true;
453
454 return 0;
455}
456
457static int bfin_musb_exit(struct musb *musb)
458{
459 gpio_free(musb->config->gpio_vrsel);
460 usb_put_phy(musb->xceiv);
461
462 return 0;
463}
464
465static const struct musb_platform_ops bfin_ops = {
466 .quirks = MUSB_DMA_INVENTRA,
467 .init = bfin_musb_init,
468 .exit = bfin_musb_exit,
469
470 .fifo_offset = bfin_fifo_offset,
471 .readb = bfin_readb,
472 .writeb = bfin_writeb,
473 .readw = bfin_readw,
474 .writew = bfin_writew,
475 .readl = bfin_readl,
476 .writel = bfin_writel,
477 .fifo_mode = 2,
478 .read_fifo = bfin_read_fifo,
479 .write_fifo = bfin_write_fifo,
480#ifdef CONFIG_USB_INVENTRA_DMA
481 .dma_init = musbhs_dma_controller_create,
482 .dma_exit = musbhs_dma_controller_destroy,
483#endif
484 .enable = bfin_musb_enable,
485 .disable = bfin_musb_disable,
486
487 .set_mode = bfin_musb_set_mode,
488
489 .vbus_status = bfin_musb_vbus_status,
490 .set_vbus = bfin_musb_set_vbus,
491
492 .adjust_channel_params = bfin_musb_adjust_channel_params,
493};
494
495static u64 bfin_dmamask = DMA_BIT_MASK(32);
496
497static int bfin_probe(struct platform_device *pdev)
498{
499 struct resource musb_resources[2];
500 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
501 struct platform_device *musb;
502 struct bfin_glue *glue;
503
504 int ret = -ENOMEM;
505
506 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
507 if (!glue)
508 goto err0;
509
510 musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
511 if (!musb)
512 goto err0;
513
514 musb->dev.parent = &pdev->dev;
515 musb->dev.dma_mask = &bfin_dmamask;
516 musb->dev.coherent_dma_mask = bfin_dmamask;
517
518 glue->dev = &pdev->dev;
519 glue->musb = musb;
520
521 pdata->platform_ops = &bfin_ops;
522
523 glue->phy = usb_phy_generic_register();
524 if (IS_ERR(glue->phy))
525 goto err1;
526 platform_set_drvdata(pdev, glue);
527
528 memset(musb_resources, 0x00, sizeof(*musb_resources) *
529 ARRAY_SIZE(musb_resources));
530
531 musb_resources[0].name = pdev->resource[0].name;
532 musb_resources[0].start = pdev->resource[0].start;
533 musb_resources[0].end = pdev->resource[0].end;
534 musb_resources[0].flags = pdev->resource[0].flags;
535
536 musb_resources[1].name = pdev->resource[1].name;
537 musb_resources[1].start = pdev->resource[1].start;
538 musb_resources[1].end = pdev->resource[1].end;
539 musb_resources[1].flags = pdev->resource[1].flags;
540
541 ret = platform_device_add_resources(musb, musb_resources,
542 ARRAY_SIZE(musb_resources));
543 if (ret) {
544 dev_err(&pdev->dev, "failed to add resources\n");
545 goto err2;
546 }
547
548 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
549 if (ret) {
550 dev_err(&pdev->dev, "failed to add platform_data\n");
551 goto err2;
552 }
553
554 ret = platform_device_add(musb);
555 if (ret) {
556 dev_err(&pdev->dev, "failed to register musb device\n");
557 goto err2;
558 }
559
560 return 0;
561
562err2:
563 usb_phy_generic_unregister(glue->phy);
564
565err1:
566 platform_device_put(musb);
567
568err0:
569 return ret;
570}
571
572static int bfin_remove(struct platform_device *pdev)
573{
574 struct bfin_glue *glue = platform_get_drvdata(pdev);
575
576 platform_device_unregister(glue->musb);
577 usb_phy_generic_unregister(glue->phy);
578
579 return 0;
580}
581
582static int __maybe_unused bfin_suspend(struct device *dev)
583{
584 struct bfin_glue *glue = dev_get_drvdata(dev);
585 struct musb *musb = glue_to_musb(glue);
586
587 if (is_host_active(musb))
588 /*
589 * During hibernate gpio_vrsel will change from high to low
590 * low which will generate wakeup event resume the system
591 * immediately. Set it to 0 before hibernate to avoid this
592 * wakeup event.
593 */
594 gpio_set_value(musb->config->gpio_vrsel, 0);
595
596 return 0;
597}
598
599static int __maybe_unused bfin_resume(struct device *dev)
600{
601 struct bfin_glue *glue = dev_get_drvdata(dev);
602 struct musb *musb = glue_to_musb(glue);
603
604 bfin_musb_reg_init(musb);
605
606 return 0;
607}
608
609static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
610
611static struct platform_driver bfin_driver = {
612 .probe = bfin_probe,
613 .remove = bfin_remove,
614 .driver = {
615 .name = "musb-blackfin",
616 .pm = &bfin_pm_ops,
617 },
618};
619
620MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
621MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
622MODULE_LICENSE("GPL v2");
623module_platform_driver(bfin_driver);
diff --git a/drivers/usb/musb/blackfin.h b/drivers/usb/musb/blackfin.h
deleted file mode 100644
index 5b149915b0f8..000000000000
--- a/drivers/usb/musb/blackfin.h
+++ /dev/null
@@ -1,81 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2007 by Analog Devices, Inc.
4 */
5
6#ifndef __MUSB_BLACKFIN_H__
7#define __MUSB_BLACKFIN_H__
8
9/*
10 * Blackfin specific definitions
11 */
12
13/* Anomalies notes:
14 *
15 * 05000450 - USB DMA Mode 1 Short Packet Data Corruption:
16 * MUSB driver is designed to transfer buffer of N * maxpacket size
17 * in DMA mode 1 and leave the rest of the data to the next
18 * transfer in DMA mode 0, so we never transmit a short packet in
19 * DMA mode 1.
20 *
21 * 05000463 - This anomaly doesn't affect this driver since it
22 * never uses L1 or L2 memory as data destination.
23 *
24 * 05000464 - This anomaly doesn't affect this driver since it
25 * never uses L1 or L2 memory as data source.
26 *
27 * 05000465 - The anomaly can be seen when SCLK is over 100 MHz, and there is
28 * no way to workaround for bulk endpoints. Since the wMaxPackSize
29 * of bulk is less than or equal to 512, while the fifo size of
30 * endpoint 5, 6, 7 is 1024, the double buffer mode is enabled
31 * automatically when these endpoints are used for bulk OUT.
32 *
33 * 05000466 - This anomaly doesn't affect this driver since it never mixes
34 * concurrent DMA and core accesses to the TX endpoint FIFOs.
35 *
36 * 05000467 - The workaround for this anomaly will introduce another
37 * anomaly - 05000465.
38 */
39
40/* The Mentor USB DMA engine on BF52x (silicon v0.0 and v0.1) seems to be
41 * unstable in host mode. This may be caused by Anomaly 05000380. After
42 * digging out the root cause, we will change this number accordingly.
43 * So, need to either use silicon v0.2+ or disable DMA mode in MUSB.
44 */
45#if ANOMALY_05000380 && defined(CONFIG_BF52x) && \
46 !defined(CONFIG_MUSB_PIO_ONLY)
47# error "Please use PIO mode in MUSB driver on bf52x chip v0.0 and v0.1"
48#endif
49
50#undef DUMP_FIFO_DATA
51#ifdef DUMP_FIFO_DATA
52static void dump_fifo_data(u8 *buf, u16 len)
53{
54 u8 *tmp = buf;
55 int i;
56
57 for (i = 0; i < len; i++) {
58 if (!(i % 16) && i)
59 pr_debug("\n");
60 pr_debug("%02x ", *tmp++);
61 }
62 pr_debug("\n");
63}
64#else
65#define dump_fifo_data(buf, len) do {} while (0)
66#endif
67
68
69#define USB_DMA_BASE USB_DMA_INTERRUPT
70#define USB_DMAx_CTRL 0x04
71#define USB_DMAx_ADDR_LOW 0x08
72#define USB_DMAx_ADDR_HIGH 0x0C
73#define USB_DMAx_COUNT_LOW 0x10
74#define USB_DMAx_COUNT_HIGH 0x14
75
76#define USB_DMA_REG(ep, reg) (USB_DMA_BASE + 0x20 * ep + reg)
77
78/* Almost 1 second */
79#define TIMER_DELAY (1 * HZ)
80
81#endif /* __MUSB_BLACKFIN_H__ */
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index eef4ad578b31..13486588e561 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -126,7 +126,6 @@ EXPORT_SYMBOL_GPL(musb_get_mode);
126 126
127/*-------------------------------------------------------------------------*/ 127/*-------------------------------------------------------------------------*/
128 128
129#ifndef CONFIG_BLACKFIN
130static int musb_ulpi_read(struct usb_phy *phy, u32 reg) 129static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
131{ 130{
132 void __iomem *addr = phy->io_priv; 131 void __iomem *addr = phy->io_priv;
@@ -208,10 +207,6 @@ out:
208 207
209 return ret; 208 return ret;
210} 209}
211#else
212#define musb_ulpi_read NULL
213#define musb_ulpi_write NULL
214#endif
215 210
216static struct usb_phy_io_ops musb_ulpi_access = { 211static struct usb_phy_io_ops musb_ulpi_access = {
217 .read = musb_ulpi_read, 212 .read = musb_ulpi_read,
@@ -2171,7 +2166,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2171 * - initializes musb->xceiv, usually by otg_get_phy() 2166 * - initializes musb->xceiv, usually by otg_get_phy()
2172 * - stops powering VBUS 2167 * - stops powering VBUS
2173 * 2168 *
2174 * There are various transceiver configurations. Blackfin, 2169 * There are various transceiver configurations.
2175 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 2170 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2176 * external/discrete ones in various flavors (twl4030 family, 2171 * external/discrete ones in various flavors (twl4030 family,
2177 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 2172 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 385841ee6f46..8a74cb2907f8 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -414,19 +414,6 @@ struct musb {
414 struct usb_gadget_driver *gadget_driver; /* its driver */ 414 struct usb_gadget_driver *gadget_driver; /* its driver */
415 struct usb_hcd *hcd; /* the usb hcd */ 415 struct usb_hcd *hcd; /* the usb hcd */
416 416
417 /*
418 * FIXME: Remove this flag.
419 *
420 * This is only added to allow Blackfin to work
421 * with current driver. For some unknown reason
422 * Blackfin doesn't work with double buffering
423 * and that's enabled by default.
424 *
425 * We added this flag to forcefully disable double
426 * buffering until we get it working.
427 */
428 unsigned double_buffer_not_ok:1;
429
430 const struct musb_hdrc_config *config; 417 const struct musb_hdrc_config *config;
431 418
432 int xceiv_old_state; 419 int xceiv_old_state;
@@ -467,34 +454,6 @@ static inline char *musb_ep_xfertype_string(u8 type)
467 return s; 454 return s;
468} 455}
469 456
470#ifdef CONFIG_BLACKFIN
471static inline int musb_read_fifosize(struct musb *musb,
472 struct musb_hw_ep *hw_ep, u8 epnum)
473{
474 musb->nr_endpoints++;
475 musb->epmask |= (1 << epnum);
476
477 if (epnum < 5) {
478 hw_ep->max_packet_sz_tx = 128;
479 hw_ep->max_packet_sz_rx = 128;
480 } else {
481 hw_ep->max_packet_sz_tx = 1024;
482 hw_ep->max_packet_sz_rx = 1024;
483 }
484 hw_ep->is_shared_fifo = false;
485
486 return 0;
487}
488
489static inline void musb_configure_ep0(struct musb *musb)
490{
491 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
492 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
493 musb->endpoints[0].is_shared_fifo = true;
494}
495
496#else
497
498static inline int musb_read_fifosize(struct musb *musb, 457static inline int musb_read_fifosize(struct musb *musb,
499 struct musb_hw_ep *hw_ep, u8 epnum) 458 struct musb_hw_ep *hw_ep, u8 epnum)
500{ 459{
@@ -531,8 +490,6 @@ static inline void musb_configure_ep0(struct musb *musb)
531 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE; 490 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
532 musb->endpoints[0].is_shared_fifo = true; 491 musb->endpoints[0].is_shared_fifo = true;
533} 492}
534#endif /* CONFIG_BLACKFIN */
535
536 493
537/***************************** Glue it together *****************************/ 494/***************************** Glue it together *****************************/
538 495
diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c
index 7cf5a1bbdaff..7dac456f7ebc 100644
--- a/drivers/usb/musb/musb_debugfs.c
+++ b/drivers/usb/musb/musb_debugfs.c
@@ -70,7 +70,6 @@ static const struct musb_register_map musb_regmap[] = {
70 { "DMA_CNTLch7", 0x274, 16 }, 70 { "DMA_CNTLch7", 0x274, 16 },
71 { "DMA_ADDRch7", 0x278, 32 }, 71 { "DMA_ADDRch7", 0x278, 32 },
72 { "DMA_COUNTch7", 0x27C, 32 }, 72 { "DMA_COUNTch7", 0x27C, 32 },
73#ifndef CONFIG_BLACKFIN
74 { "ConfigData", MUSB_CONFIGDATA,8 }, 73 { "ConfigData", MUSB_CONFIGDATA,8 },
75 { "BabbleCtl", MUSB_BABBLE_CTL,8 }, 74 { "BabbleCtl", MUSB_BABBLE_CTL,8 },
76 { "TxFIFOsz", MUSB_TXFIFOSZ, 8 }, 75 { "TxFIFOsz", MUSB_TXFIFOSZ, 8 },
@@ -79,7 +78,6 @@ static const struct musb_register_map musb_regmap[] = {
79 { "RxFIFOadd", MUSB_RXFIFOADD, 16 }, 78 { "RxFIFOadd", MUSB_RXFIFOADD, 16 },
80 { "EPInfo", MUSB_EPINFO, 8 }, 79 { "EPInfo", MUSB_EPINFO, 8 },
81 { "RAMInfo", MUSB_RAMINFO, 8 }, 80 { "RAMInfo", MUSB_RAMINFO, 8 },
82#endif
83 { } /* Terminating Entry */ 81 { } /* Terminating Entry */
84}; 82};
85 83
diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h
index a4241f4d430e..0fc8cd0c2a5c 100644
--- a/drivers/usb/musb/musb_dma.h
+++ b/drivers/usb/musb/musb_dma.h
@@ -80,17 +80,6 @@ struct musb_hw_ep;
80#define is_cppi_enabled(musb) 0 80#define is_cppi_enabled(musb) 0
81#endif 81#endif
82 82
83/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
84 * Only allow DMA mode 1 to be used when the USB will actually generate the
85 * interrupts we expect.
86 */
87#ifdef CONFIG_BLACKFIN
88# undef USE_MODE1
89# if !ANOMALY_05000456
90# define USE_MODE1
91# endif
92#endif
93
94/* 83/*
95 * DMA channel status ... updated by the dma controller driver whenever that 84 * DMA channel status ... updated by the dma controller driver whenever that
96 * status changes, and protected by the overall controller spinlock. 85 * status changes, and protected by the overall controller spinlock.
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 293e5b8da565..e564695c6c8d 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -995,15 +995,11 @@ static int musb_gadget_enable(struct usb_ep *ep,
995 /* Set TXMAXP with the FIFO size of the endpoint 995 /* Set TXMAXP with the FIFO size of the endpoint
996 * to disable double buffering mode. 996 * to disable double buffering mode.
997 */ 997 */
998 if (musb->double_buffer_not_ok) { 998 if (can_bulk_split(musb, musb_ep->type))
999 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); 999 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
1000 } else { 1000 musb_ep->packet_sz) - 1;
1001 if (can_bulk_split(musb, musb_ep->type)) 1001 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1002 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx / 1002 | (musb_ep->hb_mult << 11));
1003 musb_ep->packet_sz) - 1;
1004 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1005 | (musb_ep->hb_mult << 11));
1006 }
1007 1003
1008 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; 1004 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1009 if (musb_readw(regs, MUSB_TXCSR) 1005 if (musb_readw(regs, MUSB_TXCSR)
@@ -1038,11 +1034,8 @@ static int musb_gadget_enable(struct usb_ep *ep,
1038 /* Set RXMAXP with the FIFO size of the endpoint 1034 /* Set RXMAXP with the FIFO size of the endpoint
1039 * to disable double buffering mode. 1035 * to disable double buffering mode.
1040 */ 1036 */
1041 if (musb->double_buffer_not_ok) 1037 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1042 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); 1038 | (musb_ep->hb_mult << 11));
1043 else
1044 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1045 | (musb_ep->hb_mult << 11));
1046 1039
1047 /* force shared fifo to OUT-only mode */ 1040 /* force shared fifo to OUT-only mode */
1048 if (hw_ep->is_shared_fifo) { 1041 if (hw_ep->is_shared_fifo) {
@@ -1680,40 +1673,6 @@ static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1680 return 0; 1673 return 0;
1681} 1674}
1682 1675
1683#ifdef CONFIG_BLACKFIN
1684static struct usb_ep *musb_match_ep(struct usb_gadget *g,
1685 struct usb_endpoint_descriptor *desc,
1686 struct usb_ss_ep_comp_descriptor *ep_comp)
1687{
1688 struct usb_ep *ep = NULL;
1689
1690 switch (usb_endpoint_type(desc)) {
1691 case USB_ENDPOINT_XFER_ISOC:
1692 case USB_ENDPOINT_XFER_BULK:
1693 if (usb_endpoint_dir_in(desc))
1694 ep = gadget_find_ep_by_name(g, "ep5in");
1695 else
1696 ep = gadget_find_ep_by_name(g, "ep6out");
1697 break;
1698 case USB_ENDPOINT_XFER_INT:
1699 if (usb_endpoint_dir_in(desc))
1700 ep = gadget_find_ep_by_name(g, "ep1in");
1701 else
1702 ep = gadget_find_ep_by_name(g, "ep2out");
1703 break;
1704 default:
1705 break;
1706 }
1707
1708 if (ep && usb_gadget_ep_match_desc(g, ep, desc, ep_comp))
1709 return ep;
1710
1711 return NULL;
1712}
1713#else
1714#define musb_match_ep NULL
1715#endif
1716
1717static int musb_gadget_start(struct usb_gadget *g, 1676static int musb_gadget_start(struct usb_gadget *g,
1718 struct usb_gadget_driver *driver); 1677 struct usb_gadget_driver *driver);
1719static int musb_gadget_stop(struct usb_gadget *g); 1678static int musb_gadget_stop(struct usb_gadget *g);
@@ -1727,7 +1686,6 @@ static const struct usb_gadget_ops musb_gadget_operations = {
1727 .pullup = musb_gadget_pullup, 1686 .pullup = musb_gadget_pullup,
1728 .udc_start = musb_gadget_start, 1687 .udc_start = musb_gadget_start,
1729 .udc_stop = musb_gadget_stop, 1688 .udc_stop = musb_gadget_stop,
1730 .match_ep = musb_match_ep,
1731}; 1689};
1732 1690
1733/* ----------------------------------------------------------------------- */ 1691/* ----------------------------------------------------------------------- */
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 45ed32c2cba9..3a8451a15f7f 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -574,11 +574,8 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum)
574 /* Set RXMAXP with the FIFO size of the endpoint 574 /* Set RXMAXP with the FIFO size of the endpoint
575 * to disable double buffer mode. 575 * to disable double buffer mode.
576 */ 576 */
577 if (musb->double_buffer_not_ok) 577 musb_writew(ep->regs, MUSB_RXMAXP,
578 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); 578 qh->maxpacket | ((qh->hb_mult - 1) << 11));
579 else
580 musb_writew(ep->regs, MUSB_RXMAXP,
581 qh->maxpacket | ((qh->hb_mult - 1) << 11));
582 579
583 ep->rx_reinit = 0; 580 ep->rx_reinit = 0;
584} 581}
@@ -804,10 +801,7 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
804 /* protocol/endpoint/interval/NAKlimit */ 801 /* protocol/endpoint/interval/NAKlimit */
805 if (epnum) { 802 if (epnum) {
806 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 803 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
807 if (musb->double_buffer_not_ok) { 804 if (can_bulk_split(musb, qh->type)) {
808 musb_writew(epio, MUSB_TXMAXP,
809 hw_ep->max_packet_sz_tx);
810 } else if (can_bulk_split(musb, qh->type)) {
811 qh->hb_mult = hw_ep->max_packet_sz_tx 805 qh->hb_mult = hw_ep->max_packet_sz_tx
812 / packet_sz; 806 / packet_sz;
813 musb_writew(epio, MUSB_TXMAXP, packet_sz 807 musb_writew(epio, MUSB_TXMAXP, packet_sz
diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
index a4beba184798..88466622c89f 100644
--- a/drivers/usb/musb/musb_regs.h
+++ b/drivers/usb/musb/musb_regs.h
@@ -195,8 +195,6 @@
195#define MUSB_HUBADDR_MULTI_TT 0x80 195#define MUSB_HUBADDR_MULTI_TT 0x80
196 196
197 197
198#ifndef CONFIG_BLACKFIN
199
200/* 198/*
201 * Common USB registers 199 * Common USB registers
202 */ 200 */
@@ -416,184 +414,4 @@ static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum)
416 musb->io.busctl_offset(epnum, MUSB_TXHUBPORT)); 414 musb->io.busctl_offset(epnum, MUSB_TXHUBPORT));
417} 415}
418 416
419#else /* CONFIG_BLACKFIN */
420
421#define USB_BASE USB_FADDR
422#define USB_OFFSET(reg) (reg - USB_BASE)
423
424/*
425 * Common USB registers
426 */
427#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
428#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
429#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
430#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
431#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
432#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
433#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
434#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
435#define MUSB_FRAME USB_OFFSET(USB_FRAME)
436#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
437#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
438
439/*
440 * Additional Control Registers
441 */
442
443#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
444
445#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
446#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
447#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
448#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
449#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
450
451/* Offsets to endpoint registers */
452#define MUSB_TXMAXP 0x00
453#define MUSB_TXCSR 0x04
454#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
455#define MUSB_RXMAXP 0x08
456#define MUSB_RXCSR 0x0C
457#define MUSB_RXCOUNT 0x10
458#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
459#define MUSB_TXTYPE 0x14
460#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
461#define MUSB_TXINTERVAL 0x18
462#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
463#define MUSB_RXTYPE 0x1C
464#define MUSB_RXINTERVAL 0x20
465#define MUSB_TXCOUNT 0x28
466
467/* Offsets to endpoint registers in indexed model (using INDEX register) */
468#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
469 (0x40 + (_offset))
470
471/* Offsets to endpoint registers in flat models */
472#define MUSB_FLAT_OFFSET(_epnum, _offset) \
473 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
474
475/* Not implemented - HW has separate Tx/Rx FIFO */
476#define MUSB_TXCSR_MODE 0x0000
477
478static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
479{
480}
481
482static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
483{
484}
485
486static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
487{
488}
489
490static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
491{
492}
493
494static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
495{
496}
497
498static inline u8 musb_read_txfifosz(void __iomem *mbase)
499{
500 return 0;
501}
502
503static inline u16 musb_read_txfifoadd(void __iomem *mbase)
504{
505 return 0;
506}
507
508static inline u8 musb_read_rxfifosz(void __iomem *mbase)
509{
510 return 0;
511}
512
513static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
514{
515 return 0;
516}
517
518static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
519{
520 return 0;
521}
522
523static inline u8 musb_read_configdata(void __iomem *mbase)
524{
525 return 0;
526}
527
528static inline u16 musb_read_hwvers(void __iomem *mbase)
529{
530 /*
531 * This register is invisible on Blackfin, actually the MUSB
532 * RTL version of Blackfin is 1.9, so just hardcode its value.
533 */
534 return MUSB_HWVERS_1900;
535}
536
537static inline void musb_write_rxfunaddr(void __iomem *mbase, u8 epnum,
538 u8 qh_addr_req)
539{
540}
541
542static inline void musb_write_rxhubaddr(void __iomem *mbase, u8 epnum,
543 u8 qh_h_addr_reg)
544{
545}
546
547static inline void musb_write_rxhubport(void __iomem *mbase, u8 epnum,
548 u8 qh_h_port_reg)
549{
550}
551
552static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
553 u8 qh_addr_reg)
554{
555}
556
557static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
558 u8 qh_addr_reg)
559{
560}
561
562static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
563 u8 qh_h_port_reg)
564{
565}
566
567static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
568{
569 return 0;
570}
571
572static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
573{
574 return 0;
575}
576
577static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
578{
579 return 0;
580}
581
582static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
583{
584 return 0;
585}
586
587static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
588{
589 return 0;
590}
591
592static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
593{
594 return 0;
595}
596
597#endif /* CONFIG_BLACKFIN */
598
599#endif /* __MUSB_REGS_H__ */ 417#endif /* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 21fb9e6622f3..4389fc3422bd 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -235,11 +235,6 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
235 235
236 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 236 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
237 237
238#ifdef CONFIG_BLACKFIN
239 /* Clear DMA interrupt flags */
240 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
241#endif
242
243 if (!int_hsdma) { 238 if (!int_hsdma) {
244 musb_dbg(musb, "spurious DMA irq"); 239 musb_dbg(musb, "spurious DMA irq");
245 240
diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
index 44f7983df0a1..93665135aff1 100644
--- a/drivers/usb/musb/musbhsdma.h
+++ b/drivers/usb/musb/musbhsdma.h
@@ -6,8 +6,6 @@
6 * Copyright (C) 2005-2007 by Texas Instruments 6 * Copyright (C) 2005-2007 by Texas Instruments
7 */ 7 */
8 8
9#ifndef CONFIG_BLACKFIN
10
11#define MUSB_HSDMA_BASE 0x200 9#define MUSB_HSDMA_BASE 0x200
12#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0) 10#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
13#define MUSB_HSDMA_CONTROL 0x4 11#define MUSB_HSDMA_CONTROL 0x4
@@ -34,68 +32,6 @@
34 musb_writel(mbase, \ 32 musb_writel(mbase, \
35 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \ 33 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
36 len) 34 len)
37#else
38
39#define MUSB_HSDMA_BASE 0x400
40#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
41#define MUSB_HSDMA_CONTROL 0x04
42#define MUSB_HSDMA_ADDR_LOW 0x08
43#define MUSB_HSDMA_ADDR_HIGH 0x0C
44#define MUSB_HSDMA_COUNT_LOW 0x10
45#define MUSB_HSDMA_COUNT_HIGH 0x14
46
47#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
48 (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
49
50static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
51{
52 u32 addr = musb_readw(mbase,
53 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
54
55 addr = addr << 16;
56
57 addr |= musb_readw(mbase,
58 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
59
60 return addr;
61}
62
63static inline void musb_write_hsdma_addr(void __iomem *mbase,
64 u8 bchannel, dma_addr_t dma_addr)
65{
66 musb_writew(mbase,
67 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
68 dma_addr);
69 musb_writew(mbase,
70 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
71 (dma_addr >> 16));
72}
73
74static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
75{
76 u32 count = musb_readw(mbase,
77 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
78
79 count = count << 16;
80
81 count |= musb_readw(mbase,
82 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW));
83
84 return count;
85}
86
87static inline void musb_write_hsdma_count(void __iomem *mbase,
88 u8 bchannel, u32 len)
89{
90 musb_writew(mbase,
91 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),len);
92 musb_writew(mbase,
93 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
94 (len >> 16));
95}
96
97#endif /* CONFIG_BLACKFIN */
98
99/* control register (16-bit): */ 35/* control register (16-bit): */
100#define MUSB_HSDMA_ENABLE_SHIFT 0 36#define MUSB_HSDMA_ENABLE_SHIFT 0
101#define MUSB_HSDMA_TRANSMIT_SHIFT 1 37#define MUSB_HSDMA_TRANSMIT_SHIFT 1
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
index 5d19e6730475..9eb908a98033 100644
--- a/include/linux/usb/musb.h
+++ b/include/linux/usb/musb.h
@@ -89,13 +89,6 @@ struct musb_hdrc_config {
89 u8 ram_bits; /* ram address size */ 89 u8 ram_bits; /* ram address size */
90 90
91 struct musb_hdrc_eps_bits *eps_bits __deprecated; 91 struct musb_hdrc_eps_bits *eps_bits __deprecated;
92#ifdef CONFIG_BLACKFIN
93 /* A GPIO controlling VRSEL in Blackfin */
94 unsigned int gpio_vrsel;
95 unsigned int gpio_vrsel_active;
96 /* musb CLKIN in Blackfin in MHZ */
97 unsigned char clkin;
98#endif
99 u32 maximum_speed; 92 u32 maximum_speed;
100}; 93};
101 94
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 07:19:02 -0400