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authorAlexey Brodkin <Alexey.Brodkin@synopsys.com>2017-08-10 11:07:36 -0400
committerVineet Gupta <vgupta@synopsys.com>2017-08-10 21:08:31 -0400
commita8ec3ee861b6e4e6b82a98777c65510ae63766c1 (patch)
tree35238c6dcb677d77d8aac0d22e8ee892b7c243c0
parentb5ddb6d54729d814356937572d6c9b599f10c29f (diff)
arc: Mask individual IRQ lines during core INTC init
ARC cores on reset have all interrupt lines of built-in INTC enabled. Which means once we globally enable interrupts (very early on boot) faulty hardware blocks may trigger an interrupt that Linux kernel cannot handle yet as corresponding handler is not yet installed. In that case system falls in "interrupt storm" and basically never does anything useful except entering and exiting generic IRQ handling code. One real example of that kind of problematic hardware is DW GMAC which also has interrupts enabled on reset and if Ethernet PHY informs GMAC about link state, GMAC immediately reports that upstream to ARC core and here we are. Now with that change we mask all individual IRQ lines making entire system more fool-proof. [This patch was motivated by Adaptrum platform support] Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Eugeniy Paltsev <paltsev@synopsys.com> Tested-by: Alexandru Gagniuc <alex.g@adaptrum.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-rw-r--r--arch/arc/kernel/intc-arcv2.c3
-rw-r--r--arch/arc/kernel/intc-compact.c14
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index f928795fd07a..cf90714a676d 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -75,10 +75,13 @@ void arc_init_IRQ(void)
75 * Set a default priority for all available interrupts to prevent 75 * Set a default priority for all available interrupts to prevent
76 * switching of register banks if Fast IRQ and multiple register banks 76 * switching of register banks if Fast IRQ and multiple register banks
77 * are supported by CPU. 77 * are supported by CPU.
78 * Also disable all IRQ lines so faulty external hardware won't
79 * trigger interrupt that kernel is not ready to handle.
78 */ 80 */
79 for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { 81 for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
80 write_aux_reg(AUX_IRQ_SELECT, i); 82 write_aux_reg(AUX_IRQ_SELECT, i);
81 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); 83 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
84 write_aux_reg(AUX_IRQ_ENABLE, 0);
82 } 85 }
83 86
84 /* setup status32, don't enable intr yet as kernel doesn't want */ 87 /* setup status32, don't enable intr yet as kernel doesn't want */
diff --git a/arch/arc/kernel/intc-compact.c b/arch/arc/kernel/intc-compact.c
index 7e608c6b0a01..cef388025adf 100644
--- a/arch/arc/kernel/intc-compact.c
+++ b/arch/arc/kernel/intc-compact.c
@@ -27,7 +27,7 @@
27 */ 27 */
28void arc_init_IRQ(void) 28void arc_init_IRQ(void)
29{ 29{
30 int level_mask = 0; 30 int level_mask = 0, i;
31 31
32 /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */ 32 /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
33 level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ; 33 level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
@@ -40,6 +40,18 @@ void arc_init_IRQ(void)
40 40
41 if (level_mask) 41 if (level_mask)
42 pr_info("Level-2 interrupts bitset %x\n", level_mask); 42 pr_info("Level-2 interrupts bitset %x\n", level_mask);
43
44 /*
45 * Disable all IRQ lines so faulty external hardware won't
46 * trigger interrupt that kernel is not ready to handle.
47 */
48 for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
49 unsigned int ienb;
50
51 ienb = read_aux_reg(AUX_IENABLE);
52 ienb &= ~(1 << i);
53 write_aux_reg(AUX_IENABLE, ienb);
54 }
43} 55}
44 56
45/* 57/*