aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSifan Naeem <sifan.naeem@imgtec.com>2015-11-19 04:35:14 -0500
committerWolfram Sang <wsa@the-dreams.de>2016-01-02 16:04:05 -0500
commita8c5a8d8c9caa150f0e1faab3884ba48d9cd99fe (patch)
tree0502ad5cced7b3b50e615a2073519fb3db5630b4
parentc55ebe0e72737dd3d49f6fa3156313e1cab5dcab (diff)
i2c: img-scb: remove fifo EMPTYING interrupts handle
Now that we are using the transaction halt interrupt to safely control repeated start transfers, we no longer need to handle the fifo emptying interrupts. Handling this interrupt along with Transaction Halt interrupt can cause erratic behaviour. Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
-rw-r--r--drivers/i2c/busses/i2c-img-scb.c16
1 files changed, 3 insertions, 13 deletions
diff --git a/drivers/i2c/busses/i2c-img-scb.c b/drivers/i2c/busses/i2c-img-scb.c
index c92bcf7c204f..0af554a16ae5 100644
--- a/drivers/i2c/busses/i2c-img-scb.c
+++ b/drivers/i2c/busses/i2c-img-scb.c
@@ -154,7 +154,6 @@
154#define INT_TIMING BIT(18) 154#define INT_TIMING BIT(18)
155 155
156#define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING) 156#define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING)
157#define INT_FIFO_EMPTY_EMPTYING (INT_FIFO_EMPTY | INT_FIFO_EMPTYING)
158 157
159/* Level interrupts need clearing after handling instead of before */ 158/* Level interrupts need clearing after handling instead of before */
160#define INT_LEVEL 0x01e00 159#define INT_LEVEL 0x01e00
@@ -176,8 +175,7 @@
176 INT_WRITE_ACK_ERR | \ 175 INT_WRITE_ACK_ERR | \
177 INT_FIFO_FULL | \ 176 INT_FIFO_FULL | \
178 INT_FIFO_FILLING | \ 177 INT_FIFO_FILLING | \
179 INT_FIFO_EMPTY | \ 178 INT_FIFO_EMPTY)
180 INT_FIFO_EMPTYING)
181 179
182#define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ 180#define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \
183 INT_ADDR_ACK_ERR | \ 181 INT_ADDR_ACK_ERR | \
@@ -874,16 +872,8 @@ static unsigned int img_i2c_auto(struct img_i2c *i2c,
874 return ISR_WAITSTOP; 872 return ISR_WAITSTOP;
875 } 873 }
876 } else { 874 } else {
877 if (int_status & INT_FIFO_EMPTY_EMPTYING) { 875 if (int_status & INT_FIFO_EMPTY) {
878 /* 876 if (i2c->msg.len == 0)
879 * The write fifo empty indicates that we're in the
880 * last byte so it's safe to start a new write
881 * transaction without losing any bytes from the
882 * previous one.
883 * see 2.3.7 Repeated Start Transactions.
884 */
885 if ((int_status & INT_FIFO_EMPTY) &&
886 i2c->msg.len == 0)
887 return ISR_WAITSTOP; 877 return ISR_WAITSTOP;
888 img_i2c_write_fifo(i2c); 878 img_i2c_write_fifo(i2c);
889 } 879 }